# ! [doc = "Peripheral access API for IWRL6432 microcontrollers (generated using svd2rust v0.33.4 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
# ! [allow (non_camel_case_types)]
# ! [allow (non_snake_case)]
# ! [no_std]
use core :: ops :: Deref ; use core :: marker :: PhantomData ; # [doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS : u8 = 3 ; # [allow (unused_imports)]
use generic :: * ; # [doc = r"Common register and bit access and modify traits"]
pub mod generic { use core :: marker ; # [doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg : Copy + Default + From < bool > + core :: ops :: BitOr < Output = Self > + core :: ops :: BitAnd < Output = Self > + core :: ops :: BitOrAssign + core :: ops :: BitAndAssign + core :: ops :: Not < Output = Self > + core :: ops :: Shl < u8 , Output = Self > { # [doc = " Mask for bits of width `WI`"]
fn mask < const WI : u8 > () -> Self ; # [doc = " Mask for bits of width 1"]
fn one () -> Self ; } macro_rules ! raw_reg { ($ U : ty , $ size : literal , $ mask : ident) => { impl RawReg for $ U { # [inline (always)]
fn mask < const WI : u8 > () -> Self { $ mask ::< WI > () } # [inline (always)]
fn one () -> Self { 1 } } const fn $ mask < const WI : u8 > () -> $ U { <$ U >:: MAX >> ($ size - WI) } impl FieldSpec for $ U { type Ux = $ U ; } } ; } raw_reg ! (u8 , 8 , mask_u8) ; raw_reg ! (u16 , 16 , mask_u16) ; raw_reg ! (u32 , 32 , mask_u32) ; raw_reg ! (u64 , 64 , mask_u64) ; # [doc = " Raw register type"]
pub trait RegisterSpec { # [doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux : RawReg ; } # [doc = " Raw field type"]
pub trait FieldSpec : Sized { # [doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux : Copy + core :: fmt :: Debug + PartialEq + From < Self > ; } # [doc = " Marker for fields with fixed values"]
pub trait IsEnum : FieldSpec { } # [doc = " Trait implemented by readable registers to enable the `read` method."]
# [doc = ""]
# [doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable : RegisterSpec { } # [doc = " Trait implemented by writeable registers."]
# [doc = ""]
# [doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
# [doc = ""]
# [doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable : RegisterSpec { # [doc = " Is it safe to write any bits to register"]
type Safety ; # [doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux ; # [doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux ; } # [doc = " Reset value of the register."]
# [doc = ""]
# [doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
# [doc = " register by using the `reset` method."]
pub trait Resettable : RegisterSpec { # [doc = " Reset value of the register."]
const RESET_VALUE : Self :: Ux ; # [doc = " Reset value of the register."]
# [inline (always)]
fn reset_value () -> Self :: Ux { Self :: RESET_VALUE } } # [doc (hidden)]
pub mod raw { use super :: { marker , BitM , FieldSpec , RegisterSpec , Unsafe , Writable } ; pub struct R < REG : RegisterSpec > { pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct W < REG : RegisterSpec > { # [doc = "Writable bits"]
pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct FieldReader < FI = u8 > where FI : FieldSpec , { pub (crate) bits : FI :: Ux , _reg : marker :: PhantomData < FI > , } impl < FI : FieldSpec > FieldReader < FI > { # [doc = " Creates a new instance of the reader."]
# [allow (unused)]
# [inline (always)]
pub (crate) const fn new (bits : FI :: Ux) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct BitReader < FI = bool > { pub (crate) bits : bool , _reg : marker :: PhantomData < FI > , } impl < FI > BitReader < FI > { # [doc = " Creates a new instance of the reader."]
# [allow (unused)]
# [inline (always)]
pub (crate) const fn new (bits : bool) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > where REG : Writable + RegisterSpec , FI : FieldSpec , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , Safety) > , } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , { # [doc = " Creates a new instance of the writer"]
# [allow (unused)]
# [inline (always)]
pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } pub struct BitWriter < 'a , REG , FI = bool , M = BitM > where REG : Writable + RegisterSpec , bool : From < FI > , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , M) > , } impl < 'a , REG , FI , M > BitWriter < 'a , REG , FI , M > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Creates a new instance of the writer"]
# [allow (unused)]
# [inline (always)]
pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } } # [doc = " Register reader."]
# [doc = ""]
# [doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
# [doc = " method."]
pub type R < REG > = raw :: R < REG > ; impl < REG : RegisterSpec > R < REG > { # [doc = " Reads raw bits from register."]
# [inline (always)]
pub const fn bits (& self) -> REG :: Ux { self . bits } } impl < REG : RegisterSpec , FI > PartialEq < FI > for R < REG > where REG :: Ux : PartialEq , FI : Copy , REG :: Ux : From < FI > , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& REG :: Ux :: from (* other)) } } # [doc = " Register writer."]
# [doc = ""]
# [doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W < REG > = raw :: W < REG > ; impl < REG : Writable > W < REG > { # [doc = " Writes raw bits to the register."]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : REG :: Ux) -> & mut Self { self . bits = bits ; self } } impl < REG > W < REG > where REG : Writable < Safety = Safe > { # [doc = " Writes raw bits to the register."]
# [inline (always)]
pub fn set (& mut self , bits : REG :: Ux) -> & mut Self { self . bits = bits ; self } } # [doc = " Field reader."]
# [doc = ""]
# [doc = " Result of the `read` methods of fields."]
pub type FieldReader < FI = u8 > = raw :: FieldReader < FI > ; # [doc = " Bit-wise field reader"]
pub type BitReader < FI = bool > = raw :: BitReader < FI > ; impl < FI : FieldSpec > FieldReader < FI > { # [doc = " Reads raw bits from field."]
# [inline (always)]
pub const fn bits (& self) -> FI :: Ux { self . bits } } impl < FI : FieldSpec > core :: fmt :: Debug for FieldReader < FI > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . bits , f) } } impl < FI > PartialEq < FI > for FieldReader < FI > where FI : FieldSpec + Copy , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& FI :: Ux :: from (* other)) } } impl < FI > PartialEq < FI > for BitReader < FI > where FI : Copy , bool : From < FI > , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& bool :: from (* other)) } } impl < FI > BitReader < FI > { # [doc = " Value of the field as raw bits."]
# [inline (always)]
pub const fn bit (& self) -> bool { self . bits } # [doc = " Returns `true` if the bit is clear (0)."]
# [inline (always)]
pub const fn bit_is_clear (& self) -> bool { ! self . bit () } # [doc = " Returns `true` if the bit is set (1)."]
# [inline (always)]
pub const fn bit_is_set (& self) -> bool { self . bit () } } impl < FI > core :: fmt :: Debug for BitReader < FI > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . bits , f) } } # [doc = " Marker for register/field writers which can take any value of specified width"]
pub struct Safe ; # [doc = " You should check that value is allowed to pass to register/field writer marked with this"]
pub struct Unsafe ; # [doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct Range < const MIN : u64 , const MAX : u64 > ; # [doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeFrom < const MIN : u64 > ; # [doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeTo < const MAX : u64 > ; # [doc = " Write field Proxy"]
pub type FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > = raw :: FieldWriter < 'a , REG , WI , FI , Safety > ; impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , { # [doc = " Field width"]
pub const WIDTH : u8 = WI ; # [doc = " Field width"]
# [inline (always)]
pub const fn width (& self) -> u8 { WI } # [doc = " Field offset"]
# [inline (always)]
pub const fn offset (& self) -> u8 { self . o } } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { # [doc = " Writes raw bits to the field"]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << self . o ; self . w } } impl < 'a , REG , const WI : u8 , FI > FieldWriter < 'a , REG , WI , FI , Safe > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { # [doc = " Writes raw bits to the field"]
# [inline (always)]
pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MIN : u64 , const MAX : u64 > FieldWriter < 'a , REG , WI , FI , Range < MIN , MAX > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , { # [doc = " Writes raw bits to the field"]
# [inline (always)]
pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value >= MIN && value <= MAX) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MIN : u64 > FieldWriter < 'a , REG , WI , FI , RangeFrom < MIN > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , { # [doc = " Writes raw bits to the field"]
# [inline (always)]
pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value >= MIN) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MAX : u64 > FieldWriter < 'a , REG , WI , FI , RangeTo < MAX > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , { # [doc = " Writes raw bits to the field"]
# [inline (always)]
pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value <= MAX) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : IsEnum , REG :: Ux : From < FI :: Ux > , { # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> & 'a mut W < REG > { unsafe { self . bits (FI :: Ux :: from (variant)) } } } macro_rules ! bit_proxy { ($ writer : ident , $ mwv : ident) => { # [doc (hidden)]
pub struct $ mwv ; # [doc = " Bit-wise write field proxy"]
pub type $ writer <'a , REG , FI = bool > = raw :: BitWriter <'a , REG , FI , $ mwv >; impl <'a , REG , FI > $ writer <'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI >, { # [doc = " Field width"]
pub const WIDTH : u8 = 1 ; # [doc = " Field width"]
# [inline (always)]
pub const fn width (& self) -> u8 { Self :: WIDTH } # [doc = " Field offset"]
# [inline (always)]
pub const fn offset (& self) -> u8 { self . o } # [doc = " Writes bit to the field"]
# [inline (always)]
pub fn bit (self , value : bool) -> &'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: one ()) << self . o ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> &'a mut W < REG > { self . bit (bool :: from (variant)) } } } ; } bit_proxy ! (BitWriter , BitM) ; bit_proxy ! (BitWriter1S , Bit1S) ; bit_proxy ! (BitWriter0C , Bit0C) ; bit_proxy ! (BitWriter1C , Bit1C) ; bit_proxy ! (BitWriter0S , Bit0S) ; bit_proxy ! (BitWriter1T , Bit1T) ; bit_proxy ! (BitWriter0T , Bit0T) ; impl < 'a , REG , FI > BitWriter < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Sets the field bit"]
# [inline (always)]
pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } # [doc = " Clears the field bit"]
# [inline (always)]
pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Sets the field bit"]
# [inline (always)]
pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Clears the field bit"]
# [inline (always)]
pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Clears the field bit by passing one"]
# [inline (always)]
pub fn clear_bit_by_one (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Sets the field bit by passing zero"]
# [inline (always)]
pub fn set_bit_by_zero (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Toggle the field bit by passing one"]
# [inline (always)]
pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Toggle the field bit by passing zero"]
# [inline (always)]
pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } # [doc = " This structure provides volatile access to registers."]
# [repr (transparent)]
pub struct Reg < REG : RegisterSpec > { register : vcell :: VolatileCell < REG :: Ux > , _marker : marker :: PhantomData < REG > , } unsafe impl < REG : RegisterSpec > Send for Reg < REG > where REG :: Ux : Send { } impl < REG : RegisterSpec > Reg < REG > { # [doc = " Returns the underlying memory address of register."]
# [doc = ""]
# [doc = " ```ignore"]
# [doc = " let reg_ptr = periph.reg.as_ptr();"]
# [doc = " ```"]
# [inline (always)]
pub fn as_ptr (& self) -> * mut REG :: Ux { self . register . as_ptr () } } impl < REG : Readable > Reg < REG > { # [doc = " Reads the contents of a `Readable` register."]
# [doc = ""]
# [doc = " You can read the raw contents of a register by using `bits`:"]
# [doc = " ```ignore"]
# [doc = " let bits = periph.reg.read().bits();"]
# [doc = " ```"]
# [doc = " or get the content of a particular field of a register:"]
# [doc = " ```ignore"]
# [doc = " let reader = periph.reg.read();"]
# [doc = " let bits = reader.field1().bits();"]
# [doc = " let flag = reader.field2().bit_is_set();"]
# [doc = " ```"]
# [inline (always)]
pub fn read (& self) -> R < REG > { R { bits : self . register . get () , _reg : marker :: PhantomData , } } } impl < REG : Resettable + Writable > Reg < REG > { # [doc = " Writes the reset value to `Writable` register."]
# [doc = ""]
# [doc = " Resets the register to its initial state."]
# [inline (always)]
pub fn reset (& self) { self . register . set (REG :: RESET_VALUE) } # [doc = " Writes bits to a `Writable` register."]
# [doc = ""]
# [doc = " You can write raw bits into a register:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
# [doc = " ```"]
# [doc = " or write only the fields you need:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| w"]
# [doc = "     .field1().bits(newfield1bits)"]
# [doc = "     .field2().set_bit()"]
# [doc = "     .field3().variant(VARIANT)"]
# [doc = " );"]
# [doc = " ```"]
# [doc = " or an alternative way of saying the same:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| {"]
# [doc = "     w.field1().bits(newfield1bits);"]
# [doc = "     w.field2().set_bit();"]
# [doc = "     w.field3().variant(VARIANT)"]
# [doc = " });"]
# [doc = " ```"]
# [doc = " In the latter case, other fields will be set to their reset value."]
# [inline (always)]
pub fn write < F > (& self , f : F) where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { self . register . set (f (& mut W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , }) . bits ,) ; } } impl < REG : Writable > Reg < REG > { # [doc = " Writes 0 to a `Writable` register."]
# [doc = ""]
# [doc = " Similar to `write`, but unused bits will contain 0."]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Unsafe to use with registers which don't allow to write 0."]
# [inline (always)]
pub unsafe fn write_with_zero < F > (& self , f : F) where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { self . register . set (f (& mut W { bits : REG :: Ux :: default () , _reg : marker :: PhantomData , }) . bits ,) ; } } impl < REG : Readable + Writable > Reg < REG > { # [doc = " Modifies the contents of the register by reading and then writing it."]
# [doc = ""]
# [doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
# [doc = "    r.bits() | 3"]
# [doc = " ) });"]
# [doc = " ```"]
# [doc = " or"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|_, w| w"]
# [doc = "     .field1().bits(newfield1bits)"]
# [doc = "     .field2().set_bit()"]
# [doc = "     .field3().variant(VARIANT)"]
# [doc = " );"]
# [doc = " ```"]
# [doc = " or an alternative way of saying the same:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|_, w| {"]
# [doc = "     w.field1().bits(newfield1bits);"]
# [doc = "     w.field2().set_bit();"]
# [doc = "     w.field3().variant(VARIANT)"]
# [doc = " });"]
# [doc = " ```"]
# [doc = " Other fields will have the value they had before the call to `modify`."]
# [inline (always)]
pub fn modify < F > (& self , f : F) where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> & 'w mut W < REG > , { let bits = self . register . get () ; self . register . set (f (& R { bits , _reg : marker :: PhantomData , } , & mut W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ,) . bits ,) ; } } impl < REG : Readable > core :: fmt :: Debug for crate :: generic :: Reg < REG > where R < REG > : core :: fmt :: Debug { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } } # [cfg (feature = "rt")]
extern "C" { } # [doc (hidden)]
# [repr (C)]
pub union Vector { _handler : unsafe extern "C" fn () , _reserved : u32 , } # [cfg (feature = "rt")]
# [doc (hidden)]
# [link_section = ".vector_table.interrupts"]
# [no_mangle]
pub static __INTERRUPTS : [Vector ; 0]
= []
; # [doc = r"Enumeration of all the interrupts."]
# [derive (Copy , Clone , Debug , PartialEq , Eq)]
pub enum Interrupt { } unsafe impl cortex_m :: interrupt :: InterruptNumber for Interrupt { # [inline (always)]
fn number (self) -> u16 { match self { } } } # [doc = "GPADC_CTRL"]
pub struct GpadcCtrl { _marker : PhantomData < * const () > } unsafe impl Send for GpadcCtrl { } impl GpadcCtrl { # [doc = r"Pointer to the register block"]
pub const PTR : * const gpadc_ctrl :: RegisterBlock = 0x50f7_fc00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const gpadc_ctrl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for GpadcCtrl { type Target = gpadc_ctrl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for GpadcCtrl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GpadcCtrl") . finish () } } # [doc = "GPADC_CTRL"]
pub mod gpadc_ctrl { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { reg0 : Reg0 , reg1 : Reg1 , reg2 : Reg2 , reg3 : Reg3 , reg4 : Reg4 , reg5 : Reg5 , reg6 : Reg6 , reg7 : Reg7 , reg8 : Reg8 , reg9 : Reg9 , reg10 : Reg10 , reg11 : Reg11 , reg12 : Reg12 , reg13 : Reg13 , reg14 : Reg14 , reg15 : Reg15 , reg16 : Reg16 , reg17 : Reg17 , reg18 : Reg18 , reg19 : Reg19 , reg20 : Reg20 , reg21 : Reg21 , reg22 : Reg22 , } impl RegisterBlock { # [doc = "0x00 - gpadc modes and enable"]
# [inline (always)]
pub const fn reg0 (& self) -> & Reg0 { & self . reg0 } # [doc = "0x04 - gpadc start trigger for Inter frame mode"]
# [inline (always)]
pub const fn reg1 (& self) -> & Reg1 { & self . reg1 } # [doc = "0x08 - gpadc config for IFM"]
# [inline (always)]
pub const fn reg2 (& self) -> & Reg2 { & self . reg2 } # [doc = "0x0c - gpadc param, skip samples and collect samples for IFM"]
# [inline (always)]
pub const fn reg3 (& self) -> & Reg3 { & self . reg3 } # [doc = "0x10 - Base address for Chirp profile 0 in instruction packet RAM"]
# [inline (always)]
pub const fn reg4 (& self) -> & Reg4 { & self . reg4 } # [doc = "0x14 - Base address for Chirp profile 1 in instruction packet RAM"]
# [inline (always)]
pub const fn reg5 (& self) -> & Reg5 { & self . reg5 } # [doc = "0x18 - Base address for Chirp profile 2 in instruction packet RAM"]
# [inline (always)]
pub const fn reg6 (& self) -> & Reg6 { & self . reg6 } # [doc = "0x1c - Base address for Chirp profile 3 in instruction packet RAM"]
# [inline (always)]
pub const fn reg7 (& self) -> & Reg7 { & self . reg7 } # [doc = "0x20 - REG8"]
# [inline (always)]
pub const fn reg8 (& self) -> & Reg8 { & self . reg8 } # [doc = "0x24 - REG9"]
# [inline (always)]
pub const fn reg9 (& self) -> & Reg9 { & self . reg9 } # [doc = "0x28 - REG10"]
# [inline (always)]
pub const fn reg10 (& self) -> & Reg10 { & self . reg10 } # [doc = "0x2c - REG11"]
# [inline (always)]
pub const fn reg11 (& self) -> & Reg11 { & self . reg11 } # [doc = "0x30 - REG12"]
# [inline (always)]
pub const fn reg12 (& self) -> & Reg12 { & self . reg12 } # [doc = "0x34 - REG13"]
# [inline (always)]
pub const fn reg13 (& self) -> & Reg13 { & self . reg13 } # [doc = "0x38 - Sum of GP ADC readings"]
# [inline (always)]
pub const fn reg14 (& self) -> & Reg14 { & self . reg14 } # [doc = "0x3c - Min and Max of GP ADC readings"]
# [inline (always)]
pub const fn reg15 (& self) -> & Reg15 { & self . reg15 } # [doc = "0x40 - REG16"]
# [inline (always)]
pub const fn reg16 (& self) -> & Reg16 { & self . reg16 } # [doc = "0x44 - REG17"]
# [inline (always)]
pub const fn reg17 (& self) -> & Reg17 { & self . reg17 } # [doc = "0x48 - REG18"]
# [inline (always)]
pub const fn reg18 (& self) -> & Reg18 { & self . reg18 } # [doc = "0x4c - REG19"]
# [inline (always)]
pub const fn reg19 (& self) -> & Reg19 { & self . reg19 } # [doc = "0x50 - REG20"]
# [inline (always)]
pub const fn reg20 (& self) -> & Reg20 { & self . reg20 } # [doc = "0x54 - REG21"]
# [inline (always)]
pub const fn reg21 (& self) -> & Reg21 { & self . reg21 } # [doc = "0x58 - REG22"]
# [inline (always)]
pub const fn reg22 (& self) -> & Reg22 { & self . reg22 } } # [doc = "REG0 (rw) register accessor: gpadc modes and enable\n\nYou can [`read`](crate::Reg::read) this register and get [`reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg0`]
module"]
# [doc (alias = "REG0")]
pub type Reg0 = crate :: Reg < reg0 :: Reg0Spec > ; # [doc = "gpadc modes and enable"]
pub mod reg0 { # [doc = "Register `REG0` reader"]
pub type R = crate :: R < Reg0Spec > ; # [doc = "Register `REG0` writer"]
pub type W = crate :: W < Reg0Spec > ; # [doc = "Field `DCBIST_MODE` reader - 1:0\\]
0:Disable,1:IFM Mode enable ,2:CTM mode enable"]
pub type DcbistModeR = crate :: FieldReader ; # [doc = "Field `DCBIST_MODE` writer - 1:0\\]
0:Disable,1:IFM Mode enable ,2:CTM mode enable"]
pub type DcbistModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU1` reader - 7:2\\]
TI reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:2\\]
TI reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `GPADC_FSM_CLK_ENABLE` reader - 8:8\\]
Enable the clock to gpadc fsm"]
pub type GpadcFsmClkEnableR = crate :: BitReader ; # [doc = "Field `GPADC_FSM_CLK_ENABLE` writer - 8:8\\]
Enable the clock to gpadc fsm"]
pub type GpadcFsmClkEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `GPADC2ADCBUF_PATH_EN` reader - 11:9\\]
TI reserved"]
pub type Gpadc2adcbufPathEnR = crate :: FieldReader ; # [doc = "Field `GPADC2ADCBUF_PATH_EN` writer - 11:9\\]
TI reserved"]
pub type Gpadc2adcbufPathEnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU2` reader - 15:12\\]
TI reserved"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 15:12\\]
TI reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `GPADC_DEBUG_MODE_ENABLE` reader - 16:16\\]
1:GPADC raw samples will be collected in the Output RAM in IFM mode"]
pub type GpadcDebugModeEnableR = crate :: BitReader ; # [doc = "Field `GPADC_DEBUG_MODE_ENABLE` writer - 16:16\\]
1:GPADC raw samples will be collected in the Output RAM in IFM mode"]
pub type GpadcDebugModeEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU3` reader - 31:17\\]
TI reserved"]
pub type Nu3R = crate :: FieldReader < u16 > ; # [doc = "Field `NU3` writer - 31:17\\]
TI reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
0:Disable,1:IFM Mode enable ,2:CTM mode enable"]
# [inline (always)]
pub fn dcbist_mode (& self) -> DcbistModeR { DcbistModeR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:7 - 7:2\\]
TI reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Enable the clock to gpadc fsm"]
# [inline (always)]
pub fn gpadc_fsm_clk_enable (& self) -> GpadcFsmClkEnableR { GpadcFsmClkEnableR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:11 - 11:9\\]
TI reserved"]
# [inline (always)]
pub fn gpadc2adcbuf_path_en (& self) -> Gpadc2adcbufPathEnR { Gpadc2adcbufPathEnR :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:15 - 15:12\\]
TI reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
1:GPADC raw samples will be collected in the Output RAM in IFM mode"]
# [inline (always)]
pub fn gpadc_debug_mode_enable (& self) -> GpadcDebugModeEnableR { GpadcDebugModeEnableR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31 - 31:17\\]
TI reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
0:Disable,1:IFM Mode enable ,2:CTM mode enable"]
# [inline (always)]
# [must_use]
pub fn dcbist_mode (& mut self) -> DcbistModeW < Reg0Spec > { DcbistModeW :: new (self , 0) } # [doc = "Bits 2:7 - 7:2\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Reg0Spec > { Nu1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Enable the clock to gpadc fsm"]
# [inline (always)]
# [must_use]
pub fn gpadc_fsm_clk_enable (& mut self) -> GpadcFsmClkEnableW < Reg0Spec > { GpadcFsmClkEnableW :: new (self , 8) } # [doc = "Bits 9:11 - 11:9\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn gpadc2adcbuf_path_en (& mut self) -> Gpadc2adcbufPathEnW < Reg0Spec > { Gpadc2adcbufPathEnW :: new (self , 9) } # [doc = "Bits 12:15 - 15:12\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Reg0Spec > { Nu2W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
1:GPADC raw samples will be collected in the Output RAM in IFM mode"]
# [inline (always)]
# [must_use]
pub fn gpadc_debug_mode_enable (& mut self) -> GpadcDebugModeEnableW < Reg0Spec > { GpadcDebugModeEnableW :: new (self , 16) } # [doc = "Bits 17:31 - 31:17\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < Reg0Spec > { Nu3W :: new (self , 17) } } # [doc = "gpadc modes and enable\n\nYou can [`read`](crate::Reg::read) this register and get [`reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg0Spec ; impl crate :: RegisterSpec for Reg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg0::R`](R) reader structure"]
impl crate :: Readable for Reg0Spec { } # [doc = "`write(|w| ..)` method takes [`reg0::W`](W) writer structure"]
impl crate :: Writable for Reg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG0 to value 0"]
impl crate :: Resettable for Reg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG1 (rw) register accessor: gpadc start trigger for Inter frame mode\n\nYou can [`read`](crate::Reg::read) this register and get [`reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg1`]
module"]
# [doc (alias = "REG1")]
pub type Reg1 = crate :: Reg < reg1 :: Reg1Spec > ; # [doc = "gpadc start trigger for Inter frame mode"]
pub mod reg1 { # [doc = "Register `REG1` reader"]
pub type R = crate :: R < Reg1Spec > ; # [doc = "Register `REG1` writer"]
pub type W = crate :: W < Reg1Spec > ; # [doc = "Field `GPADC_TRIGGER` reader - 0:0\\]
Generates a single cycle pulse to trigger the IFM mode"]
pub type GpadcTriggerR = crate :: BitReader ; # [doc = "Field `GPADC_TRIGGER` writer - 0:0\\]
Generates a single cycle pulse to trigger the IFM mode"]
pub type GpadcTriggerW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 7:1\\]
TI reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:1\\]
TI reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `GPADC_INIT` reader - 8:8\\]
Resets the FSM and clears the data RAM"]
pub type GpadcInitR = crate :: BitReader ; # [doc = "Field `GPADC_INIT` writer - 8:8\\]
Resets the FSM and clears the data RAM"]
pub type GpadcInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 15:9\\]
TI reserved"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 15:9\\]
TI reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `GPADC_FSM_BYPASS` reader - 16:16\\]
1:Bypass gpadc control .When bypassed start = gpadc_start_byp_val config_val = config_value_ifm param_val = param_val_ifm"]
pub type GpadcFsmBypassR = crate :: BitReader ; # [doc = "Field `GPADC_FSM_BYPASS` writer - 16:16\\]
1:Bypass gpadc control .When bypassed start = gpadc_start_byp_val config_val = config_value_ifm param_val = param_val_ifm"]
pub type GpadcFsmBypassW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU3` reader - 23:17\\]
TI reserved"]
pub type Nu3R = crate :: FieldReader ; # [doc = "Field `NU3` writer - 23:17\\]
TI reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `GPADC_START_BYP_VAL` reader - "]
pub type GpadcStartBypValR = crate :: BitReader ; # [doc = "Field `GPADC_START_BYP_VAL` writer - "]
pub type GpadcStartBypValW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU4` reader - 31:25\\]
TI reserved"]
pub type Nu4R = crate :: FieldReader ; # [doc = "Field `NU4` writer - 31:25\\]
TI reserved"]
pub type Nu4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Generates a single cycle pulse to trigger the IFM mode"]
# [inline (always)]
pub fn gpadc_trigger (& self) -> GpadcTriggerR { GpadcTriggerR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
TI reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bit 8 - 8:8\\]
Resets the FSM and clears the data RAM"]
# [inline (always)]
pub fn gpadc_init (& self) -> GpadcInitR { GpadcInitR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:15 - 15:9\\]
TI reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 9) & 0x7f) as u8) } # [doc = "Bit 16 - 16:16\\]
1:Bypass gpadc control .When bypassed start = gpadc_start_byp_val config_val = config_value_ifm param_val = param_val_ifm"]
# [inline (always)]
pub fn gpadc_fsm_bypass (& self) -> GpadcFsmBypassR { GpadcFsmBypassR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:23 - 23:17\\]
TI reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 17) & 0x7f) as u8) } # [doc = "Bit 24"]
# [inline (always)]
pub fn gpadc_start_byp_val (& self) -> GpadcStartBypValR { GpadcStartBypValR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
TI reserved"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Generates a single cycle pulse to trigger the IFM mode"]
# [inline (always)]
# [must_use]
pub fn gpadc_trigger (& mut self) -> GpadcTriggerW < Reg1Spec > { GpadcTriggerW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Reg1Spec > { Nu1W :: new (self , 1) } # [doc = "Bit 8 - 8:8\\]
Resets the FSM and clears the data RAM"]
# [inline (always)]
# [must_use]
pub fn gpadc_init (& mut self) -> GpadcInitW < Reg1Spec > { GpadcInitW :: new (self , 8) } # [doc = "Bits 9:15 - 15:9\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Reg1Spec > { Nu2W :: new (self , 9) } # [doc = "Bit 16 - 16:16\\]
1:Bypass gpadc control .When bypassed start = gpadc_start_byp_val config_val = config_value_ifm param_val = param_val_ifm"]
# [inline (always)]
# [must_use]
pub fn gpadc_fsm_bypass (& mut self) -> GpadcFsmBypassW < Reg1Spec > { GpadcFsmBypassW :: new (self , 16) } # [doc = "Bits 17:23 - 23:17\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < Reg1Spec > { Nu3W :: new (self , 17) } # [doc = "Bit 24"]
# [inline (always)]
# [must_use]
pub fn gpadc_start_byp_val (& mut self) -> GpadcStartBypValW < Reg1Spec > { GpadcStartBypValW :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < Reg1Spec > { Nu4W :: new (self , 25) } } # [doc = "gpadc start trigger for Inter frame mode\n\nYou can [`read`](crate::Reg::read) this register and get [`reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg1Spec ; impl crate :: RegisterSpec for Reg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg1::R`](R) reader structure"]
impl crate :: Readable for Reg1Spec { } # [doc = "`write(|w| ..)` method takes [`reg1::W`](W) writer structure"]
impl crate :: Writable for Reg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG1 to value 0"]
impl crate :: Resettable for Reg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG2 (rw) register accessor: gpadc config for IFM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg2`]
module"]
# [doc (alias = "REG2")]
pub type Reg2 = crate :: Reg < reg2 :: Reg2Spec > ; # [doc = "gpadc config for IFM"]
pub mod reg2 { # [doc = "Register `REG2` reader"]
pub type R = crate :: R < Reg2Spec > ; # [doc = "Register `REG2` writer"]
pub type W = crate :: W < Reg2Spec > ; # [doc = "Field `CONFIG_VALUE_IFM` reader - 31:0\\]
Configuration value to be passed to analog in IFM mode"]
pub type ConfigValueIfmR = crate :: FieldReader < u32 > ; # [doc = "Field `CONFIG_VALUE_IFM` writer - 31:0\\]
Configuration value to be passed to analog in IFM mode"]
pub type ConfigValueIfmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Configuration value to be passed to analog in IFM mode"]
# [inline (always)]
pub fn config_value_ifm (& self) -> ConfigValueIfmR { ConfigValueIfmR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Configuration value to be passed to analog in IFM mode"]
# [inline (always)]
# [must_use]
pub fn config_value_ifm (& mut self) -> ConfigValueIfmW < Reg2Spec > { ConfigValueIfmW :: new (self , 0) } } # [doc = "gpadc config for IFM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg2Spec ; impl crate :: RegisterSpec for Reg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg2::R`](R) reader structure"]
impl crate :: Readable for Reg2Spec { } # [doc = "`write(|w| ..)` method takes [`reg2::W`](W) writer structure"]
impl crate :: Writable for Reg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG2 to value 0"]
impl crate :: Resettable for Reg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG3 (rw) register accessor: gpadc param, skip samples and collect samples for IFM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg3`]
module"]
# [doc (alias = "REG3")]
pub type Reg3 = crate :: Reg < reg3 :: Reg3Spec > ; # [doc = "gpadc param, skip samples and collect samples for IFM"]
pub mod reg3 { # [doc = "Register `REG3` reader"]
pub type R = crate :: R < Reg3Spec > ; # [doc = "Register `REG3` writer"]
pub type W = crate :: W < Reg3Spec > ; # [doc = "Field `PARAM_VAL_IFM` reader - 7:0\\]
Param value to be passed to analog in IFM mode(after one hot encoding)"]
pub type ParamValIfmR = crate :: FieldReader ; # [doc = "Field `PARAM_VAL_IFM` writer - 7:0\\]
Param value to be passed to analog in IFM mode(after one hot encoding)"]
pub type ParamValIfmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `COLLECT_SAMPLES_IFM` reader - 15:8\\]
number of GPADC readings to collect"]
pub type CollectSamplesIfmR = crate :: FieldReader ; # [doc = "Field `COLLECT_SAMPLES_IFM` writer - 15:8\\]
number of GPADC readings to collect"]
pub type CollectSamplesIfmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `SKIP_SAMPLES_IFM` reader - 22:16\\]
number of GPADC clocks to skip after trigger . Number of samples to skip = skip_samples_ifm\\[3:0\\]x(2skip_samples_ifm\\[6:4\\])"]
pub type SkipSamplesIfmR = crate :: FieldReader ; # [doc = "Field `SKIP_SAMPLES_IFM` writer - 22:16\\]
number of GPADC clocks to skip after trigger . Number of samples to skip = skip_samples_ifm\\[3:0\\]x(2skip_samples_ifm\\[6:4\\])"]
pub type SkipSamplesIfmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Param value to be passed to analog in IFM mode(after one hot encoding)"]
# [inline (always)]
pub fn param_val_ifm (& self) -> ParamValIfmR { ParamValIfmR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
number of GPADC readings to collect"]
# [inline (always)]
pub fn collect_samples_ifm (& self) -> CollectSamplesIfmR { CollectSamplesIfmR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:22 - 22:16\\]
number of GPADC clocks to skip after trigger . Number of samples to skip = skip_samples_ifm\\[3:0\\]x(2skip_samples_ifm\\[6:4\\])"]
# [inline (always)]
pub fn skip_samples_ifm (& self) -> SkipSamplesIfmR { SkipSamplesIfmR :: new (((self . bits >> 16) & 0x7f) as u8) } # [doc = "Bits 23:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 23) & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Param value to be passed to analog in IFM mode(after one hot encoding)"]
# [inline (always)]
# [must_use]
pub fn param_val_ifm (& mut self) -> ParamValIfmW < Reg3Spec > { ParamValIfmW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
number of GPADC readings to collect"]
# [inline (always)]
# [must_use]
pub fn collect_samples_ifm (& mut self) -> CollectSamplesIfmW < Reg3Spec > { CollectSamplesIfmW :: new (self , 8) } # [doc = "Bits 16:22 - 22:16\\]
number of GPADC clocks to skip after trigger . Number of samples to skip = skip_samples_ifm\\[3:0\\]x(2skip_samples_ifm\\[6:4\\])"]
# [inline (always)]
# [must_use]
pub fn skip_samples_ifm (& mut self) -> SkipSamplesIfmW < Reg3Spec > { SkipSamplesIfmW :: new (self , 16) } # [doc = "Bits 23:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg3Spec > { NuW :: new (self , 23) } } # [doc = "gpadc param, skip samples and collect samples for IFM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg3Spec ; impl crate :: RegisterSpec for Reg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg3::R`](R) reader structure"]
impl crate :: Readable for Reg3Spec { } # [doc = "`write(|w| ..)` method takes [`reg3::W`](W) writer structure"]
impl crate :: Writable for Reg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG3 to value 0"]
impl crate :: Resettable for Reg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG4 (rw) register accessor: Base address for Chirp profile 0 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg4`]
module"]
# [doc (alias = "REG4")]
pub type Reg4 = crate :: Reg < reg4 :: Reg4Spec > ; # [doc = "Base address for Chirp profile 0 in instruction packet RAM"]
pub mod reg4 { # [doc = "Register `REG4` reader"]
pub type R = crate :: R < Reg4Spec > ; # [doc = "Register `REG4` writer"]
pub type W = crate :: W < Reg4Spec > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP0` reader - 7:0\\]
Start Address of instruction-ram in CTM mode"]
pub type PktRamBaseAddrCp0R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP0` writer - 7:0\\]
Start Address of instruction-ram in CTM mode"]
pub type PktRamBaseAddrCp0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP1` reader - 15:8\\]
(End-Address + 1) of instruction-ram in CTM mode"]
pub type PktRamBaseAddrCp1R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP1` writer - 15:8\\]
(End-Address + 1) of instruction-ram in CTM mode"]
pub type PktRamBaseAddrCp1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP2` reader - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp2R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP2` writer - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP3` reader - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp3R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP3` writer - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Start Address of instruction-ram in CTM mode"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp0 (& self) -> PktRamBaseAddrCp0R { PktRamBaseAddrCp0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
(End-Address + 1) of instruction-ram in CTM mode"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp1 (& self) -> PktRamBaseAddrCp1R { PktRamBaseAddrCp1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp2 (& self) -> PktRamBaseAddrCp2R { PktRamBaseAddrCp2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp3 (& self) -> PktRamBaseAddrCp3R { PktRamBaseAddrCp3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Start Address of instruction-ram in CTM mode"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp0 (& mut self) -> PktRamBaseAddrCp0W < Reg4Spec > { PktRamBaseAddrCp0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
(End-Address + 1) of instruction-ram in CTM mode"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp1 (& mut self) -> PktRamBaseAddrCp1W < Reg4Spec > { PktRamBaseAddrCp1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp2 (& mut self) -> PktRamBaseAddrCp2W < Reg4Spec > { PktRamBaseAddrCp2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp3 (& mut self) -> PktRamBaseAddrCp3W < Reg4Spec > { PktRamBaseAddrCp3W :: new (self , 24) } } # [doc = "Base address for Chirp profile 0 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg4Spec ; impl crate :: RegisterSpec for Reg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg4::R`](R) reader structure"]
impl crate :: Readable for Reg4Spec { } # [doc = "`write(|w| ..)` method takes [`reg4::W`](W) writer structure"]
impl crate :: Writable for Reg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG4 to value 0"]
impl crate :: Resettable for Reg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG5 (rw) register accessor: Base address for Chirp profile 1 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg5`]
module"]
# [doc (alias = "REG5")]
pub type Reg5 = crate :: Reg < reg5 :: Reg5Spec > ; # [doc = "Base address for Chirp profile 1 in instruction packet RAM"]
pub mod reg5 { # [doc = "Register `REG5` reader"]
pub type R = crate :: R < Reg5Spec > ; # [doc = "Register `REG5` writer"]
pub type W = crate :: W < Reg5Spec > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP4` reader - 7:0\\]
TI reserved"]
pub type PktRamBaseAddrCp4R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP4` writer - 7:0\\]
TI reserved"]
pub type PktRamBaseAddrCp4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP5` reader - 15:8\\]
TI reserved"]
pub type PktRamBaseAddrCp5R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP5` writer - 15:8\\]
TI reserved"]
pub type PktRamBaseAddrCp5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP6` reader - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp6R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP6` writer - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP7` reader - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp7R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP7` writer - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp4 (& self) -> PktRamBaseAddrCp4R { PktRamBaseAddrCp4R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp5 (& self) -> PktRamBaseAddrCp5R { PktRamBaseAddrCp5R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp6 (& self) -> PktRamBaseAddrCp6R { PktRamBaseAddrCp6R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp7 (& self) -> PktRamBaseAddrCp7R { PktRamBaseAddrCp7R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp4 (& mut self) -> PktRamBaseAddrCp4W < Reg5Spec > { PktRamBaseAddrCp4W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp5 (& mut self) -> PktRamBaseAddrCp5W < Reg5Spec > { PktRamBaseAddrCp5W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp6 (& mut self) -> PktRamBaseAddrCp6W < Reg5Spec > { PktRamBaseAddrCp6W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp7 (& mut self) -> PktRamBaseAddrCp7W < Reg5Spec > { PktRamBaseAddrCp7W :: new (self , 24) } } # [doc = "Base address for Chirp profile 1 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg5Spec ; impl crate :: RegisterSpec for Reg5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg5::R`](R) reader structure"]
impl crate :: Readable for Reg5Spec { } # [doc = "`write(|w| ..)` method takes [`reg5::W`](W) writer structure"]
impl crate :: Writable for Reg5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG5 to value 0"]
impl crate :: Resettable for Reg5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG6 (rw) register accessor: Base address for Chirp profile 2 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg6`]
module"]
# [doc (alias = "REG6")]
pub type Reg6 = crate :: Reg < reg6 :: Reg6Spec > ; # [doc = "Base address for Chirp profile 2 in instruction packet RAM"]
pub mod reg6 { # [doc = "Register `REG6` reader"]
pub type R = crate :: R < Reg6Spec > ; # [doc = "Register `REG6` writer"]
pub type W = crate :: W < Reg6Spec > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP8` reader - 7:0\\]
TI reserved"]
pub type PktRamBaseAddrCp8R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP8` writer - 7:0\\]
TI reserved"]
pub type PktRamBaseAddrCp8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP9` reader - 15:8\\]
TI reserved"]
pub type PktRamBaseAddrCp9R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP9` writer - 15:8\\]
TI reserved"]
pub type PktRamBaseAddrCp9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP10` reader - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp10R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP10` writer - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP11` reader - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp11R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP11` writer - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp8 (& self) -> PktRamBaseAddrCp8R { PktRamBaseAddrCp8R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp9 (& self) -> PktRamBaseAddrCp9R { PktRamBaseAddrCp9R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp10 (& self) -> PktRamBaseAddrCp10R { PktRamBaseAddrCp10R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp11 (& self) -> PktRamBaseAddrCp11R { PktRamBaseAddrCp11R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp8 (& mut self) -> PktRamBaseAddrCp8W < Reg6Spec > { PktRamBaseAddrCp8W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp9 (& mut self) -> PktRamBaseAddrCp9W < Reg6Spec > { PktRamBaseAddrCp9W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp10 (& mut self) -> PktRamBaseAddrCp10W < Reg6Spec > { PktRamBaseAddrCp10W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp11 (& mut self) -> PktRamBaseAddrCp11W < Reg6Spec > { PktRamBaseAddrCp11W :: new (self , 24) } } # [doc = "Base address for Chirp profile 2 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg6Spec ; impl crate :: RegisterSpec for Reg6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg6::R`](R) reader structure"]
impl crate :: Readable for Reg6Spec { } # [doc = "`write(|w| ..)` method takes [`reg6::W`](W) writer structure"]
impl crate :: Writable for Reg6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG6 to value 0"]
impl crate :: Resettable for Reg6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG7 (rw) register accessor: Base address for Chirp profile 3 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg7`]
module"]
# [doc (alias = "REG7")]
pub type Reg7 = crate :: Reg < reg7 :: Reg7Spec > ; # [doc = "Base address for Chirp profile 3 in instruction packet RAM"]
pub mod reg7 { # [doc = "Register `REG7` reader"]
pub type R = crate :: R < Reg7Spec > ; # [doc = "Register `REG7` writer"]
pub type W = crate :: W < Reg7Spec > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP12` reader - 7:0\\]
TI reserved"]
pub type PktRamBaseAddrCp12R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP12` writer - 7:0\\]
TI reserved"]
pub type PktRamBaseAddrCp12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP13` reader - 15:8\\]
TI reserved"]
pub type PktRamBaseAddrCp13R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP13` writer - 15:8\\]
TI reserved"]
pub type PktRamBaseAddrCp13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP14` reader - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp14R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP14` writer - 23:16\\]
TI reserved"]
pub type PktRamBaseAddrCp14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP15` reader - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp15R = crate :: FieldReader ; # [doc = "Field `PKT_RAM_BASE_ADDR_CP15` writer - 31:24\\]
TI reserved"]
pub type PktRamBaseAddrCp15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp12 (& self) -> PktRamBaseAddrCp12R { PktRamBaseAddrCp12R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp13 (& self) -> PktRamBaseAddrCp13R { PktRamBaseAddrCp13R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp14 (& self) -> PktRamBaseAddrCp14R { PktRamBaseAddrCp14R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
pub fn pkt_ram_base_addr_cp15 (& self) -> PktRamBaseAddrCp15R { PktRamBaseAddrCp15R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp12 (& mut self) -> PktRamBaseAddrCp12W < Reg7Spec > { PktRamBaseAddrCp12W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp13 (& mut self) -> PktRamBaseAddrCp13W < Reg7Spec > { PktRamBaseAddrCp13W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp14 (& mut self) -> PktRamBaseAddrCp14W < Reg7Spec > { PktRamBaseAddrCp14W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn pkt_ram_base_addr_cp15 (& mut self) -> PktRamBaseAddrCp15W < Reg7Spec > { PktRamBaseAddrCp15W :: new (self , 24) } } # [doc = "Base address for Chirp profile 3 in instruction packet RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`reg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg7Spec ; impl crate :: RegisterSpec for Reg7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg7::R`](R) reader structure"]
impl crate :: Readable for Reg7Spec { } # [doc = "`write(|w| ..)` method takes [`reg7::W`](W) writer structure"]
impl crate :: Writable for Reg7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG7 to value 0"]
impl crate :: Resettable for Reg7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG8 (rw) register accessor: REG8\n\nYou can [`read`](crate::Reg::read) this register and get [`reg8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg8`]
module"]
# [doc (alias = "REG8")]
pub type Reg8 = crate :: Reg < reg8 :: Reg8Spec > ; # [doc = "REG8"]
pub mod reg8 { # [doc = "Register `REG8` reader"]
pub type R = crate :: R < Reg8Spec > ; # [doc = "Register `REG8` writer"]
pub type W = crate :: W < Reg8Spec > ; # [doc = "Field `GPADC_CLK_DIV` reader - 7:0\\]
TI reserved"]
pub type GpadcClkDivR = crate :: FieldReader ; # [doc = "Field `GPADC_CLK_DIV` writer - 7:0\\]
TI reserved"]
pub type GpadcClkDivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GPADC_CLK_ENABLE` reader - 8:8\\]
TI reserved"]
pub type GpadcClkEnableR = crate :: BitReader ; # [doc = "Field `GPADC_CLK_ENABLE` writer - 8:8\\]
TI reserved"]
pub type GpadcClkEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
pub fn gpadc_clk_div (& self) -> GpadcClkDivR { GpadcClkDivR :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 8 - 8:8\\]
TI reserved"]
# [inline (always)]
pub fn gpadc_clk_enable (& self) -> GpadcClkEnableR { GpadcClkEnableR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 9) & 0x007f_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn gpadc_clk_div (& mut self) -> GpadcClkDivW < Reg8Spec > { GpadcClkDivW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn gpadc_clk_enable (& mut self) -> GpadcClkEnableW < Reg8Spec > { GpadcClkEnableW :: new (self , 8) } # [doc = "Bits 9:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg8Spec > { NuW :: new (self , 9) } } # [doc = "REG8\n\nYou can [`read`](crate::Reg::read) this register and get [`reg8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg8Spec ; impl crate :: RegisterSpec for Reg8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg8::R`](R) reader structure"]
impl crate :: Readable for Reg8Spec { } # [doc = "`write(|w| ..)` method takes [`reg8::W`](W) writer structure"]
impl crate :: Writable for Reg8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG8 to value 0"]
impl crate :: Resettable for Reg8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG9 (rw) register accessor: REG9\n\nYou can [`read`](crate::Reg::read) this register and get [`reg9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg9`]
module"]
# [doc (alias = "REG9")]
pub type Reg9 = crate :: Reg < reg9 :: Reg9Spec > ; # [doc = "REG9"]
pub mod reg9 { # [doc = "Register `REG9` reader"]
pub type R = crate :: R < Reg9Spec > ; # [doc = "Register `REG9` writer"]
pub type W = crate :: W < Reg9Spec > ; # [doc = "Field `PARAM_NOT_USED_TX_ENA1_OFF` reader - 31:0\\]
TI reserved"]
pub type ParamNotUsedTxEna1OffR = crate :: FieldReader < u32 > ; # [doc = "Field `PARAM_NOT_USED_TX_ENA1_OFF` writer - 31:0\\]
TI reserved"]
pub type ParamNotUsedTxEna1OffW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn param_not_used_tx_ena1_off (& self) -> ParamNotUsedTxEna1OffR { ParamNotUsedTxEna1OffR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn param_not_used_tx_ena1_off (& mut self) -> ParamNotUsedTxEna1OffW < Reg9Spec > { ParamNotUsedTxEna1OffW :: new (self , 0) } } # [doc = "REG9\n\nYou can [`read`](crate::Reg::read) this register and get [`reg9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg9Spec ; impl crate :: RegisterSpec for Reg9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg9::R`](R) reader structure"]
impl crate :: Readable for Reg9Spec { } # [doc = "`write(|w| ..)` method takes [`reg9::W`](W) writer structure"]
impl crate :: Writable for Reg9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG9 to value 0"]
impl crate :: Resettable for Reg9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG10 (rw) register accessor: REG10\n\nYou can [`read`](crate::Reg::read) this register and get [`reg10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg10`]
module"]
# [doc (alias = "REG10")]
pub type Reg10 = crate :: Reg < reg10 :: Reg10Spec > ; # [doc = "REG10"]
pub mod reg10 { # [doc = "Register `REG10` reader"]
pub type R = crate :: R < Reg10Spec > ; # [doc = "Register `REG10` writer"]
pub type W = crate :: W < Reg10Spec > ; # [doc = "Field `PARAM_NOT_USED_TX_ENA2_OFF` reader - 31:0\\]
TI reserved"]
pub type ParamNotUsedTxEna2OffR = crate :: FieldReader < u32 > ; # [doc = "Field `PARAM_NOT_USED_TX_ENA2_OFF` writer - 31:0\\]
TI reserved"]
pub type ParamNotUsedTxEna2OffW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn param_not_used_tx_ena2_off (& self) -> ParamNotUsedTxEna2OffR { ParamNotUsedTxEna2OffR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn param_not_used_tx_ena2_off (& mut self) -> ParamNotUsedTxEna2OffW < Reg10Spec > { ParamNotUsedTxEna2OffW :: new (self , 0) } } # [doc = "REG10\n\nYou can [`read`](crate::Reg::read) this register and get [`reg10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg10Spec ; impl crate :: RegisterSpec for Reg10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg10::R`](R) reader structure"]
impl crate :: Readable for Reg10Spec { } # [doc = "`write(|w| ..)` method takes [`reg10::W`](W) writer structure"]
impl crate :: Writable for Reg10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG10 to value 0"]
impl crate :: Resettable for Reg10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG11 (rw) register accessor: REG11\n\nYou can [`read`](crate::Reg::read) this register and get [`reg11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg11`]
module"]
# [doc (alias = "REG11")]
pub type Reg11 = crate :: Reg < reg11 :: Reg11Spec > ; # [doc = "REG11"]
pub mod reg11 { # [doc = "Register `REG11` reader"]
pub type R = crate :: R < Reg11Spec > ; # [doc = "Register `REG11` writer"]
pub type W = crate :: W < Reg11Spec > ; # [doc = "Field `PARAM_NOT_USED_TX_ENA3_OFF` reader - 31:0\\]
TI reserved"]
pub type ParamNotUsedTxEna3OffR = crate :: FieldReader < u32 > ; # [doc = "Field `PARAM_NOT_USED_TX_ENA3_OFF` writer - 31:0\\]
TI reserved"]
pub type ParamNotUsedTxEna3OffW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn param_not_used_tx_ena3_off (& self) -> ParamNotUsedTxEna3OffR { ParamNotUsedTxEna3OffR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn param_not_used_tx_ena3_off (& mut self) -> ParamNotUsedTxEna3OffW < Reg11Spec > { ParamNotUsedTxEna3OffW :: new (self , 0) } } # [doc = "REG11\n\nYou can [`read`](crate::Reg::read) this register and get [`reg11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg11Spec ; impl crate :: RegisterSpec for Reg11Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg11::R`](R) reader structure"]
impl crate :: Readable for Reg11Spec { } # [doc = "`write(|w| ..)` method takes [`reg11::W`](W) writer structure"]
impl crate :: Writable for Reg11Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG11 to value 0"]
impl crate :: Resettable for Reg11Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG12 (rw) register accessor: REG12\n\nYou can [`read`](crate::Reg::read) this register and get [`reg12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg12`]
module"]
# [doc (alias = "REG12")]
pub type Reg12 = crate :: Reg < reg12 :: Reg12Spec > ; # [doc = "REG12"]
pub mod reg12 { # [doc = "Register `REG12` reader"]
pub type R = crate :: R < Reg12Spec > ; # [doc = "Register `REG12` writer"]
pub type W = crate :: W < Reg12Spec > ; # [doc = "Field `DRAM_ECC_ENABLE` reader - "]
pub type DramEccEnableR = crate :: BitReader ; # [doc = "Field `DRAM_ECC_ENABLE` writer - "]
pub type DramEccEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 7:1\\]
TI reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:1\\]
TI reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `DRAM_ECC_ERR_CLR` reader - 8:8\\]
TI reserved"]
pub type DramEccErrClrR = crate :: BitReader ; # [doc = "Field `DRAM_ECC_ERR_CLR` writer - 8:8\\]
TI reserved"]
pub type DramEccErrClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 15:9\\]
TI reserved"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 15:9\\]
TI reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `DRAM_ECC_ERR_ADDR` reader - 23:16\\]
TI reserved"]
pub type DramEccErrAddrR = crate :: FieldReader ; # [doc = "Field `DRAM_ECC_ERR_ADDR` writer - 23:16\\]
TI reserved"]
pub type DramEccErrAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `DRAM_REPAIRED_BIT` reader - 31:24\\]
TI reserved"]
pub type DramRepairedBitR = crate :: FieldReader ; # [doc = "Field `DRAM_REPAIRED_BIT` writer - 31:24\\]
TI reserved"]
pub type DramRepairedBitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bit 0"]
# [inline (always)]
pub fn dram_ecc_enable (& self) -> DramEccEnableR { DramEccEnableR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
TI reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bit 8 - 8:8\\]
TI reserved"]
# [inline (always)]
pub fn dram_ecc_err_clr (& self) -> DramEccErrClrR { DramEccErrClrR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:15 - 15:9\\]
TI reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 9) & 0x7f) as u8) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
pub fn dram_ecc_err_addr (& self) -> DramEccErrAddrR { DramEccErrAddrR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
pub fn dram_repaired_bit (& self) -> DramRepairedBitR { DramRepairedBitR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bit 0"]
# [inline (always)]
# [must_use]
pub fn dram_ecc_enable (& mut self) -> DramEccEnableW < Reg12Spec > { DramEccEnableW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Reg12Spec > { Nu1W :: new (self , 1) } # [doc = "Bit 8 - 8:8\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn dram_ecc_err_clr (& mut self) -> DramEccErrClrW < Reg12Spec > { DramEccErrClrW :: new (self , 8) } # [doc = "Bits 9:15 - 15:9\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Reg12Spec > { Nu2W :: new (self , 9) } # [doc = "Bits 16:23 - 23:16\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn dram_ecc_err_addr (& mut self) -> DramEccErrAddrW < Reg12Spec > { DramEccErrAddrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn dram_repaired_bit (& mut self) -> DramRepairedBitW < Reg12Spec > { DramRepairedBitW :: new (self , 24) } } # [doc = "REG12\n\nYou can [`read`](crate::Reg::read) this register and get [`reg12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg12Spec ; impl crate :: RegisterSpec for Reg12Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg12::R`](R) reader structure"]
impl crate :: Readable for Reg12Spec { } # [doc = "`write(|w| ..)` method takes [`reg12::W`](W) writer structure"]
impl crate :: Writable for Reg12Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG12 to value 0"]
impl crate :: Resettable for Reg12Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG13 (rw) register accessor: REG13\n\nYou can [`read`](crate::Reg::read) this register and get [`reg13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg13`]
module"]
# [doc (alias = "REG13")]
pub type Reg13 = crate :: Reg < reg13 :: Reg13Spec > ; # [doc = "REG13"]
pub mod reg13 { # [doc = "Register `REG13` reader"]
pub type R = crate :: R < Reg13Spec > ; # [doc = "Register `REG13` writer"]
pub type W = crate :: W < Reg13Spec > ; # [doc = "Field `SPARE_WR2` reader - 31:0\\]
TI reserved"]
pub type SpareWr2R = crate :: FieldReader < u32 > ; # [doc = "Field `SPARE_WR2` writer - 31:0\\]
TI reserved"]
pub type SpareWr2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn spare_wr2 (& self) -> SpareWr2R { SpareWr2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn spare_wr2 (& mut self) -> SpareWr2W < Reg13Spec > { SpareWr2W :: new (self , 0) } } # [doc = "REG13\n\nYou can [`read`](crate::Reg::read) this register and get [`reg13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg13Spec ; impl crate :: RegisterSpec for Reg13Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg13::R`](R) reader structure"]
impl crate :: Readable for Reg13Spec { } # [doc = "`write(|w| ..)` method takes [`reg13::W`](W) writer structure"]
impl crate :: Writable for Reg13Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG13 to value 0"]
impl crate :: Resettable for Reg13Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG14 (rw) register accessor: Sum of GP ADC readings\n\nYou can [`read`](crate::Reg::read) this register and get [`reg14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg14`]
module"]
# [doc (alias = "REG14")]
pub type Reg14 = crate :: Reg < reg14 :: Reg14Spec > ; # [doc = "Sum of GP ADC readings"]
pub mod reg14 { # [doc = "Register `REG14` reader"]
pub type R = crate :: R < Reg14Spec > ; # [doc = "Register `REG14` writer"]
pub type W = crate :: W < Reg14Spec > ; # [doc = "Field `SUM_IFM` reader - 19:0\\]
Sum of GP ADC readings"]
pub type SumIfmR = crate :: FieldReader < u32 > ; # [doc = "Field `SUM_IFM` writer - 19:0\\]
Sum of GP ADC readings"]
pub type SumIfmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `NU` reader - 31:20\\]
TI reserved"]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:20\\]
TI reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
Sum of GP ADC readings"]
# [inline (always)]
pub fn sum_ifm (& self) -> SumIfmR { SumIfmR :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
TI reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
Sum of GP ADC readings"]
# [inline (always)]
# [must_use]
pub fn sum_ifm (& mut self) -> SumIfmW < Reg14Spec > { SumIfmW :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg14Spec > { NuW :: new (self , 20) } } # [doc = "Sum of GP ADC readings\n\nYou can [`read`](crate::Reg::read) this register and get [`reg14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg14Spec ; impl crate :: RegisterSpec for Reg14Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg14::R`](R) reader structure"]
impl crate :: Readable for Reg14Spec { } # [doc = "`write(|w| ..)` method takes [`reg14::W`](W) writer structure"]
impl crate :: Writable for Reg14Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG14 to value 0"]
impl crate :: Resettable for Reg14Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG15 (rw) register accessor: Min and Max of GP ADC readings\n\nYou can [`read`](crate::Reg::read) this register and get [`reg15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg15`]
module"]
# [doc (alias = "REG15")]
pub type Reg15 = crate :: Reg < reg15 :: Reg15Spec > ; # [doc = "Min and Max of GP ADC readings"]
pub mod reg15 { # [doc = "Register `REG15` reader"]
pub type R = crate :: R < Reg15Spec > ; # [doc = "Register `REG15` writer"]
pub type W = crate :: W < Reg15Spec > ; # [doc = "Field `MIN_GPADC` reader - 9:0\\]
Min of GPADC readings"]
pub type MinGpadcR = crate :: FieldReader < u16 > ; # [doc = "Field `MIN_GPADC` writer - 9:0\\]
Min of GPADC readings"]
pub type MinGpadcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU1` reader - 15:10\\]
TI reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 15:10\\]
TI reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `MAX_GPADC` reader - 25:16\\]
Max of GPADC readings"]
pub type MaxGpadcR = crate :: FieldReader < u16 > ; # [doc = "Field `MAX_GPADC` writer - 25:16\\]
Max of GPADC readings"]
pub type MaxGpadcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU2` reader - 31:26\\]
TI reserved"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 31:26\\]
TI reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
Min of GPADC readings"]
# [inline (always)]
pub fn min_gpadc (& self) -> MinGpadcR { MinGpadcR :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:15 - 15:10\\]
TI reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bits 16:25 - 25:16\\]
Max of GPADC readings"]
# [inline (always)]
pub fn max_gpadc (& self) -> MaxGpadcR { MaxGpadcR :: new (((self . bits >> 16) & 0x03ff) as u16) } # [doc = "Bits 26:31 - 31:26\\]
TI reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
Min of GPADC readings"]
# [inline (always)]
# [must_use]
pub fn min_gpadc (& mut self) -> MinGpadcW < Reg15Spec > { MinGpadcW :: new (self , 0) } # [doc = "Bits 10:15 - 15:10\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Reg15Spec > { Nu1W :: new (self , 10) } # [doc = "Bits 16:25 - 25:16\\]
Max of GPADC readings"]
# [inline (always)]
# [must_use]
pub fn max_gpadc (& mut self) -> MaxGpadcW < Reg15Spec > { MaxGpadcW :: new (self , 16) } # [doc = "Bits 26:31 - 31:26\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Reg15Spec > { Nu2W :: new (self , 26) } } # [doc = "Min and Max of GP ADC readings\n\nYou can [`read`](crate::Reg::read) this register and get [`reg15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg15Spec ; impl crate :: RegisterSpec for Reg15Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg15::R`](R) reader structure"]
impl crate :: Readable for Reg15Spec { } # [doc = "`write(|w| ..)` method takes [`reg15::W`](W) writer structure"]
impl crate :: Writable for Reg15Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG15 to value 0"]
impl crate :: Resettable for Reg15Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG16 (rw) register accessor: REG16\n\nYou can [`read`](crate::Reg::read) this register and get [`reg16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg16`]
module"]
# [doc (alias = "REG16")]
pub type Reg16 = crate :: Reg < reg16 :: Reg16Spec > ; # [doc = "REG16"]
pub mod reg16 { # [doc = "Register `REG16` reader"]
pub type R = crate :: R < Reg16Spec > ; # [doc = "Register `REG16` writer"]
pub type W = crate :: W < Reg16Spec > ; # [doc = "Field `GPADC_MEM_INIT_DONE_STAT` reader - 0:0\\]
Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress"]
pub type GpadcMemInitDoneStatR = crate :: BitReader ; # [doc = "Field `GPADC_MEM_INIT_DONE_STAT` writer - 0:0\\]
Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress"]
pub type GpadcMemInitDoneStatW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:1\\]
TI reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:1\\]
TI reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress"]
# [inline (always)]
pub fn gpadc_mem_init_done_stat (& self) -> GpadcMemInitDoneStatR { GpadcMemInitDoneStatR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
TI reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress"]
# [inline (always)]
# [must_use]
pub fn gpadc_mem_init_done_stat (& mut self) -> GpadcMemInitDoneStatW < Reg16Spec > { GpadcMemInitDoneStatW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg16Spec > { NuW :: new (self , 1) } } # [doc = "REG16\n\nYou can [`read`](crate::Reg::read) this register and get [`reg16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg16Spec ; impl crate :: RegisterSpec for Reg16Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg16::R`](R) reader structure"]
impl crate :: Readable for Reg16Spec { } # [doc = "`write(|w| ..)` method takes [`reg16::W`](W) writer structure"]
impl crate :: Writable for Reg16Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG16 to value 0"]
impl crate :: Resettable for Reg16Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG17 (rw) register accessor: REG17\n\nYou can [`read`](crate::Reg::read) this register and get [`reg17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg17`]
module"]
# [doc (alias = "REG17")]
pub type Reg17 = crate :: Reg < reg17 :: Reg17Spec > ; # [doc = "REG17"]
pub mod reg17 { # [doc = "Register `REG17` reader"]
pub type R = crate :: R < Reg17Spec > ; # [doc = "Register `REG17` writer"]
pub type W = crate :: W < Reg17Spec > ; # [doc = "Field `GPADC_IFM_DONE_STATUS` reader - 0:0\\]
Test completion status in IFM mode.Used for FW polling"]
pub type GpadcIfmDoneStatusR = crate :: BitReader ; # [doc = "Field `GPADC_IFM_DONE_STATUS` writer - 0:0\\]
Test completion status in IFM mode.Used for FW polling"]
pub type GpadcIfmDoneStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:1\\]
TI reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:1\\]
TI reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Test completion status in IFM mode.Used for FW polling"]
# [inline (always)]
pub fn gpadc_ifm_done_status (& self) -> GpadcIfmDoneStatusR { GpadcIfmDoneStatusR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
TI reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Test completion status in IFM mode.Used for FW polling"]
# [inline (always)]
# [must_use]
pub fn gpadc_ifm_done_status (& mut self) -> GpadcIfmDoneStatusW < Reg17Spec > { GpadcIfmDoneStatusW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg17Spec > { NuW :: new (self , 1) } } # [doc = "REG17\n\nYou can [`read`](crate::Reg::read) this register and get [`reg17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg17Spec ; impl crate :: RegisterSpec for Reg17Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg17::R`](R) reader structure"]
impl crate :: Readable for Reg17Spec { } # [doc = "`write(|w| ..)` method takes [`reg17::W`](W) writer structure"]
impl crate :: Writable for Reg17Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG17 to value 0"]
impl crate :: Resettable for Reg17Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG18 (rw) register accessor: REG18\n\nYou can [`read`](crate::Reg::read) this register and get [`reg18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg18`]
module"]
# [doc (alias = "REG18")]
pub type Reg18 = crate :: Reg < reg18 :: Reg18Spec > ; # [doc = "REG18"]
pub mod reg18 { # [doc = "Register `REG18` reader"]
pub type R = crate :: R < Reg18Spec > ; # [doc = "Register `REG18` writer"]
pub type W = crate :: W < Reg18Spec > ; # [doc = "Field `GPADC_IFM_DONE_CLR` reader - 0:0\\]
Clear \"ifm_done_status\""]
pub type GpadcIfmDoneClrR = crate :: BitReader ; # [doc = "Field `GPADC_IFM_DONE_CLR` writer - 0:0\\]
Clear \"ifm_done_status\""]
pub type GpadcIfmDoneClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:1\\]
TI reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:1\\]
TI reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear \"ifm_done_status\""]
# [inline (always)]
pub fn gpadc_ifm_done_clr (& self) -> GpadcIfmDoneClrR { GpadcIfmDoneClrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
TI reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear \"ifm_done_status\""]
# [inline (always)]
# [must_use]
pub fn gpadc_ifm_done_clr (& mut self) -> GpadcIfmDoneClrW < Reg18Spec > { GpadcIfmDoneClrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg18Spec > { NuW :: new (self , 1) } } # [doc = "REG18\n\nYou can [`read`](crate::Reg::read) this register and get [`reg18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg18Spec ; impl crate :: RegisterSpec for Reg18Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg18::R`](R) reader structure"]
impl crate :: Readable for Reg18Spec { } # [doc = "`write(|w| ..)` method takes [`reg18::W`](W) writer structure"]
impl crate :: Writable for Reg18Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG18 to value 0"]
impl crate :: Resettable for Reg18Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG19 (rw) register accessor: REG19\n\nYou can [`read`](crate::Reg::read) this register and get [`reg19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg19`]
module"]
# [doc (alias = "REG19")]
pub type Reg19 = crate :: Reg < reg19 :: Reg19Spec > ; # [doc = "REG19"]
pub mod reg19 { # [doc = "Register `REG19` reader"]
pub type R = crate :: R < Reg19Spec > ; # [doc = "Register `REG19` writer"]
pub type W = crate :: W < Reg19Spec > ; # [doc = "Field `GPADC_SAMPLES_FRAME` reader - 15:0\\]
Total number of GPADC samples collected in a frame"]
pub type GpadcSamplesFrameR = crate :: FieldReader < u16 > ; # [doc = "Field `GPADC_SAMPLES_FRAME` writer - 15:0\\]
Total number of GPADC samples collected in a frame"]
pub type GpadcSamplesFrameW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - 31:16\\]
TI reserved"]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:16\\]
TI reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Total number of GPADC samples collected in a frame"]
# [inline (always)]
pub fn gpadc_samples_frame (& self) -> GpadcSamplesFrameR { GpadcSamplesFrameR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
TI reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Total number of GPADC samples collected in a frame"]
# [inline (always)]
# [must_use]
pub fn gpadc_samples_frame (& mut self) -> GpadcSamplesFrameW < Reg19Spec > { GpadcSamplesFrameW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Reg19Spec > { NuW :: new (self , 16) } } # [doc = "REG19\n\nYou can [`read`](crate::Reg::read) this register and get [`reg19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg19Spec ; impl crate :: RegisterSpec for Reg19Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg19::R`](R) reader structure"]
impl crate :: Readable for Reg19Spec { } # [doc = "`write(|w| ..)` method takes [`reg19::W`](W) writer structure"]
impl crate :: Writable for Reg19Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG19 to value 0"]
impl crate :: Resettable for Reg19Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG20 (rw) register accessor: REG20\n\nYou can [`read`](crate::Reg::read) this register and get [`reg20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg20`]
module"]
# [doc (alias = "REG20")]
pub type Reg20 = crate :: Reg < reg20 :: Reg20Spec > ; # [doc = "REG20"]
pub mod reg20 { # [doc = "Register `REG20` reader"]
pub type R = crate :: R < Reg20Spec > ; # [doc = "Register `REG20` writer"]
pub type W = crate :: W < Reg20Spec > ; # [doc = "Field `SPARE_RD1` reader - 31:0\\]
TI reserved"]
pub type SpareRd1R = crate :: FieldReader < u32 > ; # [doc = "Field `SPARE_RD1` writer - 31:0\\]
TI reserved"]
pub type SpareRd1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn spare_rd1 (& self) -> SpareRd1R { SpareRd1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn spare_rd1 (& mut self) -> SpareRd1W < Reg20Spec > { SpareRd1W :: new (self , 0) } } # [doc = "REG20\n\nYou can [`read`](crate::Reg::read) this register and get [`reg20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg20Spec ; impl crate :: RegisterSpec for Reg20Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg20::R`](R) reader structure"]
impl crate :: Readable for Reg20Spec { } # [doc = "`write(|w| ..)` method takes [`reg20::W`](W) writer structure"]
impl crate :: Writable for Reg20Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG20 to value 0"]
impl crate :: Resettable for Reg20Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG21 (rw) register accessor: REG21\n\nYou can [`read`](crate::Reg::read) this register and get [`reg21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg21`]
module"]
# [doc (alias = "REG21")]
pub type Reg21 = crate :: Reg < reg21 :: Reg21Spec > ; # [doc = "REG21"]
pub mod reg21 { # [doc = "Register `REG21` reader"]
pub type R = crate :: R < Reg21Spec > ; # [doc = "Register `REG21` writer"]
pub type W = crate :: W < Reg21Spec > ; # [doc = "Field `SPARE_RD2` reader - 31:0\\]
TI reserved"]
pub type SpareRd2R = crate :: FieldReader < u32 > ; # [doc = "Field `SPARE_RD2` writer - 31:0\\]
TI reserved"]
pub type SpareRd2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn spare_rd2 (& self) -> SpareRd2R { SpareRd2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn spare_rd2 (& mut self) -> SpareRd2W < Reg21Spec > { SpareRd2W :: new (self , 0) } } # [doc = "REG21\n\nYou can [`read`](crate::Reg::read) this register and get [`reg21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg21Spec ; impl crate :: RegisterSpec for Reg21Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg21::R`](R) reader structure"]
impl crate :: Readable for Reg21Spec { } # [doc = "`write(|w| ..)` method takes [`reg21::W`](W) writer structure"]
impl crate :: Writable for Reg21Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG21 to value 0"]
impl crate :: Resettable for Reg21Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REG22 (rw) register accessor: REG22\n\nYou can [`read`](crate::Reg::read) this register and get [`reg22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg22`]
module"]
# [doc (alias = "REG22")]
pub type Reg22 = crate :: Reg < reg22 :: Reg22Spec > ; # [doc = "REG22"]
pub mod reg22 { # [doc = "Register `REG22` reader"]
pub type R = crate :: R < Reg22Spec > ; # [doc = "Register `REG22` writer"]
pub type W = crate :: W < Reg22Spec > ; # [doc = "Field `SPARE_WR1` reader - 31:0\\]
TI reserved"]
pub type SpareWr1R = crate :: FieldReader < u32 > ; # [doc = "Field `SPARE_WR1` writer - 31:0\\]
TI reserved"]
pub type SpareWr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
pub fn spare_wr1 (& self) -> SpareWr1R { SpareWr1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI reserved"]
# [inline (always)]
# [must_use]
pub fn spare_wr1 (& mut self) -> SpareWr1W < Reg22Spec > { SpareWr1W :: new (self , 0) } } # [doc = "REG22\n\nYou can [`read`](crate::Reg::read) this register and get [`reg22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reg22Spec ; impl crate :: RegisterSpec for Reg22Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reg22::R`](R) reader structure"]
impl crate :: Readable for Reg22Spec { } # [doc = "`write(|w| ..)` method takes [`reg22::W`](W) writer structure"]
impl crate :: Writable for Reg22Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REG22 to value 0"]
impl crate :: Resettable for Reg22Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_LIN"]
pub struct AppLin { _marker : PhantomData < * const () > } unsafe impl Send for AppLin { } impl AppLin { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_lin :: RegisterBlock = 0x5300_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_lin :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppLin { type Target = app_lin :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppLin { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppLin") . finish () } } # [doc = "APP_LIN"]
pub mod app_lin { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { scigcr0 : Scigcr0 , scigcr1 : Scigcr1 , scigcr2 : Scigcr2 , scisetint : Scisetint , sciclearint : Sciclearint , scisetintlvl : Scisetintlvl , sciclearintlvl : Sciclearintlvl , sciflr : Sciflr , sciintvect0 : Sciintvect0 , sciintvect1 : Sciintvect1 , sciformat : Sciformat , brsr : Brsr , scied : Scied , scird : Scird , scitd : Scitd , scipio0 : Scipio0 , scipio1 : Scipio1 , scipio2 : Scipio2 , scipio3 : Scipio3 , scipio4 : Scipio4 , scipio5 : Scipio5 , scipio6 : Scipio6 , scipio7 : Scipio7 , scipio8 : Scipio8 , lincomp : Lincomp , linrd0 : Linrd0 , linrd1 : Linrd1 , linmask : Linmask , linid : Linid , lintd0 : Lintd0 , lintd1 : Lintd1 , mbrsr : Mbrsr , scipio9 : Scipio9 , reserved : Reserved , reserved1 : Reserved1 , reserved2 : Reserved2 , iodftctrl : Iodftctrl , } impl RegisterBlock { # [doc = "0x00 - The SCIGCR0 register defines the module reset."]
# [inline (always)]
pub const fn scigcr0 (& self) -> & Scigcr0 { & self . scigcr0 } # [doc = "0x04 - The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI."]
# [inline (always)]
pub const fn scigcr1 (& self) -> & Scigcr1 { & self . scigcr1 } # [doc = "0x08 - The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module."]
# [inline (always)]
pub const fn scigcr2 (& self) -> & Scigcr2 { & self . scigcr2 } # [doc = "0x0c - The SCISETINT register is used to enable the various interrupts available in the LIN module."]
# [inline (always)]
pub const fn scisetint (& self) -> & Scisetint { & self . scisetint } # [doc = "0x10 - The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register."]
# [inline (always)]
pub const fn sciclearint (& self) -> & Sciclearint { & self . sciclearint } # [doc = "0x14 - The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line."]
# [inline (always)]
pub const fn scisetintlvl (& self) -> & Scisetintlvl { & self . scisetintlvl } # [doc = "0x18 - The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line."]
# [inline (always)]
pub const fn sciclearintlvl (& self) -> & Sciclearintlvl { & self . sciclearintlvl } # [doc = "0x1c - The SCIFLR register indicates the current status of the various interrupt sources of the LIN module."]
# [inline (always)]
pub const fn sciflr (& self) -> & Sciflr { & self . sciflr } # [doc = "0x20 - The SCIINTVECT0 register indicates the offset for the INT0 interrupt line."]
# [inline (always)]
pub const fn sciintvect0 (& self) -> & Sciintvect0 { & self . sciintvect0 } # [doc = "0x24 - The SCIINTVECT1 register indicates the offset for the INT1 interrupt line."]
# [inline (always)]
pub const fn sciintvect1 (& self) -> & Sciintvect1 { & self . sciintvect1 } # [doc = "0x28 - The SCIFORMAT register is used to set up the character and frame lengths."]
# [inline (always)]
pub const fn sciformat (& self) -> & Sciformat { & self . sciformat } # [doc = "0x2c - The BRSR register is used to configure the baud rate of the LIN module."]
# [inline (always)]
pub const fn brsr (& self) -> & Brsr { & self . brsr } # [doc = "0x30 - The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator."]
# [inline (always)]
pub const fn scied (& self) -> & Scied { & self . scied } # [doc = "0x34 - The SCIRD register is where received data is stored and can be read from."]
# [inline (always)]
pub const fn scird (& self) -> & Scird { & self . scird } # [doc = "0x38 - The SCITD register is where data to be transmitted is written to by application software."]
# [inline (always)]
pub const fn scitd (& self) -> & Scitd { & self . scitd } # [doc = "0x3c - The SCIPIO0 register is used to enable the LINTX and LINRX pins."]
# [inline (always)]
pub const fn scipio0 (& self) -> & Scipio0 { & self . scipio0 } # [doc = "0x40 - SCIPIO1"]
# [inline (always)]
pub const fn scipio1 (& self) -> & Scipio1 { & self . scipio1 } # [doc = "0x44 - The SCIPIO2 register indicates the current status of the LINTX and LINRX pins."]
# [inline (always)]
pub const fn scipio2 (& self) -> & Scipio2 { & self . scipio2 } # [doc = "0x48 - SCIPIO3"]
# [inline (always)]
pub const fn scipio3 (& self) -> & Scipio3 { & self . scipio3 } # [doc = "0x4c - SCIPIO4"]
# [inline (always)]
pub const fn scipio4 (& self) -> & Scipio4 { & self . scipio4 } # [doc = "0x50 - SCIPIO5"]
# [inline (always)]
pub const fn scipio5 (& self) -> & Scipio5 { & self . scipio5 } # [doc = "0x54 - SCIPIO6"]
# [inline (always)]
pub const fn scipio6 (& self) -> & Scipio6 { & self . scipio6 } # [doc = "0x58 - SCIPIO7"]
# [inline (always)]
pub const fn scipio7 (& self) -> & Scipio7 { & self . scipio7 } # [doc = "0x5c - SCIPIO8"]
# [inline (always)]
pub const fn scipio8 (& self) -> & Scipio8 { & self . scipio8 } # [doc = "0x60 - The LINCOMPARE register is used to configure the sync delimeter and sync break extension."]
# [inline (always)]
pub const fn lincomp (& self) -> & Lincomp { & self . lincomp } # [doc = "0x64 - The LINRD0 register contains the lower 4 bytes of the received LIN frame data."]
# [inline (always)]
pub const fn linrd0 (& self) -> & Linrd0 { & self . linrd0 } # [doc = "0x68 - The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data."]
# [inline (always)]
pub const fn linrd1 (& self) -> & Linrd1 { & self . linrd1 } # [doc = "0x6c - The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames."]
# [inline (always)]
pub const fn linmask (& self) -> & Linmask { & self . linmask } # [doc = "0x70 - The LINID register contains the identification fields for LIN communication. NOTE: For software compatibility with future LIN modules, the HGEN CTRL bit must be set to 1, the RX ID MASK field must be set to FFh, and the TX ID MASK field must be set to FFh."]
# [inline (always)]
pub const fn linid (& self) -> & Linid { & self . linid } # [doc = "0x74 - The LINTD0 register contains the lower 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
# [inline (always)]
pub const fn lintd0 (& self) -> & Lintd0 { & self . lintd0 } # [doc = "0x78 - The LINTD1 register contains the upper 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
# [inline (always)]
pub const fn lintd1 (& self) -> & Lintd1 { & self . lintd1 } # [doc = "0x7c - The MBRSR register is used to configure the expected maximum baud rate of the LIN network."]
# [inline (always)]
pub const fn mbrsr (& self) -> & Mbrsr { & self . mbrsr } # [doc = "0x80 - Couldn't find this register in spec. But it's mentioned in RTL."]
# [inline (always)]
pub const fn scipio9 (& self) -> & Scipio9 { & self . scipio9 } # [doc = "0x84 - Reserved"]
# [inline (always)]
pub const fn reserved (& self) -> & Reserved { & self . reserved } # [doc = "0x88 - Reserved1"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0x8c - Reserved2"]
# [inline (always)]
pub const fn reserved2 (& self) -> & Reserved2 { & self . reserved2 } # [doc = "0x90 - The IODFTCTRL register is used to emulate various error and test conditions."]
# [inline (always)]
pub const fn iodftctrl (& self) -> & Iodftctrl { & self . iodftctrl } } # [doc = "SCIGCR0 (rw) register accessor: The SCIGCR0 register defines the module reset.\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr0`]
module"]
# [doc (alias = "SCIGCR0")]
pub type Scigcr0 = crate :: Reg < scigcr0 :: Scigcr0Spec > ; # [doc = "The SCIGCR0 register defines the module reset."]
pub mod scigcr0 { # [doc = "Register `SCIGCR0` reader"]
pub type R = crate :: R < Scigcr0Spec > ; # [doc = "Register `SCIGCR0` writer"]
pub type W = crate :: W < Scigcr0Spec > ; # [doc = "Field `RESET` reader - 0:0\\]
This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. Writable Only in privilege mode"]
pub type ResetR = crate :: BitReader ; # [doc = "Field `RESET` writer - 0:0\\]
This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. Writable Only in privilege mode"]
pub type ResetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. Writable Only in privilege mode"]
# [inline (always)]
pub fn reset (& self) -> ResetR { ResetR :: new ((self . bits & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. Writable Only in privilege mode"]
# [inline (always)]
# [must_use]
pub fn reset (& mut self) -> ResetW < Scigcr0Spec > { ResetW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scigcr0Spec > { Reserved1W :: new (self , 16) } } # [doc = "The SCIGCR0 register defines the module reset.\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr0Spec ; impl crate :: RegisterSpec for Scigcr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr0::R`](R) reader structure"]
impl crate :: Readable for Scigcr0Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr0::W`](W) writer structure"]
impl crate :: Writable for Scigcr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR0 to value 0"]
impl crate :: Resettable for Scigcr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIGCR1 (rw) register accessor: The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI.\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr1`]
module"]
# [doc (alias = "SCIGCR1")]
pub type Scigcr1 = crate :: Reg < scigcr1 :: Scigcr1Spec > ; # [doc = "The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI."]
pub mod scigcr1 { # [doc = "Register `SCIGCR1` reader"]
pub type R = crate :: R < Scigcr1Spec > ; # [doc = "Register `SCIGCR1` writer"]
pub type W = crate :: W < Scigcr1Spec > ; # [doc = "Field `COMMMODE` reader - 0:0\\]
SCI/LIN communication mode bit. In compatibility mode, it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5."]
pub type CommmodeR = crate :: BitReader ; # [doc = "Field `COMMMODE` writer - 0:0\\]
SCI/LIN communication mode bit. In compatibility mode, it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5."]
pub type CommmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMINGMODE` reader - 1:1\\]
SCI timing mode bit. This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation."]
pub type TimingmodeR = crate :: BitReader ; # [doc = "Field `TIMINGMODE` writer - 1:1\\]
SCI timing mode bit. This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation."]
pub type TimingmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITYENA` reader - 2:2\\]
Parity enable. Enables or disables the parity function."]
pub type ParityenaR = crate :: BitReader ; # [doc = "Field `PARITYENA` writer - 2:2\\]
Parity enable. Enables or disables the parity function."]
pub type ParityenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITY` reader - 3:3\\]
SCI parity odd/even selection. This bit is effective in SCI-compatible mode only. If the PARITY ENA bit (SCIGCR1.2) is set, PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit (in address-bit mode). The start and stop fields in the frame are not included in the parity calculation. This field is writable in SCI mode only."]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 3:3\\]
SCI parity odd/even selection. This bit is effective in SCI-compatible mode only. If the PARITY ENA bit (SCIGCR1.2) is set, PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit (in address-bit mode). The start and stop fields in the frame are not included in the parity calculation. This field is writable in SCI mode only."]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STOP` reader - 4:4\\]
SCI number of stop bits. This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until the end of the second stop bit (if STOP = 1) to begin checking for an idle period. This field is writable in SCI mode only."]
pub type StopR = crate :: BitReader ; # [doc = "Field `STOP` writer - 4:4\\]
SCI number of stop bits. This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until the end of the second stop bit (if STOP = 1) to begin checking for an idle period. This field is writable in SCI mode only."]
pub type StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLK_MASTER` reader - 5:5\\]
SCI internal clock enable or LIN Master/Slave configuration. In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines whether a LIN node is a slave or master."]
pub type ClkMasterR = crate :: BitReader ; # [doc = "Field `CLK_MASTER` writer - 5:5\\]
SCI internal clock enable or LIN Master/Slave configuration. In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines whether a LIN node is a slave or master."]
pub type ClkMasterW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LINMODE` reader - 6:6\\]
LIN mode This bit controls the mode of operation of the module. Writable Only in privilege mode"]
pub type LinmodeR = crate :: BitReader ; # [doc = "Field `LINMODE` writer - 6:6\\]
LIN mode This bit controls the mode of operation of the module. Writable Only in privilege mode"]
pub type LinmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWnRST` reader - 7:7\\]
Software reset (active low). This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime (i.e., while SWnRESET = 1): - STOP EXT Frame (SCIGCR1\\[13\\]) - CC bit (SCIGCR2\\[17\\]) - SC bit (SCIGCR2\\[16\\])"]
pub type SwnRstR = crate :: BitReader ; # [doc = "Field `SWnRST` writer - 7:7\\]
Software reset (active low). This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime (i.e., while SWnRESET = 1): - STOP EXT Frame (SCIGCR1\\[13\\]) - CC bit (SCIGCR2\\[17\\]) - SC bit (SCIGCR2\\[16\\])"]
pub type SwnRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SLEEP` reader - 8:8\\]
SCI sleep. SCI compatibility mode only. In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however, RXRDY is updated and SCIRD is loaded with new data only when an address frame is detected. The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set, regardless of the value of the SLEEP bit. In this way, if an error is detected on the receive data line while the SCI is asleep, software can promptly deal with the error condition. The SLEEP bit is not automatically cleared when an address byte is detected. This field is writable in SCI mode only."]
pub type SleepR = crate :: BitReader ; # [doc = "Field `SLEEP` writer - 8:8\\]
SCI sleep. SCI compatibility mode only. In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however, RXRDY is updated and SCIRD is loaded with new data only when an address frame is detected. The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set, regardless of the value of the SLEEP bit. In this way, if an error is detected on the receive data line while the SCI is asleep, software can promptly deal with the error condition. The SLEEP bit is not automatically cleared when an address byte is detected. This field is writable in SCI mode only."]
pub type SleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADAPT` reader - 9:9\\]
Adapt mode enable. This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file definition: automatic or select. Software and network configuration will decide which of the previous two modes. When this bit is cleared, the LIN 2.0 protocol fixed bit rate should be used. If the ADAPT bit is set, a LIN slave node detecting the baudrate will compare it to the prescalers in BRSR register and update it if they are different. The BRSR register will be updated with the new value. If this bit is not set there will be no adjustment to the BRSR register. This field is writable in LIN mode only."]
pub type AdaptR = crate :: BitReader ; # [doc = "Field `ADAPT` writer - 9:9\\]
Adapt mode enable. This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file definition: automatic or select. Software and network configuration will decide which of the previous two modes. When this bit is cleared, the LIN 2.0 protocol fixed bit rate should be used. If the ADAPT bit is set, a LIN slave node detecting the baudrate will compare it to the prescalers in BRSR register and update it if they are different. The BRSR register will be updated with the new value. If this bit is not set there will be no adjustment to the BRSR register. This field is writable in LIN mode only."]
pub type AdaptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MBUFMODE` reader - 10:10\\]
Multibuffer mode. This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage, that is, whether the RX/TX multibuffers are used or a single register, RD0/TD0, is used."]
pub type MbufmodeR = crate :: BitReader ; # [doc = "Field `MBUFMODE` writer - 10:10\\]
Multibuffer mode. This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage, that is, whether the RX/TX multibuffers are used or a single register, RD0/TD0, is used."]
pub type MbufmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTYPE` reader - 11:11\\]
Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced."]
pub type CtypeR = crate :: BitReader ; # [doc = "Field `CTYPE` writer - 11:11\\]
Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced."]
pub type CtypeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HGENCTRL` reader - 12:12\\]
HGEN control bit. This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison."]
pub type HgenctrlR = crate :: BitReader ; # [doc = "Field `HGENCTRL` writer - 12:12\\]
HGEN control bit. This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison."]
pub type HgenctrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STOPEXTFRAME` reader - 13:13\\]
Stop extended frame communication. This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped, this bit is cleared automatically."]
pub type StopextframeR = crate :: BitReader ; # [doc = "Field `STOPEXTFRAME` writer - 13:13\\]
Stop extended frame communication. This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped, this bit is cleared automatically."]
pub type StopextframeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LOOPBACK` reader - 16:16\\]
Loopback bit. This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedance state. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may result."]
pub type LoopbackR = crate :: BitReader ; # [doc = "Field `LOOPBACK` writer - 16:16\\]
Loopback bit. This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedance state. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may result."]
pub type LoopbackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONT` reader - 17:17\\]
Continue on suspend. This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set, the counters are not stopped during debug. When this bit is cleared, the counters are stopped during debug."]
pub type ContR = crate :: BitReader ; # [doc = "Field `CONT` writer - 17:17\\]
Continue on suspend. This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set, the counters are not stopped during debug. When this bit is cleared, the counters are stopped during debug."]
pub type ContW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 23:18\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 23:18\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RXENA` reader - 24:24\\]
Receive enable. This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the receive buffer or multi-buffers, prevents the RX status flags (see Table 7) from being updated by receive data, and inhibits both receive and error interrupts. However, the shift register continues to assemble data regardless of the state of RXENA. Note: If RXENA is cleared before the time the reception of a frame is complete, the data from the frame is not transferred into the receive buffer. Note: If RXENA is set before the time the reception of a frame is complete, the data from the frame is transferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process of assembling a frame, the status flags are not guaranteed to be accurate for that frame. To ensure that the status flags correctly reflect what was detected on the bus during a particular frame, RXENA should be set before the detection of that frame"]
pub type RxenaR = crate :: BitReader ; # [doc = "Field `RXENA` writer - 24:24\\]
Receive enable. This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the receive buffer or multi-buffers, prevents the RX status flags (see Table 7) from being updated by receive data, and inhibits both receive and error interrupts. However, the shift register continues to assemble data regardless of the state of RXENA. Note: If RXENA is cleared before the time the reception of a frame is complete, the data from the frame is not transferred into the receive buffer. Note: If RXENA is set before the time the reception of a frame is complete, the data from the frame is transferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process of assembling a frame, the status flags are not guaranteed to be accurate for that frame. To ensure that the status flags correctly reflect what was detected on the bus during a particular frame, RXENA should be set before the detection of that frame"]
pub type RxenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXENA` reader - 25:25\\]
Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy (with y=0, 1,...7) buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is not transmitted. If TXENA is cleared while transmission is ongoing, the data previously written to SCITD is sent (including the checksum byte in LIN mode)."]
pub type TxenaR = crate :: BitReader ; # [doc = "Field `TXENA` writer - 25:25\\]
Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy (with y=0, 1,...7) buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is not transmitted. If TXENA is cleared while transmission is ongoing, the data previously written to SCITD is sent (including the checksum byte in LIN mode)."]
pub type TxenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 31:26\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:26\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SCI/LIN communication mode bit. In compatibility mode, it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5."]
# [inline (always)]
pub fn commmode (& self) -> CommmodeR { CommmodeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SCI timing mode bit. This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation."]
# [inline (always)]
pub fn timingmode (& self) -> TimingmodeR { TimingmodeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Parity enable. Enables or disables the parity function."]
# [inline (always)]
pub fn parityena (& self) -> ParityenaR { ParityenaR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SCI parity odd/even selection. This bit is effective in SCI-compatible mode only. If the PARITY ENA bit (SCIGCR1.2) is set, PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit (in address-bit mode). The start and stop fields in the frame are not included in the parity calculation. This field is writable in SCI mode only."]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
SCI number of stop bits. This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until the end of the second stop bit (if STOP = 1) to begin checking for an idle period. This field is writable in SCI mode only."]
# [inline (always)]
pub fn stop (& self) -> StopR { StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
SCI internal clock enable or LIN Master/Slave configuration. In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines whether a LIN node is a slave or master."]
# [inline (always)]
pub fn clk_master (& self) -> ClkMasterR { ClkMasterR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
LIN mode This bit controls the mode of operation of the module. Writable Only in privilege mode"]
# [inline (always)]
pub fn linmode (& self) -> LinmodeR { LinmodeR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Software reset (active low). This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime (i.e., while SWnRESET = 1): - STOP EXT Frame (SCIGCR1\\[13\\]) - CC bit (SCIGCR2\\[17\\]) - SC bit (SCIGCR2\\[16\\])"]
# [inline (always)]
pub fn swn_rst (& self) -> SwnRstR { SwnRstR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
SCI sleep. SCI compatibility mode only. In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however, RXRDY is updated and SCIRD is loaded with new data only when an address frame is detected. The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set, regardless of the value of the SLEEP bit. In this way, if an error is detected on the receive data line while the SCI is asleep, software can promptly deal with the error condition. The SLEEP bit is not automatically cleared when an address byte is detected. This field is writable in SCI mode only."]
# [inline (always)]
pub fn sleep (& self) -> SleepR { SleepR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Adapt mode enable. This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file definition: automatic or select. Software and network configuration will decide which of the previous two modes. When this bit is cleared, the LIN 2.0 protocol fixed bit rate should be used. If the ADAPT bit is set, a LIN slave node detecting the baudrate will compare it to the prescalers in BRSR register and update it if they are different. The BRSR register will be updated with the new value. If this bit is not set there will be no adjustment to the BRSR register. This field is writable in LIN mode only."]
# [inline (always)]
pub fn adapt (& self) -> AdaptR { AdaptR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Multibuffer mode. This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage, that is, whether the RX/TX multibuffers are used or a single register, RD0/TD0, is used."]
# [inline (always)]
pub fn mbufmode (& self) -> MbufmodeR { MbufmodeR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced."]
# [inline (always)]
pub fn ctype (& self) -> CtypeR { CtypeR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
HGEN control bit. This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison."]
# [inline (always)]
pub fn hgenctrl (& self) -> HgenctrlR { HgenctrlR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Stop extended frame communication. This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped, this bit is cleared automatically."]
# [inline (always)]
pub fn stopextframe (& self) -> StopextframeR { StopextframeR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Loopback bit. This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedance state. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may result."]
# [inline (always)]
pub fn loopback (& self) -> LoopbackR { LoopbackR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Continue on suspend. This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set, the counters are not stopped during debug. When this bit is cleared, the counters are stopped during debug."]
# [inline (always)]
pub fn cont (& self) -> ContR { ContR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 18) & 0x3f) as u8) } # [doc = "Bit 24 - 24:24\\]
Receive enable. This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the receive buffer or multi-buffers, prevents the RX status flags (see Table 7) from being updated by receive data, and inhibits both receive and error interrupts. However, the shift register continues to assemble data regardless of the state of RXENA. Note: If RXENA is cleared before the time the reception of a frame is complete, the data from the frame is not transferred into the receive buffer. Note: If RXENA is set before the time the reception of a frame is complete, the data from the frame is transferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process of assembling a frame, the status flags are not guaranteed to be accurate for that frame. To ensure that the status flags correctly reflect what was detected on the bus during a particular frame, RXENA should be set before the detection of that frame"]
# [inline (always)]
pub fn rxena (& self) -> RxenaR { RxenaR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy (with y=0, 1,...7) buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is not transmitted. If TXENA is cleared while transmission is ongoing, the data previously written to SCITD is sent (including the checksum byte in LIN mode)."]
# [inline (always)]
pub fn txena (& self) -> TxenaR { TxenaR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SCI/LIN communication mode bit. In compatibility mode, it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5."]
# [inline (always)]
# [must_use]
pub fn commmode (& mut self) -> CommmodeW < Scigcr1Spec > { CommmodeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SCI timing mode bit. This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation."]
# [inline (always)]
# [must_use]
pub fn timingmode (& mut self) -> TimingmodeW < Scigcr1Spec > { TimingmodeW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Parity enable. Enables or disables the parity function."]
# [inline (always)]
# [must_use]
pub fn parityena (& mut self) -> ParityenaW < Scigcr1Spec > { ParityenaW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SCI parity odd/even selection. This bit is effective in SCI-compatible mode only. If the PARITY ENA bit (SCIGCR1.2) is set, PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit (in address-bit mode). The start and stop fields in the frame are not included in the parity calculation. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < Scigcr1Spec > { ParityW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
SCI number of stop bits. This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until the end of the second stop bit (if STOP = 1) to begin checking for an idle period. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn stop (& mut self) -> StopW < Scigcr1Spec > { StopW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
SCI internal clock enable or LIN Master/Slave configuration. In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines whether a LIN node is a slave or master."]
# [inline (always)]
# [must_use]
pub fn clk_master (& mut self) -> ClkMasterW < Scigcr1Spec > { ClkMasterW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
LIN mode This bit controls the mode of operation of the module. Writable Only in privilege mode"]
# [inline (always)]
# [must_use]
pub fn linmode (& mut self) -> LinmodeW < Scigcr1Spec > { LinmodeW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Software reset (active low). This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime (i.e., while SWnRESET = 1): - STOP EXT Frame (SCIGCR1\\[13\\]) - CC bit (SCIGCR2\\[17\\]) - SC bit (SCIGCR2\\[16\\])"]
# [inline (always)]
# [must_use]
pub fn swn_rst (& mut self) -> SwnRstW < Scigcr1Spec > { SwnRstW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
SCI sleep. SCI compatibility mode only. In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however, RXRDY is updated and SCIRD is loaded with new data only when an address frame is detected. The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set, regardless of the value of the SLEEP bit. In this way, if an error is detected on the receive data line while the SCI is asleep, software can promptly deal with the error condition. The SLEEP bit is not automatically cleared when an address byte is detected. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn sleep (& mut self) -> SleepW < Scigcr1Spec > { SleepW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Adapt mode enable. This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file definition: automatic or select. Software and network configuration will decide which of the previous two modes. When this bit is cleared, the LIN 2.0 protocol fixed bit rate should be used. If the ADAPT bit is set, a LIN slave node detecting the baudrate will compare it to the prescalers in BRSR register and update it if they are different. The BRSR register will be updated with the new value. If this bit is not set there will be no adjustment to the BRSR register. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn adapt (& mut self) -> AdaptW < Scigcr1Spec > { AdaptW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Multibuffer mode. This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage, that is, whether the RX/TX multibuffers are used or a single register, RD0/TD0, is used."]
# [inline (always)]
# [must_use]
pub fn mbufmode (& mut self) -> MbufmodeW < Scigcr1Spec > { MbufmodeW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced."]
# [inline (always)]
# [must_use]
pub fn ctype (& mut self) -> CtypeW < Scigcr1Spec > { CtypeW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
HGEN control bit. This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison."]
# [inline (always)]
# [must_use]
pub fn hgenctrl (& mut self) -> HgenctrlW < Scigcr1Spec > { HgenctrlW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Stop extended frame communication. This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped, this bit is cleared automatically."]
# [inline (always)]
# [must_use]
pub fn stopextframe (& mut self) -> StopextframeW < Scigcr1Spec > { StopextframeW :: new (self , 13) } # [doc = "Bit 16 - 16:16\\]
Loopback bit. This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedance state. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may result."]
# [inline (always)]
# [must_use]
pub fn loopback (& mut self) -> LoopbackW < Scigcr1Spec > { LoopbackW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Continue on suspend. This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set, the counters are not stopped during debug. When this bit is cleared, the counters are stopped during debug."]
# [inline (always)]
# [must_use]
pub fn cont (& mut self) -> ContW < Scigcr1Spec > { ContW :: new (self , 17) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scigcr1Spec > { Reserved1W :: new (self , 18) } # [doc = "Bit 24 - 24:24\\]
Receive enable. This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the receive buffer or multi-buffers, prevents the RX status flags (see Table 7) from being updated by receive data, and inhibits both receive and error interrupts. However, the shift register continues to assemble data regardless of the state of RXENA. Note: If RXENA is cleared before the time the reception of a frame is complete, the data from the frame is not transferred into the receive buffer. Note: If RXENA is set before the time the reception of a frame is complete, the data from the frame is transferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process of assembling a frame, the status flags are not guaranteed to be accurate for that frame. To ensure that the status flags correctly reflect what was detected on the bus during a particular frame, RXENA should be set before the detection of that frame"]
# [inline (always)]
# [must_use]
pub fn rxena (& mut self) -> RxenaW < Scigcr1Spec > { RxenaW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy (with y=0, 1,...7) buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is not transmitted. If TXENA is cleared while transmission is ongoing, the data previously written to SCITD is sent (including the checksum byte in LIN mode)."]
# [inline (always)]
# [must_use]
pub fn txena (& mut self) -> TxenaW < Scigcr1Spec > { TxenaW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < Scigcr1Spec > { Reserved2W :: new (self , 26) } } # [doc = "The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI.\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr1Spec ; impl crate :: RegisterSpec for Scigcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr1::R`](R) reader structure"]
impl crate :: Readable for Scigcr1Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr1::W`](W) writer structure"]
impl crate :: Writable for Scigcr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR1 to value 0"]
impl crate :: Resettable for Scigcr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIGCR2 (rw) register accessor: The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr2`]
module"]
# [doc (alias = "SCIGCR2")]
pub type Scigcr2 = crate :: Reg < scigcr2 :: Scigcr2Spec > ; # [doc = "The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module."]
pub mod scigcr2 { # [doc = "Register `SCIGCR2` reader"]
pub type R = crate :: R < Scigcr2Spec > ; # [doc = "Register `SCIGCR2` writer"]
pub type W = crate :: W < Scigcr2Spec > ; # [doc = "Field `POWERDOWN` reader - 0:0\\]
Power down. This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set, the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay low-power mode from being entered until completion of reception. In LIN mode the user may set the POWERDOWN bit on Sleep Command reception or on idle bus detection (more than 4 seconds, i.e. 80,000 cycles at 20kHz)"]
pub type PowerdownR = crate :: BitReader ; # [doc = "Field `POWERDOWN` writer - 0:0\\]
Power down. This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set, the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay low-power mode from being entered until completion of reception. In LIN mode the user may set the POWERDOWN bit on Sleep Command reception or on idle bus detection (more than 4 seconds, i.e. 80,000 cycles at 20kHz)"]
pub type PowerdownW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `GENWU` reader - 8:8\\]
Generate wakeup signal. This bit controls the generation of a wakeup signal, by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break."]
pub type GenwuR = crate :: BitReader ; # [doc = "Field `GENWU` writer - 8:8\\]
Generate wakeup signal. This bit controls the generation of a wakeup signal, by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break."]
pub type GenwuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 15:9\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:9\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `SC` reader - 16:16\\]
Send Checksum This mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the checkbyte will be sent after the last byte count, indicated by the SCIFORMAT\\[18:16\\]). This field is writable in LIN mode only."]
pub type ScR = crate :: BitReader ; # [doc = "Field `SC` writer - 16:16\\]
Send Checksum This mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the checkbyte will be sent after the last byte count, indicated by the SCIFORMAT\\[18:16\\]). This field is writable in LIN mode only."]
pub type ScW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC` reader - 17:17\\]
Compare Checksum. This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit. In non multibuffer mode, once the CC bit is set, the checksum will be compared on the byte that is currently being received, expected to be the checkbyte. During Multi-buffer mode, following are the scenarios associated with the CC bit : - If CC bit is set during the reception of the data, then the byte that is received after the reception of the programmed no. of data bytes indicated by SCIFORMAT\\[18:16\\], is treated as a checksum byte. - If CC bit is set during the IDLE period (i.e. during inter-frame space), then the next immediate byte will be treated as a checksum byte. A CE will immediatly be flagged if there is a checksum error. This bit is automatically cleared once the checksum is successfully compared."]
pub type CcR = crate :: BitReader ; # [doc = "Field `CC` writer - 17:17\\]
Compare Checksum. This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit. In non multibuffer mode, once the CC bit is set, the checksum will be compared on the byte that is currently being received, expected to be the checkbyte. During Multi-buffer mode, following are the scenarios associated with the CC bit : - If CC bit is set during the reception of the data, then the byte that is received after the reception of the programmed no. of data bytes indicated by SCIFORMAT\\[18:16\\], is treated as a checksum byte. - If CC bit is set during the IDLE period (i.e. during inter-frame space), then the next immediate byte will be treated as a checksum byte. A CE will immediatly be flagged if there is a checksum error. This bit is automatically cleared once the checksum is successfully compared."]
pub type CcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 31:18\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved2` writer - 31:18\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Power down. This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set, the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay low-power mode from being entered until completion of reception. In LIN mode the user may set the POWERDOWN bit on Sleep Command reception or on idle bus detection (more than 4 seconds, i.e. 80,000 cycles at 20kHz)"]
# [inline (always)]
pub fn powerdown (& self) -> PowerdownR { PowerdownR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Generate wakeup signal. This bit controls the generation of a wakeup signal, by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break."]
# [inline (always)]
pub fn genwu (& self) -> GenwuR { GenwuR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:15 - 15:9\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 9) & 0x7f) as u8) } # [doc = "Bit 16 - 16:16\\]
Send Checksum This mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the checkbyte will be sent after the last byte count, indicated by the SCIFORMAT\\[18:16\\]). This field is writable in LIN mode only."]
# [inline (always)]
pub fn sc (& self) -> ScR { ScR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Compare Checksum. This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit. In non multibuffer mode, once the CC bit is set, the checksum will be compared on the byte that is currently being received, expected to be the checkbyte. During Multi-buffer mode, following are the scenarios associated with the CC bit : - If CC bit is set during the reception of the data, then the byte that is received after the reception of the programmed no. of data bytes indicated by SCIFORMAT\\[18:16\\], is treated as a checksum byte. - If CC bit is set during the IDLE period (i.e. during inter-frame space), then the next immediate byte will be treated as a checksum byte. A CE will immediatly be flagged if there is a checksum error. This bit is automatically cleared once the checksum is successfully compared."]
# [inline (always)]
pub fn cc (& self) -> CcR { CcR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:31 - 31:18\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Power down. This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set, the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay low-power mode from being entered until completion of reception. In LIN mode the user may set the POWERDOWN bit on Sleep Command reception or on idle bus detection (more than 4 seconds, i.e. 80,000 cycles at 20kHz)"]
# [inline (always)]
# [must_use]
pub fn powerdown (& mut self) -> PowerdownW < Scigcr2Spec > { PowerdownW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Generate wakeup signal. This bit controls the generation of a wakeup signal, by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break."]
# [inline (always)]
# [must_use]
pub fn genwu (& mut self) -> GenwuW < Scigcr2Spec > { GenwuW :: new (self , 8) } # [doc = "Bits 9:15 - 15:9\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scigcr2Spec > { Reserved1W :: new (self , 9) } # [doc = "Bit 16 - 16:16\\]
Send Checksum This mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the checkbyte will be sent after the last byte count, indicated by the SCIFORMAT\\[18:16\\]). This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn sc (& mut self) -> ScW < Scigcr2Spec > { ScW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Compare Checksum. This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit. In non multibuffer mode, once the CC bit is set, the checksum will be compared on the byte that is currently being received, expected to be the checkbyte. During Multi-buffer mode, following are the scenarios associated with the CC bit : - If CC bit is set during the reception of the data, then the byte that is received after the reception of the programmed no. of data bytes indicated by SCIFORMAT\\[18:16\\], is treated as a checksum byte. - If CC bit is set during the IDLE period (i.e. during inter-frame space), then the next immediate byte will be treated as a checksum byte. A CE will immediatly be flagged if there is a checksum error. This bit is automatically cleared once the checksum is successfully compared."]
# [inline (always)]
# [must_use]
pub fn cc (& mut self) -> CcW < Scigcr2Spec > { CcW :: new (self , 17) } # [doc = "Bits 18:31 - 31:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < Scigcr2Spec > { Reserved2W :: new (self , 18) } } # [doc = "The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr2Spec ; impl crate :: RegisterSpec for Scigcr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr2::R`](R) reader structure"]
impl crate :: Readable for Scigcr2Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr2::W`](W) writer structure"]
impl crate :: Writable for Scigcr2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR2 to value 0"]
impl crate :: Resettable for Scigcr2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCISETINT (rw) register accessor: The SCISETINT register is used to enable the various interrupts available in the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scisetint`]
module"]
# [doc (alias = "SCISETINT")]
pub type Scisetint = crate :: Reg < scisetint :: ScisetintSpec > ; # [doc = "The SCISETINT register is used to enable the various interrupts available in the LIN module."]
pub mod scisetint { # [doc = "Register `SCISETINT` reader"]
pub type R = crate :: R < ScisetintSpec > ; # [doc = "Register `SCISETINT` writer"]
pub type W = crate :: W < ScisetintSpec > ; # [doc = "Field `SETBRKDTINT` reader - 0:0\\]
Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
pub type SetbrkdtintR = crate :: BitReader ; # [doc = "Field `SETBRKDTINT` writer - 0:0\\]
Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
pub type SetbrkdtintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETWAKEUPINT` reader - 1:1\\]
Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
pub type SetwakeupintR = crate :: BitReader ; # [doc = "Field `SETWAKEUPINT` writer - 1:1\\]
Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
pub type SetwakeupintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTIMEOUTINT` reader - 4:4\\]
Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
pub type SettimeoutintR = crate :: BitReader ; # [doc = "Field `SETTIMEOUTINT` writer - 4:4\\]
Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
pub type SettimeoutintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 5:5\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 5:5\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTOAWUSINT` reader - 6:6\\]
Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
pub type SettoawusintR = crate :: BitReader ; # [doc = "Field `SETTOAWUSINT` writer - 6:6\\]
Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
pub type SettoawusintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTOA3WUSINT` reader - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
pub type Settoa3wusintR = crate :: BitReader ; # [doc = "Field `SETTOA3WUSINT` writer - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
pub type Settoa3wusintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTXINT` reader - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
pub type SettxintR = crate :: BitReader ; # [doc = "Field `SETTXINT` writer - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
pub type SettxintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETRXINT` reader - 9:9\\]
Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
pub type SetrxintR = crate :: BitReader ; # [doc = "Field `SETRXINT` writer - 9:9\\]
Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
pub type SetrxintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 12:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 12:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SETIDINT` reader - 13:13\\]
Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
pub type SetidintR = crate :: BitReader ; # [doc = "Field `SETIDINT` writer - 13:13\\]
Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
pub type SetidintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 15:14\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 15:14\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SET_TX_DMA` reader - 16:16\\]
Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
pub type SetTxDmaR = crate :: BitReader ; # [doc = "Field `SET_TX_DMA` writer - 16:16\\]
Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
pub type SetTxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_DMA` reader - 17:17\\]
Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
pub type SetRxDmaR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA` writer - 17:17\\]
Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
pub type SetRxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_DMA_ALL` reader - 18:18\\]
Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
pub type SetRxDmaAllR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA_ALL` writer - 18:18\\]
Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
pub type SetRxDmaAllW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 23:19\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 23:19\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SETPEINT` reader - 24:24\\]
Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
pub type SetpeintR = crate :: BitReader ; # [doc = "Field `SETPEINT` writer - 24:24\\]
Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
pub type SetpeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETOEINT` reader - 25:25\\]
Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
pub type SetoeintR = crate :: BitReader ; # [doc = "Field `SETOEINT` writer - 25:25\\]
Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
pub type SetoeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETFEINT` reader - 26:26\\]
Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
pub type SetfeintR = crate :: BitReader ; # [doc = "Field `SETFEINT` writer - 26:26\\]
Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
pub type SetfeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETNREINT` reader - 27:27\\]
Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
pub type SetnreintR = crate :: BitReader ; # [doc = "Field `SETNREINT` writer - 27:27\\]
Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
pub type SetnreintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETISFEINT` reader - 28:28\\]
Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
pub type SetisfeintR = crate :: BitReader ; # [doc = "Field `SETISFEINT` writer - 28:28\\]
Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
pub type SetisfeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETCEINT` reader - 29:29\\]
Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
pub type SetceintR = crate :: BitReader ; # [doc = "Field `SETCEINT` writer - 29:29\\]
Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
pub type SetceintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETPBEINT` reader - 30:30\\]
Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
pub type SetpbeintR = crate :: BitReader ; # [doc = "Field `SETPBEINT` writer - 30:30\\]
Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
pub type SetpbeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETBEINT` reader - 31:31\\]
Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
pub type SetbeintR = crate :: BitReader ; # [doc = "Field `SETBEINT` writer - 31:31\\]
Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
pub type SetbeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
# [inline (always)]
pub fn setbrkdtint (& self) -> SetbrkdtintR { SetbrkdtintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
# [inline (always)]
pub fn setwakeupint (& self) -> SetwakeupintR { SetwakeupintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
# [inline (always)]
pub fn settimeoutint (& self) -> SettimeoutintR { SettimeoutintR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
# [inline (always)]
pub fn settoawusint (& self) -> SettoawusintR { SettoawusintR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
# [inline (always)]
pub fn settoa3wusint (& self) -> Settoa3wusintR { Settoa3wusintR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
# [inline (always)]
pub fn settxint (& self) -> SettxintR { SettxintR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
# [inline (always)]
pub fn setrxint (& self) -> SetrxintR { SetrxintR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bit 13 - 13:13\\]
Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
# [inline (always)]
pub fn setidint (& self) -> SetidintR { SetidintR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - 16:16\\]
Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
# [inline (always)]
pub fn set_tx_dma (& self) -> SetTxDmaR { SetTxDmaR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
# [inline (always)]
pub fn set_rx_dma (& self) -> SetRxDmaR { SetRxDmaR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
# [inline (always)]
pub fn set_rx_dma_all (& self) -> SetRxDmaAllR { SetRxDmaAllR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
# [inline (always)]
pub fn setpeint (& self) -> SetpeintR { SetpeintR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
# [inline (always)]
pub fn setoeint (& self) -> SetoeintR { SetoeintR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
# [inline (always)]
pub fn setfeint (& self) -> SetfeintR { SetfeintR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setnreint (& self) -> SetnreintR { SetnreintR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setisfeint (& self) -> SetisfeintR { SetisfeintR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setceint (& self) -> SetceintR { SetceintR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setpbeint (& self) -> SetpbeintR { SetpbeintR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setbeint (& self) -> SetbeintR { SetbeintR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn setbrkdtint (& mut self) -> SetbrkdtintW < ScisetintSpec > { SetbrkdtintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
# [inline (always)]
# [must_use]
pub fn setwakeupint (& mut self) -> SetwakeupintW < ScisetintSpec > { SetwakeupintW :: new (self , 1) } # [doc = "Bit 4 - 4:4\\]
Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn settimeoutint (& mut self) -> SettimeoutintW < ScisetintSpec > { SettimeoutintW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < ScisetintSpec > { Reserved1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn settoawusint (& mut self) -> SettoawusintW < ScisetintSpec > { SettoawusintW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn settoa3wusint (& mut self) -> Settoa3wusintW < ScisetintSpec > { Settoa3wusintW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
# [inline (always)]
# [must_use]
pub fn settxint (& mut self) -> SettxintW < ScisetintSpec > { SettxintW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
# [inline (always)]
# [must_use]
pub fn setrxint (& mut self) -> SetrxintW < ScisetintSpec > { SetrxintW :: new (self , 9) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < ScisetintSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 13 - 13:13\\]
Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
# [inline (always)]
# [must_use]
pub fn setidint (& mut self) -> SetidintW < ScisetintSpec > { SetidintW :: new (self , 13) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < ScisetintSpec > { Reserved3W :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
# [inline (always)]
# [must_use]
pub fn set_tx_dma (& mut self) -> SetTxDmaW < ScisetintSpec > { SetTxDmaW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
# [inline (always)]
# [must_use]
pub fn set_rx_dma (& mut self) -> SetRxDmaW < ScisetintSpec > { SetRxDmaW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
# [inline (always)]
# [must_use]
pub fn set_rx_dma_all (& mut self) -> SetRxDmaAllW < ScisetintSpec > { SetRxDmaAllW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < ScisetintSpec > { Reserved4W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
# [inline (always)]
# [must_use]
pub fn setpeint (& mut self) -> SetpeintW < ScisetintSpec > { SetpeintW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
# [inline (always)]
# [must_use]
pub fn setoeint (& mut self) -> SetoeintW < ScisetintSpec > { SetoeintW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
# [inline (always)]
# [must_use]
pub fn setfeint (& mut self) -> SetfeintW < ScisetintSpec > { SetfeintW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setnreint (& mut self) -> SetnreintW < ScisetintSpec > { SetnreintW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setisfeint (& mut self) -> SetisfeintW < ScisetintSpec > { SetisfeintW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setceint (& mut self) -> SetceintW < ScisetintSpec > { SetceintW :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setpbeint (& mut self) -> SetpbeintW < ScisetintSpec > { SetpbeintW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setbeint (& mut self) -> SetbeintW < ScisetintSpec > { SetbeintW :: new (self , 31) } } # [doc = "The SCISETINT register is used to enable the various interrupts available in the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScisetintSpec ; impl crate :: RegisterSpec for ScisetintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scisetint::R`](R) reader structure"]
impl crate :: Readable for ScisetintSpec { } # [doc = "`write(|w| ..)` method takes [`scisetint::W`](W) writer structure"]
impl crate :: Writable for ScisetintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCISETINT to value 0"]
impl crate :: Resettable for ScisetintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICLEARINT (rw) register accessor: The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciclearint`]
module"]
# [doc (alias = "SCICLEARINT")]
pub type Sciclearint = crate :: Reg < sciclearint :: SciclearintSpec > ; # [doc = "The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register."]
pub mod sciclearint { # [doc = "Register `SCICLEARINT` reader"]
pub type R = crate :: R < SciclearintSpec > ; # [doc = "Register `SCICLEARINT` writer"]
pub type W = crate :: W < SciclearintSpec > ; # [doc = "Field `CLRBRKDTINT` reader - 0:0\\]
Clear Break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only."]
pub type ClrbrkdtintR = crate :: BitReader ; # [doc = "Field `CLRBRKDTINT` writer - 0:0\\]
Clear Break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only."]
pub type ClrbrkdtintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRWAKEUPINT` reader - 1:1\\]
Clear Wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt."]
pub type ClrwakeupintR = crate :: BitReader ; # [doc = "Field `CLRWAKEUPINT` writer - 1:1\\]
Clear Wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt."]
pub type ClrwakeupintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTIMEOUTINT` reader - 4:4\\]
Clear Timeout interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout (LIN bus idle) interrupt. This field is writable in LIN mode only."]
pub type ClrtimeoutintR = crate :: BitReader ; # [doc = "Field `CLRTIMEOUTINT` writer - 4:4\\]
Clear Timeout interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout (LIN bus idle) interrupt. This field is writable in LIN mode only."]
pub type ClrtimeoutintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 5:5\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 5:5\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTOAWUSINT` reader - 6:6\\]
Clear Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only."]
pub type ClrtoawusintR = crate :: BitReader ; # [doc = "Field `CLRTOAWUSINT` writer - 6:6\\]
Clear Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only."]
pub type ClrtoawusintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTOA3WUSINT` reader - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only."]
pub type Clrtoa3wusintR = crate :: BitReader ; # [doc = "Field `CLRTOA3WUSINT` writer - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only."]
pub type Clrtoa3wusintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTXINT` reader - 8:8\\]
Clear Transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt."]
pub type ClrtxintR = crate :: BitReader ; # [doc = "Field `CLRTXINT` writer - 8:8\\]
Clear Transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt."]
pub type ClrtxintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRRXINT` reader - 9:9\\]
Clear Receiver interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt."]
pub type ClrrxintR = crate :: BitReader ; # [doc = "Field `CLRRXINT` writer - 9:9\\]
Clear Receiver interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt."]
pub type ClrrxintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 12:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 12:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CLRIDINT` reader - 13:13\\]
Clear Identifier interrupt. This bit is effective in LIN mode only. Setting this bit disables the ID interrupt."]
pub type ClridintR = crate :: BitReader ; # [doc = "Field `CLRIDINT` writer - 13:13\\]
Clear Identifier interrupt. This bit is effective in LIN mode only. Setting this bit disables the ID interrupt."]
pub type ClridintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 15:14\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 15:14\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLRTXDMA` reader - 16:16\\]
Clear transmit DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request."]
pub type ClrtxdmaR = crate :: BitReader ; # [doc = "Field `CLRTXDMA` writer - 16:16\\]
Clear transmit DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request."]
pub type ClrtxdmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRRXDMA` reader - 17:17\\]
Clear receiver DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request."]
pub type ClrrxdmaR = crate :: BitReader ; # [doc = "Field `CLRRXDMA` writer - 17:17\\]
Clear receiver DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request."]
pub type ClrrxdmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 18:18\\]
Reserved"]
pub type Reserved4R = crate :: BitReader ; # [doc = "Field `Reserved4` writer - 18:18\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved5` reader - 23:19\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `Reserved5` writer - 23:19\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLRPEINT` reader - 24:24\\]
Clear Parity Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt."]
pub type ClrpeintR = crate :: BitReader ; # [doc = "Field `CLRPEINT` writer - 24:24\\]
Clear Parity Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt."]
pub type ClrpeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLROEINT` reader - 25:25\\]
Clear Overrun-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt."]
pub type ClroeintR = crate :: BitReader ; # [doc = "Field `CLROEINT` writer - 25:25\\]
Clear Overrun-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt."]
pub type ClroeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRFEINT` reader - 26:26\\]
Clear Framing-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt."]
pub type ClrfeintR = crate :: BitReader ; # [doc = "Field `CLRFEINT` writer - 26:26\\]
Clear Framing-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt."]
pub type ClrfeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRNREINT` reader - 27:27\\]
Clear No-Reponse-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only."]
pub type ClrnreintR = crate :: BitReader ; # [doc = "Field `CLRNREINT` writer - 27:27\\]
Clear No-Reponse-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only."]
pub type ClrnreintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRISFEINT` reader - 28:28\\]
Clear Inconsistent-Sync-Field-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only."]
pub type ClrisfeintR = crate :: BitReader ; # [doc = "Field `CLRISFEINT` writer - 28:28\\]
Clear Inconsistent-Sync-Field-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only."]
pub type ClrisfeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRCEINT` reader - 29:29\\]
Clear checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only."]
pub type ClrceintR = crate :: BitReader ; # [doc = "Field `CLRCEINT` writer - 29:29\\]
Clear checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only."]
pub type ClrceintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRPBEINT` reader - 30:30\\]
Clear Physical Bus Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only."]
pub type ClrpbeintR = crate :: BitReader ; # [doc = "Field `CLRPBEINT` writer - 30:30\\]
Clear Physical Bus Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only."]
pub type ClrpbeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRBEINT` reader - 31:31\\]
Clear Bit Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only."]
pub type ClrbeintR = crate :: BitReader ; # [doc = "Field `CLRBEINT` writer - 31:31\\]
Clear Bit Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only."]
pub type ClrbeintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only."]
# [inline (always)]
pub fn clrbrkdtint (& self) -> ClrbrkdtintR { ClrbrkdtintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt."]
# [inline (always)]
pub fn clrwakeupint (& self) -> ClrwakeupintR { ClrwakeupintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Clear Timeout interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout (LIN bus idle) interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrtimeoutint (& self) -> ClrtimeoutintR { ClrtimeoutintR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Clear Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrtoawusint (& self) -> ClrtoawusintR { ClrtoawusintR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrtoa3wusint (& self) -> Clrtoa3wusintR { Clrtoa3wusintR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt."]
# [inline (always)]
pub fn clrtxint (& self) -> ClrtxintR { ClrtxintR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt."]
# [inline (always)]
pub fn clrrxint (& self) -> ClrrxintR { ClrrxintR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bit 13 - 13:13\\]
Clear Identifier interrupt. This bit is effective in LIN mode only. Setting this bit disables the ID interrupt."]
# [inline (always)]
pub fn clridint (& self) -> ClridintR { ClridintR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - 16:16\\]
Clear transmit DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request."]
# [inline (always)]
pub fn clrtxdma (& self) -> ClrtxdmaR { ClrtxdmaR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Clear receiver DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request."]
# [inline (always)]
pub fn clrrxdma (& self) -> ClrrxdmaR { ClrrxdmaR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt."]
# [inline (always)]
pub fn clrpeint (& self) -> ClrpeintR { ClrpeintR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt."]
# [inline (always)]
pub fn clroeint (& self) -> ClroeintR { ClroeintR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt."]
# [inline (always)]
pub fn clrfeint (& self) -> ClrfeintR { ClrfeintR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Clear No-Reponse-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrnreint (& self) -> ClrnreintR { ClrnreintR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Clear Inconsistent-Sync-Field-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrisfeint (& self) -> ClrisfeintR { ClrisfeintR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clear checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrceint (& self) -> ClrceintR { ClrceintR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Clear Physical Bus Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrpbeint (& self) -> ClrpbeintR { ClrpbeintR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Clear Bit Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrbeint (& self) -> ClrbeintR { ClrbeintR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn clrbrkdtint (& mut self) -> ClrbrkdtintW < SciclearintSpec > { ClrbrkdtintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt."]
# [inline (always)]
# [must_use]
pub fn clrwakeupint (& mut self) -> ClrwakeupintW < SciclearintSpec > { ClrwakeupintW :: new (self , 1) } # [doc = "Bit 4 - 4:4\\]
Clear Timeout interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout (LIN bus idle) interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrtimeoutint (& mut self) -> ClrtimeoutintW < SciclearintSpec > { ClrtimeoutintW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciclearintSpec > { Reserved1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Clear Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrtoawusint (& mut self) -> ClrtoawusintW < SciclearintSpec > { ClrtoawusintW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrtoa3wusint (& mut self) -> Clrtoa3wusintW < SciclearintSpec > { Clrtoa3wusintW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt."]
# [inline (always)]
# [must_use]
pub fn clrtxint (& mut self) -> ClrtxintW < SciclearintSpec > { ClrtxintW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt."]
# [inline (always)]
# [must_use]
pub fn clrrxint (& mut self) -> ClrrxintW < SciclearintSpec > { ClrrxintW :: new (self , 9) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciclearintSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 13 - 13:13\\]
Clear Identifier interrupt. This bit is effective in LIN mode only. Setting this bit disables the ID interrupt."]
# [inline (always)]
# [must_use]
pub fn clridint (& mut self) -> ClridintW < SciclearintSpec > { ClridintW :: new (self , 13) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciclearintSpec > { Reserved3W :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Clear transmit DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request."]
# [inline (always)]
# [must_use]
pub fn clrtxdma (& mut self) -> ClrtxdmaW < SciclearintSpec > { ClrtxdmaW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Clear receiver DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request."]
# [inline (always)]
# [must_use]
pub fn clrrxdma (& mut self) -> ClrrxdmaW < SciclearintSpec > { ClrrxdmaW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciclearintSpec > { Reserved4W :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < SciclearintSpec > { Reserved5W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt."]
# [inline (always)]
# [must_use]
pub fn clrpeint (& mut self) -> ClrpeintW < SciclearintSpec > { ClrpeintW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt."]
# [inline (always)]
# [must_use]
pub fn clroeint (& mut self) -> ClroeintW < SciclearintSpec > { ClroeintW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt."]
# [inline (always)]
# [must_use]
pub fn clrfeint (& mut self) -> ClrfeintW < SciclearintSpec > { ClrfeintW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Clear No-Reponse-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrnreint (& mut self) -> ClrnreintW < SciclearintSpec > { ClrnreintW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Clear Inconsistent-Sync-Field-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrisfeint (& mut self) -> ClrisfeintW < SciclearintSpec > { ClrisfeintW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clear checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrceint (& mut self) -> ClrceintW < SciclearintSpec > { ClrceintW :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Clear Physical Bus Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrpbeint (& mut self) -> ClrpbeintW < SciclearintSpec > { ClrpbeintW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Clear Bit Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrbeint (& mut self) -> ClrbeintW < SciclearintSpec > { ClrbeintW :: new (self , 31) } } # [doc = "The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciclearintSpec ; impl crate :: RegisterSpec for SciclearintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciclearint::R`](R) reader structure"]
impl crate :: Readable for SciclearintSpec { } # [doc = "`write(|w| ..)` method takes [`sciclearint::W`](W) writer structure"]
impl crate :: Writable for SciclearintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICLEARINT to value 0"]
impl crate :: Resettable for SciclearintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCISETINTLVL (rw) register accessor: The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line.\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetintlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetintlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scisetintlvl`]
module"]
# [doc (alias = "SCISETINTLVL")]
pub type Scisetintlvl = crate :: Reg < scisetintlvl :: ScisetintlvlSpec > ; # [doc = "The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line."]
pub mod scisetintlvl { # [doc = "Register `SCISETINTLVL` reader"]
pub type R = crate :: R < ScisetintlvlSpec > ; # [doc = "Register `SCISETINTLVL` writer"]
pub type W = crate :: W < ScisetintlvlSpec > ; # [doc = "Field `SETBRKDTINTLVL` reader - 0:0\\]
Set Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only."]
pub type SetbrkdtintlvlR = crate :: BitReader ; # [doc = "Field `SETBRKDTINTLVL` writer - 0:0\\]
Set Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only."]
pub type SetbrkdtintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETWAKEUPINTLVL` reader - 1:1\\]
Set Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line."]
pub type SetwakeupintlvlR = crate :: BitReader ; # [doc = "Field `SETWAKEUPINTLVL` writer - 1:1\\]
Set Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line."]
pub type SetwakeupintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTIMEOUTINTLVL` reader - 4:4\\]
Set Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SettimeoutintlvlR = crate :: BitReader ; # [doc = "Field `SETTIMEOUTINTLVL` writer - 4:4\\]
Set Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SettimeoutintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 5:5\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 5:5\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTOAWUSINTLVL` reader - 6:6\\]
Set Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SettoawusintlvlR = crate :: BitReader ; # [doc = "Field `SETTOAWUSINTLVL` writer - 6:6\\]
Set Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SettoawusintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTOA3WUSINTLVL` reader - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type Settoa3wusintlvlR = crate :: BitReader ; # [doc = "Field `SETTOA3WUSINTLVL` writer - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type Settoa3wusintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETTXINTLVL` reader - 8:8\\]
Set Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line."]
pub type SettxintlvlR = crate :: BitReader ; # [doc = "Field `SETTXINTLVL` writer - 8:8\\]
Set Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line."]
pub type SettxintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETRXINTOVO` reader - 9:9\\]
Set Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line."]
pub type SetrxintovoR = crate :: BitReader ; # [doc = "Field `SETRXINTOVO` writer - 9:9\\]
Set Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line."]
pub type SetrxintovoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 12:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 12:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SETIDINTLVL` reader - 13:13\\]
Set ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetidintlvlR = crate :: BitReader ; # [doc = "Field `SETIDINTLVL` writer - 13:13\\]
Set ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetidintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 15:14\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 15:14\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved4` reader - 17:16\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 17:16\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved5` reader - 18:18\\]
Reserved"]
pub type Reserved5R = crate :: BitReader ; # [doc = "Field `Reserved5` writer - 18:18\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved6` reader - 23:19\\]
Reserved"]
pub type Reserved6R = crate :: FieldReader ; # [doc = "Field `Reserved6` writer - 23:19\\]
Reserved"]
pub type Reserved6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SETPEINTLVL` reader - 24:24\\]
Set Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line."]
pub type SetpeintlvlR = crate :: BitReader ; # [doc = "Field `SETPEINTLVL` writer - 24:24\\]
Set Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line."]
pub type SetpeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETOEINTLVL` reader - 25:25\\]
Set Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line."]
pub type SetoeintlvlR = crate :: BitReader ; # [doc = "Field `SETOEINTLVL` writer - 25:25\\]
Set Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line."]
pub type SetoeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETFEINTLVL` reader - 26:26\\]
Set Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line."]
pub type SetfeintlvlR = crate :: BitReader ; # [doc = "Field `SETFEINTLVL` writer - 26:26\\]
Set Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line."]
pub type SetfeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETNREINTLVL` reader - 27:27\\]
Set No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetnreintlvlR = crate :: BitReader ; # [doc = "Field `SETNREINTLVL` writer - 27:27\\]
Set No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetnreintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETISFEINTLVL` reader - 28:28\\]
Set Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetisfeintlvlR = crate :: BitReader ; # [doc = "Field `SETISFEINTLVL` writer - 28:28\\]
Set Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetisfeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETCEINTLVL` reader - 29:29\\]
Set Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetceintlvlR = crate :: BitReader ; # [doc = "Field `SETCEINTLVL` writer - 29:29\\]
Set Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetceintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETPBEINTLVL` reader - 30:30\\]
Set Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetpbeintlvlR = crate :: BitReader ; # [doc = "Field `SETPBEINTLVL` writer - 30:30\\]
Set Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetpbeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETBEINTLVL` reader - 31:31\\]
Set Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetbeintlvlR = crate :: BitReader ; # [doc = "Field `SETBEINTLVL` writer - 31:31\\]
Set Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
pub type SetbeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Set Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only."]
# [inline (always)]
pub fn setbrkdtintlvl (& self) -> SetbrkdtintlvlR { SetbrkdtintlvlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line."]
# [inline (always)]
pub fn setwakeupintlvl (& self) -> SetwakeupintlvlR { SetwakeupintlvlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Set Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn settimeoutintlvl (& self) -> SettimeoutintlvlR { SettimeoutintlvlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Set Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn settoawusintlvl (& self) -> SettoawusintlvlR { SettoawusintlvlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn settoa3wusintlvl (& self) -> Settoa3wusintlvlR { Settoa3wusintlvlR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line."]
# [inline (always)]
pub fn settxintlvl (& self) -> SettxintlvlR { SettxintlvlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Set Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line."]
# [inline (always)]
pub fn setrxintovo (& self) -> SetrxintovoR { SetrxintovoR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bit 13 - 13:13\\]
Set ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setidintlvl (& self) -> SetidintlvlR { SetidintlvlR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved6 (& self) -> Reserved6R { Reserved6R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Set Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line."]
# [inline (always)]
pub fn setpeintlvl (& self) -> SetpeintlvlR { SetpeintlvlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Set Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line."]
# [inline (always)]
pub fn setoeintlvl (& self) -> SetoeintlvlR { SetoeintlvlR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Set Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line."]
# [inline (always)]
pub fn setfeintlvl (& self) -> SetfeintlvlR { SetfeintlvlR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Set No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setnreintlvl (& self) -> SetnreintlvlR { SetnreintlvlR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Set Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setisfeintlvl (& self) -> SetisfeintlvlR { SetisfeintlvlR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Set Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setceintlvl (& self) -> SetceintlvlR { SetceintlvlR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Set Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setpbeintlvl (& self) -> SetpbeintlvlR { SetpbeintlvlR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Set Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn setbeintlvl (& self) -> SetbeintlvlR { SetbeintlvlR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Set Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn setbrkdtintlvl (& mut self) -> SetbrkdtintlvlW < ScisetintlvlSpec > { SetbrkdtintlvlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line."]
# [inline (always)]
# [must_use]
pub fn setwakeupintlvl (& mut self) -> SetwakeupintlvlW < ScisetintlvlSpec > { SetwakeupintlvlW :: new (self , 1) } # [doc = "Bit 4 - 4:4\\]
Set Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn settimeoutintlvl (& mut self) -> SettimeoutintlvlW < ScisetintlvlSpec > { SettimeoutintlvlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < ScisetintlvlSpec > { Reserved1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Set Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn settoawusintlvl (& mut self) -> SettoawusintlvlW < ScisetintlvlSpec > { SettoawusintlvlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Set Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn settoa3wusintlvl (& mut self) -> Settoa3wusintlvlW < ScisetintlvlSpec > { Settoa3wusintlvlW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line."]
# [inline (always)]
# [must_use]
pub fn settxintlvl (& mut self) -> SettxintlvlW < ScisetintlvlSpec > { SettxintlvlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Set Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line."]
# [inline (always)]
# [must_use]
pub fn setrxintovo (& mut self) -> SetrxintovoW < ScisetintlvlSpec > { SetrxintovoW :: new (self , 9) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < ScisetintlvlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 13 - 13:13\\]
Set ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setidintlvl (& mut self) -> SetidintlvlW < ScisetintlvlSpec > { SetidintlvlW :: new (self , 13) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < ScisetintlvlSpec > { Reserved3W :: new (self , 14) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < ScisetintlvlSpec > { Reserved4W :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < ScisetintlvlSpec > { Reserved5W :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved6 (& mut self) -> Reserved6W < ScisetintlvlSpec > { Reserved6W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Set Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line."]
# [inline (always)]
# [must_use]
pub fn setpeintlvl (& mut self) -> SetpeintlvlW < ScisetintlvlSpec > { SetpeintlvlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Set Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line."]
# [inline (always)]
# [must_use]
pub fn setoeintlvl (& mut self) -> SetoeintlvlW < ScisetintlvlSpec > { SetoeintlvlW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Set Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line."]
# [inline (always)]
# [must_use]
pub fn setfeintlvl (& mut self) -> SetfeintlvlW < ScisetintlvlSpec > { SetfeintlvlW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Set No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setnreintlvl (& mut self) -> SetnreintlvlW < ScisetintlvlSpec > { SetnreintlvlW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Set Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setisfeintlvl (& mut self) -> SetisfeintlvlW < ScisetintlvlSpec > { SetisfeintlvlW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Set Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setceintlvl (& mut self) -> SetceintlvlW < ScisetintlvlSpec > { SetceintlvlW :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Set Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setpbeintlvl (& mut self) -> SetpbeintlvlW < ScisetintlvlSpec > { SetpbeintlvlW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Set Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn setbeintlvl (& mut self) -> SetbeintlvlW < ScisetintlvlSpec > { SetbeintlvlW :: new (self , 31) } } # [doc = "The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line.\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetintlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetintlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScisetintlvlSpec ; impl crate :: RegisterSpec for ScisetintlvlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scisetintlvl::R`](R) reader structure"]
impl crate :: Readable for ScisetintlvlSpec { } # [doc = "`write(|w| ..)` method takes [`scisetintlvl::W`](W) writer structure"]
impl crate :: Writable for ScisetintlvlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCISETINTLVL to value 0"]
impl crate :: Resettable for ScisetintlvlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICLEARINTLVL (rw) register accessor: The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearintlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearintlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciclearintlvl`]
module"]
# [doc (alias = "SCICLEARINTLVL")]
pub type Sciclearintlvl = crate :: Reg < sciclearintlvl :: SciclearintlvlSpec > ; # [doc = "The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line."]
pub mod sciclearintlvl { # [doc = "Register `SCICLEARINTLVL` reader"]
pub type R = crate :: R < SciclearintlvlSpec > ; # [doc = "Register `SCICLEARINTLVL` writer"]
pub type W = crate :: W < SciclearintlvlSpec > ; # [doc = "Field `CLRBRKDTINTLVL` reader - 0:0\\]
Clear Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only."]
pub type ClrbrkdtintlvlR = crate :: BitReader ; # [doc = "Field `CLRBRKDTINTLVL` writer - 0:0\\]
Clear Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only."]
pub type ClrbrkdtintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRWAKEUPINTLVL` reader - 1:1\\]
Clear Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line."]
pub type ClrwakeupintlvlR = crate :: BitReader ; # [doc = "Field `CLRWAKEUPINTLVL` writer - 1:1\\]
Clear Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line."]
pub type ClrwakeupintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTIMEOUTINTLVL` reader - 4:4\\]
Clear Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrtimeoutintlvlR = crate :: BitReader ; # [doc = "Field `CLRTIMEOUTINTLVL` writer - 4:4\\]
Clear Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrtimeoutintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 5:5\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 5:5\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTOAWUSINTLVL` reader - 6:6\\]
Clear Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrtoawusintlvlR = crate :: BitReader ; # [doc = "Field `CLRTOAWUSINTLVL` writer - 6:6\\]
Clear Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrtoawusintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTOA3WUSINTLVL` reader - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type Clrtoa3wusintlvlR = crate :: BitReader ; # [doc = "Field `CLRTOA3WUSINTLVL` writer - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type Clrtoa3wusintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRTXINTLVL` reader - 8:8\\]
Clear Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line."]
pub type ClrtxintlvlR = crate :: BitReader ; # [doc = "Field `CLRTXINTLVL` writer - 8:8\\]
Clear Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line."]
pub type ClrtxintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRRXINTLVL` reader - 9:9\\]
Clear Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line."]
pub type ClrrxintlvlR = crate :: BitReader ; # [doc = "Field `CLRRXINTLVL` writer - 9:9\\]
Clear Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line."]
pub type ClrrxintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 12:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 12:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CLRIDINTLVL` reader - 13:13\\]
Clear ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClridintlvlR = crate :: BitReader ; # [doc = "Field `CLRIDINTLVL` writer - 13:13\\]
Clear ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClridintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 15:14\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 15:14\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved4` reader - 17:16\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 17:16\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved5` reader - 18:18\\]
Reserved"]
pub type Reserved5R = crate :: BitReader ; # [doc = "Field `Reserved5` writer - 18:18\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved6` reader - 23:19\\]
Reserved"]
pub type Reserved6R = crate :: FieldReader ; # [doc = "Field `Reserved6` writer - 23:19\\]
Reserved"]
pub type Reserved6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLRPEINTLVL` reader - 24:24\\]
Clear Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line."]
pub type ClrpeintlvlR = crate :: BitReader ; # [doc = "Field `CLRPEINTLVL` writer - 24:24\\]
Clear Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line."]
pub type ClrpeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLROEINTLVL` reader - 25:25\\]
Clear Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line."]
pub type ClroeintlvlR = crate :: BitReader ; # [doc = "Field `CLROEINTLVL` writer - 25:25\\]
Clear Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line."]
pub type ClroeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRFEINTLVL` reader - 26:26\\]
Clear Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line."]
pub type ClrfeintlvlR = crate :: BitReader ; # [doc = "Field `CLRFEINTLVL` writer - 26:26\\]
Clear Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line."]
pub type ClrfeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRNREINTLVL` reader - 27:27\\]
Clear No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrnreintlvlR = crate :: BitReader ; # [doc = "Field `CLRNREINTLVL` writer - 27:27\\]
Clear No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrnreintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRISFEINTLVL` reader - 28:28\\]
Clear Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrisfeintlvlR = crate :: BitReader ; # [doc = "Field `CLRISFEINTLVL` writer - 28:28\\]
Clear Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrisfeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRCEINTLVL` reader - 29:29\\]
Clear Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrceintlvlR = crate :: BitReader ; # [doc = "Field `CLRCEINTLVL` writer - 29:29\\]
Clear Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrceintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRPBEINTLVL` reader - 30:30\\]
Clear Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrpbeintlvlR = crate :: BitReader ; # [doc = "Field `CLRPBEINTLVL` writer - 30:30\\]
Clear Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrpbeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLRBEINTLVL` reader - 31:31\\]
Clear Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrbeintlvlR = crate :: BitReader ; # [doc = "Field `CLRBEINTLVL` writer - 31:31\\]
Clear Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
pub type ClrbeintlvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only."]
# [inline (always)]
pub fn clrbrkdtintlvl (& self) -> ClrbrkdtintlvlR { ClrbrkdtintlvlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line."]
# [inline (always)]
pub fn clrwakeupintlvl (& self) -> ClrwakeupintlvlR { ClrwakeupintlvlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Clear Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrtimeoutintlvl (& self) -> ClrtimeoutintlvlR { ClrtimeoutintlvlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Clear Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrtoawusintlvl (& self) -> ClrtoawusintlvlR { ClrtoawusintlvlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrtoa3wusintlvl (& self) -> Clrtoa3wusintlvlR { Clrtoa3wusintlvlR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line."]
# [inline (always)]
pub fn clrtxintlvl (& self) -> ClrtxintlvlR { ClrtxintlvlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line."]
# [inline (always)]
pub fn clrrxintlvl (& self) -> ClrrxintlvlR { ClrrxintlvlR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bit 13 - 13:13\\]
Clear ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clridintlvl (& self) -> ClridintlvlR { ClridintlvlR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved6 (& self) -> Reserved6R { Reserved6R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line."]
# [inline (always)]
pub fn clrpeintlvl (& self) -> ClrpeintlvlR { ClrpeintlvlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line."]
# [inline (always)]
pub fn clroeintlvl (& self) -> ClroeintlvlR { ClroeintlvlR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line."]
# [inline (always)]
pub fn clrfeintlvl (& self) -> ClrfeintlvlR { ClrfeintlvlR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Clear No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrnreintlvl (& self) -> ClrnreintlvlR { ClrnreintlvlR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Clear Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrisfeintlvl (& self) -> ClrisfeintlvlR { ClrisfeintlvlR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clear Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrceintlvl (& self) -> ClrceintlvlR { ClrceintlvlR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Clear Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrpbeintlvl (& self) -> ClrpbeintlvlR { ClrpbeintlvlR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Clear Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
pub fn clrbeintlvl (& self) -> ClrbeintlvlR { ClrbeintlvlR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn clrbrkdtintlvl (& mut self) -> ClrbrkdtintlvlW < SciclearintlvlSpec > { ClrbrkdtintlvlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line."]
# [inline (always)]
# [must_use]
pub fn clrwakeupintlvl (& mut self) -> ClrwakeupintlvlW < SciclearintlvlSpec > { ClrwakeupintlvlW :: new (self , 1) } # [doc = "Bit 4 - 4:4\\]
Clear Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrtimeoutintlvl (& mut self) -> ClrtimeoutintlvlW < SciclearintlvlSpec > { ClrtimeoutintlvlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciclearintlvlSpec > { Reserved1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Clear Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrtoawusintlvl (& mut self) -> ClrtoawusintlvlW < SciclearintlvlSpec > { ClrtoawusintlvlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Clear Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrtoa3wusintlvl (& mut self) -> Clrtoa3wusintlvlW < SciclearintlvlSpec > { Clrtoa3wusintlvlW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line."]
# [inline (always)]
# [must_use]
pub fn clrtxintlvl (& mut self) -> ClrtxintlvlW < SciclearintlvlSpec > { ClrtxintlvlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line."]
# [inline (always)]
# [must_use]
pub fn clrrxintlvl (& mut self) -> ClrrxintlvlW < SciclearintlvlSpec > { ClrrxintlvlW :: new (self , 9) } # [doc = "Bits 10:12 - 12:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciclearintlvlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 13 - 13:13\\]
Clear ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clridintlvl (& mut self) -> ClridintlvlW < SciclearintlvlSpec > { ClridintlvlW :: new (self , 13) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciclearintlvlSpec > { Reserved3W :: new (self , 14) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciclearintlvlSpec > { Reserved4W :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < SciclearintlvlSpec > { Reserved5W :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved6 (& mut self) -> Reserved6W < SciclearintlvlSpec > { Reserved6W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line."]
# [inline (always)]
# [must_use]
pub fn clrpeintlvl (& mut self) -> ClrpeintlvlW < SciclearintlvlSpec > { ClrpeintlvlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line."]
# [inline (always)]
# [must_use]
pub fn clroeintlvl (& mut self) -> ClroeintlvlW < SciclearintlvlSpec > { ClroeintlvlW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line."]
# [inline (always)]
# [must_use]
pub fn clrfeintlvl (& mut self) -> ClrfeintlvlW < SciclearintlvlSpec > { ClrfeintlvlW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Clear No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrnreintlvl (& mut self) -> ClrnreintlvlW < SciclearintlvlSpec > { ClrnreintlvlW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Clear Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrisfeintlvl (& mut self) -> ClrisfeintlvlW < SciclearintlvlSpec > { ClrisfeintlvlW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clear Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrceintlvl (& mut self) -> ClrceintlvlW < SciclearintlvlSpec > { ClrceintlvlW :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Clear Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrpbeintlvl (& mut self) -> ClrpbeintlvlW < SciclearintlvlSpec > { ClrpbeintlvlW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Clear Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn clrbeintlvl (& mut self) -> ClrbeintlvlW < SciclearintlvlSpec > { ClrbeintlvlW :: new (self , 31) } } # [doc = "The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearintlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearintlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciclearintlvlSpec ; impl crate :: RegisterSpec for SciclearintlvlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciclearintlvl::R`](R) reader structure"]
impl crate :: Readable for SciclearintlvlSpec { } # [doc = "`write(|w| ..)` method takes [`sciclearintlvl::W`](W) writer structure"]
impl crate :: Writable for SciclearintlvlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICLEARINTLVL to value 0"]
impl crate :: Resettable for SciclearintlvlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIFLR (rw) register accessor: The SCIFLR register indicates the current status of the various interrupt sources of the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciflr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciflr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciflr`]
module"]
# [doc (alias = "SCIFLR")]
pub type Sciflr = crate :: Reg < sciflr :: SciflrSpec > ; # [doc = "The SCIFLR register indicates the current status of the various interrupt sources of the LIN module."]
pub mod sciflr { # [doc = "Register `SCIFLR` reader"]
pub type R = crate :: R < SciflrSpec > ; # [doc = "Register `SCIFLR` writer"]
pub type W = crate :: W < SciflrSpec > ; # [doc = "Field `BRKDT` reader - 0:0\\]
SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is cleared by the following: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - By writing a 1 to this bit. This bit is writable in SCI mode only."]
pub type BrkdtR = crate :: BitReader ; # [doc = "Field `BRKDT` writer - 0:0\\]
SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is cleared by the following: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - By writing a 1 to this bit. This bit is writable in SCI mode only."]
pub type BrkdtW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKEUP` reader - 1:1\\]
Wake-up flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT.1) is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit. This field is writable in LIN mode only."]
pub type WakeupR = crate :: BitReader ; # [doc = "Field `WAKEUP` writer - 1:1\\]
Wake-up flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT.1) is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit. This field is writable in LIN mode only."]
pub type WakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDLE` reader - 2:2\\]
SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state: - After a system reset - Setting the SWnRESET bit (SCIGCR1.7) - After coming out of power down This bit is writable in SCI mode only."]
pub type IdleR = crate :: BitReader ; # [doc = "Field `IDLE` writer - 2:2\\]
SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state: - After a system reset - Setting the SWnRESET bit (SCIGCR1.7) - After coming out of power down This bit is writable in SCI mode only."]
pub type IdleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BUSY` reader - 3:3\\]
Bus BUSY flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the BUSY bit is cleared. If SET WAKEUP INT is set and power down is requested while this bit is set, the SCI/LIN automatically prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is controlled directly by the SCI receiver but can be cleared by: - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset."]
pub type BusyR = crate :: BitReader ; # [doc = "Field `BUSY` writer - 3:3\\]
Bus BUSY flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the BUSY bit is cleared. If SET WAKEUP INT is set and power down is requested while this bit is set, the SCI/LIN automatically prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is controlled directly by the SCI receiver but can be cleared by: - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset."]
pub type BusyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT` reader - 4:4\\]
LIN Bus IDLE timeout flag. This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type TimeoutR = crate :: BitReader ; # [doc = "Field `TIMEOUT` writer - 4:4\\]
LIN Bus IDLE timeout flag. This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TOAWUS` reader - 6:6\\]
Timeout After Wakeup Signal flag. This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type ToawusR = crate :: BitReader ; # [doc = "Field `TOAWUS` writer - 6:6\\]
Timeout After Wakeup Signal flag. This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type ToawusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TOA3WUS` reader - 7:7\\]
Timeout After 3 Wakeup Signals flag. This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another round of wakeup signals. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type Toa3wusR = crate :: BitReader ; # [doc = "Field `TOA3WUS` writer - 7:7\\]
Timeout After 3 Wakeup Signals flag. This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another round of wakeup signals. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type Toa3wusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXRDY` reader - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s) register (SCITD in compatibility mode and LINTD0, LINTD1 in MBUF mode) is/are ready to get another character from a CPU write. In SCI compatibility mode, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte 0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer are shifted into the SCITXSHF register. This event can trigger a transmit DMA event if the DMA enable bit is set. This bit is set to 1 by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET (SCIGCR1.7) - System reset Note: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register. Note: The transmit interrupt request can be eliminated until the next series of data is written into the transmit buffers LINTD0 and LINTD1, by disaLINg the corresponding interrupt via the SCICLEARINT register or by disaLINg the transmitter via the TXENA bit (SCIGCR1.25=0)."]
pub type TxrdyR = crate :: BitReader ; # [doc = "Field `TXRDY` writer - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s) register (SCITD in compatibility mode and LINTD0, LINTD1 in MBUF mode) is/are ready to get another character from a CPU write. In SCI compatibility mode, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte 0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer are shifted into the SCITXSHF register. This event can trigger a transmit DMA event if the DMA enable bit is set. This bit is set to 1 by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET (SCIGCR1.7) - System reset Note: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register. Note: The transmit interrupt request can be eliminated until the next series of data is written into the transmit buffers LINTD0 and LINTD1, by disaLINg the corresponding interrupt via the SCICLEARINT register or by disaLINg the transmitter via the TXENA bit (SCIGCR1.25=0)."]
pub type TxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXRDY` reader - 9:9\\]
Receiver ready flag. In SCI compatibility mode, the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid frame is received in multibuffer mode, a valid frame being a message frame received with no errors. In non multibuffer mode RXRDY is set for each received byte and will be set for the last byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY flag bit is set if the interrupt-enable bit is set (SCISETINT.9). RXRDY is cleared by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET - System reset - Writing a 1 to this bit - Reading SCIRD in while in SCI compatibility mode - Reading last data byte RDy of the response in LIN mode Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register."]
pub type RxrdyR = crate :: BitReader ; # [doc = "Field `RXRDY` writer - 9:9\\]
Receiver ready flag. In SCI compatibility mode, the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid frame is received in multibuffer mode, a valid frame being a message frame received with no errors. In non multibuffer mode RXRDY is set for each received byte and will be set for the last byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY flag bit is set if the interrupt-enable bit is set (SCISETINT.9). RXRDY is cleared by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET - System reset - Writing a 1 to this bit - Reading SCIRD in while in SCI compatibility mode - Reading last data byte RDy of the response in LIN mode Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register."]
pub type RxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXWAKE` reader - 10:10\\]
SCI transmitter wakeup method select. This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset. TXWAKE is not cleared by the SWnRESET bit (SCIGCR1.7)."]
pub type TxwakeR = crate :: BitReader ; # [doc = "Field `TXWAKE` writer - 10:10\\]
SCI transmitter wakeup method select. This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset. TXWAKE is not cleared by the SWnRESET bit (SCIGCR1.7)."]
pub type TxwakeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXEMPTY` reader - 11:11\\]
Transmitter Empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register(s) (SCITD/TDy) and shift register (SCITXSHF). In multibuffer mode, this flag indicates the value of the TDx registers and shift register (SCITXSHF). In non multibuffer mode, this flag indicates the value of LINTD0 (byte) and shift register (SCITXSHF). This bit is set by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET bit (SCIGCR1.7) - System reset. Note: This bit does not cause an interrupt request."]
pub type TxemptyR = crate :: BitReader ; # [doc = "Field `TXEMPTY` writer - 11:11\\]
Transmitter Empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register(s) (SCITD/TDy) and shift register (SCITXSHF). In multibuffer mode, this flag indicates the value of the TDx registers and shift register (SCITXSHF). In non multibuffer mode, this flag indicates the value of LINTD0 (byte) and shift register (SCITXSHF). This bit is set by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET bit (SCIGCR1.7) - System reset. Note: This bit does not cause an interrupt request."]
pub type TxemptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXWAKE` reader - 12:12\\]
Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by: - RESET bit - Setting the SWnRESET bit (SCIGCR1.7) - System reset - Receipt of a data frame This bit is writable in SCI mode only."]
pub type RxwakeR = crate :: BitReader ; # [doc = "Field `RXWAKE` writer - 12:12\\]
Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by: - RESET bit - Setting the SWnRESET bit (SCIGCR1.7) - System reset - Receipt of a data frame This bit is writable in SCI mode only."]
pub type RxwakeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDTXFLAG` reader - 13:13\\]
Identifier On Transmit Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on a TX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - RESET bit (SCIGCR0.0) - Setting SWnRESET - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type IdtxflagR = crate :: BitReader ; # [doc = "Field `IDTXFLAG` writer - 13:13\\]
Identifier On Transmit Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on a TX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - RESET bit (SCIGCR0.0) - Setting SWnRESET - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type IdtxflagW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDRXFLAG` reader - 14:14\\]
Identifier On Receive Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on an RX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type IdrxflagR = crate :: BitReader ; # [doc = "Field `IDRXFLAG` writer - 14:14\\]
Identifier On Receive Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on an RX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
pub type IdrxflagW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 15:15\\]
reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 15:15\\]
reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 23:16\\]
reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 23:16\\]
reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `PE` reader - 24:24\\]
Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-line mode, only the data is used to calculate parity. An error is generated when a character is received with a mismatch between the number of 1s and its parity bit. For more information on parity checking, see the \"SCI Global Control Register (SCIGCR1)\" description. If the parity function is disabled (that is, SCIGCR1.2 = 0), the PE flag is disabled and read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE INT bit = 1. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reception of a new charcter (SCI-compatible mode) or frame (LIN mode) - Writing a 1 to this bit"]
pub type PeR = crate :: BitReader ; # [doc = "Field `PE` writer - 24:24\\]
Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-line mode, only the data is used to calculate parity. An error is generated when a character is received with a mismatch between the number of 1s and its parity bit. For more information on parity checking, see the \"SCI Global Control Register (SCIGCR1)\" description. If the parity function is disabled (that is, SCIGCR1.2 = 0), the PE flag is disabled and read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE INT bit = 1. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reception of a new charcter (SCI-compatible mode) or frame (LIN mode) - Writing a 1 to this bit"]
pub type PeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OE` reader - 25:25\\]
Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit is one. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit"]
pub type OeR = crate :: BitReader ; # [doc = "Field `OE` writer - 25:25\\]
Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit is one. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit"]
pub type OeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FE` reader - 26:26\\]
Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. Detection of a framing error causes the SCI to generate an error interrupt if the RXERR INT ENA bit is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new character (SCI-compatible mode), or frame (LIN mode) In multibuffer mode the frame is defined in the SCIFORMAT register."]
pub type FeR = crate :: BitReader ; # [doc = "Field `FE` writer - 26:26\\]
Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. Detection of a framing error causes the SCI to generate an error interrupt if the RXERR INT ENA bit is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new character (SCI-compatible mode), or frame (LIN mode) In multibuffer mode the frame is defined in the SCIFORMAT register."]
pub type FeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NRE` reader - 27:27\\]
No-Response Error Flag. This bit is effective in LIN mode only. This bit is set when there is no response to a masterΓÇÖs header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length (identifiers 0 to 61). This error is detected by the synchronizer of the module. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type NreR = crate :: BitReader ; # [doc = "Field `NRE` writer - 27:27\\]
No-Response Error Flag. This bit is effective in LIN mode only. This bit is set when there is no response to a masterΓÇÖs header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length (identifiers 0 to 61). This error is detected by the synchronizer of the module. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type NreW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ISFE` reader - 28:28\\]
Inconsistent Sync Field Error Flag. This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the \"Header Reception and Adaptive Baudrate\" section for more information. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type IsfeR = crate :: BitReader ; # [doc = "Field `ISFE` writer - 28:28\\]
Inconsistent Sync Field Error Flag. This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the \"Header Reception and Adaptive Baudrate\" section for more information. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type IsfeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CE` reader - 29:29\\]
Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type CeR = crate :: BitReader ; # [doc = "Field `CE` writer - 29:29\\]
Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type CeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PBE` reader - 30:30\\]
Physical Bus Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break Note: thie PBE will ony be flagged if no sync break can be generated. (because of a bus shortage to VBAT) or if no sync break delimeter can be generated (because of a bus shortage to GND). This field is writable in LIN mode only."]
pub type PbeR = crate :: BitReader ; # [doc = "Field `PBE` writer - 30:30\\]
Physical Bus Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break Note: thie PBE will ony be flagged if no sync break can be generated. (because of a bus shortage to VBAT) or if no sync break delimeter can be generated (because of a bus shortage to GND). This field is writable in LIN mode only."]
pub type PbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BE` reader - 31:31\\]
Bit Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type BeR = crate :: BitReader ; # [doc = "Field `BE` writer - 31:31\\]
Bit Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
pub type BeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is cleared by the following: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - By writing a 1 to this bit. This bit is writable in SCI mode only."]
# [inline (always)]
pub fn brkdt (& self) -> BrkdtR { BrkdtR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Wake-up flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT.1) is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit. This field is writable in LIN mode only."]
# [inline (always)]
pub fn wakeup (& self) -> WakeupR { WakeupR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state: - After a system reset - Setting the SWnRESET bit (SCIGCR1.7) - After coming out of power down This bit is writable in SCI mode only."]
# [inline (always)]
pub fn idle (& self) -> IdleR { IdleR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Bus BUSY flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the BUSY bit is cleared. If SET WAKEUP INT is set and power down is requested while this bit is set, the SCI/LIN automatically prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is controlled directly by the SCI receiver but can be cleared by: - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset."]
# [inline (always)]
pub fn busy (& self) -> BusyR { BusyR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
LIN Bus IDLE timeout flag. This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Timeout After Wakeup Signal flag. This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
pub fn toawus (& self) -> ToawusR { ToawusR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Timeout After 3 Wakeup Signals flag. This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another round of wakeup signals. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
pub fn toa3wus (& self) -> Toa3wusR { Toa3wusR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s) register (SCITD in compatibility mode and LINTD0, LINTD1 in MBUF mode) is/are ready to get another character from a CPU write. In SCI compatibility mode, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte 0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer are shifted into the SCITXSHF register. This event can trigger a transmit DMA event if the DMA enable bit is set. This bit is set to 1 by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET (SCIGCR1.7) - System reset Note: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register. Note: The transmit interrupt request can be eliminated until the next series of data is written into the transmit buffers LINTD0 and LINTD1, by disaLINg the corresponding interrupt via the SCICLEARINT register or by disaLINg the transmitter via the TXENA bit (SCIGCR1.25=0)."]
# [inline (always)]
pub fn txrdy (& self) -> TxrdyR { TxrdyR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Receiver ready flag. In SCI compatibility mode, the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid frame is received in multibuffer mode, a valid frame being a message frame received with no errors. In non multibuffer mode RXRDY is set for each received byte and will be set for the last byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY flag bit is set if the interrupt-enable bit is set (SCISETINT.9). RXRDY is cleared by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET - System reset - Writing a 1 to this bit - Reading SCIRD in while in SCI compatibility mode - Reading last data byte RDy of the response in LIN mode Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register."]
# [inline (always)]
pub fn rxrdy (& self) -> RxrdyR { RxrdyR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
SCI transmitter wakeup method select. This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset. TXWAKE is not cleared by the SWnRESET bit (SCIGCR1.7)."]
# [inline (always)]
pub fn txwake (& self) -> TxwakeR { TxwakeR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Transmitter Empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register(s) (SCITD/TDy) and shift register (SCITXSHF). In multibuffer mode, this flag indicates the value of the TDx registers and shift register (SCITXSHF). In non multibuffer mode, this flag indicates the value of LINTD0 (byte) and shift register (SCITXSHF). This bit is set by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET bit (SCIGCR1.7) - System reset. Note: This bit does not cause an interrupt request."]
# [inline (always)]
pub fn txempty (& self) -> TxemptyR { TxemptyR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by: - RESET bit - Setting the SWnRESET bit (SCIGCR1.7) - System reset - Receipt of a data frame This bit is writable in SCI mode only."]
# [inline (always)]
pub fn rxwake (& self) -> RxwakeR { RxwakeR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Identifier On Transmit Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on a TX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - RESET bit (SCIGCR0.0) - Setting SWnRESET - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
pub fn idtxflag (& self) -> IdtxflagR { IdtxflagR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Identifier On Receive Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on an RX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
pub fn idrxflag (& self) -> IdrxflagR { IdrxflagR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - 23:16\\]
reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 24 - 24:24\\]
Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-line mode, only the data is used to calculate parity. An error is generated when a character is received with a mismatch between the number of 1s and its parity bit. For more information on parity checking, see the \"SCI Global Control Register (SCIGCR1)\" description. If the parity function is disabled (that is, SCIGCR1.2 = 0), the PE flag is disabled and read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE INT bit = 1. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reception of a new charcter (SCI-compatible mode) or frame (LIN mode) - Writing a 1 to this bit"]
# [inline (always)]
pub fn pe (& self) -> PeR { PeR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit is one. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit"]
# [inline (always)]
pub fn oe (& self) -> OeR { OeR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. Detection of a framing error causes the SCI to generate an error interrupt if the RXERR INT ENA bit is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new character (SCI-compatible mode), or frame (LIN mode) In multibuffer mode the frame is defined in the SCIFORMAT register."]
# [inline (always)]
pub fn fe (& self) -> FeR { FeR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
No-Response Error Flag. This bit is effective in LIN mode only. This bit is set when there is no response to a masterΓÇÖs header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length (identifiers 0 to 61). This error is detected by the synchronizer of the module. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
pub fn nre (& self) -> NreR { NreR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Inconsistent Sync Field Error Flag. This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the \"Header Reception and Adaptive Baudrate\" section for more information. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
pub fn isfe (& self) -> IsfeR { IsfeR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
pub fn ce (& self) -> CeR { CeR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Physical Bus Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break Note: thie PBE will ony be flagged if no sync break can be generated. (because of a bus shortage to VBAT) or if no sync break delimeter can be generated (because of a bus shortage to GND). This field is writable in LIN mode only."]
# [inline (always)]
pub fn pbe (& self) -> PbeR { PbeR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Bit Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
pub fn be (& self) -> BeR { BeR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is cleared by the following: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - By writing a 1 to this bit. This bit is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn brkdt (& mut self) -> BrkdtW < SciflrSpec > { BrkdtW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Wake-up flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT.1) is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit. This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn wakeup (& mut self) -> WakeupW < SciflrSpec > { WakeupW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state: - After a system reset - Setting the SWnRESET bit (SCIGCR1.7) - After coming out of power down This bit is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn idle (& mut self) -> IdleW < SciflrSpec > { IdleW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Bus BUSY flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the BUSY bit is cleared. If SET WAKEUP INT is set and power down is requested while this bit is set, the SCI/LIN automatically prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is controlled directly by the SCI receiver but can be cleared by: - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset."]
# [inline (always)]
# [must_use]
pub fn busy (& mut self) -> BusyW < SciflrSpec > { BusyW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
LIN Bus IDLE timeout flag. This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < SciflrSpec > { TimeoutW :: new (self , 4) } # [doc = "Bit 6 - 6:6\\]
Timeout After Wakeup Signal flag. This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn toawus (& mut self) -> ToawusW < SciflrSpec > { ToawusW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Timeout After 3 Wakeup Signals flag. This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another round of wakeup signals. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn toa3wus (& mut self) -> Toa3wusW < SciflrSpec > { Toa3wusW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s) register (SCITD in compatibility mode and LINTD0, LINTD1 in MBUF mode) is/are ready to get another character from a CPU write. In SCI compatibility mode, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte 0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer are shifted into the SCITXSHF register. This event can trigger a transmit DMA event if the DMA enable bit is set. This bit is set to 1 by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET (SCIGCR1.7) - System reset Note: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register. Note: The transmit interrupt request can be eliminated until the next series of data is written into the transmit buffers LINTD0 and LINTD1, by disaLINg the corresponding interrupt via the SCICLEARINT register or by disaLINg the transmitter via the TXENA bit (SCIGCR1.25=0)."]
# [inline (always)]
# [must_use]
pub fn txrdy (& mut self) -> TxrdyW < SciflrSpec > { TxrdyW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Receiver ready flag. In SCI compatibility mode, the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid frame is received in multibuffer mode, a valid frame being a message frame received with no errors. In non multibuffer mode RXRDY is set for each received byte and will be set for the last byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY flag bit is set if the interrupt-enable bit is set (SCISETINT.9). RXRDY is cleared by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET - System reset - Writing a 1 to this bit - Reading SCIRD in while in SCI compatibility mode - Reading last data byte RDy of the response in LIN mode Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register."]
# [inline (always)]
# [must_use]
pub fn rxrdy (& mut self) -> RxrdyW < SciflrSpec > { RxrdyW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
SCI transmitter wakeup method select. This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset. TXWAKE is not cleared by the SWnRESET bit (SCIGCR1.7)."]
# [inline (always)]
# [must_use]
pub fn txwake (& mut self) -> TxwakeW < SciflrSpec > { TxwakeW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Transmitter Empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register(s) (SCITD/TDy) and shift register (SCITXSHF). In multibuffer mode, this flag indicates the value of the TDx registers and shift register (SCITXSHF). In non multibuffer mode, this flag indicates the value of LINTD0 (byte) and shift register (SCITXSHF). This bit is set by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET bit (SCIGCR1.7) - System reset. Note: This bit does not cause an interrupt request."]
# [inline (always)]
# [must_use]
pub fn txempty (& mut self) -> TxemptyW < SciflrSpec > { TxemptyW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by: - RESET bit - Setting the SWnRESET bit (SCIGCR1.7) - System reset - Receipt of a data frame This bit is writable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn rxwake (& mut self) -> RxwakeW < SciflrSpec > { RxwakeW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Identifier On Transmit Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on a TX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - RESET bit (SCIGCR0.0) - Setting SWnRESET - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn idtxflag (& mut self) -> IdtxflagW < SciflrSpec > { IdtxflagW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Identifier On Receive Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the \"Message Filtering and Validation\" section for more details. When this flag is set it indicates that a new valid identifier has been received on an RX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn idrxflag (& mut self) -> IdrxflagW < SciflrSpec > { IdrxflagW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciflrSpec > { Reserved1W :: new (self , 15) } # [doc = "Bits 16:23 - 23:16\\]
reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciflrSpec > { Reserved2W :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-line mode, only the data is used to calculate parity. An error is generated when a character is received with a mismatch between the number of 1s and its parity bit. For more information on parity checking, see the \"SCI Global Control Register (SCIGCR1)\" description. If the parity function is disabled (that is, SCIGCR1.2 = 0), the PE flag is disabled and read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE INT bit = 1. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reception of a new charcter (SCI-compatible mode) or frame (LIN mode) - Writing a 1 to this bit"]
# [inline (always)]
# [must_use]
pub fn pe (& mut self) -> PeW < SciflrSpec > { PeW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit is one. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit"]
# [inline (always)]
# [must_use]
pub fn oe (& mut self) -> OeW < SciflrSpec > { OeW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. Detection of a framing error causes the SCI to generate an error interrupt if the RXERR INT ENA bit is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new character (SCI-compatible mode), or frame (LIN mode) In multibuffer mode the frame is defined in the SCIFORMAT register."]
# [inline (always)]
# [must_use]
pub fn fe (& mut self) -> FeW < SciflrSpec > { FeW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
No-Response Error Flag. This bit is effective in LIN mode only. This bit is set when there is no response to a masterΓÇÖs header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length (identifiers 0 to 61). This error is detected by the synchronizer of the module. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn nre (& mut self) -> NreW < SciflrSpec > { NreW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Inconsistent Sync Field Error Flag. This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the \"Header Reception and Adaptive Baudrate\" section for more information. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn isfe (& mut self) -> IsfeW < SciflrSpec > { IsfeW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn ce (& mut self) -> CeW < SciflrSpec > { CeW :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Physical Bus Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break Note: thie PBE will ony be flagged if no sync break can be generated. (because of a bus shortage to VBAT) or if no sync break delimeter can be generated (because of a bus shortage to GND). This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn pbe (& mut self) -> PbeW < SciflrSpec > { PbeW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Bit Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn be (& mut self) -> BeW < SciflrSpec > { BeW :: new (self , 31) } } # [doc = "The SCIFLR register indicates the current status of the various interrupt sources of the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciflr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciflr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciflrSpec ; impl crate :: RegisterSpec for SciflrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciflr::R`](R) reader structure"]
impl crate :: Readable for SciflrSpec { } # [doc = "`write(|w| ..)` method takes [`sciflr::W`](W) writer structure"]
impl crate :: Writable for SciflrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIFLR to value 0"]
impl crate :: Resettable for SciflrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIINTVECT0 (rw) register accessor: The SCIINTVECT0 register indicates the offset for the INT0 interrupt line.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciintvect0`]
module"]
# [doc (alias = "SCIINTVECT0")]
pub type Sciintvect0 = crate :: Reg < sciintvect0 :: Sciintvect0Spec > ; # [doc = "The SCIINTVECT0 register indicates the offset for the INT0 interrupt line."]
pub mod sciintvect0 { # [doc = "Register `SCIINTVECT0` reader"]
pub type R = crate :: R < Sciintvect0Spec > ; # [doc = "Register `SCIINTVECT0` writer"]
pub type W = crate :: W < Sciintvect0Spec > ; # [doc = "Field `INTVECT0` reader - 4:0\\]
Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
pub type Intvect0R = crate :: FieldReader ; # [doc = "Field `INTVECT0` writer - 4:0\\]
Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
pub type Intvect0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
# [inline (always)]
pub fn intvect0 (& self) -> Intvect0R { Intvect0R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
# [inline (always)]
# [must_use]
pub fn intvect0 (& mut self) -> Intvect0W < Sciintvect0Spec > { Intvect0W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Sciintvect0Spec > { Reserved1W :: new (self , 16) } } # [doc = "The SCIINTVECT0 register indicates the offset for the INT0 interrupt line.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sciintvect0Spec ; impl crate :: RegisterSpec for Sciintvect0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciintvect0::R`](R) reader structure"]
impl crate :: Readable for Sciintvect0Spec { } # [doc = "`write(|w| ..)` method takes [`sciintvect0::W`](W) writer structure"]
impl crate :: Writable for Sciintvect0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIINTVECT0 to value 0"]
impl crate :: Resettable for Sciintvect0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIINTVECT1 (rw) register accessor: The SCIINTVECT1 register indicates the offset for the INT1 interrupt line.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciintvect1`]
module"]
# [doc (alias = "SCIINTVECT1")]
pub type Sciintvect1 = crate :: Reg < sciintvect1 :: Sciintvect1Spec > ; # [doc = "The SCIINTVECT1 register indicates the offset for the INT1 interrupt line."]
pub mod sciintvect1 { # [doc = "Register `SCIINTVECT1` reader"]
pub type R = crate :: R < Sciintvect1Spec > ; # [doc = "Register `SCIINTVECT1` writer"]
pub type W = crate :: W < Sciintvect1Spec > ; # [doc = "Field `INTVECT1` reader - 4:0\\]
Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
pub type Intvect1R = crate :: FieldReader ; # [doc = "Field `INTVECT1` writer - 4:0\\]
Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
pub type Intvect1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
# [inline (always)]
pub fn intvect1 (& self) -> Intvect1R { Intvect1R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register)."]
# [inline (always)]
# [must_use]
pub fn intvect1 (& mut self) -> Intvect1W < Sciintvect1Spec > { Intvect1W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Sciintvect1Spec > { Reserved1W :: new (self , 16) } } # [doc = "The SCIINTVECT1 register indicates the offset for the INT1 interrupt line.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sciintvect1Spec ; impl crate :: RegisterSpec for Sciintvect1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciintvect1::R`](R) reader structure"]
impl crate :: Readable for Sciintvect1Spec { } # [doc = "`write(|w| ..)` method takes [`sciintvect1::W`](W) writer structure"]
impl crate :: Writable for Sciintvect1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIINTVECT1 to value 0"]
impl crate :: Resettable for Sciintvect1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIFORMAT (rw) register accessor: The SCIFORMAT register is used to set up the character and frame lengths.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciformat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciformat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciformat`]
module"]
# [doc (alias = "SCIFORMAT")]
pub type Sciformat = crate :: Reg < sciformat :: SciformatSpec > ; # [doc = "The SCIFORMAT register is used to set up the character and frame lengths."]
pub mod sciformat { # [doc = "Register `SCIFORMAT` reader"]
pub type R = crate :: R < SciformatSpec > ; # [doc = "Register `SCIFORMAT` writer"]
pub type W = crate :: W < SciformatSpec > ; # [doc = "Field `CHAR` reader - 2:0\\]
Character length control bits. These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode, when data of fewer than eight bits in length is received, it is left justified in SCIRD/RDy and padded with trailing zeros. Data read from the SCIRD should be shifted by software to make the received data right justified. Note: Data written to the SCITD should be right justified but does not need to be padded with leading zeros. These bits are witable in SCI mode only."]
pub type CharR = crate :: FieldReader ; # [doc = "Field `CHAR` writer - 2:0\\]
Character length control bits. These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode, when data of fewer than eight bits in length is received, it is left justified in SCIRD/RDy and padded with trailing zeros. Data read from the SCIRD should be shifted by software to make the received data right justified. Note: Data written to the SCITD should be right justified but does not need to be padded with leading zeros. These bits are witable in SCI mode only."]
pub type CharW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `LENGTH` reader - 18:16\\]
Frame length control bits. In LIN mode, these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode, these bits indicate the number of characters. When these bits are used to indicate LIN response length (SCIGCR1\\[0\\]
= 1), then when there is an ID RX match, this value should be updated with the expected length of the response. In buffered SCI mode, these bits indicate the number of characters with SCIFORMAT\\[2:0\\]
bits per character. i.e. these bits indicate the transmitter/receiver format for the number of characters: 1 to 8. There can be up to eight characters with eight bits each."]
pub type LengthR = crate :: FieldReader ; # [doc = "Field `LENGTH` writer - 18:16\\]
Frame length control bits. In LIN mode, these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode, these bits indicate the number of characters. When these bits are used to indicate LIN response length (SCIGCR1\\[0\\]
= 1), then when there is an ID RX match, this value should be updated with the expected length of the response. In buffered SCI mode, these bits indicate the number of characters with SCIFORMAT\\[2:0\\]
bits per character. i.e. these bits indicate the transmitter/receiver format for the number of characters: 1 to 8. There can be up to eight characters with eight bits each."]
pub type LengthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `Reserved1` reader - 31:19\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:19\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Character length control bits. These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode, when data of fewer than eight bits in length is received, it is left justified in SCIRD/RDy and padded with trailing zeros. Data read from the SCIRD should be shifted by software to make the received data right justified. Note: Data written to the SCITD should be right justified but does not need to be padded with leading zeros. These bits are witable in SCI mode only."]
# [inline (always)]
pub fn char (& self) -> CharR { CharR :: new ((self . bits & 7) as u8) } # [doc = "Bits 16:18 - 18:16\\]
Frame length control bits. In LIN mode, these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode, these bits indicate the number of characters. When these bits are used to indicate LIN response length (SCIGCR1\\[0\\]
= 1), then when there is an ID RX match, this value should be updated with the expected length of the response. In buffered SCI mode, these bits indicate the number of characters with SCIFORMAT\\[2:0\\]
bits per character. i.e. these bits indicate the transmitter/receiver format for the number of characters: 1 to 8. There can be up to eight characters with eight bits each."]
# [inline (always)]
pub fn length (& self) -> LengthR { LengthR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bits 19:31 - 31:19\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Character length control bits. These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode, when data of fewer than eight bits in length is received, it is left justified in SCIRD/RDy and padded with trailing zeros. Data read from the SCIRD should be shifted by software to make the received data right justified. Note: Data written to the SCITD should be right justified but does not need to be padded with leading zeros. These bits are witable in SCI mode only."]
# [inline (always)]
# [must_use]
pub fn char (& mut self) -> CharW < SciformatSpec > { CharW :: new (self , 0) } # [doc = "Bits 16:18 - 18:16\\]
Frame length control bits. In LIN mode, these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode, these bits indicate the number of characters. When these bits are used to indicate LIN response length (SCIGCR1\\[0\\]
= 1), then when there is an ID RX match, this value should be updated with the expected length of the response. In buffered SCI mode, these bits indicate the number of characters with SCIFORMAT\\[2:0\\]
bits per character. i.e. these bits indicate the transmitter/receiver format for the number of characters: 1 to 8. There can be up to eight characters with eight bits each."]
# [inline (always)]
# [must_use]
pub fn length (& mut self) -> LengthW < SciformatSpec > { LengthW :: new (self , 16) } # [doc = "Bits 19:31 - 31:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciformatSpec > { Reserved1W :: new (self , 19) } } # [doc = "The SCIFORMAT register is used to set up the character and frame lengths.\n\nYou can [`read`](crate::Reg::read) this register and get [`sciformat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciformat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciformatSpec ; impl crate :: RegisterSpec for SciformatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciformat::R`](R) reader structure"]
impl crate :: Readable for SciformatSpec { } # [doc = "`write(|w| ..)` method takes [`sciformat::W`](W) writer structure"]
impl crate :: Writable for SciformatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIFORMAT to value 0"]
impl crate :: Resettable for SciformatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BRSR (rw) register accessor: The BRSR register is used to configure the baud rate of the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`brsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brsr`]
module"]
# [doc (alias = "BRSR")]
pub type Brsr = crate :: Reg < brsr :: BrsrSpec > ; # [doc = "The BRSR register is used to configure the baud rate of the LIN module."]
pub mod brsr { # [doc = "Register `BRSR` reader"]
pub type R = crate :: R < BrsrSpec > ; # [doc = "Register `BRSR` writer"]
pub type W = crate :: W < BrsrSpec > ; # [doc = "Field `SCI_LIN_PSL` reader - 15:0\\]
PRESCALER P (Low Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
pub type SciLinPslR = crate :: FieldReader < u16 > ; # [doc = "Field `SCI_LIN_PSL` writer - 15:0\\]
PRESCALER P (Low Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
pub type SciLinPslW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `SCI_LIN_PSH` reader - 23:16\\]
PRESCALER P (High Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
pub type SciLinPshR = crate :: FieldReader ; # [doc = "Field `SCI_LIN_PSH` writer - 23:16\\]
PRESCALER P (High Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
pub type SciLinPshW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `M` reader - 27:24\\]
SCI/LIN 4-bit Fractional Divider Selection. (M) These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module, and they are a fractional part for the baud rate specification. The M divider allows fine-tuning of the baud rate over the P prescaler with 15 additional intermediate values for each of the P integer values."]
pub type MR = crate :: FieldReader ; # [doc = "Field `M` writer - 27:24\\]
SCI/LIN 4-bit Fractional Divider Selection. (M) These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module, and they are a fractional part for the baud rate specification. The M divider allows fine-tuning of the baud rate over the P prescaler with 15 additional intermediate values for each of the P integer values."]
pub type MW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `U` reader - 30:28\\]
Superfractional Divider Selection. (U) These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider values. See the Superfractional Divider section for more details."]
pub type UR = crate :: FieldReader ; # [doc = "Field `U` writer - 30:28\\]
Superfractional Divider Selection. (U) These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider values. See the Superfractional Divider section for more details."]
pub type UW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
PRESCALER P (Low Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
# [inline (always)]
pub fn sci_lin_psl (& self) -> SciLinPslR { SciLinPslR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:23 - 23:16\\]
PRESCALER P (High Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
# [inline (always)]
pub fn sci_lin_psh (& self) -> SciLinPshR { SciLinPshR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:27 - 27:24\\]
SCI/LIN 4-bit Fractional Divider Selection. (M) These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module, and they are a fractional part for the baud rate specification. The M divider allows fine-tuning of the baud rate over the P prescaler with 15 additional intermediate values for each of the P integer values."]
# [inline (always)]
pub fn m (& self) -> MR { MR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:30 - 30:28\\]
Superfractional Divider Selection. (U) These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider values. See the Superfractional Divider section for more details."]
# [inline (always)]
pub fn u (& self) -> UR { UR :: new (((self . bits >> 28) & 7) as u8) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
PRESCALER P (Low Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
# [inline (always)]
# [must_use]
pub fn sci_lin_psl (& mut self) -> SciLinPslW < BrsrSpec > { SciLinPslW :: new (self , 0) } # [doc = "Bits 16:23 - 23:16\\]
PRESCALER P (High Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection."]
# [inline (always)]
# [must_use]
pub fn sci_lin_psh (& mut self) -> SciLinPshW < BrsrSpec > { SciLinPshW :: new (self , 16) } # [doc = "Bits 24:27 - 27:24\\]
SCI/LIN 4-bit Fractional Divider Selection. (M) These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module, and they are a fractional part for the baud rate specification. The M divider allows fine-tuning of the baud rate over the P prescaler with 15 additional intermediate values for each of the P integer values."]
# [inline (always)]
# [must_use]
pub fn m (& mut self) -> MW < BrsrSpec > { MW :: new (self , 24) } # [doc = "Bits 28:30 - 30:28\\]
Superfractional Divider Selection. (U) These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider values. See the Superfractional Divider section for more details."]
# [inline (always)]
# [must_use]
pub fn u (& mut self) -> UW < BrsrSpec > { UW :: new (self , 28) } } # [doc = "The BRSR register is used to configure the baud rate of the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`brsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BrsrSpec ; impl crate :: RegisterSpec for BrsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`brsr::R`](R) reader structure"]
impl crate :: Readable for BrsrSpec { } # [doc = "`write(|w| ..)` method takes [`brsr::W`](W) writer structure"]
impl crate :: Writable for BrsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BRSR to value 0"]
impl crate :: Resettable for BrsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIED (rw) register accessor: The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator.\n\nYou can [`read`](crate::Reg::read) this register and get [`scied::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scied::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scied`]
module"]
# [doc (alias = "SCIED")]
pub type Scied = crate :: Reg < scied :: SciedSpec > ; # [doc = "The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator."]
pub mod scied { # [doc = "Register `SCIED` reader"]
pub type R = crate :: R < SciedSpec > ; # [doc = "Register `SCIED` writer"]
pub type W = crate :: W < SciedSpec > ; # [doc = "Field `ED` reader - 7:0\\]
Receiver Emulation Data. This bit is effective in SCI-compatible mode only. Reading SCIED(7ΓÇô0) does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag."]
pub type EdR = crate :: FieldReader ; # [doc = "Field `ED` writer - 7:0\\]
Receiver Emulation Data. This bit is effective in SCI-compatible mode only. Reading SCIED(7ΓÇô0) does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag."]
pub type EdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Receiver Emulation Data. This bit is effective in SCI-compatible mode only. Reading SCIED(7ΓÇô0) does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag."]
# [inline (always)]
pub fn ed (& self) -> EdR { EdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Receiver Emulation Data. This bit is effective in SCI-compatible mode only. Reading SCIED(7ΓÇô0) does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag."]
# [inline (always)]
# [must_use]
pub fn ed (& mut self) -> EdW < SciedSpec > { EdW :: new (self , 0) } } # [doc = "The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator.\n\nYou can [`read`](crate::Reg::read) this register and get [`scied::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scied::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciedSpec ; impl crate :: RegisterSpec for SciedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scied::R`](R) reader structure"]
impl crate :: Readable for SciedSpec { } # [doc = "`write(|w| ..)` method takes [`scied::W`](W) writer structure"]
impl crate :: Writable for SciedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIED to value 0"]
impl crate :: Resettable for SciedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIRD (rw) register accessor: The SCIRD register is where received data is stored and can be read from.\n\nYou can [`read`](crate::Reg::read) this register and get [`scird::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scird::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scird`]
module"]
# [doc (alias = "SCIRD")]
pub type Scird = crate :: Reg < scird :: ScirdSpec > ; # [doc = "The SCIRD register is where received data is stored and can be read from."]
pub mod scird { # [doc = "Register `SCIRD` reader"]
pub type R = crate :: R < ScirdSpec > ; # [doc = "Register `SCIRD` writer"]
pub type W = crate :: W < ScirdSpec > ; # [doc = "Field `RD` reader - 7:0\\]
Received Data. This bit is effective in SCI-compatible mode only. When a frame has been completely received, the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs, the RXRDY flag is set and a receive interrupt is generated if RX INT ENA (SCISETINT0.9) is set. When the data is read from SCIRD, the RXRDY flag is automatically cleared. When the SCI receives data that is fewer than eight bits in length, it loads the data into this register in a left justified format padded with trailing zeros. Therefore, your software should perform a logical shift on the data by the correct number of positions to make it right justified."]
pub type RdR = crate :: FieldReader ; # [doc = "Field `RD` writer - 7:0\\]
Received Data. This bit is effective in SCI-compatible mode only. When a frame has been completely received, the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs, the RXRDY flag is set and a receive interrupt is generated if RX INT ENA (SCISETINT0.9) is set. When the data is read from SCIRD, the RXRDY flag is automatically cleared. When the SCI receives data that is fewer than eight bits in length, it loads the data into this register in a left justified format padded with trailing zeros. Therefore, your software should perform a logical shift on the data by the correct number of positions to make it right justified."]
pub type RdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Received Data. This bit is effective in SCI-compatible mode only. When a frame has been completely received, the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs, the RXRDY flag is set and a receive interrupt is generated if RX INT ENA (SCISETINT0.9) is set. When the data is read from SCIRD, the RXRDY flag is automatically cleared. When the SCI receives data that is fewer than eight bits in length, it loads the data into this register in a left justified format padded with trailing zeros. Therefore, your software should perform a logical shift on the data by the correct number of positions to make it right justified."]
# [inline (always)]
pub fn rd (& self) -> RdR { RdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Received Data. This bit is effective in SCI-compatible mode only. When a frame has been completely received, the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs, the RXRDY flag is set and a receive interrupt is generated if RX INT ENA (SCISETINT0.9) is set. When the data is read from SCIRD, the RXRDY flag is automatically cleared. When the SCI receives data that is fewer than eight bits in length, it loads the data into this register in a left justified format padded with trailing zeros. Therefore, your software should perform a logical shift on the data by the correct number of positions to make it right justified."]
# [inline (always)]
# [must_use]
pub fn rd (& mut self) -> RdW < ScirdSpec > { RdW :: new (self , 0) } } # [doc = "The SCIRD register is where received data is stored and can be read from.\n\nYou can [`read`](crate::Reg::read) this register and get [`scird::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scird::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScirdSpec ; impl crate :: RegisterSpec for ScirdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scird::R`](R) reader structure"]
impl crate :: Readable for ScirdSpec { } # [doc = "`write(|w| ..)` method takes [`scird::W`](W) writer structure"]
impl crate :: Writable for ScirdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIRD to value 0"]
impl crate :: Resettable for ScirdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCITD (rw) register accessor: The SCITD register is where data to be transmitted is written to by application software.\n\nYou can [`read`](crate::Reg::read) this register and get [`scitd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scitd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scitd`]
module"]
# [doc (alias = "SCITD")]
pub type Scitd = crate :: Reg < scitd :: ScitdSpec > ; # [doc = "The SCITD register is where data to be transmitted is written to by application software."]
pub mod scitd { # [doc = "Register `SCITD` reader"]
pub type R = crate :: R < ScitdSpec > ; # [doc = "Register `SCITD` writer"]
pub type W = crate :: W < ScitdSpec > ; # [doc = "Field `TD` reader - 7:0\\]
Transmit data This bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag (SCIFLR.23), which indicates that SCITD is ready to be loaded with another byte of data. Note: If TX INT ENA (SCISETINT.8) is set, this data transfer also causes an interrupt. Note: Data written to the SCIRD register that is fewer than eight bits long must be right justified, but it does not need to be padded with leading zeros."]
pub type TdR = crate :: FieldReader ; # [doc = "Field `TD` writer - 7:0\\]
Transmit data This bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag (SCIFLR.23), which indicates that SCITD is ready to be loaded with another byte of data. Note: If TX INT ENA (SCISETINT.8) is set, this data transfer also causes an interrupt. Note: Data written to the SCIRD register that is fewer than eight bits long must be right justified, but it does not need to be padded with leading zeros."]
pub type TdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Transmit data This bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag (SCIFLR.23), which indicates that SCITD is ready to be loaded with another byte of data. Note: If TX INT ENA (SCISETINT.8) is set, this data transfer also causes an interrupt. Note: Data written to the SCIRD register that is fewer than eight bits long must be right justified, but it does not need to be padded with leading zeros."]
# [inline (always)]
pub fn td (& self) -> TdR { TdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Transmit data This bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag (SCIFLR.23), which indicates that SCITD is ready to be loaded with another byte of data. Note: If TX INT ENA (SCISETINT.8) is set, this data transfer also causes an interrupt. Note: Data written to the SCIRD register that is fewer than eight bits long must be right justified, but it does not need to be padded with leading zeros."]
# [inline (always)]
# [must_use]
pub fn td (& mut self) -> TdW < ScitdSpec > { TdW :: new (self , 0) } } # [doc = "The SCITD register is where data to be transmitted is written to by application software.\n\nYou can [`read`](crate::Reg::read) this register and get [`scitd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scitd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScitdSpec ; impl crate :: RegisterSpec for ScitdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scitd::R`](R) reader structure"]
impl crate :: Readable for ScitdSpec { } # [doc = "`write(|w| ..)` method takes [`scitd::W`](W) writer structure"]
impl crate :: Writable for ScitdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCITD to value 0"]
impl crate :: Resettable for ScitdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO0 (rw) register accessor: The SCIPIO0 register is used to enable the LINTX and LINRX pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio0`]
module"]
# [doc (alias = "SCIPIO0")]
pub type Scipio0 = crate :: Reg < scipio0 :: Scipio0Spec > ; # [doc = "The SCIPIO0 register is used to enable the LINTX and LINRX pins."]
pub mod scipio0 { # [doc = "Register `SCIPIO0` reader"]
pub type R = crate :: R < Scipio0Spec > ; # [doc = "Register `SCIPIO0` writer"]
pub type W = crate :: W < Scipio0Spec > ; # [doc = "Field `CLKFUNC` reader - 0:0\\]
Reserved"]
pub type ClkfuncR = crate :: BitReader ; # [doc = "Field `CLKFUNC` writer - 0:0\\]
Reserved"]
pub type ClkfuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFUNC` reader - 1:1\\]
Receive pin function. This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin."]
pub type RxfuncR = crate :: BitReader ; # [doc = "Field `RXFUNC` writer - 1:1\\]
Receive pin function. This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin."]
pub type RxfuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFUNC` reader - 2:2\\]
Transmit pin function. This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin."]
pub type TxfuncR = crate :: BitReader ; # [doc = "Field `TXFUNC` writer - 2:2\\]
Transmit pin function. This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin."]
pub type TxfuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkfunc (& self) -> ClkfuncR { ClkfuncR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin function. This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin."]
# [inline (always)]
pub fn rxfunc (& self) -> RxfuncR { RxfuncR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin function. This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin."]
# [inline (always)]
pub fn txfunc (& self) -> TxfuncR { TxfuncR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkfunc (& mut self) -> ClkfuncW < Scipio0Spec > { ClkfuncW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin function. This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin."]
# [inline (always)]
# [must_use]
pub fn rxfunc (& mut self) -> RxfuncW < Scipio0Spec > { RxfuncW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin function. This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin."]
# [inline (always)]
# [must_use]
pub fn txfunc (& mut self) -> TxfuncW < Scipio0Spec > { TxfuncW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio0Spec > { Reserved1W :: new (self , 16) } } # [doc = "The SCIPIO0 register is used to enable the LINTX and LINRX pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio0Spec ; impl crate :: RegisterSpec for Scipio0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio0::R`](R) reader structure"]
impl crate :: Readable for Scipio0Spec { } # [doc = "`write(|w| ..)` method takes [`scipio0::W`](W) writer structure"]
impl crate :: Writable for Scipio0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO0 to value 0"]
impl crate :: Resettable for Scipio0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO1 (rw) register accessor: SCIPIO1\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio1`]
module"]
# [doc (alias = "SCIPIO1")]
pub type Scipio1 = crate :: Reg < scipio1 :: Scipio1Spec > ; # [doc = "SCIPIO1"]
pub mod scipio1 { # [doc = "Register `SCIPIO1` reader"]
pub type R = crate :: R < Scipio1Spec > ; # [doc = "Register `SCIPIO1` writer"]
pub type W = crate :: W < Scipio1Spec > ; # [doc = "Field `CLKDIR` reader - 0:0\\]
Reserved"]
pub type ClkdirR = crate :: BitReader ; # [doc = "Field `CLKDIR` writer - 0:0\\]
Reserved"]
pub type ClkdirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXDIR` reader - 1:1\\]
Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
pub type RxdirR = crate :: BitReader ; # [doc = "Field `RXDIR` writer - 1:1\\]
Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
pub type RxdirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXDIR` reader - 2:2\\]
Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
pub type TxdirR = crate :: BitReader ; # [doc = "Field `TXDIR` writer - 2:2\\]
Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
pub type TxdirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkdir (& self) -> ClkdirR { ClkdirR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
# [inline (always)]
pub fn rxdir (& self) -> RxdirR { RxdirR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
# [inline (always)]
pub fn txdir (& self) -> TxdirR { TxdirR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkdir (& mut self) -> ClkdirW < Scipio1Spec > { ClkdirW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn rxdir (& mut self) -> RxdirW < Scipio1Spec > { RxdirW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn txdir (& mut self) -> TxdirW < Scipio1Spec > { TxdirW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio1Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO1\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio1Spec ; impl crate :: RegisterSpec for Scipio1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio1::R`](R) reader structure"]
impl crate :: Readable for Scipio1Spec { } # [doc = "`write(|w| ..)` method takes [`scipio1::W`](W) writer structure"]
impl crate :: Writable for Scipio1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO1 to value 0"]
impl crate :: Resettable for Scipio1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO2 (rw) register accessor: The SCIPIO2 register indicates the current status of the LINTX and LINRX pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio2`]
module"]
# [doc (alias = "SCIPIO2")]
pub type Scipio2 = crate :: Reg < scipio2 :: Scipio2Spec > ; # [doc = "The SCIPIO2 register indicates the current status of the LINTX and LINRX pins."]
pub mod scipio2 { # [doc = "Register `SCIPIO2` reader"]
pub type R = crate :: R < Scipio2Spec > ; # [doc = "Register `SCIPIO2` writer"]
pub type W = crate :: W < Scipio2Spec > ; # [doc = "Field `CLKIN` reader - 0:0\\]
Reserved"]
pub type ClkinR = crate :: BitReader ; # [doc = "Field `CLKIN` writer - 0:0\\]
Reserved"]
pub type ClkinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXIN` reader - 1:1\\]
Receive data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin."]
pub type RxinR = crate :: BitReader ; # [doc = "Field `RXIN` writer - 1:1\\]
Receive data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin."]
pub type RxinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXIN` reader - 2:2\\]
Transmit data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin."]
pub type TxinR = crate :: BitReader ; # [doc = "Field `TXIN` writer - 2:2\\]
Transmit data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin."]
pub type TxinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkin (& self) -> ClkinR { ClkinR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin."]
# [inline (always)]
pub fn rxin (& self) -> RxinR { RxinR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin."]
# [inline (always)]
pub fn txin (& self) -> TxinR { TxinR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkin (& mut self) -> ClkinW < Scipio2Spec > { ClkinW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin."]
# [inline (always)]
# [must_use]
pub fn rxin (& mut self) -> RxinW < Scipio2Spec > { RxinW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin."]
# [inline (always)]
# [must_use]
pub fn txin (& mut self) -> TxinW < Scipio2Spec > { TxinW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio2Spec > { Reserved1W :: new (self , 16) } } # [doc = "The SCIPIO2 register indicates the current status of the LINTX and LINRX pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio2Spec ; impl crate :: RegisterSpec for Scipio2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio2::R`](R) reader structure"]
impl crate :: Readable for Scipio2Spec { } # [doc = "`write(|w| ..)` method takes [`scipio2::W`](W) writer structure"]
impl crate :: Writable for Scipio2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO2 to value 0"]
impl crate :: Resettable for Scipio2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO3 (rw) register accessor: SCIPIO3\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio3`]
module"]
# [doc (alias = "SCIPIO3")]
pub type Scipio3 = crate :: Reg < scipio3 :: Scipio3Spec > ; # [doc = "SCIPIO3"]
pub mod scipio3 { # [doc = "Register `SCIPIO3` reader"]
pub type R = crate :: R < Scipio3Spec > ; # [doc = "Register `SCIPIO3` writer"]
pub type W = crate :: W < Scipio3Spec > ; # [doc = "Field `CLKOUT` reader - 0:0\\]
Reserved"]
pub type ClkoutR = crate :: BitReader ; # [doc = "Field `CLKOUT` writer - 0:0\\]
Reserved"]
pub type ClkoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXOUT` reader - 1:1\\]
Receive pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX."]
pub type RxoutR = crate :: BitReader ; # [doc = "Field `RXOUT` writer - 1:1\\]
Receive pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX."]
pub type RxoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXOUT` reader - 2:2\\]
Transmit pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX."]
pub type TxoutR = crate :: BitReader ; # [doc = "Field `TXOUT` writer - 2:2\\]
Transmit pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX."]
pub type TxoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkout (& self) -> ClkoutR { ClkoutR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX."]
# [inline (always)]
pub fn rxout (& self) -> RxoutR { RxoutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX."]
# [inline (always)]
pub fn txout (& self) -> TxoutR { TxoutR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkout (& mut self) -> ClkoutW < Scipio3Spec > { ClkoutW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX."]
# [inline (always)]
# [must_use]
pub fn rxout (& mut self) -> RxoutW < Scipio3Spec > { RxoutW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX."]
# [inline (always)]
# [must_use]
pub fn txout (& mut self) -> TxoutW < Scipio3Spec > { TxoutW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio3Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO3\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio3Spec ; impl crate :: RegisterSpec for Scipio3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio3::R`](R) reader structure"]
impl crate :: Readable for Scipio3Spec { } # [doc = "`write(|w| ..)` method takes [`scipio3::W`](W) writer structure"]
impl crate :: Writable for Scipio3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO3 to value 0"]
impl crate :: Resettable for Scipio3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO4 (rw) register accessor: SCIPIO4\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio4`]
module"]
# [doc (alias = "SCIPIO4")]
pub type Scipio4 = crate :: Reg < scipio4 :: Scipio4Spec > ; # [doc = "SCIPIO4"]
pub mod scipio4 { # [doc = "Register `SCIPIO4` reader"]
pub type R = crate :: R < Scipio4Spec > ; # [doc = "Register `SCIPIO4` writer"]
pub type W = crate :: W < Scipio4Spec > ; # [doc = "Field `CLKSET` reader - 0:0\\]
Reserved"]
pub type ClksetR = crate :: BitReader ; # [doc = "Field `CLKSET` writer - 0:0\\]
Reserved"]
pub type ClksetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXSET` reader - 1:1\\]
Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX."]
pub type RxsetR = crate :: BitReader ; # [doc = "Field `RXSET` writer - 1:1\\]
Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX."]
pub type RxsetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXSET` reader - 2:2\\]
Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX."]
pub type TxsetR = crate :: BitReader ; # [doc = "Field `TXSET` writer - 2:2\\]
Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX."]
pub type TxsetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkset (& self) -> ClksetR { ClksetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX."]
# [inline (always)]
pub fn rxset (& self) -> RxsetR { RxsetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX."]
# [inline (always)]
pub fn txset (& self) -> TxsetR { TxsetR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkset (& mut self) -> ClksetW < Scipio4Spec > { ClksetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX."]
# [inline (always)]
# [must_use]
pub fn rxset (& mut self) -> RxsetW < Scipio4Spec > { RxsetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX."]
# [inline (always)]
# [must_use]
pub fn txset (& mut self) -> TxsetW < Scipio4Spec > { TxsetW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio4Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO4\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio4Spec ; impl crate :: RegisterSpec for Scipio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio4::R`](R) reader structure"]
impl crate :: Readable for Scipio4Spec { } # [doc = "`write(|w| ..)` method takes [`scipio4::W`](W) writer structure"]
impl crate :: Writable for Scipio4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO4 to value 0"]
impl crate :: Resettable for Scipio4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO5 (rw) register accessor: SCIPIO5\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio5`]
module"]
# [doc (alias = "SCIPIO5")]
pub type Scipio5 = crate :: Reg < scipio5 :: Scipio5Spec > ; # [doc = "SCIPIO5"]
pub mod scipio5 { # [doc = "Register `SCIPIO5` reader"]
pub type R = crate :: R < Scipio5Spec > ; # [doc = "Register `SCIPIO5` writer"]
pub type W = crate :: W < Scipio5Spec > ; # [doc = "Field `CLKCLR` reader - 0:0\\]
Reserved"]
pub type ClkclrR = crate :: BitReader ; # [doc = "Field `CLKCLR` writer - 0:0\\]
Reserved"]
pub type ClkclrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXCLR` reader - 1:1\\]
Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX."]
pub type RxclrR = crate :: BitReader ; # [doc = "Field `RXCLR` writer - 1:1\\]
Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX."]
pub type RxclrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXCLR` reader - 2:2\\]
Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX."]
pub type TxclrR = crate :: BitReader ; # [doc = "Field `TXCLR` writer - 2:2\\]
Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX."]
pub type TxclrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkclr (& self) -> ClkclrR { ClkclrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX."]
# [inline (always)]
pub fn rxclr (& self) -> RxclrR { RxclrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX."]
# [inline (always)]
pub fn txclr (& self) -> TxclrR { TxclrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkclr (& mut self) -> ClkclrW < Scipio5Spec > { ClkclrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX."]
# [inline (always)]
# [must_use]
pub fn rxclr (& mut self) -> RxclrW < Scipio5Spec > { RxclrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX."]
# [inline (always)]
# [must_use]
pub fn txclr (& mut self) -> TxclrW < Scipio5Spec > { TxclrW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio5Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO5\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio5Spec ; impl crate :: RegisterSpec for Scipio5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio5::R`](R) reader structure"]
impl crate :: Readable for Scipio5Spec { } # [doc = "`write(|w| ..)` method takes [`scipio5::W`](W) writer structure"]
impl crate :: Writable for Scipio5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO5 to value 0"]
impl crate :: Resettable for Scipio5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO6 (rw) register accessor: SCIPIO6\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio6`]
module"]
# [doc (alias = "SCIPIO6")]
pub type Scipio6 = crate :: Reg < scipio6 :: Scipio6Spec > ; # [doc = "SCIPIO6"]
pub mod scipio6 { # [doc = "Register `SCIPIO6` reader"]
pub type R = crate :: R < Scipio6Spec > ; # [doc = "Register `SCIPIO6` writer"]
pub type W = crate :: W < Scipio6Spec > ; # [doc = "Field `CLKDR` reader - 0:0\\]
Reserved"]
pub type ClkdrR = crate :: BitReader ; # [doc = "Field `CLKDR` writer - 0:0\\]
Reserved"]
pub type ClkdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXPDR` reader - 1:1\\]
Receive pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX."]
pub type RxpdrR = crate :: BitReader ; # [doc = "Field `RXPDR` writer - 1:1\\]
Receive pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX."]
pub type RxpdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXPDR` reader - 2:2\\]
Transmit pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX."]
pub type TxpdrR = crate :: BitReader ; # [doc = "Field `TXPDR` writer - 2:2\\]
Transmit pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX."]
pub type TxpdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkdr (& self) -> ClkdrR { ClkdrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX."]
# [inline (always)]
pub fn rxpdr (& self) -> RxpdrR { RxpdrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX."]
# [inline (always)]
pub fn txpdr (& self) -> TxpdrR { TxpdrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkdr (& mut self) -> ClkdrW < Scipio6Spec > { ClkdrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX."]
# [inline (always)]
# [must_use]
pub fn rxpdr (& mut self) -> RxpdrW < Scipio6Spec > { RxpdrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX."]
# [inline (always)]
# [must_use]
pub fn txpdr (& mut self) -> TxpdrW < Scipio6Spec > { TxpdrW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio6Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO6\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio6Spec ; impl crate :: RegisterSpec for Scipio6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio6::R`](R) reader structure"]
impl crate :: Readable for Scipio6Spec { } # [doc = "`write(|w| ..)` method takes [`scipio6::W`](W) writer structure"]
impl crate :: Writable for Scipio6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO6 to value 0"]
impl crate :: Resettable for Scipio6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO7 (rw) register accessor: SCIPIO7\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio7`]
module"]
# [doc (alias = "SCIPIO7")]
pub type Scipio7 = crate :: Reg < scipio7 :: Scipio7Spec > ; # [doc = "SCIPIO7"]
pub mod scipio7 { # [doc = "Register `SCIPIO7` reader"]
pub type R = crate :: R < Scipio7Spec > ; # [doc = "Register `SCIPIO7` writer"]
pub type W = crate :: W < Scipio7Spec > ; # [doc = "Field `CLKPD` reader - 0:0\\]
Reserved"]
pub type ClkpdR = crate :: BitReader ; # [doc = "Field `CLKPD` writer - 0:0\\]
Reserved"]
pub type ClkpdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXPD` reader - 1:1\\]
Receive pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX."]
pub type RxpdR = crate :: BitReader ; # [doc = "Field `RXPD` writer - 1:1\\]
Receive pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX."]
pub type RxpdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXPD` reader - 2:2\\]
Transmit pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX."]
pub type TxpdR = crate :: BitReader ; # [doc = "Field `TXPD` writer - 2:2\\]
Transmit pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX."]
pub type TxpdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkpd (& self) -> ClkpdR { ClkpdR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX."]
# [inline (always)]
pub fn rxpd (& self) -> RxpdR { RxpdR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transmit pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX."]
# [inline (always)]
pub fn txpd (& self) -> TxpdR { TxpdR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkpd (& mut self) -> ClkpdW < Scipio7Spec > { ClkpdW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Receive pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX."]
# [inline (always)]
# [must_use]
pub fn rxpd (& mut self) -> RxpdW < Scipio7Spec > { RxpdW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transmit pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX."]
# [inline (always)]
# [must_use]
pub fn txpd (& mut self) -> TxpdW < Scipio7Spec > { TxpdW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio7Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO7\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio7Spec ; impl crate :: RegisterSpec for Scipio7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio7::R`](R) reader structure"]
impl crate :: Readable for Scipio7Spec { } # [doc = "`write(|w| ..)` method takes [`scipio7::W`](W) writer structure"]
impl crate :: Writable for Scipio7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO7 to value 0"]
impl crate :: Resettable for Scipio7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO8 (rw) register accessor: SCIPIO8\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio8`]
module"]
# [doc (alias = "SCIPIO8")]
pub type Scipio8 = crate :: Reg < scipio8 :: Scipio8Spec > ; # [doc = "SCIPIO8"]
pub mod scipio8 { # [doc = "Register `SCIPIO8` reader"]
pub type R = crate :: R < Scipio8Spec > ; # [doc = "Register `SCIPIO8` writer"]
pub type W = crate :: W < Scipio8Spec > ; # [doc = "Field `CLKPSL` reader - 0:0\\]
Reserved"]
pub type ClkpslR = crate :: BitReader ; # [doc = "Field `CLKPSL` writer - 0:0\\]
Reserved"]
pub type ClkpslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXPSL` reader - 1:1\\]
RX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX."]
pub type RxpslR = crate :: BitReader ; # [doc = "Field `RXPSL` writer - 1:1\\]
RX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX."]
pub type RxpslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXPSL` reader - 2:2\\]
TX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX."]
pub type TxpslR = crate :: BitReader ; # [doc = "Field `TXPSL` writer - 2:2\\]
TX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX."]
pub type TxpslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clkpsl (& self) -> ClkpslR { ClkpslR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX."]
# [inline (always)]
pub fn rxpsl (& self) -> RxpslR { RxpslR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX."]
# [inline (always)]
pub fn txpsl (& self) -> TxpslR { TxpslR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clkpsl (& mut self) -> ClkpslW < Scipio8Spec > { ClkpslW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX."]
# [inline (always)]
# [must_use]
pub fn rxpsl (& mut self) -> RxpslW < Scipio8Spec > { RxpslW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX."]
# [inline (always)]
# [must_use]
pub fn txpsl (& mut self) -> TxpslW < Scipio8Spec > { TxpslW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio8Spec > { Reserved1W :: new (self , 16) } } # [doc = "SCIPIO8\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio8Spec ; impl crate :: RegisterSpec for Scipio8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio8::R`](R) reader structure"]
impl crate :: Readable for Scipio8Spec { } # [doc = "`write(|w| ..)` method takes [`scipio8::W`](W) writer structure"]
impl crate :: Writable for Scipio8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO8 to value 0"]
impl crate :: Resettable for Scipio8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINCOMP (rw) register accessor: The LINCOMPARE register is used to configure the sync delimeter and sync break extension.\n\nYou can [`read`](crate::Reg::read) this register and get [`lincomp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lincomp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lincomp`]
module"]
# [doc (alias = "LINCOMP")]
pub type Lincomp = crate :: Reg < lincomp :: LincompSpec > ; # [doc = "The LINCOMPARE register is used to configure the sync delimeter and sync break extension."]
pub mod lincomp { # [doc = "Register `LINCOMP` reader"]
pub type R = crate :: R < LincompSpec > ; # [doc = "Register `LINCOMP` writer"]
pub type W = crate :: W < LincompSpec > ; # [doc = "Field `SBREAK` reader - 2:0\\]
3-bit Sync Break extend. LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit. The time delay calculation for the sync break is: TSYNBRK = 13Tbit + SBREAK x Tbit These bits are writable in LIN mode only."]
pub type SbreakR = crate :: FieldReader ; # [doc = "Field `SBREAK` writer - 2:0\\]
3-bit Sync Break extend. LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit. The time delay calculation for the sync break is: TSYNBRK = 13Tbit + SBREAK x Tbit These bits are writable in LIN mode only."]
pub type SbreakW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SDEL` reader - 9:8\\]
2-bit Sync Delimiter compare. These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field. The time delay calculation for the synchronization delimiter is: TSDEL = (SDEL + 1)Tbit These bits are writable in LIN mode only."]
pub type SdelR = crate :: FieldReader ; # [doc = "Field `SDEL` writer - 9:8\\]
2-bit Sync Delimiter compare. These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field. The time delay calculation for the synchronization delimiter is: TSDEL = (SDEL + 1)Tbit These bits are writable in LIN mode only."]
pub type SdelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 15:10\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:10\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `Reserved2` reader - 31:16\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved2` writer - 31:16\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3-bit Sync Break extend. LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit. The time delay calculation for the sync break is: TSYNBRK = 13Tbit + SBREAK x Tbit These bits are writable in LIN mode only."]
# [inline (always)]
pub fn sbreak (& self) -> SbreakR { SbreakR :: new ((self . bits & 7) as u8) } # [doc = "Bits 8:9 - 9:8\\]
2-bit Sync Delimiter compare. These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field. The time delay calculation for the synchronization delimiter is: TSDEL = (SDEL + 1)Tbit These bits are writable in LIN mode only."]
# [inline (always)]
pub fn sdel (& self) -> SdelR { SdelR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3-bit Sync Break extend. LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit. The time delay calculation for the sync break is: TSYNBRK = 13Tbit + SBREAK x Tbit These bits are writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn sbreak (& mut self) -> SbreakW < LincompSpec > { SbreakW :: new (self , 0) } # [doc = "Bits 8:9 - 9:8\\]
2-bit Sync Delimiter compare. These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field. The time delay calculation for the synchronization delimiter is: TSDEL = (SDEL + 1)Tbit These bits are writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn sdel (& mut self) -> SdelW < LincompSpec > { SdelW :: new (self , 8) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < LincompSpec > { Reserved1W :: new (self , 10) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < LincompSpec > { Reserved2W :: new (self , 16) } } # [doc = "The LINCOMPARE register is used to configure the sync delimeter and sync break extension.\n\nYou can [`read`](crate::Reg::read) this register and get [`lincomp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lincomp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LincompSpec ; impl crate :: RegisterSpec for LincompSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`lincomp::R`](R) reader structure"]
impl crate :: Readable for LincompSpec { } # [doc = "`write(|w| ..)` method takes [`lincomp::W`](W) writer structure"]
impl crate :: Writable for LincompSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINCOMP to value 0"]
impl crate :: Resettable for LincompSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINRD0 (rw) register accessor: The LINRD0 register contains the lower 4 bytes of the received LIN frame data.\n\nYou can [`read`](crate::Reg::read) this register and get [`linrd0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linrd0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linrd0`]
module"]
# [doc (alias = "LINRD0")]
pub type Linrd0 = crate :: Reg < linrd0 :: Linrd0Spec > ; # [doc = "The LINRD0 register contains the lower 4 bytes of the received LIN frame data."]
pub mod linrd0 { # [doc = "Register `LINRD0` reader"]
pub type R = crate :: R < Linrd0Spec > ; # [doc = "Register `LINRD0` writer"]
pub type W = crate :: W < Linrd0Spec > ; # [doc = "Field `RD3` reader - 7:0\\]
8-bit Receive Buffer 3. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd3R = crate :: FieldReader ; # [doc = "Field `RD3` writer - 7:0\\]
8-bit Receive Buffer 3. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD2` reader - 15:8\\]
8-bit Receive Buffer 2. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd2R = crate :: FieldReader ; # [doc = "Field `RD2` writer - 15:8\\]
8-bit Receive Buffer 2. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD1` reader - 23:16\\]
8-bit Receive Buffer 1. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd1R = crate :: FieldReader ; # [doc = "Field `RD1` writer - 23:16\\]
8-bit Receive Buffer 1. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD0` reader - 31:24\\]
8-bit Receive Buffer 0 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. A read of this byte clears the RXDY byte. Note: RD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
pub type Rd0R = crate :: FieldReader ; # [doc = "Field `RD0` writer - 31:24\\]
8-bit Receive Buffer 0 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. A read of this byte clears the RXDY byte. Note: RD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
pub type Rd0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
8-bit Receive Buffer 3. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd3 (& self) -> Rd3R { Rd3R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Receive Buffer 2. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd2 (& self) -> Rd2R { Rd2R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Receive Buffer 1. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd1 (& self) -> Rd1R { Rd1R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Receive Buffer 0 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. A read of this byte clears the RXDY byte. Note: RD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
# [inline (always)]
pub fn rd0 (& self) -> Rd0R { Rd0R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
8-bit Receive Buffer 3. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd3 (& mut self) -> Rd3W < Linrd0Spec > { Rd3W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Receive Buffer 2. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd2 (& mut self) -> Rd2W < Linrd0Spec > { Rd2W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Receive Buffer 1. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd1 (& mut self) -> Rd1W < Linrd0Spec > { Rd1W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Receive Buffer 0 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. A read of this byte clears the RXDY byte. Note: RD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
# [inline (always)]
# [must_use]
pub fn rd0 (& mut self) -> Rd0W < Linrd0Spec > { Rd0W :: new (self , 24) } } # [doc = "The LINRD0 register contains the lower 4 bytes of the received LIN frame data.\n\nYou can [`read`](crate::Reg::read) this register and get [`linrd0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linrd0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Linrd0Spec ; impl crate :: RegisterSpec for Linrd0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`linrd0::R`](R) reader structure"]
impl crate :: Readable for Linrd0Spec { } # [doc = "`write(|w| ..)` method takes [`linrd0::W`](W) writer structure"]
impl crate :: Writable for Linrd0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINRD0 to value 0"]
impl crate :: Resettable for Linrd0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINRD1 (rw) register accessor: The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data.\n\nYou can [`read`](crate::Reg::read) this register and get [`linrd1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linrd1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linrd1`]
module"]
# [doc (alias = "LINRD1")]
pub type Linrd1 = crate :: Reg < linrd1 :: Linrd1Spec > ; # [doc = "The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data."]
pub mod linrd1 { # [doc = "Register `LINRD1` reader"]
pub type R = crate :: R < Linrd1Spec > ; # [doc = "Register `LINRD1` writer"]
pub type W = crate :: W < Linrd1Spec > ; # [doc = "Field `RD7` reader - 7:0\\]
8-bit Receive Buffer 7. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd7R = crate :: FieldReader ; # [doc = "Field `RD7` writer - 7:0\\]
8-bit Receive Buffer 7. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD6` reader - 15:8\\]
8-bit Receive Buffer 6. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd6R = crate :: FieldReader ; # [doc = "Field `RD6` writer - 15:8\\]
8-bit Receive Buffer 6. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD5` reader - 23:16\\]
8-bit Receive Buffer 5. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd5R = crate :: FieldReader ; # [doc = "Field `RD5` writer - 23:16\\]
8-bit Receive Buffer 5. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD4` reader - 31:24\\]
8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd4R = crate :: FieldReader ; # [doc = "Field `RD4` writer - 31:24\\]
8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
pub type Rd4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
8-bit Receive Buffer 7. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd7 (& self) -> Rd7R { Rd7R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Receive Buffer 6. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd6 (& self) -> Rd6R { Rd6R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Receive Buffer 5. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd5 (& self) -> Rd5R { Rd5R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
pub fn rd4 (& self) -> Rd4R { Rd4R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
8-bit Receive Buffer 7. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd7 (& mut self) -> Rd7W < Linrd1Spec > { Rd7W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Receive Buffer 6. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd6 (& mut self) -> Rd6W < Linrd1Spec > { Rd6W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Receive Buffer 5. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd5 (& mut self) -> Rd5W < Linrd1Spec > { Rd5W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received."]
# [inline (always)]
# [must_use]
pub fn rd4 (& mut self) -> Rd4W < Linrd1Spec > { Rd4W :: new (self , 24) } } # [doc = "The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data.\n\nYou can [`read`](crate::Reg::read) this register and get [`linrd1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linrd1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Linrd1Spec ; impl crate :: RegisterSpec for Linrd1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`linrd1::R`](R) reader structure"]
impl crate :: Readable for Linrd1Spec { } # [doc = "`write(|w| ..)` method takes [`linrd1::W`](W) writer structure"]
impl crate :: Writable for Linrd1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINRD1 to value 0"]
impl crate :: Resettable for Linrd1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINMASK (rw) register accessor: The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames.\n\nYou can [`read`](crate::Reg::read) this register and get [`linmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linmask`]
module"]
# [doc (alias = "LINMASK")]
pub type Linmask = crate :: Reg < linmask :: LinmaskSpec > ; # [doc = "The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames."]
pub mod linmask { # [doc = "Register `LINMASK` reader"]
pub type R = crate :: R < LinmaskSpec > ; # [doc = "Register `LINMASK` writer"]
pub type W = crate :: W < LinmaskSpec > ; # [doc = "Field `TXIDMASK` reader - 7:0\\]
Transmit ID mask. This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that bit is filtered and therefore not used for the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
pub type TxidmaskR = crate :: FieldReader ; # [doc = "Field `TXIDMASK` writer - 7:0\\]
Transmit ID mask. This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that bit is filtered and therefore not used for the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
pub type TxidmaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RXIDMASK` reader - 23:16\\]
Receive ID mask. This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that that bit is filtered and therefore not used in the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
pub type RxidmaskR = crate :: FieldReader ; # [doc = "Field `RXIDMASK` writer - 23:16\\]
Receive ID mask. This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that that bit is filtered and therefore not used in the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
pub type RxidmaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Transmit ID mask. This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that bit is filtered and therefore not used for the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
# [inline (always)]
pub fn txidmask (& self) -> TxidmaskR { TxidmaskR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Receive ID mask. This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that that bit is filtered and therefore not used in the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
# [inline (always)]
pub fn rxidmask (& self) -> RxidmaskR { RxidmaskR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Transmit ID mask. This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that bit is filtered and therefore not used for the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
# [inline (always)]
# [must_use]
pub fn txidmask (& mut self) -> TxidmaskW < LinmaskSpec > { TxidmaskW :: new (self , 0) } # [doc = "Bits 16:23 - 23:16\\]
Receive ID mask. This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that that bit is filtered and therefore not used in the compare. When HGENCTRL is set to 1, this field must be set to 0xFF."]
# [inline (always)]
# [must_use]
pub fn rxidmask (& mut self) -> RxidmaskW < LinmaskSpec > { RxidmaskW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < LinmaskSpec > { Reserved1W :: new (self , 24) } } # [doc = "The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames.\n\nYou can [`read`](crate::Reg::read) this register and get [`linmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LinmaskSpec ; impl crate :: RegisterSpec for LinmaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`linmask::R`](R) reader structure"]
impl crate :: Readable for LinmaskSpec { } # [doc = "`write(|w| ..)` method takes [`linmask::W`](W) writer structure"]
impl crate :: Writable for LinmaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINMASK to value 0"]
impl crate :: Resettable for LinmaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINID (rw) register accessor: The LINID register contains the identification fields for LIN communication. NOTE: For software compatibility with future LIN modules, the HGEN CTRL bit must be set to 1, the RX ID MASK field must be set to FFh, and the TX ID MASK field must be set to FFh.\n\nYou can [`read`](crate::Reg::read) this register and get [`linid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linid`]
module"]
# [doc (alias = "LINID")]
pub type Linid = crate :: Reg < linid :: LinidSpec > ; # [doc = "The LINID register contains the identification fields for LIN communication. NOTE: For software compatibility with future LIN modules, the HGEN CTRL bit must be set to 1, the RX ID MASK field must be set to FFh, and the TX ID MASK field must be set to FFh."]
pub mod linid { # [doc = "Register `LINID` reader"]
pub type R = crate :: R < LinidSpec > ; # [doc = "Register `LINID` writer"]
pub type W = crate :: W < LinidSpec > ; # [doc = "Field `IDBYTE` reader - 7:0\\]
ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node, a write to this register by the CPU initiates a header transmission. For a slave task, this byte is used for message filtering when HGENCTRL (SCIGCR1.12) is '0'. These bits are writable in LIN mode only."]
pub type IdbyteR = crate :: FieldReader ; # [doc = "Field `IDBYTE` writer - 7:0\\]
ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node, a write to this register by the CPU initiates a header transmission. For a slave task, this byte is used for message filtering when HGENCTRL (SCIGCR1.12) is '0'. These bits are writable in LIN mode only."]
pub type IdbyteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `IDSLAVETASKBYTE` reader - 15:8\\]
ID Slave Task byte. This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response, a TX response, or no action needs to be done by the LIN node. These bits are writable in LIN mode only."]
pub type IdslavetaskbyteR = crate :: FieldReader ; # [doc = "Field `IDSLAVETASKBYTE` writer - 15:8\\]
ID Slave Task byte. This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response, a TX response, or no action needs to be done by the LIN node. These bits are writable in LIN mode only."]
pub type IdslavetaskbyteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RECEIVEDID` reader - 23:16\\]
Received ID. This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been an RX/TX match. Note: If a framing error (FE) is detected during ID reception, the received ID will also not be copied to the LINID register."]
pub type ReceivedidR = crate :: FieldReader ; # [doc = "Field `RECEIVEDID` writer - 23:16\\]
Received ID. This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been an RX/TX match. Note: If a framing error (FE) is detected during ID reception, the received ID will also not be copied to the LINID register."]
pub type ReceivedidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node, a write to this register by the CPU initiates a header transmission. For a slave task, this byte is used for message filtering when HGENCTRL (SCIGCR1.12) is '0'. These bits are writable in LIN mode only."]
# [inline (always)]
pub fn idbyte (& self) -> IdbyteR { IdbyteR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
ID Slave Task byte. This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response, a TX response, or no action needs to be done by the LIN node. These bits are writable in LIN mode only."]
# [inline (always)]
pub fn idslavetaskbyte (& self) -> IdslavetaskbyteR { IdslavetaskbyteR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Received ID. This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been an RX/TX match. Note: If a framing error (FE) is detected during ID reception, the received ID will also not be copied to the LINID register."]
# [inline (always)]
pub fn receivedid (& self) -> ReceivedidR { ReceivedidR :: new (((self . bits >> 16) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node, a write to this register by the CPU initiates a header transmission. For a slave task, this byte is used for message filtering when HGENCTRL (SCIGCR1.12) is '0'. These bits are writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn idbyte (& mut self) -> IdbyteW < LinidSpec > { IdbyteW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
ID Slave Task byte. This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response, a TX response, or no action needs to be done by the LIN node. These bits are writable in LIN mode only."]
# [inline (always)]
# [must_use]
pub fn idslavetaskbyte (& mut self) -> IdslavetaskbyteW < LinidSpec > { IdslavetaskbyteW :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
Received ID. This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been an RX/TX match. Note: If a framing error (FE) is detected during ID reception, the received ID will also not be copied to the LINID register."]
# [inline (always)]
# [must_use]
pub fn receivedid (& mut self) -> ReceivedidW < LinidSpec > { ReceivedidW :: new (self , 16) } } # [doc = "The LINID register contains the identification fields for LIN communication. NOTE: For software compatibility with future LIN modules, the HGEN CTRL bit must be set to 1, the RX ID MASK field must be set to FFh, and the TX ID MASK field must be set to FFh.\n\nYou can [`read`](crate::Reg::read) this register and get [`linid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LinidSpec ; impl crate :: RegisterSpec for LinidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`linid::R`](R) reader structure"]
impl crate :: Readable for LinidSpec { } # [doc = "`write(|w| ..)` method takes [`linid::W`](W) writer structure"]
impl crate :: Writable for LinidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINID to value 0"]
impl crate :: Resettable for LinidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINTD0 (rw) register accessor: The LINTD0 register contains the lower 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame.\n\nYou can [`read`](crate::Reg::read) this register and get [`lintd0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lintd0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lintd0`]
module"]
# [doc (alias = "LINTD0")]
pub type Lintd0 = crate :: Reg < lintd0 :: Lintd0Spec > ; # [doc = "The LINTD0 register contains the lower 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
pub mod lintd0 { # [doc = "Register `LINTD0` reader"]
pub type R = crate :: R < Lintd0Spec > ; # [doc = "Register `LINTD0` writer"]
pub type W = crate :: W < Lintd0Spec > ; # [doc = "Field `TD3` reader - 7:0\\]
8-bit Transmit Buffer 3. Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td3R = crate :: FieldReader ; # [doc = "Field `TD3` writer - 7:0\\]
8-bit Transmit Buffer 3. Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TD2` reader - 15:8\\]
8-bit Transmit Buffer 2. Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td2R = crate :: FieldReader ; # [doc = "Field `TD2` writer - 15:8\\]
8-bit Transmit Buffer 2. Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TD1` reader - 23:16\\]
8-bit Transmit Buffer 3. Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td1R = crate :: FieldReader ; # [doc = "Field `TD1` writer - 23:16\\]
8-bit Transmit Buffer 3. Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TD0` reader - 31:24\\]
8-bit Transmit Buffer 0. Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer, transmission will be initiated."]
pub type Td0R = crate :: FieldReader ; # [doc = "Field `TD0` writer - 31:24\\]
8-bit Transmit Buffer 0. Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer, transmission will be initiated."]
pub type Td0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
8-bit Transmit Buffer 3. Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td3 (& self) -> Td3R { Td3R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Transmit Buffer 2. Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td2 (& self) -> Td2R { Td2R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Transmit Buffer 3. Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td1 (& self) -> Td1R { Td1R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Transmit Buffer 0. Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer, transmission will be initiated."]
# [inline (always)]
pub fn td0 (& self) -> Td0R { Td0R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
8-bit Transmit Buffer 3. Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td3 (& mut self) -> Td3W < Lintd0Spec > { Td3W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Transmit Buffer 2. Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td2 (& mut self) -> Td2W < Lintd0Spec > { Td2W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Transmit Buffer 3. Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td1 (& mut self) -> Td1W < Lintd0Spec > { Td1W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Transmit Buffer 0. Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer, transmission will be initiated."]
# [inline (always)]
# [must_use]
pub fn td0 (& mut self) -> Td0W < Lintd0Spec > { Td0W :: new (self , 24) } } # [doc = "The LINTD0 register contains the lower 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame.\n\nYou can [`read`](crate::Reg::read) this register and get [`lintd0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lintd0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lintd0Spec ; impl crate :: RegisterSpec for Lintd0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lintd0::R`](R) reader structure"]
impl crate :: Readable for Lintd0Spec { } # [doc = "`write(|w| ..)` method takes [`lintd0::W`](W) writer structure"]
impl crate :: Writable for Lintd0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINTD0 to value 0"]
impl crate :: Resettable for Lintd0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINTD1 (rw) register accessor: The LINTD1 register contains the upper 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame.\n\nYou can [`read`](crate::Reg::read) this register and get [`lintd1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lintd1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lintd1`]
module"]
# [doc (alias = "LINTD1")]
pub type Lintd1 = crate :: Reg < lintd1 :: Lintd1Spec > ; # [doc = "The LINTD1 register contains the upper 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame."]
pub mod lintd1 { # [doc = "Register `LINTD1` reader"]
pub type R = crate :: R < Lintd1Spec > ; # [doc = "Register `LINTD1` writer"]
pub type W = crate :: W < Lintd1Spec > ; # [doc = "Field `TD7` reader - 7:0\\]
8-bit Transmit Buffer 7. Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td7R = crate :: FieldReader ; # [doc = "Field `TD7` writer - 7:0\\]
8-bit Transmit Buffer 7. Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TD6` reader - 15:8\\]
8-bit Transmit Buffer 6. Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td6R = crate :: FieldReader ; # [doc = "Field `TD6` writer - 15:8\\]
8-bit Transmit Buffer 6. Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TD5` reader - 23:16\\]
8-bit Transmit Buffer 5. Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td5R = crate :: FieldReader ; # [doc = "Field `TD5` writer - 23:16\\]
8-bit Transmit Buffer 5. Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TD4` reader - 31:24\\]
8-bit Transmit Buffer 4. Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td4R = crate :: FieldReader ; # [doc = "Field `TD4` writer - 31:24\\]
8-bit Transmit Buffer 4. Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
pub type Td4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
8-bit Transmit Buffer 7. Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td7 (& self) -> Td7R { Td7R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Transmit Buffer 6. Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td6 (& self) -> Td6R { Td6R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Transmit Buffer 5. Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td5 (& self) -> Td5R { Td5R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Transmit Buffer 4. Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
pub fn td4 (& self) -> Td4R { Td4R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
8-bit Transmit Buffer 7. Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td7 (& mut self) -> Td7W < Lintd1Spec > { Td7W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
8-bit Transmit Buffer 6. Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td6 (& mut self) -> Td6W < Lintd1Spec > { Td6W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
8-bit Transmit Buffer 5. Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td5 (& mut self) -> Td5W < Lintd1Spec > { Td5W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
8-bit Transmit Buffer 4. Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission."]
# [inline (always)]
# [must_use]
pub fn td4 (& mut self) -> Td4W < Lintd1Spec > { Td4W :: new (self , 24) } } # [doc = "The LINTD1 register contains the upper 4 bytes of the data to be transmitted. NOTE: TD&lt;x-1> is equivalent to Data byte &lt;x> of the LIN frame.\n\nYou can [`read`](crate::Reg::read) this register and get [`lintd1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lintd1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lintd1Spec ; impl crate :: RegisterSpec for Lintd1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lintd1::R`](R) reader structure"]
impl crate :: Readable for Lintd1Spec { } # [doc = "`write(|w| ..)` method takes [`lintd1::W`](W) writer structure"]
impl crate :: Writable for Lintd1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINTD1 to value 0"]
impl crate :: Resettable for Lintd1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MBRSR (rw) register accessor: The MBRSR register is used to configure the expected maximum baud rate of the LIN network.\n\nYou can [`read`](crate::Reg::read) this register and get [`mbrsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbrsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbrsr`]
module"]
# [doc (alias = "MBRSR")]
pub type Mbrsr = crate :: Reg < mbrsr :: MbrsrSpec > ; # [doc = "The MBRSR register is used to configure the expected maximum baud rate of the LIN network."]
pub mod mbrsr { # [doc = "Register `MBRSR` reader"]
pub type R = crate :: R < MbrsrSpec > ; # [doc = "Register `MBRSR` writer"]
pub type W = crate :: W < MbrsrSpec > ; # [doc = "Field `MBR` reader - 12:0\\]
Maximum Baud Rate Prescaler. This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase (see the \"Header Reception and Adaptive Baudrate\" section) of a slave module if the ADAPT bit is set. In this way, a SCI/LIN slave using an automatic or select bit rate modes detects any LIN bus legal rate automatically. The MBR value should be programmed to allow a maximum baud rate that is not more than 10% above the expected operating baud rate in the LIN network. Otherwise a s 0x00 data byte could mistakenly be detected as sync break. The default value is for a 70MHz LINCLK (0xDAC). This MBR prescaler is used by the wake-up and idle time counters for a constant expiration time relative to a 20kHz rate."]
pub type MbrR = crate :: FieldReader < u16 > ; # [doc = "Field `MBR` writer - 12:0\\]
Maximum Baud Rate Prescaler. This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase (see the \"Header Reception and Adaptive Baudrate\" section) of a slave module if the ADAPT bit is set. In this way, a SCI/LIN slave using an automatic or select bit rate modes detects any LIN bus legal rate automatically. The MBR value should be programmed to allow a maximum baud rate that is not more than 10% above the expected operating baud rate in the LIN network. Otherwise a s 0x00 data byte could mistakenly be detected as sync break. The default value is for a 70MHz LINCLK (0xDAC). This MBR prescaler is used by the wake-up and idle time counters for a constant expiration time relative to a 20kHz rate."]
pub type MbrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 0:12 - 12:0\\]
Maximum Baud Rate Prescaler. This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase (see the \"Header Reception and Adaptive Baudrate\" section) of a slave module if the ADAPT bit is set. In this way, a SCI/LIN slave using an automatic or select bit rate modes detects any LIN bus legal rate automatically. The MBR value should be programmed to allow a maximum baud rate that is not more than 10% above the expected operating baud rate in the LIN network. Otherwise a s 0x00 data byte could mistakenly be detected as sync break. The default value is for a 70MHz LINCLK (0xDAC). This MBR prescaler is used by the wake-up and idle time counters for a constant expiration time relative to a 20kHz rate."]
# [inline (always)]
pub fn mbr (& self) -> MbrR { MbrR :: new ((self . bits & 0x1fff) as u16) } } impl W { # [doc = "Bits 0:12 - 12:0\\]
Maximum Baud Rate Prescaler. This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase (see the \"Header Reception and Adaptive Baudrate\" section) of a slave module if the ADAPT bit is set. In this way, a SCI/LIN slave using an automatic or select bit rate modes detects any LIN bus legal rate automatically. The MBR value should be programmed to allow a maximum baud rate that is not more than 10% above the expected operating baud rate in the LIN network. Otherwise a s 0x00 data byte could mistakenly be detected as sync break. The default value is for a 70MHz LINCLK (0xDAC). This MBR prescaler is used by the wake-up and idle time counters for a constant expiration time relative to a 20kHz rate."]
# [inline (always)]
# [must_use]
pub fn mbr (& mut self) -> MbrW < MbrsrSpec > { MbrW :: new (self , 0) } } # [doc = "The MBRSR register is used to configure the expected maximum baud rate of the LIN network.\n\nYou can [`read`](crate::Reg::read) this register and get [`mbrsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbrsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MbrsrSpec ; impl crate :: RegisterSpec for MbrsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`mbrsr::R`](R) reader structure"]
impl crate :: Readable for MbrsrSpec { } # [doc = "`write(|w| ..)` method takes [`mbrsr::W`](W) writer structure"]
impl crate :: Writable for MbrsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MBRSR to value 0"]
impl crate :: Resettable for MbrsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO9 (rw) register accessor: Couldn't find this register in spec. But it's mentioned in RTL.\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio9`]
module"]
# [doc (alias = "SCIPIO9")]
pub type Scipio9 = crate :: Reg < scipio9 :: Scipio9Spec > ; # [doc = "Couldn't find this register in spec. But it's mentioned in RTL."]
pub mod scipio9 { # [doc = "Register `SCIPIO9` reader"]
pub type R = crate :: R < Scipio9Spec > ; # [doc = "Register `SCIPIO9` writer"]
pub type W = crate :: W < Scipio9Spec > ; # [doc = "Field `CLKSL` reader - 0:0\\]
Reserved"]
pub type ClkslR = crate :: BitReader ; # [doc = "Field `CLKSL` writer - 0:0\\]
Reserved"]
pub type ClkslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXSL` reader - 1:1\\]
SCIRX PIN value"]
pub type RxslR = crate :: BitReader ; # [doc = "Field `RXSL` writer - 1:1\\]
SCIRX PIN value"]
pub type RxslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXSL` reader - 2:2\\]
SCITX PIN value"]
pub type TxslR = crate :: BitReader ; # [doc = "Field `TXSL` writer - 2:2\\]
SCITX PIN value"]
pub type TxslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn clksl (& self) -> ClkslR { ClkslR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SCIRX PIN value"]
# [inline (always)]
pub fn rxsl (& self) -> RxslR { RxslR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SCITX PIN value"]
# [inline (always)]
pub fn txsl (& self) -> TxslR { TxslR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clksl (& mut self) -> ClkslW < Scipio9Spec > { ClkslW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SCIRX PIN value"]
# [inline (always)]
# [must_use]
pub fn rxsl (& mut self) -> RxslW < Scipio9Spec > { RxslW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SCITX PIN value"]
# [inline (always)]
# [must_use]
pub fn txsl (& mut self) -> TxslW < Scipio9Spec > { TxslW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scipio9Spec > { Reserved1W :: new (self , 16) } } # [doc = "Couldn't find this register in spec. But it's mentioned in RTL.\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio9Spec ; impl crate :: RegisterSpec for Scipio9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio9::R`](R) reader structure"]
impl crate :: Readable for Scipio9Spec { } # [doc = "`write(|w| ..)` method takes [`scipio9::W`](W) writer structure"]
impl crate :: Writable for Scipio9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO9 to value 0"]
impl crate :: Resettable for Scipio9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved`]
module"]
pub type Reserved = crate :: Reg < reserved :: ReservedSpec > ; # [doc = "Reserved"]
pub mod reserved { # [doc = "Register `Reserved` reader"]
pub type R = crate :: R < ReservedSpec > ; # [doc = "Register `Reserved` writer"]
pub type W = crate :: W < ReservedSpec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ReservedSpec ; impl crate :: RegisterSpec for ReservedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved::R`](R) reader structure"]
impl crate :: Readable for ReservedSpec { } # [doc = "`write(|w| ..)` method takes [`reserved::W`](W) writer structure"]
impl crate :: Writable for ReservedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved to value 0"]
impl crate :: Resettable for ReservedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved1 (rw) register accessor: Reserved1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "Reserved1"]
pub mod reserved1 { # [doc = "Register `Reserved1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `Reserved1` writer"]
pub type W = crate :: W < Reserved1Spec > ; impl W { } # [doc = "Reserved1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved2 (rw) register accessor: Reserved2\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved2`]
module"]
pub type Reserved2 = crate :: Reg < reserved2 :: Reserved2Spec > ; # [doc = "Reserved2"]
pub mod reserved2 { # [doc = "Register `Reserved2` reader"]
pub type R = crate :: R < Reserved2Spec > ; # [doc = "Register `Reserved2` writer"]
pub type W = crate :: W < Reserved2Spec > ; impl W { } # [doc = "Reserved2\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved2Spec ; impl crate :: RegisterSpec for Reserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved2::R`](R) reader structure"]
impl crate :: Readable for Reserved2Spec { } # [doc = "`write(|w| ..)` method takes [`reserved2::W`](W) writer structure"]
impl crate :: Writable for Reserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved2 to value 0"]
impl crate :: Resettable for Reserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IODFTCTRL (rw) register accessor: The IODFTCTRL register is used to emulate various error and test conditions.\n\nYou can [`read`](crate::Reg::read) this register and get [`iodftctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iodftctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iodftctrl`]
module"]
# [doc (alias = "IODFTCTRL")]
pub type Iodftctrl = crate :: Reg < iodftctrl :: IodftctrlSpec > ; # [doc = "The IODFTCTRL register is used to emulate various error and test conditions."]
pub mod iodftctrl { # [doc = "Register `IODFTCTRL` reader"]
pub type R = crate :: R < IodftctrlSpec > ; # [doc = "Register `IODFTCTRL` writer"]
pub type W = crate :: W < IodftctrlSpec > ; # [doc = "Field `RXPENA` reader - 0:0\\]
Module Analog loopback through receive pin enable. This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. Writable Only in privilege mode"]
pub type RxpenaR = crate :: BitReader ; # [doc = "Field `RXPENA` writer - 0:0\\]
Module Analog loopback through receive pin enable. This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. Writable Only in privilege mode"]
pub type RxpenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LPBENA` reader - 1:1\\]
Module loopback enable. In analog loopback mode the complete communication path through the I/Os can be tested, whereas in digital loopback mode the I/O buffers are excluded from this path. Writable Only in privilege mode"]
pub type LpbenaR = crate :: BitReader ; # [doc = "Field `LPBENA` writer - 1:1\\]
Module loopback enable. In analog loopback mode the complete communication path through the I/Os can be tested, whereas in digital loopback mode the I/O buffers are excluded from this path. Writable Only in privilege mode"]
pub type LpbenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IODFTENA` reader - 11:8\\]
IO DFT Enable Key This field is used to enable the IODFT mode of the SCI/LIN module for testing. Writable Only in privilege mode"]
pub type IodftenaR = crate :: FieldReader ; # [doc = "Field `IODFTENA` writer - 11:8\\]
IO DFT Enable Key This field is used to enable the IODFT mode of the SCI/LIN module for testing. Writable Only in privilege mode"]
pub type IodftenaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `Reserved1` reader - 15:12\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:12\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXSHIFT` reader - 18:16\\]
Transmit shift. These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. (Not applicable to Start Bit)"]
pub type TxshiftR = crate :: FieldReader ; # [doc = "Field `TXSHIFT` writer - 18:16\\]
Transmit shift. These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. (Not applicable to Start Bit)"]
pub type TxshiftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PINSAMPLEMASK` reader - 20:19\\]
Pin sample mask. These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry. Note: During IODFT mode testing for the pin sample mask, the prescalar P must be programmed to be greater than 2."]
pub type PinsamplemaskR = crate :: FieldReader ; # [doc = "Field `PINSAMPLEMASK` writer - 20:19\\]
Pin sample mask. These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry. Note: During IODFT mode testing for the pin sample mask, the prescalar P must be programmed to be greater than 2."]
pub type PinsamplemaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved2` reader - 23:21\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 23:21\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BRKDTERRENA` reader - 24:24\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error (SCI mode only). When this bit is set, the stop bit of the frame is ANDed with ΓÇÖ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX Pin is forced to continuous low for 10 Tbits so that a BRKDT error occurs."]
pub type BrkdterrenaR = crate :: BitReader ; # [doc = "Field `BRKDTERRENA` writer - 24:24\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error (SCI mode only). When this bit is set, the stop bit of the frame is ANDed with ΓÇÖ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX Pin is forced to continuous low for 10 Tbits so that a BRKDT error occurs."]
pub type BrkdterrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PERRENA` reader - 25:25\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set, in compatible mode, the parity bit received is toggled so that a parity error occurs."]
pub type PerrenaR = crate :: BitReader ; # [doc = "Field `PERRENA` writer - 25:25\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set, in compatible mode, the parity bit received is toggled so that a parity error occurs."]
pub type PerrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FERRENA` reader - 26:26\\]
This bit is used to create a Frame Error. This bit is effective in SCI-compatible mode only. When this bit is set, the stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry."]
pub type FerrenaR = crate :: BitReader ; # [doc = "Field `FERRENA` writer - 26:26\\]
This bit is used to create a Frame Error. This bit is effective in SCI-compatible mode only. When this bit is set, the stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry."]
pub type FerrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 27:27\\]
Reserved"]
pub type Reserved3R = crate :: BitReader ; # [doc = "Field `Reserved3` writer - 27:27\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ISFERRENA` reader - 28:28\\]
Inconsistent Sync Field Error Enable bit. This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set, the bit widths in the sync field are varied so that the ISF check fails and the error flag is set."]
pub type IsferrenaR = crate :: BitReader ; # [doc = "Field `ISFERRENA` writer - 28:28\\]
Inconsistent Sync Field Error Enable bit. This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set, the bit widths in the sync field are varied so that the ISF check fails and the error flag is set."]
pub type IsferrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CERRENA` reader - 29:29\\]
Checksum Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set, the polarity of the CTYPE (checksum type) in the receive checksum calculator is changed so that a checksum error is generated."]
pub type CerrenaR = crate :: BitReader ; # [doc = "Field `CERRENA` writer - 29:29\\]
Checksum Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set, the polarity of the CTYPE (checksum type) in the receive checksum calculator is changed so that a checksum error is generated."]
pub type CerrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PBERRENA` reader - 30:30\\]
Physical Bus Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set, the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor circuitry"]
pub type PberrenaR = crate :: BitReader ; # [doc = "Field `PBERRENA` writer - 30:30\\]
Physical Bus Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set, the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor circuitry"]
pub type PberrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BERRENA` reader - 31:31\\]
Bit Errror Enable bit. This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set, the bit received is ORed with 1 and passed to the Bit monitor circuitry."]
pub type BerrenaR = crate :: BitReader ; # [doc = "Field `BERRENA` writer - 31:31\\]
Bit Errror Enable bit. This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set, the bit received is ORed with 1 and passed to the Bit monitor circuitry."]
pub type BerrenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Module Analog loopback through receive pin enable. This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. Writable Only in privilege mode"]
# [inline (always)]
pub fn rxpena (& self) -> RxpenaR { RxpenaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Module loopback enable. In analog loopback mode the complete communication path through the I/Os can be tested, whereas in digital loopback mode the I/O buffers are excluded from this path. Writable Only in privilege mode"]
# [inline (always)]
pub fn lpbena (& self) -> LpbenaR { LpbenaR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 8:11 - 11:8\\]
IO DFT Enable Key This field is used to enable the IODFT mode of the SCI/LIN module for testing. Writable Only in privilege mode"]
# [inline (always)]
pub fn iodftena (& self) -> IodftenaR { IodftenaR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:18 - 18:16\\]
Transmit shift. These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. (Not applicable to Start Bit)"]
# [inline (always)]
pub fn txshift (& self) -> TxshiftR { TxshiftR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bits 19:20 - 20:19\\]
Pin sample mask. These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry. Note: During IODFT mode testing for the pin sample mask, the prescalar P must be programmed to be greater than 2."]
# [inline (always)]
pub fn pinsamplemask (& self) -> PinsamplemaskR { PinsamplemaskR :: new (((self . bits >> 19) & 3) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error (SCI mode only). When this bit is set, the stop bit of the frame is ANDed with ΓÇÖ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX Pin is forced to continuous low for 10 Tbits so that a BRKDT error occurs."]
# [inline (always)]
pub fn brkdterrena (& self) -> BrkdterrenaR { BrkdterrenaR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set, in compatible mode, the parity bit received is toggled so that a parity error occurs."]
# [inline (always)]
pub fn perrena (& self) -> PerrenaR { PerrenaR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
This bit is used to create a Frame Error. This bit is effective in SCI-compatible mode only. When this bit is set, the stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry."]
# [inline (always)]
pub fn ferrena (& self) -> FerrenaR { FerrenaR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Inconsistent Sync Field Error Enable bit. This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set, the bit widths in the sync field are varied so that the ISF check fails and the error flag is set."]
# [inline (always)]
pub fn isferrena (& self) -> IsferrenaR { IsferrenaR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Checksum Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set, the polarity of the CTYPE (checksum type) in the receive checksum calculator is changed so that a checksum error is generated."]
# [inline (always)]
pub fn cerrena (& self) -> CerrenaR { CerrenaR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Physical Bus Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set, the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor circuitry"]
# [inline (always)]
pub fn pberrena (& self) -> PberrenaR { PberrenaR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Bit Errror Enable bit. This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set, the bit received is ORed with 1 and passed to the Bit monitor circuitry."]
# [inline (always)]
pub fn berrena (& self) -> BerrenaR { BerrenaR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Module Analog loopback through receive pin enable. This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. Writable Only in privilege mode"]
# [inline (always)]
# [must_use]
pub fn rxpena (& mut self) -> RxpenaW < IodftctrlSpec > { RxpenaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Module loopback enable. In analog loopback mode the complete communication path through the I/Os can be tested, whereas in digital loopback mode the I/O buffers are excluded from this path. Writable Only in privilege mode"]
# [inline (always)]
# [must_use]
pub fn lpbena (& mut self) -> LpbenaW < IodftctrlSpec > { LpbenaW :: new (self , 1) } # [doc = "Bits 8:11 - 11:8\\]
IO DFT Enable Key This field is used to enable the IODFT mode of the SCI/LIN module for testing. Writable Only in privilege mode"]
# [inline (always)]
# [must_use]
pub fn iodftena (& mut self) -> IodftenaW < IodftctrlSpec > { IodftenaW :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < IodftctrlSpec > { Reserved1W :: new (self , 12) } # [doc = "Bits 16:18 - 18:16\\]
Transmit shift. These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. (Not applicable to Start Bit)"]
# [inline (always)]
# [must_use]
pub fn txshift (& mut self) -> TxshiftW < IodftctrlSpec > { TxshiftW :: new (self , 16) } # [doc = "Bits 19:20 - 20:19\\]
Pin sample mask. These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry. Note: During IODFT mode testing for the pin sample mask, the prescalar P must be programmed to be greater than 2."]
# [inline (always)]
# [must_use]
pub fn pinsamplemask (& mut self) -> PinsamplemaskW < IodftctrlSpec > { PinsamplemaskW :: new (self , 19) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < IodftctrlSpec > { Reserved2W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error (SCI mode only). When this bit is set, the stop bit of the frame is ANDed with ΓÇÖ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX Pin is forced to continuous low for 10 Tbits so that a BRKDT error occurs."]
# [inline (always)]
# [must_use]
pub fn brkdterrena (& mut self) -> BrkdterrenaW < IodftctrlSpec > { BrkdterrenaW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set, in compatible mode, the parity bit received is toggled so that a parity error occurs."]
# [inline (always)]
# [must_use]
pub fn perrena (& mut self) -> PerrenaW < IodftctrlSpec > { PerrenaW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
This bit is used to create a Frame Error. This bit is effective in SCI-compatible mode only. When this bit is set, the stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry."]
# [inline (always)]
# [must_use]
pub fn ferrena (& mut self) -> FerrenaW < IodftctrlSpec > { FerrenaW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < IodftctrlSpec > { Reserved3W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Inconsistent Sync Field Error Enable bit. This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set, the bit widths in the sync field are varied so that the ISF check fails and the error flag is set."]
# [inline (always)]
# [must_use]
pub fn isferrena (& mut self) -> IsferrenaW < IodftctrlSpec > { IsferrenaW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Checksum Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set, the polarity of the CTYPE (checksum type) in the receive checksum calculator is changed so that a checksum error is generated."]
# [inline (always)]
# [must_use]
pub fn cerrena (& mut self) -> CerrenaW < IodftctrlSpec > { CerrenaW :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Physical Bus Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set, the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor circuitry"]
# [inline (always)]
# [must_use]
pub fn pberrena (& mut self) -> PberrenaW < IodftctrlSpec > { PberrenaW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Bit Errror Enable bit. This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set, the bit received is ORed with 1 and passed to the Bit monitor circuitry."]
# [inline (always)]
# [must_use]
pub fn berrena (& mut self) -> BerrenaW < IodftctrlSpec > { BerrenaW :: new (self , 31) } } # [doc = "The IODFTCTRL register is used to emulate various error and test conditions.\n\nYou can [`read`](crate::Reg::read) this register and get [`iodftctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iodftctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IodftctrlSpec ; impl crate :: RegisterSpec for IodftctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iodftctrl::R`](R) reader structure"]
impl crate :: Readable for IodftctrlSpec { } # [doc = "`write(|w| ..)` method takes [`iodftctrl::W`](W) writer structure"]
impl crate :: Writable for IodftctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IODFTCTRL to value 0"]
impl crate :: Resettable for IodftctrlSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_UART"]
pub struct AppUart0 { _marker : PhantomData < * const () > } unsafe impl Send for AppUart0 { } impl AppUart0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_uart_0 :: RegisterBlock = 0x53f7_f000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_uart_0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppUart0 { type Target = app_uart_0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppUart0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppUart0") . finish () } } # [doc = "APP_UART"]
pub mod app_uart_0 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { scigcr0 : Scigcr0 , scigcr1 : Scigcr1 , reserved1 : Reserved1 , scisetint : Scisetint , sciclearint : Sciclearint , scisetintlvl : Scisetintlvl , sciclearintlvl : Sciclearintlvl , sciflr : Sciflr , sciintvect0 : Sciintvect0 , sciintvect1 : Sciintvect1 , scichar : Scichar , scibaud : Scibaud , scied : Scied , scird : Scird , scitd : Scitd , scipio0 : Scipio0 , scipio1 : Scipio1 , scipio2 : Scipio2 , scipio3 : Scipio3 , scipio4 : Scipio4 , scipio5 : Scipio5 , scipio6 : Scipio6 , scipio7 : Scipio7 , scipio8 : Scipio8 , reserved2 : Reserved2 , reserved3 : Reserved3 , reserved4 : Reserved4 , reserved5 : Reserved5 , reserved6 : Reserved6 , reserved7 : Reserved7 , reserved8 : Reserved8 , reserved9 : Reserved9 , scipio9 : Scipio9 , _reserved33 : [u8 ; 0x0c]
, sciiodctrl : Sciiodctrl , } impl RegisterBlock { # [doc = "0x00 - The SCIGCR0 register defines the module reset"]
# [inline (always)]
pub const fn scigcr0 (& self) -> & Scigcr0 { & self . scigcr0 } # [doc = "0x04 - The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI"]
# [inline (always)]
pub const fn scigcr1 (& self) -> & Scigcr1 { & self . scigcr1 } # [doc = "0x08 - Reserved"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0x0c - SCI Set Interrupt Register"]
# [inline (always)]
pub const fn scisetint (& self) -> & Scisetint { & self . scisetint } # [doc = "0x10 - SCI Clear Interrupt Register"]
# [inline (always)]
pub const fn sciclearint (& self) -> & Sciclearint { & self . sciclearint } # [doc = "0x14 - SCI Set Interrupt Level Register"]
# [inline (always)]
pub const fn scisetintlvl (& self) -> & Scisetintlvl { & self . scisetintlvl } # [doc = "0x18 - SCI Clear Interrupt Level Register"]
# [inline (always)]
pub const fn sciclearintlvl (& self) -> & Sciclearintlvl { & self . sciclearintlvl } # [doc = "0x1c - SCI Flags Register"]
# [inline (always)]
pub const fn sciflr (& self) -> & Sciflr { & self . sciflr } # [doc = "0x20 - SCI Interrupt Offset Vector 0 Register"]
# [inline (always)]
pub const fn sciintvect0 (& self) -> & Sciintvect0 { & self . sciintvect0 } # [doc = "0x24 - SCI Interrupt Offset Vector 1 Register"]
# [inline (always)]
pub const fn sciintvect1 (& self) -> & Sciintvect1 { & self . sciintvect1 } # [doc = "0x28 - SCI Character Control Register"]
# [inline (always)]
pub const fn scichar (& self) -> & Scichar { & self . scichar } # [doc = "0x2c - SCI Baud Rate Selection Register"]
# [inline (always)]
pub const fn scibaud (& self) -> & Scibaud { & self . scibaud } # [doc = "0x30 - Receiver Emulation Data Buffer"]
# [inline (always)]
pub const fn scied (& self) -> & Scied { & self . scied } # [doc = "0x34 - Receiver Data Buffer"]
# [inline (always)]
pub const fn scird (& self) -> & Scird { & self . scird } # [doc = "0x38 - Transmit Data Buffer Register"]
# [inline (always)]
pub const fn scitd (& self) -> & Scitd { & self . scitd } # [doc = "0x3c - SCI Pin I/O Control Register 0"]
# [inline (always)]
pub const fn scipio0 (& self) -> & Scipio0 { & self . scipio0 } # [doc = "0x40 - SCI Pin I/O Control Register 1"]
# [inline (always)]
pub const fn scipio1 (& self) -> & Scipio1 { & self . scipio1 } # [doc = "0x44 - SCI Pin I/O Control Register 2"]
# [inline (always)]
pub const fn scipio2 (& self) -> & Scipio2 { & self . scipio2 } # [doc = "0x48 - SCI Pin I/O Control Register 3"]
# [inline (always)]
pub const fn scipio3 (& self) -> & Scipio3 { & self . scipio3 } # [doc = "0x4c - SCI Pin I/O Control Register 4"]
# [inline (always)]
pub const fn scipio4 (& self) -> & Scipio4 { & self . scipio4 } # [doc = "0x50 - SCI Pin I/O Control Register 5"]
# [inline (always)]
pub const fn scipio5 (& self) -> & Scipio5 { & self . scipio5 } # [doc = "0x54 - SCI Pin I/O Control Register 6"]
# [inline (always)]
pub const fn scipio6 (& self) -> & Scipio6 { & self . scipio6 } # [doc = "0x58 - SCI Pin I/O Control Register 7"]
# [inline (always)]
pub const fn scipio7 (& self) -> & Scipio7 { & self . scipio7 } # [doc = "0x5c - SCI Pin I/O Control Register 8"]
# [inline (always)]
pub const fn scipio8 (& self) -> & Scipio8 { & self . scipio8 } # [doc = "0x60 - Reserved"]
# [inline (always)]
pub const fn reserved2 (& self) -> & Reserved2 { & self . reserved2 } # [doc = "0x64 - Reserved"]
# [inline (always)]
pub const fn reserved3 (& self) -> & Reserved3 { & self . reserved3 } # [doc = "0x68 - Reserved"]
# [inline (always)]
pub const fn reserved4 (& self) -> & Reserved4 { & self . reserved4 } # [doc = "0x6c - Reserved"]
# [inline (always)]
pub const fn reserved5 (& self) -> & Reserved5 { & self . reserved5 } # [doc = "0x70 - Reserved"]
# [inline (always)]
pub const fn reserved6 (& self) -> & Reserved6 { & self . reserved6 } # [doc = "0x74 - Reserved"]
# [inline (always)]
pub const fn reserved7 (& self) -> & Reserved7 { & self . reserved7 } # [doc = "0x78 - Reserved"]
# [inline (always)]
pub const fn reserved8 (& self) -> & Reserved8 { & self . reserved8 } # [doc = "0x7c - Reserved"]
# [inline (always)]
pub const fn reserved9 (& self) -> & Reserved9 { & self . reserved9 } # [doc = "0x80 - SCI Pin I/O Control Register 9"]
# [inline (always)]
pub const fn scipio9 (& self) -> & Scipio9 { & self . scipio9 } # [doc = "0x90 - SCI IO DFT Control"]
# [inline (always)]
pub const fn sciiodctrl (& self) -> & Sciiodctrl { & self . sciiodctrl } } # [doc = "SCIGCR0 (rw) register accessor: The SCIGCR0 register defines the module reset\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr0`]
module"]
# [doc (alias = "SCIGCR0")]
pub type Scigcr0 = crate :: Reg < scigcr0 :: Scigcr0Spec > ; # [doc = "The SCIGCR0 register defines the module reset"]
pub mod scigcr0 { # [doc = "Register `SCIGCR0` reader"]
pub type R = crate :: R < Scigcr0Spec > ; # [doc = "Register `SCIGCR0` writer"]
pub type W = crate :: W < Scigcr0Spec > ; # [doc = "Field `RESET` reader - 0:0\\]
GIO reset"]
pub type ResetR = crate :: BitReader ; # [doc = "Field `RESET` writer - 0:0\\]
GIO reset"]
pub type ResetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
GIO reset"]
# [inline (always)]
pub fn reset (& self) -> ResetR { ResetR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
GIO reset"]
# [inline (always)]
# [must_use]
pub fn reset (& mut self) -> ResetW < Scigcr0Spec > { ResetW :: new (self , 0) } } # [doc = "The SCIGCR0 register defines the module reset\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr0Spec ; impl crate :: RegisterSpec for Scigcr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr0::R`](R) reader structure"]
impl crate :: Readable for Scigcr0Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr0::W`](W) writer structure"]
impl crate :: Writable for Scigcr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR0 to value 0"]
impl crate :: Resettable for Scigcr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIGCR1 (rw) register accessor: The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr1`]
module"]
# [doc (alias = "SCIGCR1")]
pub type Scigcr1 = crate :: Reg < scigcr1 :: Scigcr1Spec > ; # [doc = "The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI"]
pub mod scigcr1 { # [doc = "Register `SCIGCR1` reader"]
pub type R = crate :: R < Scigcr1Spec > ; # [doc = "Register `SCIGCR1` writer"]
pub type W = crate :: W < Scigcr1Spec > ; # [doc = "Field `COMM_MODE` reader - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
pub type CommModeR = crate :: BitReader ; # [doc = "Field `COMM_MODE` writer - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
pub type CommModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMING_MODE` reader - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
pub type TimingModeR = crate :: BitReader ; # [doc = "Field `TIMING_MODE` writer - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
pub type TimingModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITY_ENA` reader - 2:2\\]
SCI parity enable"]
pub type ParityEnaR = crate :: BitReader ; # [doc = "Field `PARITY_ENA` writer - 2:2\\]
SCI parity enable"]
pub type ParityEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITY` reader - 3:3\\]
SCI parity odd/even selection"]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 3:3\\]
SCI parity odd/even selection"]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STOP` reader - 4:4\\]
SCI number of stop bits"]
pub type StopR = crate :: BitReader ; # [doc = "Field `STOP` writer - 4:4\\]
SCI number of stop bits"]
pub type StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLOCK` reader - 5:5\\]
SCI internal clock enable"]
pub type ClockR = crate :: BitReader ; # [doc = "Field `CLOCK` writer - 5:5\\]
SCI internal clock enable"]
pub type ClockW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 6:6\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `RESERVED1` writer - 6:6\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SW_nRESET` reader - 7:7\\]
Software reset (active low)"]
pub type SwNResetR = crate :: BitReader ; # [doc = "Field `SW_nRESET` writer - 7:7\\]
Software reset (active low)"]
pub type SwNResetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SLEEP` reader - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
pub type SleepR = crate :: BitReader ; # [doc = "Field `SLEEP` writer - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
pub type SleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POWERDOWN` reader - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
pub type PowerdownR = crate :: BitReader ; # [doc = "Field `POWERDOWN` writer - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
pub type PowerdownW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `LOOP_BACK` reader - 16:16\\]
Enable bit for loopback mode"]
pub type LoopBackR = crate :: BitReader ; # [doc = "Field `LOOP_BACK` writer - 16:16\\]
Enable bit for loopback mode"]
pub type LoopBackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONT` reader - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
pub type ContR = crate :: BitReader ; # [doc = "Field `CONT` writer - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
pub type ContW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 23:18\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:18\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RXENA` reader - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
pub type RxenaR = crate :: BitReader ; # [doc = "Field `RXENA` writer - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
pub type RxenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXENA` reader - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
pub type TxenaR = crate :: BitReader ; # [doc = "Field `TXENA` writer - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
pub type TxenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:26\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:26\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
# [inline (always)]
pub fn comm_mode (& self) -> CommModeR { CommModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
# [inline (always)]
pub fn timing_mode (& self) -> TimingModeR { TimingModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SCI parity enable"]
# [inline (always)]
pub fn parity_ena (& self) -> ParityEnaR { ParityEnaR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SCI parity odd/even selection"]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
SCI number of stop bits"]
# [inline (always)]
pub fn stop (& self) -> StopR { StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
SCI internal clock enable"]
# [inline (always)]
pub fn clock (& self) -> ClockR { ClockR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Software reset (active low)"]
# [inline (always)]
pub fn sw_n_reset (& self) -> SwNResetR { SwNResetR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
# [inline (always)]
pub fn sleep (& self) -> SleepR { SleepR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
# [inline (always)]
pub fn powerdown (& self) -> PowerdownR { PowerdownR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Enable bit for loopback mode"]
# [inline (always)]
pub fn loop_back (& self) -> LoopBackR { LoopBackR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
# [inline (always)]
pub fn cont (& self) -> ContR { ContR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 18) & 0x3f) as u8) } # [doc = "Bit 24 - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
# [inline (always)]
pub fn rxena (& self) -> RxenaR { RxenaR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
# [inline (always)]
pub fn txena (& self) -> TxenaR { TxenaR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
# [inline (always)]
# [must_use]
pub fn comm_mode (& mut self) -> CommModeW < Scigcr1Spec > { CommModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
# [inline (always)]
# [must_use]
pub fn timing_mode (& mut self) -> TimingModeW < Scigcr1Spec > { TimingModeW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SCI parity enable"]
# [inline (always)]
# [must_use]
pub fn parity_ena (& mut self) -> ParityEnaW < Scigcr1Spec > { ParityEnaW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SCI parity odd/even selection"]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < Scigcr1Spec > { ParityW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
SCI number of stop bits"]
# [inline (always)]
# [must_use]
pub fn stop (& mut self) -> StopW < Scigcr1Spec > { StopW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
SCI internal clock enable"]
# [inline (always)]
# [must_use]
pub fn clock (& mut self) -> ClockW < Scigcr1Spec > { ClockW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scigcr1Spec > { Reserved1W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Software reset (active low)"]
# [inline (always)]
# [must_use]
pub fn sw_n_reset (& mut self) -> SwNResetW < Scigcr1Spec > { SwNResetW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
# [inline (always)]
# [must_use]
pub fn sleep (& mut self) -> SleepW < Scigcr1Spec > { SleepW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
# [inline (always)]
# [must_use]
pub fn powerdown (& mut self) -> PowerdownW < Scigcr1Spec > { PowerdownW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < Scigcr1Spec > { Reserved2W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
Enable bit for loopback mode"]
# [inline (always)]
# [must_use]
pub fn loop_back (& mut self) -> LoopBackW < Scigcr1Spec > { LoopBackW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
# [inline (always)]
# [must_use]
pub fn cont (& mut self) -> ContW < Scigcr1Spec > { ContW :: new (self , 17) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < Scigcr1Spec > { Reserved3W :: new (self , 18) } # [doc = "Bit 24 - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
# [inline (always)]
# [must_use]
pub fn rxena (& mut self) -> RxenaW < Scigcr1Spec > { RxenaW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
# [inline (always)]
# [must_use]
pub fn txena (& mut self) -> TxenaW < Scigcr1Spec > { TxenaW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < Scigcr1Spec > { Reserved4W :: new (self , 26) } } # [doc = "The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr1Spec ; impl crate :: RegisterSpec for Scigcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr1::R`](R) reader structure"]
impl crate :: Readable for Scigcr1Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr1::W`](W) writer structure"]
impl crate :: Writable for Scigcr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR1 to value 0"]
impl crate :: Resettable for Scigcr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
# [doc (alias = "RESERVED1")]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "Reserved"]
pub mod reserved1 { # [doc = "Register `RESERVED1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `RESERVED1` writer"]
pub type W = crate :: W < Reserved1Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCISETINT (rw) register accessor: SCI Set Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scisetint`]
module"]
# [doc (alias = "SCISETINT")]
pub type Scisetint = crate :: Reg < scisetint :: ScisetintSpec > ; # [doc = "SCI Set Interrupt Register"]
pub mod scisetint { # [doc = "Register `SCISETINT` reader"]
pub type R = crate :: R < ScisetintSpec > ; # [doc = "Register `SCISETINT` writer"]
pub type W = crate :: W < ScisetintSpec > ; # [doc = "Field `SET_BRKDT_INT` reader - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetBrkdtIntR = crate :: BitReader ; # [doc = "Field `SET_BRKDT_INT` writer - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetBrkdtIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_WAKEUP_INT` reader - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetWakeupIntR = crate :: BitReader ; # [doc = "Field `SET_WAKEUP_INT` writer - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetWakeupIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `SET_TX_INT` reader - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxIntR = crate :: BitReader ; # [doc = "Field `SET_TX_INT` writer - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_INT` reader - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetRxIntR = crate :: BitReader ; # [doc = "Field `SET_RX_INT` writer - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetRxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `SET_TX_DMA` reader - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxDmaR = crate :: BitReader ; # [doc = "Field `SET_TX_DMA` writer - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_DMA` reader - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type SetRxDmaR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA` writer - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type SetRxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_DMA_ALL` reader - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
pub type SetRxDmaAllR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA_ALL` writer - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
pub type SetRxDmaAllW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 23:19\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:19\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SET_PE_INT` reader - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetPeIntR = crate :: BitReader ; # [doc = "Field `SET_PE_INT` writer - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetPeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_OE_INT` reader - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetOeIntR = crate :: BitReader ; # [doc = "Field `SET_OE_INT` writer - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetOeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_FE_INT` reader - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetFeIntR = crate :: BitReader ; # [doc = "Field `SET_FE_INT` writer - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetFeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:27\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:27\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_brkdt_int (& self) -> SetBrkdtIntR { SetBrkdtIntR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_wakeup_int (& self) -> SetWakeupIntR { SetWakeupIntR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_tx_int (& self) -> SetTxIntR { SetTxIntR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_rx_int (& self) -> SetRxIntR { SetRxIntR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_tx_dma (& self) -> SetTxDmaR { SetTxDmaR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn set_rx_dma (& self) -> SetRxDmaR { SetRxDmaR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
# [inline (always)]
pub fn set_rx_dma_all (& self) -> SetRxDmaAllR { SetRxDmaAllR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_pe_int (& self) -> SetPeIntR { SetPeIntR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_oe_int (& self) -> SetOeIntR { SetOeIntR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_fe_int (& self) -> SetFeIntR { SetFeIntR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_brkdt_int (& mut self) -> SetBrkdtIntW < ScisetintSpec > { SetBrkdtIntW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_wakeup_int (& mut self) -> SetWakeupIntW < ScisetintSpec > { SetWakeupIntW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < ScisetintSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_tx_int (& mut self) -> SetTxIntW < ScisetintSpec > { SetTxIntW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_rx_int (& mut self) -> SetRxIntW < ScisetintSpec > { SetRxIntW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < ScisetintSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_tx_dma (& mut self) -> SetTxDmaW < ScisetintSpec > { SetTxDmaW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn set_rx_dma (& mut self) -> SetRxDmaW < ScisetintSpec > { SetRxDmaW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
# [inline (always)]
# [must_use]
pub fn set_rx_dma_all (& mut self) -> SetRxDmaAllW < ScisetintSpec > { SetRxDmaAllW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < ScisetintSpec > { Reserved3W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_pe_int (& mut self) -> SetPeIntW < ScisetintSpec > { SetPeIntW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_oe_int (& mut self) -> SetOeIntW < ScisetintSpec > { SetOeIntW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_fe_int (& mut self) -> SetFeIntW < ScisetintSpec > { SetFeIntW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < ScisetintSpec > { Reserved4W :: new (self , 27) } } # [doc = "SCI Set Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScisetintSpec ; impl crate :: RegisterSpec for ScisetintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scisetint::R`](R) reader structure"]
impl crate :: Readable for ScisetintSpec { } # [doc = "`write(|w| ..)` method takes [`scisetint::W`](W) writer structure"]
impl crate :: Writable for ScisetintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCISETINT to value 0"]
impl crate :: Resettable for ScisetintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICLEARINT (rw) register accessor: SCI Clear Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciclearint`]
module"]
# [doc (alias = "SCICLEARINT")]
pub type Sciclearint = crate :: Reg < sciclearint :: SciclearintSpec > ; # [doc = "SCI Clear Interrupt Register"]
pub mod sciclearint { # [doc = "Register `SCICLEARINT` reader"]
pub type R = crate :: R < SciclearintSpec > ; # [doc = "Register `SCICLEARINT` writer"]
pub type W = crate :: W < SciclearintSpec > ; # [doc = "Field `CLR_BRKDT_INT` reader - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrBrkdtIntR = crate :: BitReader ; # [doc = "Field `CLR_BRKDT_INT` writer - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrBrkdtIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_WAKEUP_INT` reader - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrWakeupIntR = crate :: BitReader ; # [doc = "Field `CLR_WAKEUP_INT` writer - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrWakeupIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLR_TX_INT` reader - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrTxIntR = crate :: BitReader ; # [doc = "Field `CLR_TX_INT` writer - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrTxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_INT` reader - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrRxIntR = crate :: BitReader ; # [doc = "Field `CLR_RX_INT` writer - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrRxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLR_TX_DMA` reader - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrTxDmaR = crate :: BitReader ; # [doc = "Field `CLR_TX_DMA` writer - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrTxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_DMA` reader - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrRxDmaR = crate :: BitReader ; # [doc = "Field `CLR_RX_DMA` writer - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrRxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_DMA_ALL` reader - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
pub type ClrRxDmaAllR = crate :: BitReader ; # [doc = "Field `CLR_RX_DMA_ALL` writer - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
pub type ClrRxDmaAllW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 23:19\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:19\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLR_PE_INT` reader - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type ClrPeIntR = crate :: BitReader ; # [doc = "Field `CLR_PE_INT` writer - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type ClrPeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_OE_INT` reader - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrOeIntR = crate :: BitReader ; # [doc = "Field `CLR_OE_INT` writer - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrOeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_FE_INT` reader - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrFeIntR = crate :: BitReader ; # [doc = "Field `CLR_FE_INT` writer - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrFeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:27\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:27\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_brkdt_int (& self) -> ClrBrkdtIntR { ClrBrkdtIntR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_wakeup_int (& self) -> ClrWakeupIntR { ClrWakeupIntR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_tx_int (& self) -> ClrTxIntR { ClrTxIntR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_rx_int (& self) -> ClrRxIntR { ClrRxIntR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn clr_tx_dma (& self) -> ClrTxDmaR { ClrTxDmaR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn clr_rx_dma (& self) -> ClrRxDmaR { ClrRxDmaR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
# [inline (always)]
pub fn clr_rx_dma_all (& self) -> ClrRxDmaAllR { ClrRxDmaAllR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn clr_pe_int (& self) -> ClrPeIntR { ClrPeIntR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_oe_int (& self) -> ClrOeIntR { ClrOeIntR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_fe_int (& self) -> ClrFeIntR { ClrFeIntR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_brkdt_int (& mut self) -> ClrBrkdtIntW < SciclearintSpec > { ClrBrkdtIntW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_wakeup_int (& mut self) -> ClrWakeupIntW < SciclearintSpec > { ClrWakeupIntW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciclearintSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_tx_int (& mut self) -> ClrTxIntW < SciclearintSpec > { ClrTxIntW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_rx_int (& mut self) -> ClrRxIntW < SciclearintSpec > { ClrRxIntW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciclearintSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn clr_tx_dma (& mut self) -> ClrTxDmaW < SciclearintSpec > { ClrTxDmaW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn clr_rx_dma (& mut self) -> ClrRxDmaW < SciclearintSpec > { ClrRxDmaW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
# [inline (always)]
# [must_use]
pub fn clr_rx_dma_all (& mut self) -> ClrRxDmaAllW < SciclearintSpec > { ClrRxDmaAllW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciclearintSpec > { Reserved3W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_pe_int (& mut self) -> ClrPeIntW < SciclearintSpec > { ClrPeIntW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_oe_int (& mut self) -> ClrOeIntW < SciclearintSpec > { ClrOeIntW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_fe_int (& mut self) -> ClrFeIntW < SciclearintSpec > { ClrFeIntW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciclearintSpec > { Reserved4W :: new (self , 27) } } # [doc = "SCI Clear Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciclearintSpec ; impl crate :: RegisterSpec for SciclearintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciclearint::R`](R) reader structure"]
impl crate :: Readable for SciclearintSpec { } # [doc = "`write(|w| ..)` method takes [`sciclearint::W`](W) writer structure"]
impl crate :: Writable for SciclearintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICLEARINT to value 0"]
impl crate :: Resettable for SciclearintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCISETINTLVL (rw) register accessor: SCI Set Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetintlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetintlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scisetintlvl`]
module"]
# [doc (alias = "SCISETINTLVL")]
pub type Scisetintlvl = crate :: Reg < scisetintlvl :: ScisetintlvlSpec > ; # [doc = "SCI Set Interrupt Level Register"]
pub mod scisetintlvl { # [doc = "Register `SCISETINTLVL` reader"]
pub type R = crate :: R < ScisetintlvlSpec > ; # [doc = "Register `SCISETINTLVL` writer"]
pub type W = crate :: W < ScisetintlvlSpec > ; # [doc = "Field `SET_BRKDT_INT_LVL` reader - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetBrkdtIntLvlR = crate :: BitReader ; # [doc = "Field `SET_BRKDT_INT_LVL` writer - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetBrkdtIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_WAKEUP_INT_LVL` reader - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetWakeupIntLvlR = crate :: BitReader ; # [doc = "Field `SET_WAKEUP_INT_LVL` writer - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetWakeupIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `SET_TX_INT_LVL` reader - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetTxIntLvlR = crate :: BitReader ; # [doc = "Field `SET_TX_INT_LVL` writer - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetTxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_INT_LVL` reader - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxIntLvlR = crate :: BitReader ; # [doc = "Field `SET_RX_INT_LVL` writer - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 14:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 14:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SET_INC_BR_INT_LVL` reader - 15:15\\]
Reserved"]
pub type SetIncBrIntLvlR = crate :: BitReader ; # [doc = "Field `SET_INC_BR_INT_LVL` writer - 15:15\\]
Reserved"]
pub type SetIncBrIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 17:16\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 17:16\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SET_RX_DMA_ALL_INT_LVL` reader - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxDmaAllIntLvlR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA_ALL_INT_LVL` writer - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxDmaAllIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 23:19\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 23:19\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SET_PE_INT_LVL` reader - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetPeIntLvlR = crate :: BitReader ; # [doc = "Field `SET_PE_INT_LVL` writer - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetPeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_OE_INT_LVL` reader - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetOeIntLvlR = crate :: BitReader ; # [doc = "Field `SET_OE_INT_LVL` writer - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetOeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_FE_INT_LVL` reader - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetFeIntLvlR = crate :: BitReader ; # [doc = "Field `SET_FE_INT_LVL` writer - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetFeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED5` reader - 31:27\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `RESERVED5` writer - 31:27\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_brkdt_int_lvl (& self) -> SetBrkdtIntLvlR { SetBrkdtIntLvlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_wakeup_int_lvl (& self) -> SetWakeupIntLvlR { SetWakeupIntLvlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_tx_int_lvl (& self) -> SetTxIntLvlR { SetTxIntLvlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_rx_int_lvl (& self) -> SetRxIntLvlR { SetRxIntLvlR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
pub fn set_inc_br_int_lvl (& self) -> SetIncBrIntLvlR { SetIncBrIntLvlR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_rx_dma_all_int_lvl (& self) -> SetRxDmaAllIntLvlR { SetRxDmaAllIntLvlR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_pe_int_lvl (& self) -> SetPeIntLvlR { SetPeIntLvlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_oe_int_lvl (& self) -> SetOeIntLvlR { SetOeIntLvlR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_fe_int_lvl (& self) -> SetFeIntLvlR { SetFeIntLvlR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_brkdt_int_lvl (& mut self) -> SetBrkdtIntLvlW < ScisetintlvlSpec > { SetBrkdtIntLvlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_wakeup_int_lvl (& mut self) -> SetWakeupIntLvlW < ScisetintlvlSpec > { SetWakeupIntLvlW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < ScisetintlvlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_tx_int_lvl (& mut self) -> SetTxIntLvlW < ScisetintlvlSpec > { SetTxIntLvlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_rx_int_lvl (& mut self) -> SetRxIntLvlW < ScisetintlvlSpec > { SetRxIntLvlW :: new (self , 9) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < ScisetintlvlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn set_inc_br_int_lvl (& mut self) -> SetIncBrIntLvlW < ScisetintlvlSpec > { SetIncBrIntLvlW :: new (self , 15) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < ScisetintlvlSpec > { Reserved3W :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_rx_dma_all_int_lvl (& mut self) -> SetRxDmaAllIntLvlW < ScisetintlvlSpec > { SetRxDmaAllIntLvlW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < ScisetintlvlSpec > { Reserved4W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_pe_int_lvl (& mut self) -> SetPeIntLvlW < ScisetintlvlSpec > { SetPeIntLvlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_oe_int_lvl (& mut self) -> SetOeIntLvlW < ScisetintlvlSpec > { SetOeIntLvlW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_fe_int_lvl (& mut self) -> SetFeIntLvlW < ScisetintlvlSpec > { SetFeIntLvlW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < ScisetintlvlSpec > { Reserved5W :: new (self , 27) } } # [doc = "SCI Set Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetintlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetintlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScisetintlvlSpec ; impl crate :: RegisterSpec for ScisetintlvlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scisetintlvl::R`](R) reader structure"]
impl crate :: Readable for ScisetintlvlSpec { } # [doc = "`write(|w| ..)` method takes [`scisetintlvl::W`](W) writer structure"]
impl crate :: Writable for ScisetintlvlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCISETINTLVL to value 0"]
impl crate :: Resettable for ScisetintlvlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICLEARINTLVL (rw) register accessor: SCI Clear Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearintlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearintlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciclearintlvl`]
module"]
# [doc (alias = "SCICLEARINTLVL")]
pub type Sciclearintlvl = crate :: Reg < sciclearintlvl :: SciclearintlvlSpec > ; # [doc = "SCI Clear Interrupt Level Register"]
pub mod sciclearintlvl { # [doc = "Register `SCICLEARINTLVL` reader"]
pub type R = crate :: R < SciclearintlvlSpec > ; # [doc = "Register `SCICLEARINTLVL` writer"]
pub type W = crate :: W < SciclearintlvlSpec > ; # [doc = "Field `CLR_BRKDT_INT_LVL` reader - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrBrkdtIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_BRKDT_INT_LVL` writer - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrBrkdtIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_WAKEUP_INT_LVL` reader - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrWakeupIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_WAKEUP_INT_LVL` writer - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrWakeupIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLR_TX_INT_LVL` reader - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrTxIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_TX_INT_LVL` writer - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrTxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_INT_LVL` reader - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrRxIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_RX_INT_LVL` writer - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrRxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 14:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 14:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLR_INC_BR_INT_LVL` reader - "]
pub type ClrIncBrIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_INC_BR_INT_LVL` writer - "]
pub type ClrIncBrIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 17:16\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 17:16\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_RX_DMA_ALL_INT_LVL` reader - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
pub type ClrRxDmaAllIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_RX_DMA_ALL_INT_LVL` writer - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
pub type ClrRxDmaAllIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 23:19\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 23:19\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLR_PE_INT_LVL` reader - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrPeIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_PE_INT_LVL` writer - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrPeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_OE_INT_LVL` reader - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrOeIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_OE_INT_LVL` writer - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrOeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_FE_INT_LVL` reader - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrFeIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_FE_INT_LVL` writer - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrFeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED5` reader - 31:27\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `RESERVED5` writer - 31:27\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_brkdt_int_lvl (& self) -> ClrBrkdtIntLvlR { ClrBrkdtIntLvlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_wakeup_int_lvl (& self) -> ClrWakeupIntLvlR { ClrWakeupIntLvlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_tx_int_lvl (& self) -> ClrTxIntLvlR { ClrTxIntLvlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_rx_int_lvl (& self) -> ClrRxIntLvlR { ClrRxIntLvlR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bit 15"]
# [inline (always)]
pub fn clr_inc_br_int_lvl (& self) -> ClrIncBrIntLvlR { ClrIncBrIntLvlR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
# [inline (always)]
pub fn clr_rx_dma_all_int_lvl (& self) -> ClrRxDmaAllIntLvlR { ClrRxDmaAllIntLvlR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_pe_int_lvl (& self) -> ClrPeIntLvlR { ClrPeIntLvlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_oe_int_lvl (& self) -> ClrOeIntLvlR { ClrOeIntLvlR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_fe_int_lvl (& self) -> ClrFeIntLvlR { ClrFeIntLvlR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_brkdt_int_lvl (& mut self) -> ClrBrkdtIntLvlW < SciclearintlvlSpec > { ClrBrkdtIntLvlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_wakeup_int_lvl (& mut self) -> ClrWakeupIntLvlW < SciclearintlvlSpec > { ClrWakeupIntLvlW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciclearintlvlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_tx_int_lvl (& mut self) -> ClrTxIntLvlW < SciclearintlvlSpec > { ClrTxIntLvlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_rx_int_lvl (& mut self) -> ClrRxIntLvlW < SciclearintlvlSpec > { ClrRxIntLvlW :: new (self , 9) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciclearintlvlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 15"]
# [inline (always)]
# [must_use]
pub fn clr_inc_br_int_lvl (& mut self) -> ClrIncBrIntLvlW < SciclearintlvlSpec > { ClrIncBrIntLvlW :: new (self , 15) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciclearintlvlSpec > { Reserved3W :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
# [inline (always)]
# [must_use]
pub fn clr_rx_dma_all_int_lvl (& mut self) -> ClrRxDmaAllIntLvlW < SciclearintlvlSpec > { ClrRxDmaAllIntLvlW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciclearintlvlSpec > { Reserved4W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_pe_int_lvl (& mut self) -> ClrPeIntLvlW < SciclearintlvlSpec > { ClrPeIntLvlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_oe_int_lvl (& mut self) -> ClrOeIntLvlW < SciclearintlvlSpec > { ClrOeIntLvlW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_fe_int_lvl (& mut self) -> ClrFeIntLvlW < SciclearintlvlSpec > { ClrFeIntLvlW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < SciclearintlvlSpec > { Reserved5W :: new (self , 27) } } # [doc = "SCI Clear Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearintlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearintlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciclearintlvlSpec ; impl crate :: RegisterSpec for SciclearintlvlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciclearintlvl::R`](R) reader structure"]
impl crate :: Readable for SciclearintlvlSpec { } # [doc = "`write(|w| ..)` method takes [`sciclearintlvl::W`](W) writer structure"]
impl crate :: Writable for SciclearintlvlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICLEARINTLVL to value 0"]
impl crate :: Resettable for SciclearintlvlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIFLR (rw) register accessor: SCI Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciflr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciflr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciflr`]
module"]
# [doc (alias = "SCIFLR")]
pub type Sciflr = crate :: Reg < sciflr :: SciflrSpec > ; # [doc = "SCI Flags Register"]
pub mod sciflr { # [doc = "Register `SCIFLR` reader"]
pub type R = crate :: R < SciflrSpec > ; # [doc = "Register `SCIFLR` writer"]
pub type W = crate :: W < SciflrSpec > ; # [doc = "Field `BRKDT` reader - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
pub type BrkdtR = crate :: BitReader ; # [doc = "Field `BRKDT` writer - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
pub type BrkdtW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKEUP` reader - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
pub type WakeupR = crate :: BitReader ; # [doc = "Field `WAKEUP` writer - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
pub type WakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDLE` reader - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
pub type IdleR = crate :: BitReader ; # [doc = "Field `IDLE` writer - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
pub type IdleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Bus_busy_flag` reader - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
pub type BusBusyFlagR = crate :: BitReader ; # [doc = "Field `Bus_busy_flag` writer - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
pub type BusBusyFlagW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:4\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:4\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXRDY` reader - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
pub type TxrdyR = crate :: BitReader ; # [doc = "Field `TXRDY` writer - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
pub type TxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXRDY` reader - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
pub type RxrdyR = crate :: BitReader ; # [doc = "Field `RXRDY` writer - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
pub type RxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXWAKE` reader - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
pub type TxwakeR = crate :: BitReader ; # [doc = "Field `TXWAKE` writer - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
pub type TxwakeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_EMPTY` reader - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
pub type TxEmptyR = crate :: BitReader ; # [doc = "Field `TX_EMPTY` writer - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
pub type TxEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXWAKE` reader - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
pub type RxwakeR = crate :: BitReader ; # [doc = "Field `RXWAKE` writer - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
pub type RxwakeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 23:13\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED2` writer - 23:13\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `PE` reader - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
pub type PeR = crate :: BitReader ; # [doc = "Field `PE` writer - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
pub type PeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OE` reader - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
pub type OeR = crate :: BitReader ; # [doc = "Field `OE` writer - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
pub type OeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FE` reader - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
pub type FeR = crate :: BitReader ; # [doc = "Field `FE` writer - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
pub type FeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 31:27\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 31:27\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
# [inline (always)]
pub fn brkdt (& self) -> BrkdtR { BrkdtR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
# [inline (always)]
pub fn wakeup (& self) -> WakeupR { WakeupR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
# [inline (always)]
pub fn idle (& self) -> IdleR { IdleR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
# [inline (always)]
pub fn bus_busy_flag (& self) -> BusBusyFlagR { BusBusyFlagR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
# [inline (always)]
pub fn txrdy (& self) -> TxrdyR { TxrdyR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
# [inline (always)]
pub fn rxrdy (& self) -> RxrdyR { RxrdyR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
# [inline (always)]
pub fn txwake (& self) -> TxwakeR { TxwakeR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
# [inline (always)]
pub fn tx_empty (& self) -> TxEmptyR { TxEmptyR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
# [inline (always)]
pub fn rxwake (& self) -> RxwakeR { RxwakeR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:23 - 23:13\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 13) & 0x07ff) as u16) } # [doc = "Bit 24 - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
# [inline (always)]
pub fn pe (& self) -> PeR { PeR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
# [inline (always)]
pub fn oe (& self) -> OeR { OeR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
# [inline (always)]
pub fn fe (& self) -> FeR { FeR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
# [inline (always)]
# [must_use]
pub fn brkdt (& mut self) -> BrkdtW < SciflrSpec > { BrkdtW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
# [inline (always)]
# [must_use]
pub fn wakeup (& mut self) -> WakeupW < SciflrSpec > { WakeupW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
# [inline (always)]
# [must_use]
pub fn idle (& mut self) -> IdleW < SciflrSpec > { IdleW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
# [inline (always)]
# [must_use]
pub fn bus_busy_flag (& mut self) -> BusBusyFlagW < SciflrSpec > { BusBusyFlagW :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciflrSpec > { Reserved1W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
# [inline (always)]
# [must_use]
pub fn txrdy (& mut self) -> TxrdyW < SciflrSpec > { TxrdyW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
# [inline (always)]
# [must_use]
pub fn rxrdy (& mut self) -> RxrdyW < SciflrSpec > { RxrdyW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
# [inline (always)]
# [must_use]
pub fn txwake (& mut self) -> TxwakeW < SciflrSpec > { TxwakeW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
# [inline (always)]
# [must_use]
pub fn tx_empty (& mut self) -> TxEmptyW < SciflrSpec > { TxEmptyW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
# [inline (always)]
# [must_use]
pub fn rxwake (& mut self) -> RxwakeW < SciflrSpec > { RxwakeW :: new (self , 12) } # [doc = "Bits 13:23 - 23:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciflrSpec > { Reserved2W :: new (self , 13) } # [doc = "Bit 24 - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
# [inline (always)]
# [must_use]
pub fn pe (& mut self) -> PeW < SciflrSpec > { PeW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
# [inline (always)]
# [must_use]
pub fn oe (& mut self) -> OeW < SciflrSpec > { OeW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
# [inline (always)]
# [must_use]
pub fn fe (& mut self) -> FeW < SciflrSpec > { FeW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciflrSpec > { Reserved3W :: new (self , 27) } } # [doc = "SCI Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciflr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciflr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciflrSpec ; impl crate :: RegisterSpec for SciflrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciflr::R`](R) reader structure"]
impl crate :: Readable for SciflrSpec { } # [doc = "`write(|w| ..)` method takes [`sciflr::W`](W) writer structure"]
impl crate :: Writable for SciflrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIFLR to value 0"]
impl crate :: Resettable for SciflrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIINTVECT0 (rw) register accessor: SCI Interrupt Offset Vector 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciintvect0`]
module"]
# [doc (alias = "SCIINTVECT0")]
pub type Sciintvect0 = crate :: Reg < sciintvect0 :: Sciintvect0Spec > ; # [doc = "SCI Interrupt Offset Vector 0 Register"]
pub mod sciintvect0 { # [doc = "Register `SCIINTVECT0` reader"]
pub type R = crate :: R < Sciintvect0Spec > ; # [doc = "Register `SCIINTVECT0` writer"]
pub type W = crate :: W < Sciintvect0Spec > ; # [doc = "Field `INTVECT0` reader - 3:0\\]
Interrupt vector offset for INT0"]
pub type Intvect0R = crate :: FieldReader ; # [doc = "Field `INTVECT0` writer - 3:0\\]
Interrupt vector offset for INT0"]
pub type Intvect0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT0"]
# [inline (always)]
pub fn intvect0 (& self) -> Intvect0R { Intvect0R :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT0"]
# [inline (always)]
# [must_use]
pub fn intvect0 (& mut self) -> Intvect0W < Sciintvect0Spec > { Intvect0W :: new (self , 0) } } # [doc = "SCI Interrupt Offset Vector 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sciintvect0Spec ; impl crate :: RegisterSpec for Sciintvect0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciintvect0::R`](R) reader structure"]
impl crate :: Readable for Sciintvect0Spec { } # [doc = "`write(|w| ..)` method takes [`sciintvect0::W`](W) writer structure"]
impl crate :: Writable for Sciintvect0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIINTVECT0 to value 0"]
impl crate :: Resettable for Sciintvect0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIINTVECT1 (rw) register accessor: SCI Interrupt Offset Vector 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciintvect1`]
module"]
# [doc (alias = "SCIINTVECT1")]
pub type Sciintvect1 = crate :: Reg < sciintvect1 :: Sciintvect1Spec > ; # [doc = "SCI Interrupt Offset Vector 1 Register"]
pub mod sciintvect1 { # [doc = "Register `SCIINTVECT1` reader"]
pub type R = crate :: R < Sciintvect1Spec > ; # [doc = "Register `SCIINTVECT1` writer"]
pub type W = crate :: W < Sciintvect1Spec > ; # [doc = "Field `INTVECT1` reader - 3:0\\]
Interrupt vector offset for INT1"]
pub type Intvect1R = crate :: FieldReader ; # [doc = "Field `INTVECT1` writer - 3:0\\]
Interrupt vector offset for INT1"]
pub type Intvect1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT1"]
# [inline (always)]
pub fn intvect1 (& self) -> Intvect1R { Intvect1R :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT1"]
# [inline (always)]
# [must_use]
pub fn intvect1 (& mut self) -> Intvect1W < Sciintvect1Spec > { Intvect1W :: new (self , 0) } } # [doc = "SCI Interrupt Offset Vector 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sciintvect1Spec ; impl crate :: RegisterSpec for Sciintvect1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciintvect1::R`](R) reader structure"]
impl crate :: Readable for Sciintvect1Spec { } # [doc = "`write(|w| ..)` method takes [`sciintvect1::W`](W) writer structure"]
impl crate :: Writable for Sciintvect1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIINTVECT1 to value 0"]
impl crate :: Resettable for Sciintvect1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICHAR (rw) register accessor: SCI Character Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scichar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scichar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scichar`]
module"]
# [doc (alias = "SCICHAR")]
pub type Scichar = crate :: Reg < scichar :: ScicharSpec > ; # [doc = "SCI Character Control Register"]
pub mod scichar { # [doc = "Register `SCICHAR` reader"]
pub type R = crate :: R < ScicharSpec > ; # [doc = "Register `SCICHAR` writer"]
pub type W = crate :: W < ScicharSpec > ; # [doc = "Field `CHAR` reader - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
pub type CharR = crate :: FieldReader ; # [doc = "Field `CHAR` writer - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
pub type CharW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
# [inline (always)]
pub fn char (& self) -> CharR { CharR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
# [inline (always)]
# [must_use]
pub fn char (& mut self) -> CharW < ScicharSpec > { CharW :: new (self , 0) } } # [doc = "SCI Character Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scichar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scichar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScicharSpec ; impl crate :: RegisterSpec for ScicharSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scichar::R`](R) reader structure"]
impl crate :: Readable for ScicharSpec { } # [doc = "`write(|w| ..)` method takes [`scichar::W`](W) writer structure"]
impl crate :: Writable for ScicharSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICHAR to value 0"]
impl crate :: Resettable for ScicharSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIBAUD (rw) register accessor: SCI Baud Rate Selection Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scibaud::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scibaud::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scibaud`]
module"]
# [doc (alias = "SCIBAUD")]
pub type Scibaud = crate :: Reg < scibaud :: ScibaudSpec > ; # [doc = "SCI Baud Rate Selection Register"]
pub mod scibaud { # [doc = "Register `SCIBAUD` reader"]
pub type R = crate :: R < ScibaudSpec > ; # [doc = "Register `SCIBAUD` writer"]
pub type W = crate :: W < ScibaudSpec > ; # [doc = "Field `BAUD` reader - 23:0\\]
SCI 24-bit baud selection"]
pub type BaudR = crate :: FieldReader < u32 > ; # [doc = "Field `BAUD` writer - 23:0\\]
SCI 24-bit baud selection"]
pub type BaudW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
SCI 24-bit baud selection"]
# [inline (always)]
pub fn baud (& self) -> BaudR { BaudR :: new (self . bits & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
SCI 24-bit baud selection"]
# [inline (always)]
# [must_use]
pub fn baud (& mut self) -> BaudW < ScibaudSpec > { BaudW :: new (self , 0) } } # [doc = "SCI Baud Rate Selection Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scibaud::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scibaud::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScibaudSpec ; impl crate :: RegisterSpec for ScibaudSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scibaud::R`](R) reader structure"]
impl crate :: Readable for ScibaudSpec { } # [doc = "`write(|w| ..)` method takes [`scibaud::W`](W) writer structure"]
impl crate :: Writable for ScibaudSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIBAUD to value 0"]
impl crate :: Resettable for ScibaudSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIED (rw) register accessor: Receiver Emulation Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scied::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scied::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scied`]
module"]
# [doc (alias = "SCIED")]
pub type Scied = crate :: Reg < scied :: SciedSpec > ; # [doc = "Receiver Emulation Data Buffer"]
pub mod scied { # [doc = "Register `SCIED` reader"]
pub type R = crate :: R < SciedSpec > ; # [doc = "Register `SCIED` writer"]
pub type W = crate :: W < SciedSpec > ; # [doc = "Field `ED` reader - 7:0\\]
Receiver Emulation Data Buffer"]
pub type EdR = crate :: FieldReader ; # [doc = "Field `ED` writer - 7:0\\]
Receiver Emulation Data Buffer"]
pub type EdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Receiver Emulation Data Buffer"]
# [inline (always)]
pub fn ed (& self) -> EdR { EdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Receiver Emulation Data Buffer"]
# [inline (always)]
# [must_use]
pub fn ed (& mut self) -> EdW < SciedSpec > { EdW :: new (self , 0) } } # [doc = "Receiver Emulation Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scied::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scied::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciedSpec ; impl crate :: RegisterSpec for SciedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scied::R`](R) reader structure"]
impl crate :: Readable for SciedSpec { } # [doc = "`write(|w| ..)` method takes [`scied::W`](W) writer structure"]
impl crate :: Writable for SciedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIED to value 0"]
impl crate :: Resettable for SciedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIRD (rw) register accessor: Receiver Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scird::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scird::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scird`]
module"]
# [doc (alias = "SCIRD")]
pub type Scird = crate :: Reg < scird :: ScirdSpec > ; # [doc = "Receiver Data Buffer"]
pub mod scird { # [doc = "Register `SCIRD` reader"]
pub type R = crate :: R < ScirdSpec > ; # [doc = "Register `SCIRD` writer"]
pub type W = crate :: W < ScirdSpec > ; # [doc = "Field `RD` reader - 7:0\\]
Contains received data."]
pub type RdR = crate :: FieldReader ; # [doc = "Field `RD` writer - 7:0\\]
Contains received data."]
pub type RdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Contains received data."]
# [inline (always)]
pub fn rd (& self) -> RdR { RdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Contains received data."]
# [inline (always)]
# [must_use]
pub fn rd (& mut self) -> RdW < ScirdSpec > { RdW :: new (self , 0) } } # [doc = "Receiver Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scird::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scird::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScirdSpec ; impl crate :: RegisterSpec for ScirdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scird::R`](R) reader structure"]
impl crate :: Readable for ScirdSpec { } # [doc = "`write(|w| ..)` method takes [`scird::W`](W) writer structure"]
impl crate :: Writable for ScirdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIRD to value 0"]
impl crate :: Resettable for ScirdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCITD (rw) register accessor: Transmit Data Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scitd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scitd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scitd`]
module"]
# [doc (alias = "SCITD")]
pub type Scitd = crate :: Reg < scitd :: ScitdSpec > ; # [doc = "Transmit Data Buffer Register"]
pub mod scitd { # [doc = "Register `SCITD` reader"]
pub type R = crate :: R < ScitdSpec > ; # [doc = "Register `SCITD` writer"]
pub type W = crate :: W < ScitdSpec > ; # [doc = "Field `TD` reader - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
pub type TdR = crate :: FieldReader ; # [doc = "Field `TD` writer - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
pub type TdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
# [inline (always)]
pub fn td (& self) -> TdR { TdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
# [inline (always)]
# [must_use]
pub fn td (& mut self) -> TdW < ScitdSpec > { TdW :: new (self , 0) } } # [doc = "Transmit Data Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scitd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scitd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScitdSpec ; impl crate :: RegisterSpec for ScitdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scitd::R`](R) reader structure"]
impl crate :: Readable for ScitdSpec { } # [doc = "`write(|w| ..)` method takes [`scitd::W`](W) writer structure"]
impl crate :: Writable for ScitdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCITD to value 0"]
impl crate :: Resettable for ScitdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO0 (rw) register accessor: SCI Pin I/O Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio0`]
module"]
# [doc (alias = "SCIPIO0")]
pub type Scipio0 = crate :: Reg < scipio0 :: Scipio0Spec > ; # [doc = "SCI Pin I/O Control Register 0"]
pub mod scipio0 { # [doc = "Register `SCIPIO0` reader"]
pub type R = crate :: R < Scipio0Spec > ; # [doc = "Register `SCIPIO0` writer"]
pub type W = crate :: W < Scipio0Spec > ; # [doc = "Field `CLK_FUNC` reader - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
pub type ClkFuncR = crate :: BitReader ; # [doc = "Field `CLK_FUNC` writer - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
pub type ClkFuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_FUNC` reader - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxFuncR = crate :: BitReader ; # [doc = "Field `RX_FUNC` writer - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxFuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_FUNC` reader - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
pub type TxFuncR = crate :: BitReader ; # [doc = "Field `TX_FUNC` writer - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
pub type TxFuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
# [inline (always)]
pub fn clk_func (& self) -> ClkFuncR { ClkFuncR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
pub fn rx_func (& self) -> RxFuncR { RxFuncR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
# [inline (always)]
pub fn tx_func (& self) -> TxFuncR { TxFuncR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
# [inline (always)]
# [must_use]
pub fn clk_func (& mut self) -> ClkFuncW < Scipio0Spec > { ClkFuncW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn rx_func (& mut self) -> RxFuncW < Scipio0Spec > { RxFuncW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
# [inline (always)]
# [must_use]
pub fn tx_func (& mut self) -> TxFuncW < Scipio0Spec > { TxFuncW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio0Spec ; impl crate :: RegisterSpec for Scipio0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio0::R`](R) reader structure"]
impl crate :: Readable for Scipio0Spec { } # [doc = "`write(|w| ..)` method takes [`scipio0::W`](W) writer structure"]
impl crate :: Writable for Scipio0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO0 to value 0"]
impl crate :: Resettable for Scipio0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO1 (rw) register accessor: SCI Pin I/O Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio1`]
module"]
# [doc (alias = "SCIPIO1")]
pub type Scipio1 = crate :: Reg < scipio1 :: Scipio1Spec > ; # [doc = "SCI Pin I/O Control Register 1"]
pub mod scipio1 { # [doc = "Register `SCIPIO1` reader"]
pub type R = crate :: R < Scipio1Spec > ; # [doc = "Register `SCIPIO1` writer"]
pub type W = crate :: W < Scipio1Spec > ; # [doc = "Field `CLK_DIR` reader - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
pub type ClkDirR = crate :: BitReader ; # [doc = "Field `CLK_DIR` writer - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
pub type ClkDirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DIR` reader - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxDirR = crate :: BitReader ; # [doc = "Field `RX_DIR` writer - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxDirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DIR` reader - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
pub type TxDirR = crate :: BitReader ; # [doc = "Field `TX_DIR` writer - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
pub type TxDirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
# [inline (always)]
pub fn clk_dir (& self) -> ClkDirR { ClkDirR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
pub fn rx_dir (& self) -> RxDirR { RxDirR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
# [inline (always)]
pub fn tx_dir (& self) -> TxDirR { TxDirR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn clk_dir (& mut self) -> ClkDirW < Scipio1Spec > { ClkDirW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn rx_dir (& mut self) -> RxDirW < Scipio1Spec > { RxDirW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn tx_dir (& mut self) -> TxDirW < Scipio1Spec > { TxDirW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio1Spec ; impl crate :: RegisterSpec for Scipio1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio1::R`](R) reader structure"]
impl crate :: Readable for Scipio1Spec { } # [doc = "`write(|w| ..)` method takes [`scipio1::W`](W) writer structure"]
impl crate :: Writable for Scipio1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO1 to value 0"]
impl crate :: Resettable for Scipio1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO2 (rw) register accessor: SCI Pin I/O Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio2`]
module"]
# [doc (alias = "SCIPIO2")]
pub type Scipio2 = crate :: Reg < scipio2 :: Scipio2Spec > ; # [doc = "SCI Pin I/O Control Register 2"]
pub mod scipio2 { # [doc = "Register `SCIPIO2` reader"]
pub type R = crate :: R < Scipio2Spec > ; # [doc = "Register `SCIPIO2` writer"]
pub type W = crate :: W < Scipio2Spec > ; # [doc = "Field `CLK_DATA_IN` reader - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
pub type ClkDataInR = crate :: BitReader ; # [doc = "Field `CLK_DATA_IN` writer - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
pub type ClkDataInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_IN` reader - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
pub type RxDataInR = crate :: BitReader ; # [doc = "Field `RX_DATA_IN` writer - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
pub type RxDataInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_IN` reader - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
pub type TxDataInR = crate :: BitReader ; # [doc = "Field `TX_DATA_IN` writer - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
pub type TxDataInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
# [inline (always)]
pub fn clk_data_in (& self) -> ClkDataInR { ClkDataInR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
# [inline (always)]
pub fn rx_data_in (& self) -> RxDataInR { RxDataInR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
# [inline (always)]
pub fn tx_data_in (& self) -> TxDataInR { TxDataInR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
# [inline (always)]
# [must_use]
pub fn clk_data_in (& mut self) -> ClkDataInW < Scipio2Spec > { ClkDataInW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
# [inline (always)]
# [must_use]
pub fn rx_data_in (& mut self) -> RxDataInW < Scipio2Spec > { RxDataInW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
# [inline (always)]
# [must_use]
pub fn tx_data_in (& mut self) -> TxDataInW < Scipio2Spec > { TxDataInW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio2Spec ; impl crate :: RegisterSpec for Scipio2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio2::R`](R) reader structure"]
impl crate :: Readable for Scipio2Spec { } # [doc = "`write(|w| ..)` method takes [`scipio2::W`](W) writer structure"]
impl crate :: Writable for Scipio2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO2 to value 0"]
impl crate :: Resettable for Scipio2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO3 (rw) register accessor: SCI Pin I/O Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio3`]
module"]
# [doc (alias = "SCIPIO3")]
pub type Scipio3 = crate :: Reg < scipio3 :: Scipio3Spec > ; # [doc = "SCI Pin I/O Control Register 3"]
pub mod scipio3 { # [doc = "Register `SCIPIO3` reader"]
pub type R = crate :: R < Scipio3Spec > ; # [doc = "Register `SCIPIO3` writer"]
pub type W = crate :: W < Scipio3Spec > ; # [doc = "Field `CLK_DATA_OUT` reader - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
pub type ClkDataOutR = crate :: BitReader ; # [doc = "Field `CLK_DATA_OUT` writer - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
pub type ClkDataOutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_OUT` reader - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
pub type RxDataOutR = crate :: BitReader ; # [doc = "Field `RX_DATA_OUT` writer - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
pub type RxDataOutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_OUT` reader - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
pub type TxDataOutR = crate :: BitReader ; # [doc = "Field `TX_DATA_OUT` writer - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
pub type TxDataOutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
# [inline (always)]
pub fn clk_data_out (& self) -> ClkDataOutR { ClkDataOutR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
# [inline (always)]
pub fn rx_data_out (& self) -> RxDataOutR { RxDataOutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
# [inline (always)]
pub fn tx_data_out (& self) -> TxDataOutR { TxDataOutR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
# [inline (always)]
# [must_use]
pub fn clk_data_out (& mut self) -> ClkDataOutW < Scipio3Spec > { ClkDataOutW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
# [inline (always)]
# [must_use]
pub fn rx_data_out (& mut self) -> RxDataOutW < Scipio3Spec > { RxDataOutW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
# [inline (always)]
# [must_use]
pub fn tx_data_out (& mut self) -> TxDataOutW < Scipio3Spec > { TxDataOutW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio3Spec ; impl crate :: RegisterSpec for Scipio3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio3::R`](R) reader structure"]
impl crate :: Readable for Scipio3Spec { } # [doc = "`write(|w| ..)` method takes [`scipio3::W`](W) writer structure"]
impl crate :: Writable for Scipio3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO3 to value 0"]
impl crate :: Resettable for Scipio3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO4 (rw) register accessor: SCI Pin I/O Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio4`]
module"]
# [doc (alias = "SCIPIO4")]
pub type Scipio4 = crate :: Reg < scipio4 :: Scipio4Spec > ; # [doc = "SCI Pin I/O Control Register 4"]
pub mod scipio4 { # [doc = "Register `SCIPIO4` reader"]
pub type R = crate :: R < Scipio4Spec > ; # [doc = "Register `SCIPIO4` writer"]
pub type W = crate :: W < Scipio4Spec > ; # [doc = "Field `CLK_DATA_SET` reader - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
pub type ClkDataSetR = crate :: BitReader ; # [doc = "Field `CLK_DATA_SET` writer - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
pub type ClkDataSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_SET` reader - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
pub type RxDataSetR = crate :: BitReader ; # [doc = "Field `RX_DATA_SET` writer - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
pub type RxDataSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_SET` reader - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataSetR = crate :: BitReader ; # [doc = "Field `TX_DATA_SET` writer - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
# [inline (always)]
pub fn clk_data_set (& self) -> ClkDataSetR { ClkDataSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
# [inline (always)]
pub fn rx_data_set (& self) -> RxDataSetR { RxDataSetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn tx_data_set (& self) -> TxDataSetR { TxDataSetR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn clk_data_set (& mut self) -> ClkDataSetW < Scipio4Spec > { ClkDataSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn rx_data_set (& mut self) -> RxDataSetW < Scipio4Spec > { RxDataSetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn tx_data_set (& mut self) -> TxDataSetW < Scipio4Spec > { TxDataSetW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio4Spec ; impl crate :: RegisterSpec for Scipio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio4::R`](R) reader structure"]
impl crate :: Readable for Scipio4Spec { } # [doc = "`write(|w| ..)` method takes [`scipio4::W`](W) writer structure"]
impl crate :: Writable for Scipio4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO4 to value 0"]
impl crate :: Resettable for Scipio4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO5 (rw) register accessor: SCI Pin I/O Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio5`]
module"]
# [doc (alias = "SCIPIO5")]
pub type Scipio5 = crate :: Reg < scipio5 :: Scipio5Spec > ; # [doc = "SCI Pin I/O Control Register 5"]
pub mod scipio5 { # [doc = "Register `SCIPIO5` reader"]
pub type R = crate :: R < Scipio5Spec > ; # [doc = "Register `SCIPIO5` writer"]
pub type W = crate :: W < Scipio5Spec > ; # [doc = "Field `CLK_DATA_CLR` reader - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type ClkDataClrR = crate :: BitReader ; # [doc = "Field `CLK_DATA_CLR` writer - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type ClkDataClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_CLR` reader - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type RxDataClrR = crate :: BitReader ; # [doc = "Field `RX_DATA_CLR` writer - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type RxDataClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_CLR` reader - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataClrR = crate :: BitReader ; # [doc = "Field `TX_DATA_CLR` writer - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn clk_data_clr (& self) -> ClkDataClrR { ClkDataClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn rx_data_clr (& self) -> RxDataClrR { RxDataClrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn tx_data_clr (& self) -> TxDataClrR { TxDataClrR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn clk_data_clr (& mut self) -> ClkDataClrW < Scipio5Spec > { ClkDataClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn rx_data_clr (& mut self) -> RxDataClrW < Scipio5Spec > { RxDataClrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn tx_data_clr (& mut self) -> TxDataClrW < Scipio5Spec > { TxDataClrW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio5Spec ; impl crate :: RegisterSpec for Scipio5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio5::R`](R) reader structure"]
impl crate :: Readable for Scipio5Spec { } # [doc = "`write(|w| ..)` method takes [`scipio5::W`](W) writer structure"]
impl crate :: Writable for Scipio5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO5 to value 0"]
impl crate :: Resettable for Scipio5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO6 (rw) register accessor: SCI Pin I/O Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio6`]
module"]
# [doc (alias = "SCIPIO6")]
pub type Scipio6 = crate :: Reg < scipio6 :: Scipio6Spec > ; # [doc = "SCI Pin I/O Control Register 6"]
pub mod scipio6 { # [doc = "Register `SCIPIO6` reader"]
pub type R = crate :: R < Scipio6Spec > ; # [doc = "Register `SCIPIO6` writer"]
pub type W = crate :: W < Scipio6Spec > ; # [doc = "Field `CLK_PDR` reader - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
pub type ClkPdrR = crate :: BitReader ; # [doc = "Field `CLK_PDR` writer - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
pub type ClkPdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_PDR` reader - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
pub type RxPdrR = crate :: BitReader ; # [doc = "Field `RX_PDR` writer - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
pub type RxPdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_PDR` reader - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
pub type TxPdrR = crate :: BitReader ; # [doc = "Field `TX_PDR` writer - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
pub type TxPdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
# [inline (always)]
pub fn clk_pdr (& self) -> ClkPdrR { ClkPdrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
# [inline (always)]
pub fn rx_pdr (& self) -> RxPdrR { RxPdrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
# [inline (always)]
pub fn tx_pdr (& self) -> TxPdrR { TxPdrR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
# [inline (always)]
# [must_use]
pub fn clk_pdr (& mut self) -> ClkPdrW < Scipio6Spec > { ClkPdrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
# [inline (always)]
# [must_use]
pub fn rx_pdr (& mut self) -> RxPdrW < Scipio6Spec > { RxPdrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
# [inline (always)]
# [must_use]
pub fn tx_pdr (& mut self) -> TxPdrW < Scipio6Spec > { TxPdrW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio6Spec ; impl crate :: RegisterSpec for Scipio6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio6::R`](R) reader structure"]
impl crate :: Readable for Scipio6Spec { } # [doc = "`write(|w| ..)` method takes [`scipio6::W`](W) writer structure"]
impl crate :: Writable for Scipio6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO6 to value 0"]
impl crate :: Resettable for Scipio6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO7 (rw) register accessor: SCI Pin I/O Control Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio7`]
module"]
# [doc (alias = "SCIPIO7")]
pub type Scipio7 = crate :: Reg < scipio7 :: Scipio7Spec > ; # [doc = "SCI Pin I/O Control Register 7"]
pub mod scipio7 { # [doc = "Register `SCIPIO7` reader"]
pub type R = crate :: R < Scipio7Spec > ; # [doc = "Register `SCIPIO7` writer"]
pub type W = crate :: W < Scipio7Spec > ; # [doc = "Field `CLK_PD` reader - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
pub type ClkPdR = crate :: BitReader ; # [doc = "Field `CLK_PD` writer - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
pub type ClkPdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_PD` reader - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
pub type RxPdR = crate :: BitReader ; # [doc = "Field `RX_PD` writer - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
pub type RxPdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_PD` reader - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
pub type TxPdR = crate :: BitReader ; # [doc = "Field `TX_PD` writer - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
pub type TxPdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
# [inline (always)]
pub fn clk_pd (& self) -> ClkPdR { ClkPdR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
# [inline (always)]
pub fn rx_pd (& self) -> RxPdR { RxPdR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
# [inline (always)]
pub fn tx_pd (& self) -> TxPdR { TxPdR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
# [inline (always)]
# [must_use]
pub fn clk_pd (& mut self) -> ClkPdW < Scipio7Spec > { ClkPdW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
# [inline (always)]
# [must_use]
pub fn rx_pd (& mut self) -> RxPdW < Scipio7Spec > { RxPdW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
# [inline (always)]
# [must_use]
pub fn tx_pd (& mut self) -> TxPdW < Scipio7Spec > { TxPdW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio7Spec ; impl crate :: RegisterSpec for Scipio7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio7::R`](R) reader structure"]
impl crate :: Readable for Scipio7Spec { } # [doc = "`write(|w| ..)` method takes [`scipio7::W`](W) writer structure"]
impl crate :: Writable for Scipio7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO7 to value 0"]
impl crate :: Resettable for Scipio7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO8 (rw) register accessor: SCI Pin I/O Control Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio8`]
module"]
# [doc (alias = "SCIPIO8")]
pub type Scipio8 = crate :: Reg < scipio8 :: Scipio8Spec > ; # [doc = "SCI Pin I/O Control Register 8"]
pub mod scipio8 { # [doc = "Register `SCIPIO8` reader"]
pub type R = crate :: R < Scipio8Spec > ; # [doc = "Register `SCIPIO8` writer"]
pub type W = crate :: W < Scipio8Spec > ; # [doc = "Field `CLK_PSL` reader - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
pub type ClkPslR = crate :: BitReader ; # [doc = "Field `CLK_PSL` writer - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
pub type ClkPslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_PSL` reader - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
pub type RxPslR = crate :: BitReader ; # [doc = "Field `RX_PSL` writer - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
pub type RxPslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_PSL` reader - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
pub type TxPslR = crate :: BitReader ; # [doc = "Field `TX_PSL` writer - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
pub type TxPslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
# [inline (always)]
pub fn clk_psl (& self) -> ClkPslR { ClkPslR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
# [inline (always)]
pub fn rx_psl (& self) -> RxPslR { RxPslR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
# [inline (always)]
pub fn tx_psl (& self) -> TxPslR { TxPslR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
# [inline (always)]
# [must_use]
pub fn clk_psl (& mut self) -> ClkPslW < Scipio8Spec > { ClkPslW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
# [inline (always)]
# [must_use]
pub fn rx_psl (& mut self) -> RxPslW < Scipio8Spec > { RxPslW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
# [inline (always)]
# [must_use]
pub fn tx_psl (& mut self) -> TxPslW < Scipio8Spec > { TxPslW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio8Spec ; impl crate :: RegisterSpec for Scipio8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio8::R`](R) reader structure"]
impl crate :: Readable for Scipio8Spec { } # [doc = "`write(|w| ..)` method takes [`scipio8::W`](W) writer structure"]
impl crate :: Writable for Scipio8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO8 to value 0"]
impl crate :: Resettable for Scipio8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved2`]
module"]
# [doc (alias = "RESERVED2")]
pub type Reserved2 = crate :: Reg < reserved2 :: Reserved2Spec > ; # [doc = "Reserved"]
pub mod reserved2 { # [doc = "Register `RESERVED2` reader"]
pub type R = crate :: R < Reserved2Spec > ; # [doc = "Register `RESERVED2` writer"]
pub type W = crate :: W < Reserved2Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved2Spec ; impl crate :: RegisterSpec for Reserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved2::R`](R) reader structure"]
impl crate :: Readable for Reserved2Spec { } # [doc = "`write(|w| ..)` method takes [`reserved2::W`](W) writer structure"]
impl crate :: Writable for Reserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED2 to value 0"]
impl crate :: Resettable for Reserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved3`]
module"]
# [doc (alias = "RESERVED3")]
pub type Reserved3 = crate :: Reg < reserved3 :: Reserved3Spec > ; # [doc = "Reserved"]
pub mod reserved3 { # [doc = "Register `RESERVED3` reader"]
pub type R = crate :: R < Reserved3Spec > ; # [doc = "Register `RESERVED3` writer"]
pub type W = crate :: W < Reserved3Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved3Spec ; impl crate :: RegisterSpec for Reserved3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved3::R`](R) reader structure"]
impl crate :: Readable for Reserved3Spec { } # [doc = "`write(|w| ..)` method takes [`reserved3::W`](W) writer structure"]
impl crate :: Writable for Reserved3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED3 to value 0"]
impl crate :: Resettable for Reserved3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED4 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved4`]
module"]
# [doc (alias = "RESERVED4")]
pub type Reserved4 = crate :: Reg < reserved4 :: Reserved4Spec > ; # [doc = "Reserved"]
pub mod reserved4 { # [doc = "Register `RESERVED4` reader"]
pub type R = crate :: R < Reserved4Spec > ; # [doc = "Register `RESERVED4` writer"]
pub type W = crate :: W < Reserved4Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved4Spec ; impl crate :: RegisterSpec for Reserved4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved4::R`](R) reader structure"]
impl crate :: Readable for Reserved4Spec { } # [doc = "`write(|w| ..)` method takes [`reserved4::W`](W) writer structure"]
impl crate :: Writable for Reserved4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED4 to value 0"]
impl crate :: Resettable for Reserved4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED5 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved5`]
module"]
# [doc (alias = "RESERVED5")]
pub type Reserved5 = crate :: Reg < reserved5 :: Reserved5Spec > ; # [doc = "Reserved"]
pub mod reserved5 { # [doc = "Register `RESERVED5` reader"]
pub type R = crate :: R < Reserved5Spec > ; # [doc = "Register `RESERVED5` writer"]
pub type W = crate :: W < Reserved5Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved5Spec ; impl crate :: RegisterSpec for Reserved5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved5::R`](R) reader structure"]
impl crate :: Readable for Reserved5Spec { } # [doc = "`write(|w| ..)` method takes [`reserved5::W`](W) writer structure"]
impl crate :: Writable for Reserved5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED5 to value 0"]
impl crate :: Resettable for Reserved5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED6 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved6`]
module"]
# [doc (alias = "RESERVED6")]
pub type Reserved6 = crate :: Reg < reserved6 :: Reserved6Spec > ; # [doc = "Reserved"]
pub mod reserved6 { # [doc = "Register `RESERVED6` reader"]
pub type R = crate :: R < Reserved6Spec > ; # [doc = "Register `RESERVED6` writer"]
pub type W = crate :: W < Reserved6Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved6Spec ; impl crate :: RegisterSpec for Reserved6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved6::R`](R) reader structure"]
impl crate :: Readable for Reserved6Spec { } # [doc = "`write(|w| ..)` method takes [`reserved6::W`](W) writer structure"]
impl crate :: Writable for Reserved6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED6 to value 0"]
impl crate :: Resettable for Reserved6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED7 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved7`]
module"]
# [doc (alias = "RESERVED7")]
pub type Reserved7 = crate :: Reg < reserved7 :: Reserved7Spec > ; # [doc = "Reserved"]
pub mod reserved7 { # [doc = "Register `RESERVED7` reader"]
pub type R = crate :: R < Reserved7Spec > ; # [doc = "Register `RESERVED7` writer"]
pub type W = crate :: W < Reserved7Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved7Spec ; impl crate :: RegisterSpec for Reserved7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved7::R`](R) reader structure"]
impl crate :: Readable for Reserved7Spec { } # [doc = "`write(|w| ..)` method takes [`reserved7::W`](W) writer structure"]
impl crate :: Writable for Reserved7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED7 to value 0"]
impl crate :: Resettable for Reserved7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED8 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved8`]
module"]
# [doc (alias = "RESERVED8")]
pub type Reserved8 = crate :: Reg < reserved8 :: Reserved8Spec > ; # [doc = "Reserved"]
pub mod reserved8 { # [doc = "Register `RESERVED8` reader"]
pub type R = crate :: R < Reserved8Spec > ; # [doc = "Register `RESERVED8` writer"]
pub type W = crate :: W < Reserved8Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved8Spec ; impl crate :: RegisterSpec for Reserved8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved8::R`](R) reader structure"]
impl crate :: Readable for Reserved8Spec { } # [doc = "`write(|w| ..)` method takes [`reserved8::W`](W) writer structure"]
impl crate :: Writable for Reserved8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED8 to value 0"]
impl crate :: Resettable for Reserved8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED9 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved9`]
module"]
# [doc (alias = "RESERVED9")]
pub type Reserved9 = crate :: Reg < reserved9 :: Reserved9Spec > ; # [doc = "Reserved"]
pub mod reserved9 { # [doc = "Register `RESERVED9` reader"]
pub type R = crate :: R < Reserved9Spec > ; # [doc = "Register `RESERVED9` writer"]
pub type W = crate :: W < Reserved9Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved9Spec ; impl crate :: RegisterSpec for Reserved9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved9::R`](R) reader structure"]
impl crate :: Readable for Reserved9Spec { } # [doc = "`write(|w| ..)` method takes [`reserved9::W`](W) writer structure"]
impl crate :: Writable for Reserved9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED9 to value 0"]
impl crate :: Resettable for Reserved9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO9 (rw) register accessor: SCI Pin I/O Control Register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio9`]
module"]
# [doc (alias = "SCIPIO9")]
pub type Scipio9 = crate :: Reg < scipio9 :: Scipio9Spec > ; # [doc = "SCI Pin I/O Control Register 9"]
pub mod scipio9 { # [doc = "Register `SCIPIO9` reader"]
pub type R = crate :: R < Scipio9Spec > ; # [doc = "Register `SCIPIO9` writer"]
pub type W = crate :: W < Scipio9Spec > ; # [doc = "Field `CLK_SL` reader - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
pub type ClkSlR = crate :: BitReader ; # [doc = "Field `CLK_SL` writer - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
pub type ClkSlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_SL` reader - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
pub type RxSlR = crate :: BitReader ; # [doc = "Field `RX_SL` writer - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
pub type RxSlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_SL` reader - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
pub type TxSlR = crate :: BitReader ; # [doc = "Field `TX_SL` writer - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
pub type TxSlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
# [inline (always)]
pub fn clk_sl (& self) -> ClkSlR { ClkSlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
# [inline (always)]
pub fn rx_sl (& self) -> RxSlR { RxSlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
# [inline (always)]
pub fn tx_sl (& self) -> TxSlR { TxSlR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
# [inline (always)]
# [must_use]
pub fn clk_sl (& mut self) -> ClkSlW < Scipio9Spec > { ClkSlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
# [inline (always)]
# [must_use]
pub fn rx_sl (& mut self) -> RxSlW < Scipio9Spec > { RxSlW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
# [inline (always)]
# [must_use]
pub fn tx_sl (& mut self) -> TxSlW < Scipio9Spec > { TxSlW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio9Spec ; impl crate :: RegisterSpec for Scipio9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio9::R`](R) reader structure"]
impl crate :: Readable for Scipio9Spec { } # [doc = "`write(|w| ..)` method takes [`scipio9::W`](W) writer structure"]
impl crate :: Writable for Scipio9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO9 to value 0"]
impl crate :: Resettable for Scipio9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIIODCTRL (rw) register accessor: SCI IO DFT Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sciiodctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciiodctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciiodctrl`]
module"]
# [doc (alias = "SCIIODCTRL")]
pub type Sciiodctrl = crate :: Reg < sciiodctrl :: SciiodctrlSpec > ; # [doc = "SCI IO DFT Control"]
pub mod sciiodctrl { # [doc = "Register `SCIIODCTRL` reader"]
pub type R = crate :: R < SciiodctrlSpec > ; # [doc = "Register `SCIIODCTRL` writer"]
pub type W = crate :: W < SciiodctrlSpec > ; # [doc = "Field `RXP_ENA` reader - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
pub type RxpEnaR = crate :: BitReader ; # [doc = "Field `RXP_ENA` writer - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
pub type RxpEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LBP_ENA` reader - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
pub type LbpEnaR = crate :: BitReader ; # [doc = "Field `LBP_ENA` writer - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
pub type LbpEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `IODFTENA` reader - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type IodftenaR = crate :: FieldReader ; # [doc = "Field `IODFTENA` writer - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type IodftenaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED2` reader - 15:12\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:12\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TX_SHIFT` reader - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type TxShiftR = crate :: FieldReader ; # [doc = "Field `TX_SHIFT` writer - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type TxShiftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PIN_SAMPLE_MASK` reader - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
pub type PinSampleMaskR = crate :: FieldReader ; # [doc = "Field `PIN_SAMPLE_MASK` writer - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
pub type PinSampleMaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RESERVED3` reader - 23:21\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:21\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BRKDT_ENA` reader - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
pub type BrkdtEnaR = crate :: BitReader ; # [doc = "Field `BRKDT_ENA` writer - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
pub type BrkdtEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEN` reader - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
pub type PenR = crate :: BitReader ; # [doc = "Field `PEN` writer - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
pub type PenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FEN` reader - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
pub type FenR = crate :: BitReader ; # [doc = "Field `FEN` writer - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
pub type FenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:27\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:27\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
# [inline (always)]
pub fn rxp_ena (& self) -> RxpEnaR { RxpEnaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
# [inline (always)]
pub fn lbp_ena (& self) -> LbpEnaR { LbpEnaR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
pub fn iodftena (& self) -> IodftenaR { IodftenaR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:18 - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
pub fn tx_shift (& self) -> TxShiftR { TxShiftR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bits 19:20 - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
# [inline (always)]
pub fn pin_sample_mask (& self) -> PinSampleMaskR { PinSampleMaskR :: new (((self . bits >> 19) & 3) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
# [inline (always)]
pub fn brkdt_ena (& self) -> BrkdtEnaR { BrkdtEnaR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
# [inline (always)]
pub fn pen (& self) -> PenR { PenR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
# [inline (always)]
pub fn fen (& self) -> FenR { FenR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
# [inline (always)]
# [must_use]
pub fn rxp_ena (& mut self) -> RxpEnaW < SciiodctrlSpec > { RxpEnaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
# [inline (always)]
# [must_use]
pub fn lbp_ena (& mut self) -> LbpEnaW < SciiodctrlSpec > { LbpEnaW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciiodctrlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bits 8:11 - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
# [must_use]
pub fn iodftena (& mut self) -> IodftenaW < SciiodctrlSpec > { IodftenaW :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciiodctrlSpec > { Reserved2W :: new (self , 12) } # [doc = "Bits 16:18 - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
# [must_use]
pub fn tx_shift (& mut self) -> TxShiftW < SciiodctrlSpec > { TxShiftW :: new (self , 16) } # [doc = "Bits 19:20 - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
# [inline (always)]
# [must_use]
pub fn pin_sample_mask (& mut self) -> PinSampleMaskW < SciiodctrlSpec > { PinSampleMaskW :: new (self , 19) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciiodctrlSpec > { Reserved3W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
# [inline (always)]
# [must_use]
pub fn brkdt_ena (& mut self) -> BrkdtEnaW < SciiodctrlSpec > { BrkdtEnaW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
# [inline (always)]
# [must_use]
pub fn pen (& mut self) -> PenW < SciiodctrlSpec > { PenW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
# [inline (always)]
# [must_use]
pub fn fen (& mut self) -> FenW < SciiodctrlSpec > { FenW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciiodctrlSpec > { Reserved4W :: new (self , 27) } } # [doc = "SCI IO DFT Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sciiodctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciiodctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciiodctrlSpec ; impl crate :: RegisterSpec for SciiodctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciiodctrl::R`](R) reader structure"]
impl crate :: Readable for SciiodctrlSpec { } # [doc = "`write(|w| ..)` method takes [`sciiodctrl::W`](W) writer structure"]
impl crate :: Writable for SciiodctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIIODCTRL to value 0"]
impl crate :: Resettable for SciiodctrlSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_SPI"]
pub struct AppSpi0 { _marker : PhantomData < * const () > } unsafe impl Send for AppSpi0 { } impl AppSpi0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_spi_0 :: RegisterBlock = 0x53f7_f400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_spi_0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppSpi0 { type Target = app_spi_0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppSpi0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppSpi0") . finish () } } # [doc = "APP_SPI"]
pub mod app_spi_0 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { hl_rev : HlRev , hl_hwinfo : HlHwinfo , _reserved2 : [u8 ; 0x08]
, hl_sysconfig : HlSysconfig , _reserved3 : [u8 ; 0xec]
, revision : Revision , _reserved4 : [u8 ; 0x0c]
, sysconfig : Sysconfig , sysstatus : Sysstatus , irqstatus : Irqstatus , irqenable : Irqenable , wakeupenable : Wakeupenable , syst : Syst , modulctrl : Modulctrl , ch0conf : Ch0conf , ch0stat : Ch0stat , ch0ctrl : Ch0ctrl , tx0 : Tx0 , rx0 : Rx0 , ch1conf : Ch1conf , ch1stat : Ch1stat , ch1ctrl : Ch1ctrl , tx1 : Tx1 , rx1 : Rx1 , ch2conf : Ch2conf , ch2stat : Ch2stat , ch2ctrl : Ch2ctrl , tx2 : Tx2 , rx2 : Rx2 , ch3conf : Ch3conf , ch3stat : Ch3stat , ch3ctrl : Ch3ctrl , tx3 : Tx3 , rx3 : Rx3 , xferlevel : Xferlevel , daftx : Daftx , _reserved33 : [u8 ; 0x1c]
, dafrx : Dafrx , } impl RegisterBlock { # [doc = "0x00 - IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility"]
# [inline (always)]
pub const fn hl_rev (& self) -> & HlRev { & self . hl_rev } # [doc = "0x04 - Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide."]
# [inline (always)]
pub const fn hl_hwinfo (& self) -> & HlHwinfo { & self . hl_hwinfo } # [doc = "0x10 - Clock management configuration"]
# [inline (always)]
pub const fn hl_sysconfig (& self) -> & HlSysconfig { & self . hl_sysconfig } # [doc = "0x100 - This register contains the hard coded RTL revision number."]
# [inline (always)]
pub const fn revision (& self) -> & Revision { & self . revision } # [doc = "0x110 - This register allows controlling various parameters of the OCP interface."]
# [inline (always)]
pub const fn sysconfig (& self) -> & Sysconfig { & self . sysconfig } # [doc = "0x114 - This register provides status information about the module excluding the interrupt status information"]
# [inline (always)]
pub const fn sysstatus (& self) -> & Sysstatus { & self . sysstatus } # [doc = "0x118 - The interrupt status regroups all the status of the module internal events that can generate an interrupt"]
# [inline (always)]
pub const fn irqstatus (& self) -> & Irqstatus { & self . irqstatus } # [doc = "0x11c - This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis."]
# [inline (always)]
pub const fn irqenable (& self) -> & Irqenable { & self . irqenable } # [doc = "0x120 - The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."]
# [inline (always)]
pub const fn wakeupenable (& self) -> & Wakeupenable { & self . wakeupenable } # [doc = "0x124 - This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode."]
# [inline (always)]
pub const fn syst (& self) -> & Syst { & self . syst } # [doc = "0x128 - This register is dedicated to the configuration of the serial port interface."]
# [inline (always)]
pub const fn modulctrl (& self) -> & Modulctrl { & self . modulctrl } # [doc = "0x12c - This register is dedicated to the configuration of the channel 0"]
# [inline (always)]
pub const fn ch0conf (& self) -> & Ch0conf { & self . ch0conf } # [doc = "0x130 - This register provides status information about transmitter and receiver registers of channel 0"]
# [inline (always)]
pub const fn ch0stat (& self) -> & Ch0stat { & self . ch0stat } # [doc = "0x134 - This register is dedicated to enable the channel 0"]
# [inline (always)]
pub const fn ch0ctrl (& self) -> & Ch0ctrl { & self . ch0ctrl } # [doc = "0x138 - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx0 (& self) -> & Tx0 { & self . tx0 } # [doc = "0x13c - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx0 (& self) -> & Rx0 { & self . rx0 } # [doc = "0x140 - This register is dedicated to the configuration of the channel."]
# [inline (always)]
pub const fn ch1conf (& self) -> & Ch1conf { & self . ch1conf } # [doc = "0x144 - This register provides status information about transmitter and receiver registers of channel 1"]
# [inline (always)]
pub const fn ch1stat (& self) -> & Ch1stat { & self . ch1stat } # [doc = "0x148 - This register is dedicated to enable the channel 1"]
# [inline (always)]
pub const fn ch1ctrl (& self) -> & Ch1ctrl { & self . ch1ctrl } # [doc = "0x14c - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx1 (& self) -> & Tx1 { & self . tx1 } # [doc = "0x150 - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx1 (& self) -> & Rx1 { & self . rx1 } # [doc = "0x154 - This register is dedicated to the configuration of the channel 2"]
# [inline (always)]
pub const fn ch2conf (& self) -> & Ch2conf { & self . ch2conf } # [doc = "0x158 - This register provides status information about transmitter and receiver registers of channel 2"]
# [inline (always)]
pub const fn ch2stat (& self) -> & Ch2stat { & self . ch2stat } # [doc = "0x15c - This register is dedicated to enable the channel 2"]
# [inline (always)]
pub const fn ch2ctrl (& self) -> & Ch2ctrl { & self . ch2ctrl } # [doc = "0x160 - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx2 (& self) -> & Tx2 { & self . tx2 } # [doc = "0x164 - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx2 (& self) -> & Rx2 { & self . rx2 } # [doc = "0x168 - This register is dedicated to the configuration of the channel 3"]
# [inline (always)]
pub const fn ch3conf (& self) -> & Ch3conf { & self . ch3conf } # [doc = "0x16c - This register provides status information about transmitter and receiver registers of channel 3"]
# [inline (always)]
pub const fn ch3stat (& self) -> & Ch3stat { & self . ch3stat } # [doc = "0x170 - This register is dedicated to enable the channel 3"]
# [inline (always)]
pub const fn ch3ctrl (& self) -> & Ch3ctrl { & self . ch3ctrl } # [doc = "0x174 - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx3 (& self) -> & Tx3 { & self . tx3 } # [doc = "0x178 - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx3 (& self) -> & Rx3 { & self . rx3 } # [doc = "0x17c - This register provides transfer levels needed while using FIFO buffer during transfer."]
# [inline (always)]
pub const fn xferlevel (& self) -> & Xferlevel { & self . xferlevel } # [doc = "0x180 - This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."]
# [inline (always)]
pub const fn daftx (& self) -> & Daftx { & self . daftx } # [doc = "0x1a0 - This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."]
# [inline (always)]
pub const fn dafrx (& self) -> & Dafrx { & self . dafrx } } # [doc = "HL_REV (rw) register accessor: IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_rev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_rev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hl_rev`]
module"]
# [doc (alias = "HL_REV")]
pub type HlRev = crate :: Reg < hl_rev :: HlRevSpec > ; # [doc = "IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility"]
pub mod hl_rev { # [doc = "Register `HL_REV` reader"]
pub type R = crate :: R < HlRevSpec > ; # [doc = "Register `HL_REV` writer"]
pub type W = crate :: W < HlRevSpec > ; # [doc = "Field `Y_MINOR` reader - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
pub type YMinorR = crate :: FieldReader ; # [doc = "Field `Y_MINOR` writer - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
pub type YMinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `X_MAJOR` reader - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
pub type XMajorR = crate :: FieldReader ; # [doc = "Field `X_MAJOR` writer - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
pub type XMajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `R_RTL` reader - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
pub type RRtlR = crate :: FieldReader ; # [doc = "Field `R_RTL` writer - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
pub type RRtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNC` reader - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
pub type FuncR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNC` writer - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
pub type FuncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `RSVD` reader - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdR = crate :: FieldReader ; # [doc = "Field `RSVD` writer - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
# [inline (always)]
pub fn y_minor (& self) -> YMinorR { YMinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
# [inline (always)]
pub fn x_major (& self) -> XMajorR { XMajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
# [inline (always)]
pub fn r_rtl (& self) -> RRtlR { RRtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
# [inline (always)]
pub fn func (& self) -> FuncR { FuncR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
pub fn rsvd (& self) -> RsvdR { RsvdR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
# [inline (always)]
# [must_use]
pub fn y_minor (& mut self) -> YMinorW < HlRevSpec > { YMinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < HlRevSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
# [inline (always)]
# [must_use]
pub fn x_major (& mut self) -> XMajorW < HlRevSpec > { XMajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
# [inline (always)]
# [must_use]
pub fn r_rtl (& mut self) -> RRtlW < HlRevSpec > { RRtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
# [inline (always)]
# [must_use]
pub fn func (& mut self) -> FuncW < HlRevSpec > { FuncW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
# [must_use]
pub fn rsvd (& mut self) -> RsvdW < HlRevSpec > { RsvdW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < HlRevSpec > { SchemeW :: new (self , 30) } } # [doc = "IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_rev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_rev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HlRevSpec ; impl crate :: RegisterSpec for HlRevSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hl_rev::R`](R) reader structure"]
impl crate :: Readable for HlRevSpec { } # [doc = "`write(|w| ..)` method takes [`hl_rev::W`](W) writer structure"]
impl crate :: Writable for HlRevSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HL_REV to value 0"]
impl crate :: Resettable for HlRevSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HL_HWINFO (rw) register accessor: Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide.\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_hwinfo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_hwinfo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hl_hwinfo`]
module"]
# [doc (alias = "HL_HWINFO")]
pub type HlHwinfo = crate :: Reg < hl_hwinfo :: HlHwinfoSpec > ; # [doc = "Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide."]
pub mod hl_hwinfo { # [doc = "Register `HL_HWINFO` reader"]
pub type R = crate :: R < HlHwinfoSpec > ; # [doc = "Register `HL_HWINFO` writer"]
pub type W = crate :: W < HlHwinfoSpec > ; # [doc = "Field `USEFIFO` reader - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
pub type UsefifoR = crate :: BitReader ; # [doc = "Field `USEFIFO` writer - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
pub type UsefifoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFNBYTE` reader - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
pub type FfnbyteR = crate :: FieldReader ; # [doc = "Field `FFNBYTE` writer - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
pub type FfnbyteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RETMODE` reader - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
pub type RetmodeR = crate :: BitReader ; # [doc = "Field `RETMODE` writer - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
pub type RetmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RSVD` reader - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdR = crate :: FieldReader < u32 > ; # [doc = "Field `RSVD` writer - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
# [inline (always)]
pub fn usefifo (& self) -> UsefifoR { UsefifoR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:5 - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
# [inline (always)]
pub fn ffnbyte (& self) -> FfnbyteR { FfnbyteR :: new (((self . bits >> 1) & 0x1f) as u8) } # [doc = "Bit 6 - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
# [inline (always)]
pub fn retmode (& self) -> RetmodeR { RetmodeR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
pub fn rsvd (& self) -> RsvdR { RsvdR :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
# [inline (always)]
# [must_use]
pub fn usefifo (& mut self) -> UsefifoW < HlHwinfoSpec > { UsefifoW :: new (self , 0) } # [doc = "Bits 1:5 - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
# [inline (always)]
# [must_use]
pub fn ffnbyte (& mut self) -> FfnbyteW < HlHwinfoSpec > { FfnbyteW :: new (self , 1) } # [doc = "Bit 6 - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
# [inline (always)]
# [must_use]
pub fn retmode (& mut self) -> RetmodeW < HlHwinfoSpec > { RetmodeW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
# [must_use]
pub fn rsvd (& mut self) -> RsvdW < HlHwinfoSpec > { RsvdW :: new (self , 7) } } # [doc = "Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide.\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_hwinfo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_hwinfo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HlHwinfoSpec ; impl crate :: RegisterSpec for HlHwinfoSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hl_hwinfo::R`](R) reader structure"]
impl crate :: Readable for HlHwinfoSpec { } # [doc = "`write(|w| ..)` method takes [`hl_hwinfo::W`](W) writer structure"]
impl crate :: Writable for HlHwinfoSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HL_HWINFO to value 0"]
impl crate :: Resettable for HlHwinfoSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HL_SYSCONFIG (rw) register accessor: Clock management configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_sysconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_sysconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hl_sysconfig`]
module"]
# [doc (alias = "HL_SYSCONFIG")]
pub type HlSysconfig = crate :: Reg < hl_sysconfig :: HlSysconfigSpec > ; # [doc = "Clock management configuration"]
pub mod hl_sysconfig { # [doc = "Register `HL_SYSCONFIG` reader"]
pub type R = crate :: R < HlSysconfigSpec > ; # [doc = "Register `HL_SYSCONFIG` writer"]
pub type W = crate :: W < HlSysconfigSpec > ; # [doc = "Field `SOFTRESET` reader - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
pub type SoftresetR = crate :: BitReader ; # [doc = "Field `SOFTRESET` writer - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
pub type SoftresetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FREEEMU` reader - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
pub type FreeemuR = crate :: BitReader ; # [doc = "Field `FREEEMU` writer - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
pub type FreeemuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDLEMODE` reader - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
pub type IdlemodeR = crate :: FieldReader ; # [doc = "Field `IDLEMODE` writer - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
pub type IdlemodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RSVD` reader - 31:4\\]
Reserved - (RO )"]
pub type RsvdR = crate :: FieldReader < u32 > ; # [doc = "Field `RSVD` writer - 31:4\\]
Reserved - (RO )"]
pub type RsvdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
# [inline (always)]
pub fn softreset (& self) -> SoftresetR { SoftresetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
# [inline (always)]
pub fn freeemu (& self) -> FreeemuR { FreeemuR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
# [inline (always)]
pub fn idlemode (& self) -> IdlemodeR { IdlemodeR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Reserved - (RO )"]
# [inline (always)]
pub fn rsvd (& self) -> RsvdR { RsvdR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn softreset (& mut self) -> SoftresetW < HlSysconfigSpec > { SoftresetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
# [inline (always)]
# [must_use]
pub fn freeemu (& mut self) -> FreeemuW < HlSysconfigSpec > { FreeemuW :: new (self , 1) } # [doc = "Bits 2:3 - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
# [inline (always)]
# [must_use]
pub fn idlemode (& mut self) -> IdlemodeW < HlSysconfigSpec > { IdlemodeW :: new (self , 2) } # [doc = "Bits 4:31 - 31:4\\]
Reserved - (RO )"]
# [inline (always)]
# [must_use]
pub fn rsvd (& mut self) -> RsvdW < HlSysconfigSpec > { RsvdW :: new (self , 4) } } # [doc = "Clock management configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_sysconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_sysconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HlSysconfigSpec ; impl crate :: RegisterSpec for HlSysconfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hl_sysconfig::R`](R) reader structure"]
impl crate :: Readable for HlSysconfigSpec { } # [doc = "`write(|w| ..)` method takes [`hl_sysconfig::W`](W) writer structure"]
impl crate :: Writable for HlSysconfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HL_SYSCONFIG to value 0"]
impl crate :: Resettable for HlSysconfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REVISION (rw) register accessor: This register contains the hard coded RTL revision number.\n\nYou can [`read`](crate::Reg::read) this register and get [`revision::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`revision::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@revision`]
module"]
# [doc (alias = "REVISION")]
pub type Revision = crate :: Reg < revision :: RevisionSpec > ; # [doc = "This register contains the hard coded RTL revision number."]
pub mod revision { # [doc = "Register `REVISION` reader"]
pub type R = crate :: R < RevisionSpec > ; # [doc = "Register `REVISION` writer"]
pub type W = crate :: W < RevisionSpec > ; # [doc = "Field `REV` reader - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
pub type RevR = crate :: FieldReader ; # [doc = "Field `REV` writer - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
pub type RevW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_13` reader - 31:8\\]
Reads returns 0 - (RO )"]
pub type Reserved13R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_13` writer - 31:8\\]
Reads returns 0 - (RO )"]
pub type Reserved13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
# [inline (always)]
pub fn rev (& self) -> RevR { RevR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_13 (& self) -> Reserved13R { Reserved13R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
# [inline (always)]
# [must_use]
pub fn rev (& mut self) -> RevW < RevisionSpec > { RevW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_13 (& mut self) -> Reserved13W < RevisionSpec > { Reserved13W :: new (self , 8) } } # [doc = "This register contains the hard coded RTL revision number.\n\nYou can [`read`](crate::Reg::read) this register and get [`revision::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`revision::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RevisionSpec ; impl crate :: RegisterSpec for RevisionSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`revision::R`](R) reader structure"]
impl crate :: Readable for RevisionSpec { } # [doc = "`write(|w| ..)` method takes [`revision::W`](W) writer structure"]
impl crate :: Writable for RevisionSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REVISION to value 0"]
impl crate :: Resettable for RevisionSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYSCONFIG (rw) register accessor: This register allows controlling various parameters of the OCP interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysconfig`]
module"]
# [doc (alias = "SYSCONFIG")]
pub type Sysconfig = crate :: Reg < sysconfig :: SysconfigSpec > ; # [doc = "This register allows controlling various parameters of the OCP interface."]
pub mod sysconfig { # [doc = "Register `SYSCONFIG` reader"]
pub type R = crate :: R < SysconfigSpec > ; # [doc = "Register `SYSCONFIG` writer"]
pub type W = crate :: W < SysconfigSpec > ; # [doc = "Field `AUTOIDLE` reader - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
pub type AutoidleR = crate :: BitReader ; # [doc = "Field `AUTOIDLE` writer - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
pub type AutoidleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOFTRESET` reader - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
pub type SoftresetR = crate :: BitReader ; # [doc = "Field `SOFTRESET` writer - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
pub type SoftresetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENAWAKEUP` reader - 2:2\\]
WakeUp feature control - (RW )"]
pub type EnawakeupR = crate :: BitReader ; # [doc = "Field `ENAWAKEUP` writer - 2:2\\]
WakeUp feature control - (RW )"]
pub type EnawakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SIDLEMODE` reader - 4:3\\]
Power management - (RW )"]
pub type SidlemodeR = crate :: FieldReader ; # [doc = "Field `SIDLEMODE` writer - 4:3\\]
Power management - (RW )"]
pub type SidlemodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RESERVED_15` reader - 7:5\\]
Reads returns 0 - (RO )"]
pub type Reserved15R = crate :: FieldReader ; # [doc = "Field `RESERVED_15` writer - 7:5\\]
Reads returns 0 - (RO )"]
pub type Reserved15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CLOCKACTIVITY` reader - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
pub type ClockactivityR = crate :: FieldReader ; # [doc = "Field `CLOCKACTIVITY` writer - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
pub type ClockactivityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RESERVED_14` reader - 31:10\\]
Reads returns 0 - (RO )"]
pub type Reserved14R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_14` writer - 31:10\\]
Reads returns 0 - (RO )"]
pub type Reserved14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
# [inline (always)]
pub fn autoidle (& self) -> AutoidleR { AutoidleR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
# [inline (always)]
pub fn softreset (& self) -> SoftresetR { SoftresetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
WakeUp feature control - (RW )"]
# [inline (always)]
pub fn enawakeup (& self) -> EnawakeupR { EnawakeupR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:4 - 4:3\\]
Power management - (RW )"]
# [inline (always)]
pub fn sidlemode (& self) -> SidlemodeR { SidlemodeR :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 5:7 - 7:5\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_15 (& self) -> Reserved15R { Reserved15R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
# [inline (always)]
pub fn clockactivity (& self) -> ClockactivityR { ClockactivityR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:31 - 31:10\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_14 (& self) -> Reserved14R { Reserved14R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
# [inline (always)]
# [must_use]
pub fn autoidle (& mut self) -> AutoidleW < SysconfigSpec > { AutoidleW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn softreset (& mut self) -> SoftresetW < SysconfigSpec > { SoftresetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
WakeUp feature control - (RW )"]
# [inline (always)]
# [must_use]
pub fn enawakeup (& mut self) -> EnawakeupW < SysconfigSpec > { EnawakeupW :: new (self , 2) } # [doc = "Bits 3:4 - 4:3\\]
Power management - (RW )"]
# [inline (always)]
# [must_use]
pub fn sidlemode (& mut self) -> SidlemodeW < SysconfigSpec > { SidlemodeW :: new (self , 3) } # [doc = "Bits 5:7 - 7:5\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_15 (& mut self) -> Reserved15W < SysconfigSpec > { Reserved15W :: new (self , 5) } # [doc = "Bits 8:9 - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
# [inline (always)]
# [must_use]
pub fn clockactivity (& mut self) -> ClockactivityW < SysconfigSpec > { ClockactivityW :: new (self , 8) } # [doc = "Bits 10:31 - 31:10\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_14 (& mut self) -> Reserved14W < SysconfigSpec > { Reserved14W :: new (self , 10) } } # [doc = "This register allows controlling various parameters of the OCP interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysconfigSpec ; impl crate :: RegisterSpec for SysconfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sysconfig::R`](R) reader structure"]
impl crate :: Readable for SysconfigSpec { } # [doc = "`write(|w| ..)` method takes [`sysconfig::W`](W) writer structure"]
impl crate :: Writable for SysconfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYSCONFIG to value 0"]
impl crate :: Resettable for SysconfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYSSTATUS (rw) register accessor: This register provides status information about the module excluding the interrupt status information\n\nYou can [`read`](crate::Reg::read) this register and get [`sysstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysstatus`]
module"]
# [doc (alias = "SYSSTATUS")]
pub type Sysstatus = crate :: Reg < sysstatus :: SysstatusSpec > ; # [doc = "This register provides status information about the module excluding the interrupt status information"]
pub mod sysstatus { # [doc = "Register `SYSSTATUS` reader"]
pub type R = crate :: R < SysstatusSpec > ; # [doc = "Register `SYSSTATUS` writer"]
pub type W = crate :: W < SysstatusSpec > ; # [doc = "Field `RESETDONE` reader - 0:0\\]
Internal Reset Monitoring - (RO )"]
pub type ResetdoneR = crate :: BitReader ; # [doc = "Field `RESETDONE` writer - 0:0\\]
Internal Reset Monitoring - (RO )"]
pub type ResetdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_16` reader - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
pub type Reserved16R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_16` writer - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
pub type Reserved16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Internal Reset Monitoring - (RO )"]
# [inline (always)]
pub fn resetdone (& self) -> ResetdoneR { ResetdoneR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_16 (& self) -> Reserved16R { Reserved16R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Internal Reset Monitoring - (RO )"]
# [inline (always)]
# [must_use]
pub fn resetdone (& mut self) -> ResetdoneW < SysstatusSpec > { ResetdoneW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_16 (& mut self) -> Reserved16W < SysstatusSpec > { Reserved16W :: new (self , 1) } } # [doc = "This register provides status information about the module excluding the interrupt status information\n\nYou can [`read`](crate::Reg::read) this register and get [`sysstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysstatusSpec ; impl crate :: RegisterSpec for SysstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sysstatus::R`](R) reader structure"]
impl crate :: Readable for SysstatusSpec { } # [doc = "`write(|w| ..)` method takes [`sysstatus::W`](W) writer structure"]
impl crate :: Writable for SysstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYSSTATUS to value 0"]
impl crate :: Resettable for SysstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IRQSTATUS (rw) register accessor: The interrupt status regroups all the status of the module internal events that can generate an interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`irqstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqstatus`]
module"]
# [doc (alias = "IRQSTATUS")]
pub type Irqstatus = crate :: Reg < irqstatus :: IrqstatusSpec > ; # [doc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt"]
pub mod irqstatus { # [doc = "Register `IRQSTATUS` reader"]
pub type R = crate :: R < IrqstatusSpec > ; # [doc = "Register `IRQSTATUS` writer"]
pub type W = crate :: W < IrqstatusSpec > ; # [doc = "Field `TX0_EMPTY` reader - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
pub type Tx0EmptyR = crate :: BitReader ; # [doc = "Field `TX0_EMPTY` writer - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
pub type Tx0EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX0_UNDERFLOW` reader - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
pub type Tx0UnderflowR = crate :: BitReader ; # [doc = "Field `TX0_UNDERFLOW` writer - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
pub type Tx0UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_FULL` reader - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
pub type Rx0FullR = crate :: BitReader ; # [doc = "Field `RX0_FULL` writer - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
pub type Rx0FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_OVERFLOW` reader - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
pub type Rx0OverflowR = crate :: BitReader ; # [doc = "Field `RX0_OVERFLOW` writer - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
pub type Rx0OverflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_EMPTY` reader - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
pub type Tx1EmptyR = crate :: BitReader ; # [doc = "Field `TX1_EMPTY` writer - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
pub type Tx1EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_UNDERFLOW` reader - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
pub type Tx1UnderflowR = crate :: BitReader ; # [doc = "Field `TX1_UNDERFLOW` writer - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
pub type Tx1UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX1_FULL` reader - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
pub type Rx1FullR = crate :: BitReader ; # [doc = "Field `RX1_FULL` writer - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
pub type Rx1FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_10` reader - 7:7\\]
Reads returns 0 - (RO )"]
pub type Reserved10R = crate :: BitReader ; # [doc = "Field `RESERVED_10` writer - 7:7\\]
Reads returns 0 - (RO )"]
pub type Reserved10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_EMPTY` reader - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
pub type Tx2EmptyR = crate :: BitReader ; # [doc = "Field `TX2_EMPTY` writer - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
pub type Tx2EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_UNDERFLOW` reader - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
pub type Tx2UnderflowR = crate :: BitReader ; # [doc = "Field `TX2_UNDERFLOW` writer - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
pub type Tx2UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX2_FULL` reader - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
pub type Rx2FullR = crate :: BitReader ; # [doc = "Field `RX2_FULL` writer - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
pub type Rx2FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_9` reader - 11:11\\]
Reads returns 0 - (RO )"]
pub type Reserved9R = crate :: BitReader ; # [doc = "Field `RESERVED_9` writer - 11:11\\]
Reads returns 0 - (RO )"]
pub type Reserved9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_EMPTY` reader - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
pub type Tx3EmptyR = crate :: BitReader ; # [doc = "Field `TX3_EMPTY` writer - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
pub type Tx3EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_UNDERFLOW` reader - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
pub type Tx3UnderflowR = crate :: BitReader ; # [doc = "Field `TX3_UNDERFLOW` writer - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
pub type Tx3UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX3_FULL` reader - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
pub type Rx3FullR = crate :: BitReader ; # [doc = "Field `RX3_FULL` writer - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
pub type Rx3FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_7` reader - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved7R = crate :: BitReader ; # [doc = "Field `RESERVED_7` writer - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WKS` reader - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WksR = crate :: BitReader ; # [doc = "Field `WKS` writer - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WksW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOW` reader - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
pub type EowR = crate :: BitReader ; # [doc = "Field `EOW` writer - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
pub type EowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_8` reader - 31:18\\]
Reads returns 0 - (RO )"]
pub type Reserved8R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_8` writer - 31:18\\]
Reads returns 0 - (RO )"]
pub type Reserved8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
# [inline (always)]
pub fn tx0_empty (& self) -> Tx0EmptyR { Tx0EmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
# [inline (always)]
pub fn tx0_underflow (& self) -> Tx0UnderflowR { Tx0UnderflowR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
# [inline (always)]
pub fn rx0_full (& self) -> Rx0FullR { Rx0FullR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
# [inline (always)]
pub fn rx0_overflow (& self) -> Rx0OverflowR { Rx0OverflowR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
# [inline (always)]
pub fn tx1_empty (& self) -> Tx1EmptyR { Tx1EmptyR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
# [inline (always)]
pub fn tx1_underflow (& self) -> Tx1UnderflowR { Tx1UnderflowR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
# [inline (always)]
pub fn rx1_full (& self) -> Rx1FullR { Rx1FullR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_10 (& self) -> Reserved10R { Reserved10R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
# [inline (always)]
pub fn tx2_empty (& self) -> Tx2EmptyR { Tx2EmptyR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
# [inline (always)]
pub fn tx2_underflow (& self) -> Tx2UnderflowR { Tx2UnderflowR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
# [inline (always)]
pub fn rx2_full (& self) -> Rx2FullR { Rx2FullR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_9 (& self) -> Reserved9R { Reserved9R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
# [inline (always)]
pub fn tx3_empty (& self) -> Tx3EmptyR { Tx3EmptyR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
# [inline (always)]
pub fn tx3_underflow (& self) -> Tx3UnderflowR { Tx3UnderflowR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
# [inline (always)]
pub fn rx3_full (& self) -> Rx3FullR { Rx3FullR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_7 (& self) -> Reserved7R { Reserved7R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
pub fn wks (& self) -> WksR { WksR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
# [inline (always)]
pub fn eow (& self) -> EowR { EowR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:31 - 31:18\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_8 (& self) -> Reserved8R { Reserved8R :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_empty (& mut self) -> Tx0EmptyW < IrqstatusSpec > { Tx0EmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_underflow (& mut self) -> Tx0UnderflowW < IrqstatusSpec > { Tx0UnderflowW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_full (& mut self) -> Rx0FullW < IrqstatusSpec > { Rx0FullW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_overflow (& mut self) -> Rx0OverflowW < IrqstatusSpec > { Rx0OverflowW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_empty (& mut self) -> Tx1EmptyW < IrqstatusSpec > { Tx1EmptyW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_underflow (& mut self) -> Tx1UnderflowW < IrqstatusSpec > { Tx1UnderflowW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx1_full (& mut self) -> Rx1FullW < IrqstatusSpec > { Rx1FullW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_10 (& mut self) -> Reserved10W < IrqstatusSpec > { Reserved10W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_empty (& mut self) -> Tx2EmptyW < IrqstatusSpec > { Tx2EmptyW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_underflow (& mut self) -> Tx2UnderflowW < IrqstatusSpec > { Tx2UnderflowW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx2_full (& mut self) -> Rx2FullW < IrqstatusSpec > { Rx2FullW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_9 (& mut self) -> Reserved9W < IrqstatusSpec > { Reserved9W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_empty (& mut self) -> Tx3EmptyW < IrqstatusSpec > { Tx3EmptyW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_underflow (& mut self) -> Tx3UnderflowW < IrqstatusSpec > { Tx3UnderflowW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx3_full (& mut self) -> Rx3FullW < IrqstatusSpec > { Rx3FullW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_7 (& mut self) -> Reserved7W < IrqstatusSpec > { Reserved7W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn wks (& mut self) -> WksW < IrqstatusSpec > { WksW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn eow (& mut self) -> EowW < IrqstatusSpec > { EowW :: new (self , 17) } # [doc = "Bits 18:31 - 31:18\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_8 (& mut self) -> Reserved8W < IrqstatusSpec > { Reserved8W :: new (self , 18) } } # [doc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`irqstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqstatusSpec ; impl crate :: RegisterSpec for IrqstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`irqstatus::R`](R) reader structure"]
impl crate :: Readable for IrqstatusSpec { } # [doc = "`write(|w| ..)` method takes [`irqstatus::W`](W) writer structure"]
impl crate :: Writable for IrqstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IRQSTATUS to value 0"]
impl crate :: Resettable for IrqstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IRQENABLE (rw) register accessor: This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`irqenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqenable`]
module"]
# [doc (alias = "IRQENABLE")]
pub type Irqenable = crate :: Reg < irqenable :: IrqenableSpec > ; # [doc = "This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis."]
pub mod irqenable { # [doc = "Register `IRQENABLE` reader"]
pub type R = crate :: R < IrqenableSpec > ; # [doc = "Register `IRQENABLE` writer"]
pub type W = crate :: W < IrqenableSpec > ; # [doc = "Field `TX0_EMPTY_ENABLE` reader - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
pub type Tx0EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX0_EMPTY_ENABLE` writer - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
pub type Tx0EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX0_UNDERFLOW_ENABLE` reader - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
pub type Tx0UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX0_UNDERFLOW_ENABLE` writer - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
pub type Tx0UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_FULL_ENABLE` reader - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
pub type Rx0FullEnableR = crate :: BitReader ; # [doc = "Field `RX0_FULL_ENABLE` writer - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
pub type Rx0FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_OVERFLOW_ENABLE` reader - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
pub type Rx0OverflowEnableR = crate :: BitReader ; # [doc = "Field `RX0_OVERFLOW_ENABLE` writer - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
pub type Rx0OverflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_EMPTY_ENABLE` reader - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
pub type Tx1EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX1_EMPTY_ENABLE` writer - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
pub type Tx1EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_UNDERFLOW_ENABLE` reader - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
pub type Tx1UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX1_UNDERFLOW_ENABLE` writer - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
pub type Tx1UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX1_FULL_ENABLE` reader - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
pub type Rx1FullEnableR = crate :: BitReader ; # [doc = "Field `RX1_FULL_ENABLE` writer - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
pub type Rx1FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_3` reader - 7:7\\]
Reads return 0 - (RO )"]
pub type Reserved3R = crate :: BitReader ; # [doc = "Field `RESERVED_3` writer - 7:7\\]
Reads return 0 - (RO )"]
pub type Reserved3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_EMPTY_ENABLE` reader - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
pub type Tx2EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX2_EMPTY_ENABLE` writer - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
pub type Tx2EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_UNDERFLOW_ENABLE` reader - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
pub type Tx2UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX2_UNDERFLOW_ENABLE` writer - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
pub type Tx2UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX2_FULL_ENABLE` reader - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
pub type Rx2FullEnableR = crate :: BitReader ; # [doc = "Field `RX2_FULL_ENABLE` writer - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
pub type Rx2FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_6` reader - 11:11\\]
Reads return 0 - (RO )"]
pub type Reserved6R = crate :: BitReader ; # [doc = "Field `RESERVED_6` writer - 11:11\\]
Reads return 0 - (RO )"]
pub type Reserved6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_EMPTY_ENABLE` reader - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
pub type Tx3EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX3_EMPTY_ENABLE` writer - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
pub type Tx3EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_UNDERFLOW_ENABLE` reader - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
pub type Tx3UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX3_UNDERFLOW_ENABLE` writer - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
pub type Tx3UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX3_FULL_ENABLE` reader - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
pub type Rx3FullEnableR = crate :: BitReader ; # [doc = "Field `RX3_FULL_ENABLE` writer - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
pub type Rx3FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_4` reader - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved4R = crate :: BitReader ; # [doc = "Field `RESERVED_4` writer - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WKE` reader - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkeR = crate :: BitReader ; # [doc = "Field `WKE` writer - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOW_ENABLE` reader - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
pub type EowEnableR = crate :: BitReader ; # [doc = "Field `EOW_ENABLE` writer - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
pub type EowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_5` reader - 31:18\\]
Reads return 0 - (RO )"]
pub type Reserved5R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_5` writer - 31:18\\]
Reads return 0 - (RO )"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn tx0_empty_enable (& self) -> Tx0EmptyEnableR { Tx0EmptyEnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn tx0_underflow_enable (& self) -> Tx0UnderflowEnableR { Tx0UnderflowEnableR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn rx0_full_enable (& self) -> Rx0FullEnableR { Rx0FullEnableR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn rx0_overflow_enable (& self) -> Rx0OverflowEnableR { Rx0OverflowEnableR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
pub fn tx1_empty_enable (& self) -> Tx1EmptyEnableR { Tx1EmptyEnableR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
pub fn tx1_underflow_enable (& self) -> Tx1UnderflowEnableR { Tx1UnderflowEnableR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
pub fn rx1_full_enable (& self) -> Rx1FullEnableR { Rx1FullEnableR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Reads return 0 - (RO )"]
# [inline (always)]
pub fn reserved_3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
pub fn tx2_empty_enable (& self) -> Tx2EmptyEnableR { Tx2EmptyEnableR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
pub fn tx2_underflow_enable (& self) -> Tx2UnderflowEnableR { Tx2UnderflowEnableR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
pub fn rx2_full_enable (& self) -> Rx2FullEnableR { Rx2FullEnableR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Reads return 0 - (RO )"]
# [inline (always)]
pub fn reserved_6 (& self) -> Reserved6R { Reserved6R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
# [inline (always)]
pub fn tx3_empty_enable (& self) -> Tx3EmptyEnableR { Tx3EmptyEnableR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
pub fn tx3_underflow_enable (& self) -> Tx3UnderflowEnableR { Tx3UnderflowEnableR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
pub fn rx3_full_enable (& self) -> Rx3FullEnableR { Rx3FullEnableR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
pub fn wke (& self) -> WkeR { WkeR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
# [inline (always)]
pub fn eow_enable (& self) -> EowEnableR { EowEnableR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:31 - 31:18\\]
Reads return 0 - (RO )"]
# [inline (always)]
pub fn reserved_5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_empty_enable (& mut self) -> Tx0EmptyEnableW < IrqenableSpec > { Tx0EmptyEnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_underflow_enable (& mut self) -> Tx0UnderflowEnableW < IrqenableSpec > { Tx0UnderflowEnableW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_full_enable (& mut self) -> Rx0FullEnableW < IrqenableSpec > { Rx0FullEnableW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_overflow_enable (& mut self) -> Rx0OverflowEnableW < IrqenableSpec > { Rx0OverflowEnableW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_empty_enable (& mut self) -> Tx1EmptyEnableW < IrqenableSpec > { Tx1EmptyEnableW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_underflow_enable (& mut self) -> Tx1UnderflowEnableW < IrqenableSpec > { Tx1UnderflowEnableW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx1_full_enable (& mut self) -> Rx1FullEnableW < IrqenableSpec > { Rx1FullEnableW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Reads return 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_3 (& mut self) -> Reserved3W < IrqenableSpec > { Reserved3W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_empty_enable (& mut self) -> Tx2EmptyEnableW < IrqenableSpec > { Tx2EmptyEnableW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_underflow_enable (& mut self) -> Tx2UnderflowEnableW < IrqenableSpec > { Tx2UnderflowEnableW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx2_full_enable (& mut self) -> Rx2FullEnableW < IrqenableSpec > { Rx2FullEnableW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Reads return 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_6 (& mut self) -> Reserved6W < IrqenableSpec > { Reserved6W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_empty_enable (& mut self) -> Tx3EmptyEnableW < IrqenableSpec > { Tx3EmptyEnableW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_underflow_enable (& mut self) -> Tx3UnderflowEnableW < IrqenableSpec > { Tx3UnderflowEnableW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx3_full_enable (& mut self) -> Rx3FullEnableW < IrqenableSpec > { Rx3FullEnableW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_4 (& mut self) -> Reserved4W < IrqenableSpec > { Reserved4W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn wke (& mut self) -> WkeW < IrqenableSpec > { WkeW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn eow_enable (& mut self) -> EowEnableW < IrqenableSpec > { EowEnableW :: new (self , 17) } # [doc = "Bits 18:31 - 31:18\\]
Reads return 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_5 (& mut self) -> Reserved5W < IrqenableSpec > { Reserved5W :: new (self , 18) } } # [doc = "This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`irqenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqenableSpec ; impl crate :: RegisterSpec for IrqenableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`irqenable::R`](R) reader structure"]
impl crate :: Readable for IrqenableSpec { } # [doc = "`write(|w| ..)` method takes [`irqenable::W`](W) writer structure"]
impl crate :: Writable for IrqenableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IRQENABLE to value 0"]
impl crate :: Resettable for IrqenableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WAKEUPENABLE (rw) register accessor: The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeupenable`]
module"]
# [doc (alias = "WAKEUPENABLE")]
pub type Wakeupenable = crate :: Reg < wakeupenable :: WakeupenableSpec > ; # [doc = "The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."]
pub mod wakeupenable { # [doc = "Register `WAKEUPENABLE` reader"]
pub type R = crate :: R < WakeupenableSpec > ; # [doc = "Register `WAKEUPENABLE` writer"]
pub type W = crate :: W < WakeupenableSpec > ; # [doc = "Field `WKEN` reader - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkenR = crate :: BitReader ; # [doc = "Field `WKEN` writer - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_18` reader - 31:1\\]
Reads returns 0 - (RO )"]
pub type Reserved18R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_18` writer - 31:1\\]
Reads returns 0 - (RO )"]
pub type Reserved18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
pub fn wken (& self) -> WkenR { WkenR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_18 (& self) -> Reserved18R { Reserved18R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn wken (& mut self) -> WkenW < WakeupenableSpec > { WkenW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_18 (& mut self) -> Reserved18W < WakeupenableSpec > { Reserved18W :: new (self , 1) } } # [doc = "The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WakeupenableSpec ; impl crate :: RegisterSpec for WakeupenableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wakeupenable::R`](R) reader structure"]
impl crate :: Readable for WakeupenableSpec { } # [doc = "`write(|w| ..)` method takes [`wakeupenable::W`](W) writer structure"]
impl crate :: Writable for WakeupenableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WAKEUPENABLE to value 0"]
impl crate :: Resettable for WakeupenableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYST (rw) register accessor: This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`syst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syst`]
module"]
# [doc (alias = "SYST")]
pub type Syst = crate :: Reg < syst :: SystSpec > ; # [doc = "This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode."]
pub mod syst { # [doc = "Register `SYST` reader"]
pub type R = crate :: R < SystSpec > ; # [doc = "Register `SYST` writer"]
pub type W = crate :: W < SystSpec > ; # [doc = "Field `SPIEN_0` reader - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien0R = crate :: BitReader ; # [doc = "Field `SPIEN_0` writer - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIEN_1` reader - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien1R = crate :: BitReader ; # [doc = "Field `SPIEN_1` writer - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIEN_2` reader - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien2R = crate :: BitReader ; # [doc = "Field `SPIEN_2` writer - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIEN_3` reader - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien3R = crate :: BitReader ; # [doc = "Field `SPIEN_3` writer - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDAT_0` reader - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat0R = crate :: BitReader ; # [doc = "Field `SPIDAT_0` writer - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDAT_1` reader - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat1R = crate :: BitReader ; # [doc = "Field `SPIDAT_1` writer - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPICLK` reader - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
pub type SpiclkR = crate :: BitReader ; # [doc = "Field `SPICLK` writer - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
pub type SpiclkW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKD` reader - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
pub type WakdR = crate :: BitReader ; # [doc = "Field `WAKD` writer - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
pub type WakdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDATDIR0` reader - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
pub type Spidatdir0R = crate :: BitReader ; # [doc = "Field `SPIDATDIR0` writer - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
pub type Spidatdir0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDATDIR1` reader - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
pub type Spidatdir1R = crate :: BitReader ; # [doc = "Field `SPIDATDIR1` writer - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
pub type Spidatdir1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIENDIR` reader - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
pub type SpiendirR = crate :: BitReader ; # [doc = "Field `SPIENDIR` writer - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
pub type SpiendirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SSB` reader - 11:11\\]
Set status bit - (RW )"]
pub type SsbR = crate :: BitReader ; # [doc = "Field `SSB` writer - 11:11\\]
Set status bit - (RW )"]
pub type SsbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_17` reader - 31:12\\]
Reads returns 0 - (RO )"]
pub type Reserved17R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_17` writer - 31:12\\]
Reads returns 0 - (RO )"]
pub type Reserved17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_0 (& self) -> Spien0R { Spien0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_1 (& self) -> Spien1R { Spien1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_2 (& self) -> Spien2R { Spien2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_3 (& self) -> Spien3R { Spien3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spidat_0 (& self) -> Spidat0R { Spidat0R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spidat_1 (& self) -> Spidat1R { Spidat1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
# [inline (always)]
pub fn spiclk (& self) -> SpiclkR { SpiclkR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
# [inline (always)]
pub fn wakd (& self) -> WakdR { WakdR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
# [inline (always)]
pub fn spidatdir0 (& self) -> Spidatdir0R { Spidatdir0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
# [inline (always)]
pub fn spidatdir1 (& self) -> Spidatdir1R { Spidatdir1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
# [inline (always)]
pub fn spiendir (& self) -> SpiendirR { SpiendirR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Set status bit - (RW )"]
# [inline (always)]
pub fn ssb (& self) -> SsbR { SsbR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:31 - 31:12\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_17 (& self) -> Reserved17R { Reserved17R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_0 (& mut self) -> Spien0W < SystSpec > { Spien0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_1 (& mut self) -> Spien1W < SystSpec > { Spien1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_2 (& mut self) -> Spien2W < SystSpec > { Spien2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_3 (& mut self) -> Spien3W < SystSpec > { Spien3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spidat_0 (& mut self) -> Spidat0W < SystSpec > { Spidat0W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spidat_1 (& mut self) -> Spidat1W < SystSpec > { Spidat1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
# [inline (always)]
# [must_use]
pub fn spiclk (& mut self) -> SpiclkW < SystSpec > { SpiclkW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
# [inline (always)]
# [must_use]
pub fn wakd (& mut self) -> WakdW < SystSpec > { WakdW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn spidatdir0 (& mut self) -> Spidatdir0W < SystSpec > { Spidatdir0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn spidatdir1 (& mut self) -> Spidatdir1W < SystSpec > { Spidatdir1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
# [inline (always)]
# [must_use]
pub fn spiendir (& mut self) -> SpiendirW < SystSpec > { SpiendirW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Set status bit - (RW )"]
# [inline (always)]
# [must_use]
pub fn ssb (& mut self) -> SsbW < SystSpec > { SsbW :: new (self , 11) } # [doc = "Bits 12:31 - 31:12\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_17 (& mut self) -> Reserved17W < SystSpec > { Reserved17W :: new (self , 12) } } # [doc = "This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`syst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SystSpec ; impl crate :: RegisterSpec for SystSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`syst::R`](R) reader structure"]
impl crate :: Readable for SystSpec { } # [doc = "`write(|w| ..)` method takes [`syst::W`](W) writer structure"]
impl crate :: Writable for SystSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYST to value 0"]
impl crate :: Resettable for SystSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MODULCTRL (rw) register accessor: This register is dedicated to the configuration of the serial port interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`modulctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modulctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modulctrl`]
module"]
# [doc (alias = "MODULCTRL")]
pub type Modulctrl = crate :: Reg < modulctrl :: ModulctrlSpec > ; # [doc = "This register is dedicated to the configuration of the serial port interface."]
pub mod modulctrl { # [doc = "Register `MODULCTRL` reader"]
pub type R = crate :: R < ModulctrlSpec > ; # [doc = "Register `MODULCTRL` writer"]
pub type W = crate :: W < ModulctrlSpec > ; # [doc = "Field `SINGLE` reader - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
pub type SingleR = crate :: BitReader ; # [doc = "Field `SINGLE` writer - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
pub type SingleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PIN34` reader - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
pub type Pin34R = crate :: BitReader ; # [doc = "Field `PIN34` writer - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
pub type Pin34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MS` reader - 2:2\\]
Master/ Slave - (RW )"]
pub type MsR = crate :: BitReader ; # [doc = "Field `MS` writer - 2:2\\]
Master/ Slave - (RW )"]
pub type MsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SYSTEM_TEST` reader - 3:3\\]
Enables the system test mode - (RW )"]
pub type SystemTestR = crate :: BitReader ; # [doc = "Field `SYSTEM_TEST` writer - 3:3\\]
Enables the system test mode - (RW )"]
pub type SystemTestW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INITDLY` reader - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
pub type InitdlyR = crate :: FieldReader ; # [doc = "Field `INITDLY` writer - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
pub type InitdlyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `MOA` reader - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
pub type MoaR = crate :: BitReader ; # [doc = "Field `MOA` writer - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
pub type MoaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FDAA` reader - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
pub type FdaaR = crate :: BitReader ; # [doc = "Field `FDAA` writer - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
pub type FdaaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_11` reader - 31:9\\]
Reads returns 0 - (RO )"]
pub type Reserved11R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_11` writer - 31:9\\]
Reads returns 0 - (RO )"]
pub type Reserved11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
# [inline (always)]
pub fn single (& self) -> SingleR { SingleR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
# [inline (always)]
pub fn pin34 (& self) -> Pin34R { Pin34R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Master/ Slave - (RW )"]
# [inline (always)]
pub fn ms (& self) -> MsR { MsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Enables the system test mode - (RW )"]
# [inline (always)]
pub fn system_test (& self) -> SystemTestR { SystemTestR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
# [inline (always)]
pub fn initdly (& self) -> InitdlyR { InitdlyR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
# [inline (always)]
pub fn moa (& self) -> MoaR { MoaR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
# [inline (always)]
pub fn fdaa (& self) -> FdaaR { FdaaR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:31 - 31:9\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_11 (& self) -> Reserved11R { Reserved11R :: new ((self . bits >> 9) & 0x007f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn single (& mut self) -> SingleW < ModulctrlSpec > { SingleW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
# [inline (always)]
# [must_use]
pub fn pin34 (& mut self) -> Pin34W < ModulctrlSpec > { Pin34W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Master/ Slave - (RW )"]
# [inline (always)]
# [must_use]
pub fn ms (& mut self) -> MsW < ModulctrlSpec > { MsW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Enables the system test mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn system_test (& mut self) -> SystemTestW < ModulctrlSpec > { SystemTestW :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
# [inline (always)]
# [must_use]
pub fn initdly (& mut self) -> InitdlyW < ModulctrlSpec > { InitdlyW :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
# [inline (always)]
# [must_use]
pub fn moa (& mut self) -> MoaW < ModulctrlSpec > { MoaW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
# [inline (always)]
# [must_use]
pub fn fdaa (& mut self) -> FdaaW < ModulctrlSpec > { FdaaW :: new (self , 8) } # [doc = "Bits 9:31 - 31:9\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_11 (& mut self) -> Reserved11W < ModulctrlSpec > { Reserved11W :: new (self , 9) } } # [doc = "This register is dedicated to the configuration of the serial port interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`modulctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modulctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ModulctrlSpec ; impl crate :: RegisterSpec for ModulctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`modulctrl::R`](R) reader structure"]
impl crate :: Readable for ModulctrlSpec { } # [doc = "`write(|w| ..)` method takes [`modulctrl::W`](W) writer structure"]
impl crate :: Writable for ModulctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MODULCTRL to value 0"]
impl crate :: Resettable for ModulctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH0CONF (rw) register accessor: This register is dedicated to the configuration of the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0conf`]
module"]
# [doc (alias = "CH0CONF")]
pub type Ch0conf = crate :: Reg < ch0conf :: Ch0confSpec > ; # [doc = "This register is dedicated to the configuration of the channel 0"]
pub mod ch0conf { # [doc = "Register `CH0CONF` reader"]
pub type R = crate :: R < Ch0confSpec > ; # [doc = "Register `CH0CONF` writer"]
pub type W = crate :: W < Ch0confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIENSLV` reader - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
pub type SpienslvR = crate :: FieldReader ; # [doc = "Field `SPIENSLV` writer - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
pub type SpienslvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS0` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs0R = crate :: FieldReader ; # [doc = "Field `TCS0` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
# [inline (always)]
pub fn spienslv (& self) -> SpienslvR { SpienslvR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs0 (& self) -> Tcs0R { Tcs0R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch0confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch0confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch0confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch0confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch0confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch0confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch0confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch0confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch0confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch0confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch0confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch0confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch0confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
# [inline (always)]
# [must_use]
pub fn spienslv (& mut self) -> SpienslvW < Ch0confSpec > { SpienslvW :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch0confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch0confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs0 (& mut self) -> Tcs0W < Ch0confSpec > { Tcs0W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch0confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch0confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch0confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch0confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch0confSpec ; impl crate :: RegisterSpec for Ch0confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch0conf::R`](R) reader structure"]
impl crate :: Readable for Ch0confSpec { } # [doc = "`write(|w| ..)` method takes [`ch0conf::W`](W) writer structure"]
impl crate :: Writable for Ch0confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH0CONF to value 0"]
impl crate :: Resettable for Ch0confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH0STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0stat`]
module"]
# [doc (alias = "CH0STAT")]
pub type Ch0stat = crate :: Reg < ch0stat :: Ch0statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 0"]
pub mod ch0stat { # [doc = "Register `CH0STAT` reader"]
pub type R = crate :: R < Ch0statSpec > ; # [doc = "Register `CH0STAT` writer"]
pub type W = crate :: W < Ch0statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch0statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch0statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch0statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch0statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch0statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch0statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch0statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch0statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch0statSpec ; impl crate :: RegisterSpec for Ch0statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch0stat::R`](R) reader structure"]
impl crate :: Readable for Ch0statSpec { } # [doc = "`write(|w| ..)` method takes [`ch0stat::W`](W) writer structure"]
impl crate :: Writable for Ch0statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH0STAT to value 0"]
impl crate :: Resettable for Ch0statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH0CTRL (rw) register accessor: This register is dedicated to enable the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0ctrl`]
module"]
# [doc (alias = "CH0CTRL")]
pub type Ch0ctrl = crate :: Reg < ch0ctrl :: Ch0ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 0"]
pub mod ch0ctrl { # [doc = "Register `CH0CTRL` reader"]
pub type R = crate :: R < Ch0ctrlSpec > ; # [doc = "Register `CH0CTRL` writer"]
pub type W = crate :: W < Ch0ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch0ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch0ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch0ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch0ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch0ctrlSpec ; impl crate :: RegisterSpec for Ch0ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch0ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch0ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch0ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch0ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH0CTRL to value 0"]
impl crate :: Resettable for Ch0ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX0 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx0`]
module"]
# [doc (alias = "TX0")]
pub type Tx0 = crate :: Reg < tx0 :: Tx0Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx0 { # [doc = "Register `TX0` reader"]
pub type R = crate :: R < Tx0Spec > ; # [doc = "Register `TX0` writer"]
pub type W = crate :: W < Tx0Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 0 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 0 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx0Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx0Spec ; impl crate :: RegisterSpec for Tx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx0::R`](R) reader structure"]
impl crate :: Readable for Tx0Spec { } # [doc = "`write(|w| ..)` method takes [`tx0::W`](W) writer structure"]
impl crate :: Writable for Tx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX0 to value 0"]
impl crate :: Resettable for Tx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX0 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx0`]
module"]
# [doc (alias = "RX0")]
pub type Rx0 = crate :: Reg < rx0 :: Rx0Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx0 { # [doc = "Register `RX0` reader"]
pub type R = crate :: R < Rx0Spec > ; # [doc = "Register `RX0` writer"]
pub type W = crate :: W < Rx0Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 0 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 0 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx0Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx0Spec ; impl crate :: RegisterSpec for Rx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx0::R`](R) reader structure"]
impl crate :: Readable for Rx0Spec { } # [doc = "`write(|w| ..)` method takes [`rx0::W`](W) writer structure"]
impl crate :: Writable for Rx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX0 to value 0"]
impl crate :: Resettable for Rx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1CONF (rw) register accessor: This register is dedicated to the configuration of the channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1conf`]
module"]
# [doc (alias = "CH1CONF")]
pub type Ch1conf = crate :: Reg < ch1conf :: Ch1confSpec > ; # [doc = "This register is dedicated to the configuration of the channel."]
pub mod ch1conf { # [doc = "Register `CH1CONF` reader"]
pub type R = crate :: R < Ch1confSpec > ; # [doc = "Register `CH1CONF` writer"]
pub type W = crate :: W < Ch1confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS1` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs1R = crate :: FieldReader ; # [doc = "Field `TCS1` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs1 (& self) -> Tcs1R { Tcs1R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch1confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch1confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch1confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch1confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch1confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch1confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch1confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch1confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch1confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch1confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch1confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch1confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch1confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch1confSpec > { Reserved1W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch1confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch1confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs1 (& mut self) -> Tcs1W < Ch1confSpec > { Tcs1W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch1confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch1confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch1confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch1confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch1confSpec ; impl crate :: RegisterSpec for Ch1confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1conf::R`](R) reader structure"]
impl crate :: Readable for Ch1confSpec { } # [doc = "`write(|w| ..)` method takes [`ch1conf::W`](W) writer structure"]
impl crate :: Writable for Ch1confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1CONF to value 0"]
impl crate :: Resettable for Ch1confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1stat`]
module"]
# [doc (alias = "CH1STAT")]
pub type Ch1stat = crate :: Reg < ch1stat :: Ch1statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 1"]
pub mod ch1stat { # [doc = "Register `CH1STAT` reader"]
pub type R = crate :: R < Ch1statSpec > ; # [doc = "Register `CH1STAT` writer"]
pub type W = crate :: W < Ch1statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch1statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch1statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch1statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch1statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch1statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch1statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch1statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch1statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch1statSpec ; impl crate :: RegisterSpec for Ch1statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1stat::R`](R) reader structure"]
impl crate :: Readable for Ch1statSpec { } # [doc = "`write(|w| ..)` method takes [`ch1stat::W`](W) writer structure"]
impl crate :: Writable for Ch1statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1STAT to value 0"]
impl crate :: Resettable for Ch1statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1CTRL (rw) register accessor: This register is dedicated to enable the channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1ctrl`]
module"]
# [doc (alias = "CH1CTRL")]
pub type Ch1ctrl = crate :: Reg < ch1ctrl :: Ch1ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 1"]
pub mod ch1ctrl { # [doc = "Register `CH1CTRL` reader"]
pub type R = crate :: R < Ch1ctrlSpec > ; # [doc = "Register `CH1CTRL` writer"]
pub type W = crate :: W < Ch1ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch1ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch1ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch1ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch1ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch1ctrlSpec ; impl crate :: RegisterSpec for Ch1ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch1ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch1ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch1ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1CTRL to value 0"]
impl crate :: Resettable for Ch1ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX1 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx1`]
module"]
# [doc (alias = "TX1")]
pub type Tx1 = crate :: Reg < tx1 :: Tx1Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx1 { # [doc = "Register `TX1` reader"]
pub type R = crate :: R < Tx1Spec > ; # [doc = "Register `TX1` writer"]
pub type W = crate :: W < Tx1Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 1 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 1 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx1Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx1Spec ; impl crate :: RegisterSpec for Tx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx1::R`](R) reader structure"]
impl crate :: Readable for Tx1Spec { } # [doc = "`write(|w| ..)` method takes [`tx1::W`](W) writer structure"]
impl crate :: Writable for Tx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX1 to value 0"]
impl crate :: Resettable for Tx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX1 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx1`]
module"]
# [doc (alias = "RX1")]
pub type Rx1 = crate :: Reg < rx1 :: Rx1Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx1 { # [doc = "Register `RX1` reader"]
pub type R = crate :: R < Rx1Spec > ; # [doc = "Register `RX1` writer"]
pub type W = crate :: W < Rx1Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 1 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 1 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx1Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx1Spec ; impl crate :: RegisterSpec for Rx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx1::R`](R) reader structure"]
impl crate :: Readable for Rx1Spec { } # [doc = "`write(|w| ..)` method takes [`rx1::W`](W) writer structure"]
impl crate :: Writable for Rx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX1 to value 0"]
impl crate :: Resettable for Rx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2CONF (rw) register accessor: This register is dedicated to the configuration of the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2conf`]
module"]
# [doc (alias = "CH2CONF")]
pub type Ch2conf = crate :: Reg < ch2conf :: Ch2confSpec > ; # [doc = "This register is dedicated to the configuration of the channel 2"]
pub mod ch2conf { # [doc = "Register `CH2CONF` reader"]
pub type R = crate :: R < Ch2confSpec > ; # [doc = "Register `CH2CONF` writer"]
pub type W = crate :: W < Ch2confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS2` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs2R = crate :: FieldReader ; # [doc = "Field `TCS2` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs2 (& self) -> Tcs2R { Tcs2R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch2confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch2confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch2confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch2confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch2confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch2confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch2confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch2confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch2confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch2confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch2confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch2confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch2confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch2confSpec > { Reserved1W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch2confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch2confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs2 (& mut self) -> Tcs2W < Ch2confSpec > { Tcs2W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch2confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch2confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch2confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch2confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch2confSpec ; impl crate :: RegisterSpec for Ch2confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2conf::R`](R) reader structure"]
impl crate :: Readable for Ch2confSpec { } # [doc = "`write(|w| ..)` method takes [`ch2conf::W`](W) writer structure"]
impl crate :: Writable for Ch2confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2CONF to value 0"]
impl crate :: Resettable for Ch2confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2stat`]
module"]
# [doc (alias = "CH2STAT")]
pub type Ch2stat = crate :: Reg < ch2stat :: Ch2statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 2"]
pub mod ch2stat { # [doc = "Register `CH2STAT` reader"]
pub type R = crate :: R < Ch2statSpec > ; # [doc = "Register `CH2STAT` writer"]
pub type W = crate :: W < Ch2statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch2statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch2statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch2statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch2statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch2statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch2statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch2statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch2statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch2statSpec ; impl crate :: RegisterSpec for Ch2statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2stat::R`](R) reader structure"]
impl crate :: Readable for Ch2statSpec { } # [doc = "`write(|w| ..)` method takes [`ch2stat::W`](W) writer structure"]
impl crate :: Writable for Ch2statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2STAT to value 0"]
impl crate :: Resettable for Ch2statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2CTRL (rw) register accessor: This register is dedicated to enable the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2ctrl`]
module"]
# [doc (alias = "CH2CTRL")]
pub type Ch2ctrl = crate :: Reg < ch2ctrl :: Ch2ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 2"]
pub mod ch2ctrl { # [doc = "Register `CH2CTRL` reader"]
pub type R = crate :: R < Ch2ctrlSpec > ; # [doc = "Register `CH2CTRL` writer"]
pub type W = crate :: W < Ch2ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch2ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch2ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch2ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch2ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch2ctrlSpec ; impl crate :: RegisterSpec for Ch2ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch2ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch2ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch2ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2CTRL to value 0"]
impl crate :: Resettable for Ch2ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX2 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx2`]
module"]
# [doc (alias = "TX2")]
pub type Tx2 = crate :: Reg < tx2 :: Tx2Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx2 { # [doc = "Register `TX2` reader"]
pub type R = crate :: R < Tx2Spec > ; # [doc = "Register `TX2` writer"]
pub type W = crate :: W < Tx2Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 2 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 2 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx2Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx2Spec ; impl crate :: RegisterSpec for Tx2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx2::R`](R) reader structure"]
impl crate :: Readable for Tx2Spec { } # [doc = "`write(|w| ..)` method takes [`tx2::W`](W) writer structure"]
impl crate :: Writable for Tx2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX2 to value 0"]
impl crate :: Resettable for Tx2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX2 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx2`]
module"]
# [doc (alias = "RX2")]
pub type Rx2 = crate :: Reg < rx2 :: Rx2Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx2 { # [doc = "Register `RX2` reader"]
pub type R = crate :: R < Rx2Spec > ; # [doc = "Register `RX2` writer"]
pub type W = crate :: W < Rx2Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 2 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 2 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx2Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx2Spec ; impl crate :: RegisterSpec for Rx2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx2::R`](R) reader structure"]
impl crate :: Readable for Rx2Spec { } # [doc = "`write(|w| ..)` method takes [`rx2::W`](W) writer structure"]
impl crate :: Writable for Rx2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX2 to value 0"]
impl crate :: Resettable for Rx2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3CONF (rw) register accessor: This register is dedicated to the configuration of the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3conf`]
module"]
# [doc (alias = "CH3CONF")]
pub type Ch3conf = crate :: Reg < ch3conf :: Ch3confSpec > ; # [doc = "This register is dedicated to the configuration of the channel 3"]
pub mod ch3conf { # [doc = "Register `CH3CONF` reader"]
pub type R = crate :: R < Ch3confSpec > ; # [doc = "Register `CH3CONF` writer"]
pub type W = crate :: W < Ch3confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS3` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs3R = crate :: FieldReader ; # [doc = "Field `TCS3` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs3 (& self) -> Tcs3R { Tcs3R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch3confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch3confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch3confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch3confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch3confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch3confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch3confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch3confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch3confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch3confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch3confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch3confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch3confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch3confSpec > { Reserved1W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch3confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch3confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs3 (& mut self) -> Tcs3W < Ch3confSpec > { Tcs3W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch3confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch3confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch3confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch3confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch3confSpec ; impl crate :: RegisterSpec for Ch3confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3conf::R`](R) reader structure"]
impl crate :: Readable for Ch3confSpec { } # [doc = "`write(|w| ..)` method takes [`ch3conf::W`](W) writer structure"]
impl crate :: Writable for Ch3confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3CONF to value 0"]
impl crate :: Resettable for Ch3confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3stat`]
module"]
# [doc (alias = "CH3STAT")]
pub type Ch3stat = crate :: Reg < ch3stat :: Ch3statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 3"]
pub mod ch3stat { # [doc = "Register `CH3STAT` reader"]
pub type R = crate :: R < Ch3statSpec > ; # [doc = "Register `CH3STAT` writer"]
pub type W = crate :: W < Ch3statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch3statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch3statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch3statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch3statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch3statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch3statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch3statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch3statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch3statSpec ; impl crate :: RegisterSpec for Ch3statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3stat::R`](R) reader structure"]
impl crate :: Readable for Ch3statSpec { } # [doc = "`write(|w| ..)` method takes [`ch3stat::W`](W) writer structure"]
impl crate :: Writable for Ch3statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3STAT to value 0"]
impl crate :: Resettable for Ch3statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3CTRL (rw) register accessor: This register is dedicated to enable the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3ctrl`]
module"]
# [doc (alias = "CH3CTRL")]
pub type Ch3ctrl = crate :: Reg < ch3ctrl :: Ch3ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 3"]
pub mod ch3ctrl { # [doc = "Register `CH3CTRL` reader"]
pub type R = crate :: R < Ch3ctrlSpec > ; # [doc = "Register `CH3CTRL` writer"]
pub type W = crate :: W < Ch3ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch3ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch3ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch3ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch3ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch3ctrlSpec ; impl crate :: RegisterSpec for Ch3ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch3ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch3ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch3ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3CTRL to value 0"]
impl crate :: Resettable for Ch3ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX3 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx3`]
module"]
# [doc (alias = "TX3")]
pub type Tx3 = crate :: Reg < tx3 :: Tx3Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx3 { # [doc = "Register `TX3` reader"]
pub type R = crate :: R < Tx3Spec > ; # [doc = "Register `TX3` writer"]
pub type W = crate :: W < Tx3Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 3 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 3 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx3Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx3Spec ; impl crate :: RegisterSpec for Tx3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx3::R`](R) reader structure"]
impl crate :: Readable for Tx3Spec { } # [doc = "`write(|w| ..)` method takes [`tx3::W`](W) writer structure"]
impl crate :: Writable for Tx3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX3 to value 0"]
impl crate :: Resettable for Tx3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX3 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx3`]
module"]
# [doc (alias = "RX3")]
pub type Rx3 = crate :: Reg < rx3 :: Rx3Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx3 { # [doc = "Register `RX3` reader"]
pub type R = crate :: R < Rx3Spec > ; # [doc = "Register `RX3` writer"]
pub type W = crate :: W < Rx3Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 3 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 3 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx3Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx3Spec ; impl crate :: RegisterSpec for Rx3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx3::R`](R) reader structure"]
impl crate :: Readable for Rx3Spec { } # [doc = "`write(|w| ..)` method takes [`rx3::W`](W) writer structure"]
impl crate :: Writable for Rx3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX3 to value 0"]
impl crate :: Resettable for Rx3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XFERLEVEL (rw) register accessor: This register provides transfer levels needed while using FIFO buffer during transfer.\n\nYou can [`read`](crate::Reg::read) this register and get [`xferlevel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xferlevel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xferlevel`]
module"]
# [doc (alias = "XFERLEVEL")]
pub type Xferlevel = crate :: Reg < xferlevel :: XferlevelSpec > ; # [doc = "This register provides transfer levels needed while using FIFO buffer during transfer."]
pub mod xferlevel { # [doc = "Register `XFERLEVEL` reader"]
pub type R = crate :: R < XferlevelSpec > ; # [doc = "Register `XFERLEVEL` writer"]
pub type W = crate :: W < XferlevelSpec > ; # [doc = "Field `AEL` reader - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
pub type AelR = crate :: FieldReader ; # [doc = "Field `AEL` writer - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
pub type AelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `AFL` reader - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
pub type AflR = crate :: FieldReader ; # [doc = "Field `AFL` writer - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
pub type AflW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `WCNT` reader - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
pub type WcntR = crate :: FieldReader < u16 > ; # [doc = "Field `WCNT` writer - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
pub type WcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
# [inline (always)]
pub fn ael (& self) -> AelR { AelR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
# [inline (always)]
pub fn afl (& self) -> AflR { AflR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
# [inline (always)]
pub fn wcnt (& self) -> WcntR { WcntR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn ael (& mut self) -> AelW < XferlevelSpec > { AelW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
# [inline (always)]
# [must_use]
pub fn afl (& mut self) -> AflW < XferlevelSpec > { AflW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
# [inline (always)]
# [must_use]
pub fn wcnt (& mut self) -> WcntW < XferlevelSpec > { WcntW :: new (self , 16) } } # [doc = "This register provides transfer levels needed while using FIFO buffer during transfer.\n\nYou can [`read`](crate::Reg::read) this register and get [`xferlevel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xferlevel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XferlevelSpec ; impl crate :: RegisterSpec for XferlevelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xferlevel::R`](R) reader structure"]
impl crate :: Readable for XferlevelSpec { } # [doc = "`write(|w| ..)` method takes [`xferlevel::W`](W) writer structure"]
impl crate :: Writable for XferlevelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XFERLEVEL to value 0"]
impl crate :: Resettable for XferlevelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DAFTX (rw) register accessor: This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`daftx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daftx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daftx`]
module"]
# [doc (alias = "DAFTX")]
pub type Daftx = crate :: Reg < daftx :: DaftxSpec > ; # [doc = "This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."]
pub mod daftx { # [doc = "Register `DAFTX` reader"]
pub type R = crate :: R < DaftxSpec > ; # [doc = "Register `DAFTX` writer"]
pub type W = crate :: W < DaftxSpec > ; # [doc = "Field `DAFTDATA` reader - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
pub type DaftdataR = crate :: FieldReader < u32 > ; # [doc = "Field `DAFTDATA` writer - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
pub type DaftdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
# [inline (always)]
pub fn daftdata (& self) -> DaftdataR { DaftdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
# [inline (always)]
# [must_use]
pub fn daftdata (& mut self) -> DaftdataW < DaftxSpec > { DaftdataW :: new (self , 0) } } # [doc = "This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`daftx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daftx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DaftxSpec ; impl crate :: RegisterSpec for DaftxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`daftx::R`](R) reader structure"]
impl crate :: Readable for DaftxSpec { } # [doc = "`write(|w| ..)` method takes [`daftx::W`](W) writer structure"]
impl crate :: Writable for DaftxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DAFTX to value 0"]
impl crate :: Resettable for DaftxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DAFRX (rw) register accessor: This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`dafrx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dafrx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dafrx`]
module"]
# [doc (alias = "DAFRX")]
pub type Dafrx = crate :: Reg < dafrx :: DafrxSpec > ; # [doc = "This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."]
pub mod dafrx { # [doc = "Register `DAFRX` reader"]
pub type R = crate :: R < DafrxSpec > ; # [doc = "Register `DAFRX` writer"]
pub type W = crate :: W < DafrxSpec > ; # [doc = "Field `DAFRDATA` reader - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
pub type DafrdataR = crate :: FieldReader < u32 > ; # [doc = "Field `DAFRDATA` writer - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
pub type DafrdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
# [inline (always)]
pub fn dafrdata (& self) -> DafrdataR { DafrdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
# [inline (always)]
# [must_use]
pub fn dafrdata (& mut self) -> DafrdataW < DafrxSpec > { DafrdataW :: new (self , 0) } } # [doc = "This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`dafrx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dafrx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DafrxSpec ; impl crate :: RegisterSpec for DafrxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dafrx::R`](R) reader structure"]
impl crate :: Readable for DafrxSpec { } # [doc = "`write(|w| ..)` method takes [`dafrx::W`](W) writer structure"]
impl crate :: Writable for DafrxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DAFRX to value 0"]
impl crate :: Resettable for DafrxSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_CANCFG"]
pub struct AppCancfg { _marker : PhantomData < * const () > } unsafe impl Send for AppCancfg { } impl AppCancfg { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_cancfg :: RegisterBlock = 0x53f7_f800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_cancfg :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppCancfg { type Target = app_cancfg :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppCancfg { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppCancfg") . finish () } } # [doc = "APP_CANCFG"]
pub mod app_cancfg { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { ss_pid : SsPid , ss_ctrl : SsCtrl , ss_stat : SsStat , ss_ics : SsIcs , ss_irs : SsIrs , ss_iecs : SsIecs , ss_ie : SsIe , ss_ies : SsIes , ss_eoi : SsEoi , ss_ext_ts_ps : SsExtTsPs , ss_ext_ts_usic : SsExtTsUsic , _reserved11 : [u8 ; 0x01d4]
, crel : Crel , endn : Endn , cust : Cust , dbtp : Dbtp , test : Test , rwd : Rwd , cccr : Cccr , nbtp : Nbtp , tscc : Tscc , tscv : Tscv , tocc : Tocc , tocv : Tocv , res00 : Res00 , res01 : Res01 , res02 : Res02 , res03 : Res03 , ecr : Ecr , psr : Psr , tdcr : Tdcr , res04 : Res04 , ir : Ir , ie : Ie , ils : Ils , ile : Ile , res05 : Res05 , res06 : Res06 , res07 : Res07 , res08 : Res08 , res09 : Res09 , res10 : Res10 , res11 : Res11 , res12 : Res12 , gfc : Gfc , sidfc : Sidfc , xidfc : Xidfc , res13 : Res13 , xidam : Xidam , hpms : Hpms , ndat1 : Ndat1 , ndat2 : Ndat2 , rxf0c : Rxf0c , rxf0s : Rxf0s , rxf0a : Rxf0a , rxbc : Rxbc , rxf1c : Rxf1c , rxf1s : Rxf1s , rxf1a : Rxf1a , rxesc : Rxesc , txbc : Txbc , txfqs : Txfqs , txesc : Txesc , txbrp : Txbrp , txbar : Txbar , txbcr : Txbcr , txbto : Txbto , txbcf : Txbcf , txbtie : Txbtie , txbcie : Txbcie , res14 : Res14 , res15 : Res15 , txefc : Txefc , txefs : Txefs , txefa : Txefa , res16 : Res16 , } impl RegisterBlock { # [doc = "0x00 - SS_PID"]
# [inline (always)]
pub const fn ss_pid (& self) -> & SsPid { & self . ss_pid } # [doc = "0x04 - SS_CTRL"]
# [inline (always)]
pub const fn ss_ctrl (& self) -> & SsCtrl { & self . ss_ctrl } # [doc = "0x08 - SS_STAT"]
# [inline (always)]
pub const fn ss_stat (& self) -> & SsStat { & self . ss_stat } # [doc = "0x0c - SS_ICS"]
# [inline (always)]
pub const fn ss_ics (& self) -> & SsIcs { & self . ss_ics } # [doc = "0x10 - SS_IRS"]
# [inline (always)]
pub const fn ss_irs (& self) -> & SsIrs { & self . ss_irs } # [doc = "0x14 - SS_IECS"]
# [inline (always)]
pub const fn ss_iecs (& self) -> & SsIecs { & self . ss_iecs } # [doc = "0x18 - SS_IE"]
# [inline (always)]
pub const fn ss_ie (& self) -> & SsIe { & self . ss_ie } # [doc = "0x1c - SS_IES"]
# [inline (always)]
pub const fn ss_ies (& self) -> & SsIes { & self . ss_ies } # [doc = "0x20 - SS_EOI"]
# [inline (always)]
pub const fn ss_eoi (& self) -> & SsEoi { & self . ss_eoi } # [doc = "0x24 - SS_EXT_TS_PS"]
# [inline (always)]
pub const fn ss_ext_ts_ps (& self) -> & SsExtTsPs { & self . ss_ext_ts_ps } # [doc = "0x28 - SS_EXT_TS_USIC"]
# [inline (always)]
pub const fn ss_ext_ts_usic (& self) -> & SsExtTsUsic { & self . ss_ext_ts_usic } # [doc = "0x200 - CREL"]
# [inline (always)]
pub const fn crel (& self) -> & Crel { & self . crel } # [doc = "0x204 - ENDN"]
# [inline (always)]
pub const fn endn (& self) -> & Endn { & self . endn } # [doc = "0x208 - CUST"]
# [inline (always)]
pub const fn cust (& self) -> & Cust { & self . cust } # [doc = "0x20c - DBTP"]
# [inline (always)]
pub const fn dbtp (& self) -> & Dbtp { & self . dbtp } # [doc = "0x210 - TEST"]
# [inline (always)]
pub const fn test (& self) -> & Test { & self . test } # [doc = "0x214 - RWD"]
# [inline (always)]
pub const fn rwd (& self) -> & Rwd { & self . rwd } # [doc = "0x218 - CCCR"]
# [inline (always)]
pub const fn cccr (& self) -> & Cccr { & self . cccr } # [doc = "0x21c - NBTP"]
# [inline (always)]
pub const fn nbtp (& self) -> & Nbtp { & self . nbtp } # [doc = "0x220 - TSCC"]
# [inline (always)]
pub const fn tscc (& self) -> & Tscc { & self . tscc } # [doc = "0x224 - TSCV"]
# [inline (always)]
pub const fn tscv (& self) -> & Tscv { & self . tscv } # [doc = "0x228 - TOCC"]
# [inline (always)]
pub const fn tocc (& self) -> & Tocc { & self . tocc } # [doc = "0x22c - TOCV"]
# [inline (always)]
pub const fn tocv (& self) -> & Tocv { & self . tocv } # [doc = "0x230 - RES00"]
# [inline (always)]
pub const fn res00 (& self) -> & Res00 { & self . res00 } # [doc = "0x234 - RES01"]
# [inline (always)]
pub const fn res01 (& self) -> & Res01 { & self . res01 } # [doc = "0x238 - RES02"]
# [inline (always)]
pub const fn res02 (& self) -> & Res02 { & self . res02 } # [doc = "0x23c - RES03"]
# [inline (always)]
pub const fn res03 (& self) -> & Res03 { & self . res03 } # [doc = "0x240 - ECR"]
# [inline (always)]
pub const fn ecr (& self) -> & Ecr { & self . ecr } # [doc = "0x244 - PSR"]
# [inline (always)]
pub const fn psr (& self) -> & Psr { & self . psr } # [doc = "0x248 - TDCR"]
# [inline (always)]
pub const fn tdcr (& self) -> & Tdcr { & self . tdcr } # [doc = "0x24c - RES04"]
# [inline (always)]
pub const fn res04 (& self) -> & Res04 { & self . res04 } # [doc = "0x250 - IR"]
# [inline (always)]
pub const fn ir (& self) -> & Ir { & self . ir } # [doc = "0x254 - IE"]
# [inline (always)]
pub const fn ie (& self) -> & Ie { & self . ie } # [doc = "0x258 - ILS"]
# [inline (always)]
pub const fn ils (& self) -> & Ils { & self . ils } # [doc = "0x25c - ILE"]
# [inline (always)]
pub const fn ile (& self) -> & Ile { & self . ile } # [doc = "0x260 - RES05"]
# [inline (always)]
pub const fn res05 (& self) -> & Res05 { & self . res05 } # [doc = "0x264 - RES06"]
# [inline (always)]
pub const fn res06 (& self) -> & Res06 { & self . res06 } # [doc = "0x268 - RES07"]
# [inline (always)]
pub const fn res07 (& self) -> & Res07 { & self . res07 } # [doc = "0x26c - RES08"]
# [inline (always)]
pub const fn res08 (& self) -> & Res08 { & self . res08 } # [doc = "0x270 - RES09"]
# [inline (always)]
pub const fn res09 (& self) -> & Res09 { & self . res09 } # [doc = "0x274 - RES10"]
# [inline (always)]
pub const fn res10 (& self) -> & Res10 { & self . res10 } # [doc = "0x278 - RES11"]
# [inline (always)]
pub const fn res11 (& self) -> & Res11 { & self . res11 } # [doc = "0x27c - RES12"]
# [inline (always)]
pub const fn res12 (& self) -> & Res12 { & self . res12 } # [doc = "0x280 - GFC"]
# [inline (always)]
pub const fn gfc (& self) -> & Gfc { & self . gfc } # [doc = "0x284 - SIDFC"]
# [inline (always)]
pub const fn sidfc (& self) -> & Sidfc { & self . sidfc } # [doc = "0x288 - XIDFC"]
# [inline (always)]
pub const fn xidfc (& self) -> & Xidfc { & self . xidfc } # [doc = "0x28c - RES13"]
# [inline (always)]
pub const fn res13 (& self) -> & Res13 { & self . res13 } # [doc = "0x290 - XIDAM"]
# [inline (always)]
pub const fn xidam (& self) -> & Xidam { & self . xidam } # [doc = "0x294 - HPMS"]
# [inline (always)]
pub const fn hpms (& self) -> & Hpms { & self . hpms } # [doc = "0x298 - NDAT1"]
# [inline (always)]
pub const fn ndat1 (& self) -> & Ndat1 { & self . ndat1 } # [doc = "0x29c - NDAT2"]
# [inline (always)]
pub const fn ndat2 (& self) -> & Ndat2 { & self . ndat2 } # [doc = "0x2a0 - RXF0C"]
# [inline (always)]
pub const fn rxf0c (& self) -> & Rxf0c { & self . rxf0c } # [doc = "0x2a4 - RXF0S"]
# [inline (always)]
pub const fn rxf0s (& self) -> & Rxf0s { & self . rxf0s } # [doc = "0x2a8 - RXF0A"]
# [inline (always)]
pub const fn rxf0a (& self) -> & Rxf0a { & self . rxf0a } # [doc = "0x2ac - RXBC"]
# [inline (always)]
pub const fn rxbc (& self) -> & Rxbc { & self . rxbc } # [doc = "0x2b0 - RXF1C"]
# [inline (always)]
pub const fn rxf1c (& self) -> & Rxf1c { & self . rxf1c } # [doc = "0x2b4 - RXF1S"]
# [inline (always)]
pub const fn rxf1s (& self) -> & Rxf1s { & self . rxf1s } # [doc = "0x2b8 - RXF1A"]
# [inline (always)]
pub const fn rxf1a (& self) -> & Rxf1a { & self . rxf1a } # [doc = "0x2bc - RXESC"]
# [inline (always)]
pub const fn rxesc (& self) -> & Rxesc { & self . rxesc } # [doc = "0x2c0 - TXBC"]
# [inline (always)]
pub const fn txbc (& self) -> & Txbc { & self . txbc } # [doc = "0x2c4 - TXFQS"]
# [inline (always)]
pub const fn txfqs (& self) -> & Txfqs { & self . txfqs } # [doc = "0x2c8 - TXESC"]
# [inline (always)]
pub const fn txesc (& self) -> & Txesc { & self . txesc } # [doc = "0x2cc - TXBRP"]
# [inline (always)]
pub const fn txbrp (& self) -> & Txbrp { & self . txbrp } # [doc = "0x2d0 - TXBAR"]
# [inline (always)]
pub const fn txbar (& self) -> & Txbar { & self . txbar } # [doc = "0x2d4 - TXBCR"]
# [inline (always)]
pub const fn txbcr (& self) -> & Txbcr { & self . txbcr } # [doc = "0x2d8 - TXBTO"]
# [inline (always)]
pub const fn txbto (& self) -> & Txbto { & self . txbto } # [doc = "0x2dc - TXBCF"]
# [inline (always)]
pub const fn txbcf (& self) -> & Txbcf { & self . txbcf } # [doc = "0x2e0 - TXBTIE"]
# [inline (always)]
pub const fn txbtie (& self) -> & Txbtie { & self . txbtie } # [doc = "0x2e4 - TXBCIE"]
# [inline (always)]
pub const fn txbcie (& self) -> & Txbcie { & self . txbcie } # [doc = "0x2e8 - RES14"]
# [inline (always)]
pub const fn res14 (& self) -> & Res14 { & self . res14 } # [doc = "0x2ec - RES15"]
# [inline (always)]
pub const fn res15 (& self) -> & Res15 { & self . res15 } # [doc = "0x2f0 - TXEFC"]
# [inline (always)]
pub const fn txefc (& self) -> & Txefc { & self . txefc } # [doc = "0x2f4 - TXEFS"]
# [inline (always)]
pub const fn txefs (& self) -> & Txefs { & self . txefs } # [doc = "0x2f8 - TXEFA"]
# [inline (always)]
pub const fn txefa (& self) -> & Txefa { & self . txefa } # [doc = "0x2fc - RES16"]
# [inline (always)]
pub const fn res16 (& self) -> & Res16 { & self . res16 } } # [doc = "SS_PID (rw) register accessor: SS_PID\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_pid`]
module"]
# [doc (alias = "SS_PID")]
pub type SsPid = crate :: Reg < ss_pid :: SsPidSpec > ; # [doc = "SS_PID"]
pub mod ss_pid { # [doc = "Register `SS_PID` reader"]
pub type R = crate :: R < SsPidSpec > ; # [doc = "Register `SS_PID` writer"]
pub type W = crate :: W < SsPidSpec > ; # [doc = "Field `MINOR` reader - 5:0\\]
Minor revision"]
pub type MinorR = crate :: FieldReader ; # [doc = "Field `MINOR` writer - 5:0\\]
Minor revision"]
pub type MinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR` reader - 10:8\\]
Major revision"]
pub type MajorR = crate :: FieldReader ; # [doc = "Field `MAJOR` writer - 10:8\\]
Major revision"]
pub type MajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL` reader - 15:11\\]
RTL revision. Will vary depending on release."]
pub type RtlR = crate :: FieldReader ; # [doc = "Field `RTL` writer - 15:11\\]
RTL revision. Will vary depending on release."]
pub type RtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `MODULE_ID` reader - 27:16\\]
Module ID"]
pub type ModuleIdR = crate :: FieldReader < u16 > ; # [doc = "Field `MODULE_ID` writer - 27:16\\]
Module ID"]
pub type ModuleIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `BU` reader - 29:28\\]
Business Unit: 10 = Processors"]
pub type BuR = crate :: FieldReader ; # [doc = "Field `BU` writer - 29:28\\]
Business Unit: 10 = Processors"]
pub type BuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
PID register scheme"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
PID register scheme"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor revision"]
# [inline (always)]
pub fn minor (& self) -> MinorR { MinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major revision"]
# [inline (always)]
pub fn major (& self) -> MajorR { MajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL revision. Will vary depending on release."]
# [inline (always)]
pub fn rtl (& self) -> RtlR { RtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Module ID"]
# [inline (always)]
pub fn module_id (& self) -> ModuleIdR { ModuleIdR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
Business Unit: 10 = Processors"]
# [inline (always)]
pub fn bu (& self) -> BuR { BuR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
PID register scheme"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor revision"]
# [inline (always)]
# [must_use]
pub fn minor (& mut self) -> MinorW < SsPidSpec > { MinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < SsPidSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major revision"]
# [inline (always)]
# [must_use]
pub fn major (& mut self) -> MajorW < SsPidSpec > { MajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL revision. Will vary depending on release."]
# [inline (always)]
# [must_use]
pub fn rtl (& mut self) -> RtlW < SsPidSpec > { RtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Module ID"]
# [inline (always)]
# [must_use]
pub fn module_id (& mut self) -> ModuleIdW < SsPidSpec > { ModuleIdW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
Business Unit: 10 = Processors"]
# [inline (always)]
# [must_use]
pub fn bu (& mut self) -> BuW < SsPidSpec > { BuW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
PID register scheme"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < SsPidSpec > { SchemeW :: new (self , 30) } } # [doc = "SS_PID\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsPidSpec ; impl crate :: RegisterSpec for SsPidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_pid::R`](R) reader structure"]
impl crate :: Readable for SsPidSpec { } # [doc = "`write(|w| ..)` method takes [`ss_pid::W`](W) writer structure"]
impl crate :: Writable for SsPidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_PID to value 0"]
impl crate :: Resettable for SsPidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_CTRL (rw) register accessor: SS_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_ctrl`]
module"]
# [doc (alias = "SS_CTRL")]
pub type SsCtrl = crate :: Reg < ss_ctrl :: SsCtrlSpec > ; # [doc = "SS_CTRL"]
pub mod ss_ctrl { # [doc = "Register `SS_CTRL` reader"]
pub type R = crate :: R < SsCtrlSpec > ; # [doc = "Register `SS_CTRL` writer"]
pub type W = crate :: W < SsCtrlSpec > ; # [doc = "Field `NU` reader - 2:0\\]
Reserved"]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - 2:0\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `DBGSUSP_FREE` reader - 3:3\\]
0-Honor Debug Suspend, 1-Disregard debug suspend"]
pub type DbgsuspFreeR = crate :: BitReader ; # [doc = "Field `DBGSUSP_FREE` writer - 3:3\\]
0-Honor Debug Suspend, 1-Disregard debug suspend"]
pub type DbgsuspFreeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKEUPREGEN` reader - 4:4\\]
Wakeup Request Enable"]
pub type WakeupregenR = crate :: BitReader ; # [doc = "Field `WAKEUPREGEN` writer - 4:4\\]
Wakeup Request Enable"]
pub type WakeupregenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AUTOWAKEUP` reader - 5:5\\]
Automatic Wakeup Enable"]
pub type AutowakeupR = crate :: BitReader ; # [doc = "Field `AUTOWAKEUP` writer - 5:5\\]
Automatic Wakeup Enable"]
pub type AutowakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EXT_TS_CNTR_EN` reader - 6:6\\]
External TimeStamp Counter Enable"]
pub type ExtTsCntrEnR = crate :: BitReader ; # [doc = "Field `EXT_TS_CNTR_EN` writer - 6:6\\]
External TimeStamp Counter Enable"]
pub type ExtTsCntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU0` reader - 31:7\\]
Reserved"]
pub type Nu0R = crate :: FieldReader < u32 > ; # [doc = "Field `NU0` writer - 31:7\\]
Reserved"]
pub type Nu0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
0-Honor Debug Suspend, 1-Disregard debug suspend"]
# [inline (always)]
pub fn dbgsusp_free (& self) -> DbgsuspFreeR { DbgsuspFreeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Wakeup Request Enable"]
# [inline (always)]
pub fn wakeupregen (& self) -> WakeupregenR { WakeupregenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Automatic Wakeup Enable"]
# [inline (always)]
pub fn autowakeup (& self) -> AutowakeupR { AutowakeupR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
External TimeStamp Counter Enable"]
# [inline (always)]
pub fn ext_ts_cntr_en (& self) -> ExtTsCntrEnR { ExtTsCntrEnR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Reserved"]
# [inline (always)]
pub fn nu0 (& self) -> Nu0R { Nu0R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < SsCtrlSpec > { NuW :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
0-Honor Debug Suspend, 1-Disregard debug suspend"]
# [inline (always)]
# [must_use]
pub fn dbgsusp_free (& mut self) -> DbgsuspFreeW < SsCtrlSpec > { DbgsuspFreeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Wakeup Request Enable"]
# [inline (always)]
# [must_use]
pub fn wakeupregen (& mut self) -> WakeupregenW < SsCtrlSpec > { WakeupregenW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Automatic Wakeup Enable"]
# [inline (always)]
# [must_use]
pub fn autowakeup (& mut self) -> AutowakeupW < SsCtrlSpec > { AutowakeupW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
External TimeStamp Counter Enable"]
# [inline (always)]
# [must_use]
pub fn ext_ts_cntr_en (& mut self) -> ExtTsCntrEnW < SsCtrlSpec > { ExtTsCntrEnW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu0 (& mut self) -> Nu0W < SsCtrlSpec > { Nu0W :: new (self , 7) } } # [doc = "SS_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsCtrlSpec ; impl crate :: RegisterSpec for SsCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_ctrl::R`](R) reader structure"]
impl crate :: Readable for SsCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`ss_ctrl::W`](W) writer structure"]
impl crate :: Writable for SsCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_CTRL to value 0"]
impl crate :: Resettable for SsCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_STAT (rw) register accessor: SS_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_stat`]
module"]
# [doc (alias = "SS_STAT")]
pub type SsStat = crate :: Reg < ss_stat :: SsStatSpec > ; # [doc = "SS_STAT"]
pub mod ss_stat { # [doc = "Register `SS_STAT` reader"]
pub type R = crate :: R < SsStatSpec > ; # [doc = "Register `SS_STAT` writer"]
pub type W = crate :: W < SsStatSpec > ; # [doc = "Field `NU` reader - 0:0\\]
Reserved"]
pub type NuR = crate :: BitReader ; # [doc = "Field `NU` writer - 0:0\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMI_DONE` reader - 1:1\\]
0:Memory Initialization is in progress, 1:Memory Intialization Done"]
pub type MmiDoneR = crate :: BitReader ; # [doc = "Field `MMI_DONE` writer - 1:1\\]
0:Memory Initialization is in progress, 1:Memory Intialization Done"]
pub type MmiDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EN_FDOE` reader - 2:2\\]
Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe"]
pub type EnFdoeR = crate :: BitReader ; # [doc = "Field `EN_FDOE` writer - 2:2\\]
Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe"]
pub type EnFdoeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 31:3\\]
Reserved"]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - 31:3\\]
Reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 29 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
0:Memory Initialization is in progress, 1:Memory Intialization Done"]
# [inline (always)]
pub fn mmi_done (& self) -> MmiDoneR { MmiDoneR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe"]
# [inline (always)]
pub fn en_fdoe (& self) -> EnFdoeR { EnFdoeR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:31 - 31:3\\]
Reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 3) & 0x1fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < SsStatSpec > { NuW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
0:Memory Initialization is in progress, 1:Memory Intialization Done"]
# [inline (always)]
# [must_use]
pub fn mmi_done (& mut self) -> MmiDoneW < SsStatSpec > { MmiDoneW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe"]
# [inline (always)]
# [must_use]
pub fn en_fdoe (& mut self) -> EnFdoeW < SsStatSpec > { EnFdoeW :: new (self , 2) } # [doc = "Bits 3:31 - 31:3\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < SsStatSpec > { Nu1W :: new (self , 3) } } # [doc = "SS_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsStatSpec ; impl crate :: RegisterSpec for SsStatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_stat::R`](R) reader structure"]
impl crate :: Readable for SsStatSpec { } # [doc = "`write(|w| ..)` method takes [`ss_stat::W`](W) writer structure"]
impl crate :: Writable for SsStatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_STAT to value 0"]
impl crate :: Resettable for SsStatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_ICS (rw) register accessor: SS_ICS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ics::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ics::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_ics`]
module"]
# [doc (alias = "SS_ICS")]
pub type SsIcs = crate :: Reg < ss_ics :: SsIcsSpec > ; # [doc = "SS_ICS"]
pub mod ss_ics { # [doc = "Register `SS_ICS` reader"]
pub type R = crate :: R < SsIcsSpec > ; # [doc = "Register `SS_ICS` writer"]
pub type W = crate :: W < SsIcsSpec > ; # [doc = "Field `ICS` reader - 0:0\\]
This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)"]
pub type IcsR = crate :: BitReader ; # [doc = "Field `ICS` writer - 0:0\\]
This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)"]
pub type IcsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 31:1\\]
Reserved"]
pub type Nu2R = crate :: FieldReader < u32 > ; # [doc = "Field `NU2` writer - 31:1\\]
Reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)"]
# [inline (always)]
pub fn ics (& self) -> IcsR { IcsR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)"]
# [inline (always)]
# [must_use]
pub fn ics (& mut self) -> IcsW < SsIcsSpec > { IcsW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < SsIcsSpec > { Nu2W :: new (self , 1) } } # [doc = "SS_ICS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ics::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ics::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsIcsSpec ; impl crate :: RegisterSpec for SsIcsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_ics::R`](R) reader structure"]
impl crate :: Readable for SsIcsSpec { } # [doc = "`write(|w| ..)` method takes [`ss_ics::W`](W) writer structure"]
impl crate :: Writable for SsIcsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_ICS to value 0"]
impl crate :: Resettable for SsIcsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_IRS (rw) register accessor: SS_IRS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_irs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_irs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_irs`]
module"]
# [doc (alias = "SS_IRS")]
pub type SsIrs = crate :: Reg < ss_irs :: SsIrsSpec > ; # [doc = "SS_IRS"]
pub mod ss_irs { # [doc = "Register `SS_IRS` reader"]
pub type R = crate :: R < SsIrsSpec > ; # [doc = "Register `SS_IRS` writer"]
pub type W = crate :: W < SsIrsSpec > ; # [doc = "Field `IRS` reader - 0:0\\]
External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)"]
pub type IrsR = crate :: BitReader ; # [doc = "Field `IRS` writer - 0:0\\]
External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)"]
pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU3` reader - 31:1\\]
Reserved"]
pub type Nu3R = crate :: FieldReader < u32 > ; # [doc = "Field `NU3` writer - 31:1\\]
Reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)"]
# [inline (always)]
pub fn irs (& self) -> IrsR { IrsR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)"]
# [inline (always)]
# [must_use]
pub fn irs (& mut self) -> IrsW < SsIrsSpec > { IrsW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < SsIrsSpec > { Nu3W :: new (self , 1) } } # [doc = "SS_IRS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_irs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_irs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsIrsSpec ; impl crate :: RegisterSpec for SsIrsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_irs::R`](R) reader structure"]
impl crate :: Readable for SsIrsSpec { } # [doc = "`write(|w| ..)` method takes [`ss_irs::W`](W) writer structure"]
impl crate :: Writable for SsIrsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_IRS to value 0"]
impl crate :: Resettable for SsIrsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_IECS (rw) register accessor: SS_IECS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_iecs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_iecs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_iecs`]
module"]
# [doc (alias = "SS_IECS")]
pub type SsIecs = crate :: Reg < ss_iecs :: SsIecsSpec > ; # [doc = "SS_IECS"]
pub mod ss_iecs { # [doc = "Register `SS_IECS` reader"]
pub type R = crate :: R < SsIecsSpec > ; # [doc = "Register `SS_IECS` writer"]
pub type W = crate :: W < SsIecsSpec > ; # [doc = "Field `IECS` reader - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)"]
pub type IecsR = crate :: BitReader ; # [doc = "Field `IECS` writer - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)"]
pub type IecsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU4` reader - 31:1\\]
Reserved"]
pub type Nu4R = crate :: FieldReader < u32 > ; # [doc = "Field `NU4` writer - 31:1\\]
Reserved"]
pub type Nu4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)"]
# [inline (always)]
pub fn iecs (& self) -> IecsR { IecsR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)"]
# [inline (always)]
# [must_use]
pub fn iecs (& mut self) -> IecsW < SsIecsSpec > { IecsW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < SsIecsSpec > { Nu4W :: new (self , 1) } } # [doc = "SS_IECS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_iecs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_iecs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsIecsSpec ; impl crate :: RegisterSpec for SsIecsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_iecs::R`](R) reader structure"]
impl crate :: Readable for SsIecsSpec { } # [doc = "`write(|w| ..)` method takes [`ss_iecs::W`](W) writer structure"]
impl crate :: Writable for SsIecsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_IECS to value 0"]
impl crate :: Resettable for SsIecsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_IE (rw) register accessor: SS_IE\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_ie`]
module"]
# [doc (alias = "SS_IE")]
pub type SsIe = crate :: Reg < ss_ie :: SsIeSpec > ; # [doc = "SS_IE"]
pub mod ss_ie { # [doc = "Register `SS_IE` reader"]
pub type R = crate :: R < SsIeSpec > ; # [doc = "Register `SS_IE` writer"]
pub type W = crate :: W < SsIeSpec > ; # [doc = "Field `IE` reader - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)"]
pub type IeR = crate :: BitReader ; # [doc = "Field `IE` writer - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)"]
pub type IeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU5` reader - 31:1\\]
Reserved"]
pub type Nu5R = crate :: FieldReader < u32 > ; # [doc = "Field `NU5` writer - 31:1\\]
Reserved"]
pub type Nu5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)"]
# [inline (always)]
pub fn ie (& self) -> IeR { IeR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu5 (& self) -> Nu5R { Nu5R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)"]
# [inline (always)]
# [must_use]
pub fn ie (& mut self) -> IeW < SsIeSpec > { IeW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu5 (& mut self) -> Nu5W < SsIeSpec > { Nu5W :: new (self , 1) } } # [doc = "SS_IE\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsIeSpec ; impl crate :: RegisterSpec for SsIeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_ie::R`](R) reader structure"]
impl crate :: Readable for SsIeSpec { } # [doc = "`write(|w| ..)` method takes [`ss_ie::W`](W) writer structure"]
impl crate :: Writable for SsIeSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_IE to value 0"]
impl crate :: Resettable for SsIeSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_IES (rw) register accessor: SS_IES\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ies::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ies::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_ies`]
module"]
# [doc (alias = "SS_IES")]
pub type SsIes = crate :: Reg < ss_ies :: SsIesSpec > ; # [doc = "SS_IES"]
pub mod ss_ies { # [doc = "Register `SS_IES` reader"]
pub type R = crate :: R < SsIesSpec > ; # [doc = "Register `SS_IES` writer"]
pub type W = crate :: W < SsIesSpec > ; # [doc = "Field `IES` reader - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)"]
pub type IesR = crate :: BitReader ; # [doc = "Field `IES` writer - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)"]
pub type IesW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU6` reader - 31:1\\]
Reserved"]
pub type Nu6R = crate :: FieldReader < u32 > ; # [doc = "Field `NU6` writer - 31:1\\]
Reserved"]
pub type Nu6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)"]
# [inline (always)]
pub fn ies (& self) -> IesR { IesR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu6 (& self) -> Nu6R { Nu6R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)"]
# [inline (always)]
# [must_use]
pub fn ies (& mut self) -> IesW < SsIesSpec > { IesW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu6 (& mut self) -> Nu6W < SsIesSpec > { Nu6W :: new (self , 1) } } # [doc = "SS_IES\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ies::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ies::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsIesSpec ; impl crate :: RegisterSpec for SsIesSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_ies::R`](R) reader structure"]
impl crate :: Readable for SsIesSpec { } # [doc = "`write(|w| ..)` method takes [`ss_ies::W`](W) writer structure"]
impl crate :: Writable for SsIesSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_IES to value 0"]
impl crate :: Resettable for SsIesSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_EOI (rw) register accessor: SS_EOI\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_eoi`]
module"]
# [doc (alias = "SS_EOI")]
pub type SsEoi = crate :: Reg < ss_eoi :: SsEoiSpec > ; # [doc = "SS_EOI"]
pub mod ss_eoi { # [doc = "Register `SS_EOI` reader"]
pub type R = crate :: R < SsEoiSpec > ; # [doc = "Register `SS_EOI` writer"]
pub type W = crate :: W < SsEoiSpec > ; # [doc = "Field `EOI` reader - 7:0\\]
Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt mcan_0_eoi(1): EOI value for mcan\\[0\\]
interrupt mcan_1_eoi(2): EOI value for mcan\\[1\\]
interrupt (EOI - End Of Interrupt)"]
pub type EoiR = crate :: FieldReader ; # [doc = "Field `EOI` writer - 7:0\\]
Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt mcan_0_eoi(1): EOI value for mcan\\[0\\]
interrupt mcan_1_eoi(2): EOI value for mcan\\[1\\]
interrupt (EOI - End Of Interrupt)"]
pub type EoiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU7` reader - 31:8\\]
Reserved"]
pub type Nu7R = crate :: FieldReader < u32 > ; # [doc = "Field `NU7` writer - 31:8\\]
Reserved"]
pub type Nu7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt mcan_0_eoi(1): EOI value for mcan\\[0\\]
interrupt mcan_1_eoi(2): EOI value for mcan\\[1\\]
interrupt (EOI - End Of Interrupt)"]
# [inline (always)]
pub fn eoi (& self) -> EoiR { EoiR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu7 (& self) -> Nu7R { Nu7R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt mcan_0_eoi(1): EOI value for mcan\\[0\\]
interrupt mcan_1_eoi(2): EOI value for mcan\\[1\\]
interrupt (EOI - End Of Interrupt)"]
# [inline (always)]
# [must_use]
pub fn eoi (& mut self) -> EoiW < SsEoiSpec > { EoiW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu7 (& mut self) -> Nu7W < SsEoiSpec > { Nu7W :: new (self , 8) } } # [doc = "SS_EOI\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsEoiSpec ; impl crate :: RegisterSpec for SsEoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_eoi::R`](R) reader structure"]
impl crate :: Readable for SsEoiSpec { } # [doc = "`write(|w| ..)` method takes [`ss_eoi::W`](W) writer structure"]
impl crate :: Writable for SsEoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_EOI to value 0"]
impl crate :: Resettable for SsEoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_EXT_TS_PS (rw) register accessor: SS_EXT_TS_PS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ext_ts_ps::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ext_ts_ps::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_ext_ts_ps`]
module"]
# [doc (alias = "SS_EXT_TS_PS")]
pub type SsExtTsPs = crate :: Reg < ss_ext_ts_ps :: SsExtTsPsSpec > ; # [doc = "SS_EXT_TS_PS"]
pub mod ss_ext_ts_ps { # [doc = "Register `SS_EXT_TS_PS` reader"]
pub type R = crate :: R < SsExtTsPsSpec > ; # [doc = "Register `SS_EXT_TS_PS` writer"]
pub type W = crate :: W < SsExtTsPsSpec > ; # [doc = "Field `PRESCALE` reader - 23:0\\]
External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 ."]
pub type PrescaleR = crate :: FieldReader < u32 > ; # [doc = "Field `PRESCALE` writer - 23:0\\]
External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 ."]
pub type PrescaleW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU8` reader - 31:24\\]
Reserved"]
pub type Nu8R = crate :: FieldReader ; # [doc = "Field `NU8` writer - 31:24\\]
Reserved"]
pub type Nu8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 ."]
# [inline (always)]
pub fn prescale (& self) -> PrescaleR { PrescaleR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn nu8 (& self) -> Nu8R { Nu8R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 ."]
# [inline (always)]
# [must_use]
pub fn prescale (& mut self) -> PrescaleW < SsExtTsPsSpec > { PrescaleW :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu8 (& mut self) -> Nu8W < SsExtTsPsSpec > { Nu8W :: new (self , 24) } } # [doc = "SS_EXT_TS_PS\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ext_ts_ps::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ext_ts_ps::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsExtTsPsSpec ; impl crate :: RegisterSpec for SsExtTsPsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_ext_ts_ps::R`](R) reader structure"]
impl crate :: Readable for SsExtTsPsSpec { } # [doc = "`write(|w| ..)` method takes [`ss_ext_ts_ps::W`](W) writer structure"]
impl crate :: Writable for SsExtTsPsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_EXT_TS_PS to value 0"]
impl crate :: Resettable for SsExtTsPsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SS_EXT_TS_USIC (rw) register accessor: SS_EXT_TS_USIC\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ext_ts_usic::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ext_ts_usic::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_ext_ts_usic`]
module"]
# [doc (alias = "SS_EXT_TS_USIC")]
pub type SsExtTsUsic = crate :: Reg < ss_ext_ts_usic :: SsExtTsUsicSpec > ; # [doc = "SS_EXT_TS_USIC"]
pub mod ss_ext_ts_usic { # [doc = "Register `SS_EXT_TS_USIC` reader"]
pub type R = crate :: R < SsExtTsUsicSpec > ; # [doc = "Register `SS_EXT_TS_USIC` writer"]
pub type W = crate :: W < SsExtTsUsicSpec > ; # [doc = "Field `EXT_TS_INTR_CNTR` reader - 4:0\\]
Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)"]
pub type ExtTsIntrCntrR = crate :: FieldReader ; # [doc = "Field `EXT_TS_INTR_CNTR` writer - 4:0\\]
Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)"]
pub type ExtTsIntrCntrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU9` reader - 31:5\\]
Reserved"]
pub type Nu9R = crate :: FieldReader < u32 > ; # [doc = "Field `NU9` writer - 31:5\\]
Reserved"]
pub type Nu9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 27 , u32 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)"]
# [inline (always)]
pub fn ext_ts_intr_cntr (& self) -> ExtTsIntrCntrR { ExtTsIntrCntrR :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:31 - 31:5\\]
Reserved"]
# [inline (always)]
pub fn nu9 (& self) -> Nu9R { Nu9R :: new ((self . bits >> 5) & 0x07ff_ffff) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)"]
# [inline (always)]
# [must_use]
pub fn ext_ts_intr_cntr (& mut self) -> ExtTsIntrCntrW < SsExtTsUsicSpec > { ExtTsIntrCntrW :: new (self , 0) } # [doc = "Bits 5:31 - 31:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu9 (& mut self) -> Nu9W < SsExtTsUsicSpec > { Nu9W :: new (self , 5) } } # [doc = "SS_EXT_TS_USIC\n\nYou can [`read`](crate::Reg::read) this register and get [`ss_ext_ts_usic::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ss_ext_ts_usic::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SsExtTsUsicSpec ; impl crate :: RegisterSpec for SsExtTsUsicSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ss_ext_ts_usic::R`](R) reader structure"]
impl crate :: Readable for SsExtTsUsicSpec { } # [doc = "`write(|w| ..)` method takes [`ss_ext_ts_usic::W`](W) writer structure"]
impl crate :: Writable for SsExtTsUsicSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SS_EXT_TS_USIC to value 0"]
impl crate :: Resettable for SsExtTsUsicSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CREL (rw) register accessor: CREL\n\nYou can [`read`](crate::Reg::read) this register and get [`crel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crel`]
module"]
# [doc (alias = "CREL")]
pub type Crel = crate :: Reg < crel :: CrelSpec > ; # [doc = "CREL"]
pub mod crel { # [doc = "Register `CREL` reader"]
pub type R = crate :: R < CrelSpec > ; # [doc = "Register `CREL` writer"]
pub type W = crate :: W < CrelSpec > ; # [doc = "Field `DAY` reader - 7:0\\]
Time Stamp Day"]
pub type DayR = crate :: FieldReader ; # [doc = "Field `DAY` writer - 7:0\\]
Time Stamp Day"]
pub type DayW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `MON` reader - 15:8\\]
Time Stamp Month"]
pub type MonR = crate :: FieldReader ; # [doc = "Field `MON` writer - 15:8\\]
Time Stamp Month"]
pub type MonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `YEAR` reader - 19:16\\]
Time Stamp Year"]
pub type YearR = crate :: FieldReader ; # [doc = "Field `YEAR` writer - 19:16\\]
Time Stamp Year"]
pub type YearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `SUBSTEP` reader - 23:20\\]
Sub-Step of Core Release"]
pub type SubstepR = crate :: FieldReader ; # [doc = "Field `SUBSTEP` writer - 23:20\\]
Sub-Step of Core Release"]
pub type SubstepW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STEP` reader - 27:24\\]
Step of Core Release"]
pub type StepR = crate :: FieldReader ; # [doc = "Field `STEP` writer - 27:24\\]
Step of Core Release"]
pub type StepW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `REL` reader - 31:28\\]
Core Release"]
pub type RelR = crate :: FieldReader ; # [doc = "Field `REL` writer - 31:28\\]
Core Release"]
pub type RelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Time Stamp Day"]
# [inline (always)]
pub fn day (& self) -> DayR { DayR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Time Stamp Month"]
# [inline (always)]
pub fn mon (& self) -> MonR { MonR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:19 - 19:16\\]
Time Stamp Year"]
# [inline (always)]
pub fn year (& self) -> YearR { YearR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - 23:20\\]
Sub-Step of Core Release"]
# [inline (always)]
pub fn substep (& self) -> SubstepR { SubstepR :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - 27:24\\]
Step of Core Release"]
# [inline (always)]
pub fn step (& self) -> StepR { StepR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:31 - 31:28\\]
Core Release"]
# [inline (always)]
pub fn rel (& self) -> RelR { RelR :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Time Stamp Day"]
# [inline (always)]
# [must_use]
pub fn day (& mut self) -> DayW < CrelSpec > { DayW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Time Stamp Month"]
# [inline (always)]
# [must_use]
pub fn mon (& mut self) -> MonW < CrelSpec > { MonW :: new (self , 8) } # [doc = "Bits 16:19 - 19:16\\]
Time Stamp Year"]
# [inline (always)]
# [must_use]
pub fn year (& mut self) -> YearW < CrelSpec > { YearW :: new (self , 16) } # [doc = "Bits 20:23 - 23:20\\]
Sub-Step of Core Release"]
# [inline (always)]
# [must_use]
pub fn substep (& mut self) -> SubstepW < CrelSpec > { SubstepW :: new (self , 20) } # [doc = "Bits 24:27 - 27:24\\]
Step of Core Release"]
# [inline (always)]
# [must_use]
pub fn step (& mut self) -> StepW < CrelSpec > { StepW :: new (self , 24) } # [doc = "Bits 28:31 - 31:28\\]
Core Release"]
# [inline (always)]
# [must_use]
pub fn rel (& mut self) -> RelW < CrelSpec > { RelW :: new (self , 28) } } # [doc = "CREL\n\nYou can [`read`](crate::Reg::read) this register and get [`crel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrelSpec ; impl crate :: RegisterSpec for CrelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`crel::R`](R) reader structure"]
impl crate :: Readable for CrelSpec { } # [doc = "`write(|w| ..)` method takes [`crel::W`](W) writer structure"]
impl crate :: Writable for CrelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CREL to value 0"]
impl crate :: Resettable for CrelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ENDN (rw) register accessor: ENDN\n\nYou can [`read`](crate::Reg::read) this register and get [`endn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endn`]
module"]
# [doc (alias = "ENDN")]
pub type Endn = crate :: Reg < endn :: EndnSpec > ; # [doc = "ENDN"]
pub mod endn { # [doc = "Register `ENDN` reader"]
pub type R = crate :: R < EndnSpec > ; # [doc = "Register `ENDN` writer"]
pub type W = crate :: W < EndnSpec > ; # [doc = "Field `ETV` reader - 31:0\\]
Endianess test value"]
pub type EtvR = crate :: FieldReader < u32 > ; # [doc = "Field `ETV` writer - 31:0\\]
Endianess test value"]
pub type EtvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Endianess test value"]
# [inline (always)]
pub fn etv (& self) -> EtvR { EtvR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Endianess test value"]
# [inline (always)]
# [must_use]
pub fn etv (& mut self) -> EtvW < EndnSpec > { EtvW :: new (self , 0) } } # [doc = "ENDN\n\nYou can [`read`](crate::Reg::read) this register and get [`endn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndnSpec ; impl crate :: RegisterSpec for EndnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`endn::R`](R) reader structure"]
impl crate :: Readable for EndnSpec { } # [doc = "`write(|w| ..)` method takes [`endn::W`](W) writer structure"]
impl crate :: Writable for EndnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ENDN to value 0"]
impl crate :: Resettable for EndnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CUST (rw) register accessor: CUST\n\nYou can [`read`](crate::Reg::read) this register and get [`cust::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cust::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cust`]
module"]
# [doc (alias = "CUST")]
pub type Cust = crate :: Reg < cust :: CustSpec > ; # [doc = "CUST"]
pub mod cust { # [doc = "Register `CUST` reader"]
pub type R = crate :: R < CustSpec > ; # [doc = "Register `CUST` writer"]
pub type W = crate :: W < CustSpec > ; # [doc = "Field `CUST` reader - 31:0\\]
Custom"]
pub type CustR = crate :: FieldReader < u32 > ; # [doc = "Field `CUST` writer - 31:0\\]
Custom"]
pub type CustW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Custom"]
# [inline (always)]
pub fn cust (& self) -> CustR { CustR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Custom"]
# [inline (always)]
# [must_use]
pub fn cust (& mut self) -> CustW < CustSpec > { CustW :: new (self , 0) } } # [doc = "CUST\n\nYou can [`read`](crate::Reg::read) this register and get [`cust::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cust::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CustSpec ; impl crate :: RegisterSpec for CustSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cust::R`](R) reader structure"]
impl crate :: Readable for CustSpec { } # [doc = "`write(|w| ..)` method takes [`cust::W`](W) writer structure"]
impl crate :: Writable for CustSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CUST to value 0"]
impl crate :: Resettable for CustSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DBTP (rw) register accessor: DBTP\n\nYou can [`read`](crate::Reg::read) this register and get [`dbtp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbtp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbtp`]
module"]
# [doc (alias = "DBTP")]
pub type Dbtp = crate :: Reg < dbtp :: DbtpSpec > ; # [doc = "DBTP"]
pub mod dbtp { # [doc = "Register `DBTP` reader"]
pub type R = crate :: R < DbtpSpec > ; # [doc = "Register `DBTP` writer"]
pub type W = crate :: W < DbtpSpec > ; # [doc = "Field `DSJW` reader - 3:0\\]
Data resynchronization Jump Width"]
pub type DsjwR = crate :: FieldReader ; # [doc = "Field `DSJW` writer - 3:0\\]
Data resynchronization Jump Width"]
pub type DsjwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DTSEG2` reader - 7:4\\]
Data time segment after sample point"]
pub type Dtseg2R = crate :: FieldReader ; # [doc = "Field `DTSEG2` writer - 7:4\\]
Data time segment after sample point"]
pub type Dtseg2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DTSEG1` reader - 12:8\\]
Data time segment before smaple point"]
pub type Dtseg1R = crate :: FieldReader ; # [doc = "Field `DTSEG1` writer - 12:8\\]
Data time segment before smaple point"]
pub type Dtseg1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU11` reader - 15:13\\]
Reserved"]
pub type Nu11R = crate :: FieldReader ; # [doc = "Field `NU11` writer - 15:13\\]
Reserved"]
pub type Nu11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `DBRP` reader - 20:16\\]
Data Baud Rate Prescaler"]
pub type DbrpR = crate :: FieldReader ; # [doc = "Field `DBRP` writer - 20:16\\]
Data Baud Rate Prescaler"]
pub type DbrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU12` reader - 22:21\\]
Reserved"]
pub type Nu12R = crate :: FieldReader ; # [doc = "Field `NU12` writer - 22:21\\]
Reserved"]
pub type Nu12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TDC` reader - 23:23\\]
Transmitter Delay Compensation"]
pub type TdcR = crate :: BitReader ; # [doc = "Field `TDC` writer - 23:23\\]
Transmitter Delay Compensation"]
pub type TdcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU13` reader - 31:24\\]
Reserved"]
pub type Nu13R = crate :: FieldReader ; # [doc = "Field `NU13` writer - 31:24\\]
Reserved"]
pub type Nu13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Data resynchronization Jump Width"]
# [inline (always)]
pub fn dsjw (& self) -> DsjwR { DsjwR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
Data time segment after sample point"]
# [inline (always)]
pub fn dtseg2 (& self) -> Dtseg2R { Dtseg2R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Data time segment before smaple point"]
# [inline (always)]
pub fn dtseg1 (& self) -> Dtseg1R { Dtseg1R :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved"]
# [inline (always)]
pub fn nu11 (& self) -> Nu11R { Nu11R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
Data Baud Rate Prescaler"]
# [inline (always)]
pub fn dbrp (& self) -> DbrpR { DbrpR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:22 - 22:21\\]
Reserved"]
# [inline (always)]
pub fn nu12 (& self) -> Nu12R { Nu12R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Transmitter Delay Compensation"]
# [inline (always)]
pub fn tdc (& self) -> TdcR { TdcR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn nu13 (& self) -> Nu13R { Nu13R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Data resynchronization Jump Width"]
# [inline (always)]
# [must_use]
pub fn dsjw (& mut self) -> DsjwW < DbtpSpec > { DsjwW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
Data time segment after sample point"]
# [inline (always)]
# [must_use]
pub fn dtseg2 (& mut self) -> Dtseg2W < DbtpSpec > { Dtseg2W :: new (self , 4) } # [doc = "Bits 8:12 - 12:8\\]
Data time segment before smaple point"]
# [inline (always)]
# [must_use]
pub fn dtseg1 (& mut self) -> Dtseg1W < DbtpSpec > { Dtseg1W :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu11 (& mut self) -> Nu11W < DbtpSpec > { Nu11W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
Data Baud Rate Prescaler"]
# [inline (always)]
# [must_use]
pub fn dbrp (& mut self) -> DbrpW < DbtpSpec > { DbrpW :: new (self , 16) } # [doc = "Bits 21:22 - 22:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu12 (& mut self) -> Nu12W < DbtpSpec > { Nu12W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Transmitter Delay Compensation"]
# [inline (always)]
# [must_use]
pub fn tdc (& mut self) -> TdcW < DbtpSpec > { TdcW :: new (self , 23) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu13 (& mut self) -> Nu13W < DbtpSpec > { Nu13W :: new (self , 24) } } # [doc = "DBTP\n\nYou can [`read`](crate::Reg::read) this register and get [`dbtp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbtp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbtpSpec ; impl crate :: RegisterSpec for DbtpSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dbtp::R`](R) reader structure"]
impl crate :: Readable for DbtpSpec { } # [doc = "`write(|w| ..)` method takes [`dbtp::W`](W) writer structure"]
impl crate :: Writable for DbtpSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DBTP to value 0"]
impl crate :: Resettable for DbtpSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TEST (rw) register accessor: TEST\n\nYou can [`read`](crate::Reg::read) this register and get [`test::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`test::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@test`]
module"]
# [doc (alias = "TEST")]
pub type Test = crate :: Reg < test :: TestSpec > ; # [doc = "TEST"]
pub mod test { # [doc = "Register `TEST` reader"]
pub type R = crate :: R < TestSpec > ; # [doc = "Register `TEST` writer"]
pub type W = crate :: W < TestSpec > ; # [doc = "Field `NU14` reader - 3:0\\]
Reserved"]
pub type Nu14R = crate :: FieldReader ; # [doc = "Field `NU14` writer - 3:0\\]
Reserved"]
pub type Nu14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `LBCK` reader - 4:4\\]
Loop Back Mode"]
pub type LbckR = crate :: BitReader ; # [doc = "Field `LBCK` writer - 4:4\\]
Loop Back Mode"]
pub type LbckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX` reader - 6:5\\]
Control of Transmit Pin"]
pub type TxR = crate :: FieldReader ; # [doc = "Field `TX` writer - 6:5\\]
Control of Transmit Pin"]
pub type TxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RX` reader - 7:7\\]
Receive Pin"]
pub type RxR = crate :: BitReader ; # [doc = "Field `RX` writer - 7:7\\]
Receive Pin"]
pub type RxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU15` reader - 31:8\\]
Reserved"]
pub type Nu15R = crate :: FieldReader < u32 > ; # [doc = "Field `NU15` writer - 31:8\\]
Reserved"]
pub type Nu15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Reserved"]
# [inline (always)]
pub fn nu14 (& self) -> Nu14R { Nu14R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Loop Back Mode"]
# [inline (always)]
pub fn lbck (& self) -> LbckR { LbckR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:6 - 6:5\\]
Control of Transmit Pin"]
# [inline (always)]
pub fn tx (& self) -> TxR { TxR :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - 7:7\\]
Receive Pin"]
# [inline (always)]
pub fn rx (& self) -> RxR { RxR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu15 (& self) -> Nu15R { Nu15R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu14 (& mut self) -> Nu14W < TestSpec > { Nu14W :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Loop Back Mode"]
# [inline (always)]
# [must_use]
pub fn lbck (& mut self) -> LbckW < TestSpec > { LbckW :: new (self , 4) } # [doc = "Bits 5:6 - 6:5\\]
Control of Transmit Pin"]
# [inline (always)]
# [must_use]
pub fn tx (& mut self) -> TxW < TestSpec > { TxW :: new (self , 5) } # [doc = "Bit 7 - 7:7\\]
Receive Pin"]
# [inline (always)]
# [must_use]
pub fn rx (& mut self) -> RxW < TestSpec > { RxW :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu15 (& mut self) -> Nu15W < TestSpec > { Nu15W :: new (self , 8) } } # [doc = "TEST\n\nYou can [`read`](crate::Reg::read) this register and get [`test::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`test::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TestSpec ; impl crate :: RegisterSpec for TestSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`test::R`](R) reader structure"]
impl crate :: Readable for TestSpec { } # [doc = "`write(|w| ..)` method takes [`test::W`](W) writer structure"]
impl crate :: Writable for TestSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TEST to value 0"]
impl crate :: Resettable for TestSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RWD (rw) register accessor: RWD\n\nYou can [`read`](crate::Reg::read) this register and get [`rwd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rwd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwd`]
module"]
# [doc (alias = "RWD")]
pub type Rwd = crate :: Reg < rwd :: RwdSpec > ; # [doc = "RWD"]
pub mod rwd { # [doc = "Register `RWD` reader"]
pub type R = crate :: R < RwdSpec > ; # [doc = "Register `RWD` writer"]
pub type W = crate :: W < RwdSpec > ; # [doc = "Field `WDC` reader - 7:0\\]
Watchdog Counter Value"]
pub type WdcR = crate :: FieldReader ; # [doc = "Field `WDC` writer - 7:0\\]
Watchdog Counter Value"]
pub type WdcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `WDV` reader - 15:8\\]
Watchdog Value"]
pub type WdvR = crate :: FieldReader ; # [doc = "Field `WDV` writer - 15:8\\]
Watchdog Value"]
pub type WdvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU16` reader - 31:16\\]
Reserved"]
pub type Nu16R = crate :: FieldReader < u16 > ; # [doc = "Field `NU16` writer - 31:16\\]
Reserved"]
pub type Nu16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Watchdog Counter Value"]
# [inline (always)]
pub fn wdc (& self) -> WdcR { WdcR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Watchdog Value"]
# [inline (always)]
pub fn wdv (& self) -> WdvR { WdvR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu16 (& self) -> Nu16R { Nu16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Watchdog Counter Value"]
# [inline (always)]
# [must_use]
pub fn wdc (& mut self) -> WdcW < RwdSpec > { WdcW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Watchdog Value"]
# [inline (always)]
# [must_use]
pub fn wdv (& mut self) -> WdvW < RwdSpec > { WdvW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu16 (& mut self) -> Nu16W < RwdSpec > { Nu16W :: new (self , 16) } } # [doc = "RWD\n\nYou can [`read`](crate::Reg::read) this register and get [`rwd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rwd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwdSpec ; impl crate :: RegisterSpec for RwdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rwd::R`](R) reader structure"]
impl crate :: Readable for RwdSpec { } # [doc = "`write(|w| ..)` method takes [`rwd::W`](W) writer structure"]
impl crate :: Writable for RwdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RWD to value 0"]
impl crate :: Resettable for RwdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCCR (rw) register accessor: CCCR\n\nYou can [`read`](crate::Reg::read) this register and get [`cccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cccr`]
module"]
# [doc (alias = "CCCR")]
pub type Cccr = crate :: Reg < cccr :: CccrSpec > ; # [doc = "CCCR"]
pub mod cccr { # [doc = "Register `CCCR` reader"]
pub type R = crate :: R < CccrSpec > ; # [doc = "Register `CCCR` writer"]
pub type W = crate :: W < CccrSpec > ; # [doc = "Field `INIT` reader - 0:0\\]
Initialization"]
pub type InitR = crate :: BitReader ; # [doc = "Field `INIT` writer - 0:0\\]
Initialization"]
pub type InitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CCE` reader - 1:1\\]
Configuration Change Enable"]
pub type CceR = crate :: BitReader ; # [doc = "Field `CCE` writer - 1:1\\]
Configuration Change Enable"]
pub type CceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ASM` reader - 2:2\\]
Restriced Operation Mode"]
pub type AsmR = crate :: BitReader ; # [doc = "Field `ASM` writer - 2:2\\]
Restriced Operation Mode"]
pub type AsmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSA` reader - 3:3\\]
Clock Stop Acknowledge"]
pub type CsaR = crate :: BitReader ; # [doc = "Field `CSA` writer - 3:3\\]
Clock Stop Acknowledge"]
pub type CsaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSR` reader - 4:4\\]
Clock Stop Request"]
pub type CsrR = crate :: BitReader ; # [doc = "Field `CSR` writer - 4:4\\]
Clock Stop Request"]
pub type CsrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MON` reader - 5:5\\]
Bus Monitoring Mode"]
pub type MonR = crate :: BitReader ; # [doc = "Field `MON` writer - 5:5\\]
Bus Monitoring Mode"]
pub type MonW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DAR` reader - 6:6\\]
Disable Automatic Regransmission"]
pub type DarR = crate :: BitReader ; # [doc = "Field `DAR` writer - 6:6\\]
Disable Automatic Regransmission"]
pub type DarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEST` reader - 7:7\\]
Test Mode enable"]
pub type TestR = crate :: BitReader ; # [doc = "Field `TEST` writer - 7:7\\]
Test Mode enable"]
pub type TestW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FDOE` reader - 8:8\\]
FD Operation Enable"]
pub type FdoeR = crate :: BitReader ; # [doc = "Field `FDOE` writer - 8:8\\]
FD Operation Enable"]
pub type FdoeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BRSE` reader - 9:9\\]
Bit Rate Switch Enable"]
pub type BrseR = crate :: BitReader ; # [doc = "Field `BRSE` writer - 9:9\\]
Bit Rate Switch Enable"]
pub type BrseW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU17` reader - 11:10\\]
Reserved"]
pub type Nu17R = crate :: FieldReader ; # [doc = "Field `NU17` writer - 11:10\\]
Reserved"]
pub type Nu17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PXHD` reader - 12:12\\]
Protocol Exception Handling Disable"]
pub type PxhdR = crate :: BitReader ; # [doc = "Field `PXHD` writer - 12:12\\]
Protocol Exception Handling Disable"]
pub type PxhdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EFBI` reader - 13:13\\]
Edge Filtering durign Bus Integration"]
pub type EfbiR = crate :: BitReader ; # [doc = "Field `EFBI` writer - 13:13\\]
Edge Filtering durign Bus Integration"]
pub type EfbiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXP` reader - 14:14\\]
Transmit Pause"]
pub type TxpR = crate :: BitReader ; # [doc = "Field `TXP` writer - 14:14\\]
Transmit Pause"]
pub type TxpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU18` reader - 31:15\\]
Reserved"]
pub type Nu18R = crate :: FieldReader < u32 > ; # [doc = "Field `NU18` writer - 31:15\\]
Reserved"]
pub type Nu18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 17 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Initialization"]
# [inline (always)]
pub fn init (& self) -> InitR { InitR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Configuration Change Enable"]
# [inline (always)]
pub fn cce (& self) -> CceR { CceR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Restriced Operation Mode"]
# [inline (always)]
pub fn asm (& self) -> AsmR { AsmR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Clock Stop Acknowledge"]
# [inline (always)]
pub fn csa (& self) -> CsaR { CsaR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Clock Stop Request"]
# [inline (always)]
pub fn csr (& self) -> CsrR { CsrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Bus Monitoring Mode"]
# [inline (always)]
pub fn mon (& self) -> MonR { MonR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Disable Automatic Regransmission"]
# [inline (always)]
pub fn dar (& self) -> DarR { DarR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Test Mode enable"]
# [inline (always)]
pub fn test (& self) -> TestR { TestR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
FD Operation Enable"]
# [inline (always)]
pub fn fdoe (& self) -> FdoeR { FdoeR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Bit Rate Switch Enable"]
# [inline (always)]
pub fn brse (& self) -> BrseR { BrseR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:11 - 11:10\\]
Reserved"]
# [inline (always)]
pub fn nu17 (& self) -> Nu17R { Nu17R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - 12:12\\]
Protocol Exception Handling Disable"]
# [inline (always)]
pub fn pxhd (& self) -> PxhdR { PxhdR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Edge Filtering durign Bus Integration"]
# [inline (always)]
pub fn efbi (& self) -> EfbiR { EfbiR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Transmit Pause"]
# [inline (always)]
pub fn txp (& self) -> TxpR { TxpR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:31 - 31:15\\]
Reserved"]
# [inline (always)]
pub fn nu18 (& self) -> Nu18R { Nu18R :: new ((self . bits >> 15) & 0x0001_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Initialization"]
# [inline (always)]
# [must_use]
pub fn init (& mut self) -> InitW < CccrSpec > { InitW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Configuration Change Enable"]
# [inline (always)]
# [must_use]
pub fn cce (& mut self) -> CceW < CccrSpec > { CceW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Restriced Operation Mode"]
# [inline (always)]
# [must_use]
pub fn asm (& mut self) -> AsmW < CccrSpec > { AsmW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Clock Stop Acknowledge"]
# [inline (always)]
# [must_use]
pub fn csa (& mut self) -> CsaW < CccrSpec > { CsaW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Clock Stop Request"]
# [inline (always)]
# [must_use]
pub fn csr (& mut self) -> CsrW < CccrSpec > { CsrW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Bus Monitoring Mode"]
# [inline (always)]
# [must_use]
pub fn mon (& mut self) -> MonW < CccrSpec > { MonW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Disable Automatic Regransmission"]
# [inline (always)]
# [must_use]
pub fn dar (& mut self) -> DarW < CccrSpec > { DarW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Test Mode enable"]
# [inline (always)]
# [must_use]
pub fn test (& mut self) -> TestW < CccrSpec > { TestW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
FD Operation Enable"]
# [inline (always)]
# [must_use]
pub fn fdoe (& mut self) -> FdoeW < CccrSpec > { FdoeW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Bit Rate Switch Enable"]
# [inline (always)]
# [must_use]
pub fn brse (& mut self) -> BrseW < CccrSpec > { BrseW :: new (self , 9) } # [doc = "Bits 10:11 - 11:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu17 (& mut self) -> Nu17W < CccrSpec > { Nu17W :: new (self , 10) } # [doc = "Bit 12 - 12:12\\]
Protocol Exception Handling Disable"]
# [inline (always)]
# [must_use]
pub fn pxhd (& mut self) -> PxhdW < CccrSpec > { PxhdW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Edge Filtering durign Bus Integration"]
# [inline (always)]
# [must_use]
pub fn efbi (& mut self) -> EfbiW < CccrSpec > { EfbiW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Transmit Pause"]
# [inline (always)]
# [must_use]
pub fn txp (& mut self) -> TxpW < CccrSpec > { TxpW :: new (self , 14) } # [doc = "Bits 15:31 - 31:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu18 (& mut self) -> Nu18W < CccrSpec > { Nu18W :: new (self , 15) } } # [doc = "CCCR\n\nYou can [`read`](crate::Reg::read) this register and get [`cccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CccrSpec ; impl crate :: RegisterSpec for CccrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cccr::R`](R) reader structure"]
impl crate :: Readable for CccrSpec { } # [doc = "`write(|w| ..)` method takes [`cccr::W`](W) writer structure"]
impl crate :: Writable for CccrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCCR to value 0"]
impl crate :: Resettable for CccrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "NBTP (rw) register accessor: NBTP\n\nYou can [`read`](crate::Reg::read) this register and get [`nbtp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nbtp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nbtp`]
module"]
# [doc (alias = "NBTP")]
pub type Nbtp = crate :: Reg < nbtp :: NbtpSpec > ; # [doc = "NBTP"]
pub mod nbtp { # [doc = "Register `NBTP` reader"]
pub type R = crate :: R < NbtpSpec > ; # [doc = "Register `NBTP` writer"]
pub type W = crate :: W < NbtpSpec > ; # [doc = "Field `NTSEG2` reader - 6:0\\]
Nominal Time segment after sample point"]
pub type Ntseg2R = crate :: FieldReader ; # [doc = "Field `NTSEG2` writer - 6:0\\]
Nominal Time segment after sample point"]
pub type Ntseg2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU19` reader - 7:7\\]
Reserved"]
pub type Nu19R = crate :: BitReader ; # [doc = "Field `NU19` writer - 7:7\\]
Reserved"]
pub type Nu19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NTSEG1` reader - 15:8\\]
Nominal Time segment before sample point"]
pub type Ntseg1R = crate :: FieldReader ; # [doc = "Field `NTSEG1` writer - 15:8\\]
Nominal Time segment before sample point"]
pub type Ntseg1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NBRP` reader - 24:16\\]
Nominal Baud Rate Prescaler"]
pub type NbrpR = crate :: FieldReader < u16 > ; # [doc = "Field `NBRP` writer - 24:16\\]
Nominal Baud Rate Prescaler"]
pub type NbrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `NSJW` reader - 31:25\\]
Nominal Resynchronization Jump Width"]
pub type NsjwR = crate :: FieldReader ; # [doc = "Field `NSJW` writer - 31:25\\]
Nominal Resynchronization Jump Width"]
pub type NsjwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:6 - 6:0\\]
Nominal Time segment after sample point"]
# [inline (always)]
pub fn ntseg2 (& self) -> Ntseg2R { Ntseg2R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
pub fn nu19 (& self) -> Nu19R { Nu19R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:15 - 15:8\\]
Nominal Time segment before sample point"]
# [inline (always)]
pub fn ntseg1 (& self) -> Ntseg1R { Ntseg1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:24 - 24:16\\]
Nominal Baud Rate Prescaler"]
# [inline (always)]
pub fn nbrp (& self) -> NbrpR { NbrpR :: new (((self . bits >> 16) & 0x01ff) as u16) } # [doc = "Bits 25:31 - 31:25\\]
Nominal Resynchronization Jump Width"]
# [inline (always)]
pub fn nsjw (& self) -> NsjwR { NsjwR :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - 6:0\\]
Nominal Time segment after sample point"]
# [inline (always)]
# [must_use]
pub fn ntseg2 (& mut self) -> Ntseg2W < NbtpSpec > { Ntseg2W :: new (self , 0) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu19 (& mut self) -> Nu19W < NbtpSpec > { Nu19W :: new (self , 7) } # [doc = "Bits 8:15 - 15:8\\]
Nominal Time segment before sample point"]
# [inline (always)]
# [must_use]
pub fn ntseg1 (& mut self) -> Ntseg1W < NbtpSpec > { Ntseg1W :: new (self , 8) } # [doc = "Bits 16:24 - 24:16\\]
Nominal Baud Rate Prescaler"]
# [inline (always)]
# [must_use]
pub fn nbrp (& mut self) -> NbrpW < NbtpSpec > { NbrpW :: new (self , 16) } # [doc = "Bits 25:31 - 31:25\\]
Nominal Resynchronization Jump Width"]
# [inline (always)]
# [must_use]
pub fn nsjw (& mut self) -> NsjwW < NbtpSpec > { NsjwW :: new (self , 25) } } # [doc = "NBTP\n\nYou can [`read`](crate::Reg::read) this register and get [`nbtp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nbtp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NbtpSpec ; impl crate :: RegisterSpec for NbtpSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`nbtp::R`](R) reader structure"]
impl crate :: Readable for NbtpSpec { } # [doc = "`write(|w| ..)` method takes [`nbtp::W`](W) writer structure"]
impl crate :: Writable for NbtpSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets NBTP to value 0"]
impl crate :: Resettable for NbtpSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TSCC (rw) register accessor: TSCC\n\nYou can [`read`](crate::Reg::read) this register and get [`tscc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tscc`]
module"]
# [doc (alias = "TSCC")]
pub type Tscc = crate :: Reg < tscc :: TsccSpec > ; # [doc = "TSCC"]
pub mod tscc { # [doc = "Register `TSCC` reader"]
pub type R = crate :: R < TsccSpec > ; # [doc = "Register `TSCC` writer"]
pub type W = crate :: W < TsccSpec > ; # [doc = "Field `TSS` reader - 1:0\\]
Timestamp Select"]
pub type TssR = crate :: FieldReader ; # [doc = "Field `TSS` writer - 1:0\\]
Timestamp Select"]
pub type TssW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU20` reader - 15:2\\]
Reserved"]
pub type Nu20R = crate :: FieldReader < u16 > ; # [doc = "Field `NU20` writer - 15:2\\]
Reserved"]
pub type Nu20W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `TCP` reader - 19:16\\]
Timestamp Counter Prescaler"]
pub type TcpR = crate :: FieldReader ; # [doc = "Field `TCP` writer - 19:16\\]
Timestamp Counter Prescaler"]
pub type TcpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU21` reader - 31:20\\]
Reserved"]
pub type Nu21R = crate :: FieldReader < u16 > ; # [doc = "Field `NU21` writer - 31:20\\]
Reserved"]
pub type Nu21W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Timestamp Select"]
# [inline (always)]
pub fn tss (& self) -> TssR { TssR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:15 - 15:2\\]
Reserved"]
# [inline (always)]
pub fn nu20 (& self) -> Nu20R { Nu20R :: new (((self . bits >> 2) & 0x3fff) as u16) } # [doc = "Bits 16:19 - 19:16\\]
Timestamp Counter Prescaler"]
# [inline (always)]
pub fn tcp (& self) -> TcpR { TcpR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn nu21 (& self) -> Nu21R { Nu21R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Timestamp Select"]
# [inline (always)]
# [must_use]
pub fn tss (& mut self) -> TssW < TsccSpec > { TssW :: new (self , 0) } # [doc = "Bits 2:15 - 15:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu20 (& mut self) -> Nu20W < TsccSpec > { Nu20W :: new (self , 2) } # [doc = "Bits 16:19 - 19:16\\]
Timestamp Counter Prescaler"]
# [inline (always)]
# [must_use]
pub fn tcp (& mut self) -> TcpW < TsccSpec > { TcpW :: new (self , 16) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu21 (& mut self) -> Nu21W < TsccSpec > { Nu21W :: new (self , 20) } } # [doc = "TSCC\n\nYou can [`read`](crate::Reg::read) this register and get [`tscc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TsccSpec ; impl crate :: RegisterSpec for TsccSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tscc::R`](R) reader structure"]
impl crate :: Readable for TsccSpec { } # [doc = "`write(|w| ..)` method takes [`tscc::W`](W) writer structure"]
impl crate :: Writable for TsccSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TSCC to value 0"]
impl crate :: Resettable for TsccSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TSCV (rw) register accessor: TSCV\n\nYou can [`read`](crate::Reg::read) this register and get [`tscv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tscv`]
module"]
# [doc (alias = "TSCV")]
pub type Tscv = crate :: Reg < tscv :: TscvSpec > ; # [doc = "TSCV"]
pub mod tscv { # [doc = "Register `TSCV` reader"]
pub type R = crate :: R < TscvSpec > ; # [doc = "Register `TSCV` writer"]
pub type W = crate :: W < TscvSpec > ; # [doc = "Field `TSC` reader - 15:0\\]
Timestamp Counter"]
pub type TscR = crate :: FieldReader < u16 > ; # [doc = "Field `TSC` writer - 15:0\\]
Timestamp Counter"]
pub type TscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU22` reader - 31:16\\]
Reserved"]
pub type Nu22R = crate :: FieldReader < u16 > ; # [doc = "Field `NU22` writer - 31:16\\]
Reserved"]
pub type Nu22W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Timestamp Counter"]
# [inline (always)]
pub fn tsc (& self) -> TscR { TscR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu22 (& self) -> Nu22R { Nu22R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Timestamp Counter"]
# [inline (always)]
# [must_use]
pub fn tsc (& mut self) -> TscW < TscvSpec > { TscW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu22 (& mut self) -> Nu22W < TscvSpec > { Nu22W :: new (self , 16) } } # [doc = "TSCV\n\nYou can [`read`](crate::Reg::read) this register and get [`tscv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TscvSpec ; impl crate :: RegisterSpec for TscvSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tscv::R`](R) reader structure"]
impl crate :: Readable for TscvSpec { } # [doc = "`write(|w| ..)` method takes [`tscv::W`](W) writer structure"]
impl crate :: Writable for TscvSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TSCV to value 0"]
impl crate :: Resettable for TscvSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TOCC (rw) register accessor: TOCC\n\nYou can [`read`](crate::Reg::read) this register and get [`tocc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tocc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tocc`]
module"]
# [doc (alias = "TOCC")]
pub type Tocc = crate :: Reg < tocc :: ToccSpec > ; # [doc = "TOCC"]
pub mod tocc { # [doc = "Register `TOCC` reader"]
pub type R = crate :: R < ToccSpec > ; # [doc = "Register `TOCC` writer"]
pub type W = crate :: W < ToccSpec > ; # [doc = "Field `ETOC` reader - 0:0\\]
Enable Timeout Counter"]
pub type EtocR = crate :: BitReader ; # [doc = "Field `ETOC` writer - 0:0\\]
Enable Timeout Counter"]
pub type EtocW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TOS` reader - 2:1\\]
Timeout Select"]
pub type TosR = crate :: FieldReader ; # [doc = "Field `TOS` writer - 2:1\\]
Timeout Select"]
pub type TosW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU23` reader - 15:3\\]
Reserved"]
pub type Nu23R = crate :: FieldReader < u16 > ; # [doc = "Field `NU23` writer - 15:3\\]
Reserved"]
pub type Nu23W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `TOP` reader - 31:16\\]
Timeout Period"]
pub type TopR = crate :: FieldReader < u16 > ; # [doc = "Field `TOP` writer - 31:16\\]
Timeout Period"]
pub type TopW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Enable Timeout Counter"]
# [inline (always)]
pub fn etoc (& self) -> EtocR { EtocR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:2 - 2:1\\]
Timeout Select"]
# [inline (always)]
pub fn tos (& self) -> TosR { TosR :: new (((self . bits >> 1) & 3) as u8) } # [doc = "Bits 3:15 - 15:3\\]
Reserved"]
# [inline (always)]
pub fn nu23 (& self) -> Nu23R { Nu23R :: new (((self . bits >> 3) & 0x1fff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Timeout Period"]
# [inline (always)]
pub fn top (& self) -> TopR { TopR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Enable Timeout Counter"]
# [inline (always)]
# [must_use]
pub fn etoc (& mut self) -> EtocW < ToccSpec > { EtocW :: new (self , 0) } # [doc = "Bits 1:2 - 2:1\\]
Timeout Select"]
# [inline (always)]
# [must_use]
pub fn tos (& mut self) -> TosW < ToccSpec > { TosW :: new (self , 1) } # [doc = "Bits 3:15 - 15:3\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu23 (& mut self) -> Nu23W < ToccSpec > { Nu23W :: new (self , 3) } # [doc = "Bits 16:31 - 31:16\\]
Timeout Period"]
# [inline (always)]
# [must_use]
pub fn top (& mut self) -> TopW < ToccSpec > { TopW :: new (self , 16) } } # [doc = "TOCC\n\nYou can [`read`](crate::Reg::read) this register and get [`tocc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tocc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ToccSpec ; impl crate :: RegisterSpec for ToccSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tocc::R`](R) reader structure"]
impl crate :: Readable for ToccSpec { } # [doc = "`write(|w| ..)` method takes [`tocc::W`](W) writer structure"]
impl crate :: Writable for ToccSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TOCC to value 0"]
impl crate :: Resettable for ToccSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TOCV (rw) register accessor: TOCV\n\nYou can [`read`](crate::Reg::read) this register and get [`tocv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tocv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tocv`]
module"]
# [doc (alias = "TOCV")]
pub type Tocv = crate :: Reg < tocv :: TocvSpec > ; # [doc = "TOCV"]
pub mod tocv { # [doc = "Register `TOCV` reader"]
pub type R = crate :: R < TocvSpec > ; # [doc = "Register `TOCV` writer"]
pub type W = crate :: W < TocvSpec > ; # [doc = "Field `TOC` reader - 15:0\\]
Timeout Counter"]
pub type TocR = crate :: FieldReader < u16 > ; # [doc = "Field `TOC` writer - 15:0\\]
Timeout Counter"]
pub type TocW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU24` reader - 31:16\\]
Reserved"]
pub type Nu24R = crate :: FieldReader < u16 > ; # [doc = "Field `NU24` writer - 31:16\\]
Reserved"]
pub type Nu24W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Timeout Counter"]
# [inline (always)]
pub fn toc (& self) -> TocR { TocR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu24 (& self) -> Nu24R { Nu24R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Timeout Counter"]
# [inline (always)]
# [must_use]
pub fn toc (& mut self) -> TocW < TocvSpec > { TocW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu24 (& mut self) -> Nu24W < TocvSpec > { Nu24W :: new (self , 16) } } # [doc = "TOCV\n\nYou can [`read`](crate::Reg::read) this register and get [`tocv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tocv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TocvSpec ; impl crate :: RegisterSpec for TocvSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tocv::R`](R) reader structure"]
impl crate :: Readable for TocvSpec { } # [doc = "`write(|w| ..)` method takes [`tocv::W`](W) writer structure"]
impl crate :: Writable for TocvSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TOCV to value 0"]
impl crate :: Resettable for TocvSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES00 (rw) register accessor: RES00\n\nYou can [`read`](crate::Reg::read) this register and get [`res00::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res00::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res00`]
module"]
# [doc (alias = "RES00")]
pub type Res00 = crate :: Reg < res00 :: Res00Spec > ; # [doc = "RES00"]
pub mod res00 { # [doc = "Register `RES00` reader"]
pub type R = crate :: R < Res00Spec > ; # [doc = "Register `RES00` writer"]
pub type W = crate :: W < Res00Spec > ; # [doc = "Field `RES00` reader - 31:0\\]
Reserved"]
pub type Res00R = crate :: FieldReader < u32 > ; # [doc = "Field `RES00` writer - 31:0\\]
Reserved"]
pub type Res00W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res00 (& self) -> Res00R { Res00R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res00 (& mut self) -> Res00W < Res00Spec > { Res00W :: new (self , 0) } } # [doc = "RES00\n\nYou can [`read`](crate::Reg::read) this register and get [`res00::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res00::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res00Spec ; impl crate :: RegisterSpec for Res00Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res00::R`](R) reader structure"]
impl crate :: Readable for Res00Spec { } # [doc = "`write(|w| ..)` method takes [`res00::W`](W) writer structure"]
impl crate :: Writable for Res00Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES00 to value 0"]
impl crate :: Resettable for Res00Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES01 (rw) register accessor: RES01\n\nYou can [`read`](crate::Reg::read) this register and get [`res01::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res01::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res01`]
module"]
# [doc (alias = "RES01")]
pub type Res01 = crate :: Reg < res01 :: Res01Spec > ; # [doc = "RES01"]
pub mod res01 { # [doc = "Register `RES01` reader"]
pub type R = crate :: R < Res01Spec > ; # [doc = "Register `RES01` writer"]
pub type W = crate :: W < Res01Spec > ; # [doc = "Field `RES01` reader - 31:0\\]
Reserved"]
pub type Res01R = crate :: FieldReader < u32 > ; # [doc = "Field `RES01` writer - 31:0\\]
Reserved"]
pub type Res01W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res01 (& self) -> Res01R { Res01R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res01 (& mut self) -> Res01W < Res01Spec > { Res01W :: new (self , 0) } } # [doc = "RES01\n\nYou can [`read`](crate::Reg::read) this register and get [`res01::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res01::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res01Spec ; impl crate :: RegisterSpec for Res01Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res01::R`](R) reader structure"]
impl crate :: Readable for Res01Spec { } # [doc = "`write(|w| ..)` method takes [`res01::W`](W) writer structure"]
impl crate :: Writable for Res01Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES01 to value 0"]
impl crate :: Resettable for Res01Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES02 (rw) register accessor: RES02\n\nYou can [`read`](crate::Reg::read) this register and get [`res02::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res02::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res02`]
module"]
# [doc (alias = "RES02")]
pub type Res02 = crate :: Reg < res02 :: Res02Spec > ; # [doc = "RES02"]
pub mod res02 { # [doc = "Register `RES02` reader"]
pub type R = crate :: R < Res02Spec > ; # [doc = "Register `RES02` writer"]
pub type W = crate :: W < Res02Spec > ; # [doc = "Field `RES02` reader - 31:0\\]
Reserved"]
pub type Res02R = crate :: FieldReader < u32 > ; # [doc = "Field `RES02` writer - 31:0\\]
Reserved"]
pub type Res02W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res02 (& self) -> Res02R { Res02R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res02 (& mut self) -> Res02W < Res02Spec > { Res02W :: new (self , 0) } } # [doc = "RES02\n\nYou can [`read`](crate::Reg::read) this register and get [`res02::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res02::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res02Spec ; impl crate :: RegisterSpec for Res02Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res02::R`](R) reader structure"]
impl crate :: Readable for Res02Spec { } # [doc = "`write(|w| ..)` method takes [`res02::W`](W) writer structure"]
impl crate :: Writable for Res02Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES02 to value 0"]
impl crate :: Resettable for Res02Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES03 (rw) register accessor: RES03\n\nYou can [`read`](crate::Reg::read) this register and get [`res03::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res03::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res03`]
module"]
# [doc (alias = "RES03")]
pub type Res03 = crate :: Reg < res03 :: Res03Spec > ; # [doc = "RES03"]
pub mod res03 { # [doc = "Register `RES03` reader"]
pub type R = crate :: R < Res03Spec > ; # [doc = "Register `RES03` writer"]
pub type W = crate :: W < Res03Spec > ; # [doc = "Field `RES03` reader - 31:0\\]
Reserved"]
pub type Res03R = crate :: FieldReader < u32 > ; # [doc = "Field `RES03` writer - 31:0\\]
Reserved"]
pub type Res03W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res03 (& self) -> Res03R { Res03R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res03 (& mut self) -> Res03W < Res03Spec > { Res03W :: new (self , 0) } } # [doc = "RES03\n\nYou can [`read`](crate::Reg::read) this register and get [`res03::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res03::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res03Spec ; impl crate :: RegisterSpec for Res03Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res03::R`](R) reader structure"]
impl crate :: Readable for Res03Spec { } # [doc = "`write(|w| ..)` method takes [`res03::W`](W) writer structure"]
impl crate :: Writable for Res03Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES03 to value 0"]
impl crate :: Resettable for Res03Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECR (rw) register accessor: ECR\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`]
module"]
# [doc (alias = "ECR")]
pub type Ecr = crate :: Reg < ecr :: EcrSpec > ; # [doc = "ECR"]
pub mod ecr { # [doc = "Register `ECR` reader"]
pub type R = crate :: R < EcrSpec > ; # [doc = "Register `ECR` writer"]
pub type W = crate :: W < EcrSpec > ; # [doc = "Field `TEC` reader - 7:0\\]
Transmit Error Counter"]
pub type TecR = crate :: FieldReader ; # [doc = "Field `TEC` writer - 7:0\\]
Transmit Error Counter"]
pub type TecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `REC` reader - 14:8\\]
Recieve Error Counter"]
pub type RecR = crate :: FieldReader ; # [doc = "Field `REC` writer - 14:8\\]
Recieve Error Counter"]
pub type RecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `RP` reader - 15:15\\]
Recieve Error Passive"]
pub type RpR = crate :: BitReader ; # [doc = "Field `RP` writer - 15:15\\]
Recieve Error Passive"]
pub type RpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CEL` reader - 23:16\\]
CAN Error Logging"]
pub type CelR = crate :: FieldReader ; # [doc = "Field `CEL` writer - 23:16\\]
CAN Error Logging"]
pub type CelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU25` reader - 31:24\\]
Reserved"]
pub type Nu25R = crate :: FieldReader ; # [doc = "Field `NU25` writer - 31:24\\]
Reserved"]
pub type Nu25W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Transmit Error Counter"]
# [inline (always)]
pub fn tec (& self) -> TecR { TecR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:14 - 14:8\\]
Recieve Error Counter"]
# [inline (always)]
pub fn rec (& self) -> RecR { RecR :: new (((self . bits >> 8) & 0x7f) as u8) } # [doc = "Bit 15 - 15:15\\]
Recieve Error Passive"]
# [inline (always)]
pub fn rp (& self) -> RpR { RpR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - 23:16\\]
CAN Error Logging"]
# [inline (always)]
pub fn cel (& self) -> CelR { CelR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn nu25 (& self) -> Nu25R { Nu25R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Transmit Error Counter"]
# [inline (always)]
# [must_use]
pub fn tec (& mut self) -> TecW < EcrSpec > { TecW :: new (self , 0) } # [doc = "Bits 8:14 - 14:8\\]
Recieve Error Counter"]
# [inline (always)]
# [must_use]
pub fn rec (& mut self) -> RecW < EcrSpec > { RecW :: new (self , 8) } # [doc = "Bit 15 - 15:15\\]
Recieve Error Passive"]
# [inline (always)]
# [must_use]
pub fn rp (& mut self) -> RpW < EcrSpec > { RpW :: new (self , 15) } # [doc = "Bits 16:23 - 23:16\\]
CAN Error Logging"]
# [inline (always)]
# [must_use]
pub fn cel (& mut self) -> CelW < EcrSpec > { CelW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu25 (& mut self) -> Nu25W < EcrSpec > { Nu25W :: new (self , 24) } } # [doc = "ECR\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrSpec ; impl crate :: RegisterSpec for EcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecr::R`](R) reader structure"]
impl crate :: Readable for EcrSpec { } # [doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"]
impl crate :: Writable for EcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECR to value 0"]
impl crate :: Resettable for EcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSR (rw) register accessor: PSR\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psr`]
module"]
# [doc (alias = "PSR")]
pub type Psr = crate :: Reg < psr :: PsrSpec > ; # [doc = "PSR"]
pub mod psr { # [doc = "Register `PSR` reader"]
pub type R = crate :: R < PsrSpec > ; # [doc = "Register `PSR` writer"]
pub type W = crate :: W < PsrSpec > ; # [doc = "Field `LEC` reader - 2:0\\]
Last Error Code"]
pub type LecR = crate :: FieldReader ; # [doc = "Field `LEC` writer - 2:0\\]
Last Error Code"]
pub type LecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ACT` reader - 4:3\\]
Activity"]
pub type ActR = crate :: FieldReader ; # [doc = "Field `ACT` writer - 4:3\\]
Activity"]
pub type ActW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EP` reader - 5:5\\]
Error Passive"]
pub type EpR = crate :: BitReader ; # [doc = "Field `EP` writer - 5:5\\]
Error Passive"]
pub type EpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EW` reader - 6:6\\]
Warning Status"]
pub type EwR = crate :: BitReader ; # [doc = "Field `EW` writer - 6:6\\]
Warning Status"]
pub type EwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BO` reader - 7:7\\]
Bus_Off status"]
pub type BoR = crate :: BitReader ; # [doc = "Field `BO` writer - 7:7\\]
Bus_Off status"]
pub type BoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DLEC` reader - 10:8\\]
Data Phase Last Error Code"]
pub type DlecR = crate :: FieldReader ; # [doc = "Field `DLEC` writer - 10:8\\]
Data Phase Last Error Code"]
pub type DlecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RESI` reader - 11:11\\]
ESI flag of last recieved CAN FD Message"]
pub type ResiR = crate :: BitReader ; # [doc = "Field `RESI` writer - 11:11\\]
ESI flag of last recieved CAN FD Message"]
pub type ResiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RBRS` reader - 12:12\\]
BRS flag of last recieved CAN FD Message"]
pub type RbrsR = crate :: BitReader ; # [doc = "Field `RBRS` writer - 12:12\\]
BRS flag of last recieved CAN FD Message"]
pub type RbrsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RFDF` reader - 13:13\\]
Recieved a CAN FD Message"]
pub type RfdfR = crate :: BitReader ; # [doc = "Field `RFDF` writer - 13:13\\]
Recieved a CAN FD Message"]
pub type RfdfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PXE` reader - 14:14\\]
Protocol Exception Event"]
pub type PxeR = crate :: BitReader ; # [doc = "Field `PXE` writer - 14:14\\]
Protocol Exception Event"]
pub type PxeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU26` reader - 15:15\\]
Reserved"]
pub type Nu26R = crate :: BitReader ; # [doc = "Field `NU26` writer - 15:15\\]
Reserved"]
pub type Nu26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TDCV` reader - 22:16\\]
Transmitter Delay Compensation Value"]
pub type TdcvR = crate :: FieldReader ; # [doc = "Field `TDCV` writer - 22:16\\]
Transmitter Delay Compensation Value"]
pub type TdcvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU27` reader - 31:23\\]
Reserved"]
pub type Nu27R = crate :: FieldReader < u16 > ; # [doc = "Field `NU27` writer - 31:23\\]
Reserved"]
pub type Nu27W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Last Error Code"]
# [inline (always)]
pub fn lec (& self) -> LecR { LecR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:4 - 4:3\\]
Activity"]
# [inline (always)]
pub fn act (& self) -> ActR { ActR :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bit 5 - 5:5\\]
Error Passive"]
# [inline (always)]
pub fn ep (& self) -> EpR { EpR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Warning Status"]
# [inline (always)]
pub fn ew (& self) -> EwR { EwR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Bus_Off status"]
# [inline (always)]
pub fn bo (& self) -> BoR { BoR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
Data Phase Last Error Code"]
# [inline (always)]
pub fn dlec (& self) -> DlecR { DlecR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
ESI flag of last recieved CAN FD Message"]
# [inline (always)]
pub fn resi (& self) -> ResiR { ResiR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
BRS flag of last recieved CAN FD Message"]
# [inline (always)]
pub fn rbrs (& self) -> RbrsR { RbrsR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Recieved a CAN FD Message"]
# [inline (always)]
pub fn rfdf (& self) -> RfdfR { RfdfR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Protocol Exception Event"]
# [inline (always)]
pub fn pxe (& self) -> PxeR { PxeR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
pub fn nu26 (& self) -> Nu26R { Nu26R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:22 - 22:16\\]
Transmitter Delay Compensation Value"]
# [inline (always)]
pub fn tdcv (& self) -> TdcvR { TdcvR :: new (((self . bits >> 16) & 0x7f) as u8) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
pub fn nu27 (& self) -> Nu27R { Nu27R :: new (((self . bits >> 23) & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Last Error Code"]
# [inline (always)]
# [must_use]
pub fn lec (& mut self) -> LecW < PsrSpec > { LecW :: new (self , 0) } # [doc = "Bits 3:4 - 4:3\\]
Activity"]
# [inline (always)]
# [must_use]
pub fn act (& mut self) -> ActW < PsrSpec > { ActW :: new (self , 3) } # [doc = "Bit 5 - 5:5\\]
Error Passive"]
# [inline (always)]
# [must_use]
pub fn ep (& mut self) -> EpW < PsrSpec > { EpW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Warning Status"]
# [inline (always)]
# [must_use]
pub fn ew (& mut self) -> EwW < PsrSpec > { EwW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Bus_Off status"]
# [inline (always)]
# [must_use]
pub fn bo (& mut self) -> BoW < PsrSpec > { BoW :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
Data Phase Last Error Code"]
# [inline (always)]
# [must_use]
pub fn dlec (& mut self) -> DlecW < PsrSpec > { DlecW :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
ESI flag of last recieved CAN FD Message"]
# [inline (always)]
# [must_use]
pub fn resi (& mut self) -> ResiW < PsrSpec > { ResiW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
BRS flag of last recieved CAN FD Message"]
# [inline (always)]
# [must_use]
pub fn rbrs (& mut self) -> RbrsW < PsrSpec > { RbrsW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Recieved a CAN FD Message"]
# [inline (always)]
# [must_use]
pub fn rfdf (& mut self) -> RfdfW < PsrSpec > { RfdfW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Protocol Exception Event"]
# [inline (always)]
# [must_use]
pub fn pxe (& mut self) -> PxeW < PsrSpec > { PxeW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu26 (& mut self) -> Nu26W < PsrSpec > { Nu26W :: new (self , 15) } # [doc = "Bits 16:22 - 22:16\\]
Transmitter Delay Compensation Value"]
# [inline (always)]
# [must_use]
pub fn tdcv (& mut self) -> TdcvW < PsrSpec > { TdcvW :: new (self , 16) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu27 (& mut self) -> Nu27W < PsrSpec > { Nu27W :: new (self , 23) } } # [doc = "PSR\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsrSpec ; impl crate :: RegisterSpec for PsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`psr::R`](R) reader structure"]
impl crate :: Readable for PsrSpec { } # [doc = "`write(|w| ..)` method takes [`psr::W`](W) writer structure"]
impl crate :: Writable for PsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSR to value 0"]
impl crate :: Resettable for PsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TDCR (rw) register accessor: TDCR\n\nYou can [`read`](crate::Reg::read) this register and get [`tdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdcr`]
module"]
# [doc (alias = "TDCR")]
pub type Tdcr = crate :: Reg < tdcr :: TdcrSpec > ; # [doc = "TDCR"]
pub mod tdcr { # [doc = "Register `TDCR` reader"]
pub type R = crate :: R < TdcrSpec > ; # [doc = "Register `TDCR` writer"]
pub type W = crate :: W < TdcrSpec > ; # [doc = "Field `TDCF` reader - 6:0\\]
Transmitter Delay Compensation Filter Window Length"]
pub type TdcfR = crate :: FieldReader ; # [doc = "Field `TDCF` writer - 6:0\\]
Transmitter Delay Compensation Filter Window Length"]
pub type TdcfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU28` reader - 7:7\\]
Reserved"]
pub type Nu28R = crate :: BitReader ; # [doc = "Field `NU28` writer - 7:7\\]
Reserved"]
pub type Nu28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TDCO` reader - 14:8\\]
Transmitter Delay Compensation Offset"]
pub type TdcoR = crate :: FieldReader ; # [doc = "Field `TDCO` writer - 14:8\\]
Transmitter Delay Compensation Offset"]
pub type TdcoW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU29` reader - 31:15\\]
Reserved"]
pub type Nu29R = crate :: FieldReader < u32 > ; # [doc = "Field `NU29` writer - 31:15\\]
Reserved"]
pub type Nu29W < 'a , REG > = crate :: FieldWriter < 'a , REG , 17 , u32 > ; impl R { # [doc = "Bits 0:6 - 6:0\\]
Transmitter Delay Compensation Filter Window Length"]
# [inline (always)]
pub fn tdcf (& self) -> TdcfR { TdcfR :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
pub fn nu28 (& self) -> Nu28R { Nu28R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:14 - 14:8\\]
Transmitter Delay Compensation Offset"]
# [inline (always)]
pub fn tdco (& self) -> TdcoR { TdcoR :: new (((self . bits >> 8) & 0x7f) as u8) } # [doc = "Bits 15:31 - 31:15\\]
Reserved"]
# [inline (always)]
pub fn nu29 (& self) -> Nu29R { Nu29R :: new ((self . bits >> 15) & 0x0001_ffff) } } impl W { # [doc = "Bits 0:6 - 6:0\\]
Transmitter Delay Compensation Filter Window Length"]
# [inline (always)]
# [must_use]
pub fn tdcf (& mut self) -> TdcfW < TdcrSpec > { TdcfW :: new (self , 0) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu28 (& mut self) -> Nu28W < TdcrSpec > { Nu28W :: new (self , 7) } # [doc = "Bits 8:14 - 14:8\\]
Transmitter Delay Compensation Offset"]
# [inline (always)]
# [must_use]
pub fn tdco (& mut self) -> TdcoW < TdcrSpec > { TdcoW :: new (self , 8) } # [doc = "Bits 15:31 - 31:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu29 (& mut self) -> Nu29W < TdcrSpec > { Nu29W :: new (self , 15) } } # [doc = "TDCR\n\nYou can [`read`](crate::Reg::read) this register and get [`tdcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TdcrSpec ; impl crate :: RegisterSpec for TdcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tdcr::R`](R) reader structure"]
impl crate :: Readable for TdcrSpec { } # [doc = "`write(|w| ..)` method takes [`tdcr::W`](W) writer structure"]
impl crate :: Writable for TdcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TDCR to value 0"]
impl crate :: Resettable for TdcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES04 (rw) register accessor: RES04\n\nYou can [`read`](crate::Reg::read) this register and get [`res04::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res04::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res04`]
module"]
# [doc (alias = "RES04")]
pub type Res04 = crate :: Reg < res04 :: Res04Spec > ; # [doc = "RES04"]
pub mod res04 { # [doc = "Register `RES04` reader"]
pub type R = crate :: R < Res04Spec > ; # [doc = "Register `RES04` writer"]
pub type W = crate :: W < Res04Spec > ; # [doc = "Field `RES04` reader - 31:0\\]
Reserved"]
pub type Res04R = crate :: FieldReader < u32 > ; # [doc = "Field `RES04` writer - 31:0\\]
Reserved"]
pub type Res04W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res04 (& self) -> Res04R { Res04R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res04 (& mut self) -> Res04W < Res04Spec > { Res04W :: new (self , 0) } } # [doc = "RES04\n\nYou can [`read`](crate::Reg::read) this register and get [`res04::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res04::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res04Spec ; impl crate :: RegisterSpec for Res04Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res04::R`](R) reader structure"]
impl crate :: Readable for Res04Spec { } # [doc = "`write(|w| ..)` method takes [`res04::W`](W) writer structure"]
impl crate :: Writable for Res04Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES04 to value 0"]
impl crate :: Resettable for Res04Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IR (rw) register accessor: IR\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
module"]
# [doc (alias = "IR")]
pub type Ir = crate :: Reg < ir :: IrSpec > ; # [doc = "IR"]
pub mod ir { # [doc = "Register `IR` reader"]
pub type R = crate :: R < IrSpec > ; # [doc = "Register `IR` writer"]
pub type W = crate :: W < IrSpec > ; # [doc = "Field `RF0N` reader - 0:0\\]
Rx FIFO 0 New Message"]
pub type Rf0nR = crate :: BitReader ; # [doc = "Field `RF0N` writer - 0:0\\]
Rx FIFO 0 New Message"]
pub type Rf0nW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0W` reader - 1:1\\]
Rx FIFO 0 Watermark Reached"]
pub type Rf0wR = crate :: BitReader ; # [doc = "Field `RF0W` writer - 1:1\\]
Rx FIFO 0 Watermark Reached"]
pub type Rf0wW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0F` reader - 2:2\\]
Rx FIFO 0 Full"]
pub type Rf0fR = crate :: BitReader ; # [doc = "Field `RF0F` writer - 2:2\\]
Rx FIFO 0 Full"]
pub type Rf0fW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0L` reader - 3:3\\]
Rx FIFO 0 Message Lost"]
pub type Rf0lR = crate :: BitReader ; # [doc = "Field `RF0L` writer - 3:3\\]
Rx FIFO 0 Message Lost"]
pub type Rf0lW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1N` reader - 4:4\\]
Rx FIFO 1 New Message"]
pub type Rf1nR = crate :: BitReader ; # [doc = "Field `RF1N` writer - 4:4\\]
Rx FIFO 1 New Message"]
pub type Rf1nW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1W` reader - 5:5\\]
Rx FIFO 1 Watermark Reached"]
pub type Rf1wR = crate :: BitReader ; # [doc = "Field `RF1W` writer - 5:5\\]
Rx FIFO 1 Watermark Reached"]
pub type Rf1wW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1F` reader - 6:6\\]
Rx FIFO 1 Full"]
pub type Rf1fR = crate :: BitReader ; # [doc = "Field `RF1F` writer - 6:6\\]
Rx FIFO 1 Full"]
pub type Rf1fW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1L` reader - 7:7\\]
Rx FIFO 1 Message Lost"]
pub type Rf1lR = crate :: BitReader ; # [doc = "Field `RF1L` writer - 7:7\\]
Rx FIFO 1 Message Lost"]
pub type Rf1lW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HPM` reader - 8:8\\]
High Priority Message"]
pub type HpmR = crate :: BitReader ; # [doc = "Field `HPM` writer - 8:8\\]
High Priority Message"]
pub type HpmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TC` reader - 9:9\\]
Transmission Complete"]
pub type TcR = crate :: BitReader ; # [doc = "Field `TC` writer - 9:9\\]
Transmission Complete"]
pub type TcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCF` reader - 10:10\\]
Transmission Cancellation Finished"]
pub type TcfR = crate :: BitReader ; # [doc = "Field `TCF` writer - 10:10\\]
Transmission Cancellation Finished"]
pub type TcfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TFE` reader - 11:11\\]
Tx FIFO Empty"]
pub type TfeR = crate :: BitReader ; # [doc = "Field `TFE` writer - 11:11\\]
Tx FIFO Empty"]
pub type TfeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFN` reader - 12:12\\]
Tx Event FIFO New Entry"]
pub type TefnR = crate :: BitReader ; # [doc = "Field `TEFN` writer - 12:12\\]
Tx Event FIFO New Entry"]
pub type TefnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFW` reader - 13:13\\]
Tx Event FIFO Watermark Reached"]
pub type TefwR = crate :: BitReader ; # [doc = "Field `TEFW` writer - 13:13\\]
Tx Event FIFO Watermark Reached"]
pub type TefwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFF` reader - 14:14\\]
Tx Event FIFO Full"]
pub type TeffR = crate :: BitReader ; # [doc = "Field `TEFF` writer - 14:14\\]
Tx Event FIFO Full"]
pub type TeffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFL` reader - 15:15\\]
Tx Event FIFO Element Lost"]
pub type TeflR = crate :: BitReader ; # [doc = "Field `TEFL` writer - 15:15\\]
Tx Event FIFO Element Lost"]
pub type TeflW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TSW` reader - 16:16\\]
Timestamp Wraparound"]
pub type TswR = crate :: BitReader ; # [doc = "Field `TSW` writer - 16:16\\]
Timestamp Wraparound"]
pub type TswW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MRAF` reader - 17:17\\]
Message RAM Access Failure"]
pub type MrafR = crate :: BitReader ; # [doc = "Field `MRAF` writer - 17:17\\]
Message RAM Access Failure"]
pub type MrafW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TOO` reader - 18:18\\]
Timeout Occurred"]
pub type TooR = crate :: BitReader ; # [doc = "Field `TOO` writer - 18:18\\]
Timeout Occurred"]
pub type TooW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DRX` reader - 19:19\\]
Message stored to Dedicated Rx Buffer"]
pub type DrxR = crate :: BitReader ; # [doc = "Field `DRX` writer - 19:19\\]
Message stored to Dedicated Rx Buffer"]
pub type DrxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BEC` reader - 20:20\\]
Bit Error Corrected"]
pub type BecR = crate :: BitReader ; # [doc = "Field `BEC` writer - 20:20\\]
Bit Error Corrected"]
pub type BecW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BEU` reader - 21:21\\]
Bit Error Uncorrected"]
pub type BeuR = crate :: BitReader ; # [doc = "Field `BEU` writer - 21:21\\]
Bit Error Uncorrected"]
pub type BeuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ELO` reader - 22:22\\]
Error Logging Overflow"]
pub type EloR = crate :: BitReader ; # [doc = "Field `ELO` writer - 22:22\\]
Error Logging Overflow"]
pub type EloW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP` reader - 23:23\\]
Error Passive"]
pub type EpR = crate :: BitReader ; # [doc = "Field `EP` writer - 23:23\\]
Error Passive"]
pub type EpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EW` reader - 24:24\\]
Warning Status"]
pub type EwR = crate :: BitReader ; # [doc = "Field `EW` writer - 24:24\\]
Warning Status"]
pub type EwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BO` reader - 25:25\\]
Bus_Off Status"]
pub type BoR = crate :: BitReader ; # [doc = "Field `BO` writer - 25:25\\]
Bus_Off Status"]
pub type BoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WDI` reader - 26:26\\]
Watchdog Interrupt"]
pub type WdiR = crate :: BitReader ; # [doc = "Field `WDI` writer - 26:26\\]
Watchdog Interrupt"]
pub type WdiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEA` reader - 27:27\\]
Protocol Error in Arbitration Phase"]
pub type PeaR = crate :: BitReader ; # [doc = "Field `PEA` writer - 27:27\\]
Protocol Error in Arbitration Phase"]
pub type PeaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PED` reader - 28:28\\]
Protocol Error in data Phase"]
pub type PedR = crate :: BitReader ; # [doc = "Field `PED` writer - 28:28\\]
Protocol Error in data Phase"]
pub type PedW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ARA` reader - 29:29\\]
Access to Reserved Address"]
pub type AraR = crate :: BitReader ; # [doc = "Field `ARA` writer - 29:29\\]
Access to Reserved Address"]
pub type AraW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU30` reader - 31:30\\]
Reserved"]
pub type Nu30R = crate :: FieldReader ; # [doc = "Field `NU30` writer - 31:30\\]
Reserved"]
pub type Nu30W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Rx FIFO 0 New Message"]
# [inline (always)]
pub fn rf0n (& self) -> Rf0nR { Rf0nR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Rx FIFO 0 Watermark Reached"]
# [inline (always)]
pub fn rf0w (& self) -> Rf0wR { Rf0wR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Rx FIFO 0 Full"]
# [inline (always)]
pub fn rf0f (& self) -> Rf0fR { Rf0fR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Rx FIFO 0 Message Lost"]
# [inline (always)]
pub fn rf0l (& self) -> Rf0lR { Rf0lR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Rx FIFO 1 New Message"]
# [inline (always)]
pub fn rf1n (& self) -> Rf1nR { Rf1nR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Rx FIFO 1 Watermark Reached"]
# [inline (always)]
pub fn rf1w (& self) -> Rf1wR { Rf1wR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Rx FIFO 1 Full"]
# [inline (always)]
pub fn rf1f (& self) -> Rf1fR { Rf1fR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Rx FIFO 1 Message Lost"]
# [inline (always)]
pub fn rf1l (& self) -> Rf1lR { Rf1lR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
High Priority Message"]
# [inline (always)]
pub fn hpm (& self) -> HpmR { HpmR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmission Complete"]
# [inline (always)]
pub fn tc (& self) -> TcR { TcR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Transmission Cancellation Finished"]
# [inline (always)]
pub fn tcf (& self) -> TcfR { TcfR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Tx FIFO Empty"]
# [inline (always)]
pub fn tfe (& self) -> TfeR { TfeR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Tx Event FIFO New Entry"]
# [inline (always)]
pub fn tefn (& self) -> TefnR { TefnR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Tx Event FIFO Watermark Reached"]
# [inline (always)]
pub fn tefw (& self) -> TefwR { TefwR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Tx Event FIFO Full"]
# [inline (always)]
pub fn teff (& self) -> TeffR { TeffR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Tx Event FIFO Element Lost"]
# [inline (always)]
pub fn tefl (& self) -> TeflR { TeflR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Timestamp Wraparound"]
# [inline (always)]
pub fn tsw (& self) -> TswR { TswR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Message RAM Access Failure"]
# [inline (always)]
pub fn mraf (& self) -> MrafR { MrafR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Timeout Occurred"]
# [inline (always)]
pub fn too (& self) -> TooR { TooR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Message stored to Dedicated Rx Buffer"]
# [inline (always)]
pub fn drx (& self) -> DrxR { DrxR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Bit Error Corrected"]
# [inline (always)]
pub fn bec (& self) -> BecR { BecR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Bit Error Uncorrected"]
# [inline (always)]
pub fn beu (& self) -> BeuR { BeuR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Error Logging Overflow"]
# [inline (always)]
pub fn elo (& self) -> EloR { EloR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Error Passive"]
# [inline (always)]
pub fn ep (& self) -> EpR { EpR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Warning Status"]
# [inline (always)]
pub fn ew (& self) -> EwR { EwR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Bus_Off Status"]
# [inline (always)]
pub fn bo (& self) -> BoR { BoR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Watchdog Interrupt"]
# [inline (always)]
pub fn wdi (& self) -> WdiR { WdiR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Protocol Error in Arbitration Phase"]
# [inline (always)]
pub fn pea (& self) -> PeaR { PeaR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Protocol Error in data Phase"]
# [inline (always)]
pub fn ped (& self) -> PedR { PedR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Access to Reserved Address"]
# [inline (always)]
pub fn ara (& self) -> AraR { AraR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
pub fn nu30 (& self) -> Nu30R { Nu30R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Rx FIFO 0 New Message"]
# [inline (always)]
# [must_use]
pub fn rf0n (& mut self) -> Rf0nW < IrSpec > { Rf0nW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Rx FIFO 0 Watermark Reached"]
# [inline (always)]
# [must_use]
pub fn rf0w (& mut self) -> Rf0wW < IrSpec > { Rf0wW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Rx FIFO 0 Full"]
# [inline (always)]
# [must_use]
pub fn rf0f (& mut self) -> Rf0fW < IrSpec > { Rf0fW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Rx FIFO 0 Message Lost"]
# [inline (always)]
# [must_use]
pub fn rf0l (& mut self) -> Rf0lW < IrSpec > { Rf0lW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Rx FIFO 1 New Message"]
# [inline (always)]
# [must_use]
pub fn rf1n (& mut self) -> Rf1nW < IrSpec > { Rf1nW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Rx FIFO 1 Watermark Reached"]
# [inline (always)]
# [must_use]
pub fn rf1w (& mut self) -> Rf1wW < IrSpec > { Rf1wW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Rx FIFO 1 Full"]
# [inline (always)]
# [must_use]
pub fn rf1f (& mut self) -> Rf1fW < IrSpec > { Rf1fW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Rx FIFO 1 Message Lost"]
# [inline (always)]
# [must_use]
pub fn rf1l (& mut self) -> Rf1lW < IrSpec > { Rf1lW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
High Priority Message"]
# [inline (always)]
# [must_use]
pub fn hpm (& mut self) -> HpmW < IrSpec > { HpmW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmission Complete"]
# [inline (always)]
# [must_use]
pub fn tc (& mut self) -> TcW < IrSpec > { TcW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Transmission Cancellation Finished"]
# [inline (always)]
# [must_use]
pub fn tcf (& mut self) -> TcfW < IrSpec > { TcfW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Tx FIFO Empty"]
# [inline (always)]
# [must_use]
pub fn tfe (& mut self) -> TfeW < IrSpec > { TfeW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Tx Event FIFO New Entry"]
# [inline (always)]
# [must_use]
pub fn tefn (& mut self) -> TefnW < IrSpec > { TefnW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Tx Event FIFO Watermark Reached"]
# [inline (always)]
# [must_use]
pub fn tefw (& mut self) -> TefwW < IrSpec > { TefwW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Tx Event FIFO Full"]
# [inline (always)]
# [must_use]
pub fn teff (& mut self) -> TeffW < IrSpec > { TeffW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Tx Event FIFO Element Lost"]
# [inline (always)]
# [must_use]
pub fn tefl (& mut self) -> TeflW < IrSpec > { TeflW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Timestamp Wraparound"]
# [inline (always)]
# [must_use]
pub fn tsw (& mut self) -> TswW < IrSpec > { TswW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Message RAM Access Failure"]
# [inline (always)]
# [must_use]
pub fn mraf (& mut self) -> MrafW < IrSpec > { MrafW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Timeout Occurred"]
# [inline (always)]
# [must_use]
pub fn too (& mut self) -> TooW < IrSpec > { TooW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Message stored to Dedicated Rx Buffer"]
# [inline (always)]
# [must_use]
pub fn drx (& mut self) -> DrxW < IrSpec > { DrxW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Bit Error Corrected"]
# [inline (always)]
# [must_use]
pub fn bec (& mut self) -> BecW < IrSpec > { BecW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Bit Error Uncorrected"]
# [inline (always)]
# [must_use]
pub fn beu (& mut self) -> BeuW < IrSpec > { BeuW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Error Logging Overflow"]
# [inline (always)]
# [must_use]
pub fn elo (& mut self) -> EloW < IrSpec > { EloW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Error Passive"]
# [inline (always)]
# [must_use]
pub fn ep (& mut self) -> EpW < IrSpec > { EpW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Warning Status"]
# [inline (always)]
# [must_use]
pub fn ew (& mut self) -> EwW < IrSpec > { EwW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Bus_Off Status"]
# [inline (always)]
# [must_use]
pub fn bo (& mut self) -> BoW < IrSpec > { BoW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Watchdog Interrupt"]
# [inline (always)]
# [must_use]
pub fn wdi (& mut self) -> WdiW < IrSpec > { WdiW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Protocol Error in Arbitration Phase"]
# [inline (always)]
# [must_use]
pub fn pea (& mut self) -> PeaW < IrSpec > { PeaW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Protocol Error in data Phase"]
# [inline (always)]
# [must_use]
pub fn ped (& mut self) -> PedW < IrSpec > { PedW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Access to Reserved Address"]
# [inline (always)]
# [must_use]
pub fn ara (& mut self) -> AraW < IrSpec > { AraW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu30 (& mut self) -> Nu30W < IrSpec > { Nu30W :: new (self , 30) } } # [doc = "IR\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrSpec ; impl crate :: RegisterSpec for IrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ir::R`](R) reader structure"]
impl crate :: Readable for IrSpec { } # [doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"]
impl crate :: Writable for IrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IR to value 0"]
impl crate :: Resettable for IrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IE (rw) register accessor: IE\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`]
module"]
# [doc (alias = "IE")]
pub type Ie = crate :: Reg < ie :: IeSpec > ; # [doc = "IE"]
pub mod ie { # [doc = "Register `IE` reader"]
pub type R = crate :: R < IeSpec > ; # [doc = "Register `IE` writer"]
pub type W = crate :: W < IeSpec > ; # [doc = "Field `RF0NE` reader - 0:0\\]
Rx FIFO 0 New Message Interrupt Enable"]
pub type Rf0neR = crate :: BitReader ; # [doc = "Field `RF0NE` writer - 0:0\\]
Rx FIFO 0 New Message Interrupt Enable"]
pub type Rf0neW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0WE` reader - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Enable"]
pub type Rf0weR = crate :: BitReader ; # [doc = "Field `RF0WE` writer - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Enable"]
pub type Rf0weW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0FE` reader - 2:2\\]
Rx FIFO 0 Full Interrupt Enable"]
pub type Rf0feR = crate :: BitReader ; # [doc = "Field `RF0FE` writer - 2:2\\]
Rx FIFO 0 Full Interrupt Enable"]
pub type Rf0feW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0LE` reader - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Enable"]
pub type Rf0leR = crate :: BitReader ; # [doc = "Field `RF0LE` writer - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Enable"]
pub type Rf0leW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1NE` reader - 4:4\\]
Rx FIFO 1 New Message Interrupt Enable"]
pub type Rf1neR = crate :: BitReader ; # [doc = "Field `RF1NE` writer - 4:4\\]
Rx FIFO 1 New Message Interrupt Enable"]
pub type Rf1neW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1WE` reader - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Enable"]
pub type Rf1weR = crate :: BitReader ; # [doc = "Field `RF1WE` writer - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Enable"]
pub type Rf1weW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1FE` reader - 6:6\\]
Rx FIFO 1 Full Interrupt Enable"]
pub type Rf1feR = crate :: BitReader ; # [doc = "Field `RF1FE` writer - 6:6\\]
Rx FIFO 1 Full Interrupt Enable"]
pub type Rf1feW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1LE` reader - 7:7\\]
rx FIFO 1 Message Lost Interrupt Enable"]
pub type Rf1leR = crate :: BitReader ; # [doc = "Field `RF1LE` writer - 7:7\\]
rx FIFO 1 Message Lost Interrupt Enable"]
pub type Rf1leW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HPME` reader - 8:8\\]
High Priority message Interrupt Enable"]
pub type HpmeR = crate :: BitReader ; # [doc = "Field `HPME` writer - 8:8\\]
High Priority message Interrupt Enable"]
pub type HpmeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCE` reader - 9:9\\]
Transmission Completed Interrupt Enable"]
pub type TceR = crate :: BitReader ; # [doc = "Field `TCE` writer - 9:9\\]
Transmission Completed Interrupt Enable"]
pub type TceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCFE` reader - 10:10\\]
Transmission Cancellation Finishied Interrupt Enable"]
pub type TcfeR = crate :: BitReader ; # [doc = "Field `TCFE` writer - 10:10\\]
Transmission Cancellation Finishied Interrupt Enable"]
pub type TcfeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TFEE` reader - 11:11\\]
Tx FIFO Empty Interrupt Enable"]
pub type TfeeR = crate :: BitReader ; # [doc = "Field `TFEE` writer - 11:11\\]
Tx FIFO Empty Interrupt Enable"]
pub type TfeeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFNE` reader - 12:12\\]
Tx Event FIFO New Entry Interrupt Enable"]
pub type TefneR = crate :: BitReader ; # [doc = "Field `TEFNE` writer - 12:12\\]
Tx Event FIFO New Entry Interrupt Enable"]
pub type TefneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFWE` reader - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt enable"]
pub type TefweR = crate :: BitReader ; # [doc = "Field `TEFWE` writer - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt enable"]
pub type TefweW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFFE` reader - 14:14\\]
Tx Event FIFO Full Interrupt Enable"]
pub type TeffeR = crate :: BitReader ; # [doc = "Field `TEFFE` writer - 14:14\\]
Tx Event FIFO Full Interrupt Enable"]
pub type TeffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFLE` reader - 15:15\\]
Tx Event FIFO Event Lost Interrupt Enable"]
pub type TefleR = crate :: BitReader ; # [doc = "Field `TEFLE` writer - 15:15\\]
Tx Event FIFO Event Lost Interrupt Enable"]
pub type TefleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TSWE` reader - 16:16\\]
Timestamp Wraparound Interrupt Enable"]
pub type TsweR = crate :: BitReader ; # [doc = "Field `TSWE` writer - 16:16\\]
Timestamp Wraparound Interrupt Enable"]
pub type TsweW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MRAFE` reader - 17:17\\]
Message RAM Access Failure Interrupt Enable"]
pub type MrafeR = crate :: BitReader ; # [doc = "Field `MRAFE` writer - 17:17\\]
Message RAM Access Failure Interrupt Enable"]
pub type MrafeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TOOE` reader - 18:18\\]
Timeout Occurred Interrupt Enable"]
pub type TooeR = crate :: BitReader ; # [doc = "Field `TOOE` writer - 18:18\\]
Timeout Occurred Interrupt Enable"]
pub type TooeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DRX` reader - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Enable"]
pub type DrxR = crate :: BitReader ; # [doc = "Field `DRX` writer - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Enable"]
pub type DrxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BECE` reader - 20:20\\]
Bit Error Corrected Interrupt Enable"]
pub type BeceR = crate :: BitReader ; # [doc = "Field `BECE` writer - 20:20\\]
Bit Error Corrected Interrupt Enable"]
pub type BeceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BEUE` reader - 21:21\\]
Bit Error Uncorrected Interrupt Enable"]
pub type BeueR = crate :: BitReader ; # [doc = "Field `BEUE` writer - 21:21\\]
Bit Error Uncorrected Interrupt Enable"]
pub type BeueW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ELOE` reader - 22:22\\]
Error Logging Overflow Interrupt Enable"]
pub type EloeR = crate :: BitReader ; # [doc = "Field `ELOE` writer - 22:22\\]
Error Logging Overflow Interrupt Enable"]
pub type EloeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EPE` reader - 23:23\\]
Error Passive Interrupt Enable"]
pub type EpeR = crate :: BitReader ; # [doc = "Field `EPE` writer - 23:23\\]
Error Passive Interrupt Enable"]
pub type EpeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EWE` reader - 24:24\\]
Warning Status Interrupt Enable"]
pub type EweR = crate :: BitReader ; # [doc = "Field `EWE` writer - 24:24\\]
Warning Status Interrupt Enable"]
pub type EweW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BOE` reader - 25:25\\]
Bus_Off Status Interrupt Enable"]
pub type BoeR = crate :: BitReader ; # [doc = "Field `BOE` writer - 25:25\\]
Bus_Off Status Interrupt Enable"]
pub type BoeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WDIE` reader - 26:26\\]
Watchdog Interrupt Enable"]
pub type WdieR = crate :: BitReader ; # [doc = "Field `WDIE` writer - 26:26\\]
Watchdog Interrupt Enable"]
pub type WdieW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEAE` reader - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Enable"]
pub type PeaeR = crate :: BitReader ; # [doc = "Field `PEAE` writer - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Enable"]
pub type PeaeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEDE` reader - 28:28\\]
Protocol Error in Data Phase Interrupt Enable"]
pub type PedeR = crate :: BitReader ; # [doc = "Field `PEDE` writer - 28:28\\]
Protocol Error in Data Phase Interrupt Enable"]
pub type PedeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ARAE` reader - 29:29\\]
Accees to Reserve Address Interrupt Enable"]
pub type AraeR = crate :: BitReader ; # [doc = "Field `ARAE` writer - 29:29\\]
Accees to Reserve Address Interrupt Enable"]
pub type AraeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU31` reader - 31:30\\]
Reserved"]
pub type Nu31R = crate :: FieldReader ; # [doc = "Field `NU31` writer - 31:30\\]
Reserved"]
pub type Nu31W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Rx FIFO 0 New Message Interrupt Enable"]
# [inline (always)]
pub fn rf0ne (& self) -> Rf0neR { Rf0neR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Enable"]
# [inline (always)]
pub fn rf0we (& self) -> Rf0weR { Rf0weR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Rx FIFO 0 Full Interrupt Enable"]
# [inline (always)]
pub fn rf0fe (& self) -> Rf0feR { Rf0feR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Enable"]
# [inline (always)]
pub fn rf0le (& self) -> Rf0leR { Rf0leR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Rx FIFO 1 New Message Interrupt Enable"]
# [inline (always)]
pub fn rf1ne (& self) -> Rf1neR { Rf1neR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Enable"]
# [inline (always)]
pub fn rf1we (& self) -> Rf1weR { Rf1weR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Rx FIFO 1 Full Interrupt Enable"]
# [inline (always)]
pub fn rf1fe (& self) -> Rf1feR { Rf1feR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
rx FIFO 1 Message Lost Interrupt Enable"]
# [inline (always)]
pub fn rf1le (& self) -> Rf1leR { Rf1leR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
High Priority message Interrupt Enable"]
# [inline (always)]
pub fn hpme (& self) -> HpmeR { HpmeR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmission Completed Interrupt Enable"]
# [inline (always)]
pub fn tce (& self) -> TceR { TceR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Transmission Cancellation Finishied Interrupt Enable"]
# [inline (always)]
pub fn tcfe (& self) -> TcfeR { TcfeR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Tx FIFO Empty Interrupt Enable"]
# [inline (always)]
pub fn tfee (& self) -> TfeeR { TfeeR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Tx Event FIFO New Entry Interrupt Enable"]
# [inline (always)]
pub fn tefne (& self) -> TefneR { TefneR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt enable"]
# [inline (always)]
pub fn tefwe (& self) -> TefweR { TefweR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Tx Event FIFO Full Interrupt Enable"]
# [inline (always)]
pub fn teffe (& self) -> TeffeR { TeffeR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Tx Event FIFO Event Lost Interrupt Enable"]
# [inline (always)]
pub fn tefle (& self) -> TefleR { TefleR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Timestamp Wraparound Interrupt Enable"]
# [inline (always)]
pub fn tswe (& self) -> TsweR { TsweR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Message RAM Access Failure Interrupt Enable"]
# [inline (always)]
pub fn mrafe (& self) -> MrafeR { MrafeR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Timeout Occurred Interrupt Enable"]
# [inline (always)]
pub fn tooe (& self) -> TooeR { TooeR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Enable"]
# [inline (always)]
pub fn drx (& self) -> DrxR { DrxR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Bit Error Corrected Interrupt Enable"]
# [inline (always)]
pub fn bece (& self) -> BeceR { BeceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Bit Error Uncorrected Interrupt Enable"]
# [inline (always)]
pub fn beue (& self) -> BeueR { BeueR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Error Logging Overflow Interrupt Enable"]
# [inline (always)]
pub fn eloe (& self) -> EloeR { EloeR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Error Passive Interrupt Enable"]
# [inline (always)]
pub fn epe (& self) -> EpeR { EpeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Warning Status Interrupt Enable"]
# [inline (always)]
pub fn ewe (& self) -> EweR { EweR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Bus_Off Status Interrupt Enable"]
# [inline (always)]
pub fn boe (& self) -> BoeR { BoeR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Watchdog Interrupt Enable"]
# [inline (always)]
pub fn wdie (& self) -> WdieR { WdieR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Enable"]
# [inline (always)]
pub fn peae (& self) -> PeaeR { PeaeR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Protocol Error in Data Phase Interrupt Enable"]
# [inline (always)]
pub fn pede (& self) -> PedeR { PedeR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Accees to Reserve Address Interrupt Enable"]
# [inline (always)]
pub fn arae (& self) -> AraeR { AraeR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
pub fn nu31 (& self) -> Nu31R { Nu31R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Rx FIFO 0 New Message Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf0ne (& mut self) -> Rf0neW < IeSpec > { Rf0neW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf0we (& mut self) -> Rf0weW < IeSpec > { Rf0weW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Rx FIFO 0 Full Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf0fe (& mut self) -> Rf0feW < IeSpec > { Rf0feW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf0le (& mut self) -> Rf0leW < IeSpec > { Rf0leW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Rx FIFO 1 New Message Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf1ne (& mut self) -> Rf1neW < IeSpec > { Rf1neW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf1we (& mut self) -> Rf1weW < IeSpec > { Rf1weW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Rx FIFO 1 Full Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf1fe (& mut self) -> Rf1feW < IeSpec > { Rf1feW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
rx FIFO 1 Message Lost Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn rf1le (& mut self) -> Rf1leW < IeSpec > { Rf1leW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
High Priority message Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn hpme (& mut self) -> HpmeW < IeSpec > { HpmeW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmission Completed Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tce (& mut self) -> TceW < IeSpec > { TceW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Transmission Cancellation Finishied Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tcfe (& mut self) -> TcfeW < IeSpec > { TcfeW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Tx FIFO Empty Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tfee (& mut self) -> TfeeW < IeSpec > { TfeeW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Tx Event FIFO New Entry Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tefne (& mut self) -> TefneW < IeSpec > { TefneW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tefwe (& mut self) -> TefweW < IeSpec > { TefweW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Tx Event FIFO Full Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn teffe (& mut self) -> TeffeW < IeSpec > { TeffeW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Tx Event FIFO Event Lost Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tefle (& mut self) -> TefleW < IeSpec > { TefleW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Timestamp Wraparound Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tswe (& mut self) -> TsweW < IeSpec > { TsweW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Message RAM Access Failure Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn mrafe (& mut self) -> MrafeW < IeSpec > { MrafeW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Timeout Occurred Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tooe (& mut self) -> TooeW < IeSpec > { TooeW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn drx (& mut self) -> DrxW < IeSpec > { DrxW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Bit Error Corrected Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn bece (& mut self) -> BeceW < IeSpec > { BeceW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Bit Error Uncorrected Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn beue (& mut self) -> BeueW < IeSpec > { BeueW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Error Logging Overflow Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn eloe (& mut self) -> EloeW < IeSpec > { EloeW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Error Passive Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn epe (& mut self) -> EpeW < IeSpec > { EpeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Warning Status Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn ewe (& mut self) -> EweW < IeSpec > { EweW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Bus_Off Status Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn boe (& mut self) -> BoeW < IeSpec > { BoeW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Watchdog Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn wdie (& mut self) -> WdieW < IeSpec > { WdieW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn peae (& mut self) -> PeaeW < IeSpec > { PeaeW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Protocol Error in Data Phase Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn pede (& mut self) -> PedeW < IeSpec > { PedeW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Accees to Reserve Address Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn arae (& mut self) -> AraeW < IeSpec > { AraeW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu31 (& mut self) -> Nu31W < IeSpec > { Nu31W :: new (self , 30) } } # [doc = "IE\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IeSpec ; impl crate :: RegisterSpec for IeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ie::R`](R) reader structure"]
impl crate :: Readable for IeSpec { } # [doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"]
impl crate :: Writable for IeSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IE to value 0"]
impl crate :: Resettable for IeSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ILS (rw) register accessor: ILS\n\nYou can [`read`](crate::Reg::read) this register and get [`ils::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ils::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ils`]
module"]
# [doc (alias = "ILS")]
pub type Ils = crate :: Reg < ils :: IlsSpec > ; # [doc = "ILS"]
pub mod ils { # [doc = "Register `ILS` reader"]
pub type R = crate :: R < IlsSpec > ; # [doc = "Register `ILS` writer"]
pub type W = crate :: W < IlsSpec > ; # [doc = "Field `RF0NL` reader - 0:0\\]
Rx FIFO 0 New Message Interrupt Line"]
pub type Rf0nlR = crate :: BitReader ; # [doc = "Field `RF0NL` writer - 0:0\\]
Rx FIFO 0 New Message Interrupt Line"]
pub type Rf0nlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0WL` reader - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Line"]
pub type Rf0wlR = crate :: BitReader ; # [doc = "Field `RF0WL` writer - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Line"]
pub type Rf0wlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0FL` reader - 2:2\\]
Rx FIFO 0 Full Interrupt Line"]
pub type Rf0flR = crate :: BitReader ; # [doc = "Field `RF0FL` writer - 2:2\\]
Rx FIFO 0 Full Interrupt Line"]
pub type Rf0flW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0LL` reader - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Line"]
pub type Rf0llR = crate :: BitReader ; # [doc = "Field `RF0LL` writer - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Line"]
pub type Rf0llW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1NL` reader - 4:4\\]
Rx FIFO 1 New Message Interrupt Line"]
pub type Rf1nlR = crate :: BitReader ; # [doc = "Field `RF1NL` writer - 4:4\\]
Rx FIFO 1 New Message Interrupt Line"]
pub type Rf1nlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1WL` reader - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Line"]
pub type Rf1wlR = crate :: BitReader ; # [doc = "Field `RF1WL` writer - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Line"]
pub type Rf1wlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1FL` reader - 6:6\\]
Rx FIFO 1 Full Interrupt Line"]
pub type Rf1flR = crate :: BitReader ; # [doc = "Field `RF1FL` writer - 6:6\\]
Rx FIFO 1 Full Interrupt Line"]
pub type Rf1flW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1LL` reader - 7:7\\]
rx FIFO 1 Message Lost Interrupt Line"]
pub type Rf1llR = crate :: BitReader ; # [doc = "Field `RF1LL` writer - 7:7\\]
rx FIFO 1 Message Lost Interrupt Line"]
pub type Rf1llW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HPML` reader - 8:8\\]
High Priority message Interrupt Line"]
pub type HpmlR = crate :: BitReader ; # [doc = "Field `HPML` writer - 8:8\\]
High Priority message Interrupt Line"]
pub type HpmlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCL` reader - 9:9\\]
Transmission Completed Interrupt Line"]
pub type TclR = crate :: BitReader ; # [doc = "Field `TCL` writer - 9:9\\]
Transmission Completed Interrupt Line"]
pub type TclW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCFL` reader - 10:10\\]
Transmission Cancellation Finishied Interrupt Line"]
pub type TcflR = crate :: BitReader ; # [doc = "Field `TCFL` writer - 10:10\\]
Transmission Cancellation Finishied Interrupt Line"]
pub type TcflW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TFEL` reader - 11:11\\]
Tx FIFO Empty Interrupt Line"]
pub type TfelR = crate :: BitReader ; # [doc = "Field `TFEL` writer - 11:11\\]
Tx FIFO Empty Interrupt Line"]
pub type TfelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFNL` reader - 12:12\\]
Tx Event FIFO New Entry Interrupt Line"]
pub type TefnlR = crate :: BitReader ; # [doc = "Field `TEFNL` writer - 12:12\\]
Tx Event FIFO New Entry Interrupt Line"]
pub type TefnlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFWL` reader - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt Line"]
pub type TefwlR = crate :: BitReader ; # [doc = "Field `TEFWL` writer - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt Line"]
pub type TefwlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFFL` reader - 14:14\\]
Tx Event FIFO Full Interrupt Line"]
pub type TefflR = crate :: BitReader ; # [doc = "Field `TEFFL` writer - 14:14\\]
Tx Event FIFO Full Interrupt Line"]
pub type TefflW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFLL` reader - 15:15\\]
Tx Event FIFO Event Lost Interrupt Line"]
pub type TefllR = crate :: BitReader ; # [doc = "Field `TEFLL` writer - 15:15\\]
Tx Event FIFO Event Lost Interrupt Line"]
pub type TefllW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TSWL` reader - 16:16\\]
Timestamp Wraparound Interrupt Line"]
pub type TswlR = crate :: BitReader ; # [doc = "Field `TSWL` writer - 16:16\\]
Timestamp Wraparound Interrupt Line"]
pub type TswlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MRAFL` reader - 17:17\\]
Message RAM Access Failure Interrupt Line"]
pub type MraflR = crate :: BitReader ; # [doc = "Field `MRAFL` writer - 17:17\\]
Message RAM Access Failure Interrupt Line"]
pub type MraflW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TOOL` reader - 18:18\\]
Timeout Occurred Interrupt Line"]
pub type ToolR = crate :: BitReader ; # [doc = "Field `TOOL` writer - 18:18\\]
Timeout Occurred Interrupt Line"]
pub type ToolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DRXL` reader - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Line"]
pub type DrxlR = crate :: BitReader ; # [doc = "Field `DRXL` writer - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Line"]
pub type DrxlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BECL` reader - 20:20\\]
Bit Error Corrected Interrupt Line"]
pub type BeclR = crate :: BitReader ; # [doc = "Field `BECL` writer - 20:20\\]
Bit Error Corrected Interrupt Line"]
pub type BeclW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BEUL` reader - 21:21\\]
Bit Error Uncorrected Interrupt Line"]
pub type BeulR = crate :: BitReader ; # [doc = "Field `BEUL` writer - 21:21\\]
Bit Error Uncorrected Interrupt Line"]
pub type BeulW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ELOL` reader - 22:22\\]
Error Logging Overflow Interrupt Line"]
pub type ElolR = crate :: BitReader ; # [doc = "Field `ELOL` writer - 22:22\\]
Error Logging Overflow Interrupt Line"]
pub type ElolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EPL` reader - 23:23\\]
Error Passive Interrupt Line"]
pub type EplR = crate :: BitReader ; # [doc = "Field `EPL` writer - 23:23\\]
Error Passive Interrupt Line"]
pub type EplW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EWL` reader - 24:24\\]
Warning Status Interrupt Line"]
pub type EwlR = crate :: BitReader ; # [doc = "Field `EWL` writer - 24:24\\]
Warning Status Interrupt Line"]
pub type EwlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BOL` reader - 25:25\\]
Bus_Off Status Interrupt Line"]
pub type BolR = crate :: BitReader ; # [doc = "Field `BOL` writer - 25:25\\]
Bus_Off Status Interrupt Line"]
pub type BolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WDIL` reader - 26:26\\]
Watchdog Interrupt Line"]
pub type WdilR = crate :: BitReader ; # [doc = "Field `WDIL` writer - 26:26\\]
Watchdog Interrupt Line"]
pub type WdilW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEAL` reader - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Line"]
pub type PealR = crate :: BitReader ; # [doc = "Field `PEAL` writer - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Line"]
pub type PealW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEDL` reader - 28:28\\]
Protocol Error in Data Phase Interrupt Line"]
pub type PedlR = crate :: BitReader ; # [doc = "Field `PEDL` writer - 28:28\\]
Protocol Error in Data Phase Interrupt Line"]
pub type PedlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ARAL` reader - 29:29\\]
Accees to Reserve Address Interrupt Line"]
pub type AralR = crate :: BitReader ; # [doc = "Field `ARAL` writer - 29:29\\]
Accees to Reserve Address Interrupt Line"]
pub type AralW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU32` reader - 31:30\\]
Reserved"]
pub type Nu32R = crate :: FieldReader ; # [doc = "Field `NU32` writer - 31:30\\]
Reserved"]
pub type Nu32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Rx FIFO 0 New Message Interrupt Line"]
# [inline (always)]
pub fn rf0nl (& self) -> Rf0nlR { Rf0nlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Line"]
# [inline (always)]
pub fn rf0wl (& self) -> Rf0wlR { Rf0wlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Rx FIFO 0 Full Interrupt Line"]
# [inline (always)]
pub fn rf0fl (& self) -> Rf0flR { Rf0flR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Line"]
# [inline (always)]
pub fn rf0ll (& self) -> Rf0llR { Rf0llR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Rx FIFO 1 New Message Interrupt Line"]
# [inline (always)]
pub fn rf1nl (& self) -> Rf1nlR { Rf1nlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Line"]
# [inline (always)]
pub fn rf1wl (& self) -> Rf1wlR { Rf1wlR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Rx FIFO 1 Full Interrupt Line"]
# [inline (always)]
pub fn rf1fl (& self) -> Rf1flR { Rf1flR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
rx FIFO 1 Message Lost Interrupt Line"]
# [inline (always)]
pub fn rf1ll (& self) -> Rf1llR { Rf1llR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
High Priority message Interrupt Line"]
# [inline (always)]
pub fn hpml (& self) -> HpmlR { HpmlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmission Completed Interrupt Line"]
# [inline (always)]
pub fn tcl (& self) -> TclR { TclR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Transmission Cancellation Finishied Interrupt Line"]
# [inline (always)]
pub fn tcfl (& self) -> TcflR { TcflR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Tx FIFO Empty Interrupt Line"]
# [inline (always)]
pub fn tfel (& self) -> TfelR { TfelR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Tx Event FIFO New Entry Interrupt Line"]
# [inline (always)]
pub fn tefnl (& self) -> TefnlR { TefnlR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt Line"]
# [inline (always)]
pub fn tefwl (& self) -> TefwlR { TefwlR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Tx Event FIFO Full Interrupt Line"]
# [inline (always)]
pub fn teffl (& self) -> TefflR { TefflR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Tx Event FIFO Event Lost Interrupt Line"]
# [inline (always)]
pub fn tefll (& self) -> TefllR { TefllR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Timestamp Wraparound Interrupt Line"]
# [inline (always)]
pub fn tswl (& self) -> TswlR { TswlR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Message RAM Access Failure Interrupt Line"]
# [inline (always)]
pub fn mrafl (& self) -> MraflR { MraflR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Timeout Occurred Interrupt Line"]
# [inline (always)]
pub fn tool (& self) -> ToolR { ToolR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Line"]
# [inline (always)]
pub fn drxl (& self) -> DrxlR { DrxlR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Bit Error Corrected Interrupt Line"]
# [inline (always)]
pub fn becl (& self) -> BeclR { BeclR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Bit Error Uncorrected Interrupt Line"]
# [inline (always)]
pub fn beul (& self) -> BeulR { BeulR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Error Logging Overflow Interrupt Line"]
# [inline (always)]
pub fn elol (& self) -> ElolR { ElolR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Error Passive Interrupt Line"]
# [inline (always)]
pub fn epl (& self) -> EplR { EplR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Warning Status Interrupt Line"]
# [inline (always)]
pub fn ewl (& self) -> EwlR { EwlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Bus_Off Status Interrupt Line"]
# [inline (always)]
pub fn bol (& self) -> BolR { BolR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Watchdog Interrupt Line"]
# [inline (always)]
pub fn wdil (& self) -> WdilR { WdilR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Line"]
# [inline (always)]
pub fn peal (& self) -> PealR { PealR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Protocol Error in Data Phase Interrupt Line"]
# [inline (always)]
pub fn pedl (& self) -> PedlR { PedlR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Accees to Reserve Address Interrupt Line"]
# [inline (always)]
pub fn aral (& self) -> AralR { AralR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
pub fn nu32 (& self) -> Nu32R { Nu32R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Rx FIFO 0 New Message Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf0nl (& mut self) -> Rf0nlW < IlsSpec > { Rf0nlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Rx FIFO 0 Watermark Reached Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf0wl (& mut self) -> Rf0wlW < IlsSpec > { Rf0wlW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Rx FIFO 0 Full Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf0fl (& mut self) -> Rf0flW < IlsSpec > { Rf0flW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Rx FIFO 0 Message Lost Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf0ll (& mut self) -> Rf0llW < IlsSpec > { Rf0llW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Rx FIFO 1 New Message Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf1nl (& mut self) -> Rf1nlW < IlsSpec > { Rf1nlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Rx FIFO 1 Watermark Reached Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf1wl (& mut self) -> Rf1wlW < IlsSpec > { Rf1wlW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Rx FIFO 1 Full Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf1fl (& mut self) -> Rf1flW < IlsSpec > { Rf1flW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
rx FIFO 1 Message Lost Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn rf1ll (& mut self) -> Rf1llW < IlsSpec > { Rf1llW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
High Priority message Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn hpml (& mut self) -> HpmlW < IlsSpec > { HpmlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmission Completed Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tcl (& mut self) -> TclW < IlsSpec > { TclW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Transmission Cancellation Finishied Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tcfl (& mut self) -> TcflW < IlsSpec > { TcflW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Tx FIFO Empty Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tfel (& mut self) -> TfelW < IlsSpec > { TfelW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Tx Event FIFO New Entry Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tefnl (& mut self) -> TefnlW < IlsSpec > { TefnlW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Tx Event FIFO Watermark Reached Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tefwl (& mut self) -> TefwlW < IlsSpec > { TefwlW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Tx Event FIFO Full Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn teffl (& mut self) -> TefflW < IlsSpec > { TefflW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Tx Event FIFO Event Lost Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tefll (& mut self) -> TefllW < IlsSpec > { TefllW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Timestamp Wraparound Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tswl (& mut self) -> TswlW < IlsSpec > { TswlW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Message RAM Access Failure Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn mrafl (& mut self) -> MraflW < IlsSpec > { MraflW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Timeout Occurred Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn tool (& mut self) -> ToolW < IlsSpec > { ToolW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Message stored to Dedicated Rx Buffer Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn drxl (& mut self) -> DrxlW < IlsSpec > { DrxlW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Bit Error Corrected Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn becl (& mut self) -> BeclW < IlsSpec > { BeclW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Bit Error Uncorrected Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn beul (& mut self) -> BeulW < IlsSpec > { BeulW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Error Logging Overflow Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn elol (& mut self) -> ElolW < IlsSpec > { ElolW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Error Passive Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn epl (& mut self) -> EplW < IlsSpec > { EplW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Warning Status Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn ewl (& mut self) -> EwlW < IlsSpec > { EwlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Bus_Off Status Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn bol (& mut self) -> BolW < IlsSpec > { BolW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Watchdog Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn wdil (& mut self) -> WdilW < IlsSpec > { WdilW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Protocol Error in Arbitration Phase Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn peal (& mut self) -> PealW < IlsSpec > { PealW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Protocol Error in Data Phase Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn pedl (& mut self) -> PedlW < IlsSpec > { PedlW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Accees to Reserve Address Interrupt Line"]
# [inline (always)]
# [must_use]
pub fn aral (& mut self) -> AralW < IlsSpec > { AralW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu32 (& mut self) -> Nu32W < IlsSpec > { Nu32W :: new (self , 30) } } # [doc = "ILS\n\nYou can [`read`](crate::Reg::read) this register and get [`ils::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ils::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IlsSpec ; impl crate :: RegisterSpec for IlsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ils::R`](R) reader structure"]
impl crate :: Readable for IlsSpec { } # [doc = "`write(|w| ..)` method takes [`ils::W`](W) writer structure"]
impl crate :: Writable for IlsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ILS to value 0"]
impl crate :: Resettable for IlsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ILE (rw) register accessor: ILE\n\nYou can [`read`](crate::Reg::read) this register and get [`ile::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ile::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ile`]
module"]
# [doc (alias = "ILE")]
pub type Ile = crate :: Reg < ile :: IleSpec > ; # [doc = "ILE"]
pub mod ile { # [doc = "Register `ILE` reader"]
pub type R = crate :: R < IleSpec > ; # [doc = "Register `ILE` writer"]
pub type W = crate :: W < IleSpec > ; # [doc = "Field `EINT0` reader - 0:0\\]
Enable Interrupt Line 0"]
pub type Eint0R = crate :: BitReader ; # [doc = "Field `EINT0` writer - 0:0\\]
Enable Interrupt Line 0"]
pub type Eint0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EINT1` reader - 1:1\\]
Enable Interrupt Line 1"]
pub type Eint1R = crate :: BitReader ; # [doc = "Field `EINT1` writer - 1:1\\]
Enable Interrupt Line 1"]
pub type Eint1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU33` reader - 31:2\\]
Reserved"]
pub type Nu33R = crate :: FieldReader < u32 > ; # [doc = "Field `NU33` writer - 31:2\\]
Reserved"]
pub type Nu33W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Enable Interrupt Line 0"]
# [inline (always)]
pub fn eint0 (& self) -> Eint0R { Eint0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Enable Interrupt Line 1"]
# [inline (always)]
pub fn eint1 (& self) -> Eint1R { Eint1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu33 (& self) -> Nu33R { Nu33R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Enable Interrupt Line 0"]
# [inline (always)]
# [must_use]
pub fn eint0 (& mut self) -> Eint0W < IleSpec > { Eint0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Enable Interrupt Line 1"]
# [inline (always)]
# [must_use]
pub fn eint1 (& mut self) -> Eint1W < IleSpec > { Eint1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu33 (& mut self) -> Nu33W < IleSpec > { Nu33W :: new (self , 2) } } # [doc = "ILE\n\nYou can [`read`](crate::Reg::read) this register and get [`ile::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ile::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IleSpec ; impl crate :: RegisterSpec for IleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ile::R`](R) reader structure"]
impl crate :: Readable for IleSpec { } # [doc = "`write(|w| ..)` method takes [`ile::W`](W) writer structure"]
impl crate :: Writable for IleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ILE to value 0"]
impl crate :: Resettable for IleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES05 (rw) register accessor: RES05\n\nYou can [`read`](crate::Reg::read) this register and get [`res05::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res05::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res05`]
module"]
# [doc (alias = "RES05")]
pub type Res05 = crate :: Reg < res05 :: Res05Spec > ; # [doc = "RES05"]
pub mod res05 { # [doc = "Register `RES05` reader"]
pub type R = crate :: R < Res05Spec > ; # [doc = "Register `RES05` writer"]
pub type W = crate :: W < Res05Spec > ; # [doc = "Field `RES05` reader - 31:0\\]
Reserved"]
pub type Res05R = crate :: FieldReader < u32 > ; # [doc = "Field `RES05` writer - 31:0\\]
Reserved"]
pub type Res05W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res05 (& self) -> Res05R { Res05R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res05 (& mut self) -> Res05W < Res05Spec > { Res05W :: new (self , 0) } } # [doc = "RES05\n\nYou can [`read`](crate::Reg::read) this register and get [`res05::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res05::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res05Spec ; impl crate :: RegisterSpec for Res05Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res05::R`](R) reader structure"]
impl crate :: Readable for Res05Spec { } # [doc = "`write(|w| ..)` method takes [`res05::W`](W) writer structure"]
impl crate :: Writable for Res05Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES05 to value 0"]
impl crate :: Resettable for Res05Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES06 (rw) register accessor: RES06\n\nYou can [`read`](crate::Reg::read) this register and get [`res06::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res06::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res06`]
module"]
# [doc (alias = "RES06")]
pub type Res06 = crate :: Reg < res06 :: Res06Spec > ; # [doc = "RES06"]
pub mod res06 { # [doc = "Register `RES06` reader"]
pub type R = crate :: R < Res06Spec > ; # [doc = "Register `RES06` writer"]
pub type W = crate :: W < Res06Spec > ; # [doc = "Field `RES06` reader - 31:0\\]
Reserved"]
pub type Res06R = crate :: FieldReader < u32 > ; # [doc = "Field `RES06` writer - 31:0\\]
Reserved"]
pub type Res06W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res06 (& self) -> Res06R { Res06R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res06 (& mut self) -> Res06W < Res06Spec > { Res06W :: new (self , 0) } } # [doc = "RES06\n\nYou can [`read`](crate::Reg::read) this register and get [`res06::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res06::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res06Spec ; impl crate :: RegisterSpec for Res06Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res06::R`](R) reader structure"]
impl crate :: Readable for Res06Spec { } # [doc = "`write(|w| ..)` method takes [`res06::W`](W) writer structure"]
impl crate :: Writable for Res06Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES06 to value 0"]
impl crate :: Resettable for Res06Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES07 (rw) register accessor: RES07\n\nYou can [`read`](crate::Reg::read) this register and get [`res07::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res07::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res07`]
module"]
# [doc (alias = "RES07")]
pub type Res07 = crate :: Reg < res07 :: Res07Spec > ; # [doc = "RES07"]
pub mod res07 { # [doc = "Register `RES07` reader"]
pub type R = crate :: R < Res07Spec > ; # [doc = "Register `RES07` writer"]
pub type W = crate :: W < Res07Spec > ; # [doc = "Field `RES07` reader - 31:0\\]
Reserved"]
pub type Res07R = crate :: FieldReader < u32 > ; # [doc = "Field `RES07` writer - 31:0\\]
Reserved"]
pub type Res07W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res07 (& self) -> Res07R { Res07R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res07 (& mut self) -> Res07W < Res07Spec > { Res07W :: new (self , 0) } } # [doc = "RES07\n\nYou can [`read`](crate::Reg::read) this register and get [`res07::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res07::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res07Spec ; impl crate :: RegisterSpec for Res07Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res07::R`](R) reader structure"]
impl crate :: Readable for Res07Spec { } # [doc = "`write(|w| ..)` method takes [`res07::W`](W) writer structure"]
impl crate :: Writable for Res07Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES07 to value 0"]
impl crate :: Resettable for Res07Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES08 (rw) register accessor: RES08\n\nYou can [`read`](crate::Reg::read) this register and get [`res08::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res08::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res08`]
module"]
# [doc (alias = "RES08")]
pub type Res08 = crate :: Reg < res08 :: Res08Spec > ; # [doc = "RES08"]
pub mod res08 { # [doc = "Register `RES08` reader"]
pub type R = crate :: R < Res08Spec > ; # [doc = "Register `RES08` writer"]
pub type W = crate :: W < Res08Spec > ; # [doc = "Field `RES08` reader - 31:0\\]
Reserved"]
pub type Res08R = crate :: FieldReader < u32 > ; # [doc = "Field `RES08` writer - 31:0\\]
Reserved"]
pub type Res08W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res08 (& self) -> Res08R { Res08R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res08 (& mut self) -> Res08W < Res08Spec > { Res08W :: new (self , 0) } } # [doc = "RES08\n\nYou can [`read`](crate::Reg::read) this register and get [`res08::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res08::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res08Spec ; impl crate :: RegisterSpec for Res08Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res08::R`](R) reader structure"]
impl crate :: Readable for Res08Spec { } # [doc = "`write(|w| ..)` method takes [`res08::W`](W) writer structure"]
impl crate :: Writable for Res08Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES08 to value 0"]
impl crate :: Resettable for Res08Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES09 (rw) register accessor: RES09\n\nYou can [`read`](crate::Reg::read) this register and get [`res09::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res09::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res09`]
module"]
# [doc (alias = "RES09")]
pub type Res09 = crate :: Reg < res09 :: Res09Spec > ; # [doc = "RES09"]
pub mod res09 { # [doc = "Register `RES09` reader"]
pub type R = crate :: R < Res09Spec > ; # [doc = "Register `RES09` writer"]
pub type W = crate :: W < Res09Spec > ; # [doc = "Field `RES09` reader - 31:0\\]
Reserved"]
pub type Res09R = crate :: FieldReader < u32 > ; # [doc = "Field `RES09` writer - 31:0\\]
Reserved"]
pub type Res09W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res09 (& self) -> Res09R { Res09R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res09 (& mut self) -> Res09W < Res09Spec > { Res09W :: new (self , 0) } } # [doc = "RES09\n\nYou can [`read`](crate::Reg::read) this register and get [`res09::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res09::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res09Spec ; impl crate :: RegisterSpec for Res09Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res09::R`](R) reader structure"]
impl crate :: Readable for Res09Spec { } # [doc = "`write(|w| ..)` method takes [`res09::W`](W) writer structure"]
impl crate :: Writable for Res09Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES09 to value 0"]
impl crate :: Resettable for Res09Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES10 (rw) register accessor: RES10\n\nYou can [`read`](crate::Reg::read) this register and get [`res10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res10`]
module"]
# [doc (alias = "RES10")]
pub type Res10 = crate :: Reg < res10 :: Res10Spec > ; # [doc = "RES10"]
pub mod res10 { # [doc = "Register `RES10` reader"]
pub type R = crate :: R < Res10Spec > ; # [doc = "Register `RES10` writer"]
pub type W = crate :: W < Res10Spec > ; # [doc = "Field `RES10` reader - 31:0\\]
Reserved"]
pub type Res10R = crate :: FieldReader < u32 > ; # [doc = "Field `RES10` writer - 31:0\\]
Reserved"]
pub type Res10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res10 (& self) -> Res10R { Res10R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res10 (& mut self) -> Res10W < Res10Spec > { Res10W :: new (self , 0) } } # [doc = "RES10\n\nYou can [`read`](crate::Reg::read) this register and get [`res10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res10Spec ; impl crate :: RegisterSpec for Res10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res10::R`](R) reader structure"]
impl crate :: Readable for Res10Spec { } # [doc = "`write(|w| ..)` method takes [`res10::W`](W) writer structure"]
impl crate :: Writable for Res10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES10 to value 0"]
impl crate :: Resettable for Res10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES11 (rw) register accessor: RES11\n\nYou can [`read`](crate::Reg::read) this register and get [`res11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res11`]
module"]
# [doc (alias = "RES11")]
pub type Res11 = crate :: Reg < res11 :: Res11Spec > ; # [doc = "RES11"]
pub mod res11 { # [doc = "Register `RES11` reader"]
pub type R = crate :: R < Res11Spec > ; # [doc = "Register `RES11` writer"]
pub type W = crate :: W < Res11Spec > ; # [doc = "Field `RES11` reader - 31:0\\]
Reserved"]
pub type Res11R = crate :: FieldReader < u32 > ; # [doc = "Field `RES11` writer - 31:0\\]
Reserved"]
pub type Res11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res11 (& self) -> Res11R { Res11R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res11 (& mut self) -> Res11W < Res11Spec > { Res11W :: new (self , 0) } } # [doc = "RES11\n\nYou can [`read`](crate::Reg::read) this register and get [`res11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res11Spec ; impl crate :: RegisterSpec for Res11Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res11::R`](R) reader structure"]
impl crate :: Readable for Res11Spec { } # [doc = "`write(|w| ..)` method takes [`res11::W`](W) writer structure"]
impl crate :: Writable for Res11Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES11 to value 0"]
impl crate :: Resettable for Res11Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES12 (rw) register accessor: RES12\n\nYou can [`read`](crate::Reg::read) this register and get [`res12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res12`]
module"]
# [doc (alias = "RES12")]
pub type Res12 = crate :: Reg < res12 :: Res12Spec > ; # [doc = "RES12"]
pub mod res12 { # [doc = "Register `RES12` reader"]
pub type R = crate :: R < Res12Spec > ; # [doc = "Register `RES12` writer"]
pub type W = crate :: W < Res12Spec > ; # [doc = "Field `RES12` reader - 31:0\\]
Reserved"]
pub type Res12R = crate :: FieldReader < u32 > ; # [doc = "Field `RES12` writer - 31:0\\]
Reserved"]
pub type Res12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res12 (& self) -> Res12R { Res12R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res12 (& mut self) -> Res12W < Res12Spec > { Res12W :: new (self , 0) } } # [doc = "RES12\n\nYou can [`read`](crate::Reg::read) this register and get [`res12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res12Spec ; impl crate :: RegisterSpec for Res12Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res12::R`](R) reader structure"]
impl crate :: Readable for Res12Spec { } # [doc = "`write(|w| ..)` method takes [`res12::W`](W) writer structure"]
impl crate :: Writable for Res12Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES12 to value 0"]
impl crate :: Resettable for Res12Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GFC (rw) register accessor: GFC\n\nYou can [`read`](crate::Reg::read) this register and get [`gfc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gfc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gfc`]
module"]
# [doc (alias = "GFC")]
pub type Gfc = crate :: Reg < gfc :: GfcSpec > ; # [doc = "GFC"]
pub mod gfc { # [doc = "Register `GFC` reader"]
pub type R = crate :: R < GfcSpec > ; # [doc = "Register `GFC` writer"]
pub type W = crate :: W < GfcSpec > ; # [doc = "Field `RRFE` reader - 0:0\\]
reject Remote Frames Extended"]
pub type RrfeR = crate :: BitReader ; # [doc = "Field `RRFE` writer - 0:0\\]
reject Remote Frames Extended"]
pub type RrfeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RRFS` reader - 1:1\\]
reject Remote Frames Standard"]
pub type RrfsR = crate :: BitReader ; # [doc = "Field `RRFS` writer - 1:1\\]
reject Remote Frames Standard"]
pub type RrfsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ANFE` reader - 3:2\\]
Accept Non-matching Frames Extended"]
pub type AnfeR = crate :: FieldReader ; # [doc = "Field `ANFE` writer - 3:2\\]
Accept Non-matching Frames Extended"]
pub type AnfeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ANFS` reader - 5:4\\]
Accept Non-matching Frames Standard"]
pub type AnfsR = crate :: FieldReader ; # [doc = "Field `ANFS` writer - 5:4\\]
Accept Non-matching Frames Standard"]
pub type AnfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU34` reader - 31:6\\]
Reserved"]
pub type Nu34R = crate :: FieldReader < u32 > ; # [doc = "Field `NU34` writer - 31:6\\]
Reserved"]
pub type Nu34W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
reject Remote Frames Extended"]
# [inline (always)]
pub fn rrfe (& self) -> RrfeR { RrfeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
reject Remote Frames Standard"]
# [inline (always)]
pub fn rrfs (& self) -> RrfsR { RrfsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - 3:2\\]
Accept Non-matching Frames Extended"]
# [inline (always)]
pub fn anfe (& self) -> AnfeR { AnfeR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Accept Non-matching Frames Standard"]
# [inline (always)]
pub fn anfs (& self) -> AnfsR { AnfsR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu34 (& self) -> Nu34R { Nu34R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
reject Remote Frames Extended"]
# [inline (always)]
# [must_use]
pub fn rrfe (& mut self) -> RrfeW < GfcSpec > { RrfeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
reject Remote Frames Standard"]
# [inline (always)]
# [must_use]
pub fn rrfs (& mut self) -> RrfsW < GfcSpec > { RrfsW :: new (self , 1) } # [doc = "Bits 2:3 - 3:2\\]
Accept Non-matching Frames Extended"]
# [inline (always)]
# [must_use]
pub fn anfe (& mut self) -> AnfeW < GfcSpec > { AnfeW :: new (self , 2) } # [doc = "Bits 4:5 - 5:4\\]
Accept Non-matching Frames Standard"]
# [inline (always)]
# [must_use]
pub fn anfs (& mut self) -> AnfsW < GfcSpec > { AnfsW :: new (self , 4) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu34 (& mut self) -> Nu34W < GfcSpec > { Nu34W :: new (self , 6) } } # [doc = "GFC\n\nYou can [`read`](crate::Reg::read) this register and get [`gfc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gfc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GfcSpec ; impl crate :: RegisterSpec for GfcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gfc::R`](R) reader structure"]
impl crate :: Readable for GfcSpec { } # [doc = "`write(|w| ..)` method takes [`gfc::W`](W) writer structure"]
impl crate :: Writable for GfcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GFC to value 0"]
impl crate :: Resettable for GfcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIDFC (rw) register accessor: SIDFC\n\nYou can [`read`](crate::Reg::read) this register and get [`sidfc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidfc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sidfc`]
module"]
# [doc (alias = "SIDFC")]
pub type Sidfc = crate :: Reg < sidfc :: SidfcSpec > ; # [doc = "SIDFC"]
pub mod sidfc { # [doc = "Register `SIDFC` reader"]
pub type R = crate :: R < SidfcSpec > ; # [doc = "Register `SIDFC` writer"]
pub type W = crate :: W < SidfcSpec > ; # [doc = "Field `NU35` reader - 1:0\\]
Reserved"]
pub type Nu35R = crate :: FieldReader ; # [doc = "Field `NU35` writer - 1:0\\]
Reserved"]
pub type Nu35W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FLSSA_S` reader - 15:2\\]
Filter List Standard Start Address"]
pub type FlssaSR = crate :: FieldReader < u16 > ; # [doc = "Field `FLSSA_S` writer - 15:2\\]
Filter List Standard Start Address"]
pub type FlssaSW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `LSS_S` reader - 23:16\\]
List Size Standard"]
pub type LssSR = crate :: FieldReader ; # [doc = "Field `LSS_S` writer - 23:16\\]
List Size Standard"]
pub type LssSW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU36` reader - 31:24\\]
Reserved"]
pub type Nu36R = crate :: FieldReader ; # [doc = "Field `NU36` writer - 31:24\\]
Reserved"]
pub type Nu36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu35 (& self) -> Nu35R { Nu35R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:15 - 15:2\\]
Filter List Standard Start Address"]
# [inline (always)]
pub fn flssa_s (& self) -> FlssaSR { FlssaSR :: new (((self . bits >> 2) & 0x3fff) as u16) } # [doc = "Bits 16:23 - 23:16\\]
List Size Standard"]
# [inline (always)]
pub fn lss_s (& self) -> LssSR { LssSR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn nu36 (& self) -> Nu36R { Nu36R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu35 (& mut self) -> Nu35W < SidfcSpec > { Nu35W :: new (self , 0) } # [doc = "Bits 2:15 - 15:2\\]
Filter List Standard Start Address"]
# [inline (always)]
# [must_use]
pub fn flssa_s (& mut self) -> FlssaSW < SidfcSpec > { FlssaSW :: new (self , 2) } # [doc = "Bits 16:23 - 23:16\\]
List Size Standard"]
# [inline (always)]
# [must_use]
pub fn lss_s (& mut self) -> LssSW < SidfcSpec > { LssSW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu36 (& mut self) -> Nu36W < SidfcSpec > { Nu36W :: new (self , 24) } } # [doc = "SIDFC\n\nYou can [`read`](crate::Reg::read) this register and get [`sidfc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidfc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SidfcSpec ; impl crate :: RegisterSpec for SidfcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sidfc::R`](R) reader structure"]
impl crate :: Readable for SidfcSpec { } # [doc = "`write(|w| ..)` method takes [`sidfc::W`](W) writer structure"]
impl crate :: Writable for SidfcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIDFC to value 0"]
impl crate :: Resettable for SidfcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XIDFC (rw) register accessor: XIDFC\n\nYou can [`read`](crate::Reg::read) this register and get [`xidfc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xidfc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xidfc`]
module"]
# [doc (alias = "XIDFC")]
pub type Xidfc = crate :: Reg < xidfc :: XidfcSpec > ; # [doc = "XIDFC"]
pub mod xidfc { # [doc = "Register `XIDFC` reader"]
pub type R = crate :: R < XidfcSpec > ; # [doc = "Register `XIDFC` writer"]
pub type W = crate :: W < XidfcSpec > ; # [doc = "Field `NU37` reader - 1:0\\]
Reserved"]
pub type Nu37R = crate :: FieldReader ; # [doc = "Field `NU37` writer - 1:0\\]
Reserved"]
pub type Nu37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FLSSA_X` reader - 15:2\\]
Filter List Standard Start Address"]
pub type FlssaXR = crate :: FieldReader < u16 > ; # [doc = "Field `FLSSA_X` writer - 15:2\\]
Filter List Standard Start Address"]
pub type FlssaXW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `LSS_X` reader - 22:16\\]
List Size Standard"]
pub type LssXR = crate :: FieldReader ; # [doc = "Field `LSS_X` writer - 22:16\\]
List Size Standard"]
pub type LssXW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU38` reader - 31:23\\]
Reserved"]
pub type Nu38R = crate :: FieldReader < u16 > ; # [doc = "Field `NU38` writer - 31:23\\]
Reserved"]
pub type Nu38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu37 (& self) -> Nu37R { Nu37R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:15 - 15:2\\]
Filter List Standard Start Address"]
# [inline (always)]
pub fn flssa_x (& self) -> FlssaXR { FlssaXR :: new (((self . bits >> 2) & 0x3fff) as u16) } # [doc = "Bits 16:22 - 22:16\\]
List Size Standard"]
# [inline (always)]
pub fn lss_x (& self) -> LssXR { LssXR :: new (((self . bits >> 16) & 0x7f) as u8) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
pub fn nu38 (& self) -> Nu38R { Nu38R :: new (((self . bits >> 23) & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu37 (& mut self) -> Nu37W < XidfcSpec > { Nu37W :: new (self , 0) } # [doc = "Bits 2:15 - 15:2\\]
Filter List Standard Start Address"]
# [inline (always)]
# [must_use]
pub fn flssa_x (& mut self) -> FlssaXW < XidfcSpec > { FlssaXW :: new (self , 2) } # [doc = "Bits 16:22 - 22:16\\]
List Size Standard"]
# [inline (always)]
# [must_use]
pub fn lss_x (& mut self) -> LssXW < XidfcSpec > { LssXW :: new (self , 16) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu38 (& mut self) -> Nu38W < XidfcSpec > { Nu38W :: new (self , 23) } } # [doc = "XIDFC\n\nYou can [`read`](crate::Reg::read) this register and get [`xidfc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xidfc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XidfcSpec ; impl crate :: RegisterSpec for XidfcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xidfc::R`](R) reader structure"]
impl crate :: Readable for XidfcSpec { } # [doc = "`write(|w| ..)` method takes [`xidfc::W`](W) writer structure"]
impl crate :: Writable for XidfcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XIDFC to value 0"]
impl crate :: Resettable for XidfcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES13 (rw) register accessor: RES13\n\nYou can [`read`](crate::Reg::read) this register and get [`res13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res13`]
module"]
# [doc (alias = "RES13")]
pub type Res13 = crate :: Reg < res13 :: Res13Spec > ; # [doc = "RES13"]
pub mod res13 { # [doc = "Register `RES13` reader"]
pub type R = crate :: R < Res13Spec > ; # [doc = "Register `RES13` writer"]
pub type W = crate :: W < Res13Spec > ; # [doc = "Field `RES13` reader - 31:0\\]
Reserved"]
pub type Res13R = crate :: FieldReader < u32 > ; # [doc = "Field `RES13` writer - 31:0\\]
Reserved"]
pub type Res13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res13 (& self) -> Res13R { Res13R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res13 (& mut self) -> Res13W < Res13Spec > { Res13W :: new (self , 0) } } # [doc = "RES13\n\nYou can [`read`](crate::Reg::read) this register and get [`res13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res13Spec ; impl crate :: RegisterSpec for Res13Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res13::R`](R) reader structure"]
impl crate :: Readable for Res13Spec { } # [doc = "`write(|w| ..)` method takes [`res13::W`](W) writer structure"]
impl crate :: Writable for Res13Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES13 to value 0"]
impl crate :: Resettable for Res13Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XIDAM (rw) register accessor: XIDAM\n\nYou can [`read`](crate::Reg::read) this register and get [`xidam::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xidam::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xidam`]
module"]
# [doc (alias = "XIDAM")]
pub type Xidam = crate :: Reg < xidam :: XidamSpec > ; # [doc = "XIDAM"]
pub mod xidam { # [doc = "Register `XIDAM` reader"]
pub type R = crate :: R < XidamSpec > ; # [doc = "Register `XIDAM` writer"]
pub type W = crate :: W < XidamSpec > ; # [doc = "Field `EIDM` reader - 28:0\\]
Extended ID Mask"]
pub type EidmR = crate :: FieldReader < u32 > ; # [doc = "Field `EIDM` writer - 28:0\\]
Extended ID Mask"]
pub type EidmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 29 , u32 > ; # [doc = "Field `NU39` reader - 31:29\\]
Reserved"]
pub type Nu39R = crate :: FieldReader ; # [doc = "Field `NU39` writer - 31:29\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:28 - 28:0\\]
Extended ID Mask"]
# [inline (always)]
pub fn eidm (& self) -> EidmR { EidmR :: new (self . bits & 0x1fff_ffff) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:28 - 28:0\\]
Extended ID Mask"]
# [inline (always)]
# [must_use]
pub fn eidm (& mut self) -> EidmW < XidamSpec > { EidmW :: new (self , 0) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < XidamSpec > { Nu39W :: new (self , 29) } } # [doc = "XIDAM\n\nYou can [`read`](crate::Reg::read) this register and get [`xidam::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xidam::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XidamSpec ; impl crate :: RegisterSpec for XidamSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xidam::R`](R) reader structure"]
impl crate :: Readable for XidamSpec { } # [doc = "`write(|w| ..)` method takes [`xidam::W`](W) writer structure"]
impl crate :: Writable for XidamSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XIDAM to value 0"]
impl crate :: Resettable for XidamSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HPMS (rw) register accessor: HPMS\n\nYou can [`read`](crate::Reg::read) this register and get [`hpms::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hpms::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpms`]
module"]
# [doc (alias = "HPMS")]
pub type Hpms = crate :: Reg < hpms :: HpmsSpec > ; # [doc = "HPMS"]
pub mod hpms { # [doc = "Register `HPMS` reader"]
pub type R = crate :: R < HpmsSpec > ; # [doc = "Register `HPMS` writer"]
pub type W = crate :: W < HpmsSpec > ; # [doc = "Field `BIDX` reader - 5:0\\]
Buffer Index"]
pub type BidxR = crate :: FieldReader ; # [doc = "Field `BIDX` writer - 5:0\\]
Buffer Index"]
pub type BidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `MSI` reader - 7:6\\]
Message Storeage Indicator"]
pub type MsiR = crate :: FieldReader ; # [doc = "Field `MSI` writer - 7:6\\]
Message Storeage Indicator"]
pub type MsiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FIDX` reader - 14:8\\]
Filter Index"]
pub type FidxR = crate :: FieldReader ; # [doc = "Field `FIDX` writer - 14:8\\]
Filter Index"]
pub type FidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `FLST` reader - 15:15\\]
Filter List"]
pub type FlstR = crate :: BitReader ; # [doc = "Field `FLST` writer - 15:15\\]
Filter List"]
pub type FlstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU40` reader - 31:16\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u16 > ; # [doc = "Field `NU40` writer - 31:16\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Buffer Index"]
# [inline (always)]
pub fn bidx (& self) -> BidxR { BidxR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Message Storeage Indicator"]
# [inline (always)]
pub fn msi (& self) -> MsiR { MsiR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:14 - 14:8\\]
Filter Index"]
# [inline (always)]
pub fn fidx (& self) -> FidxR { FidxR :: new (((self . bits >> 8) & 0x7f) as u8) } # [doc = "Bit 15 - 15:15\\]
Filter List"]
# [inline (always)]
pub fn flst (& self) -> FlstR { FlstR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Buffer Index"]
# [inline (always)]
# [must_use]
pub fn bidx (& mut self) -> BidxW < HpmsSpec > { BidxW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Message Storeage Indicator"]
# [inline (always)]
# [must_use]
pub fn msi (& mut self) -> MsiW < HpmsSpec > { MsiW :: new (self , 6) } # [doc = "Bits 8:14 - 14:8\\]
Filter Index"]
# [inline (always)]
# [must_use]
pub fn fidx (& mut self) -> FidxW < HpmsSpec > { FidxW :: new (self , 8) } # [doc = "Bit 15 - 15:15\\]
Filter List"]
# [inline (always)]
# [must_use]
pub fn flst (& mut self) -> FlstW < HpmsSpec > { FlstW :: new (self , 15) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < HpmsSpec > { Nu40W :: new (self , 16) } } # [doc = "HPMS\n\nYou can [`read`](crate::Reg::read) this register and get [`hpms::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hpms::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HpmsSpec ; impl crate :: RegisterSpec for HpmsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hpms::R`](R) reader structure"]
impl crate :: Readable for HpmsSpec { } # [doc = "`write(|w| ..)` method takes [`hpms::W`](W) writer structure"]
impl crate :: Writable for HpmsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HPMS to value 0"]
impl crate :: Resettable for HpmsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "NDAT1 (rw) register accessor: NDAT1\n\nYou can [`read`](crate::Reg::read) this register and get [`ndat1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ndat1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ndat1`]
module"]
# [doc (alias = "NDAT1")]
pub type Ndat1 = crate :: Reg < ndat1 :: Ndat1Spec > ; # [doc = "NDAT1"]
pub mod ndat1 { # [doc = "Register `NDAT1` reader"]
pub type R = crate :: R < Ndat1Spec > ; # [doc = "Register `NDAT1` writer"]
pub type W = crate :: W < Ndat1Spec > ; # [doc = "Field `ND0_31` reader - 31:0\\]
New Data 0-31"]
pub type Nd0_31R = crate :: FieldReader < u32 > ; # [doc = "Field `ND0_31` writer - 31:0\\]
New Data 0-31"]
pub type Nd0_31W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
New Data 0-31"]
# [inline (always)]
pub fn nd0_31 (& self) -> Nd0_31R { Nd0_31R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
New Data 0-31"]
# [inline (always)]
# [must_use]
pub fn nd0_31 (& mut self) -> Nd0_31W < Ndat1Spec > { Nd0_31W :: new (self , 0) } } # [doc = "NDAT1\n\nYou can [`read`](crate::Reg::read) this register and get [`ndat1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ndat1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ndat1Spec ; impl crate :: RegisterSpec for Ndat1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ndat1::R`](R) reader structure"]
impl crate :: Readable for Ndat1Spec { } # [doc = "`write(|w| ..)` method takes [`ndat1::W`](W) writer structure"]
impl crate :: Writable for Ndat1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets NDAT1 to value 0"]
impl crate :: Resettable for Ndat1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "NDAT2 (rw) register accessor: NDAT2\n\nYou can [`read`](crate::Reg::read) this register and get [`ndat2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ndat2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ndat2`]
module"]
# [doc (alias = "NDAT2")]
pub type Ndat2 = crate :: Reg < ndat2 :: Ndat2Spec > ; # [doc = "NDAT2"]
pub mod ndat2 { # [doc = "Register `NDAT2` reader"]
pub type R = crate :: R < Ndat2Spec > ; # [doc = "Register `NDAT2` writer"]
pub type W = crate :: W < Ndat2Spec > ; # [doc = "Field `ND32_63` reader - 31:0\\]
New Data 32-63"]
pub type Nd32_63R = crate :: FieldReader < u32 > ; # [doc = "Field `ND32_63` writer - 31:0\\]
New Data 32-63"]
pub type Nd32_63W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
New Data 32-63"]
# [inline (always)]
pub fn nd32_63 (& self) -> Nd32_63R { Nd32_63R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
New Data 32-63"]
# [inline (always)]
# [must_use]
pub fn nd32_63 (& mut self) -> Nd32_63W < Ndat2Spec > { Nd32_63W :: new (self , 0) } } # [doc = "NDAT2\n\nYou can [`read`](crate::Reg::read) this register and get [`ndat2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ndat2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ndat2Spec ; impl crate :: RegisterSpec for Ndat2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ndat2::R`](R) reader structure"]
impl crate :: Readable for Ndat2Spec { } # [doc = "`write(|w| ..)` method takes [`ndat2::W`](W) writer structure"]
impl crate :: Writable for Ndat2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets NDAT2 to value 0"]
impl crate :: Resettable for Ndat2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXF0C (rw) register accessor: RXF0C\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf0c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf0c`]
module"]
# [doc (alias = "RXF0C")]
pub type Rxf0c = crate :: Reg < rxf0c :: Rxf0cSpec > ; # [doc = "RXF0C"]
pub mod rxf0c { # [doc = "Register `RXF0C` reader"]
pub type R = crate :: R < Rxf0cSpec > ; # [doc = "Register `RXF0C` writer"]
pub type W = crate :: W < Rxf0cSpec > ; # [doc = "Field `NU41` reader - 1:0\\]
Reserved"]
pub type Nu41R = crate :: FieldReader ; # [doc = "Field `NU41` writer - 1:0\\]
Reserved"]
pub type Nu41W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `F0SA` reader - 14:2\\]
Rx FIFO 0 Start Address"]
pub type F0saR = crate :: FieldReader < u16 > ; # [doc = "Field `F0SA` writer - 14:2\\]
Rx FIFO 0 Start Address"]
pub type F0saW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `NU42` reader - 15:15\\]
Reserved"]
pub type Nu42R = crate :: BitReader ; # [doc = "Field `NU42` writer - 15:15\\]
Reserved"]
pub type Nu42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F0S` reader - 22:16\\]
Rx FIFO 0 Size"]
pub type F0sR = crate :: FieldReader ; # [doc = "Field `F0S` writer - 22:16\\]
Rx FIFO 0 Size"]
pub type F0sW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU42_1` reader - 23:23\\]
Reserved"]
pub type Nu42_1R = crate :: BitReader ; # [doc = "Field `NU42_1` writer - 23:23\\]
Reserved"]
pub type Nu42_1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F0WM` reader - 30:24\\]
Rx FIFO 0 Watermark"]
pub type F0wmR = crate :: FieldReader ; # [doc = "Field `F0WM` writer - 30:24\\]
Rx FIFO 0 Watermark"]
pub type F0wmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `F0OM` reader - 31:31\\]
Rx FIFO 0 Operation Mode"]
pub type F0omR = crate :: BitReader ; # [doc = "Field `F0OM` writer - 31:31\\]
Rx FIFO 0 Operation Mode"]
pub type F0omW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu41 (& self) -> Nu41R { Nu41R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:14 - 14:2\\]
Rx FIFO 0 Start Address"]
# [inline (always)]
pub fn f0sa (& self) -> F0saR { F0saR :: new (((self . bits >> 2) & 0x1fff) as u16) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
pub fn nu42 (& self) -> Nu42R { Nu42R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:22 - 22:16\\]
Rx FIFO 0 Size"]
# [inline (always)]
pub fn f0s (& self) -> F0sR { F0sR :: new (((self . bits >> 16) & 0x7f) as u8) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
pub fn nu42_1 (& self) -> Nu42_1R { Nu42_1R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:30 - 30:24\\]
Rx FIFO 0 Watermark"]
# [inline (always)]
pub fn f0wm (& self) -> F0wmR { F0wmR :: new (((self . bits >> 24) & 0x7f) as u8) } # [doc = "Bit 31 - 31:31\\]
Rx FIFO 0 Operation Mode"]
# [inline (always)]
pub fn f0om (& self) -> F0omR { F0omR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu41 (& mut self) -> Nu41W < Rxf0cSpec > { Nu41W :: new (self , 0) } # [doc = "Bits 2:14 - 14:2\\]
Rx FIFO 0 Start Address"]
# [inline (always)]
# [must_use]
pub fn f0sa (& mut self) -> F0saW < Rxf0cSpec > { F0saW :: new (self , 2) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu42 (& mut self) -> Nu42W < Rxf0cSpec > { Nu42W :: new (self , 15) } # [doc = "Bits 16:22 - 22:16\\]
Rx FIFO 0 Size"]
# [inline (always)]
# [must_use]
pub fn f0s (& mut self) -> F0sW < Rxf0cSpec > { F0sW :: new (self , 16) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu42_1 (& mut self) -> Nu42_1W < Rxf0cSpec > { Nu42_1W :: new (self , 23) } # [doc = "Bits 24:30 - 30:24\\]
Rx FIFO 0 Watermark"]
# [inline (always)]
# [must_use]
pub fn f0wm (& mut self) -> F0wmW < Rxf0cSpec > { F0wmW :: new (self , 24) } # [doc = "Bit 31 - 31:31\\]
Rx FIFO 0 Operation Mode"]
# [inline (always)]
# [must_use]
pub fn f0om (& mut self) -> F0omW < Rxf0cSpec > { F0omW :: new (self , 31) } } # [doc = "RXF0C\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf0c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rxf0cSpec ; impl crate :: RegisterSpec for Rxf0cSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxf0c::R`](R) reader structure"]
impl crate :: Readable for Rxf0cSpec { } # [doc = "`write(|w| ..)` method takes [`rxf0c::W`](W) writer structure"]
impl crate :: Writable for Rxf0cSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXF0C to value 0"]
impl crate :: Resettable for Rxf0cSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXF0S (rw) register accessor: RXF0S\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf0s::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0s::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf0s`]
module"]
# [doc (alias = "RXF0S")]
pub type Rxf0s = crate :: Reg < rxf0s :: Rxf0sSpec > ; # [doc = "RXF0S"]
pub mod rxf0s { # [doc = "Register `RXF0S` reader"]
pub type R = crate :: R < Rxf0sSpec > ; # [doc = "Register `RXF0S` writer"]
pub type W = crate :: W < Rxf0sSpec > ; # [doc = "Field `F0FL` reader - 6:0\\]
Rx FIFO 0 Fill Level"]
pub type F0flR = crate :: FieldReader ; # [doc = "Field `F0FL` writer - 6:0\\]
Rx FIFO 0 Fill Level"]
pub type F0flW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU43` reader - 7:7\\]
Reserved"]
pub type Nu43R = crate :: BitReader ; # [doc = "Field `NU43` writer - 7:7\\]
Reserved"]
pub type Nu43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F0GI` reader - 13:8\\]
Rx FIFO 0 Get Index"]
pub type F0giR = crate :: FieldReader ; # [doc = "Field `F0GI` writer - 13:8\\]
Rx FIFO 0 Get Index"]
pub type F0giW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU44` reader - 15:14\\]
Reserved"]
pub type Nu44R = crate :: FieldReader ; # [doc = "Field `NU44` writer - 15:14\\]
Reserved"]
pub type Nu44W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `F0PI` reader - 21:16\\]
Rx FIFO 0 Put Index"]
pub type F0piR = crate :: FieldReader ; # [doc = "Field `F0PI` writer - 21:16\\]
Rx FIFO 0 Put Index"]
pub type F0piW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU45` reader - 23:22\\]
Reserved"]
pub type Nu45R = crate :: FieldReader ; # [doc = "Field `NU45` writer - 23:22\\]
Reserved"]
pub type Nu45W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `F0F` reader - 24:24\\]
Rx FIFO 0 Full"]
pub type F0fR = crate :: BitReader ; # [doc = "Field `F0F` writer - 24:24\\]
Rx FIFO 0 Full"]
pub type F0fW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF0L` reader - 25:25\\]
Rx FIFO 0 Message Lost"]
pub type Rf0lR = crate :: BitReader ; # [doc = "Field `RF0L` writer - 25:25\\]
Rx FIFO 0 Message Lost"]
pub type Rf0lW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU46` reader - 31:26\\]
Reserved"]
pub type Nu46R = crate :: FieldReader ; # [doc = "Field `NU46` writer - 31:26\\]
Reserved"]
pub type Nu46W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:6 - 6:0\\]
Rx FIFO 0 Fill Level"]
# [inline (always)]
pub fn f0fl (& self) -> F0flR { F0flR :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
pub fn nu43 (& self) -> Nu43R { Nu43R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:13 - 13:8\\]
Rx FIFO 0 Get Index"]
# [inline (always)]
pub fn f0gi (& self) -> F0giR { F0giR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
pub fn nu44 (& self) -> Nu44R { Nu44R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:21 - 21:16\\]
Rx FIFO 0 Put Index"]
# [inline (always)]
pub fn f0pi (& self) -> F0piR { F0piR :: new (((self . bits >> 16) & 0x3f) as u8) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
pub fn nu45 (& self) -> Nu45R { Nu45R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bit 24 - 24:24\\]
Rx FIFO 0 Full"]
# [inline (always)]
pub fn f0f (& self) -> F0fR { F0fR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Rx FIFO 0 Message Lost"]
# [inline (always)]
pub fn rf0l (& self) -> Rf0lR { Rf0lR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn nu46 (& self) -> Nu46R { Nu46R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:6 - 6:0\\]
Rx FIFO 0 Fill Level"]
# [inline (always)]
# [must_use]
pub fn f0fl (& mut self) -> F0flW < Rxf0sSpec > { F0flW :: new (self , 0) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu43 (& mut self) -> Nu43W < Rxf0sSpec > { Nu43W :: new (self , 7) } # [doc = "Bits 8:13 - 13:8\\]
Rx FIFO 0 Get Index"]
# [inline (always)]
# [must_use]
pub fn f0gi (& mut self) -> F0giW < Rxf0sSpec > { F0giW :: new (self , 8) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu44 (& mut self) -> Nu44W < Rxf0sSpec > { Nu44W :: new (self , 14) } # [doc = "Bits 16:21 - 21:16\\]
Rx FIFO 0 Put Index"]
# [inline (always)]
# [must_use]
pub fn f0pi (& mut self) -> F0piW < Rxf0sSpec > { F0piW :: new (self , 16) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu45 (& mut self) -> Nu45W < Rxf0sSpec > { Nu45W :: new (self , 22) } # [doc = "Bit 24 - 24:24\\]
Rx FIFO 0 Full"]
# [inline (always)]
# [must_use]
pub fn f0f (& mut self) -> F0fW < Rxf0sSpec > { F0fW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Rx FIFO 0 Message Lost"]
# [inline (always)]
# [must_use]
pub fn rf0l (& mut self) -> Rf0lW < Rxf0sSpec > { Rf0lW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu46 (& mut self) -> Nu46W < Rxf0sSpec > { Nu46W :: new (self , 26) } } # [doc = "RXF0S\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf0s::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0s::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rxf0sSpec ; impl crate :: RegisterSpec for Rxf0sSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxf0s::R`](R) reader structure"]
impl crate :: Readable for Rxf0sSpec { } # [doc = "`write(|w| ..)` method takes [`rxf0s::W`](W) writer structure"]
impl crate :: Writable for Rxf0sSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXF0S to value 0"]
impl crate :: Resettable for Rxf0sSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXF0A (rw) register accessor: RXF0A\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf0a`]
module"]
# [doc (alias = "RXF0A")]
pub type Rxf0a = crate :: Reg < rxf0a :: Rxf0aSpec > ; # [doc = "RXF0A"]
pub mod rxf0a { # [doc = "Register `RXF0A` reader"]
pub type R = crate :: R < Rxf0aSpec > ; # [doc = "Register `RXF0A` writer"]
pub type W = crate :: W < Rxf0aSpec > ; # [doc = "Field `F0AI` reader - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
pub type F0aiR = crate :: FieldReader ; # [doc = "Field `F0AI` writer - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
pub type F0aiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU47` reader - 31:6\\]
Reserved"]
pub type Nu47R = crate :: FieldReader < u32 > ; # [doc = "Field `NU47` writer - 31:6\\]
Reserved"]
pub type Nu47W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
# [inline (always)]
pub fn f0ai (& self) -> F0aiR { F0aiR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu47 (& self) -> Nu47R { Nu47R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
# [inline (always)]
# [must_use]
pub fn f0ai (& mut self) -> F0aiW < Rxf0aSpec > { F0aiW :: new (self , 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu47 (& mut self) -> Nu47W < Rxf0aSpec > { Nu47W :: new (self , 6) } } # [doc = "RXF0A\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rxf0aSpec ; impl crate :: RegisterSpec for Rxf0aSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxf0a::R`](R) reader structure"]
impl crate :: Readable for Rxf0aSpec { } # [doc = "`write(|w| ..)` method takes [`rxf0a::W`](W) writer structure"]
impl crate :: Writable for Rxf0aSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXF0A to value 0"]
impl crate :: Resettable for Rxf0aSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXBC (rw) register accessor: RXBC\n\nYou can [`read`](crate::Reg::read) this register and get [`rxbc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxbc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxbc`]
module"]
# [doc (alias = "RXBC")]
pub type Rxbc = crate :: Reg < rxbc :: RxbcSpec > ; # [doc = "RXBC"]
pub mod rxbc { # [doc = "Register `RXBC` reader"]
pub type R = crate :: R < RxbcSpec > ; # [doc = "Register `RXBC` writer"]
pub type W = crate :: W < RxbcSpec > ; # [doc = "Field `NU48` reader - 1:0\\]
Reserved"]
pub type Nu48R = crate :: FieldReader ; # [doc = "Field `NU48` writer - 1:0\\]
Reserved"]
pub type Nu48W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RBSA` reader - 15:2\\]
Rx Buffer Start Address"]
pub type RbsaR = crate :: FieldReader < u16 > ; # [doc = "Field `RBSA` writer - 15:2\\]
Rx Buffer Start Address"]
pub type RbsaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `NU49` reader - 31:16\\]
Reserved"]
pub type Nu49R = crate :: FieldReader < u16 > ; # [doc = "Field `NU49` writer - 31:16\\]
Reserved"]
pub type Nu49W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu48 (& self) -> Nu48R { Nu48R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:15 - 15:2\\]
Rx Buffer Start Address"]
# [inline (always)]
pub fn rbsa (& self) -> RbsaR { RbsaR :: new (((self . bits >> 2) & 0x3fff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu49 (& self) -> Nu49R { Nu49R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu48 (& mut self) -> Nu48W < RxbcSpec > { Nu48W :: new (self , 0) } # [doc = "Bits 2:15 - 15:2\\]
Rx Buffer Start Address"]
# [inline (always)]
# [must_use]
pub fn rbsa (& mut self) -> RbsaW < RxbcSpec > { RbsaW :: new (self , 2) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu49 (& mut self) -> Nu49W < RxbcSpec > { Nu49W :: new (self , 16) } } # [doc = "RXBC\n\nYou can [`read`](crate::Reg::read) this register and get [`rxbc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxbc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxbcSpec ; impl crate :: RegisterSpec for RxbcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxbc::R`](R) reader structure"]
impl crate :: Readable for RxbcSpec { } # [doc = "`write(|w| ..)` method takes [`rxbc::W`](W) writer structure"]
impl crate :: Writable for RxbcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXBC to value 0"]
impl crate :: Resettable for RxbcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXF1C (rw) register accessor: RXF1C\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf1c`]
module"]
# [doc (alias = "RXF1C")]
pub type Rxf1c = crate :: Reg < rxf1c :: Rxf1cSpec > ; # [doc = "RXF1C"]
pub mod rxf1c { # [doc = "Register `RXF1C` reader"]
pub type R = crate :: R < Rxf1cSpec > ; # [doc = "Register `RXF1C` writer"]
pub type W = crate :: W < Rxf1cSpec > ; # [doc = "Field `NU499` reader - 1:0\\]
Reserved"]
pub type Nu499R = crate :: FieldReader ; # [doc = "Field `NU499` writer - 1:0\\]
Reserved"]
pub type Nu499W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `F1SA` reader - 14:2\\]
Rx FIFO 0 Start Address"]
pub type F1saR = crate :: FieldReader < u16 > ; # [doc = "Field `F1SA` writer - 14:2\\]
Rx FIFO 0 Start Address"]
pub type F1saW < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `NU50` reader - 15:15\\]
Reserved"]
pub type Nu50R = crate :: BitReader ; # [doc = "Field `NU50` writer - 15:15\\]
Reserved"]
pub type Nu50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F1S` reader - 22:16\\]
Rx FIFO 0 Size"]
pub type F1sR = crate :: FieldReader ; # [doc = "Field `F1S` writer - 22:16\\]
Rx FIFO 0 Size"]
pub type F1sW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU50_1` reader - 23:23\\]
Reserved"]
pub type Nu50_1R = crate :: BitReader ; # [doc = "Field `NU50_1` writer - 23:23\\]
Reserved"]
pub type Nu50_1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F1WM` reader - 30:24\\]
Rx FIFO 0 Watermark"]
pub type F1wmR = crate :: FieldReader ; # [doc = "Field `F1WM` writer - 30:24\\]
Rx FIFO 0 Watermark"]
pub type F1wmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `F1OM` reader - 31:31\\]
Rx FIFO 0 Operation Mode"]
pub type F1omR = crate :: BitReader ; # [doc = "Field `F1OM` writer - 31:31\\]
Rx FIFO 0 Operation Mode"]
pub type F1omW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu499 (& self) -> Nu499R { Nu499R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:14 - 14:2\\]
Rx FIFO 0 Start Address"]
# [inline (always)]
pub fn f1sa (& self) -> F1saR { F1saR :: new (((self . bits >> 2) & 0x1fff) as u16) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
pub fn nu50 (& self) -> Nu50R { Nu50R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:22 - 22:16\\]
Rx FIFO 0 Size"]
# [inline (always)]
pub fn f1s (& self) -> F1sR { F1sR :: new (((self . bits >> 16) & 0x7f) as u8) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
pub fn nu50_1 (& self) -> Nu50_1R { Nu50_1R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:30 - 30:24\\]
Rx FIFO 0 Watermark"]
# [inline (always)]
pub fn f1wm (& self) -> F1wmR { F1wmR :: new (((self . bits >> 24) & 0x7f) as u8) } # [doc = "Bit 31 - 31:31\\]
Rx FIFO 0 Operation Mode"]
# [inline (always)]
pub fn f1om (& self) -> F1omR { F1omR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu499 (& mut self) -> Nu499W < Rxf1cSpec > { Nu499W :: new (self , 0) } # [doc = "Bits 2:14 - 14:2\\]
Rx FIFO 0 Start Address"]
# [inline (always)]
# [must_use]
pub fn f1sa (& mut self) -> F1saW < Rxf1cSpec > { F1saW :: new (self , 2) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu50 (& mut self) -> Nu50W < Rxf1cSpec > { Nu50W :: new (self , 15) } # [doc = "Bits 16:22 - 22:16\\]
Rx FIFO 0 Size"]
# [inline (always)]
# [must_use]
pub fn f1s (& mut self) -> F1sW < Rxf1cSpec > { F1sW :: new (self , 16) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu50_1 (& mut self) -> Nu50_1W < Rxf1cSpec > { Nu50_1W :: new (self , 23) } # [doc = "Bits 24:30 - 30:24\\]
Rx FIFO 0 Watermark"]
# [inline (always)]
# [must_use]
pub fn f1wm (& mut self) -> F1wmW < Rxf1cSpec > { F1wmW :: new (self , 24) } # [doc = "Bit 31 - 31:31\\]
Rx FIFO 0 Operation Mode"]
# [inline (always)]
# [must_use]
pub fn f1om (& mut self) -> F1omW < Rxf1cSpec > { F1omW :: new (self , 31) } } # [doc = "RXF1C\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rxf1cSpec ; impl crate :: RegisterSpec for Rxf1cSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxf1c::R`](R) reader structure"]
impl crate :: Readable for Rxf1cSpec { } # [doc = "`write(|w| ..)` method takes [`rxf1c::W`](W) writer structure"]
impl crate :: Writable for Rxf1cSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXF1C to value 0"]
impl crate :: Resettable for Rxf1cSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXF1S (rw) register accessor: RXF1S\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf1s::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1s::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf1s`]
module"]
# [doc (alias = "RXF1S")]
pub type Rxf1s = crate :: Reg < rxf1s :: Rxf1sSpec > ; # [doc = "RXF1S"]
pub mod rxf1s { # [doc = "Register `RXF1S` reader"]
pub type R = crate :: R < Rxf1sSpec > ; # [doc = "Register `RXF1S` writer"]
pub type W = crate :: W < Rxf1sSpec > ; # [doc = "Field `F1FL` reader - 6:0\\]
Rx FIFO 0 Fill Level"]
pub type F1flR = crate :: FieldReader ; # [doc = "Field `F1FL` writer - 6:0\\]
Rx FIFO 0 Fill Level"]
pub type F1flW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU51` reader - 7:7\\]
Reserved"]
pub type Nu51R = crate :: BitReader ; # [doc = "Field `NU51` writer - 7:7\\]
Reserved"]
pub type Nu51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F1GI` reader - 13:8\\]
Rx FIFO 0 Get Index"]
pub type F1giR = crate :: FieldReader ; # [doc = "Field `F1GI` writer - 13:8\\]
Rx FIFO 0 Get Index"]
pub type F1giW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU52` reader - 15:14\\]
Reserved"]
pub type Nu52R = crate :: FieldReader ; # [doc = "Field `NU52` writer - 15:14\\]
Reserved"]
pub type Nu52W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `F1PI` reader - 21:16\\]
Rx FIFO 0 Put Index"]
pub type F1piR = crate :: FieldReader ; # [doc = "Field `F1PI` writer - 21:16\\]
Rx FIFO 0 Put Index"]
pub type F1piW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU53` reader - 23:22\\]
Reserved"]
pub type Nu53R = crate :: FieldReader ; # [doc = "Field `NU53` writer - 23:22\\]
Reserved"]
pub type Nu53W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `F1F` reader - 24:24\\]
Rx FIFO 0 Full"]
pub type F1fR = crate :: BitReader ; # [doc = "Field `F1F` writer - 24:24\\]
Rx FIFO 0 Full"]
pub type F1fW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RF1L` reader - 25:25\\]
Rx FIFO 0 Message Lost"]
pub type Rf1lR = crate :: BitReader ; # [doc = "Field `RF1L` writer - 25:25\\]
Rx FIFO 0 Message Lost"]
pub type Rf1lW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU54` reader - 31:26\\]
Reserved"]
pub type Nu54R = crate :: FieldReader ; # [doc = "Field `NU54` writer - 31:26\\]
Reserved"]
pub type Nu54W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:6 - 6:0\\]
Rx FIFO 0 Fill Level"]
# [inline (always)]
pub fn f1fl (& self) -> F1flR { F1flR :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
pub fn nu51 (& self) -> Nu51R { Nu51R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:13 - 13:8\\]
Rx FIFO 0 Get Index"]
# [inline (always)]
pub fn f1gi (& self) -> F1giR { F1giR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
pub fn nu52 (& self) -> Nu52R { Nu52R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:21 - 21:16\\]
Rx FIFO 0 Put Index"]
# [inline (always)]
pub fn f1pi (& self) -> F1piR { F1piR :: new (((self . bits >> 16) & 0x3f) as u8) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
pub fn nu53 (& self) -> Nu53R { Nu53R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bit 24 - 24:24\\]
Rx FIFO 0 Full"]
# [inline (always)]
pub fn f1f (& self) -> F1fR { F1fR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Rx FIFO 0 Message Lost"]
# [inline (always)]
pub fn rf1l (& self) -> Rf1lR { Rf1lR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn nu54 (& self) -> Nu54R { Nu54R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:6 - 6:0\\]
Rx FIFO 0 Fill Level"]
# [inline (always)]
# [must_use]
pub fn f1fl (& mut self) -> F1flW < Rxf1sSpec > { F1flW :: new (self , 0) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu51 (& mut self) -> Nu51W < Rxf1sSpec > { Nu51W :: new (self , 7) } # [doc = "Bits 8:13 - 13:8\\]
Rx FIFO 0 Get Index"]
# [inline (always)]
# [must_use]
pub fn f1gi (& mut self) -> F1giW < Rxf1sSpec > { F1giW :: new (self , 8) } # [doc = "Bits 14:15 - 15:14\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu52 (& mut self) -> Nu52W < Rxf1sSpec > { Nu52W :: new (self , 14) } # [doc = "Bits 16:21 - 21:16\\]
Rx FIFO 0 Put Index"]
# [inline (always)]
# [must_use]
pub fn f1pi (& mut self) -> F1piW < Rxf1sSpec > { F1piW :: new (self , 16) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu53 (& mut self) -> Nu53W < Rxf1sSpec > { Nu53W :: new (self , 22) } # [doc = "Bit 24 - 24:24\\]
Rx FIFO 0 Full"]
# [inline (always)]
# [must_use]
pub fn f1f (& mut self) -> F1fW < Rxf1sSpec > { F1fW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Rx FIFO 0 Message Lost"]
# [inline (always)]
# [must_use]
pub fn rf1l (& mut self) -> Rf1lW < Rxf1sSpec > { Rf1lW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu54 (& mut self) -> Nu54W < Rxf1sSpec > { Nu54W :: new (self , 26) } } # [doc = "RXF1S\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf1s::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1s::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rxf1sSpec ; impl crate :: RegisterSpec for Rxf1sSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxf1s::R`](R) reader structure"]
impl crate :: Readable for Rxf1sSpec { } # [doc = "`write(|w| ..)` method takes [`rxf1s::W`](W) writer structure"]
impl crate :: Writable for Rxf1sSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXF1S to value 0"]
impl crate :: Resettable for Rxf1sSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXF1A (rw) register accessor: RXF1A\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf1a`]
module"]
# [doc (alias = "RXF1A")]
pub type Rxf1a = crate :: Reg < rxf1a :: Rxf1aSpec > ; # [doc = "RXF1A"]
pub mod rxf1a { # [doc = "Register `RXF1A` reader"]
pub type R = crate :: R < Rxf1aSpec > ; # [doc = "Register `RXF1A` writer"]
pub type W = crate :: W < Rxf1aSpec > ; # [doc = "Field `F1AI` reader - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
pub type F1aiR = crate :: FieldReader ; # [doc = "Field `F1AI` writer - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
pub type F1aiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU55` reader - 31:6\\]
Reserved"]
pub type Nu55R = crate :: FieldReader < u32 > ; # [doc = "Field `NU55` writer - 31:6\\]
Reserved"]
pub type Nu55W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
# [inline (always)]
pub fn f1ai (& self) -> F1aiR { F1aiR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu55 (& self) -> Nu55R { Nu55R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Rx FIFO 0 Acknowledge Index"]
# [inline (always)]
# [must_use]
pub fn f1ai (& mut self) -> F1aiW < Rxf1aSpec > { F1aiW :: new (self , 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu55 (& mut self) -> Nu55W < Rxf1aSpec > { Nu55W :: new (self , 6) } } # [doc = "RXF1A\n\nYou can [`read`](crate::Reg::read) this register and get [`rxf1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rxf1aSpec ; impl crate :: RegisterSpec for Rxf1aSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxf1a::R`](R) reader structure"]
impl crate :: Readable for Rxf1aSpec { } # [doc = "`write(|w| ..)` method takes [`rxf1a::W`](W) writer structure"]
impl crate :: Writable for Rxf1aSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXF1A to value 0"]
impl crate :: Resettable for Rxf1aSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RXESC (rw) register accessor: RXESC\n\nYou can [`read`](crate::Reg::read) this register and get [`rxesc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxesc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxesc`]
module"]
# [doc (alias = "RXESC")]
pub type Rxesc = crate :: Reg < rxesc :: RxescSpec > ; # [doc = "RXESC"]
pub mod rxesc { # [doc = "Register `RXESC` reader"]
pub type R = crate :: R < RxescSpec > ; # [doc = "Register `RXESC` writer"]
pub type W = crate :: W < RxescSpec > ; # [doc = "Field `F0DS` reader - 2:0\\]
Rx FIFO 0 Data Field Size"]
pub type F0dsR = crate :: FieldReader ; # [doc = "Field `F0DS` writer - 2:0\\]
Rx FIFO 0 Data Field Size"]
pub type F0dsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU56` reader - 3:3\\]
Reserved"]
pub type Nu56R = crate :: BitReader ; # [doc = "Field `NU56` writer - 3:3\\]
Reserved"]
pub type Nu56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F1DS` reader - 6:4\\]
Rx FIFO 1 Data Field Size"]
pub type F1dsR = crate :: FieldReader ; # [doc = "Field `F1DS` writer - 6:4\\]
Rx FIFO 1 Data Field Size"]
pub type F1dsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU57` reader - 7:7\\]
Reserved"]
pub type Nu57R = crate :: BitReader ; # [doc = "Field `NU57` writer - 7:7\\]
Reserved"]
pub type Nu57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RBDS` reader - 10:8\\]
Rx Buffer data Field Size"]
pub type RbdsR = crate :: FieldReader ; # [doc = "Field `RBDS` writer - 10:8\\]
Rx Buffer data Field Size"]
pub type RbdsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU58` reader - 31:11\\]
Reserved"]
pub type Nu58R = crate :: FieldReader < u32 > ; # [doc = "Field `NU58` writer - 31:11\\]
Reserved"]
pub type Nu58W < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Rx FIFO 0 Data Field Size"]
# [inline (always)]
pub fn f0ds (& self) -> F0dsR { F0dsR :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
Reserved"]
# [inline (always)]
pub fn nu56 (& self) -> Nu56R { Nu56R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Rx FIFO 1 Data Field Size"]
# [inline (always)]
pub fn f1ds (& self) -> F1dsR { F1dsR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
pub fn nu57 (& self) -> Nu57R { Nu57R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
Rx Buffer data Field Size"]
# [inline (always)]
pub fn rbds (& self) -> RbdsR { RbdsR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu58 (& self) -> Nu58R { Nu58R :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Rx FIFO 0 Data Field Size"]
# [inline (always)]
# [must_use]
pub fn f0ds (& mut self) -> F0dsW < RxescSpec > { F0dsW :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu56 (& mut self) -> Nu56W < RxescSpec > { Nu56W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Rx FIFO 1 Data Field Size"]
# [inline (always)]
# [must_use]
pub fn f1ds (& mut self) -> F1dsW < RxescSpec > { F1dsW :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu57 (& mut self) -> Nu57W < RxescSpec > { Nu57W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
Rx Buffer data Field Size"]
# [inline (always)]
# [must_use]
pub fn rbds (& mut self) -> RbdsW < RxescSpec > { RbdsW :: new (self , 8) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu58 (& mut self) -> Nu58W < RxescSpec > { Nu58W :: new (self , 11) } } # [doc = "RXESC\n\nYou can [`read`](crate::Reg::read) this register and get [`rxesc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxesc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxescSpec ; impl crate :: RegisterSpec for RxescSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rxesc::R`](R) reader structure"]
impl crate :: Readable for RxescSpec { } # [doc = "`write(|w| ..)` method takes [`rxesc::W`](W) writer structure"]
impl crate :: Writable for RxescSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RXESC to value 0"]
impl crate :: Resettable for RxescSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBC (rw) register accessor: TXBC\n\nYou can [`read`](crate::Reg::read) this register and get [`txbc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbc`]
module"]
# [doc (alias = "TXBC")]
pub type Txbc = crate :: Reg < txbc :: TxbcSpec > ; # [doc = "TXBC"]
pub mod txbc { # [doc = "Register `TXBC` reader"]
pub type R = crate :: R < TxbcSpec > ; # [doc = "Register `TXBC` writer"]
pub type W = crate :: W < TxbcSpec > ; # [doc = "Field `NU59` reader - 1:0\\]
Reserved"]
pub type Nu59R = crate :: FieldReader ; # [doc = "Field `NU59` writer - 1:0\\]
Reserved"]
pub type Nu59W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TBSA` reader - 15:2\\]
Tx Buffers Start Address"]
pub type TbsaR = crate :: FieldReader < u16 > ; # [doc = "Field `TBSA` writer - 15:2\\]
Tx Buffers Start Address"]
pub type TbsaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `NDTB` reader - 21:16\\]
Number of Dedicated Transmit Buffers"]
pub type NdtbR = crate :: FieldReader ; # [doc = "Field `NDTB` writer - 21:16\\]
Number of Dedicated Transmit Buffers"]
pub type NdtbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU60` reader - 23:22\\]
Reserved"]
pub type Nu60R = crate :: FieldReader ; # [doc = "Field `NU60` writer - 23:22\\]
Reserved"]
pub type Nu60W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TFQS` reader - 29:24\\]
Transmit FIFO/Queue Size"]
pub type TfqsR = crate :: FieldReader ; # [doc = "Field `TFQS` writer - 29:24\\]
Transmit FIFO/Queue Size"]
pub type TfqsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TFQM` reader - 30:30\\]
Tx FIFO/Queue Mode"]
pub type TfqmR = crate :: BitReader ; # [doc = "Field `TFQM` writer - 30:30\\]
Tx FIFO/Queue Mode"]
pub type TfqmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU61` reader - 31:31\\]
Reserved"]
pub type Nu61R = crate :: BitReader ; # [doc = "Field `NU61` writer - 31:31\\]
Reserved"]
pub type Nu61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu59 (& self) -> Nu59R { Nu59R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:15 - 15:2\\]
Tx Buffers Start Address"]
# [inline (always)]
pub fn tbsa (& self) -> TbsaR { TbsaR :: new (((self . bits >> 2) & 0x3fff) as u16) } # [doc = "Bits 16:21 - 21:16\\]
Number of Dedicated Transmit Buffers"]
# [inline (always)]
pub fn ndtb (& self) -> NdtbR { NdtbR :: new (((self . bits >> 16) & 0x3f) as u8) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
pub fn nu60 (& self) -> Nu60R { Nu60R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:29 - 29:24\\]
Transmit FIFO/Queue Size"]
# [inline (always)]
pub fn tfqs (& self) -> TfqsR { TfqsR :: new (((self . bits >> 24) & 0x3f) as u8) } # [doc = "Bit 30 - 30:30\\]
Tx FIFO/Queue Mode"]
# [inline (always)]
pub fn tfqm (& self) -> TfqmR { TfqmR :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Reserved"]
# [inline (always)]
pub fn nu61 (& self) -> Nu61R { Nu61R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu59 (& mut self) -> Nu59W < TxbcSpec > { Nu59W :: new (self , 0) } # [doc = "Bits 2:15 - 15:2\\]
Tx Buffers Start Address"]
# [inline (always)]
# [must_use]
pub fn tbsa (& mut self) -> TbsaW < TxbcSpec > { TbsaW :: new (self , 2) } # [doc = "Bits 16:21 - 21:16\\]
Number of Dedicated Transmit Buffers"]
# [inline (always)]
# [must_use]
pub fn ndtb (& mut self) -> NdtbW < TxbcSpec > { NdtbW :: new (self , 16) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu60 (& mut self) -> Nu60W < TxbcSpec > { Nu60W :: new (self , 22) } # [doc = "Bits 24:29 - 29:24\\]
Transmit FIFO/Queue Size"]
# [inline (always)]
# [must_use]
pub fn tfqs (& mut self) -> TfqsW < TxbcSpec > { TfqsW :: new (self , 24) } # [doc = "Bit 30 - 30:30\\]
Tx FIFO/Queue Mode"]
# [inline (always)]
# [must_use]
pub fn tfqm (& mut self) -> TfqmW < TxbcSpec > { TfqmW :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu61 (& mut self) -> Nu61W < TxbcSpec > { Nu61W :: new (self , 31) } } # [doc = "TXBC\n\nYou can [`read`](crate::Reg::read) this register and get [`txbc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbcSpec ; impl crate :: RegisterSpec for TxbcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbc::R`](R) reader structure"]
impl crate :: Readable for TxbcSpec { } # [doc = "`write(|w| ..)` method takes [`txbc::W`](W) writer structure"]
impl crate :: Writable for TxbcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBC to value 0"]
impl crate :: Resettable for TxbcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXFQS (rw) register accessor: TXFQS\n\nYou can [`read`](crate::Reg::read) this register and get [`txfqs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfqs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfqs`]
module"]
# [doc (alias = "TXFQS")]
pub type Txfqs = crate :: Reg < txfqs :: TxfqsSpec > ; # [doc = "TXFQS"]
pub mod txfqs { # [doc = "Register `TXFQS` reader"]
pub type R = crate :: R < TxfqsSpec > ; # [doc = "Register `TXFQS` writer"]
pub type W = crate :: W < TxfqsSpec > ; # [doc = "Field `TFFL` reader - 5:0\\]
Tx FIFO Free Level"]
pub type TfflR = crate :: FieldReader ; # [doc = "Field `TFFL` writer - 5:0\\]
Tx FIFO Free Level"]
pub type TfflW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU62` reader - 7:6\\]
Reserved"]
pub type Nu62R = crate :: FieldReader ; # [doc = "Field `NU62` writer - 7:6\\]
Reserved"]
pub type Nu62W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TFGI` reader - 12:8\\]
Tx Queue Get Index"]
pub type TfgiR = crate :: FieldReader ; # [doc = "Field `TFGI` writer - 12:8\\]
Tx Queue Get Index"]
pub type TfgiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU63` reader - 15:13\\]
Reserved"]
pub type Nu63R = crate :: FieldReader ; # [doc = "Field `NU63` writer - 15:13\\]
Reserved"]
pub type Nu63W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TFQPI` reader - 20:16\\]
Tx FIFO/Queue Put Index"]
pub type TfqpiR = crate :: FieldReader ; # [doc = "Field `TFQPI` writer - 20:16\\]
Tx FIFO/Queue Put Index"]
pub type TfqpiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TFQF` reader - 21:21\\]
Tx FIFO/Queue Full"]
pub type TfqfR = crate :: BitReader ; # [doc = "Field `TFQF` writer - 21:21\\]
Tx FIFO/Queue Full"]
pub type TfqfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU64` reader - 31:22\\]
Reserved"]
pub type Nu64R = crate :: FieldReader < u16 > ; # [doc = "Field `NU64` writer - 31:22\\]
Reserved"]
pub type Nu64W < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Tx FIFO Free Level"]
# [inline (always)]
pub fn tffl (& self) -> TfflR { TfflR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Reserved"]
# [inline (always)]
pub fn nu62 (& self) -> Nu62R { Nu62R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Tx Queue Get Index"]
# [inline (always)]
pub fn tfgi (& self) -> TfgiR { TfgiR :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved"]
# [inline (always)]
pub fn nu63 (& self) -> Nu63R { Nu63R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
Tx FIFO/Queue Put Index"]
# [inline (always)]
pub fn tfqpi (& self) -> TfqpiR { TfqpiR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bit 21 - 21:21\\]
Tx FIFO/Queue Full"]
# [inline (always)]
pub fn tfqf (& self) -> TfqfR { TfqfR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bits 22:31 - 31:22\\]
Reserved"]
# [inline (always)]
pub fn nu64 (& self) -> Nu64R { Nu64R :: new (((self . bits >> 22) & 0x03ff) as u16) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Tx FIFO Free Level"]
# [inline (always)]
# [must_use]
pub fn tffl (& mut self) -> TfflW < TxfqsSpec > { TfflW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu62 (& mut self) -> Nu62W < TxfqsSpec > { Nu62W :: new (self , 6) } # [doc = "Bits 8:12 - 12:8\\]
Tx Queue Get Index"]
# [inline (always)]
# [must_use]
pub fn tfgi (& mut self) -> TfgiW < TxfqsSpec > { TfgiW :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu63 (& mut self) -> Nu63W < TxfqsSpec > { Nu63W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
Tx FIFO/Queue Put Index"]
# [inline (always)]
# [must_use]
pub fn tfqpi (& mut self) -> TfqpiW < TxfqsSpec > { TfqpiW :: new (self , 16) } # [doc = "Bit 21 - 21:21\\]
Tx FIFO/Queue Full"]
# [inline (always)]
# [must_use]
pub fn tfqf (& mut self) -> TfqfW < TxfqsSpec > { TfqfW :: new (self , 21) } # [doc = "Bits 22:31 - 31:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu64 (& mut self) -> Nu64W < TxfqsSpec > { Nu64W :: new (self , 22) } } # [doc = "TXFQS\n\nYou can [`read`](crate::Reg::read) this register and get [`txfqs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfqs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfqsSpec ; impl crate :: RegisterSpec for TxfqsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txfqs::R`](R) reader structure"]
impl crate :: Readable for TxfqsSpec { } # [doc = "`write(|w| ..)` method takes [`txfqs::W`](W) writer structure"]
impl crate :: Writable for TxfqsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXFQS to value 0"]
impl crate :: Resettable for TxfqsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXESC (rw) register accessor: TXESC\n\nYou can [`read`](crate::Reg::read) this register and get [`txesc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txesc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txesc`]
module"]
# [doc (alias = "TXESC")]
pub type Txesc = crate :: Reg < txesc :: TxescSpec > ; # [doc = "TXESC"]
pub mod txesc { # [doc = "Register `TXESC` reader"]
pub type R = crate :: R < TxescSpec > ; # [doc = "Register `TXESC` writer"]
pub type W = crate :: W < TxescSpec > ; # [doc = "Field `TBDS` reader - 2:0\\]
Tx Buffer Data Field Size"]
pub type TbdsR = crate :: FieldReader ; # [doc = "Field `TBDS` writer - 2:0\\]
Tx Buffer Data Field Size"]
pub type TbdsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU65` reader - 31:3\\]
Reserved"]
pub type Nu65R = crate :: FieldReader < u32 > ; # [doc = "Field `NU65` writer - 31:3\\]
Reserved"]
pub type Nu65W < 'a , REG > = crate :: FieldWriter < 'a , REG , 29 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Tx Buffer Data Field Size"]
# [inline (always)]
pub fn tbds (& self) -> TbdsR { TbdsR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:31 - 31:3\\]
Reserved"]
# [inline (always)]
pub fn nu65 (& self) -> Nu65R { Nu65R :: new ((self . bits >> 3) & 0x1fff_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Tx Buffer Data Field Size"]
# [inline (always)]
# [must_use]
pub fn tbds (& mut self) -> TbdsW < TxescSpec > { TbdsW :: new (self , 0) } # [doc = "Bits 3:31 - 31:3\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu65 (& mut self) -> Nu65W < TxescSpec > { Nu65W :: new (self , 3) } } # [doc = "TXESC\n\nYou can [`read`](crate::Reg::read) this register and get [`txesc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txesc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxescSpec ; impl crate :: RegisterSpec for TxescSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txesc::R`](R) reader structure"]
impl crate :: Readable for TxescSpec { } # [doc = "`write(|w| ..)` method takes [`txesc::W`](W) writer structure"]
impl crate :: Writable for TxescSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXESC to value 0"]
impl crate :: Resettable for TxescSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBRP (rw) register accessor: TXBRP\n\nYou can [`read`](crate::Reg::read) this register and get [`txbrp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbrp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbrp`]
module"]
# [doc (alias = "TXBRP")]
pub type Txbrp = crate :: Reg < txbrp :: TxbrpSpec > ; # [doc = "TXBRP"]
pub mod txbrp { # [doc = "Register `TXBRP` reader"]
pub type R = crate :: R < TxbrpSpec > ; # [doc = "Register `TXBRP` writer"]
pub type W = crate :: W < TxbrpSpec > ; # [doc = "Field `TRP` reader - 31:0\\]
Transmission Request Pending"]
pub type TrpR = crate :: FieldReader < u32 > ; # [doc = "Field `TRP` writer - 31:0\\]
Transmission Request Pending"]
pub type TrpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Transmission Request Pending"]
# [inline (always)]
pub fn trp (& self) -> TrpR { TrpR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Transmission Request Pending"]
# [inline (always)]
# [must_use]
pub fn trp (& mut self) -> TrpW < TxbrpSpec > { TrpW :: new (self , 0) } } # [doc = "TXBRP\n\nYou can [`read`](crate::Reg::read) this register and get [`txbrp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbrp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbrpSpec ; impl crate :: RegisterSpec for TxbrpSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbrp::R`](R) reader structure"]
impl crate :: Readable for TxbrpSpec { } # [doc = "`write(|w| ..)` method takes [`txbrp::W`](W) writer structure"]
impl crate :: Writable for TxbrpSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBRP to value 0"]
impl crate :: Resettable for TxbrpSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBAR (rw) register accessor: TXBAR\n\nYou can [`read`](crate::Reg::read) this register and get [`txbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbar`]
module"]
# [doc (alias = "TXBAR")]
pub type Txbar = crate :: Reg < txbar :: TxbarSpec > ; # [doc = "TXBAR"]
pub mod txbar { # [doc = "Register `TXBAR` reader"]
pub type R = crate :: R < TxbarSpec > ; # [doc = "Register `TXBAR` writer"]
pub type W = crate :: W < TxbarSpec > ; # [doc = "Field `AR` reader - 31:0\\]
Add request"]
pub type ArR = crate :: FieldReader < u32 > ; # [doc = "Field `AR` writer - 31:0\\]
Add request"]
pub type ArW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Add request"]
# [inline (always)]
pub fn ar (& self) -> ArR { ArR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Add request"]
# [inline (always)]
# [must_use]
pub fn ar (& mut self) -> ArW < TxbarSpec > { ArW :: new (self , 0) } } # [doc = "TXBAR\n\nYou can [`read`](crate::Reg::read) this register and get [`txbar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbarSpec ; impl crate :: RegisterSpec for TxbarSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbar::R`](R) reader structure"]
impl crate :: Readable for TxbarSpec { } # [doc = "`write(|w| ..)` method takes [`txbar::W`](W) writer structure"]
impl crate :: Writable for TxbarSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBAR to value 0"]
impl crate :: Resettable for TxbarSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBCR (rw) register accessor: TXBCR\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcr`]
module"]
# [doc (alias = "TXBCR")]
pub type Txbcr = crate :: Reg < txbcr :: TxbcrSpec > ; # [doc = "TXBCR"]
pub mod txbcr { # [doc = "Register `TXBCR` reader"]
pub type R = crate :: R < TxbcrSpec > ; # [doc = "Register `TXBCR` writer"]
pub type W = crate :: W < TxbcrSpec > ; # [doc = "Field `CR` reader - 31:0\\]
Cancellation Request"]
pub type CrR = crate :: FieldReader < u32 > ; # [doc = "Field `CR` writer - 31:0\\]
Cancellation Request"]
pub type CrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Cancellation Request"]
# [inline (always)]
pub fn cr (& self) -> CrR { CrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Cancellation Request"]
# [inline (always)]
# [must_use]
pub fn cr (& mut self) -> CrW < TxbcrSpec > { CrW :: new (self , 0) } } # [doc = "TXBCR\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbcrSpec ; impl crate :: RegisterSpec for TxbcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbcr::R`](R) reader structure"]
impl crate :: Readable for TxbcrSpec { } # [doc = "`write(|w| ..)` method takes [`txbcr::W`](W) writer structure"]
impl crate :: Writable for TxbcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBCR to value 0"]
impl crate :: Resettable for TxbcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBTO (rw) register accessor: TXBTO\n\nYou can [`read`](crate::Reg::read) this register and get [`txbto::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbto::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbto`]
module"]
# [doc (alias = "TXBTO")]
pub type Txbto = crate :: Reg < txbto :: TxbtoSpec > ; # [doc = "TXBTO"]
pub mod txbto { # [doc = "Register `TXBTO` reader"]
pub type R = crate :: R < TxbtoSpec > ; # [doc = "Register `TXBTO` writer"]
pub type W = crate :: W < TxbtoSpec > ; # [doc = "Field `TO` reader - 31:0\\]
Transmission Occurred"]
pub type ToR = crate :: FieldReader < u32 > ; # [doc = "Field `TO` writer - 31:0\\]
Transmission Occurred"]
pub type ToW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Transmission Occurred"]
# [inline (always)]
pub fn to (& self) -> ToR { ToR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Transmission Occurred"]
# [inline (always)]
# [must_use]
pub fn to (& mut self) -> ToW < TxbtoSpec > { ToW :: new (self , 0) } } # [doc = "TXBTO\n\nYou can [`read`](crate::Reg::read) this register and get [`txbto::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbto::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbtoSpec ; impl crate :: RegisterSpec for TxbtoSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbto::R`](R) reader structure"]
impl crate :: Readable for TxbtoSpec { } # [doc = "`write(|w| ..)` method takes [`txbto::W`](W) writer structure"]
impl crate :: Writable for TxbtoSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBTO to value 0"]
impl crate :: Resettable for TxbtoSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBCF (rw) register accessor: TXBCF\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcf`]
module"]
# [doc (alias = "TXBCF")]
pub type Txbcf = crate :: Reg < txbcf :: TxbcfSpec > ; # [doc = "TXBCF"]
pub mod txbcf { # [doc = "Register `TXBCF` reader"]
pub type R = crate :: R < TxbcfSpec > ; # [doc = "Register `TXBCF` writer"]
pub type W = crate :: W < TxbcfSpec > ; # [doc = "Field `CF` reader - 31:0\\]
Cancellation Finished"]
pub type CfR = crate :: FieldReader < u32 > ; # [doc = "Field `CF` writer - 31:0\\]
Cancellation Finished"]
pub type CfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Cancellation Finished"]
# [inline (always)]
pub fn cf (& self) -> CfR { CfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Cancellation Finished"]
# [inline (always)]
# [must_use]
pub fn cf (& mut self) -> CfW < TxbcfSpec > { CfW :: new (self , 0) } } # [doc = "TXBCF\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbcfSpec ; impl crate :: RegisterSpec for TxbcfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbcf::R`](R) reader structure"]
impl crate :: Readable for TxbcfSpec { } # [doc = "`write(|w| ..)` method takes [`txbcf::W`](W) writer structure"]
impl crate :: Writable for TxbcfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBCF to value 0"]
impl crate :: Resettable for TxbcfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBTIE (rw) register accessor: TXBTIE\n\nYou can [`read`](crate::Reg::read) this register and get [`txbtie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbtie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbtie`]
module"]
# [doc (alias = "TXBTIE")]
pub type Txbtie = crate :: Reg < txbtie :: TxbtieSpec > ; # [doc = "TXBTIE"]
pub mod txbtie { # [doc = "Register `TXBTIE` reader"]
pub type R = crate :: R < TxbtieSpec > ; # [doc = "Register `TXBTIE` writer"]
pub type W = crate :: W < TxbtieSpec > ; # [doc = "Field `TIE` reader - 31:0\\]
Transmission Interrupt Enable"]
pub type TieR = crate :: FieldReader < u32 > ; # [doc = "Field `TIE` writer - 31:0\\]
Transmission Interrupt Enable"]
pub type TieW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Transmission Interrupt Enable"]
# [inline (always)]
pub fn tie (& self) -> TieR { TieR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Transmission Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn tie (& mut self) -> TieW < TxbtieSpec > { TieW :: new (self , 0) } } # [doc = "TXBTIE\n\nYou can [`read`](crate::Reg::read) this register and get [`txbtie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbtie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbtieSpec ; impl crate :: RegisterSpec for TxbtieSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbtie::R`](R) reader structure"]
impl crate :: Readable for TxbtieSpec { } # [doc = "`write(|w| ..)` method takes [`txbtie::W`](W) writer structure"]
impl crate :: Writable for TxbtieSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBTIE to value 0"]
impl crate :: Resettable for TxbtieSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXBCIE (rw) register accessor: TXBCIE\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcie`]
module"]
# [doc (alias = "TXBCIE")]
pub type Txbcie = crate :: Reg < txbcie :: TxbcieSpec > ; # [doc = "TXBCIE"]
pub mod txbcie { # [doc = "Register `TXBCIE` reader"]
pub type R = crate :: R < TxbcieSpec > ; # [doc = "Register `TXBCIE` writer"]
pub type W = crate :: W < TxbcieSpec > ; # [doc = "Field `CFIE` reader - 31:0\\]
Cancellation Finished Interrupt Enable"]
pub type CfieR = crate :: FieldReader < u32 > ; # [doc = "Field `CFIE` writer - 31:0\\]
Cancellation Finished Interrupt Enable"]
pub type CfieW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Cancellation Finished Interrupt Enable"]
# [inline (always)]
pub fn cfie (& self) -> CfieR { CfieR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Cancellation Finished Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn cfie (& mut self) -> CfieW < TxbcieSpec > { CfieW :: new (self , 0) } } # [doc = "TXBCIE\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbcieSpec ; impl crate :: RegisterSpec for TxbcieSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txbcie::R`](R) reader structure"]
impl crate :: Readable for TxbcieSpec { } # [doc = "`write(|w| ..)` method takes [`txbcie::W`](W) writer structure"]
impl crate :: Writable for TxbcieSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXBCIE to value 0"]
impl crate :: Resettable for TxbcieSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES14 (rw) register accessor: RES14\n\nYou can [`read`](crate::Reg::read) this register and get [`res14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res14`]
module"]
# [doc (alias = "RES14")]
pub type Res14 = crate :: Reg < res14 :: Res14Spec > ; # [doc = "RES14"]
pub mod res14 { # [doc = "Register `RES14` reader"]
pub type R = crate :: R < Res14Spec > ; # [doc = "Register `RES14` writer"]
pub type W = crate :: W < Res14Spec > ; # [doc = "Field `RES14` reader - 31:0\\]
Reserved"]
pub type Res14R = crate :: FieldReader < u32 > ; # [doc = "Field `RES14` writer - 31:0\\]
Reserved"]
pub type Res14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res14 (& self) -> Res14R { Res14R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res14 (& mut self) -> Res14W < Res14Spec > { Res14W :: new (self , 0) } } # [doc = "RES14\n\nYou can [`read`](crate::Reg::read) this register and get [`res14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res14Spec ; impl crate :: RegisterSpec for Res14Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res14::R`](R) reader structure"]
impl crate :: Readable for Res14Spec { } # [doc = "`write(|w| ..)` method takes [`res14::W`](W) writer structure"]
impl crate :: Writable for Res14Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES14 to value 0"]
impl crate :: Resettable for Res14Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES15 (rw) register accessor: RES15\n\nYou can [`read`](crate::Reg::read) this register and get [`res15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res15`]
module"]
# [doc (alias = "RES15")]
pub type Res15 = crate :: Reg < res15 :: Res15Spec > ; # [doc = "RES15"]
pub mod res15 { # [doc = "Register `RES15` reader"]
pub type R = crate :: R < Res15Spec > ; # [doc = "Register `RES15` writer"]
pub type W = crate :: W < Res15Spec > ; # [doc = "Field `RES15` reader - 31:0\\]
Reserved"]
pub type Res15R = crate :: FieldReader < u32 > ; # [doc = "Field `RES15` writer - 31:0\\]
Reserved"]
pub type Res15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res15 (& self) -> Res15R { Res15R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res15 (& mut self) -> Res15W < Res15Spec > { Res15W :: new (self , 0) } } # [doc = "RES15\n\nYou can [`read`](crate::Reg::read) this register and get [`res15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res15Spec ; impl crate :: RegisterSpec for Res15Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res15::R`](R) reader structure"]
impl crate :: Readable for Res15Spec { } # [doc = "`write(|w| ..)` method takes [`res15::W`](W) writer structure"]
impl crate :: Writable for Res15Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES15 to value 0"]
impl crate :: Resettable for Res15Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXEFC (rw) register accessor: TXEFC\n\nYou can [`read`](crate::Reg::read) this register and get [`txefc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txefc`]
module"]
# [doc (alias = "TXEFC")]
pub type Txefc = crate :: Reg < txefc :: TxefcSpec > ; # [doc = "TXEFC"]
pub mod txefc { # [doc = "Register `TXEFC` reader"]
pub type R = crate :: R < TxefcSpec > ; # [doc = "Register `TXEFC` writer"]
pub type W = crate :: W < TxefcSpec > ; # [doc = "Field `NU66` reader - 1:0\\]
Reserved"]
pub type Nu66R = crate :: FieldReader ; # [doc = "Field `NU66` writer - 1:0\\]
Reserved"]
pub type Nu66W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EFSA` reader - 15:2\\]
Event FIFO Start Address"]
pub type EfsaR = crate :: FieldReader < u16 > ; # [doc = "Field `EFSA` writer - 15:2\\]
Event FIFO Start Address"]
pub type EfsaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; # [doc = "Field `EFS` reader - 21:16\\]
Event FIFO Size"]
pub type EfsR = crate :: FieldReader ; # [doc = "Field `EFS` writer - 21:16\\]
Event FIFO Size"]
pub type EfsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU67` reader - 23:22\\]
Reserved"]
pub type Nu67R = crate :: FieldReader ; # [doc = "Field `NU67` writer - 23:22\\]
Reserved"]
pub type Nu67W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EFWM` reader - 29:24\\]
Event FIFO Watermark"]
pub type EfwmR = crate :: FieldReader ; # [doc = "Field `EFWM` writer - 29:24\\]
Event FIFO Watermark"]
pub type EfwmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU68` reader - 31:30\\]
Reserved"]
pub type Nu68R = crate :: FieldReader ; # [doc = "Field `NU68` writer - 31:30\\]
Reserved"]
pub type Nu68W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
pub fn nu66 (& self) -> Nu66R { Nu66R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:15 - 15:2\\]
Event FIFO Start Address"]
# [inline (always)]
pub fn efsa (& self) -> EfsaR { EfsaR :: new (((self . bits >> 2) & 0x3fff) as u16) } # [doc = "Bits 16:21 - 21:16\\]
Event FIFO Size"]
# [inline (always)]
pub fn efs (& self) -> EfsR { EfsR :: new (((self . bits >> 16) & 0x3f) as u8) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
pub fn nu67 (& self) -> Nu67R { Nu67R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:29 - 29:24\\]
Event FIFO Watermark"]
# [inline (always)]
pub fn efwm (& self) -> EfwmR { EfwmR :: new (((self . bits >> 24) & 0x3f) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
pub fn nu68 (& self) -> Nu68R { Nu68R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu66 (& mut self) -> Nu66W < TxefcSpec > { Nu66W :: new (self , 0) } # [doc = "Bits 2:15 - 15:2\\]
Event FIFO Start Address"]
# [inline (always)]
# [must_use]
pub fn efsa (& mut self) -> EfsaW < TxefcSpec > { EfsaW :: new (self , 2) } # [doc = "Bits 16:21 - 21:16\\]
Event FIFO Size"]
# [inline (always)]
# [must_use]
pub fn efs (& mut self) -> EfsW < TxefcSpec > { EfsW :: new (self , 16) } # [doc = "Bits 22:23 - 23:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu67 (& mut self) -> Nu67W < TxefcSpec > { Nu67W :: new (self , 22) } # [doc = "Bits 24:29 - 29:24\\]
Event FIFO Watermark"]
# [inline (always)]
# [must_use]
pub fn efwm (& mut self) -> EfwmW < TxefcSpec > { EfwmW :: new (self , 24) } # [doc = "Bits 30:31 - 31:30\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu68 (& mut self) -> Nu68W < TxefcSpec > { Nu68W :: new (self , 30) } } # [doc = "TXEFC\n\nYou can [`read`](crate::Reg::read) this register and get [`txefc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxefcSpec ; impl crate :: RegisterSpec for TxefcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txefc::R`](R) reader structure"]
impl crate :: Readable for TxefcSpec { } # [doc = "`write(|w| ..)` method takes [`txefc::W`](W) writer structure"]
impl crate :: Writable for TxefcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXEFC to value 0"]
impl crate :: Resettable for TxefcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXEFS (rw) register accessor: TXEFS\n\nYou can [`read`](crate::Reg::read) this register and get [`txefs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txefs`]
module"]
# [doc (alias = "TXEFS")]
pub type Txefs = crate :: Reg < txefs :: TxefsSpec > ; # [doc = "TXEFS"]
pub mod txefs { # [doc = "Register `TXEFS` reader"]
pub type R = crate :: R < TxefsSpec > ; # [doc = "Register `TXEFS` writer"]
pub type W = crate :: W < TxefsSpec > ; # [doc = "Field `EFFL` reader - 5:0\\]
Event FIFO FIll Level"]
pub type EfflR = crate :: FieldReader ; # [doc = "Field `EFFL` writer - 5:0\\]
Event FIFO FIll Level"]
pub type EfflW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU69` reader - 7:6\\]
Reserved"]
pub type Nu69R = crate :: FieldReader ; # [doc = "Field `NU69` writer - 7:6\\]
Reserved"]
pub type Nu69W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EFGI` reader - 12:8\\]
Event FIFO Get Index"]
pub type EfgiR = crate :: FieldReader ; # [doc = "Field `EFGI` writer - 12:8\\]
Event FIFO Get Index"]
pub type EfgiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU70` reader - 15:13\\]
Reserved"]
pub type Nu70R = crate :: FieldReader ; # [doc = "Field `NU70` writer - 15:13\\]
Reserved"]
pub type Nu70W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `EFPI` reader - 20:16\\]
Event FIFO Put Index"]
pub type EfpiR = crate :: FieldReader ; # [doc = "Field `EFPI` writer - 20:16\\]
Event FIFO Put Index"]
pub type EfpiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU71` reader - 23:21\\]
Reserved"]
pub type Nu71R = crate :: FieldReader ; # [doc = "Field `NU71` writer - 23:21\\]
Reserved"]
pub type Nu71W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `EFF` reader - 24:24\\]
Event FIFO Full"]
pub type EffR = crate :: BitReader ; # [doc = "Field `EFF` writer - 24:24\\]
Event FIFO Full"]
pub type EffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEFL` reader - 25:25\\]
Tx Event FIFO Element Lost"]
pub type TeflR = crate :: BitReader ; # [doc = "Field `TEFL` writer - 25:25\\]
Tx Event FIFO Element Lost"]
pub type TeflW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU72` reader - 31:26\\]
Reserved"]
pub type Nu72R = crate :: FieldReader ; # [doc = "Field `NU72` writer - 31:26\\]
Reserved"]
pub type Nu72W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event FIFO FIll Level"]
# [inline (always)]
pub fn effl (& self) -> EfflR { EfflR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Reserved"]
# [inline (always)]
pub fn nu69 (& self) -> Nu69R { Nu69R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Event FIFO Get Index"]
# [inline (always)]
pub fn efgi (& self) -> EfgiR { EfgiR :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved"]
# [inline (always)]
pub fn nu70 (& self) -> Nu70R { Nu70R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
Event FIFO Put Index"]
# [inline (always)]
pub fn efpi (& self) -> EfpiR { EfpiR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
pub fn nu71 (& self) -> Nu71R { Nu71R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Event FIFO Full"]
# [inline (always)]
pub fn eff (& self) -> EffR { EffR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Tx Event FIFO Element Lost"]
# [inline (always)]
pub fn tefl (& self) -> TeflR { TeflR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn nu72 (& self) -> Nu72R { Nu72R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event FIFO FIll Level"]
# [inline (always)]
# [must_use]
pub fn effl (& mut self) -> EfflW < TxefsSpec > { EfflW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu69 (& mut self) -> Nu69W < TxefsSpec > { Nu69W :: new (self , 6) } # [doc = "Bits 8:12 - 12:8\\]
Event FIFO Get Index"]
# [inline (always)]
# [must_use]
pub fn efgi (& mut self) -> EfgiW < TxefsSpec > { EfgiW :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu70 (& mut self) -> Nu70W < TxefsSpec > { Nu70W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
Event FIFO Put Index"]
# [inline (always)]
# [must_use]
pub fn efpi (& mut self) -> EfpiW < TxefsSpec > { EfpiW :: new (self , 16) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu71 (& mut self) -> Nu71W < TxefsSpec > { Nu71W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Event FIFO Full"]
# [inline (always)]
# [must_use]
pub fn eff (& mut self) -> EffW < TxefsSpec > { EffW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Tx Event FIFO Element Lost"]
# [inline (always)]
# [must_use]
pub fn tefl (& mut self) -> TeflW < TxefsSpec > { TeflW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu72 (& mut self) -> Nu72W < TxefsSpec > { Nu72W :: new (self , 26) } } # [doc = "TXEFS\n\nYou can [`read`](crate::Reg::read) this register and get [`txefs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxefsSpec ; impl crate :: RegisterSpec for TxefsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txefs::R`](R) reader structure"]
impl crate :: Readable for TxefsSpec { } # [doc = "`write(|w| ..)` method takes [`txefs::W`](W) writer structure"]
impl crate :: Writable for TxefsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXEFS to value 0"]
impl crate :: Resettable for TxefsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TXEFA (rw) register accessor: TXEFA\n\nYou can [`read`](crate::Reg::read) this register and get [`txefa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txefa`]
module"]
# [doc (alias = "TXEFA")]
pub type Txefa = crate :: Reg < txefa :: TxefaSpec > ; # [doc = "TXEFA"]
pub mod txefa { # [doc = "Register `TXEFA` reader"]
pub type R = crate :: R < TxefaSpec > ; # [doc = "Register `TXEFA` writer"]
pub type W = crate :: W < TxefaSpec > ; # [doc = "Field `EFAI` reader - 4:0\\]
Event FIFO Acknowledge Index"]
pub type EfaiR = crate :: FieldReader ; # [doc = "Field `EFAI` writer - 4:0\\]
Event FIFO Acknowledge Index"]
pub type EfaiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU73` reader - 31:5\\]
Reserved"]
pub type Nu73R = crate :: FieldReader < u32 > ; # [doc = "Field `NU73` writer - 31:5\\]
Reserved"]
pub type Nu73W < 'a , REG > = crate :: FieldWriter < 'a , REG , 27 , u32 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Event FIFO Acknowledge Index"]
# [inline (always)]
pub fn efai (& self) -> EfaiR { EfaiR :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:31 - 31:5\\]
Reserved"]
# [inline (always)]
pub fn nu73 (& self) -> Nu73R { Nu73R :: new ((self . bits >> 5) & 0x07ff_ffff) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Event FIFO Acknowledge Index"]
# [inline (always)]
# [must_use]
pub fn efai (& mut self) -> EfaiW < TxefaSpec > { EfaiW :: new (self , 0) } # [doc = "Bits 5:31 - 31:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu73 (& mut self) -> Nu73W < TxefaSpec > { Nu73W :: new (self , 5) } } # [doc = "TXEFA\n\nYou can [`read`](crate::Reg::read) this register and get [`txefa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxefaSpec ; impl crate :: RegisterSpec for TxefaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`txefa::R`](R) reader structure"]
impl crate :: Readable for TxefaSpec { } # [doc = "`write(|w| ..)` method takes [`txefa::W`](W) writer structure"]
impl crate :: Writable for TxefaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TXEFA to value 0"]
impl crate :: Resettable for TxefaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RES16 (rw) register accessor: RES16\n\nYou can [`read`](crate::Reg::read) this register and get [`res16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res16`]
module"]
# [doc (alias = "RES16")]
pub type Res16 = crate :: Reg < res16 :: Res16Spec > ; # [doc = "RES16"]
pub mod res16 { # [doc = "Register `RES16` reader"]
pub type R = crate :: R < Res16Spec > ; # [doc = "Register `RES16` writer"]
pub type W = crate :: W < Res16Spec > ; # [doc = "Field `RES16` reader - 31:0\\]
Reserved"]
pub type Res16R = crate :: FieldReader < u32 > ; # [doc = "Field `RES16` writer - 31:0\\]
Reserved"]
pub type Res16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn res16 (& self) -> Res16R { Res16R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn res16 (& mut self) -> Res16W < Res16Spec > { Res16W :: new (self , 0) } } # [doc = "RES16\n\nYou can [`read`](crate::Reg::read) this register and get [`res16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res16Spec ; impl crate :: RegisterSpec for Res16Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`res16::R`](R) reader structure"]
impl crate :: Readable for Res16Spec { } # [doc = "`write(|w| ..)` method takes [`res16::W`](W) writer structure"]
impl crate :: Writable for Res16Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RES16 to value 0"]
impl crate :: Resettable for Res16Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_CANECC"]
pub struct AppCanecc { _marker : PhantomData < * const () > } unsafe impl Send for AppCanecc { } impl AppCanecc { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_canecc :: RegisterBlock = 0x53f7_fc00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_canecc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppCanecc { type Target = app_canecc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppCanecc { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppCanecc") . finish () } } # [doc = "APP_CANECC"]
pub mod app_canecc { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { rev : Rev , _reserved1 : [u8 ; 0x04]
, vector : Vector , stat : Stat , _reserved3 : [u8 ; 0x04]
, ctrl : Ctrl , err_ctrl1 : ErrCtrl1 , err_ctrl2 : ErrCtrl2 , err_stat1 : ErrStat1 , err_stat2 : ErrStat2 , err_stat3 : ErrStat3 , _reserved9 : [u8 ; 0x10]
, sec_eoi_reg : SecEoiReg , sec_status_reg0 : SecStatusReg0 , _reserved11 : [u8 ; 0x3c]
, sec_enable_set_reg0 : SecEnableSetReg0 , _reserved12 : [u8 ; 0x3c]
, sec_enable_clr_reg0 : SecEnableClrReg0 , _reserved13 : [u8 ; 0x78]
, ded_eoi_reg : DedEoiReg , ded_status_reg0 : DedStatusReg0 , _reserved15 : [u8 ; 0x3c]
, ded_enable_set_reg0 : DedEnableSetReg0 , _reserved16 : [u8 ; 0x3c]
, ded_enable_clr_reg0 : DedEnableClrReg0 , _reserved17 : [u8 ; 0x3c]
, aggr_enable_set : AggrEnableSet , aggr_enable_clr : AggrEnableClr , aggr_status_set : AggrStatusSet , aggr_status_clr : AggrStatusClr , } impl RegisterBlock { # [doc = "0x00 - Aggregator Revision Register"]
# [inline (always)]
pub const fn rev (& self) -> & Rev { & self . rev } # [doc = "0x08 - ECC Vector Register"]
# [inline (always)]
pub const fn vector (& self) -> & Vector { & self . vector } # [doc = "0x0c - Misc Status"]
# [inline (always)]
pub const fn stat (& self) -> & Stat { & self . stat } # [doc = "0x14 - CTRL"]
# [inline (always)]
pub const fn ctrl (& self) -> & Ctrl { & self . ctrl } # [doc = "0x18 - ERR_CTRL1"]
# [inline (always)]
pub const fn err_ctrl1 (& self) -> & ErrCtrl1 { & self . err_ctrl1 } # [doc = "0x1c - ERR_CTRL2"]
# [inline (always)]
pub const fn err_ctrl2 (& self) -> & ErrCtrl2 { & self . err_ctrl2 } # [doc = "0x20 - ERR_STAT1"]
# [inline (always)]
pub const fn err_stat1 (& self) -> & ErrStat1 { & self . err_stat1 } # [doc = "0x24 - ERR_STAT2"]
# [inline (always)]
pub const fn err_stat2 (& self) -> & ErrStat2 { & self . err_stat2 } # [doc = "0x28 - ERR_STAT3"]
# [inline (always)]
pub const fn err_stat3 (& self) -> & ErrStat3 { & self . err_stat3 } # [doc = "0x3c - EOI Register"]
# [inline (always)]
pub const fn sec_eoi_reg (& self) -> & SecEoiReg { & self . sec_eoi_reg } # [doc = "0x40 - Interrupt Status Register 0"]
# [inline (always)]
pub const fn sec_status_reg0 (& self) -> & SecStatusReg0 { & self . sec_status_reg0 } # [doc = "0x80 - Interrupt Enable Set Register 0"]
# [inline (always)]
pub const fn sec_enable_set_reg0 (& self) -> & SecEnableSetReg0 { & self . sec_enable_set_reg0 } # [doc = "0xc0 - Interrupt Enable Clear Register 0"]
# [inline (always)]
pub const fn sec_enable_clr_reg0 (& self) -> & SecEnableClrReg0 { & self . sec_enable_clr_reg0 } # [doc = "0x13c - EOI Register"]
# [inline (always)]
pub const fn ded_eoi_reg (& self) -> & DedEoiReg { & self . ded_eoi_reg } # [doc = "0x140 - Interrupt Status Register 0"]
# [inline (always)]
pub const fn ded_status_reg0 (& self) -> & DedStatusReg0 { & self . ded_status_reg0 } # [doc = "0x180 - Interrupt Enable Set Register 0"]
# [inline (always)]
pub const fn ded_enable_set_reg0 (& self) -> & DedEnableSetReg0 { & self . ded_enable_set_reg0 } # [doc = "0x1c0 - Interrupt Enable Clear Register 0"]
# [inline (always)]
pub const fn ded_enable_clr_reg0 (& self) -> & DedEnableClrReg0 { & self . ded_enable_clr_reg0 } # [doc = "0x200 - AGGR interrupt enable set Register"]
# [inline (always)]
pub const fn aggr_enable_set (& self) -> & AggrEnableSet { & self . aggr_enable_set } # [doc = "0x204 - AGGR interrupt enable clear Register"]
# [inline (always)]
pub const fn aggr_enable_clr (& self) -> & AggrEnableClr { & self . aggr_enable_clr } # [doc = "0x208 - AGGR interrupt status set Register"]
# [inline (always)]
pub const fn aggr_status_set (& self) -> & AggrStatusSet { & self . aggr_status_set } # [doc = "0x20c - AGGR interrupt status clear Register"]
# [inline (always)]
pub const fn aggr_status_clr (& self) -> & AggrStatusClr { & self . aggr_status_clr } } # [doc = "REV (rw) register accessor: Aggregator Revision Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rev`]
module"]
# [doc (alias = "REV")]
pub type Rev = crate :: Reg < rev :: RevSpec > ; # [doc = "Aggregator Revision Register"]
pub mod rev { # [doc = "Register `REV` reader"]
pub type R = crate :: R < RevSpec > ; # [doc = "Register `REV` writer"]
pub type W = crate :: W < RevSpec > ; # [doc = "Field `REVMIN` reader - 5:0\\]
Minor version"]
pub type RevminR = crate :: FieldReader ; # [doc = "Field `REVMIN` writer - 5:0\\]
Minor version"]
pub type RevminW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom version"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom version"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `REVMAJ` reader - 10:8\\]
Major version"]
pub type RevmajR = crate :: FieldReader ; # [doc = "Field `REVMAJ` writer - 10:8\\]
Major version"]
pub type RevmajW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `REVRTL` reader - 15:11\\]
RTL version"]
pub type RevrtlR = crate :: FieldReader ; # [doc = "Field `REVRTL` writer - 15:11\\]
RTL version"]
pub type RevrtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `MODULE_ID` reader - 27:16\\]
Module ID"]
pub type ModuleIdR = crate :: FieldReader < u16 > ; # [doc = "Field `MODULE_ID` writer - 27:16\\]
Module ID"]
pub type ModuleIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `BU` reader - 29:28\\]
bu"]
pub type BuR = crate :: FieldReader ; # [doc = "Field `BU` writer - 29:28\\]
bu"]
pub type BuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
Scheme"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
Scheme"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor version"]
# [inline (always)]
pub fn revmin (& self) -> RevminR { RevminR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom version"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major version"]
# [inline (always)]
pub fn revmaj (& self) -> RevmajR { RevmajR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL version"]
# [inline (always)]
pub fn revrtl (& self) -> RevrtlR { RevrtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Module ID"]
# [inline (always)]
pub fn module_id (& self) -> ModuleIdR { ModuleIdR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
bu"]
# [inline (always)]
pub fn bu (& self) -> BuR { BuR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Scheme"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor version"]
# [inline (always)]
# [must_use]
pub fn revmin (& mut self) -> RevminW < RevSpec > { RevminW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom version"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < RevSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major version"]
# [inline (always)]
# [must_use]
pub fn revmaj (& mut self) -> RevmajW < RevSpec > { RevmajW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL version"]
# [inline (always)]
# [must_use]
pub fn revrtl (& mut self) -> RevrtlW < RevSpec > { RevrtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Module ID"]
# [inline (always)]
# [must_use]
pub fn module_id (& mut self) -> ModuleIdW < RevSpec > { ModuleIdW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
bu"]
# [inline (always)]
# [must_use]
pub fn bu (& mut self) -> BuW < RevSpec > { BuW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
Scheme"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < RevSpec > { SchemeW :: new (self , 30) } } # [doc = "Aggregator Revision Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RevSpec ; impl crate :: RegisterSpec for RevSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rev::R`](R) reader structure"]
impl crate :: Readable for RevSpec { } # [doc = "`write(|w| ..)` method takes [`rev::W`](W) writer structure"]
impl crate :: Writable for RevSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REV to value 0"]
impl crate :: Resettable for RevSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "VECTOR (rw) register accessor: ECC Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`vector::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vector::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vector`]
module"]
# [doc (alias = "VECTOR")]
pub type Vector = crate :: Reg < vector :: VectorSpec > ; # [doc = "ECC Vector Register"]
pub mod vector { # [doc = "Register `VECTOR` reader"]
pub type R = crate :: R < VectorSpec > ; # [doc = "Register `VECTOR` writer"]
pub type W = crate :: W < VectorSpec > ; # [doc = "Field `ECC_VEC` reader - 10:0\\]
Value written to select the corresponding ECC RAM for control or status"]
pub type EccVecR = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_VEC` writer - 10:0\\]
Value written to select the corresponding ECC RAM for control or status"]
pub type EccVecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `NU0` reader - 14:11\\]
Reserved"]
pub type Nu0R = crate :: FieldReader ; # [doc = "Field `NU0` writer - 14:11\\]
Reserved"]
pub type Nu0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RD_SVBUS` reader - 15:15\\]
Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type RdSvbusR = crate :: BitReader ; # [doc = "Field `RD_SVBUS` writer - 15:15\\]
Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type RdSvbusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RD_SVBUS_ADDR` reader - 23:16\\]
Read address"]
pub type RdSvbusAddrR = crate :: FieldReader ; # [doc = "Field `RD_SVBUS_ADDR` writer - 23:16\\]
Read address"]
pub type RdSvbusAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD_SVBUS_DONE` reader - 24:24\\]
Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field."]
pub type RdSvbusDoneR = crate :: BitReader ; # [doc = "Field `RD_SVBUS_DONE` writer - 24:24\\]
Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field."]
pub type RdSvbusDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 31:25\\]
Reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 31:25\\]
Reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:10 - 10:0\\]
Value written to select the corresponding ECC RAM for control or status"]
# [inline (always)]
pub fn ecc_vec (& self) -> EccVecR { EccVecR :: new ((self . bits & 0x07ff) as u16) } # [doc = "Bits 11:14 - 14:11\\]
Reserved"]
# [inline (always)]
pub fn nu0 (& self) -> Nu0R { Nu0R :: new (((self . bits >> 11) & 0x0f) as u8) } # [doc = "Bit 15 - 15:15\\]
Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn rd_svbus (& self) -> RdSvbusR { RdSvbusR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - 23:16\\]
Read address"]
# [inline (always)]
pub fn rd_svbus_addr (& self) -> RdSvbusAddrR { RdSvbusAddrR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 24 - 24:24\\]
Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field."]
# [inline (always)]
pub fn rd_svbus_done (& self) -> RdSvbusDoneR { RdSvbusDoneR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
Reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:10 - 10:0\\]
Value written to select the corresponding ECC RAM for control or status"]
# [inline (always)]
# [must_use]
pub fn ecc_vec (& mut self) -> EccVecW < VectorSpec > { EccVecW :: new (self , 0) } # [doc = "Bits 11:14 - 14:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu0 (& mut self) -> Nu0W < VectorSpec > { Nu0W :: new (self , 11) } # [doc = "Bit 15 - 15:15\\]
Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn rd_svbus (& mut self) -> RdSvbusW < VectorSpec > { RdSvbusW :: new (self , 15) } # [doc = "Bits 16:23 - 23:16\\]
Read address"]
# [inline (always)]
# [must_use]
pub fn rd_svbus_addr (& mut self) -> RdSvbusAddrW < VectorSpec > { RdSvbusAddrW :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn rd_svbus_done (& mut self) -> RdSvbusDoneW < VectorSpec > { RdSvbusDoneW :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < VectorSpec > { Nu1W :: new (self , 25) } } # [doc = "ECC Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`vector::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vector::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct VectorSpec ; impl crate :: RegisterSpec for VectorSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`vector::R`](R) reader structure"]
impl crate :: Readable for VectorSpec { } # [doc = "`write(|w| ..)` method takes [`vector::W`](W) writer structure"]
impl crate :: Writable for VectorSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets VECTOR to value 0"]
impl crate :: Resettable for VectorSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "STAT (rw) register accessor: Misc Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
# [doc (alias = "STAT")]
pub type Stat = crate :: Reg < stat :: StatSpec > ; # [doc = "Misc Status"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < StatSpec > ; # [doc = "Register `STAT` writer"]
pub type W = crate :: W < StatSpec > ; # [doc = "Field `NUM_RAMS` reader - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator"]
pub type NumRamsR = crate :: FieldReader < u16 > ; # [doc = "Field `NUM_RAMS` writer - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator"]
pub type NumRamsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `NU2` reader - 31:11\\]
Reserved"]
pub type Nu2R = crate :: FieldReader < u32 > ; # [doc = "Field `NU2` writer - 31:11\\]
Reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:10 - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator"]
# [inline (always)]
pub fn num_rams (& self) -> NumRamsR { NumRamsR :: new ((self . bits & 0x07ff) as u16) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:10 - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator"]
# [inline (always)]
# [must_use]
pub fn num_rams (& mut self) -> NumRamsW < StatSpec > { NumRamsW :: new (self , 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < StatSpec > { Nu2W :: new (self , 11) } } # [doc = "Misc Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatSpec ; impl crate :: RegisterSpec for StatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for StatSpec { } # [doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"]
impl crate :: Writable for StatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for StatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTRL (rw) register accessor: CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
# [doc (alias = "CTRL")]
pub type Ctrl = crate :: Reg < ctrl :: CtrlSpec > ; # [doc = "CTRL"]
pub mod ctrl { # [doc = "Register `CTRL` reader"]
pub type R = crate :: R < CtrlSpec > ; # [doc = "Register `CTRL` writer"]
pub type W = crate :: W < CtrlSpec > ; # [doc = "Field `ECC_EN` reader - 0:0\\]
TI Internal : Enable ECC"]
pub type EccEnR = crate :: BitReader ; # [doc = "Field `ECC_EN` writer - 0:0\\]
TI Internal : Enable ECC"]
pub type EccEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ECC_CHK` reader - 1:1\\]
TI Internal : Enable ECC check"]
pub type EccChkR = crate :: BitReader ; # [doc = "Field `ECC_CHK` writer - 1:1\\]
TI Internal : Enable ECC check"]
pub type EccChkW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EN_RMW` reader - 2:2\\]
TI Internal : Enable rmw"]
pub type EnRmwR = crate :: BitReader ; # [doc = "Field `EN_RMW` writer - 2:2\\]
TI Internal : Enable rmw"]
pub type EnRmwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE_SEC` reader - 3:3\\]
TI Internal : Force Single Bit Error"]
pub type ForceSecR = crate :: BitReader ; # [doc = "Field `FORCE_SEC` writer - 3:3\\]
TI Internal : Force Single Bit Error"]
pub type ForceSecW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE_DED` reader - 4:4\\]
TI Internal : Force Double Bit Error"]
pub type ForceDedR = crate :: BitReader ; # [doc = "Field `FORCE_DED` writer - 4:4\\]
TI Internal : Force Double Bit Error"]
pub type ForceDedW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE_N_ROW` reader - 5:5\\]
TI Internal : Force Error on any RAM read"]
pub type ForceNRowR = crate :: BitReader ; # [doc = "Field `FORCE_N_ROW` writer - 5:5\\]
TI Internal : Force Error on any RAM read"]
pub type ForceNRowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERROR_ONCE` reader - 6:6\\]
TI Internal : Force Error only once"]
pub type ErrorOnceR = crate :: BitReader ; # [doc = "Field `ERROR_ONCE` writer - 6:6\\]
TI Internal : Force Error only once"]
pub type ErrorOnceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHECK PARITY` reader - 7:7\\]
TI Internal : Check Parity"]
pub type CheckparityR = crate :: BitReader ; # [doc = "Field `CHECK PARITY` writer - 7:7\\]
TI Internal : Check Parity"]
pub type CheckparityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHECK TIMEOUT` reader - 8:8\\]
TI Internal : Check timeout"]
pub type ChecktimeoutR = crate :: BitReader ; # [doc = "Field `CHECK TIMEOUT` writer - 8:8\\]
TI Internal : Check timeout"]
pub type ChecktimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU3` reader - 31:9\\]
TI Internal : Reserved"]
pub type Nu3R = crate :: FieldReader < u32 > ; # [doc = "Field `NU3` writer - 31:9\\]
TI Internal : Reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
TI Internal : Enable ECC"]
# [inline (always)]
pub fn ecc_en (& self) -> EccEnR { EccEnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TI Internal : Enable ECC check"]
# [inline (always)]
pub fn ecc_chk (& self) -> EccChkR { EccChkR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TI Internal : Enable rmw"]
# [inline (always)]
pub fn en_rmw (& self) -> EnRmwR { EnRmwR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
TI Internal : Force Single Bit Error"]
# [inline (always)]
pub fn force_sec (& self) -> ForceSecR { ForceSecR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
TI Internal : Force Double Bit Error"]
# [inline (always)]
pub fn force_ded (& self) -> ForceDedR { ForceDedR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
TI Internal : Force Error on any RAM read"]
# [inline (always)]
pub fn force_n_row (& self) -> ForceNRowR { ForceNRowR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
TI Internal : Force Error only once"]
# [inline (always)]
pub fn error_once (& self) -> ErrorOnceR { ErrorOnceR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
TI Internal : Check Parity"]
# [inline (always)]
pub fn checkparity (& self) -> CheckparityR { CheckparityR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
TI Internal : Check timeout"]
# [inline (always)]
pub fn checktimeout (& self) -> ChecktimeoutR { ChecktimeoutR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:31 - 31:9\\]
TI Internal : Reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new ((self . bits >> 9) & 0x007f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
TI Internal : Enable ECC"]
# [inline (always)]
# [must_use]
pub fn ecc_en (& mut self) -> EccEnW < CtrlSpec > { EccEnW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TI Internal : Enable ECC check"]
# [inline (always)]
# [must_use]
pub fn ecc_chk (& mut self) -> EccChkW < CtrlSpec > { EccChkW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TI Internal : Enable rmw"]
# [inline (always)]
# [must_use]
pub fn en_rmw (& mut self) -> EnRmwW < CtrlSpec > { EnRmwW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
TI Internal : Force Single Bit Error"]
# [inline (always)]
# [must_use]
pub fn force_sec (& mut self) -> ForceSecW < CtrlSpec > { ForceSecW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
TI Internal : Force Double Bit Error"]
# [inline (always)]
# [must_use]
pub fn force_ded (& mut self) -> ForceDedW < CtrlSpec > { ForceDedW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
TI Internal : Force Error on any RAM read"]
# [inline (always)]
# [must_use]
pub fn force_n_row (& mut self) -> ForceNRowW < CtrlSpec > { ForceNRowW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
TI Internal : Force Error only once"]
# [inline (always)]
# [must_use]
pub fn error_once (& mut self) -> ErrorOnceW < CtrlSpec > { ErrorOnceW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
TI Internal : Check Parity"]
# [inline (always)]
# [must_use]
pub fn checkparity (& mut self) -> CheckparityW < CtrlSpec > { CheckparityW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
TI Internal : Check timeout"]
# [inline (always)]
# [must_use]
pub fn checktimeout (& mut self) -> ChecktimeoutW < CtrlSpec > { ChecktimeoutW :: new (self , 8) } # [doc = "Bits 9:31 - 31:9\\]
TI Internal : Reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < CtrlSpec > { Nu3W :: new (self , 9) } } # [doc = "CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec ; impl crate :: RegisterSpec for CtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
impl crate :: Readable for CtrlSpec { } # [doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate :: Writable for CtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTRL to value 0"]
impl crate :: Resettable for CtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERR_CTRL1 (rw) register accessor: ERR_CTRL1\n\nYou can [`read`](crate::Reg::read) this register and get [`err_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_ctrl1`]
module"]
# [doc (alias = "ERR_CTRL1")]
pub type ErrCtrl1 = crate :: Reg < err_ctrl1 :: ErrCtrl1Spec > ; # [doc = "ERR_CTRL1"]
pub mod err_ctrl1 { # [doc = "Register `ERR_CTRL1` reader"]
pub type R = crate :: R < ErrCtrl1Spec > ; # [doc = "Register `ERR_CTRL1` writer"]
pub type W = crate :: W < ErrCtrl1Spec > ; # [doc = "Field `ECC_ROW` reader - 31:0\\]
TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"]
pub type EccRowR = crate :: FieldReader < u32 > ; # [doc = "Field `ECC_ROW` writer - 31:0\\]
TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"]
pub type EccRowW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"]
# [inline (always)]
pub fn ecc_row (& self) -> EccRowR { EccRowR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"]
# [inline (always)]
# [must_use]
pub fn ecc_row (& mut self) -> EccRowW < ErrCtrl1Spec > { EccRowW :: new (self , 0) } } # [doc = "ERR_CTRL1\n\nYou can [`read`](crate::Reg::read) this register and get [`err_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrCtrl1Spec ; impl crate :: RegisterSpec for ErrCtrl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`err_ctrl1::R`](R) reader structure"]
impl crate :: Readable for ErrCtrl1Spec { } # [doc = "`write(|w| ..)` method takes [`err_ctrl1::W`](W) writer structure"]
impl crate :: Writable for ErrCtrl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERR_CTRL1 to value 0"]
impl crate :: Resettable for ErrCtrl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERR_CTRL2 (rw) register accessor: ERR_CTRL2\n\nYou can [`read`](crate::Reg::read) this register and get [`err_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_ctrl2`]
module"]
# [doc (alias = "ERR_CTRL2")]
pub type ErrCtrl2 = crate :: Reg < err_ctrl2 :: ErrCtrl2Spec > ; # [doc = "ERR_CTRL2"]
pub mod err_ctrl2 { # [doc = "Register `ERR_CTRL2` reader"]
pub type R = crate :: R < ErrCtrl2Spec > ; # [doc = "Register `ERR_CTRL2` writer"]
pub type W = crate :: W < ErrCtrl2Spec > ; # [doc = "Field `ECC_BIT1` reader - 15:0\\]
TI Internal : Data bit that needs to be flipped when force_sec is set"]
pub type EccBit1R = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_BIT1` writer - 15:0\\]
TI Internal : Data bit that needs to be flipped when force_sec is set"]
pub type EccBit1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `ECC_BIT2` reader - 31:16\\]
TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"]
pub type EccBit2R = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_BIT2` writer - 31:16\\]
TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"]
pub type EccBit2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
TI Internal : Data bit that needs to be flipped when force_sec is set"]
# [inline (always)]
pub fn ecc_bit1 (& self) -> EccBit1R { EccBit1R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"]
# [inline (always)]
pub fn ecc_bit2 (& self) -> EccBit2R { EccBit2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
TI Internal : Data bit that needs to be flipped when force_sec is set"]
# [inline (always)]
# [must_use]
pub fn ecc_bit1 (& mut self) -> EccBit1W < ErrCtrl2Spec > { EccBit1W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"]
# [inline (always)]
# [must_use]
pub fn ecc_bit2 (& mut self) -> EccBit2W < ErrCtrl2Spec > { EccBit2W :: new (self , 16) } } # [doc = "ERR_CTRL2\n\nYou can [`read`](crate::Reg::read) this register and get [`err_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrCtrl2Spec ; impl crate :: RegisterSpec for ErrCtrl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`err_ctrl2::R`](R) reader structure"]
impl crate :: Readable for ErrCtrl2Spec { } # [doc = "`write(|w| ..)` method takes [`err_ctrl2::W`](W) writer structure"]
impl crate :: Writable for ErrCtrl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERR_CTRL2 to value 0"]
impl crate :: Resettable for ErrCtrl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERR_STAT1 (rw) register accessor: ERR_STAT1\n\nYou can [`read`](crate::Reg::read) this register and get [`err_stat1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_stat1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_stat1`]
module"]
# [doc (alias = "ERR_STAT1")]
pub type ErrStat1 = crate :: Reg < err_stat1 :: ErrStat1Spec > ; # [doc = "ERR_STAT1"]
pub mod err_stat1 { # [doc = "Register `ERR_STAT1` reader"]
pub type R = crate :: R < ErrStat1Spec > ; # [doc = "Register `ERR_STAT1` writer"]
pub type W = crate :: W < ErrStat1Spec > ; # [doc = "Field `ECC_SEC` reader - 1:0\\]
TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccSecR = crate :: FieldReader ; # [doc = "Field `ECC_SEC` writer - 1:0\\]
TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccSecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECC_DED` reader - 3:2\\]
TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccDedR = crate :: FieldReader ; # [doc = "Field `ECC_DED` writer - 3:2\\]
TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccDedW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECC_OTHER` reader - 4:4\\]
TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccOtherR = crate :: BitReader ; # [doc = "Field `ECC_OTHER` writer - 4:4\\]
TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccOtherW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ECC_PAR` reader - 6:5\\]
TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccParR = crate :: FieldReader ; # [doc = "Field `ECC_PAR` writer - 6:5\\]
TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccParW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECC_CTRL_REG` reader - 7:7\\]
TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccCtrlRegR = crate :: BitReader ; # [doc = "Field `ECC_CTRL_REG` writer - 7:7\\]
TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing."]
pub type EccCtrlRegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_ECC_SEC` reader - 9:8\\]
TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccSecR = crate :: FieldReader ; # [doc = "Field `CLR_ECC_SEC` writer - 9:8\\]
TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccSecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_ECC_DED` reader - 11:10\\]
TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccDedR = crate :: FieldReader ; # [doc = "Field `CLR_ECC_DED` writer - 11:10\\]
TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccDedW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_ECC_OTHER` reader - 12:12\\]
TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccOtherR = crate :: BitReader ; # [doc = "Field `CLR_ECC_OTHER` writer - 12:12\\]
TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccOtherW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_ECC_PAR` reader - 14:13\\]
TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccParR = crate :: FieldReader ; # [doc = "Field `CLR_ECC_PAR` writer - 14:13\\]
TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccParW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_ECC_CTRL_REG` reader - 15:15\\]
TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccCtrlRegR = crate :: BitReader ; # [doc = "Field `CLR_ECC_CTRL_REG` writer - 15:15\\]
TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing."]
pub type ClrEccCtrlRegW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ECC_BIT1_STS` reader - 31:16\\]
TI Internal : Data bit that corresponds to the single-bit error"]
pub type EccBit1StsR = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_BIT1_STS` writer - 31:16\\]
TI Internal : Data bit that corresponds to the single-bit error"]
pub type EccBit1StsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
pub fn ecc_sec (& self) -> EccSecR { EccSecR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
pub fn ecc_ded (& self) -> EccDedR { EccDedR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bit 4 - 4:4\\]
TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
pub fn ecc_other (& self) -> EccOtherR { EccOtherR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:6 - 6:5\\]
TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
pub fn ecc_par (& self) -> EccParR { EccParR :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - 7:7\\]
TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
pub fn ecc_ctrl_reg (& self) -> EccCtrlRegR { EccCtrlRegR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - 9:8\\]
TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
pub fn clr_ecc_sec (& self) -> ClrEccSecR { ClrEccSecR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
pub fn clr_ecc_ded (& self) -> ClrEccDedR { ClrEccDedR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - 12:12\\]
TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
pub fn clr_ecc_other (& self) -> ClrEccOtherR { ClrEccOtherR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - 14:13\\]
TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
pub fn clr_ecc_par (& self) -> ClrEccParR { ClrEccParR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - 15:15\\]
TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
pub fn clr_ecc_ctrl_reg (& self) -> ClrEccCtrlRegR { ClrEccCtrlRegR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
TI Internal : Data bit that corresponds to the single-bit error"]
# [inline (always)]
pub fn ecc_bit1_sts (& self) -> EccBit1StsR { EccBit1StsR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn ecc_sec (& mut self) -> EccSecW < ErrStat1Spec > { EccSecW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn ecc_ded (& mut self) -> EccDedW < ErrStat1Spec > { EccDedW :: new (self , 2) } # [doc = "Bit 4 - 4:4\\]
TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn ecc_other (& mut self) -> EccOtherW < ErrStat1Spec > { EccOtherW :: new (self , 4) } # [doc = "Bits 5:6 - 6:5\\]
TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn ecc_par (& mut self) -> EccParW < ErrStat1Spec > { EccParW :: new (self , 5) } # [doc = "Bit 7 - 7:7\\]
TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn ecc_ctrl_reg (& mut self) -> EccCtrlRegW < ErrStat1Spec > { EccCtrlRegW :: new (self , 7) } # [doc = "Bits 8:9 - 9:8\\]
TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn clr_ecc_sec (& mut self) -> ClrEccSecW < ErrStat1Spec > { ClrEccSecW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn clr_ecc_ded (& mut self) -> ClrEccDedW < ErrStat1Spec > { ClrEccDedW :: new (self , 10) } # [doc = "Bit 12 - 12:12\\]
TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn clr_ecc_other (& mut self) -> ClrEccOtherW < ErrStat1Spec > { ClrEccOtherW :: new (self , 12) } # [doc = "Bits 13:14 - 14:13\\]
TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn clr_ecc_par (& mut self) -> ClrEccParW < ErrStat1Spec > { ClrEccParW :: new (self , 13) } # [doc = "Bit 15 - 15:15\\]
TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing."]
# [inline (always)]
# [must_use]
pub fn clr_ecc_ctrl_reg (& mut self) -> ClrEccCtrlRegW < ErrStat1Spec > { ClrEccCtrlRegW :: new (self , 15) } # [doc = "Bits 16:31 - 31:16\\]
TI Internal : Data bit that corresponds to the single-bit error"]
# [inline (always)]
# [must_use]
pub fn ecc_bit1_sts (& mut self) -> EccBit1StsW < ErrStat1Spec > { EccBit1StsW :: new (self , 16) } } # [doc = "ERR_STAT1\n\nYou can [`read`](crate::Reg::read) this register and get [`err_stat1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_stat1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrStat1Spec ; impl crate :: RegisterSpec for ErrStat1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`err_stat1::R`](R) reader structure"]
impl crate :: Readable for ErrStat1Spec { } # [doc = "`write(|w| ..)` method takes [`err_stat1::W`](W) writer structure"]
impl crate :: Writable for ErrStat1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERR_STAT1 to value 0"]
impl crate :: Resettable for ErrStat1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERR_STAT2 (rw) register accessor: ERR_STAT2\n\nYou can [`read`](crate::Reg::read) this register and get [`err_stat2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_stat2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_stat2`]
module"]
# [doc (alias = "ERR_STAT2")]
pub type ErrStat2 = crate :: Reg < err_stat2 :: ErrStat2Spec > ; # [doc = "ERR_STAT2"]
pub mod err_stat2 { # [doc = "Register `ERR_STAT2` reader"]
pub type R = crate :: R < ErrStat2Spec > ; # [doc = "Register `ERR_STAT2` writer"]
pub type W = crate :: W < ErrStat2Spec > ; # [doc = "Field `ECC_ROW` reader - 31:0\\]
TI Internal : Row address where the single or double-bit error has occurred"]
pub type EccRowR = crate :: FieldReader < u32 > ; # [doc = "Field `ECC_ROW` writer - 31:0\\]
TI Internal : Row address where the single or double-bit error has occurred"]
pub type EccRowW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI Internal : Row address where the single or double-bit error has occurred"]
# [inline (always)]
pub fn ecc_row (& self) -> EccRowR { EccRowR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI Internal : Row address where the single or double-bit error has occurred"]
# [inline (always)]
# [must_use]
pub fn ecc_row (& mut self) -> EccRowW < ErrStat2Spec > { EccRowW :: new (self , 0) } } # [doc = "ERR_STAT2\n\nYou can [`read`](crate::Reg::read) this register and get [`err_stat2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_stat2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrStat2Spec ; impl crate :: RegisterSpec for ErrStat2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`err_stat2::R`](R) reader structure"]
impl crate :: Readable for ErrStat2Spec { } # [doc = "`write(|w| ..)` method takes [`err_stat2::W`](W) writer structure"]
impl crate :: Writable for ErrStat2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERR_STAT2 to value 0"]
impl crate :: Resettable for ErrStat2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERR_STAT3 (rw) register accessor: ERR_STAT3\n\nYou can [`read`](crate::Reg::read) this register and get [`err_stat3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_stat3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_stat3`]
module"]
# [doc (alias = "ERR_STAT3")]
pub type ErrStat3 = crate :: Reg < err_stat3 :: ErrStat3Spec > ; # [doc = "ERR_STAT3"]
pub mod err_stat3 { # [doc = "Register `ERR_STAT3` reader"]
pub type R = crate :: R < ErrStat3Spec > ; # [doc = "Register `ERR_STAT3` writer"]
pub type W = crate :: W < ErrStat3Spec > ; # [doc = "Field `NU4` reader - 0:0\\]
TI Internal : Reserved"]
pub type Nu4R = crate :: BitReader ; # [doc = "Field `NU4` writer - 0:0\\]
TI Internal : Reserved"]
pub type Nu4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT_PEND` reader - 1:1\\]
TI Internal : Timeout pending"]
pub type TimeoutPendR = crate :: BitReader ; # [doc = "Field `TIMEOUT_PEND` writer - 1:1\\]
TI Internal : Timeout pending"]
pub type TimeoutPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU5` reader - 8:2\\]
TI Internal : Reserved"]
pub type Nu5R = crate :: FieldReader ; # [doc = "Field `NU5` writer - 8:2\\]
TI Internal : Reserved"]
pub type Nu5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `CLR_TIMEOUT_PEND` reader - 9:9\\]
TI Internal : Clear timeout pending"]
pub type ClrTimeoutPendR = crate :: BitReader ; # [doc = "Field `CLR_TIMEOUT_PEND` writer - 9:9\\]
TI Internal : Clear timeout pending"]
pub type ClrTimeoutPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU6` reader - 31:10\\]
TI Internal : Reserved"]
pub type Nu6R = crate :: FieldReader < u32 > ; # [doc = "Field `NU6` writer - 31:10\\]
TI Internal : Reserved"]
pub type Nu6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
TI Internal : Reserved"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TI Internal : Timeout pending"]
# [inline (always)]
pub fn timeout_pend (& self) -> TimeoutPendR { TimeoutPendR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:8 - 8:2\\]
TI Internal : Reserved"]
# [inline (always)]
pub fn nu5 (& self) -> Nu5R { Nu5R :: new (((self . bits >> 2) & 0x7f) as u8) } # [doc = "Bit 9 - 9:9\\]
TI Internal : Clear timeout pending"]
# [inline (always)]
pub fn clr_timeout_pend (& self) -> ClrTimeoutPendR { ClrTimeoutPendR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:31 - 31:10\\]
TI Internal : Reserved"]
# [inline (always)]
pub fn nu6 (& self) -> Nu6R { Nu6R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
TI Internal : Reserved"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < ErrStat3Spec > { Nu4W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TI Internal : Timeout pending"]
# [inline (always)]
# [must_use]
pub fn timeout_pend (& mut self) -> TimeoutPendW < ErrStat3Spec > { TimeoutPendW :: new (self , 1) } # [doc = "Bits 2:8 - 8:2\\]
TI Internal : Reserved"]
# [inline (always)]
# [must_use]
pub fn nu5 (& mut self) -> Nu5W < ErrStat3Spec > { Nu5W :: new (self , 2) } # [doc = "Bit 9 - 9:9\\]
TI Internal : Clear timeout pending"]
# [inline (always)]
# [must_use]
pub fn clr_timeout_pend (& mut self) -> ClrTimeoutPendW < ErrStat3Spec > { ClrTimeoutPendW :: new (self , 9) } # [doc = "Bits 10:31 - 31:10\\]
TI Internal : Reserved"]
# [inline (always)]
# [must_use]
pub fn nu6 (& mut self) -> Nu6W < ErrStat3Spec > { Nu6W :: new (self , 10) } } # [doc = "ERR_STAT3\n\nYou can [`read`](crate::Reg::read) this register and get [`err_stat3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_stat3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrStat3Spec ; impl crate :: RegisterSpec for ErrStat3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`err_stat3::R`](R) reader structure"]
impl crate :: Readable for ErrStat3Spec { } # [doc = "`write(|w| ..)` method takes [`err_stat3::W`](W) writer structure"]
impl crate :: Writable for ErrStat3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERR_STAT3 to value 0"]
impl crate :: Resettable for ErrStat3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_EOI_REG (rw) register accessor: EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_eoi_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_eoi_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_eoi_reg`]
module"]
# [doc (alias = "SEC_EOI_REG")]
pub type SecEoiReg = crate :: Reg < sec_eoi_reg :: SecEoiRegSpec > ; # [doc = "EOI Register"]
pub mod sec_eoi_reg { # [doc = "Register `SEC_EOI_REG` reader"]
pub type R = crate :: R < SecEoiRegSpec > ; # [doc = "Register `SEC_EOI_REG` writer"]
pub type W = crate :: W < SecEoiRegSpec > ; # [doc = "Field `SEC_EOI_WR` reader - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
pub type SecEoiWrR = crate :: BitReader ; # [doc = "Field `SEC_EOI_WR` writer - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
pub type SecEoiWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU7` reader - 31:1\\]
Reserved"]
pub type Nu7R = crate :: FieldReader < u32 > ; # [doc = "Field `NU7` writer - 31:1\\]
Reserved"]
pub type Nu7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
# [inline (always)]
pub fn sec_eoi_wr (& self) -> SecEoiWrR { SecEoiWrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu7 (& self) -> Nu7R { Nu7R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn sec_eoi_wr (& mut self) -> SecEoiWrW < SecEoiRegSpec > { SecEoiWrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu7 (& mut self) -> Nu7W < SecEoiRegSpec > { Nu7W :: new (self , 1) } } # [doc = "EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_eoi_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_eoi_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecEoiRegSpec ; impl crate :: RegisterSpec for SecEoiRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_eoi_reg::R`](R) reader structure"]
impl crate :: Readable for SecEoiRegSpec { } # [doc = "`write(|w| ..)` method takes [`sec_eoi_reg::W`](W) writer structure"]
impl crate :: Writable for SecEoiRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_EOI_REG to value 0"]
impl crate :: Resettable for SecEoiRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_STATUS_REG0 (rw) register accessor: Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_status_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_status_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_status_reg0`]
module"]
# [doc (alias = "SEC_STATUS_REG0")]
pub type SecStatusReg0 = crate :: Reg < sec_status_reg0 :: SecStatusReg0Spec > ; # [doc = "Interrupt Status Register 0"]
pub mod sec_status_reg0 { # [doc = "Register `SEC_STATUS_REG0` reader"]
pub type R = crate :: R < SecStatusReg0Spec > ; # [doc = "Register `SEC_STATUS_REG0` writer"]
pub type W = crate :: W < SecStatusReg0Spec > ; # [doc = "Field `SEC_PEND` reader - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
pub type SecPendR = crate :: BitReader ; # [doc = "Field `SEC_PEND` writer - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
pub type SecPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRL_EDC_VBUSS_PEND` reader - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
pub type CtrlEdcVbussPendR = crate :: BitReader ; # [doc = "Field `CTRL_EDC_VBUSS_PEND` writer - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
pub type CtrlEdcVbussPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU8` reader - 31:2\\]
Reserved"]
pub type Nu8R = crate :: FieldReader < u32 > ; # [doc = "Field `NU8` writer - 31:2\\]
Reserved"]
pub type Nu8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
# [inline (always)]
pub fn sec_pend (& self) -> SecPendR { SecPendR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
# [inline (always)]
pub fn ctrl_edc_vbuss_pend (& self) -> CtrlEdcVbussPendR { CtrlEdcVbussPendR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu8 (& self) -> Nu8R { Nu8R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
# [inline (always)]
# [must_use]
pub fn sec_pend (& mut self) -> SecPendW < SecStatusReg0Spec > { SecPendW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
# [inline (always)]
# [must_use]
pub fn ctrl_edc_vbuss_pend (& mut self) -> CtrlEdcVbussPendW < SecStatusReg0Spec > { CtrlEdcVbussPendW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu8 (& mut self) -> Nu8W < SecStatusReg0Spec > { Nu8W :: new (self , 2) } } # [doc = "Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_status_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_status_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecStatusReg0Spec ; impl crate :: RegisterSpec for SecStatusReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_status_reg0::R`](R) reader structure"]
impl crate :: Readable for SecStatusReg0Spec { } # [doc = "`write(|w| ..)` method takes [`sec_status_reg0::W`](W) writer structure"]
impl crate :: Writable for SecStatusReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_STATUS_REG0 to value 0"]
impl crate :: Resettable for SecStatusReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_ENABLE_SET_REG0 (rw) register accessor: Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_set_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_set_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_enable_set_reg0`]
module"]
# [doc (alias = "SEC_ENABLE_SET_REG0")]
pub type SecEnableSetReg0 = crate :: Reg < sec_enable_set_reg0 :: SecEnableSetReg0Spec > ; # [doc = "Interrupt Enable Set Register 0"]
pub mod sec_enable_set_reg0 { # [doc = "Register `SEC_ENABLE_SET_REG0` reader"]
pub type R = crate :: R < SecEnableSetReg0Spec > ; # [doc = "Register `SEC_ENABLE_SET_REG0` writer"]
pub type W = crate :: W < SecEnableSetReg0Spec > ; # [doc = "Field `SEC_EN_SET` reader - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type SecEnSetR = crate :: BitReader ; # [doc = "Field `SEC_EN_SET` writer - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type SecEnSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_SET` reader - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type CtrlEdcVbussEnableSetR = crate :: BitReader ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_SET` writer - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type CtrlEdcVbussEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU9` reader - 31:2\\]
Reserved"]
pub type Nu9R = crate :: FieldReader < u32 > ; # [doc = "Field `NU9` writer - 31:2\\]
Reserved"]
pub type Nu9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn sec_en_set (& self) -> SecEnSetR { SecEnSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn ctrl_edc_vbuss_enable_set (& self) -> CtrlEdcVbussEnableSetR { CtrlEdcVbussEnableSetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu9 (& self) -> Nu9R { Nu9R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn sec_en_set (& mut self) -> SecEnSetW < SecEnableSetReg0Spec > { SecEnSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn ctrl_edc_vbuss_enable_set (& mut self) -> CtrlEdcVbussEnableSetW < SecEnableSetReg0Spec > { CtrlEdcVbussEnableSetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu9 (& mut self) -> Nu9W < SecEnableSetReg0Spec > { Nu9W :: new (self , 2) } } # [doc = "Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_set_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_set_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecEnableSetReg0Spec ; impl crate :: RegisterSpec for SecEnableSetReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_enable_set_reg0::R`](R) reader structure"]
impl crate :: Readable for SecEnableSetReg0Spec { } # [doc = "`write(|w| ..)` method takes [`sec_enable_set_reg0::W`](W) writer structure"]
impl crate :: Writable for SecEnableSetReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_ENABLE_SET_REG0 to value 0"]
impl crate :: Resettable for SecEnableSetReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_ENABLE_CLR_REG0 (rw) register accessor: Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_clr_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_clr_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_enable_clr_reg0`]
module"]
# [doc (alias = "SEC_ENABLE_CLR_REG0")]
pub type SecEnableClrReg0 = crate :: Reg < sec_enable_clr_reg0 :: SecEnableClrReg0Spec > ; # [doc = "Interrupt Enable Clear Register 0"]
pub mod sec_enable_clr_reg0 { # [doc = "Register `SEC_ENABLE_CLR_REG0` reader"]
pub type R = crate :: R < SecEnableClrReg0Spec > ; # [doc = "Register `SEC_ENABLE_CLR_REG0` writer"]
pub type W = crate :: W < SecEnableClrReg0Spec > ; # [doc = "Field `SEC_EN_CLR` reader - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type SecEnClrR = crate :: BitReader ; # [doc = "Field `SEC_EN_CLR` writer - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type SecEnClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_CLR` reader - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type CtrlEdcVbussEnableClrR = crate :: BitReader ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_CLR` writer - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type CtrlEdcVbussEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU10` reader - 31:2\\]
Reserved"]
pub type Nu10R = crate :: FieldReader < u32 > ; # [doc = "Field `NU10` writer - 31:2\\]
Reserved"]
pub type Nu10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
pub fn sec_en_clr (& self) -> SecEnClrR { SecEnClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
pub fn ctrl_edc_vbuss_enable_clr (& self) -> CtrlEdcVbussEnableClrR { CtrlEdcVbussEnableClrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu10 (& self) -> Nu10R { Nu10R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn sec_en_clr (& mut self) -> SecEnClrW < SecEnableClrReg0Spec > { SecEnClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn ctrl_edc_vbuss_enable_clr (& mut self) -> CtrlEdcVbussEnableClrW < SecEnableClrReg0Spec > { CtrlEdcVbussEnableClrW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu10 (& mut self) -> Nu10W < SecEnableClrReg0Spec > { Nu10W :: new (self , 2) } } # [doc = "Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_clr_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_clr_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecEnableClrReg0Spec ; impl crate :: RegisterSpec for SecEnableClrReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_enable_clr_reg0::R`](R) reader structure"]
impl crate :: Readable for SecEnableClrReg0Spec { } # [doc = "`write(|w| ..)` method takes [`sec_enable_clr_reg0::W`](W) writer structure"]
impl crate :: Writable for SecEnableClrReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_ENABLE_CLR_REG0 to value 0"]
impl crate :: Resettable for SecEnableClrReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_EOI_REG (rw) register accessor: EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_eoi_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_eoi_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_eoi_reg`]
module"]
# [doc (alias = "DED_EOI_REG")]
pub type DedEoiReg = crate :: Reg < ded_eoi_reg :: DedEoiRegSpec > ; # [doc = "EOI Register"]
pub mod ded_eoi_reg { # [doc = "Register `DED_EOI_REG` reader"]
pub type R = crate :: R < DedEoiRegSpec > ; # [doc = "Register `DED_EOI_REG` writer"]
pub type W = crate :: W < DedEoiRegSpec > ; # [doc = "Field `DED_EOI_WR` reader - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
pub type DedEoiWrR = crate :: BitReader ; # [doc = "Field `DED_EOI_WR` writer - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
pub type DedEoiWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU11` reader - 31:1\\]
Reserved"]
pub type Nu11R = crate :: FieldReader < u32 > ; # [doc = "Field `NU11` writer - 31:1\\]
Reserved"]
pub type Nu11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
# [inline (always)]
pub fn ded_eoi_wr (& self) -> DedEoiWrR { DedEoiWrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu11 (& self) -> Nu11R { Nu11R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn ded_eoi_wr (& mut self) -> DedEoiWrW < DedEoiRegSpec > { DedEoiWrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu11 (& mut self) -> Nu11W < DedEoiRegSpec > { Nu11W :: new (self , 1) } } # [doc = "EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_eoi_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_eoi_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedEoiRegSpec ; impl crate :: RegisterSpec for DedEoiRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_eoi_reg::R`](R) reader structure"]
impl crate :: Readable for DedEoiRegSpec { } # [doc = "`write(|w| ..)` method takes [`ded_eoi_reg::W`](W) writer structure"]
impl crate :: Writable for DedEoiRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_EOI_REG to value 0"]
impl crate :: Resettable for DedEoiRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_STATUS_REG0 (rw) register accessor: Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_status_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_status_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_status_reg0`]
module"]
# [doc (alias = "DED_STATUS_REG0")]
pub type DedStatusReg0 = crate :: Reg < ded_status_reg0 :: DedStatusReg0Spec > ; # [doc = "Interrupt Status Register 0"]
pub mod ded_status_reg0 { # [doc = "Register `DED_STATUS_REG0` reader"]
pub type R = crate :: R < DedStatusReg0Spec > ; # [doc = "Register `DED_STATUS_REG0` writer"]
pub type W = crate :: W < DedStatusReg0Spec > ; # [doc = "Field `DED_PEND` reader - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
pub type DedPendR = crate :: BitReader ; # [doc = "Field `DED_PEND` writer - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
pub type DedPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRL_EDC_VBUSS_PEND` reader - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
pub type CtrlEdcVbussPendR = crate :: BitReader ; # [doc = "Field `CTRL_EDC_VBUSS_PEND` writer - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
pub type CtrlEdcVbussPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU12` reader - 31:2\\]
Reserved"]
pub type Nu12R = crate :: FieldReader < u32 > ; # [doc = "Field `NU12` writer - 31:2\\]
Reserved"]
pub type Nu12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
# [inline (always)]
pub fn ded_pend (& self) -> DedPendR { DedPendR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
# [inline (always)]
pub fn ctrl_edc_vbuss_pend (& self) -> CtrlEdcVbussPendR { CtrlEdcVbussPendR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu12 (& self) -> Nu12R { Nu12R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for msgmem_pend."]
# [inline (always)]
# [must_use]
pub fn ded_pend (& mut self) -> DedPendW < DedStatusReg0Spec > { DedPendW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for ctrl_edc_vbuss_pend."]
# [inline (always)]
# [must_use]
pub fn ctrl_edc_vbuss_pend (& mut self) -> CtrlEdcVbussPendW < DedStatusReg0Spec > { CtrlEdcVbussPendW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu12 (& mut self) -> Nu12W < DedStatusReg0Spec > { Nu12W :: new (self , 2) } } # [doc = "Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_status_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_status_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedStatusReg0Spec ; impl crate :: RegisterSpec for DedStatusReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_status_reg0::R`](R) reader structure"]
impl crate :: Readable for DedStatusReg0Spec { } # [doc = "`write(|w| ..)` method takes [`ded_status_reg0::W`](W) writer structure"]
impl crate :: Writable for DedStatusReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_STATUS_REG0 to value 0"]
impl crate :: Resettable for DedStatusReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_ENABLE_SET_REG0 (rw) register accessor: Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_set_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_set_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_enable_set_reg0`]
module"]
# [doc (alias = "DED_ENABLE_SET_REG0")]
pub type DedEnableSetReg0 = crate :: Reg < ded_enable_set_reg0 :: DedEnableSetReg0Spec > ; # [doc = "Interrupt Enable Set Register 0"]
pub mod ded_enable_set_reg0 { # [doc = "Register `DED_ENABLE_SET_REG0` reader"]
pub type R = crate :: R < DedEnableSetReg0Spec > ; # [doc = "Register `DED_ENABLE_SET_REG0` writer"]
pub type W = crate :: W < DedEnableSetReg0Spec > ; # [doc = "Field `DED_EN_SET` reader - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type DedEnSetR = crate :: BitReader ; # [doc = "Field `DED_EN_SET` writer - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type DedEnSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_SET` reader - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type CtrlEdcVbussEnableSetR = crate :: BitReader ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_SET` writer - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type CtrlEdcVbussEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU13` reader - 31:2\\]
Reserved"]
pub type Nu13R = crate :: FieldReader < u32 > ; # [doc = "Field `NU13` writer - 31:2\\]
Reserved"]
pub type Nu13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn ded_en_set (& self) -> DedEnSetR { DedEnSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn ctrl_edc_vbuss_enable_set (& self) -> CtrlEdcVbussEnableSetR { CtrlEdcVbussEnableSetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu13 (& self) -> Nu13R { Nu13R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn ded_en_set (& mut self) -> DedEnSetW < DedEnableSetReg0Spec > { DedEnSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn ctrl_edc_vbuss_enable_set (& mut self) -> CtrlEdcVbussEnableSetW < DedEnableSetReg0Spec > { CtrlEdcVbussEnableSetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu13 (& mut self) -> Nu13W < DedEnableSetReg0Spec > { Nu13W :: new (self , 2) } } # [doc = "Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_set_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_set_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedEnableSetReg0Spec ; impl crate :: RegisterSpec for DedEnableSetReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_enable_set_reg0::R`](R) reader structure"]
impl crate :: Readable for DedEnableSetReg0Spec { } # [doc = "`write(|w| ..)` method takes [`ded_enable_set_reg0::W`](W) writer structure"]
impl crate :: Writable for DedEnableSetReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_ENABLE_SET_REG0 to value 0"]
impl crate :: Resettable for DedEnableSetReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_ENABLE_CLR_REG0 (rw) register accessor: Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_clr_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_clr_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_enable_clr_reg0`]
module"]
# [doc (alias = "DED_ENABLE_CLR_REG0")]
pub type DedEnableClrReg0 = crate :: Reg < ded_enable_clr_reg0 :: DedEnableClrReg0Spec > ; # [doc = "Interrupt Enable Clear Register 0"]
pub mod ded_enable_clr_reg0 { # [doc = "Register `DED_ENABLE_CLR_REG0` reader"]
pub type R = crate :: R < DedEnableClrReg0Spec > ; # [doc = "Register `DED_ENABLE_CLR_REG0` writer"]
pub type W = crate :: W < DedEnableClrReg0Spec > ; # [doc = "Field `DED_EN_CLR` reader - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type DedEnClrR = crate :: BitReader ; # [doc = "Field `DED_EN_CLR` writer - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type DedEnClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_CLR` reader - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type CtrlEdcVbussEnableClrR = crate :: BitReader ; # [doc = "Field `CTRL_EDC_VBUSS_ENABLE_CLR` writer - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type CtrlEdcVbussEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU14` reader - 31:2\\]
Reserved"]
pub type Nu14R = crate :: FieldReader < u32 > ; # [doc = "Field `NU14` writer - 31:2\\]
Reserved"]
pub type Nu14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
pub fn ded_en_clr (& self) -> DedEnClrR { DedEnClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
pub fn ctrl_edc_vbuss_enable_clr (& self) -> CtrlEdcVbussEnableClrR { CtrlEdcVbussEnableClrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu14 (& self) -> Nu14R { Nu14R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn ded_en_clr (& mut self) -> DedEnClrW < DedEnableClrReg0Spec > { DedEnClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn ctrl_edc_vbuss_enable_clr (& mut self) -> CtrlEdcVbussEnableClrW < DedEnableClrReg0Spec > { CtrlEdcVbussEnableClrW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu14 (& mut self) -> Nu14W < DedEnableClrReg0Spec > { Nu14W :: new (self , 2) } } # [doc = "Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_clr_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_clr_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedEnableClrReg0Spec ; impl crate :: RegisterSpec for DedEnableClrReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_enable_clr_reg0::R`](R) reader structure"]
impl crate :: Readable for DedEnableClrReg0Spec { } # [doc = "`write(|w| ..)` method takes [`ded_enable_clr_reg0::W`](W) writer structure"]
impl crate :: Writable for DedEnableClrReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_ENABLE_CLR_REG0 to value 0"]
impl crate :: Resettable for DedEnableClrReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_ENABLE_SET (rw) register accessor: AGGR interrupt enable set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_enable_set`]
module"]
# [doc (alias = "AGGR_ENABLE_SET")]
pub type AggrEnableSet = crate :: Reg < aggr_enable_set :: AggrEnableSetSpec > ; # [doc = "AGGR interrupt enable set Register"]
pub mod aggr_enable_set { # [doc = "Register `AGGR_ENABLE_SET` reader"]
pub type R = crate :: R < AggrEnableSetSpec > ; # [doc = "Register `AGGR_ENABLE_SET` writer"]
pub type W = crate :: W < AggrEnableSetSpec > ; # [doc = "Field `PARITY` reader - 0:0\\]
Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 0:0\\]
Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT` reader - 1:1\\]
Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type TimeoutR = crate :: BitReader ; # [doc = "Field `TIMEOUT` writer - 1:1\\]
Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
pub type TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU15` reader - 31:2\\]
Reserved"]
pub type Nu15R = crate :: FieldReader < u32 > ; # [doc = "Field `NU15` writer - 31:2\\]
Reserved"]
pub type Nu15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu15 (& self) -> Nu15R { Nu15R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrEnableSetSpec > { ParityW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrEnableSetSpec > { TimeoutW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu15 (& mut self) -> Nu15W < AggrEnableSetSpec > { Nu15W :: new (self , 2) } } # [doc = "AGGR interrupt enable set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrEnableSetSpec ; impl crate :: RegisterSpec for AggrEnableSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_enable_set::R`](R) reader structure"]
impl crate :: Readable for AggrEnableSetSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_enable_set::W`](W) writer structure"]
impl crate :: Writable for AggrEnableSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_ENABLE_SET to value 0"]
impl crate :: Resettable for AggrEnableSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_ENABLE_CLR (rw) register accessor: AGGR interrupt enable clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_enable_clr`]
module"]
# [doc (alias = "AGGR_ENABLE_CLR")]
pub type AggrEnableClr = crate :: Reg < aggr_enable_clr :: AggrEnableClrSpec > ; # [doc = "AGGR interrupt enable clear Register"]
pub mod aggr_enable_clr { # [doc = "Register `AGGR_ENABLE_CLR` reader"]
pub type R = crate :: R < AggrEnableClrSpec > ; # [doc = "Register `AGGR_ENABLE_CLR` writer"]
pub type W = crate :: W < AggrEnableClrSpec > ; # [doc = "Field `PARITY` reader - 0:0\\]
Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 0:0\\]
Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT` reader - 1:1\\]
Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type TimeoutR = crate :: BitReader ; # [doc = "Field `TIMEOUT` writer - 1:1\\]
Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
pub type TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU16` reader - 31:2\\]
Reserved"]
pub type Nu16R = crate :: FieldReader < u32 > ; # [doc = "Field `NU16` writer - 31:2\\]
Reserved"]
pub type Nu16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu16 (& self) -> Nu16R { Nu16R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrEnableClrSpec > { ParityW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0."]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrEnableClrSpec > { TimeoutW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu16 (& mut self) -> Nu16W < AggrEnableClrSpec > { Nu16W :: new (self , 2) } } # [doc = "AGGR interrupt enable clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrEnableClrSpec ; impl crate :: RegisterSpec for AggrEnableClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_enable_clr::R`](R) reader structure"]
impl crate :: Readable for AggrEnableClrSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_enable_clr::W`](W) writer structure"]
impl crate :: Writable for AggrEnableClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_ENABLE_CLR to value 0"]
impl crate :: Resettable for AggrEnableClrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_STATUS_SET (rw) register accessor: AGGR interrupt status set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_status_set`]
module"]
# [doc (alias = "AGGR_STATUS_SET")]
pub type AggrStatusSet = crate :: Reg < aggr_status_set :: AggrStatusSetSpec > ; # [doc = "AGGR interrupt status set Register"]
pub mod aggr_status_set { # [doc = "Register `AGGR_STATUS_SET` reader"]
pub type R = crate :: R < AggrStatusSetSpec > ; # [doc = "Register `AGGR_STATUS_SET` writer"]
pub type W = crate :: W < AggrStatusSetSpec > ; # [doc = "Field `PARITY` reader - 1:0\\]
Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
pub type ParityR = crate :: FieldReader ; # [doc = "Field `PARITY` writer - 1:0\\]
Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
pub type ParityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIMEOUT` reader - 3:2\\]
Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
pub type TimeoutR = crate :: FieldReader ; # [doc = "Field `TIMEOUT` writer - 3:2\\]
Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
pub type TimeoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU17` reader - 31:4\\]
Reserved"]
pub type Nu17R = crate :: FieldReader < u32 > ; # [doc = "Field `NU17` writer - 31:4\\]
Reserved"]
pub type Nu17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Reserved"]
# [inline (always)]
pub fn nu17 (& self) -> Nu17R { Nu17R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrStatusSetSpec > { ParityW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrStatusSetSpec > { TimeoutW :: new (self , 2) } # [doc = "Bits 4:31 - 31:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu17 (& mut self) -> Nu17W < AggrStatusSetSpec > { Nu17W :: new (self , 4) } } # [doc = "AGGR interrupt status set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrStatusSetSpec ; impl crate :: RegisterSpec for AggrStatusSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_status_set::R`](R) reader structure"]
impl crate :: Readable for AggrStatusSetSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_status_set::W`](W) writer structure"]
impl crate :: Writable for AggrStatusSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_STATUS_SET to value 0"]
impl crate :: Resettable for AggrStatusSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_STATUS_CLR (rw) register accessor: AGGR interrupt status clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_status_clr`]
module"]
# [doc (alias = "AGGR_STATUS_CLR")]
pub type AggrStatusClr = crate :: Reg < aggr_status_clr :: AggrStatusClrSpec > ; # [doc = "AGGR interrupt status clear Register"]
pub mod aggr_status_clr { # [doc = "Register `AGGR_STATUS_CLR` reader"]
pub type R = crate :: R < AggrStatusClrSpec > ; # [doc = "Register `AGGR_STATUS_CLR` writer"]
pub type W = crate :: W < AggrStatusClrSpec > ; # [doc = "Field `PARITY` reader - 1:0\\]
Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
pub type ParityR = crate :: FieldReader ; # [doc = "Field `PARITY` writer - 1:0\\]
Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
pub type ParityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIMEOUT` reader - 3:2\\]
Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
pub type TimeoutR = crate :: FieldReader ; # [doc = "Field `TIMEOUT` writer - 3:2\\]
Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
pub type TimeoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU18` reader - 31:4\\]
Reserved"]
pub type Nu18R = crate :: FieldReader < u32 > ; # [doc = "Field `NU18` writer - 31:4\\]
Reserved"]
pub type Nu18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Reserved"]
# [inline (always)]
pub fn nu18 (& self) -> Nu18R { Nu18R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrStatusClrSpec > { ParityW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field."]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrStatusClrSpec > { TimeoutW :: new (self , 2) } # [doc = "Bits 4:31 - 31:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu18 (& mut self) -> Nu18W < AggrStatusClrSpec > { Nu18W :: new (self , 4) } } # [doc = "AGGR interrupt status clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrStatusClrSpec ; impl crate :: RegisterSpec for AggrStatusClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_status_clr::R`](R) reader structure"]
impl crate :: Readable for AggrStatusClrSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_status_clr::W`](W) writer structure"]
impl crate :: Writable for AggrStatusClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_STATUS_CLR to value 0"]
impl crate :: Resettable for AggrStatusClrSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Register test environment"]
pub struct TptcA0 { _marker : PhantomData < * const () > } unsafe impl Send for TptcA0 { } impl TptcA0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tptc_a0 :: RegisterBlock = 0x5400_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tptc_a0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TptcA0 { type Target = tptc_a0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TptcA0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TptcA0") . finish () } } # [doc = "Register test environment"]
pub mod tptc_a0 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , tccfg : Tccfg , _reserved2 : [u8 ; 0xf8]
, tcstat : Tcstat , intstat : Intstat , inten : Inten , intclr : Intclr , intcmd : Intcmd , _reserved7 : [u8 ; 0x0c]
, errstat : Errstat , erren : Erren , errclr : Errclr , errdet : Errdet , errcmd : Errcmd , _reserved12 : [u8 ; 0x0c]
, rdrate : Rdrate , _reserved13 : [u8 ; 0xbc]
, popt : Popt , psrc : Psrc , pcnt : Pcnt , pdst : Pdst , pbidx : Pbidx , pmpprxy : Pmpprxy , _reserved19 : [u8 ; 0x28]
, saopt : Saopt , sasrc : Sasrc , sacnt : Sacnt , sadst : Sadst , sabidx : Sabidx , sampprxy : Sampprxy , sacntrld : Sacntrld , sasrcbref : Sasrcbref , sadstbref : Sadstbref , sabcnt : Sabcnt , _reserved29 : [u8 ; 0x18]
, dfcntrld : Dfcntrld , dfsrcbref : Dfsrcbref , _reserved31 : [u8 ; 0x78]
, dfopt0 : Dfopt0 , dfsrc0 : Dfsrc0 , dfacnt0 : Dfacnt0 , dfdst0 : Dfdst0 , dfbidx0 : Dfbidx0 , dfmpprxy0 : Dfmpprxy0 , dfbcnt0 : Dfbcnt0 , _reserved38 : [u8 ; 0x24]
, dfopt1 : Dfopt1 , dfsrc1 : Dfsrc1 , dfacnt1 : Dfacnt1 , dfdst1 : Dfdst1 , dfbidx1 : Dfbidx1 , dfmpprxy1 : Dfmpprxy1 , dfbcnt1 : Dfbcnt1 , } impl RegisterBlock { # [doc = "0x00 - Peripheral ID Register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - TC Configuration Register"]
# [inline (always)]
pub const fn tccfg (& self) -> & Tccfg { & self . tccfg } # [doc = "0x100 - TC Status Register"]
# [inline (always)]
pub const fn tcstat (& self) -> & Tcstat { & self . tcstat } # [doc = "0x104 - Interrupt Status Register"]
# [inline (always)]
pub const fn intstat (& self) -> & Intstat { & self . intstat } # [doc = "0x108 - Interrupt Enable Register"]
# [inline (always)]
pub const fn inten (& self) -> & Inten { & self . inten } # [doc = "0x10c - Interrupt Clear Register"]
# [inline (always)]
pub const fn intclr (& self) -> & Intclr { & self . intclr } # [doc = "0x110 - Interrupt Command Register"]
# [inline (always)]
pub const fn intcmd (& self) -> & Intcmd { & self . intcmd } # [doc = "0x120 - Error Status Register"]
# [inline (always)]
pub const fn errstat (& self) -> & Errstat { & self . errstat } # [doc = "0x124 - Error Enable Register"]
# [inline (always)]
pub const fn erren (& self) -> & Erren { & self . erren } # [doc = "0x128 - Error Clear Register"]
# [inline (always)]
pub const fn errclr (& self) -> & Errclr { & self . errclr } # [doc = "0x12c - Error Details Register"]
# [inline (always)]
pub const fn errdet (& self) -> & Errdet { & self . errdet } # [doc = "0x130 - Error Command Register"]
# [inline (always)]
pub const fn errcmd (& self) -> & Errcmd { & self . errcmd } # [doc = "0x140 - Read Rate Register"]
# [inline (always)]
pub const fn rdrate (& self) -> & Rdrate { & self . rdrate } # [doc = "0x200 - Prog Set Options"]
# [inline (always)]
pub const fn popt (& self) -> & Popt { & self . popt } # [doc = "0x204 - Prog Set Src Address"]
# [inline (always)]
pub const fn psrc (& self) -> & Psrc { & self . psrc } # [doc = "0x208 - Prog Set Count"]
# [inline (always)]
pub const fn pcnt (& self) -> & Pcnt { & self . pcnt } # [doc = "0x20c - Prog Set Dst Address"]
# [inline (always)]
pub const fn pdst (& self) -> & Pdst { & self . pdst } # [doc = "0x210 - Prog Set B-Dim Idx"]
# [inline (always)]
pub const fn pbidx (& self) -> & Pbidx { & self . pbidx } # [doc = "0x214 - Prog Set Mem Protect Proxy"]
# [inline (always)]
pub const fn pmpprxy (& self) -> & Pmpprxy { & self . pmpprxy } # [doc = "0x240 - Src Actv Set Options"]
# [inline (always)]
pub const fn saopt (& self) -> & Saopt { & self . saopt } # [doc = "0x244 - Src Actv Set Src Address"]
# [inline (always)]
pub const fn sasrc (& self) -> & Sasrc { & self . sasrc } # [doc = "0x248 - Src Actv Set A-Count"]
# [inline (always)]
pub const fn sacnt (& self) -> & Sacnt { & self . sacnt } # [doc = "0x24c - Src Actv Set Dst Address"]
# [inline (always)]
pub const fn sadst (& self) -> & Sadst { & self . sadst } # [doc = "0x250 - Src Actv Set B-Dim Idx"]
# [inline (always)]
pub const fn sabidx (& self) -> & Sabidx { & self . sabidx } # [doc = "0x254 - Src Actv Set Mem Protect Proxy"]
# [inline (always)]
pub const fn sampprxy (& self) -> & Sampprxy { & self . sampprxy } # [doc = "0x258 - Src Actv Set Cnt Reload"]
# [inline (always)]
pub const fn sacntrld (& self) -> & Sacntrld { & self . sacntrld } # [doc = "0x25c - Src Actv Set Src Addr B-Reference"]
# [inline (always)]
pub const fn sasrcbref (& self) -> & Sasrcbref { & self . sasrcbref } # [doc = "0x260 - Src Actv Set Dst Addr B-Reference"]
# [inline (always)]
pub const fn sadstbref (& self) -> & Sadstbref { & self . sadstbref } # [doc = "0x264 - Src Actv Set B-Count"]
# [inline (always)]
pub const fn sabcnt (& self) -> & Sabcnt { & self . sabcnt } # [doc = "0x280 - Dst FIFO Set Cnt Reload"]
# [inline (always)]
pub const fn dfcntrld (& self) -> & Dfcntrld { & self . dfcntrld } # [doc = "0x284 - Dst FIFO Set Src Addr B-Reference"]
# [inline (always)]
pub const fn dfsrcbref (& self) -> & Dfsrcbref { & self . dfsrcbref } # [doc = "0x300 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt0 (& self) -> & Dfopt0 { & self . dfopt0 } # [doc = "0x304 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc0 (& self) -> & Dfsrc0 { & self . dfsrc0 } # [doc = "0x308 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt0 (& self) -> & Dfacnt0 { & self . dfacnt0 } # [doc = "0x30c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst0 (& self) -> & Dfdst0 { & self . dfdst0 } # [doc = "0x310 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx0 (& self) -> & Dfbidx0 { & self . dfbidx0 } # [doc = "0x314 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy0 (& self) -> & Dfmpprxy0 { & self . dfmpprxy0 } # [doc = "0x318 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt0 (& self) -> & Dfbcnt0 { & self . dfbcnt0 } # [doc = "0x340 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt1 (& self) -> & Dfopt1 { & self . dfopt1 } # [doc = "0x344 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc1 (& self) -> & Dfsrc1 { & self . dfsrc1 } # [doc = "0x348 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt1 (& self) -> & Dfacnt1 { & self . dfacnt1 } # [doc = "0x34c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst1 (& self) -> & Dfdst1 { & self . dfdst1 } # [doc = "0x350 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx1 (& self) -> & Dfbidx1 { & self . dfbidx1 } # [doc = "0x354 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy1 (& self) -> & Dfmpprxy1 { & self . dfmpprxy1 } # [doc = "0x358 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt1 (& self) -> & Dfbcnt1 { & self . dfbcnt1 } } # [doc = "PID (rw) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "Peripheral ID Register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR_REVISION` reader - 5:0\\]
Minor Revision"]
pub type MinorRevisionR = crate :: FieldReader ; # [doc = "Field `MINOR_REVISION` writer - 5:0\\]
Minor Revision"]
pub type MinorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM_REVISION_FIELD` reader - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldR = crate :: FieldReader ; # [doc = "Field `CUSTOM_REVISION_FIELD` writer - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR_REVISION` reader - 10:8\\]
Major Revision"]
pub type MajorRevisionR = crate :: FieldReader ; # [doc = "Field `MAJOR_REVISION` writer - 10:8\\]
Major Revision"]
pub type MajorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL_VERSION` reader - 15:11\\]
RTL Version"]
pub type RtlVersionR = crate :: FieldReader ; # [doc = "Field `RTL_VERSION` writer - 15:11\\]
RTL Version"]
pub type RtlVersionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNCTION_INDICATES_A` reader - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNCTION_INDICATES_A` writer - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `PID_SCHEME` reader - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeR = crate :: FieldReader ; # [doc = "Field `PID_SCHEME` writer - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
pub fn minor_revision (& self) -> MinorRevisionR { MinorRevisionR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
pub fn custom_revision_field (& self) -> CustomRevisionFieldR { CustomRevisionFieldR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
pub fn major_revision (& self) -> MajorRevisionR { MajorRevisionR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
pub fn rtl_version (& self) -> RtlVersionR { RtlVersionR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
pub fn function_indicates_a (& self) -> FunctionIndicatesAR { FunctionIndicatesAR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
pub fn pid_scheme (& self) -> PidSchemeR { PidSchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
# [must_use]
pub fn minor_revision (& mut self) -> MinorRevisionW < PidSpec > { MinorRevisionW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
# [must_use]
pub fn custom_revision_field (& mut self) -> CustomRevisionFieldW < PidSpec > { CustomRevisionFieldW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
# [must_use]
pub fn major_revision (& mut self) -> MajorRevisionW < PidSpec > { MajorRevisionW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
# [must_use]
pub fn rtl_version (& mut self) -> RtlVersionW < PidSpec > { RtlVersionW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
# [must_use]
pub fn function_indicates_a (& mut self) -> FunctionIndicatesAW < PidSpec > { FunctionIndicatesAW :: new (self , 16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
# [must_use]
pub fn pid_scheme (& mut self) -> PidSchemeW < PidSpec > { PidSchemeW :: new (self , 30) } } # [doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCCFG (rw) register accessor: TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tccfg`]
module"]
# [doc (alias = "TCCFG")]
pub type Tccfg = crate :: Reg < tccfg :: TccfgSpec > ; # [doc = "TC Configuration Register"]
pub mod tccfg { # [doc = "Register `TCCFG` reader"]
pub type R = crate :: R < TccfgSpec > ; # [doc = "Register `TCCFG` writer"]
pub type W = crate :: W < TccfgSpec > ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` reader - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationR = crate :: FieldReader ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` writer - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` reader - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationR = crate :: FieldReader ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` writer - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DST_REGISTER_FIFO` reader - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoR = crate :: FieldReader ; # [doc = "Field `DST_REGISTER_FIFO` writer - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
pub fn fifo_size_parameterization (& self) -> FifoSizeParameterizationR { FifoSizeParameterizationR :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
pub fn bus_width_parameterization (& self) -> BusWidthParameterizationR { BusWidthParameterizationR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
pub fn dst_register_fifo (& self) -> DstRegisterFifoR { DstRegisterFifoR :: new (((self . bits >> 8) & 3) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
# [must_use]
pub fn fifo_size_parameterization (& mut self) -> FifoSizeParameterizationW < TccfgSpec > { FifoSizeParameterizationW :: new (self , 0) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
# [must_use]
pub fn bus_width_parameterization (& mut self) -> BusWidthParameterizationW < TccfgSpec > { BusWidthParameterizationW :: new (self , 4) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
# [must_use]
pub fn dst_register_fifo (& mut self) -> DstRegisterFifoW < TccfgSpec > { DstRegisterFifoW :: new (self , 8) } } # [doc = "TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TccfgSpec ; impl crate :: RegisterSpec for TccfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tccfg::R`](R) reader structure"]
impl crate :: Readable for TccfgSpec { } # [doc = "`write(|w| ..)` method takes [`tccfg::W`](W) writer structure"]
impl crate :: Writable for TccfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCCFG to value 0"]
impl crate :: Resettable for TccfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCSTAT (rw) register accessor: TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcstat`]
module"]
# [doc (alias = "TCSTAT")]
pub type Tcstat = crate :: Reg < tcstat :: TcstatSpec > ; # [doc = "TC Status Register"]
pub mod tcstat { # [doc = "Register `TCSTAT` reader"]
pub type R = crate :: R < TcstatSpec > ; # [doc = "Register `TCSTAT` writer"]
pub type W = crate :: W < TcstatSpec > ; # [doc = "Field `PROGRAM_REGISTER_SET` reader - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetR = crate :: BitReader ; # [doc = "Field `PROGRAM_REGISTER_SET` writer - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOURCE_ACTIVE_STATE` reader - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateR = crate :: BitReader ; # [doc = "Field `SOURCE_ACTIVE_STATE` writer - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WRITE_STATUS_ACTIVE` reader - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveR = crate :: BitReader ; # [doc = "Field `WRITE_STATUS_ACTIVE` writer - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ACTIVE_STATE` reader - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateR = crate :: FieldReader ; # [doc = "Field `DESTINATION_ACTIVE_STATE` writer - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CHANNEL_ACTIVE` reader - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveR = crate :: BitReader ; # [doc = "Field `CHANNEL_ACTIVE` writer - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DST_FIFO_START` reader - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartR = crate :: FieldReader ; # [doc = "Field `DST_FIFO_START` writer - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
pub fn program_register_set (& self) -> ProgramRegisterSetR { ProgramRegisterSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
pub fn source_active_state (& self) -> SourceActiveStateR { SourceActiveStateR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
pub fn write_status_active (& self) -> WriteStatusActiveR { WriteStatusActiveR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
pub fn destination_active_state (& self) -> DestinationActiveStateR { DestinationActiveStateR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
pub fn channel_active (& self) -> ChannelActiveR { ChannelActiveR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
pub fn dst_fifo_start (& self) -> DstFifoStartR { DstFifoStartR :: new (((self . bits >> 12) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
# [must_use]
pub fn program_register_set (& mut self) -> ProgramRegisterSetW < TcstatSpec > { ProgramRegisterSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
# [must_use]
pub fn source_active_state (& mut self) -> SourceActiveStateW < TcstatSpec > { SourceActiveStateW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
# [must_use]
pub fn write_status_active (& mut self) -> WriteStatusActiveW < TcstatSpec > { WriteStatusActiveW :: new (self , 2) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
# [must_use]
pub fn destination_active_state (& mut self) -> DestinationActiveStateW < TcstatSpec > { DestinationActiveStateW :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
# [must_use]
pub fn channel_active (& mut self) -> ChannelActiveW < TcstatSpec > { ChannelActiveW :: new (self , 8) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
# [must_use]
pub fn dst_fifo_start (& mut self) -> DstFifoStartW < TcstatSpec > { DstFifoStartW :: new (self , 12) } } # [doc = "TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcstatSpec ; impl crate :: RegisterSpec for TcstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tcstat::R`](R) reader structure"]
impl crate :: Readable for TcstatSpec { } # [doc = "`write(|w| ..)` method takes [`tcstat::W`](W) writer structure"]
impl crate :: Writable for TcstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCSTAT to value 0"]
impl crate :: Resettable for TcstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTSTAT (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstat`]
module"]
# [doc (alias = "INTSTAT")]
pub type Intstat = crate :: Reg < intstat :: IntstatSpec > ; # [doc = "Interrupt Status Register"]
pub mod intstat { # [doc = "Register `INTSTAT` reader"]
pub type R = crate :: R < IntstatSpec > ; # [doc = "Register `INTSTAT` writer"]
pub type W = crate :: W < IntstatSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntstatSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntstatSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntstatSpec ; impl crate :: RegisterSpec for IntstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intstat::R`](R) reader structure"]
impl crate :: Readable for IntstatSpec { } # [doc = "`write(|w| ..)` method takes [`intstat::W`](W) writer structure"]
impl crate :: Writable for IntstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTSTAT to value 0"]
impl crate :: Resettable for IntstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
# [doc (alias = "INTEN")]
pub type Inten = crate :: Reg < inten :: IntenSpec > ; # [doc = "Interrupt Enable Register"]
pub mod inten { # [doc = "Register `INTEN` reader"]
pub type R = crate :: R < IntenSpec > ; # [doc = "Register `INTEN` writer"]
pub type W = crate :: W < IntenSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntenSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntenSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenSpec ; impl crate :: RegisterSpec for IntenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`inten::R`](R) reader structure"]
impl crate :: Readable for IntenSpec { } # [doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
impl crate :: Writable for IntenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTEN to value 0"]
impl crate :: Resettable for IntenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCLR (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`]
module"]
# [doc (alias = "INTCLR")]
pub type Intclr = crate :: Reg < intclr :: IntclrSpec > ; # [doc = "Interrupt Clear Register"]
pub mod intclr { # [doc = "Register `INTCLR` reader"]
pub type R = crate :: R < IntclrSpec > ; # [doc = "Register `INTCLR` writer"]
pub type W = crate :: W < IntclrSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntclrSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntclrSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntclrSpec ; impl crate :: RegisterSpec for IntclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intclr::R`](R) reader structure"]
impl crate :: Readable for IntclrSpec { } # [doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"]
impl crate :: Writable for IntclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCLR to value 0"]
impl crate :: Resettable for IntclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCMD (rw) register accessor: Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intcmd`]
module"]
# [doc (alias = "INTCMD")]
pub type Intcmd = crate :: Reg < intcmd :: IntcmdSpec > ; # [doc = "Interrupt Command Register"]
pub mod intcmd { # [doc = "Register `INTCMD` reader"]
pub type R = crate :: R < IntcmdSpec > ; # [doc = "Register `INTCMD` writer"]
pub type W = crate :: W < IntcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_INTERRUPT` reader - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptR = crate :: BitReader ; # [doc = "Field `SET_TPTC_INTERRUPT` writer - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_interrupt (& self) -> SetTptcInterruptR { SetTptcInterruptR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < IntcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_interrupt (& mut self) -> SetTptcInterruptW < IntcmdSpec > { SetTptcInterruptW :: new (self , 1) } } # [doc = "Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntcmdSpec ; impl crate :: RegisterSpec for IntcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intcmd::R`](R) reader structure"]
impl crate :: Readable for IntcmdSpec { } # [doc = "`write(|w| ..)` method takes [`intcmd::W`](W) writer structure"]
impl crate :: Writable for IntcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCMD to value 0"]
impl crate :: Resettable for IntcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRSTAT (rw) register accessor: Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errstat`]
module"]
# [doc (alias = "ERRSTAT")]
pub type Errstat = crate :: Reg < errstat :: ErrstatSpec > ; # [doc = "Error Status Register"]
pub mod errstat { # [doc = "Register `ERRSTAT` reader"]
pub type R = crate :: R < ErrstatSpec > ; # [doc = "Register `ERRSTAT` writer"]
pub type W = crate :: W < ErrstatSpec > ; # [doc = "Field `BUS_ERROR_EVENT` reader - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventR = crate :: BitReader ; # [doc = "Field `BUS_ERROR_EVENT` writer - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_ERROR` reader - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorR = crate :: BitReader ; # [doc = "Field `TR_ERROR` writer - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMR_ADDRESS_ERROR` reader - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorR = crate :: BitReader ; # [doc = "Field `MMR_ADDRESS_ERROR` writer - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
pub fn bus_error_event (& self) -> BusErrorEventR { BusErrorEventR :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
pub fn tr_error (& self) -> TrErrorR { TrErrorR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
pub fn mmr_address_error (& self) -> MmrAddressErrorR { MmrAddressErrorR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
# [must_use]
pub fn bus_error_event (& mut self) -> BusErrorEventW < ErrstatSpec > { BusErrorEventW :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn tr_error (& mut self) -> TrErrorW < ErrstatSpec > { TrErrorW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn mmr_address_error (& mut self) -> MmrAddressErrorW < ErrstatSpec > { MmrAddressErrorW :: new (self , 3) } } # [doc = "Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrstatSpec ; impl crate :: RegisterSpec for ErrstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errstat::R`](R) reader structure"]
impl crate :: Readable for ErrstatSpec { } # [doc = "`write(|w| ..)` method takes [`errstat::W`](W) writer structure"]
impl crate :: Writable for ErrstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRSTAT to value 0"]
impl crate :: Resettable for ErrstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERREN (rw) register accessor: Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erren`]
module"]
# [doc (alias = "ERREN")]
pub type Erren = crate :: Reg < erren :: ErrenSpec > ; # [doc = "Error Enable Register"]
pub mod erren { # [doc = "Register `ERREN` reader"]
pub type R = crate :: R < ErrenSpec > ; # [doc = "Register `ERREN` writer"]
pub type W = crate :: W < ErrenSpec > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` reader - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` writer - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` reader - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` writer - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR` reader - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR` writer - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_2 (& self) -> InterruptEnableFor2R { InterruptEnableFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_1 (& self) -> InterruptEnableFor1R { InterruptEnableFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for (& self) -> InterruptEnableForR { InterruptEnableForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_2 (& mut self) -> InterruptEnableFor2W < ErrenSpec > { InterruptEnableFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_1 (& mut self) -> InterruptEnableFor1W < ErrenSpec > { InterruptEnableFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for (& mut self) -> InterruptEnableForW < ErrenSpec > { InterruptEnableForW :: new (self , 3) } } # [doc = "Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrenSpec ; impl crate :: RegisterSpec for ErrenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erren::R`](R) reader structure"]
impl crate :: Readable for ErrenSpec { } # [doc = "`write(|w| ..)` method takes [`erren::W`](W) writer structure"]
impl crate :: Writable for ErrenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERREN to value 0"]
impl crate :: Resettable for ErrenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCLR (rw) register accessor: Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errclr`]
module"]
# [doc (alias = "ERRCLR")]
pub type Errclr = crate :: Reg < errclr :: ErrclrSpec > ; # [doc = "Error Clear Register"]
pub mod errclr { # [doc = "Register `ERRCLR` reader"]
pub type R = crate :: R < ErrclrSpec > ; # [doc = "Register `ERRCLR` writer"]
pub type W = crate :: W < ErrclrSpec > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` reader - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` writer - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` reader - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` writer - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR` reader - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR` writer - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_2 (& self) -> InterruptClearFor2R { InterruptClearFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_1 (& self) -> InterruptClearFor1R { InterruptClearFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for (& self) -> InterruptClearForR { InterruptClearForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_2 (& mut self) -> InterruptClearFor2W < ErrclrSpec > { InterruptClearFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_1 (& mut self) -> InterruptClearFor1W < ErrclrSpec > { InterruptClearFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for (& mut self) -> InterruptClearForW < ErrclrSpec > { InterruptClearForW :: new (self , 3) } } # [doc = "Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrclrSpec ; impl crate :: RegisterSpec for ErrclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errclr::R`](R) reader structure"]
impl crate :: Readable for ErrclrSpec { } # [doc = "`write(|w| ..)` method takes [`errclr::W`](W) writer structure"]
impl crate :: Writable for ErrclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCLR to value 0"]
impl crate :: Resettable for ErrclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRDET (rw) register accessor: Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errdet`]
module"]
# [doc (alias = "ERRDET")]
pub type Errdet = crate :: Reg < errdet :: ErrdetSpec > ; # [doc = "Error Details Register"]
pub mod errdet { # [doc = "Register `ERRDET` reader"]
pub type R = crate :: R < ErrdetSpec > ; # [doc = "Register `ERRDET` writer"]
pub type W = crate :: W < ErrdetSpec > ; # [doc = "Field `TRANSACTION_STATUS` reader - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusR = crate :: FieldReader ; # [doc = "Field `TRANSACTION_STATUS` writer - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` reader - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` writer - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` reader - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` writer - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
pub fn transaction_status (& self) -> TransactionStatusR { TransactionStatusR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcinten (& self) -> ContainsTheOptTcintenR { ContainsTheOptTcintenR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcchen (& self) -> ContainsTheOptTcchenR { ContainsTheOptTcchenR :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
# [must_use]
pub fn transaction_status (& mut self) -> TransactionStatusW < ErrdetSpec > { TransactionStatusW :: new (self , 0) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < ErrdetSpec > { TransferCompleteCodeW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcinten (& mut self) -> ContainsTheOptTcintenW < ErrdetSpec > { ContainsTheOptTcintenW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcchen (& mut self) -> ContainsTheOptTcchenW < ErrdetSpec > { ContainsTheOptTcchenW :: new (self , 17) } } # [doc = "Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrdetSpec ; impl crate :: RegisterSpec for ErrdetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errdet::R`](R) reader structure"]
impl crate :: Readable for ErrdetSpec { } # [doc = "`write(|w| ..)` method takes [`errdet::W`](W) writer structure"]
impl crate :: Writable for ErrdetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRDET to value 0"]
impl crate :: Resettable for ErrdetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCMD (rw) register accessor: Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errcmd`]
module"]
# [doc (alias = "ERRCMD")]
pub type Errcmd = crate :: Reg < errcmd :: ErrcmdSpec > ; # [doc = "Error Command Register"]
pub mod errcmd { # [doc = "Register `ERRCMD` reader"]
pub type R = crate :: R < ErrcmdSpec > ; # [doc = "Register `ERRCMD` writer"]
pub type W = crate :: W < ErrcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_ERROR` reader - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorR = crate :: BitReader ; # [doc = "Field `SET_TPTC_ERROR` writer - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_error (& self) -> SetTptcErrorR { SetTptcErrorR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < ErrcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_error (& mut self) -> SetTptcErrorW < ErrcmdSpec > { SetTptcErrorW :: new (self , 1) } } # [doc = "Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrcmdSpec ; impl crate :: RegisterSpec for ErrcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errcmd::R`](R) reader structure"]
impl crate :: Readable for ErrcmdSpec { } # [doc = "`write(|w| ..)` method takes [`errcmd::W`](W) writer structure"]
impl crate :: Writable for ErrcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCMD to value 0"]
impl crate :: Resettable for ErrcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RDRATE (rw) register accessor: Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdrate`]
module"]
# [doc (alias = "RDRATE")]
pub type Rdrate = crate :: Reg < rdrate :: RdrateSpec > ; # [doc = "Read Rate Register"]
pub mod rdrate { # [doc = "Register `RDRATE` reader"]
pub type R = crate :: R < RdrateSpec > ; # [doc = "Register `RDRATE` writer"]
pub type W = crate :: W < RdrateSpec > ; # [doc = "Field `READ_RATE_CONTROL` reader - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlR = crate :: FieldReader ; # [doc = "Field `READ_RATE_CONTROL` writer - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
pub fn read_rate_control (& self) -> ReadRateControlR { ReadRateControlR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
# [must_use]
pub fn read_rate_control (& mut self) -> ReadRateControlW < RdrateSpec > { ReadRateControlW :: new (self , 0) } } # [doc = "Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrateSpec ; impl crate :: RegisterSpec for RdrateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rdrate::R`](R) reader structure"]
impl crate :: Readable for RdrateSpec { } # [doc = "`write(|w| ..)` method takes [`rdrate::W`](W) writer structure"]
impl crate :: Writable for RdrateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RDRATE to value 0"]
impl crate :: Resettable for RdrateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "POPT (rw) register accessor: Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@popt`]
module"]
# [doc (alias = "POPT")]
pub type Popt = crate :: Reg < popt :: PoptSpec > ; # [doc = "Prog Set Options"]
pub mod popt { # [doc = "Register `POPT` reader"]
pub type R = crate :: R < PoptSpec > ; # [doc = "Register `POPT` writer"]
pub type W = crate :: W < PoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < PoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < PoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < PoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < PoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < PoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < PoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < PoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < PoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PoptSpec ; impl crate :: RegisterSpec for PoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`popt::R`](R) reader structure"]
impl crate :: Readable for PoptSpec { } # [doc = "`write(|w| ..)` method takes [`popt::W`](W) writer structure"]
impl crate :: Writable for PoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets POPT to value 0"]
impl crate :: Resettable for PoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSRC (rw) register accessor: Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psrc`]
module"]
# [doc (alias = "PSRC")]
pub type Psrc = crate :: Reg < psrc :: PsrcSpec > ; # [doc = "Prog Set Src Address"]
pub mod psrc { # [doc = "Register `PSRC` reader"]
pub type R = crate :: R < PsrcSpec > ; # [doc = "Register `PSRC` writer"]
pub type W = crate :: W < PsrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR` reader - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR` writer - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
pub fn source_address_for (& self) -> SourceAddressForR { SourceAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for (& mut self) -> SourceAddressForW < PsrcSpec > { SourceAddressForW :: new (self , 0) } } # [doc = "Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsrcSpec ; impl crate :: RegisterSpec for PsrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`psrc::R`](R) reader structure"]
impl crate :: Readable for PsrcSpec { } # [doc = "`write(|w| ..)` method takes [`psrc::W`](W) writer structure"]
impl crate :: Writable for PsrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSRC to value 0"]
impl crate :: Resettable for PsrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCNT (rw) register accessor: Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcnt`]
module"]
# [doc (alias = "PCNT")]
pub type Pcnt = crate :: Reg < pcnt :: PcntSpec > ; # [doc = "Prog Set Count"]
pub mod pcnt { # [doc = "Register `PCNT` reader"]
pub type R = crate :: R < PcntSpec > ; # [doc = "Register `PCNT` writer"]
pub type W = crate :: W < PcntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` reader - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` writer - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
pub fn bdimension_count__number (& self) -> BdimensionCount_NumberR { BdimensionCount_NumberR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < PcntSpec > { AdimensionCount_NumberW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
# [must_use]
pub fn bdimension_count__number (& mut self) -> BdimensionCount_NumberW < PcntSpec > { BdimensionCount_NumberW :: new (self , 16) } } # [doc = "Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcntSpec ; impl crate :: RegisterSpec for PcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcnt::R`](R) reader structure"]
impl crate :: Readable for PcntSpec { } # [doc = "`write(|w| ..)` method takes [`pcnt::W`](W) writer structure"]
impl crate :: Writable for PcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCNT to value 0"]
impl crate :: Resettable for PcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PDST (rw) register accessor: Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdst`]
module"]
# [doc (alias = "PDST")]
pub type Pdst = crate :: Reg < pdst :: PdstSpec > ; # [doc = "Prog Set Dst Address"]
pub mod pdst { # [doc = "Register `PDST` reader"]
pub type R = crate :: R < PdstSpec > ; # [doc = "Register `PDST` writer"]
pub type W = crate :: W < PdstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` reader - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` writer - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
pub fn destination_address_for (& self) -> DestinationAddressForR { DestinationAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for (& mut self) -> DestinationAddressForW < PdstSpec > { DestinationAddressForW :: new (self , 0) } } # [doc = "Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PdstSpec ; impl crate :: RegisterSpec for PdstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pdst::R`](R) reader structure"]
impl crate :: Readable for PdstSpec { } # [doc = "`write(|w| ..)` method takes [`pdst::W`](W) writer structure"]
impl crate :: Writable for PdstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PDST to value 0"]
impl crate :: Resettable for PdstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIDX (rw) register accessor: Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbidx`]
module"]
# [doc (alias = "PBIDX")]
pub type Pbidx = crate :: Reg < pbidx :: PbidxSpec > ; # [doc = "Prog Set B-Dim Idx"]
pub mod pbidx { # [doc = "Register `PBIDX` reader"]
pub type R = crate :: R < PbidxSpec > ; # [doc = "Register `PBIDX` writer"]
pub type W = crate :: W < PbidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < PbidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < PbidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbidxSpec ; impl crate :: RegisterSpec for PbidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbidx::R`](R) reader structure"]
impl crate :: Readable for PbidxSpec { } # [doc = "`write(|w| ..)` method takes [`pbidx::W`](W) writer structure"]
impl crate :: Writable for PbidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIDX to value 0"]
impl crate :: Resettable for PbidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PMPPRXY (rw) register accessor: Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmpprxy`]
module"]
# [doc (alias = "PMPPRXY")]
pub type Pmpprxy = crate :: Reg < pmpprxy :: PmpprxySpec > ; # [doc = "Prog Set Mem Protect Proxy"]
pub mod pmpprxy { # [doc = "Register `PMPPRXY` reader"]
pub type R = crate :: R < PmpprxySpec > ; # [doc = "Register `PMPPRXY` writer"]
pub type W = crate :: W < PmpprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < PmpprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < PmpprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < PmpprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmpprxySpec ; impl crate :: RegisterSpec for PmpprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmpprxy::R`](R) reader structure"]
impl crate :: Readable for PmpprxySpec { } # [doc = "`write(|w| ..)` method takes [`pmpprxy::W`](W) writer structure"]
impl crate :: Writable for PmpprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PMPPRXY to value 0"]
impl crate :: Resettable for PmpprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAOPT (rw) register accessor: Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@saopt`]
module"]
# [doc (alias = "SAOPT")]
pub type Saopt = crate :: Reg < saopt :: SaoptSpec > ; # [doc = "Src Actv Set Options"]
pub mod saopt { # [doc = "Register `SAOPT` reader"]
pub type R = crate :: R < SaoptSpec > ; # [doc = "Register `SAOPT` writer"]
pub type W = crate :: W < SaoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < SaoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < SaoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < SaoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < SaoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < SaoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < SaoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < SaoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < SaoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SaoptSpec ; impl crate :: RegisterSpec for SaoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`saopt::R`](R) reader structure"]
impl crate :: Readable for SaoptSpec { } # [doc = "`write(|w| ..)` method takes [`saopt::W`](W) writer structure"]
impl crate :: Writable for SaoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAOPT to value 0"]
impl crate :: Resettable for SaoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRC (rw) register accessor: Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrc`]
module"]
# [doc (alias = "SASRC")]
pub type Sasrc = crate :: Reg < sasrc :: SasrcSpec > ; # [doc = "Src Actv Set Src Address"]
pub mod sasrc { # [doc = "Register `SASRC` reader"]
pub type R = crate :: R < SasrcSpec > ; # [doc = "Register `SASRC` writer"]
pub type W = crate :: W < SasrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` reader - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` writer - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
pub fn source_address_for_1 (& self) -> SourceAddressFor1R { SourceAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for_1 (& mut self) -> SourceAddressFor1W < SasrcSpec > { SourceAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcSpec ; impl crate :: RegisterSpec for SasrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrc::R`](R) reader structure"]
impl crate :: Readable for SasrcSpec { } # [doc = "`write(|w| ..)` method takes [`sasrc::W`](W) writer structure"]
impl crate :: Writable for SasrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRC to value 0"]
impl crate :: Resettable for SasrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNT (rw) register accessor: Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacnt`]
module"]
# [doc (alias = "SACNT")]
pub type Sacnt = crate :: Reg < sacnt :: SacntSpec > ; # [doc = "Src Actv Set A-Count"]
pub mod sacnt { # [doc = "Register `SACNT` reader"]
pub type R = crate :: R < SacntSpec > ; # [doc = "Register `SACNT` writer"]
pub type W = crate :: W < SacntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < SacntSpec > { AdimensionCount_NumberW :: new (self , 0) } } # [doc = "Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntSpec ; impl crate :: RegisterSpec for SacntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacnt::R`](R) reader structure"]
impl crate :: Readable for SacntSpec { } # [doc = "`write(|w| ..)` method takes [`sacnt::W`](W) writer structure"]
impl crate :: Writable for SacntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNT to value 0"]
impl crate :: Resettable for SacntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADST (rw) register accessor: Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadst`]
module"]
# [doc (alias = "SADST")]
pub type Sadst = crate :: Reg < sadst :: SadstSpec > ; # [doc = "Src Actv Set Dst Address"]
pub mod sadst { # [doc = "Register `SADST` reader"]
pub type R = crate :: R < SadstSpec > ; # [doc = "Register `SADST` writer"]
pub type W = crate :: W < SadstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` reader - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` writer - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
pub fn destination_address_for_1 (& self) -> DestinationAddressFor1R { DestinationAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for_1 (& mut self) -> DestinationAddressFor1W < SadstSpec > { DestinationAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstSpec ; impl crate :: RegisterSpec for SadstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadst::R`](R) reader structure"]
impl crate :: Readable for SadstSpec { } # [doc = "`write(|w| ..)` method takes [`sadst::W`](W) writer structure"]
impl crate :: Writable for SadstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADST to value 0"]
impl crate :: Resettable for SadstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABIDX (rw) register accessor: Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabidx`]
module"]
# [doc (alias = "SABIDX")]
pub type Sabidx = crate :: Reg < sabidx :: SabidxSpec > ; # [doc = "Src Actv Set B-Dim Idx"]
pub mod sabidx { # [doc = "Register `SABIDX` reader"]
pub type R = crate :: R < SabidxSpec > ; # [doc = "Register `SABIDX` writer"]
pub type W = crate :: W < SabidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < SabidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < SabidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabidxSpec ; impl crate :: RegisterSpec for SabidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabidx::R`](R) reader structure"]
impl crate :: Readable for SabidxSpec { } # [doc = "`write(|w| ..)` method takes [`sabidx::W`](W) writer structure"]
impl crate :: Writable for SabidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABIDX to value 0"]
impl crate :: Resettable for SabidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAMPPRXY (rw) register accessor: Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sampprxy`]
module"]
# [doc (alias = "SAMPPRXY")]
pub type Sampprxy = crate :: Reg < sampprxy :: SampprxySpec > ; # [doc = "Src Actv Set Mem Protect Proxy"]
pub mod sampprxy { # [doc = "Register `SAMPPRXY` reader"]
pub type R = crate :: R < SampprxySpec > ; # [doc = "Register `SAMPPRXY` writer"]
pub type W = crate :: W < SampprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < SampprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < SampprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < SampprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SampprxySpec ; impl crate :: RegisterSpec for SampprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sampprxy::R`](R) reader structure"]
impl crate :: Readable for SampprxySpec { } # [doc = "`write(|w| ..)` method takes [`sampprxy::W`](W) writer structure"]
impl crate :: Writable for SampprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAMPPRXY to value 0"]
impl crate :: Resettable for SampprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNTRLD (rw) register accessor: Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacntrld`]
module"]
# [doc (alias = "SACNTRLD")]
pub type Sacntrld = crate :: Reg < sacntrld :: SacntrldSpec > ; # [doc = "Src Actv Set Cnt Reload"]
pub mod sacntrld { # [doc = "Register `SACNTRLD` reader"]
pub type R = crate :: R < SacntrldSpec > ; # [doc = "Register `SACNTRLD` writer"]
pub type W = crate :: W < SacntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE` reader - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueR = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE` writer - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value (& self) -> AcntReloadValueR { AcntReloadValueR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value (& mut self) -> AcntReloadValueW < SacntrldSpec > { AcntReloadValueW :: new (self , 0) } } # [doc = "Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntrldSpec ; impl crate :: RegisterSpec for SacntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacntrld::R`](R) reader structure"]
impl crate :: Readable for SacntrldSpec { } # [doc = "`write(|w| ..)` method takes [`sacntrld::W`](W) writer structure"]
impl crate :: Writable for SacntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNTRLD to value 0"]
impl crate :: Resettable for SacntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRCBREF (rw) register accessor: Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrcbref`]
module"]
# [doc (alias = "SASRCBREF")]
pub type Sasrcbref = crate :: Reg < sasrcbref :: SasrcbrefSpec > ; # [doc = "Src Actv Set Src Addr B-Reference"]
pub mod sasrcbref { # [doc = "Register `SASRCBREF` reader"]
pub type R = crate :: R < SasrcbrefSpec > ; # [doc = "Register `SASRCBREF` writer"]
pub type W = crate :: W < SasrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` reader - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` writer - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference (& self) -> SourceAddressReferenceR { SourceAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference (& mut self) -> SourceAddressReferenceW < SasrcbrefSpec > { SourceAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcbrefSpec ; impl crate :: RegisterSpec for SasrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrcbref::R`](R) reader structure"]
impl crate :: Readable for SasrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sasrcbref::W`](W) writer structure"]
impl crate :: Writable for SasrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRCBREF to value 0"]
impl crate :: Resettable for SasrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADSTBREF (rw) register accessor: Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadstbref`]
module"]
# [doc (alias = "SADSTBREF")]
pub type Sadstbref = crate :: Reg < sadstbref :: SadstbrefSpec > ; # [doc = "Src Actv Set Dst Addr B-Reference"]
pub mod sadstbref { # [doc = "Register `SADSTBREF` reader"]
pub type R = crate :: R < SadstbrefSpec > ; # [doc = "Register `SADSTBREF` writer"]
pub type W = crate :: W < SadstbrefSpec > ; # [doc = "Field `DST_ADDRESS_REFERENCE` reader - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `DST_ADDRESS_REFERENCE` writer - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
pub fn dst_address_reference (& self) -> DstAddressReferenceR { DstAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn dst_address_reference (& mut self) -> DstAddressReferenceW < SadstbrefSpec > { DstAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstbrefSpec ; impl crate :: RegisterSpec for SadstbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadstbref::R`](R) reader structure"]
impl crate :: Readable for SadstbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sadstbref::W`](W) writer structure"]
impl crate :: Writable for SadstbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADSTBREF to value 0"]
impl crate :: Resettable for SadstbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABCNT (rw) register accessor: Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabcnt`]
module"]
# [doc (alias = "SABCNT")]
pub type Sabcnt = crate :: Reg < sabcnt :: SabcntSpec > ; # [doc = "Src Actv Set B-Count"]
pub mod sabcnt { # [doc = "Register `SABCNT` reader"]
pub type R = crate :: R < SabcntSpec > ; # [doc = "Register `SABCNT` writer"]
pub type W = crate :: W < SabcntSpec > ; # [doc = "Field `BDIMENSION_COUNT` reader - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT` writer - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bdimension_count (& self) -> BdimensionCountR { BdimensionCountR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bdimension_count (& mut self) -> BdimensionCountW < SabcntSpec > { BdimensionCountW :: new (self , 0) } } # [doc = "Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabcntSpec ; impl crate :: RegisterSpec for SabcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabcnt::R`](R) reader structure"]
impl crate :: Readable for SabcntSpec { } # [doc = "`write(|w| ..)` method takes [`sabcnt::W`](W) writer structure"]
impl crate :: Writable for SabcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABCNT to value 0"]
impl crate :: Resettable for SabcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFCNTRLD (rw) register accessor: Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfcntrld`]
module"]
# [doc (alias = "DFCNTRLD")]
pub type Dfcntrld = crate :: Reg < dfcntrld :: DfcntrldSpec > ; # [doc = "Dst FIFO Set Cnt Reload"]
pub mod dfcntrld { # [doc = "Register `DFCNTRLD` reader"]
pub type R = crate :: R < DfcntrldSpec > ; # [doc = "Register `DFCNTRLD` writer"]
pub type W = crate :: W < DfcntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` reader - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1R = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` writer - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value_1 (& self) -> AcntReloadValue1R { AcntReloadValue1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value_1 (& mut self) -> AcntReloadValue1W < DfcntrldSpec > { AcntReloadValue1W :: new (self , 0) } } # [doc = "Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfcntrldSpec ; impl crate :: RegisterSpec for DfcntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfcntrld::R`](R) reader structure"]
impl crate :: Readable for DfcntrldSpec { } # [doc = "`write(|w| ..)` method takes [`dfcntrld::W`](W) writer structure"]
impl crate :: Writable for DfcntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFCNTRLD to value 0"]
impl crate :: Resettable for DfcntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRCBREF (rw) register accessor: Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrcbref`]
module"]
# [doc (alias = "DFSRCBREF")]
pub type Dfsrcbref = crate :: Reg < dfsrcbref :: DfsrcbrefSpec > ; # [doc = "Dst FIFO Set Src Addr B-Reference"]
pub mod dfsrcbref { # [doc = "Register `DFSRCBREF` reader"]
pub type R = crate :: R < DfsrcbrefSpec > ; # [doc = "Register `DFSRCBREF` writer"]
pub type W = crate :: W < DfsrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` reader - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` writer - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference_1 (& self) -> SourceAddressReference1R { SourceAddressReference1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference_1 (& mut self) -> SourceAddressReference1W < DfsrcbrefSpec > { SourceAddressReference1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfsrcbrefSpec ; impl crate :: RegisterSpec for DfsrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrcbref::R`](R) reader structure"]
impl crate :: Readable for DfsrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`dfsrcbref::W`](W) writer structure"]
impl crate :: Writable for DfsrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRCBREF to value 0"]
impl crate :: Resettable for DfsrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT0 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt0`]
module"]
# [doc (alias = "DFOPT0")]
pub type Dfopt0 = crate :: Reg < dfopt0 :: Dfopt0Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt0 { # [doc = "Register `DFOPT0` reader"]
pub type R = crate :: R < Dfopt0Spec > ; # [doc = "Register `DFOPT0` writer"]
pub type W = crate :: W < Dfopt0Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt0Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt0Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt0Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt0Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt0Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt0Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt0Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt0Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt0Spec ; impl crate :: RegisterSpec for Dfopt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt0::R`](R) reader structure"]
impl crate :: Readable for Dfopt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt0::W`](W) writer structure"]
impl crate :: Writable for Dfopt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT0 to value 0"]
impl crate :: Resettable for Dfopt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC0 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc0`]
module"]
# [doc (alias = "DFSRC0")]
pub type Dfsrc0 = crate :: Reg < dfsrc0 :: Dfsrc0Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc0 { # [doc = "Register `DFSRC0` reader"]
pub type R = crate :: R < Dfsrc0Spec > ; # [doc = "Register `DFSRC0` writer"]
pub type W = crate :: W < Dfsrc0Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is (& self) -> SourceAddressIsR { SourceAddressIsR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is (& mut self) -> SourceAddressIsW < Dfsrc0Spec > { SourceAddressIsW :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc0Spec ; impl crate :: RegisterSpec for Dfsrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc0::R`](R) reader structure"]
impl crate :: Readable for Dfsrc0Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc0::W`](W) writer structure"]
impl crate :: Writable for Dfsrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC0 to value 0"]
impl crate :: Resettable for Dfsrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT0 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt0`]
module"]
# [doc (alias = "DFACNT0")]
pub type Dfacnt0 = crate :: Reg < dfacnt0 :: Dfacnt0Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt0 { # [doc = "Register `DFACNT0` reader"]
pub type R = crate :: R < Dfacnt0Spec > ; # [doc = "Register `DFACNT0` writer"]
pub type W = crate :: W < Dfacnt0Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_1 (& self) -> AdimensionCount_Number1R { AdimensionCount_Number1R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_1 (& mut self) -> AdimensionCount_Number1W < Dfacnt0Spec > { AdimensionCount_Number1W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt0Spec ; impl crate :: RegisterSpec for Dfacnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt0::R`](R) reader structure"]
impl crate :: Readable for Dfacnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt0::W`](W) writer structure"]
impl crate :: Writable for Dfacnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT0 to value 0"]
impl crate :: Resettable for Dfacnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST0 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst0`]
module"]
# [doc (alias = "DFDST0")]
pub type Dfdst0 = crate :: Reg < dfdst0 :: Dfdst0Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst0 { # [doc = "Register `DFDST0` reader"]
pub type R = crate :: R < Dfdst0Spec > ; # [doc = "Register `DFDST0` writer"]
pub type W = crate :: W < Dfdst0Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_2 (& self) -> DestinationAddressFor2R { DestinationAddressFor2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_2 (& mut self) -> DestinationAddressFor2W < Dfdst0Spec > { DestinationAddressFor2W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst0Spec ; impl crate :: RegisterSpec for Dfdst0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst0::R`](R) reader structure"]
impl crate :: Readable for Dfdst0Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst0::W`](W) writer structure"]
impl crate :: Writable for Dfdst0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST0 to value 0"]
impl crate :: Resettable for Dfdst0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX0 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx0`]
module"]
# [doc (alias = "DFBIDX0")]
pub type Dfbidx0 = crate :: Reg < dfbidx0 :: Dfbidx0Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx0 { # [doc = "Register `DFBIDX0` reader"]
pub type R = crate :: R < Dfbidx0Spec > ; # [doc = "Register `DFBIDX0` writer"]
pub type W = crate :: W < Dfbidx0Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx0Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx0Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx0Spec ; impl crate :: RegisterSpec for Dfbidx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx0::R`](R) reader structure"]
impl crate :: Readable for Dfbidx0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx0::W`](W) writer structure"]
impl crate :: Writable for Dfbidx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX0 to value 0"]
impl crate :: Resettable for Dfbidx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY0 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy0`]
module"]
# [doc (alias = "DFMPPRXY0")]
pub type Dfmpprxy0 = crate :: Reg < dfmpprxy0 :: Dfmpprxy0Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy0 { # [doc = "Register `DFMPPRXY0` reader"]
pub type R = crate :: R < Dfmpprxy0Spec > ; # [doc = "Register `DFMPPRXY0` writer"]
pub type W = crate :: W < Dfmpprxy0Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy0Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy0Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy0Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy0Spec ; impl crate :: RegisterSpec for Dfmpprxy0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy0::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy0Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy0::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY0 to value 0"]
impl crate :: Resettable for Dfmpprxy0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT0 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt0`]
module"]
# [doc (alias = "DFBCNT0")]
pub type Dfbcnt0 = crate :: Reg < dfbcnt0 :: Dfbcnt0Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt0 { # [doc = "Register `DFBCNT0` reader"]
pub type R = crate :: R < Dfbcnt0Spec > ; # [doc = "Register `DFBCNT0` writer"]
pub type W = crate :: W < Dfbcnt0Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForR = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for (& self) -> BcountRemainingForR { BcountRemainingForR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for (& mut self) -> BcountRemainingForW < Dfbcnt0Spec > { BcountRemainingForW :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt0Spec ; impl crate :: RegisterSpec for Dfbcnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt0::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt0::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT0 to value 0"]
impl crate :: Resettable for Dfbcnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT1 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt1`]
module"]
# [doc (alias = "DFOPT1")]
pub type Dfopt1 = crate :: Reg < dfopt1 :: Dfopt1Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt1 { # [doc = "Register `DFOPT1` reader"]
pub type R = crate :: R < Dfopt1Spec > ; # [doc = "Register `DFOPT1` writer"]
pub type W = crate :: W < Dfopt1Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt1Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt1Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt1Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt1Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt1Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt1Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt1Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt1Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt1Spec ; impl crate :: RegisterSpec for Dfopt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt1::R`](R) reader structure"]
impl crate :: Readable for Dfopt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt1::W`](W) writer structure"]
impl crate :: Writable for Dfopt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT1 to value 0"]
impl crate :: Resettable for Dfopt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC1 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc1`]
module"]
# [doc (alias = "DFSRC1")]
pub type Dfsrc1 = crate :: Reg < dfsrc1 :: Dfsrc1Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc1 { # [doc = "Register `DFSRC1` reader"]
pub type R = crate :: R < Dfsrc1Spec > ; # [doc = "Register `DFSRC1` writer"]
pub type W = crate :: W < Dfsrc1Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is_1 (& self) -> SourceAddressIs1R { SourceAddressIs1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is_1 (& mut self) -> SourceAddressIs1W < Dfsrc1Spec > { SourceAddressIs1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc1Spec ; impl crate :: RegisterSpec for Dfsrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc1::R`](R) reader structure"]
impl crate :: Readable for Dfsrc1Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc1::W`](W) writer structure"]
impl crate :: Writable for Dfsrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC1 to value 0"]
impl crate :: Resettable for Dfsrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT1 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt1`]
module"]
# [doc (alias = "DFACNT1")]
pub type Dfacnt1 = crate :: Reg < dfacnt1 :: Dfacnt1Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt1 { # [doc = "Register `DFACNT1` reader"]
pub type R = crate :: R < Dfacnt1Spec > ; # [doc = "Register `DFACNT1` writer"]
pub type W = crate :: W < Dfacnt1Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_2 (& self) -> AdimensionCount_Number2R { AdimensionCount_Number2R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_2 (& mut self) -> AdimensionCount_Number2W < Dfacnt1Spec > { AdimensionCount_Number2W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt1Spec ; impl crate :: RegisterSpec for Dfacnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt1::R`](R) reader structure"]
impl crate :: Readable for Dfacnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt1::W`](W) writer structure"]
impl crate :: Writable for Dfacnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT1 to value 0"]
impl crate :: Resettable for Dfacnt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST1 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst1`]
module"]
# [doc (alias = "DFDST1")]
pub type Dfdst1 = crate :: Reg < dfdst1 :: Dfdst1Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst1 { # [doc = "Register `DFDST1` reader"]
pub type R = crate :: R < Dfdst1Spec > ; # [doc = "Register `DFDST1` writer"]
pub type W = crate :: W < Dfdst1Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_3 (& self) -> DestinationAddressFor3R { DestinationAddressFor3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_3 (& mut self) -> DestinationAddressFor3W < Dfdst1Spec > { DestinationAddressFor3W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst1Spec ; impl crate :: RegisterSpec for Dfdst1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst1::R`](R) reader structure"]
impl crate :: Readable for Dfdst1Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst1::W`](W) writer structure"]
impl crate :: Writable for Dfdst1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST1 to value 0"]
impl crate :: Resettable for Dfdst1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX1 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx1`]
module"]
# [doc (alias = "DFBIDX1")]
pub type Dfbidx1 = crate :: Reg < dfbidx1 :: Dfbidx1Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx1 { # [doc = "Register `DFBIDX1` reader"]
pub type R = crate :: R < Dfbidx1Spec > ; # [doc = "Register `DFBIDX1` writer"]
pub type W = crate :: W < Dfbidx1Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx1Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx1Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx1Spec ; impl crate :: RegisterSpec for Dfbidx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx1::R`](R) reader structure"]
impl crate :: Readable for Dfbidx1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx1::W`](W) writer structure"]
impl crate :: Writable for Dfbidx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX1 to value 0"]
impl crate :: Resettable for Dfbidx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY1 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy1`]
module"]
# [doc (alias = "DFMPPRXY1")]
pub type Dfmpprxy1 = crate :: Reg < dfmpprxy1 :: Dfmpprxy1Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy1 { # [doc = "Register `DFMPPRXY1` reader"]
pub type R = crate :: R < Dfmpprxy1Spec > ; # [doc = "Register `DFMPPRXY1` writer"]
pub type W = crate :: W < Dfmpprxy1Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy1Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy1Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy1Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy1Spec ; impl crate :: RegisterSpec for Dfmpprxy1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy1::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy1Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy1::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY1 to value 0"]
impl crate :: Resettable for Dfmpprxy1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT1 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt1`]
module"]
# [doc (alias = "DFBCNT1")]
pub type Dfbcnt1 = crate :: Reg < dfbcnt1 :: Dfbcnt1Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt1 { # [doc = "Register `DFBCNT1` reader"]
pub type R = crate :: R < Dfbcnt1Spec > ; # [doc = "Register `DFBCNT1` writer"]
pub type W = crate :: W < Dfbcnt1Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1R = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for_1 (& self) -> BcountRemainingFor1R { BcountRemainingFor1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for_1 (& mut self) -> BcountRemainingFor1W < Dfbcnt1Spec > { BcountRemainingFor1W :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt1Spec ; impl crate :: RegisterSpec for Dfbcnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt1::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt1::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT1 to value 0"]
impl crate :: Resettable for Dfbcnt1Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Register test environment"]
pub struct TptcA1 { _marker : PhantomData < * const () > } unsafe impl Send for TptcA1 { } impl TptcA1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tptc_a1 :: RegisterBlock = 0x5401_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tptc_a1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TptcA1 { type Target = tptc_a1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TptcA1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TptcA1") . finish () } } # [doc = "Register test environment"]
pub mod tptc_a1 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , tccfg : Tccfg , _reserved2 : [u8 ; 0xf8]
, tcstat : Tcstat , intstat : Intstat , inten : Inten , intclr : Intclr , intcmd : Intcmd , _reserved7 : [u8 ; 0x0c]
, errstat : Errstat , erren : Erren , errclr : Errclr , errdet : Errdet , errcmd : Errcmd , _reserved12 : [u8 ; 0x0c]
, rdrate : Rdrate , _reserved13 : [u8 ; 0xbc]
, popt : Popt , psrc : Psrc , pcnt : Pcnt , pdst : Pdst , pbidx : Pbidx , pmpprxy : Pmpprxy , _reserved19 : [u8 ; 0x28]
, saopt : Saopt , sasrc : Sasrc , sacnt : Sacnt , sadst : Sadst , sabidx : Sabidx , sampprxy : Sampprxy , sacntrld : Sacntrld , sasrcbref : Sasrcbref , sadstbref : Sadstbref , sabcnt : Sabcnt , _reserved29 : [u8 ; 0x18]
, dfcntrld : Dfcntrld , dfsrcbref : Dfsrcbref , _reserved31 : [u8 ; 0x78]
, dfopt0 : Dfopt0 , dfsrc0 : Dfsrc0 , dfacnt0 : Dfacnt0 , dfdst0 : Dfdst0 , dfbidx0 : Dfbidx0 , dfmpprxy0 : Dfmpprxy0 , dfbcnt0 : Dfbcnt0 , _reserved38 : [u8 ; 0x24]
, dfopt1 : Dfopt1 , dfsrc1 : Dfsrc1 , dfacnt1 : Dfacnt1 , dfdst1 : Dfdst1 , dfbidx1 : Dfbidx1 , dfmpprxy1 : Dfmpprxy1 , dfbcnt1 : Dfbcnt1 , } impl RegisterBlock { # [doc = "0x00 - Peripheral ID Register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - TC Configuration Register"]
# [inline (always)]
pub const fn tccfg (& self) -> & Tccfg { & self . tccfg } # [doc = "0x100 - TC Status Register"]
# [inline (always)]
pub const fn tcstat (& self) -> & Tcstat { & self . tcstat } # [doc = "0x104 - Interrupt Status Register"]
# [inline (always)]
pub const fn intstat (& self) -> & Intstat { & self . intstat } # [doc = "0x108 - Interrupt Enable Register"]
# [inline (always)]
pub const fn inten (& self) -> & Inten { & self . inten } # [doc = "0x10c - Interrupt Clear Register"]
# [inline (always)]
pub const fn intclr (& self) -> & Intclr { & self . intclr } # [doc = "0x110 - Interrupt Command Register"]
# [inline (always)]
pub const fn intcmd (& self) -> & Intcmd { & self . intcmd } # [doc = "0x120 - Error Status Register"]
# [inline (always)]
pub const fn errstat (& self) -> & Errstat { & self . errstat } # [doc = "0x124 - Error Enable Register"]
# [inline (always)]
pub const fn erren (& self) -> & Erren { & self . erren } # [doc = "0x128 - Error Clear Register"]
# [inline (always)]
pub const fn errclr (& self) -> & Errclr { & self . errclr } # [doc = "0x12c - Error Details Register"]
# [inline (always)]
pub const fn errdet (& self) -> & Errdet { & self . errdet } # [doc = "0x130 - Error Command Register"]
# [inline (always)]
pub const fn errcmd (& self) -> & Errcmd { & self . errcmd } # [doc = "0x140 - Read Rate Register"]
# [inline (always)]
pub const fn rdrate (& self) -> & Rdrate { & self . rdrate } # [doc = "0x200 - Prog Set Options"]
# [inline (always)]
pub const fn popt (& self) -> & Popt { & self . popt } # [doc = "0x204 - Prog Set Src Address"]
# [inline (always)]
pub const fn psrc (& self) -> & Psrc { & self . psrc } # [doc = "0x208 - Prog Set Count"]
# [inline (always)]
pub const fn pcnt (& self) -> & Pcnt { & self . pcnt } # [doc = "0x20c - Prog Set Dst Address"]
# [inline (always)]
pub const fn pdst (& self) -> & Pdst { & self . pdst } # [doc = "0x210 - Prog Set B-Dim Idx"]
# [inline (always)]
pub const fn pbidx (& self) -> & Pbidx { & self . pbidx } # [doc = "0x214 - Prog Set Mem Protect Proxy"]
# [inline (always)]
pub const fn pmpprxy (& self) -> & Pmpprxy { & self . pmpprxy } # [doc = "0x240 - Src Actv Set Options"]
# [inline (always)]
pub const fn saopt (& self) -> & Saopt { & self . saopt } # [doc = "0x244 - Src Actv Set Src Address"]
# [inline (always)]
pub const fn sasrc (& self) -> & Sasrc { & self . sasrc } # [doc = "0x248 - Src Actv Set A-Count"]
# [inline (always)]
pub const fn sacnt (& self) -> & Sacnt { & self . sacnt } # [doc = "0x24c - Src Actv Set Dst Address"]
# [inline (always)]
pub const fn sadst (& self) -> & Sadst { & self . sadst } # [doc = "0x250 - Src Actv Set B-Dim Idx"]
# [inline (always)]
pub const fn sabidx (& self) -> & Sabidx { & self . sabidx } # [doc = "0x254 - Src Actv Set Mem Protect Proxy"]
# [inline (always)]
pub const fn sampprxy (& self) -> & Sampprxy { & self . sampprxy } # [doc = "0x258 - Src Actv Set Cnt Reload"]
# [inline (always)]
pub const fn sacntrld (& self) -> & Sacntrld { & self . sacntrld } # [doc = "0x25c - Src Actv Set Src Addr B-Reference"]
# [inline (always)]
pub const fn sasrcbref (& self) -> & Sasrcbref { & self . sasrcbref } # [doc = "0x260 - Src Actv Set Dst Addr B-Reference"]
# [inline (always)]
pub const fn sadstbref (& self) -> & Sadstbref { & self . sadstbref } # [doc = "0x264 - Src Actv Set B-Count"]
# [inline (always)]
pub const fn sabcnt (& self) -> & Sabcnt { & self . sabcnt } # [doc = "0x280 - Dst FIFO Set Cnt Reload"]
# [inline (always)]
pub const fn dfcntrld (& self) -> & Dfcntrld { & self . dfcntrld } # [doc = "0x284 - Dst FIFO Set Src Addr B-Reference"]
# [inline (always)]
pub const fn dfsrcbref (& self) -> & Dfsrcbref { & self . dfsrcbref } # [doc = "0x300 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt0 (& self) -> & Dfopt0 { & self . dfopt0 } # [doc = "0x304 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc0 (& self) -> & Dfsrc0 { & self . dfsrc0 } # [doc = "0x308 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt0 (& self) -> & Dfacnt0 { & self . dfacnt0 } # [doc = "0x30c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst0 (& self) -> & Dfdst0 { & self . dfdst0 } # [doc = "0x310 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx0 (& self) -> & Dfbidx0 { & self . dfbidx0 } # [doc = "0x314 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy0 (& self) -> & Dfmpprxy0 { & self . dfmpprxy0 } # [doc = "0x318 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt0 (& self) -> & Dfbcnt0 { & self . dfbcnt0 } # [doc = "0x340 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt1 (& self) -> & Dfopt1 { & self . dfopt1 } # [doc = "0x344 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc1 (& self) -> & Dfsrc1 { & self . dfsrc1 } # [doc = "0x348 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt1 (& self) -> & Dfacnt1 { & self . dfacnt1 } # [doc = "0x34c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst1 (& self) -> & Dfdst1 { & self . dfdst1 } # [doc = "0x350 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx1 (& self) -> & Dfbidx1 { & self . dfbidx1 } # [doc = "0x354 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy1 (& self) -> & Dfmpprxy1 { & self . dfmpprxy1 } # [doc = "0x358 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt1 (& self) -> & Dfbcnt1 { & self . dfbcnt1 } } # [doc = "PID (rw) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "Peripheral ID Register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR_REVISION` reader - 5:0\\]
Minor Revision"]
pub type MinorRevisionR = crate :: FieldReader ; # [doc = "Field `MINOR_REVISION` writer - 5:0\\]
Minor Revision"]
pub type MinorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM_REVISION_FIELD` reader - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldR = crate :: FieldReader ; # [doc = "Field `CUSTOM_REVISION_FIELD` writer - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR_REVISION` reader - 10:8\\]
Major Revision"]
pub type MajorRevisionR = crate :: FieldReader ; # [doc = "Field `MAJOR_REVISION` writer - 10:8\\]
Major Revision"]
pub type MajorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL_VERSION` reader - 15:11\\]
RTL Version"]
pub type RtlVersionR = crate :: FieldReader ; # [doc = "Field `RTL_VERSION` writer - 15:11\\]
RTL Version"]
pub type RtlVersionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNCTION_INDICATES_A` reader - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNCTION_INDICATES_A` writer - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `PID_SCHEME` reader - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeR = crate :: FieldReader ; # [doc = "Field `PID_SCHEME` writer - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
pub fn minor_revision (& self) -> MinorRevisionR { MinorRevisionR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
pub fn custom_revision_field (& self) -> CustomRevisionFieldR { CustomRevisionFieldR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
pub fn major_revision (& self) -> MajorRevisionR { MajorRevisionR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
pub fn rtl_version (& self) -> RtlVersionR { RtlVersionR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
pub fn function_indicates_a (& self) -> FunctionIndicatesAR { FunctionIndicatesAR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
pub fn pid_scheme (& self) -> PidSchemeR { PidSchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
# [must_use]
pub fn minor_revision (& mut self) -> MinorRevisionW < PidSpec > { MinorRevisionW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
# [must_use]
pub fn custom_revision_field (& mut self) -> CustomRevisionFieldW < PidSpec > { CustomRevisionFieldW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
# [must_use]
pub fn major_revision (& mut self) -> MajorRevisionW < PidSpec > { MajorRevisionW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
# [must_use]
pub fn rtl_version (& mut self) -> RtlVersionW < PidSpec > { RtlVersionW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
# [must_use]
pub fn function_indicates_a (& mut self) -> FunctionIndicatesAW < PidSpec > { FunctionIndicatesAW :: new (self , 16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
# [must_use]
pub fn pid_scheme (& mut self) -> PidSchemeW < PidSpec > { PidSchemeW :: new (self , 30) } } # [doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCCFG (rw) register accessor: TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tccfg`]
module"]
# [doc (alias = "TCCFG")]
pub type Tccfg = crate :: Reg < tccfg :: TccfgSpec > ; # [doc = "TC Configuration Register"]
pub mod tccfg { # [doc = "Register `TCCFG` reader"]
pub type R = crate :: R < TccfgSpec > ; # [doc = "Register `TCCFG` writer"]
pub type W = crate :: W < TccfgSpec > ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` reader - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationR = crate :: FieldReader ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` writer - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` reader - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationR = crate :: FieldReader ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` writer - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DST_REGISTER_FIFO` reader - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoR = crate :: FieldReader ; # [doc = "Field `DST_REGISTER_FIFO` writer - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
pub fn fifo_size_parameterization (& self) -> FifoSizeParameterizationR { FifoSizeParameterizationR :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
pub fn bus_width_parameterization (& self) -> BusWidthParameterizationR { BusWidthParameterizationR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
pub fn dst_register_fifo (& self) -> DstRegisterFifoR { DstRegisterFifoR :: new (((self . bits >> 8) & 3) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
# [must_use]
pub fn fifo_size_parameterization (& mut self) -> FifoSizeParameterizationW < TccfgSpec > { FifoSizeParameterizationW :: new (self , 0) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
# [must_use]
pub fn bus_width_parameterization (& mut self) -> BusWidthParameterizationW < TccfgSpec > { BusWidthParameterizationW :: new (self , 4) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
# [must_use]
pub fn dst_register_fifo (& mut self) -> DstRegisterFifoW < TccfgSpec > { DstRegisterFifoW :: new (self , 8) } } # [doc = "TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TccfgSpec ; impl crate :: RegisterSpec for TccfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tccfg::R`](R) reader structure"]
impl crate :: Readable for TccfgSpec { } # [doc = "`write(|w| ..)` method takes [`tccfg::W`](W) writer structure"]
impl crate :: Writable for TccfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCCFG to value 0"]
impl crate :: Resettable for TccfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCSTAT (rw) register accessor: TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcstat`]
module"]
# [doc (alias = "TCSTAT")]
pub type Tcstat = crate :: Reg < tcstat :: TcstatSpec > ; # [doc = "TC Status Register"]
pub mod tcstat { # [doc = "Register `TCSTAT` reader"]
pub type R = crate :: R < TcstatSpec > ; # [doc = "Register `TCSTAT` writer"]
pub type W = crate :: W < TcstatSpec > ; # [doc = "Field `PROGRAM_REGISTER_SET` reader - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetR = crate :: BitReader ; # [doc = "Field `PROGRAM_REGISTER_SET` writer - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOURCE_ACTIVE_STATE` reader - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateR = crate :: BitReader ; # [doc = "Field `SOURCE_ACTIVE_STATE` writer - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WRITE_STATUS_ACTIVE` reader - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveR = crate :: BitReader ; # [doc = "Field `WRITE_STATUS_ACTIVE` writer - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ACTIVE_STATE` reader - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateR = crate :: FieldReader ; # [doc = "Field `DESTINATION_ACTIVE_STATE` writer - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CHANNEL_ACTIVE` reader - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveR = crate :: BitReader ; # [doc = "Field `CHANNEL_ACTIVE` writer - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DST_FIFO_START` reader - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartR = crate :: FieldReader ; # [doc = "Field `DST_FIFO_START` writer - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
pub fn program_register_set (& self) -> ProgramRegisterSetR { ProgramRegisterSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
pub fn source_active_state (& self) -> SourceActiveStateR { SourceActiveStateR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
pub fn write_status_active (& self) -> WriteStatusActiveR { WriteStatusActiveR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
pub fn destination_active_state (& self) -> DestinationActiveStateR { DestinationActiveStateR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
pub fn channel_active (& self) -> ChannelActiveR { ChannelActiveR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
pub fn dst_fifo_start (& self) -> DstFifoStartR { DstFifoStartR :: new (((self . bits >> 12) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
# [must_use]
pub fn program_register_set (& mut self) -> ProgramRegisterSetW < TcstatSpec > { ProgramRegisterSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
# [must_use]
pub fn source_active_state (& mut self) -> SourceActiveStateW < TcstatSpec > { SourceActiveStateW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
# [must_use]
pub fn write_status_active (& mut self) -> WriteStatusActiveW < TcstatSpec > { WriteStatusActiveW :: new (self , 2) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
# [must_use]
pub fn destination_active_state (& mut self) -> DestinationActiveStateW < TcstatSpec > { DestinationActiveStateW :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
# [must_use]
pub fn channel_active (& mut self) -> ChannelActiveW < TcstatSpec > { ChannelActiveW :: new (self , 8) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
# [must_use]
pub fn dst_fifo_start (& mut self) -> DstFifoStartW < TcstatSpec > { DstFifoStartW :: new (self , 12) } } # [doc = "TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcstatSpec ; impl crate :: RegisterSpec for TcstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tcstat::R`](R) reader structure"]
impl crate :: Readable for TcstatSpec { } # [doc = "`write(|w| ..)` method takes [`tcstat::W`](W) writer structure"]
impl crate :: Writable for TcstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCSTAT to value 0"]
impl crate :: Resettable for TcstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTSTAT (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstat`]
module"]
# [doc (alias = "INTSTAT")]
pub type Intstat = crate :: Reg < intstat :: IntstatSpec > ; # [doc = "Interrupt Status Register"]
pub mod intstat { # [doc = "Register `INTSTAT` reader"]
pub type R = crate :: R < IntstatSpec > ; # [doc = "Register `INTSTAT` writer"]
pub type W = crate :: W < IntstatSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntstatSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntstatSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntstatSpec ; impl crate :: RegisterSpec for IntstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intstat::R`](R) reader structure"]
impl crate :: Readable for IntstatSpec { } # [doc = "`write(|w| ..)` method takes [`intstat::W`](W) writer structure"]
impl crate :: Writable for IntstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTSTAT to value 0"]
impl crate :: Resettable for IntstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
# [doc (alias = "INTEN")]
pub type Inten = crate :: Reg < inten :: IntenSpec > ; # [doc = "Interrupt Enable Register"]
pub mod inten { # [doc = "Register `INTEN` reader"]
pub type R = crate :: R < IntenSpec > ; # [doc = "Register `INTEN` writer"]
pub type W = crate :: W < IntenSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntenSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntenSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenSpec ; impl crate :: RegisterSpec for IntenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`inten::R`](R) reader structure"]
impl crate :: Readable for IntenSpec { } # [doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
impl crate :: Writable for IntenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTEN to value 0"]
impl crate :: Resettable for IntenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCLR (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`]
module"]
# [doc (alias = "INTCLR")]
pub type Intclr = crate :: Reg < intclr :: IntclrSpec > ; # [doc = "Interrupt Clear Register"]
pub mod intclr { # [doc = "Register `INTCLR` reader"]
pub type R = crate :: R < IntclrSpec > ; # [doc = "Register `INTCLR` writer"]
pub type W = crate :: W < IntclrSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntclrSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntclrSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntclrSpec ; impl crate :: RegisterSpec for IntclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intclr::R`](R) reader structure"]
impl crate :: Readable for IntclrSpec { } # [doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"]
impl crate :: Writable for IntclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCLR to value 0"]
impl crate :: Resettable for IntclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCMD (rw) register accessor: Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intcmd`]
module"]
# [doc (alias = "INTCMD")]
pub type Intcmd = crate :: Reg < intcmd :: IntcmdSpec > ; # [doc = "Interrupt Command Register"]
pub mod intcmd { # [doc = "Register `INTCMD` reader"]
pub type R = crate :: R < IntcmdSpec > ; # [doc = "Register `INTCMD` writer"]
pub type W = crate :: W < IntcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_INTERRUPT` reader - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptR = crate :: BitReader ; # [doc = "Field `SET_TPTC_INTERRUPT` writer - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_interrupt (& self) -> SetTptcInterruptR { SetTptcInterruptR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < IntcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_interrupt (& mut self) -> SetTptcInterruptW < IntcmdSpec > { SetTptcInterruptW :: new (self , 1) } } # [doc = "Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntcmdSpec ; impl crate :: RegisterSpec for IntcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intcmd::R`](R) reader structure"]
impl crate :: Readable for IntcmdSpec { } # [doc = "`write(|w| ..)` method takes [`intcmd::W`](W) writer structure"]
impl crate :: Writable for IntcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCMD to value 0"]
impl crate :: Resettable for IntcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRSTAT (rw) register accessor: Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errstat`]
module"]
# [doc (alias = "ERRSTAT")]
pub type Errstat = crate :: Reg < errstat :: ErrstatSpec > ; # [doc = "Error Status Register"]
pub mod errstat { # [doc = "Register `ERRSTAT` reader"]
pub type R = crate :: R < ErrstatSpec > ; # [doc = "Register `ERRSTAT` writer"]
pub type W = crate :: W < ErrstatSpec > ; # [doc = "Field `BUS_ERROR_EVENT` reader - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventR = crate :: BitReader ; # [doc = "Field `BUS_ERROR_EVENT` writer - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_ERROR` reader - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorR = crate :: BitReader ; # [doc = "Field `TR_ERROR` writer - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMR_ADDRESS_ERROR` reader - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorR = crate :: BitReader ; # [doc = "Field `MMR_ADDRESS_ERROR` writer - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
pub fn bus_error_event (& self) -> BusErrorEventR { BusErrorEventR :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
pub fn tr_error (& self) -> TrErrorR { TrErrorR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
pub fn mmr_address_error (& self) -> MmrAddressErrorR { MmrAddressErrorR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
# [must_use]
pub fn bus_error_event (& mut self) -> BusErrorEventW < ErrstatSpec > { BusErrorEventW :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn tr_error (& mut self) -> TrErrorW < ErrstatSpec > { TrErrorW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn mmr_address_error (& mut self) -> MmrAddressErrorW < ErrstatSpec > { MmrAddressErrorW :: new (self , 3) } } # [doc = "Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrstatSpec ; impl crate :: RegisterSpec for ErrstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errstat::R`](R) reader structure"]
impl crate :: Readable for ErrstatSpec { } # [doc = "`write(|w| ..)` method takes [`errstat::W`](W) writer structure"]
impl crate :: Writable for ErrstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRSTAT to value 0"]
impl crate :: Resettable for ErrstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERREN (rw) register accessor: Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erren`]
module"]
# [doc (alias = "ERREN")]
pub type Erren = crate :: Reg < erren :: ErrenSpec > ; # [doc = "Error Enable Register"]
pub mod erren { # [doc = "Register `ERREN` reader"]
pub type R = crate :: R < ErrenSpec > ; # [doc = "Register `ERREN` writer"]
pub type W = crate :: W < ErrenSpec > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` reader - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` writer - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` reader - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` writer - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR` reader - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR` writer - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_2 (& self) -> InterruptEnableFor2R { InterruptEnableFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_1 (& self) -> InterruptEnableFor1R { InterruptEnableFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for (& self) -> InterruptEnableForR { InterruptEnableForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_2 (& mut self) -> InterruptEnableFor2W < ErrenSpec > { InterruptEnableFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_1 (& mut self) -> InterruptEnableFor1W < ErrenSpec > { InterruptEnableFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for (& mut self) -> InterruptEnableForW < ErrenSpec > { InterruptEnableForW :: new (self , 3) } } # [doc = "Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrenSpec ; impl crate :: RegisterSpec for ErrenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erren::R`](R) reader structure"]
impl crate :: Readable for ErrenSpec { } # [doc = "`write(|w| ..)` method takes [`erren::W`](W) writer structure"]
impl crate :: Writable for ErrenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERREN to value 0"]
impl crate :: Resettable for ErrenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCLR (rw) register accessor: Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errclr`]
module"]
# [doc (alias = "ERRCLR")]
pub type Errclr = crate :: Reg < errclr :: ErrclrSpec > ; # [doc = "Error Clear Register"]
pub mod errclr { # [doc = "Register `ERRCLR` reader"]
pub type R = crate :: R < ErrclrSpec > ; # [doc = "Register `ERRCLR` writer"]
pub type W = crate :: W < ErrclrSpec > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` reader - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` writer - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` reader - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` writer - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR` reader - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR` writer - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_2 (& self) -> InterruptClearFor2R { InterruptClearFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_1 (& self) -> InterruptClearFor1R { InterruptClearFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for (& self) -> InterruptClearForR { InterruptClearForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_2 (& mut self) -> InterruptClearFor2W < ErrclrSpec > { InterruptClearFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_1 (& mut self) -> InterruptClearFor1W < ErrclrSpec > { InterruptClearFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for (& mut self) -> InterruptClearForW < ErrclrSpec > { InterruptClearForW :: new (self , 3) } } # [doc = "Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrclrSpec ; impl crate :: RegisterSpec for ErrclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errclr::R`](R) reader structure"]
impl crate :: Readable for ErrclrSpec { } # [doc = "`write(|w| ..)` method takes [`errclr::W`](W) writer structure"]
impl crate :: Writable for ErrclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCLR to value 0"]
impl crate :: Resettable for ErrclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRDET (rw) register accessor: Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errdet`]
module"]
# [doc (alias = "ERRDET")]
pub type Errdet = crate :: Reg < errdet :: ErrdetSpec > ; # [doc = "Error Details Register"]
pub mod errdet { # [doc = "Register `ERRDET` reader"]
pub type R = crate :: R < ErrdetSpec > ; # [doc = "Register `ERRDET` writer"]
pub type W = crate :: W < ErrdetSpec > ; # [doc = "Field `TRANSACTION_STATUS` reader - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusR = crate :: FieldReader ; # [doc = "Field `TRANSACTION_STATUS` writer - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` reader - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` writer - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` reader - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` writer - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
pub fn transaction_status (& self) -> TransactionStatusR { TransactionStatusR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcinten (& self) -> ContainsTheOptTcintenR { ContainsTheOptTcintenR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcchen (& self) -> ContainsTheOptTcchenR { ContainsTheOptTcchenR :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
# [must_use]
pub fn transaction_status (& mut self) -> TransactionStatusW < ErrdetSpec > { TransactionStatusW :: new (self , 0) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < ErrdetSpec > { TransferCompleteCodeW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcinten (& mut self) -> ContainsTheOptTcintenW < ErrdetSpec > { ContainsTheOptTcintenW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcchen (& mut self) -> ContainsTheOptTcchenW < ErrdetSpec > { ContainsTheOptTcchenW :: new (self , 17) } } # [doc = "Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrdetSpec ; impl crate :: RegisterSpec for ErrdetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errdet::R`](R) reader structure"]
impl crate :: Readable for ErrdetSpec { } # [doc = "`write(|w| ..)` method takes [`errdet::W`](W) writer structure"]
impl crate :: Writable for ErrdetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRDET to value 0"]
impl crate :: Resettable for ErrdetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCMD (rw) register accessor: Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errcmd`]
module"]
# [doc (alias = "ERRCMD")]
pub type Errcmd = crate :: Reg < errcmd :: ErrcmdSpec > ; # [doc = "Error Command Register"]
pub mod errcmd { # [doc = "Register `ERRCMD` reader"]
pub type R = crate :: R < ErrcmdSpec > ; # [doc = "Register `ERRCMD` writer"]
pub type W = crate :: W < ErrcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_ERROR` reader - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorR = crate :: BitReader ; # [doc = "Field `SET_TPTC_ERROR` writer - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_error (& self) -> SetTptcErrorR { SetTptcErrorR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < ErrcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_error (& mut self) -> SetTptcErrorW < ErrcmdSpec > { SetTptcErrorW :: new (self , 1) } } # [doc = "Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrcmdSpec ; impl crate :: RegisterSpec for ErrcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errcmd::R`](R) reader structure"]
impl crate :: Readable for ErrcmdSpec { } # [doc = "`write(|w| ..)` method takes [`errcmd::W`](W) writer structure"]
impl crate :: Writable for ErrcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCMD to value 0"]
impl crate :: Resettable for ErrcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RDRATE (rw) register accessor: Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdrate`]
module"]
# [doc (alias = "RDRATE")]
pub type Rdrate = crate :: Reg < rdrate :: RdrateSpec > ; # [doc = "Read Rate Register"]
pub mod rdrate { # [doc = "Register `RDRATE` reader"]
pub type R = crate :: R < RdrateSpec > ; # [doc = "Register `RDRATE` writer"]
pub type W = crate :: W < RdrateSpec > ; # [doc = "Field `READ_RATE_CONTROL` reader - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlR = crate :: FieldReader ; # [doc = "Field `READ_RATE_CONTROL` writer - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
pub fn read_rate_control (& self) -> ReadRateControlR { ReadRateControlR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
# [must_use]
pub fn read_rate_control (& mut self) -> ReadRateControlW < RdrateSpec > { ReadRateControlW :: new (self , 0) } } # [doc = "Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrateSpec ; impl crate :: RegisterSpec for RdrateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rdrate::R`](R) reader structure"]
impl crate :: Readable for RdrateSpec { } # [doc = "`write(|w| ..)` method takes [`rdrate::W`](W) writer structure"]
impl crate :: Writable for RdrateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RDRATE to value 0"]
impl crate :: Resettable for RdrateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "POPT (rw) register accessor: Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@popt`]
module"]
# [doc (alias = "POPT")]
pub type Popt = crate :: Reg < popt :: PoptSpec > ; # [doc = "Prog Set Options"]
pub mod popt { # [doc = "Register `POPT` reader"]
pub type R = crate :: R < PoptSpec > ; # [doc = "Register `POPT` writer"]
pub type W = crate :: W < PoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < PoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < PoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < PoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < PoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < PoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < PoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < PoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < PoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PoptSpec ; impl crate :: RegisterSpec for PoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`popt::R`](R) reader structure"]
impl crate :: Readable for PoptSpec { } # [doc = "`write(|w| ..)` method takes [`popt::W`](W) writer structure"]
impl crate :: Writable for PoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets POPT to value 0"]
impl crate :: Resettable for PoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSRC (rw) register accessor: Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psrc`]
module"]
# [doc (alias = "PSRC")]
pub type Psrc = crate :: Reg < psrc :: PsrcSpec > ; # [doc = "Prog Set Src Address"]
pub mod psrc { # [doc = "Register `PSRC` reader"]
pub type R = crate :: R < PsrcSpec > ; # [doc = "Register `PSRC` writer"]
pub type W = crate :: W < PsrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR` reader - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR` writer - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
pub fn source_address_for (& self) -> SourceAddressForR { SourceAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for (& mut self) -> SourceAddressForW < PsrcSpec > { SourceAddressForW :: new (self , 0) } } # [doc = "Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsrcSpec ; impl crate :: RegisterSpec for PsrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`psrc::R`](R) reader structure"]
impl crate :: Readable for PsrcSpec { } # [doc = "`write(|w| ..)` method takes [`psrc::W`](W) writer structure"]
impl crate :: Writable for PsrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSRC to value 0"]
impl crate :: Resettable for PsrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCNT (rw) register accessor: Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcnt`]
module"]
# [doc (alias = "PCNT")]
pub type Pcnt = crate :: Reg < pcnt :: PcntSpec > ; # [doc = "Prog Set Count"]
pub mod pcnt { # [doc = "Register `PCNT` reader"]
pub type R = crate :: R < PcntSpec > ; # [doc = "Register `PCNT` writer"]
pub type W = crate :: W < PcntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` reader - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` writer - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
pub fn bdimension_count__number (& self) -> BdimensionCount_NumberR { BdimensionCount_NumberR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < PcntSpec > { AdimensionCount_NumberW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
# [must_use]
pub fn bdimension_count__number (& mut self) -> BdimensionCount_NumberW < PcntSpec > { BdimensionCount_NumberW :: new (self , 16) } } # [doc = "Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcntSpec ; impl crate :: RegisterSpec for PcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcnt::R`](R) reader structure"]
impl crate :: Readable for PcntSpec { } # [doc = "`write(|w| ..)` method takes [`pcnt::W`](W) writer structure"]
impl crate :: Writable for PcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCNT to value 0"]
impl crate :: Resettable for PcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PDST (rw) register accessor: Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdst`]
module"]
# [doc (alias = "PDST")]
pub type Pdst = crate :: Reg < pdst :: PdstSpec > ; # [doc = "Prog Set Dst Address"]
pub mod pdst { # [doc = "Register `PDST` reader"]
pub type R = crate :: R < PdstSpec > ; # [doc = "Register `PDST` writer"]
pub type W = crate :: W < PdstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` reader - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` writer - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
pub fn destination_address_for (& self) -> DestinationAddressForR { DestinationAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for (& mut self) -> DestinationAddressForW < PdstSpec > { DestinationAddressForW :: new (self , 0) } } # [doc = "Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PdstSpec ; impl crate :: RegisterSpec for PdstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pdst::R`](R) reader structure"]
impl crate :: Readable for PdstSpec { } # [doc = "`write(|w| ..)` method takes [`pdst::W`](W) writer structure"]
impl crate :: Writable for PdstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PDST to value 0"]
impl crate :: Resettable for PdstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIDX (rw) register accessor: Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbidx`]
module"]
# [doc (alias = "PBIDX")]
pub type Pbidx = crate :: Reg < pbidx :: PbidxSpec > ; # [doc = "Prog Set B-Dim Idx"]
pub mod pbidx { # [doc = "Register `PBIDX` reader"]
pub type R = crate :: R < PbidxSpec > ; # [doc = "Register `PBIDX` writer"]
pub type W = crate :: W < PbidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < PbidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < PbidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbidxSpec ; impl crate :: RegisterSpec for PbidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbidx::R`](R) reader structure"]
impl crate :: Readable for PbidxSpec { } # [doc = "`write(|w| ..)` method takes [`pbidx::W`](W) writer structure"]
impl crate :: Writable for PbidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIDX to value 0"]
impl crate :: Resettable for PbidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PMPPRXY (rw) register accessor: Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmpprxy`]
module"]
# [doc (alias = "PMPPRXY")]
pub type Pmpprxy = crate :: Reg < pmpprxy :: PmpprxySpec > ; # [doc = "Prog Set Mem Protect Proxy"]
pub mod pmpprxy { # [doc = "Register `PMPPRXY` reader"]
pub type R = crate :: R < PmpprxySpec > ; # [doc = "Register `PMPPRXY` writer"]
pub type W = crate :: W < PmpprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < PmpprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < PmpprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < PmpprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmpprxySpec ; impl crate :: RegisterSpec for PmpprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmpprxy::R`](R) reader structure"]
impl crate :: Readable for PmpprxySpec { } # [doc = "`write(|w| ..)` method takes [`pmpprxy::W`](W) writer structure"]
impl crate :: Writable for PmpprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PMPPRXY to value 0"]
impl crate :: Resettable for PmpprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAOPT (rw) register accessor: Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@saopt`]
module"]
# [doc (alias = "SAOPT")]
pub type Saopt = crate :: Reg < saopt :: SaoptSpec > ; # [doc = "Src Actv Set Options"]
pub mod saopt { # [doc = "Register `SAOPT` reader"]
pub type R = crate :: R < SaoptSpec > ; # [doc = "Register `SAOPT` writer"]
pub type W = crate :: W < SaoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < SaoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < SaoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < SaoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < SaoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < SaoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < SaoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < SaoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < SaoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SaoptSpec ; impl crate :: RegisterSpec for SaoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`saopt::R`](R) reader structure"]
impl crate :: Readable for SaoptSpec { } # [doc = "`write(|w| ..)` method takes [`saopt::W`](W) writer structure"]
impl crate :: Writable for SaoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAOPT to value 0"]
impl crate :: Resettable for SaoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRC (rw) register accessor: Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrc`]
module"]
# [doc (alias = "SASRC")]
pub type Sasrc = crate :: Reg < sasrc :: SasrcSpec > ; # [doc = "Src Actv Set Src Address"]
pub mod sasrc { # [doc = "Register `SASRC` reader"]
pub type R = crate :: R < SasrcSpec > ; # [doc = "Register `SASRC` writer"]
pub type W = crate :: W < SasrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` reader - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` writer - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
pub fn source_address_for_1 (& self) -> SourceAddressFor1R { SourceAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for_1 (& mut self) -> SourceAddressFor1W < SasrcSpec > { SourceAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcSpec ; impl crate :: RegisterSpec for SasrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrc::R`](R) reader structure"]
impl crate :: Readable for SasrcSpec { } # [doc = "`write(|w| ..)` method takes [`sasrc::W`](W) writer structure"]
impl crate :: Writable for SasrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRC to value 0"]
impl crate :: Resettable for SasrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNT (rw) register accessor: Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacnt`]
module"]
# [doc (alias = "SACNT")]
pub type Sacnt = crate :: Reg < sacnt :: SacntSpec > ; # [doc = "Src Actv Set A-Count"]
pub mod sacnt { # [doc = "Register `SACNT` reader"]
pub type R = crate :: R < SacntSpec > ; # [doc = "Register `SACNT` writer"]
pub type W = crate :: W < SacntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < SacntSpec > { AdimensionCount_NumberW :: new (self , 0) } } # [doc = "Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntSpec ; impl crate :: RegisterSpec for SacntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacnt::R`](R) reader structure"]
impl crate :: Readable for SacntSpec { } # [doc = "`write(|w| ..)` method takes [`sacnt::W`](W) writer structure"]
impl crate :: Writable for SacntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNT to value 0"]
impl crate :: Resettable for SacntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADST (rw) register accessor: Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadst`]
module"]
# [doc (alias = "SADST")]
pub type Sadst = crate :: Reg < sadst :: SadstSpec > ; # [doc = "Src Actv Set Dst Address"]
pub mod sadst { # [doc = "Register `SADST` reader"]
pub type R = crate :: R < SadstSpec > ; # [doc = "Register `SADST` writer"]
pub type W = crate :: W < SadstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` reader - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` writer - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
pub fn destination_address_for_1 (& self) -> DestinationAddressFor1R { DestinationAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for_1 (& mut self) -> DestinationAddressFor1W < SadstSpec > { DestinationAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstSpec ; impl crate :: RegisterSpec for SadstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadst::R`](R) reader structure"]
impl crate :: Readable for SadstSpec { } # [doc = "`write(|w| ..)` method takes [`sadst::W`](W) writer structure"]
impl crate :: Writable for SadstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADST to value 0"]
impl crate :: Resettable for SadstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABIDX (rw) register accessor: Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabidx`]
module"]
# [doc (alias = "SABIDX")]
pub type Sabidx = crate :: Reg < sabidx :: SabidxSpec > ; # [doc = "Src Actv Set B-Dim Idx"]
pub mod sabidx { # [doc = "Register `SABIDX` reader"]
pub type R = crate :: R < SabidxSpec > ; # [doc = "Register `SABIDX` writer"]
pub type W = crate :: W < SabidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < SabidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < SabidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabidxSpec ; impl crate :: RegisterSpec for SabidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabidx::R`](R) reader structure"]
impl crate :: Readable for SabidxSpec { } # [doc = "`write(|w| ..)` method takes [`sabidx::W`](W) writer structure"]
impl crate :: Writable for SabidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABIDX to value 0"]
impl crate :: Resettable for SabidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAMPPRXY (rw) register accessor: Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sampprxy`]
module"]
# [doc (alias = "SAMPPRXY")]
pub type Sampprxy = crate :: Reg < sampprxy :: SampprxySpec > ; # [doc = "Src Actv Set Mem Protect Proxy"]
pub mod sampprxy { # [doc = "Register `SAMPPRXY` reader"]
pub type R = crate :: R < SampprxySpec > ; # [doc = "Register `SAMPPRXY` writer"]
pub type W = crate :: W < SampprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < SampprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < SampprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < SampprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SampprxySpec ; impl crate :: RegisterSpec for SampprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sampprxy::R`](R) reader structure"]
impl crate :: Readable for SampprxySpec { } # [doc = "`write(|w| ..)` method takes [`sampprxy::W`](W) writer structure"]
impl crate :: Writable for SampprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAMPPRXY to value 0"]
impl crate :: Resettable for SampprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNTRLD (rw) register accessor: Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacntrld`]
module"]
# [doc (alias = "SACNTRLD")]
pub type Sacntrld = crate :: Reg < sacntrld :: SacntrldSpec > ; # [doc = "Src Actv Set Cnt Reload"]
pub mod sacntrld { # [doc = "Register `SACNTRLD` reader"]
pub type R = crate :: R < SacntrldSpec > ; # [doc = "Register `SACNTRLD` writer"]
pub type W = crate :: W < SacntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE` reader - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueR = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE` writer - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value (& self) -> AcntReloadValueR { AcntReloadValueR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value (& mut self) -> AcntReloadValueW < SacntrldSpec > { AcntReloadValueW :: new (self , 0) } } # [doc = "Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntrldSpec ; impl crate :: RegisterSpec for SacntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacntrld::R`](R) reader structure"]
impl crate :: Readable for SacntrldSpec { } # [doc = "`write(|w| ..)` method takes [`sacntrld::W`](W) writer structure"]
impl crate :: Writable for SacntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNTRLD to value 0"]
impl crate :: Resettable for SacntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRCBREF (rw) register accessor: Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrcbref`]
module"]
# [doc (alias = "SASRCBREF")]
pub type Sasrcbref = crate :: Reg < sasrcbref :: SasrcbrefSpec > ; # [doc = "Src Actv Set Src Addr B-Reference"]
pub mod sasrcbref { # [doc = "Register `SASRCBREF` reader"]
pub type R = crate :: R < SasrcbrefSpec > ; # [doc = "Register `SASRCBREF` writer"]
pub type W = crate :: W < SasrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` reader - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` writer - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference (& self) -> SourceAddressReferenceR { SourceAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference (& mut self) -> SourceAddressReferenceW < SasrcbrefSpec > { SourceAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcbrefSpec ; impl crate :: RegisterSpec for SasrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrcbref::R`](R) reader structure"]
impl crate :: Readable for SasrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sasrcbref::W`](W) writer structure"]
impl crate :: Writable for SasrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRCBREF to value 0"]
impl crate :: Resettable for SasrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADSTBREF (rw) register accessor: Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadstbref`]
module"]
# [doc (alias = "SADSTBREF")]
pub type Sadstbref = crate :: Reg < sadstbref :: SadstbrefSpec > ; # [doc = "Src Actv Set Dst Addr B-Reference"]
pub mod sadstbref { # [doc = "Register `SADSTBREF` reader"]
pub type R = crate :: R < SadstbrefSpec > ; # [doc = "Register `SADSTBREF` writer"]
pub type W = crate :: W < SadstbrefSpec > ; # [doc = "Field `DST_ADDRESS_REFERENCE` reader - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `DST_ADDRESS_REFERENCE` writer - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
pub fn dst_address_reference (& self) -> DstAddressReferenceR { DstAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn dst_address_reference (& mut self) -> DstAddressReferenceW < SadstbrefSpec > { DstAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstbrefSpec ; impl crate :: RegisterSpec for SadstbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadstbref::R`](R) reader structure"]
impl crate :: Readable for SadstbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sadstbref::W`](W) writer structure"]
impl crate :: Writable for SadstbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADSTBREF to value 0"]
impl crate :: Resettable for SadstbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABCNT (rw) register accessor: Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabcnt`]
module"]
# [doc (alias = "SABCNT")]
pub type Sabcnt = crate :: Reg < sabcnt :: SabcntSpec > ; # [doc = "Src Actv Set B-Count"]
pub mod sabcnt { # [doc = "Register `SABCNT` reader"]
pub type R = crate :: R < SabcntSpec > ; # [doc = "Register `SABCNT` writer"]
pub type W = crate :: W < SabcntSpec > ; # [doc = "Field `BDIMENSION_COUNT` reader - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT` writer - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bdimension_count (& self) -> BdimensionCountR { BdimensionCountR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bdimension_count (& mut self) -> BdimensionCountW < SabcntSpec > { BdimensionCountW :: new (self , 0) } } # [doc = "Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabcntSpec ; impl crate :: RegisterSpec for SabcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabcnt::R`](R) reader structure"]
impl crate :: Readable for SabcntSpec { } # [doc = "`write(|w| ..)` method takes [`sabcnt::W`](W) writer structure"]
impl crate :: Writable for SabcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABCNT to value 0"]
impl crate :: Resettable for SabcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFCNTRLD (rw) register accessor: Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfcntrld`]
module"]
# [doc (alias = "DFCNTRLD")]
pub type Dfcntrld = crate :: Reg < dfcntrld :: DfcntrldSpec > ; # [doc = "Dst FIFO Set Cnt Reload"]
pub mod dfcntrld { # [doc = "Register `DFCNTRLD` reader"]
pub type R = crate :: R < DfcntrldSpec > ; # [doc = "Register `DFCNTRLD` writer"]
pub type W = crate :: W < DfcntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` reader - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1R = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` writer - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value_1 (& self) -> AcntReloadValue1R { AcntReloadValue1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value_1 (& mut self) -> AcntReloadValue1W < DfcntrldSpec > { AcntReloadValue1W :: new (self , 0) } } # [doc = "Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfcntrldSpec ; impl crate :: RegisterSpec for DfcntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfcntrld::R`](R) reader structure"]
impl crate :: Readable for DfcntrldSpec { } # [doc = "`write(|w| ..)` method takes [`dfcntrld::W`](W) writer structure"]
impl crate :: Writable for DfcntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFCNTRLD to value 0"]
impl crate :: Resettable for DfcntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRCBREF (rw) register accessor: Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrcbref`]
module"]
# [doc (alias = "DFSRCBREF")]
pub type Dfsrcbref = crate :: Reg < dfsrcbref :: DfsrcbrefSpec > ; # [doc = "Dst FIFO Set Src Addr B-Reference"]
pub mod dfsrcbref { # [doc = "Register `DFSRCBREF` reader"]
pub type R = crate :: R < DfsrcbrefSpec > ; # [doc = "Register `DFSRCBREF` writer"]
pub type W = crate :: W < DfsrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` reader - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` writer - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference_1 (& self) -> SourceAddressReference1R { SourceAddressReference1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference_1 (& mut self) -> SourceAddressReference1W < DfsrcbrefSpec > { SourceAddressReference1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfsrcbrefSpec ; impl crate :: RegisterSpec for DfsrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrcbref::R`](R) reader structure"]
impl crate :: Readable for DfsrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`dfsrcbref::W`](W) writer structure"]
impl crate :: Writable for DfsrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRCBREF to value 0"]
impl crate :: Resettable for DfsrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT0 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt0`]
module"]
# [doc (alias = "DFOPT0")]
pub type Dfopt0 = crate :: Reg < dfopt0 :: Dfopt0Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt0 { # [doc = "Register `DFOPT0` reader"]
pub type R = crate :: R < Dfopt0Spec > ; # [doc = "Register `DFOPT0` writer"]
pub type W = crate :: W < Dfopt0Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt0Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt0Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt0Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt0Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt0Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt0Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt0Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt0Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt0Spec ; impl crate :: RegisterSpec for Dfopt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt0::R`](R) reader structure"]
impl crate :: Readable for Dfopt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt0::W`](W) writer structure"]
impl crate :: Writable for Dfopt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT0 to value 0"]
impl crate :: Resettable for Dfopt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC0 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc0`]
module"]
# [doc (alias = "DFSRC0")]
pub type Dfsrc0 = crate :: Reg < dfsrc0 :: Dfsrc0Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc0 { # [doc = "Register `DFSRC0` reader"]
pub type R = crate :: R < Dfsrc0Spec > ; # [doc = "Register `DFSRC0` writer"]
pub type W = crate :: W < Dfsrc0Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is (& self) -> SourceAddressIsR { SourceAddressIsR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is (& mut self) -> SourceAddressIsW < Dfsrc0Spec > { SourceAddressIsW :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc0Spec ; impl crate :: RegisterSpec for Dfsrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc0::R`](R) reader structure"]
impl crate :: Readable for Dfsrc0Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc0::W`](W) writer structure"]
impl crate :: Writable for Dfsrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC0 to value 0"]
impl crate :: Resettable for Dfsrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT0 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt0`]
module"]
# [doc (alias = "DFACNT0")]
pub type Dfacnt0 = crate :: Reg < dfacnt0 :: Dfacnt0Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt0 { # [doc = "Register `DFACNT0` reader"]
pub type R = crate :: R < Dfacnt0Spec > ; # [doc = "Register `DFACNT0` writer"]
pub type W = crate :: W < Dfacnt0Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_1 (& self) -> AdimensionCount_Number1R { AdimensionCount_Number1R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_1 (& mut self) -> AdimensionCount_Number1W < Dfacnt0Spec > { AdimensionCount_Number1W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt0Spec ; impl crate :: RegisterSpec for Dfacnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt0::R`](R) reader structure"]
impl crate :: Readable for Dfacnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt0::W`](W) writer structure"]
impl crate :: Writable for Dfacnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT0 to value 0"]
impl crate :: Resettable for Dfacnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST0 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst0`]
module"]
# [doc (alias = "DFDST0")]
pub type Dfdst0 = crate :: Reg < dfdst0 :: Dfdst0Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst0 { # [doc = "Register `DFDST0` reader"]
pub type R = crate :: R < Dfdst0Spec > ; # [doc = "Register `DFDST0` writer"]
pub type W = crate :: W < Dfdst0Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_2 (& self) -> DestinationAddressFor2R { DestinationAddressFor2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_2 (& mut self) -> DestinationAddressFor2W < Dfdst0Spec > { DestinationAddressFor2W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst0Spec ; impl crate :: RegisterSpec for Dfdst0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst0::R`](R) reader structure"]
impl crate :: Readable for Dfdst0Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst0::W`](W) writer structure"]
impl crate :: Writable for Dfdst0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST0 to value 0"]
impl crate :: Resettable for Dfdst0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX0 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx0`]
module"]
# [doc (alias = "DFBIDX0")]
pub type Dfbidx0 = crate :: Reg < dfbidx0 :: Dfbidx0Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx0 { # [doc = "Register `DFBIDX0` reader"]
pub type R = crate :: R < Dfbidx0Spec > ; # [doc = "Register `DFBIDX0` writer"]
pub type W = crate :: W < Dfbidx0Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx0Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx0Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx0Spec ; impl crate :: RegisterSpec for Dfbidx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx0::R`](R) reader structure"]
impl crate :: Readable for Dfbidx0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx0::W`](W) writer structure"]
impl crate :: Writable for Dfbidx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX0 to value 0"]
impl crate :: Resettable for Dfbidx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY0 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy0`]
module"]
# [doc (alias = "DFMPPRXY0")]
pub type Dfmpprxy0 = crate :: Reg < dfmpprxy0 :: Dfmpprxy0Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy0 { # [doc = "Register `DFMPPRXY0` reader"]
pub type R = crate :: R < Dfmpprxy0Spec > ; # [doc = "Register `DFMPPRXY0` writer"]
pub type W = crate :: W < Dfmpprxy0Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy0Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy0Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy0Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy0Spec ; impl crate :: RegisterSpec for Dfmpprxy0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy0::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy0Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy0::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY0 to value 0"]
impl crate :: Resettable for Dfmpprxy0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT0 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt0`]
module"]
# [doc (alias = "DFBCNT0")]
pub type Dfbcnt0 = crate :: Reg < dfbcnt0 :: Dfbcnt0Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt0 { # [doc = "Register `DFBCNT0` reader"]
pub type R = crate :: R < Dfbcnt0Spec > ; # [doc = "Register `DFBCNT0` writer"]
pub type W = crate :: W < Dfbcnt0Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForR = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for (& self) -> BcountRemainingForR { BcountRemainingForR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for (& mut self) -> BcountRemainingForW < Dfbcnt0Spec > { BcountRemainingForW :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt0Spec ; impl crate :: RegisterSpec for Dfbcnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt0::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt0::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT0 to value 0"]
impl crate :: Resettable for Dfbcnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT1 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt1`]
module"]
# [doc (alias = "DFOPT1")]
pub type Dfopt1 = crate :: Reg < dfopt1 :: Dfopt1Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt1 { # [doc = "Register `DFOPT1` reader"]
pub type R = crate :: R < Dfopt1Spec > ; # [doc = "Register `DFOPT1` writer"]
pub type W = crate :: W < Dfopt1Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt1Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt1Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt1Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt1Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt1Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt1Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt1Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt1Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt1Spec ; impl crate :: RegisterSpec for Dfopt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt1::R`](R) reader structure"]
impl crate :: Readable for Dfopt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt1::W`](W) writer structure"]
impl crate :: Writable for Dfopt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT1 to value 0"]
impl crate :: Resettable for Dfopt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC1 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc1`]
module"]
# [doc (alias = "DFSRC1")]
pub type Dfsrc1 = crate :: Reg < dfsrc1 :: Dfsrc1Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc1 { # [doc = "Register `DFSRC1` reader"]
pub type R = crate :: R < Dfsrc1Spec > ; # [doc = "Register `DFSRC1` writer"]
pub type W = crate :: W < Dfsrc1Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is_1 (& self) -> SourceAddressIs1R { SourceAddressIs1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is_1 (& mut self) -> SourceAddressIs1W < Dfsrc1Spec > { SourceAddressIs1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc1Spec ; impl crate :: RegisterSpec for Dfsrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc1::R`](R) reader structure"]
impl crate :: Readable for Dfsrc1Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc1::W`](W) writer structure"]
impl crate :: Writable for Dfsrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC1 to value 0"]
impl crate :: Resettable for Dfsrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT1 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt1`]
module"]
# [doc (alias = "DFACNT1")]
pub type Dfacnt1 = crate :: Reg < dfacnt1 :: Dfacnt1Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt1 { # [doc = "Register `DFACNT1` reader"]
pub type R = crate :: R < Dfacnt1Spec > ; # [doc = "Register `DFACNT1` writer"]
pub type W = crate :: W < Dfacnt1Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_2 (& self) -> AdimensionCount_Number2R { AdimensionCount_Number2R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_2 (& mut self) -> AdimensionCount_Number2W < Dfacnt1Spec > { AdimensionCount_Number2W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt1Spec ; impl crate :: RegisterSpec for Dfacnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt1::R`](R) reader structure"]
impl crate :: Readable for Dfacnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt1::W`](W) writer structure"]
impl crate :: Writable for Dfacnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT1 to value 0"]
impl crate :: Resettable for Dfacnt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST1 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst1`]
module"]
# [doc (alias = "DFDST1")]
pub type Dfdst1 = crate :: Reg < dfdst1 :: Dfdst1Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst1 { # [doc = "Register `DFDST1` reader"]
pub type R = crate :: R < Dfdst1Spec > ; # [doc = "Register `DFDST1` writer"]
pub type W = crate :: W < Dfdst1Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_3 (& self) -> DestinationAddressFor3R { DestinationAddressFor3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_3 (& mut self) -> DestinationAddressFor3W < Dfdst1Spec > { DestinationAddressFor3W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst1Spec ; impl crate :: RegisterSpec for Dfdst1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst1::R`](R) reader structure"]
impl crate :: Readable for Dfdst1Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst1::W`](W) writer structure"]
impl crate :: Writable for Dfdst1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST1 to value 0"]
impl crate :: Resettable for Dfdst1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX1 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx1`]
module"]
# [doc (alias = "DFBIDX1")]
pub type Dfbidx1 = crate :: Reg < dfbidx1 :: Dfbidx1Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx1 { # [doc = "Register `DFBIDX1` reader"]
pub type R = crate :: R < Dfbidx1Spec > ; # [doc = "Register `DFBIDX1` writer"]
pub type W = crate :: W < Dfbidx1Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx1Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx1Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx1Spec ; impl crate :: RegisterSpec for Dfbidx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx1::R`](R) reader structure"]
impl crate :: Readable for Dfbidx1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx1::W`](W) writer structure"]
impl crate :: Writable for Dfbidx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX1 to value 0"]
impl crate :: Resettable for Dfbidx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY1 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy1`]
module"]
# [doc (alias = "DFMPPRXY1")]
pub type Dfmpprxy1 = crate :: Reg < dfmpprxy1 :: Dfmpprxy1Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy1 { # [doc = "Register `DFMPPRXY1` reader"]
pub type R = crate :: R < Dfmpprxy1Spec > ; # [doc = "Register `DFMPPRXY1` writer"]
pub type W = crate :: W < Dfmpprxy1Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy1Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy1Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy1Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy1Spec ; impl crate :: RegisterSpec for Dfmpprxy1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy1::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy1Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy1::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY1 to value 0"]
impl crate :: Resettable for Dfmpprxy1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT1 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt1`]
module"]
# [doc (alias = "DFBCNT1")]
pub type Dfbcnt1 = crate :: Reg < dfbcnt1 :: Dfbcnt1Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt1 { # [doc = "Register `DFBCNT1` reader"]
pub type R = crate :: R < Dfbcnt1Spec > ; # [doc = "Register `DFBCNT1` writer"]
pub type W = crate :: W < Dfbcnt1Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1R = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for_1 (& self) -> BcountRemainingFor1R { BcountRemainingFor1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for_1 (& mut self) -> BcountRemainingFor1W < Dfbcnt1Spec > { BcountRemainingFor1W :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt1Spec ; impl crate :: RegisterSpec for Dfbcnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt1::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt1::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT1 to value 0"]
impl crate :: Resettable for Dfbcnt1Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_CRC"]
pub struct AppCrc { _marker : PhantomData < * const () > } unsafe impl Send for AppCrc { } impl AppCrc { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_crc :: RegisterBlock = 0x5402_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_crc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppCrc { type Target = app_crc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppCrc { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppCrc") . finish () } } # [doc = "APP_CRC"]
pub mod app_crc { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { crc_ctrl0 : CrcCtrl0 , _reserved1 : [u8 ; 0x04]
, crc_ctrl1 : CrcCtrl1 , _reserved2 : [u8 ; 0x04]
, crc_ctrl2 : CrcCtrl2 , _reserved3 : [u8 ; 0x04]
, crc_ints : CrcInts , _reserved4 : [u8 ; 0x04]
, crc_intr : CrcIntr , _reserved5 : [u8 ; 0x04]
, crc_status_reg : CrcStatusReg , _reserved6 : [u8 ; 0x04]
, crc_int_offset_reg : CrcIntOffsetReg , _reserved7 : [u8 ; 0x04]
, crc_busy : CrcBusy , _reserved8 : [u8 ; 0x04]
, crc_pcount_reg1 : CrcPcountReg1 , crc_scount_reg1 : CrcScountReg1 , crc_cursec_reg1 : CrcCursecReg1 , crc_wdtopld1 : CrcWdtopld1 , crc_bctopld1 : CrcBctopld1 , _reserved13 : [u8 ; 0x0c]
, psa_sigregl1 : PsaSigregl1 , psa_sigregh1 : PsaSigregh1 , crc_regl1 : CrcRegl1 , crc_regh1 : CrcRegh1 , psa_secsigregl1 : PsaSecsigregl1 , psa_secsigregh1 : PsaSecsigregh1 , raw_dataregl1 : RawDataregl1 , raw_dataregh1 : RawDataregh1 , crc_pcount_reg2 : CrcPcountReg2 , crc_scount_reg2 : CrcScountReg2 , crc_cursec_reg2 : CrcCursecReg2 , crc_wdtopld2 : CrcWdtopld2 , crc_bctopld2 : CrcBctopld2 , _reserved26 : [u8 ; 0x0c]
, psa_sigregl2 : PsaSigregl2 , psa_sigregh2 : PsaSigregh2 , crc_regl2 : CrcRegl2 , crc_regh2 : CrcRegh2 , psa_secsigregl2 : PsaSecsigregl2 , psa_secsigregh2 : PsaSecsigregh2 , raw_dataregl2 : RawDataregl2 , raw_dataregh2 : RawDataregh2 , crc_pcount_reg3 : CrcPcountReg3 , crc_scount_reg3 : CrcScountReg3 , crc_cursec_reg3 : CrcCursecReg3 , crc_wdtopld3 : CrcWdtopld3 , crc_bctopld3 : CrcBctopld3 , _reserved39 : [u8 ; 0x0c]
, psa_sigregl3 : PsaSigregl3 , psa_sigregh3 : PsaSigregh3 , crc_regl3 : CrcRegl3 , crc_regh3 : CrcRegh3 , psa_secsigregl3 : PsaSecsigregl3 , psa_secsigregh3 : PsaSecsigregh3 , raw_dataregl3 : RawDataregl3 , raw_dataregh3 : RawDataregh3 , crc_pcount_reg4 : CrcPcountReg4 , crc_scount_reg4 : CrcScountReg4 , crc_cursec_reg4 : CrcCursecReg4 , crc_wdtopld4 : CrcWdtopld4 , crc_bctopld4 : CrcBctopld4 , _reserved52 : [u8 ; 0x0c]
, psa_sigregl4 : PsaSigregl4 , psa_sigregh4 : PsaSigregh4 , crc_regl4 : CrcRegl4 , crc_regh4 : CrcRegh4 , psa_secsigregl4 : PsaSecsigregl4 , psa_secsigregh4 : PsaSecsigregh4 , raw_dataregl4 : RawDataregl4 , raw_dataregh4 : RawDataregh4 , mcrc_bus_sel : McrcBusSel , mcrc_reserved : McrcReserved , } impl RegisterBlock { # [doc = "0x00 - Contains sw reset control bit to reset PSA"]
# [inline (always)]
pub const fn crc_ctrl0 (& self) -> & CrcCtrl0 { & self . crc_ctrl0 } # [doc = "0x08 - Contains power down control bit"]
# [inline (always)]
pub const fn crc_ctrl1 (& self) -> & CrcCtrl1 { & self . crc_ctrl1 } # [doc = "0x10 - Contains channel mode, data trace enable control bits"]
# [inline (always)]
pub const fn crc_ctrl2 (& self) -> & CrcCtrl2 { & self . crc_ctrl2 } # [doc = "0x18 - Write one to a bit to enable a interrupt"]
# [inline (always)]
pub const fn crc_ints (& self) -> & CrcInts { & self . crc_ints } # [doc = "0x20 - Write one to a bit to disable a interrupt"]
# [inline (always)]
pub const fn crc_intr (& self) -> & CrcIntr { & self . crc_intr } # [doc = "0x28 - Contains interrupt flags for different types of interrupt"]
# [inline (always)]
pub const fn crc_status_reg (& self) -> & CrcStatusReg { & self . crc_status_reg } # [doc = "0x30 - Contains the interrupt offset vector address"]
# [inline (always)]
pub const fn crc_int_offset_reg (& self) -> & CrcIntOffsetReg { & self . crc_int_offset_reg } # [doc = "0x38 - Contains the busy flag for each channel"]
# [inline (always)]
pub const fn crc_busy (& self) -> & CrcBusy { & self . crc_busy } # [doc = "0x40 - Channel 1 preload register for the pattern count"]
# [inline (always)]
pub const fn crc_pcount_reg1 (& self) -> & CrcPcountReg1 { & self . crc_pcount_reg1 } # [doc = "0x44 - Channel 1 preload register for the sector count"]
# [inline (always)]
pub const fn crc_scount_reg1 (& self) -> & CrcScountReg1 { & self . crc_scount_reg1 } # [doc = "0x48 - Channel 1 current sector register contains the sector number which causes CRC failure"]
# [inline (always)]
pub const fn crc_cursec_reg1 (& self) -> & CrcCursecReg1 { & self . crc_cursec_reg1 } # [doc = "0x4c - Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
# [inline (always)]
pub const fn crc_wdtopld1 (& self) -> & CrcWdtopld1 { & self . crc_wdtopld1 } # [doc = "0x50 - Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"]
# [inline (always)]
pub const fn crc_bctopld1 (& self) -> & CrcBctopld1 { & self . crc_bctopld1 } # [doc = "0x60 - Channel 1 PSA signature low register"]
# [inline (always)]
pub const fn psa_sigregl1 (& self) -> & PsaSigregl1 { & self . psa_sigregl1 } # [doc = "0x64 - Channel 1 PSA signature high register"]
# [inline (always)]
pub const fn psa_sigregh1 (& self) -> & PsaSigregh1 { & self . psa_sigregh1 } # [doc = "0x68 - Channel 1 CRC value low register"]
# [inline (always)]
pub const fn crc_regl1 (& self) -> & CrcRegl1 { & self . crc_regl1 } # [doc = "0x6c - Channel 1 CRC value high register"]
# [inline (always)]
pub const fn crc_regh1 (& self) -> & CrcRegh1 { & self . crc_regh1 } # [doc = "0x70 - Channel 1 PSA sector signature low regis-ter"]
# [inline (always)]
pub const fn psa_secsigregl1 (& self) -> & PsaSecsigregl1 { & self . psa_secsigregl1 } # [doc = "0x74 - Channel 1 PSA sector signature high regis-ter"]
# [inline (always)]
pub const fn psa_secsigregh1 (& self) -> & PsaSecsigregh1 { & self . psa_secsigregh1 } # [doc = "0x78 - Channel 1 un-compressed raw data low register"]
# [inline (always)]
pub const fn raw_dataregl1 (& self) -> & RawDataregl1 { & self . raw_dataregl1 } # [doc = "0x7c - Channel 1 un-compressed raw data high register"]
# [inline (always)]
pub const fn raw_dataregh1 (& self) -> & RawDataregh1 { & self . raw_dataregh1 } # [doc = "0x80 - Channel 2 preload register for the pattern count"]
# [inline (always)]
pub const fn crc_pcount_reg2 (& self) -> & CrcPcountReg2 { & self . crc_pcount_reg2 } # [doc = "0x84 - Channel 2 preload register for the sector count"]
# [inline (always)]
pub const fn crc_scount_reg2 (& self) -> & CrcScountReg2 { & self . crc_scount_reg2 } # [doc = "0x88 - Channel 2 current sector register contains the sector number which causes CRC fail-ure"]
# [inline (always)]
pub const fn crc_cursec_reg2 (& self) -> & CrcCursecReg2 { & self . crc_cursec_reg2 } # [doc = "0x8c - Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
# [inline (always)]
pub const fn crc_wdtopld2 (& self) -> & CrcWdtopld2 { & self . crc_wdtopld2 } # [doc = "0x90 - Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"]
# [inline (always)]
pub const fn crc_bctopld2 (& self) -> & CrcBctopld2 { & self . crc_bctopld2 } # [doc = "0xa0 - Channel 2 PSA signature low register"]
# [inline (always)]
pub const fn psa_sigregl2 (& self) -> & PsaSigregl2 { & self . psa_sigregl2 } # [doc = "0xa4 - Channel 2 PSA signature high register"]
# [inline (always)]
pub const fn psa_sigregh2 (& self) -> & PsaSigregh2 { & self . psa_sigregh2 } # [doc = "0xa8 - Channel 2 CRC value low register"]
# [inline (always)]
pub const fn crc_regl2 (& self) -> & CrcRegl2 { & self . crc_regl2 } # [doc = "0xac - Channel 2 CRC value high register"]
# [inline (always)]
pub const fn crc_regh2 (& self) -> & CrcRegh2 { & self . crc_regh2 } # [doc = "0xb0 - Channel 2 PSA sector signature low regis-ter"]
# [inline (always)]
pub const fn psa_secsigregl2 (& self) -> & PsaSecsigregl2 { & self . psa_secsigregl2 } # [doc = "0xb4 - Channel 2 PSA sector signature high regis-ter"]
# [inline (always)]
pub const fn psa_secsigregh2 (& self) -> & PsaSecsigregh2 { & self . psa_secsigregh2 } # [doc = "0xb8 - Channel 2 un-compressed raw data low register"]
# [inline (always)]
pub const fn raw_dataregl2 (& self) -> & RawDataregl2 { & self . raw_dataregl2 } # [doc = "0xbc - Channel 2 un-compressed raw data high Register"]
# [inline (always)]
pub const fn raw_dataregh2 (& self) -> & RawDataregh2 { & self . raw_dataregh2 } # [doc = "0xc0 - Channel 3 preload register for the pattern count"]
# [inline (always)]
pub const fn crc_pcount_reg3 (& self) -> & CrcPcountReg3 { & self . crc_pcount_reg3 } # [doc = "0xc4 - Channel 3 preload register for the sector count"]
# [inline (always)]
pub const fn crc_scount_reg3 (& self) -> & CrcScountReg3 { & self . crc_scount_reg3 } # [doc = "0xc8 - Channel 3 current sector register contains the sector number which causes CRC fail-ure"]
# [inline (always)]
pub const fn crc_cursec_reg3 (& self) -> & CrcCursecReg3 { & self . crc_cursec_reg3 } # [doc = "0xcc - Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
# [inline (always)]
pub const fn crc_wdtopld3 (& self) -> & CrcWdtopld3 { & self . crc_wdtopld3 } # [doc = "0xd0 - Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"]
# [inline (always)]
pub const fn crc_bctopld3 (& self) -> & CrcBctopld3 { & self . crc_bctopld3 } # [doc = "0xe0 - Channel 3 PSA signature low register"]
# [inline (always)]
pub const fn psa_sigregl3 (& self) -> & PsaSigregl3 { & self . psa_sigregl3 } # [doc = "0xe4 - Channel 3 PSA signature high register"]
# [inline (always)]
pub const fn psa_sigregh3 (& self) -> & PsaSigregh3 { & self . psa_sigregh3 } # [doc = "0xe8 - Channel 3 CRC value low register"]
# [inline (always)]
pub const fn crc_regl3 (& self) -> & CrcRegl3 { & self . crc_regl3 } # [doc = "0xec - Channel 3 CRC value high register"]
# [inline (always)]
pub const fn crc_regh3 (& self) -> & CrcRegh3 { & self . crc_regh3 } # [doc = "0xf0 - Channel 3 PSA sector signature low regis-ter"]
# [inline (always)]
pub const fn psa_secsigregl3 (& self) -> & PsaSecsigregl3 { & self . psa_secsigregl3 } # [doc = "0xf4 - Channel 3 PSA sector signature high regis-ter"]
# [inline (always)]
pub const fn psa_secsigregh3 (& self) -> & PsaSecsigregh3 { & self . psa_secsigregh3 } # [doc = "0xf8 - Channel 3 un-compressed raw data low register"]
# [inline (always)]
pub const fn raw_dataregl3 (& self) -> & RawDataregl3 { & self . raw_dataregl3 } # [doc = "0xfc - Channel 3 un-compressed raw data high Register"]
# [inline (always)]
pub const fn raw_dataregh3 (& self) -> & RawDataregh3 { & self . raw_dataregh3 } # [doc = "0x100 - Channel 4 preload register for the pattern count"]
# [inline (always)]
pub const fn crc_pcount_reg4 (& self) -> & CrcPcountReg4 { & self . crc_pcount_reg4 } # [doc = "0x104 - Channel 4 preload register for the sector count"]
# [inline (always)]
pub const fn crc_scount_reg4 (& self) -> & CrcScountReg4 { & self . crc_scount_reg4 } # [doc = "0x108 - Channel 4 current sector register contains the sector number which causes CRC fail-ure"]
# [inline (always)]
pub const fn crc_cursec_reg4 (& self) -> & CrcCursecReg4 { & self . crc_cursec_reg4 } # [doc = "0x10c - Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
# [inline (always)]
pub const fn crc_wdtopld4 (& self) -> & CrcWdtopld4 { & self . crc_wdtopld4 } # [doc = "0x110 - Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"]
# [inline (always)]
pub const fn crc_bctopld4 (& self) -> & CrcBctopld4 { & self . crc_bctopld4 } # [doc = "0x120 - Channel 4 PSA signature low register"]
# [inline (always)]
pub const fn psa_sigregl4 (& self) -> & PsaSigregl4 { & self . psa_sigregl4 } # [doc = "0x124 - Channel 4 PSA signature high register"]
# [inline (always)]
pub const fn psa_sigregh4 (& self) -> & PsaSigregh4 { & self . psa_sigregh4 } # [doc = "0x128 - Channel 4 CRC value low register"]
# [inline (always)]
pub const fn crc_regl4 (& self) -> & CrcRegl4 { & self . crc_regl4 } # [doc = "0x12c - Channel 4 CRC value high register"]
# [inline (always)]
pub const fn crc_regh4 (& self) -> & CrcRegh4 { & self . crc_regh4 } # [doc = "0x130 - Channel 4 PSA sector signature low regis-ter"]
# [inline (always)]
pub const fn psa_secsigregl4 (& self) -> & PsaSecsigregl4 { & self . psa_secsigregl4 } # [doc = "0x134 - Channel 4 PSA sector signature high regis-ter"]
# [inline (always)]
pub const fn psa_secsigregh4 (& self) -> & PsaSecsigregh4 { & self . psa_secsigregh4 } # [doc = "0x138 - Channel 4 un-compressed raw data low register"]
# [inline (always)]
pub const fn raw_dataregl4 (& self) -> & RawDataregl4 { & self . raw_dataregl4 } # [doc = "0x13c - Channel 4 un-compressed raw data high Register"]
# [inline (always)]
pub const fn raw_dataregh4 (& self) -> & RawDataregh4 { & self . raw_dataregh4 } # [doc = "0x140 - Disables either or all tracing of data buses"]
# [inline (always)]
pub const fn mcrc_bus_sel (& self) -> & McrcBusSel { & self . mcrc_bus_sel } # [doc = "0x144 - 0x144 to 0x1FF is reserved area."]
# [inline (always)]
pub const fn mcrc_reserved (& self) -> & McrcReserved { & self . mcrc_reserved } } # [doc = "CRC_CTRL0 (rw) register accessor: Contains sw reset control bit to reset PSA\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_ctrl0`]
module"]
# [doc (alias = "CRC_CTRL0")]
pub type CrcCtrl0 = crate :: Reg < crc_ctrl0 :: CrcCtrl0Spec > ; # [doc = "Contains sw reset control bit to reset PSA"]
pub mod crc_ctrl0 { # [doc = "Register `CRC_CTRL0` reader"]
pub type R = crate :: R < CrcCtrl0Spec > ; # [doc = "Register `CRC_CTRL0` writer"]
pub type W = crate :: W < CrcCtrl0Spec > ; # [doc = "Field `CH1_PSA_SWREST` reader - 0:0\\]
Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
pub type Ch1PsaSwrestR = crate :: BitReader ; # [doc = "Field `CH1_PSA_SWREST` writer - 0:0\\]
Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
pub type Ch1PsaSwrestW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_DW_SEL` reader - 2:1\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
pub type Ch1DwSelR = crate :: FieldReader ; # [doc = "Field `CH1_DW_SEL` writer - 2:1\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
pub type Ch1DwSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CH1_CRC_SEL` reader - 4:3\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
pub type Ch1CrcSelR = crate :: FieldReader ; # [doc = "Field `CH1_CRC_SEL` writer - 4:3\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
pub type Ch1CrcSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CH1_BIT_SWAP` reader - 5:5\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
pub type Ch1BitSwapR = crate :: BitReader ; # [doc = "Field `CH1_BIT_SWAP` writer - 5:5\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
pub type Ch1BitSwapW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_BYTE_SWAP` reader - 6:6\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
pub type Ch1ByteSwapR = crate :: BitReader ; # [doc = "Field `CH1_BYTE_SWAP` writer - 6:6\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
pub type Ch1ByteSwapW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_CRC_SEL2` reader - 7:7\\]
Refer \"CH1_DW_SEL\" field description"]
pub type Ch1CrcSel2R = crate :: BitReader ; # [doc = "Field `CH1_CRC_SEL2` writer - 7:7\\]
Refer \"CH1_DW_SEL\" field description"]
pub type Ch1CrcSel2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_PSA_SWREST` reader - 8:8\\]
Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
pub type Ch2PsaSwrestR = crate :: BitReader ; # [doc = "Field `CH2_PSA_SWREST` writer - 8:8\\]
Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
pub type Ch2PsaSwrestW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_DW_SEL` reader - 10:9\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
pub type Ch2DwSelR = crate :: FieldReader ; # [doc = "Field `CH2_DW_SEL` writer - 10:9\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
pub type Ch2DwSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CH2_CRC_SEL` reader - 12:11\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
pub type Ch2CrcSelR = crate :: FieldReader ; # [doc = "Field `CH2_CRC_SEL` writer - 12:11\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
pub type Ch2CrcSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CH2_BIT_SWAP` reader - 13:13\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
pub type Ch2BitSwapR = crate :: BitReader ; # [doc = "Field `CH2_BIT_SWAP` writer - 13:13\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
pub type Ch2BitSwapW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_BYTE_SWAP` reader - 14:14\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
pub type Ch2ByteSwapR = crate :: BitReader ; # [doc = "Field `CH2_BYTE_SWAP` writer - 14:14\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
pub type Ch2ByteSwapW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_CRC_SEL2` reader - 15:15\\]
Refer \"CH2_DW_SEL\" field description"]
pub type Ch2CrcSel2R = crate :: BitReader ; # [doc = "Field `CH2_CRC_SEL2` writer - 15:15\\]
Refer \"CH2_DW_SEL\" field description"]
pub type Ch2CrcSel2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 16:16\\]
Reserved"]
pub type Nu1R = crate :: BitReader ; # [doc = "Field `NU1` writer - 16:16\\]
Reserved"]
pub type Nu1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 18:17\\]
Reserved"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 18:17\\]
Reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU3` reader - 20:19\\]
Reserved"]
pub type Nu3R = crate :: FieldReader ; # [doc = "Field `NU3` writer - 20:19\\]
Reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU4` reader - 21:21\\]
Reserved"]
pub type Nu4R = crate :: BitReader ; # [doc = "Field `NU4` writer - 21:21\\]
Reserved"]
pub type Nu4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU5` reader - 22:22\\]
Reserved"]
pub type Nu5R = crate :: BitReader ; # [doc = "Field `NU5` writer - 22:22\\]
Reserved"]
pub type Nu5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU6` reader - 23:23\\]
Reserved"]
pub type Nu6R = crate :: BitReader ; # [doc = "Field `NU6` writer - 23:23\\]
Reserved"]
pub type Nu6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU7` reader - 24:24\\]
Reserved"]
pub type Nu7R = crate :: BitReader ; # [doc = "Field `NU7` writer - 24:24\\]
Reserved"]
pub type Nu7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU8` reader - 26:25\\]
Reserved"]
pub type Nu8R = crate :: FieldReader ; # [doc = "Field `NU8` writer - 26:25\\]
Reserved"]
pub type Nu8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU9` reader - 28:27\\]
Reserved"]
pub type Nu9R = crate :: FieldReader ; # [doc = "Field `NU9` writer - 28:27\\]
Reserved"]
pub type Nu9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NU10` reader - 29:29\\]
Reserved"]
pub type Nu10R = crate :: BitReader ; # [doc = "Field `NU10` writer - 29:29\\]
Reserved"]
pub type Nu10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU11` reader - 30:30\\]
Reserved"]
pub type Nu11R = crate :: BitReader ; # [doc = "Field `NU11` writer - 30:30\\]
Reserved"]
pub type Nu11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU12` reader - 31:31\\]
Reserved"]
pub type Nu12R = crate :: BitReader ; # [doc = "Field `NU12` writer - 31:31\\]
Reserved"]
pub type Nu12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
# [inline (always)]
pub fn ch1_psa_swrest (& self) -> Ch1PsaSwrestR { Ch1PsaSwrestR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:2 - 2:1\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
# [inline (always)]
pub fn ch1_dw_sel (& self) -> Ch1DwSelR { Ch1DwSelR :: new (((self . bits >> 1) & 3) as u8) } # [doc = "Bits 3:4 - 4:3\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
# [inline (always)]
pub fn ch1_crc_sel (& self) -> Ch1CrcSelR { Ch1CrcSelR :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bit 5 - 5:5\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
# [inline (always)]
pub fn ch1_bit_swap (& self) -> Ch1BitSwapR { Ch1BitSwapR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
# [inline (always)]
pub fn ch1_byte_swap (& self) -> Ch1ByteSwapR { Ch1ByteSwapR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Refer \"CH1_DW_SEL\" field description"]
# [inline (always)]
pub fn ch1_crc_sel2 (& self) -> Ch1CrcSel2R { Ch1CrcSel2R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
# [inline (always)]
pub fn ch2_psa_swrest (& self) -> Ch2PsaSwrestR { Ch2PsaSwrestR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - 10:9\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
# [inline (always)]
pub fn ch2_dw_sel (& self) -> Ch2DwSelR { Ch2DwSelR :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 11:12 - 12:11\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
# [inline (always)]
pub fn ch2_crc_sel (& self) -> Ch2CrcSelR { Ch2CrcSelR :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bit 13 - 13:13\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
# [inline (always)]
pub fn ch2_bit_swap (& self) -> Ch2BitSwapR { Ch2BitSwapR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
# [inline (always)]
pub fn ch2_byte_swap (& self) -> Ch2ByteSwapR { Ch2ByteSwapR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Refer \"CH2_DW_SEL\" field description"]
# [inline (always)]
pub fn ch2_crc_sel2 (& self) -> Ch2CrcSel2R { Ch2CrcSel2R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:18 - 18:17\\]
Reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 17) & 3) as u8) } # [doc = "Bits 19:20 - 20:19\\]
Reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 19) & 3) as u8) } # [doc = "Bit 21 - 21:21\\]
Reserved"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Reserved"]
# [inline (always)]
pub fn nu5 (& self) -> Nu5R { Nu5R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
pub fn nu6 (& self) -> Nu6R { Nu6R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Reserved"]
# [inline (always)]
pub fn nu7 (& self) -> Nu7R { Nu7R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Reserved"]
# [inline (always)]
pub fn nu8 (& self) -> Nu8R { Nu8R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bits 27:28 - 28:27\\]
Reserved"]
# [inline (always)]
pub fn nu9 (& self) -> Nu9R { Nu9R :: new (((self . bits >> 27) & 3) as u8) } # [doc = "Bit 29 - 29:29\\]
Reserved"]
# [inline (always)]
pub fn nu10 (& self) -> Nu10R { Nu10R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Reserved"]
# [inline (always)]
pub fn nu11 (& self) -> Nu11R { Nu11R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Reserved"]
# [inline (always)]
pub fn nu12 (& self) -> Nu12R { Nu12R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
# [inline (always)]
# [must_use]
pub fn ch1_psa_swrest (& mut self) -> Ch1PsaSwrestW < CrcCtrl0Spec > { Ch1PsaSwrestW :: new (self , 0) } # [doc = "Bits 1:2 - 2:1\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
# [inline (always)]
# [must_use]
pub fn ch1_dw_sel (& mut self) -> Ch1DwSelW < CrcCtrl0Spec > { Ch1DwSelW :: new (self , 1) } # [doc = "Bits 3:4 - 4:3\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
# [inline (always)]
# [must_use]
pub fn ch1_crc_sel (& mut self) -> Ch1CrcSelW < CrcCtrl0Spec > { Ch1CrcSelW :: new (self , 3) } # [doc = "Bit 5 - 5:5\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
# [inline (always)]
# [must_use]
pub fn ch1_bit_swap (& mut self) -> Ch1BitSwapW < CrcCtrl0Spec > { Ch1BitSwapW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
# [inline (always)]
# [must_use]
pub fn ch1_byte_swap (& mut self) -> Ch1ByteSwapW < CrcCtrl0Spec > { Ch1ByteSwapW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Refer \"CH1_DW_SEL\" field description"]
# [inline (always)]
# [must_use]
pub fn ch1_crc_sel2 (& mut self) -> Ch1CrcSel2W < CrcCtrl0Spec > { Ch1CrcSel2W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ΓÇÿ0ΓÇÖ. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset"]
# [inline (always)]
# [must_use]
pub fn ch2_psa_swrest (& mut self) -> Ch2PsaSwrestW < CrcCtrl0Spec > { Ch2PsaSwrestW :: new (self , 8) } # [doc = "Bits 9:10 - 10:9\\]
CRC Data Size select. 000 ΓÇô Not Supported 001 - 16 bit Data Size 010 ΓÇô 32 Bit Data Size"]
# [inline (always)]
# [must_use]
pub fn ch2_dw_sel (& mut self) -> Ch2DwSelW < CrcCtrl0Spec > { Ch2DwSelW :: new (self , 9) } # [doc = "Bits 11:12 - 12:11\\]
CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL\\[1:0\\]} 000 ΓÇô CRC-64 001 - CRC-16 010 ΓÇô CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4"]
# [inline (always)]
# [must_use]
pub fn ch2_crc_sel (& mut self) -> Ch2CrcSelW < CrcCtrl0Spec > { Ch2CrcSelW :: new (self , 11) } # [doc = "Bit 13 - 13:13\\]
msb/lsb SWAPPING 0 ΓÇô msb (most significant bit First) 1 ΓÇô lsb (least significant bit First)"]
# [inline (always)]
# [must_use]
pub fn ch2_bit_swap (& mut self) -> Ch2BitSwapW < CrcCtrl0Spec > { Ch2BitSwapW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
BYTE SWAP Enable across Data Size 0 ΓÇô Byte Swap Disabled 1 ΓÇô Byte Swap enabled."]
# [inline (always)]
# [must_use]
pub fn ch2_byte_swap (& mut self) -> Ch2ByteSwapW < CrcCtrl0Spec > { Ch2ByteSwapW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Refer \"CH2_DW_SEL\" field description"]
# [inline (always)]
# [must_use]
pub fn ch2_crc_sel2 (& mut self) -> Ch2CrcSel2W < CrcCtrl0Spec > { Ch2CrcSel2W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < CrcCtrl0Spec > { Nu1W :: new (self , 16) } # [doc = "Bits 17:18 - 18:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < CrcCtrl0Spec > { Nu2W :: new (self , 17) } # [doc = "Bits 19:20 - 20:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < CrcCtrl0Spec > { Nu3W :: new (self , 19) } # [doc = "Bit 21 - 21:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < CrcCtrl0Spec > { Nu4W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu5 (& mut self) -> Nu5W < CrcCtrl0Spec > { Nu5W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu6 (& mut self) -> Nu6W < CrcCtrl0Spec > { Nu6W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu7 (& mut self) -> Nu7W < CrcCtrl0Spec > { Nu7W :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu8 (& mut self) -> Nu8W < CrcCtrl0Spec > { Nu8W :: new (self , 25) } # [doc = "Bits 27:28 - 28:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu9 (& mut self) -> Nu9W < CrcCtrl0Spec > { Nu9W :: new (self , 27) } # [doc = "Bit 29 - 29:29\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu10 (& mut self) -> Nu10W < CrcCtrl0Spec > { Nu10W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu11 (& mut self) -> Nu11W < CrcCtrl0Spec > { Nu11W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu12 (& mut self) -> Nu12W < CrcCtrl0Spec > { Nu12W :: new (self , 31) } } # [doc = "Contains sw reset control bit to reset PSA\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCtrl0Spec ; impl crate :: RegisterSpec for CrcCtrl0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_ctrl0::R`](R) reader structure"]
impl crate :: Readable for CrcCtrl0Spec { } # [doc = "`write(|w| ..)` method takes [`crc_ctrl0::W`](W) writer structure"]
impl crate :: Writable for CrcCtrl0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CTRL0 to value 0"]
impl crate :: Resettable for CrcCtrl0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_CTRL1 (rw) register accessor: Contains power down control bit\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_ctrl1`]
module"]
# [doc (alias = "CRC_CTRL1")]
pub type CrcCtrl1 = crate :: Reg < crc_ctrl1 :: CrcCtrl1Spec > ; # [doc = "Contains power down control bit"]
pub mod crc_ctrl1 { # [doc = "Register `CRC_CTRL1` reader"]
pub type R = crate :: R < CrcCtrl1Spec > ; # [doc = "Register `CRC_CTRL1` writer"]
pub type W = crate :: W < CrcCtrl1Spec > ; # [doc = "Field `PWDN` reader - 0:0\\]
Power Down. When set, MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode"]
pub type PwdnR = crate :: BitReader ; # [doc = "Field `PWDN` writer - 0:0\\]
Power Down. When set, MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode"]
pub type PwdnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:1\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved1` writer - 31:1\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Power Down. When set, MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode"]
# [inline (always)]
pub fn pwdn (& self) -> PwdnR { PwdnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Power Down. When set, MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode"]
# [inline (always)]
# [must_use]
pub fn pwdn (& mut self) -> PwdnW < CrcCtrl1Spec > { PwdnW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcCtrl1Spec > { Reserved1W :: new (self , 1) } } # [doc = "Contains power down control bit\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCtrl1Spec ; impl crate :: RegisterSpec for CrcCtrl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_ctrl1::R`](R) reader structure"]
impl crate :: Readable for CrcCtrl1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_ctrl1::W`](W) writer structure"]
impl crate :: Writable for CrcCtrl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CTRL1 to value 0"]
impl crate :: Resettable for CrcCtrl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_CTRL2 (rw) register accessor: Contains channel mode, data trace enable control bits\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_ctrl2`]
module"]
# [doc (alias = "CRC_CTRL2")]
pub type CrcCtrl2 = crate :: Reg < crc_ctrl2 :: CrcCtrl2Spec > ; # [doc = "Contains channel mode, data trace enable control bits"]
pub mod crc_ctrl2 { # [doc = "Register `CRC_CTRL2` reader"]
pub type R = crate :: R < CrcCtrl2Spec > ; # [doc = "Register `CRC_CTRL2` writer"]
pub type W = crate :: W < CrcCtrl2Spec > ; # [doc = "Field `CH1_MODE` reader - 1:0\\]
Channel 1 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
pub type Ch1ModeR = crate :: FieldReader ; # [doc = "Field `CH1_MODE` writer - 1:0\\]
Channel 1 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
pub type Ch1ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 3:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 3:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CH1_TRACEEN` reader - 4:4\\]
Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel snoops on the CPU VBUSM, ITCM, DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature Register does not compress any read data on these buses. 0 = Data Trace disable 1 = Data Trace enable"]
pub type Ch1TraceenR = crate :: BitReader ; # [doc = "Field `CH1_TRACEEN` writer - 4:4\\]
Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel snoops on the CPU VBUSM, ITCM, DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature Register does not compress any read data on these buses. 0 = Data Trace disable 1 = Data Trace enable"]
pub type Ch1TraceenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 7:5\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 7:5\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CH2_MODE` reader - 9:8\\]
Channel 2 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
pub type Ch2ModeR = crate :: FieldReader ; # [doc = "Field `CH2_MODE` writer - 9:8\\]
Channel 2 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
pub type Ch2ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved3` reader - 15:10\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 15:10\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU13` reader - 17:16\\]
Reserved"]
pub type Nu13R = crate :: FieldReader ; # [doc = "Field `NU13` writer - 17:16\\]
Reserved"]
pub type Nu13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved4` reader - 23:18\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 23:18\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU14` reader - 25:24\\]
Reserved"]
pub type Nu14R = crate :: FieldReader ; # [doc = "Field `NU14` writer - 25:24\\]
Reserved"]
pub type Nu14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved5` reader - 31:26\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `Reserved5` writer - 31:26\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Channel 1 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
# [inline (always)]
pub fn ch1_mode (& self) -> Ch1ModeR { Ch1ModeR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bit 4 - 4:4\\]
Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel snoops on the CPU VBUSM, ITCM, DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature Register does not compress any read data on these buses. 0 = Data Trace disable 1 = Data Trace enable"]
# [inline (always)]
pub fn ch1_traceen (& self) -> Ch1TraceenR { Ch1TraceenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:7 - 7:5\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Channel 2 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
# [inline (always)]
pub fn ch2_mode (& self) -> Ch2ModeR { Ch2ModeR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn nu13 (& self) -> Nu13R { Nu13R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 18) & 0x3f) as u8) } # [doc = "Bits 24:25 - 25:24\\]
Reserved"]
# [inline (always)]
pub fn nu14 (& self) -> Nu14R { Nu14R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Channel 1 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
# [inline (always)]
# [must_use]
pub fn ch1_mode (& mut self) -> Ch1ModeW < CrcCtrl2Spec > { Ch1ModeW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcCtrl2Spec > { Reserved1W :: new (self , 2) } # [doc = "Bit 4 - 4:4\\]
Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel snoops on the CPU VBUSM, ITCM, DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature Register does not compress any read data on these buses. 0 = Data Trace disable 1 = Data Trace enable"]
# [inline (always)]
# [must_use]
pub fn ch1_traceen (& mut self) -> Ch1TraceenW < CrcCtrl2Spec > { Ch1TraceenW :: new (self , 4) } # [doc = "Bits 5:7 - 7:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < CrcCtrl2Spec > { Reserved2W :: new (self , 5) } # [doc = "Bits 8:9 - 9:8\\]
Channel 2 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode"]
# [inline (always)]
# [must_use]
pub fn ch2_mode (& mut self) -> Ch2ModeW < CrcCtrl2Spec > { Ch2ModeW :: new (self , 8) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < CrcCtrl2Spec > { Reserved3W :: new (self , 10) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu13 (& mut self) -> Nu13W < CrcCtrl2Spec > { Nu13W :: new (self , 16) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < CrcCtrl2Spec > { Reserved4W :: new (self , 18) } # [doc = "Bits 24:25 - 25:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu14 (& mut self) -> Nu14W < CrcCtrl2Spec > { Nu14W :: new (self , 24) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < CrcCtrl2Spec > { Reserved5W :: new (self , 26) } } # [doc = "Contains channel mode, data trace enable control bits\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCtrl2Spec ; impl crate :: RegisterSpec for CrcCtrl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_ctrl2::R`](R) reader structure"]
impl crate :: Readable for CrcCtrl2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_ctrl2::W`](W) writer structure"]
impl crate :: Writable for CrcCtrl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CTRL2 to value 0"]
impl crate :: Resettable for CrcCtrl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_INTS (rw) register accessor: Write one to a bit to enable a interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_ints`]
module"]
# [doc (alias = "CRC_INTS")]
pub type CrcInts = crate :: Reg < crc_ints :: CrcIntsSpec > ; # [doc = "Write one to a bit to enable a interrupt"]
pub mod crc_ints { # [doc = "Register `CRC_INTS` reader"]
pub type R = crate :: R < CrcIntsSpec > ; # [doc = "Register `CRC_INTS` writer"]
pub type W = crate :: W < CrcIntsSpec > ; # [doc = "Field `Reserved1` reader - 0:0\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 0:0\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_CRCFAILENS` reader - 1:1\\]
Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
pub type Ch1CrcfailensR = crate :: BitReader ; # [doc = "Field `CH1_CRCFAILENS` writer - 1:1\\]
Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
pub type Ch1CrcfailensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_OVERENS` reader - 2:2\\]
Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
pub type Ch1OverensR = crate :: BitReader ; # [doc = "Field `CH1_OVERENS` writer - 2:2\\]
Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
pub type Ch1OverensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_UNDERENS` reader - 3:3\\]
Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
pub type Ch1UnderensR = crate :: BitReader ; # [doc = "Field `CH1_UNDERENS` writer - 3:3\\]
Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
pub type Ch1UnderensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_TIMEOUTENS` reader - 4:4\\]
Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
pub type Ch1TimeoutensR = crate :: BitReader ; # [doc = "Field `CH1_TIMEOUTENS` writer - 4:4\\]
Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
pub type Ch1TimeoutensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 8:5\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 8:5\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CH2_CRCFAILENS` reader - 9:9\\]
Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
pub type Ch2CrcfailensR = crate :: BitReader ; # [doc = "Field `CH2_CRCFAILENS` writer - 9:9\\]
Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
pub type Ch2CrcfailensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_OVERENS` reader - 10:10\\]
Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
pub type Ch2OverensR = crate :: BitReader ; # [doc = "Field `CH2_OVERENS` writer - 10:10\\]
Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
pub type Ch2OverensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_UNDERENS` reader - 11:11\\]
Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
pub type Ch2UnderensR = crate :: BitReader ; # [doc = "Field `CH2_UNDERENS` writer - 11:11\\]
Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
pub type Ch2UnderensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_TIMEOUTENS` reader - 12:12\\]
Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
pub type Ch2TimeoutensR = crate :: BitReader ; # [doc = "Field `CH2_TIMEOUTENS` writer - 12:12\\]
Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
pub type Ch2TimeoutensW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 16:13\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 16:13\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU15` reader - 17:17\\]
Reserved"]
pub type Nu15R = crate :: BitReader ; # [doc = "Field `NU15` writer - 17:17\\]
Reserved"]
pub type Nu15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU16` reader - 18:18\\]
Reserved"]
pub type Nu16R = crate :: BitReader ; # [doc = "Field `NU16` writer - 18:18\\]
Reserved"]
pub type Nu16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU17` reader - 19:19\\]
Reserved"]
pub type Nu17R = crate :: BitReader ; # [doc = "Field `NU17` writer - 19:19\\]
Reserved"]
pub type Nu17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU18` reader - 20:20\\]
Reserved"]
pub type Nu18R = crate :: BitReader ; # [doc = "Field `NU18` writer - 20:20\\]
Reserved"]
pub type Nu18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 24:21\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 24:21\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU19` reader - 25:25\\]
Reserved"]
pub type Nu19R = crate :: BitReader ; # [doc = "Field `NU19` writer - 25:25\\]
Reserved"]
pub type Nu19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU20` reader - 26:26\\]
Reserved"]
pub type Nu20R = crate :: BitReader ; # [doc = "Field `NU20` writer - 26:26\\]
Reserved"]
pub type Nu20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU21` reader - 27:27\\]
Reserved"]
pub type Nu21R = crate :: BitReader ; # [doc = "Field `NU21` writer - 27:27\\]
Reserved"]
pub type Nu21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU22` reader - 28:28\\]
Reserved"]
pub type Nu22R = crate :: BitReader ; # [doc = "Field `NU22` writer - 28:28\\]
Reserved"]
pub type Nu22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved5` reader - 31:29\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `Reserved5` writer - 31:29\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
# [inline (always)]
pub fn ch1_crcfailens (& self) -> Ch1CrcfailensR { Ch1CrcfailensR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
# [inline (always)]
pub fn ch1_overens (& self) -> Ch1OverensR { Ch1OverensR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
# [inline (always)]
pub fn ch1_underens (& self) -> Ch1UnderensR { Ch1UnderensR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
# [inline (always)]
pub fn ch1_timeoutens (& self) -> Ch1TimeoutensR { Ch1TimeoutensR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:8 - 8:5\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bit 9 - 9:9\\]
Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
# [inline (always)]
pub fn ch2_crcfailens (& self) -> Ch2CrcfailensR { Ch2CrcfailensR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
# [inline (always)]
pub fn ch2_overens (& self) -> Ch2OverensR { Ch2OverensR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
# [inline (always)]
pub fn ch2_underens (& self) -> Ch2UnderensR { Ch2UnderensR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
# [inline (always)]
pub fn ch2_timeoutens (& self) -> Ch2TimeoutensR { Ch2TimeoutensR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:16 - 16:13\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
pub fn nu15 (& self) -> Nu15R { Nu15R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
pub fn nu16 (& self) -> Nu16R { Nu16R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Reserved"]
# [inline (always)]
pub fn nu17 (& self) -> Nu17R { Nu17R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Reserved"]
# [inline (always)]
pub fn nu18 (& self) -> Nu18R { Nu18R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:24 - 24:21\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 21) & 0x0f) as u8) } # [doc = "Bit 25 - 25:25\\]
Reserved"]
# [inline (always)]
pub fn nu19 (& self) -> Nu19R { Nu19R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Reserved"]
# [inline (always)]
pub fn nu20 (& self) -> Nu20R { Nu20R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
pub fn nu21 (& self) -> Nu21R { Nu21R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Reserved"]
# [inline (always)]
pub fn nu22 (& self) -> Nu22R { Nu22R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcIntsSpec > { Reserved1W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch1_crcfailens (& mut self) -> Ch1CrcfailensW < CrcIntsSpec > { Ch1CrcfailensW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch1_overens (& mut self) -> Ch1OverensW < CrcIntsSpec > { Ch1OverensW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch1_underens (& mut self) -> Ch1UnderensW < CrcIntsSpec > { Ch1UnderensW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch1_timeoutens (& mut self) -> Ch1TimeoutensW < CrcIntsSpec > { Ch1TimeoutensW :: new (self , 4) } # [doc = "Bits 5:8 - 8:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < CrcIntsSpec > { Reserved2W :: new (self , 5) } # [doc = "Bit 9 - 9:9\\]
Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch2_crcfailens (& mut self) -> Ch2CrcfailensW < CrcIntsSpec > { Ch2CrcfailensW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch2_overens (& mut self) -> Ch2OverensW < CrcIntsSpec > { Ch2OverensW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch2_underens (& mut self) -> Ch2UnderensW < CrcIntsSpec > { Ch2UnderensW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ch2_timeoutens (& mut self) -> Ch2TimeoutensW < CrcIntsSpec > { Ch2TimeoutensW :: new (self , 12) } # [doc = "Bits 13:16 - 16:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < CrcIntsSpec > { Reserved3W :: new (self , 13) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu15 (& mut self) -> Nu15W < CrcIntsSpec > { Nu15W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu16 (& mut self) -> Nu16W < CrcIntsSpec > { Nu16W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu17 (& mut self) -> Nu17W < CrcIntsSpec > { Nu17W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu18 (& mut self) -> Nu18W < CrcIntsSpec > { Nu18W :: new (self , 20) } # [doc = "Bits 21:24 - 24:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < CrcIntsSpec > { Reserved4W :: new (self , 21) } # [doc = "Bit 25 - 25:25\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu19 (& mut self) -> Nu19W < CrcIntsSpec > { Nu19W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu20 (& mut self) -> Nu20W < CrcIntsSpec > { Nu20W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu21 (& mut self) -> Nu21W < CrcIntsSpec > { Nu21W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu22 (& mut self) -> Nu22W < CrcIntsSpec > { Nu22W :: new (self , 28) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < CrcIntsSpec > { Reserved5W :: new (self , 29) } } # [doc = "Write one to a bit to enable a interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcIntsSpec ; impl crate :: RegisterSpec for CrcIntsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_ints::R`](R) reader structure"]
impl crate :: Readable for CrcIntsSpec { } # [doc = "`write(|w| ..)` method takes [`crc_ints::W`](W) writer structure"]
impl crate :: Writable for CrcIntsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_INTS to value 0"]
impl crate :: Resettable for CrcIntsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_INTR (rw) register accessor: Write one to a bit to disable a interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_intr`]
module"]
# [doc (alias = "CRC_INTR")]
pub type CrcIntr = crate :: Reg < crc_intr :: CrcIntrSpec > ; # [doc = "Write one to a bit to disable a interrupt"]
pub mod crc_intr { # [doc = "Register `CRC_INTR` reader"]
pub type R = crate :: R < CrcIntrSpec > ; # [doc = "Register `CRC_INTR` writer"]
pub type W = crate :: W < CrcIntrSpec > ; # [doc = "Field `Reserved1` reader - 0:0\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 0:0\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_CRCFAILENR` reader - 1:1\\]
Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
pub type Ch1CrcfailenrR = crate :: BitReader ; # [doc = "Field `CH1_CRCFAILENR` writer - 1:1\\]
Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
pub type Ch1CrcfailenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_OVERENR` reader - 2:2\\]
Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
pub type Ch1OverenrR = crate :: BitReader ; # [doc = "Field `CH1_OVERENR` writer - 2:2\\]
Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
pub type Ch1OverenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_UNDERENR` reader - 3:3\\]
Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
pub type Ch1UnderenrR = crate :: BitReader ; # [doc = "Field `CH1_UNDERENR` writer - 3:3\\]
Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
pub type Ch1UnderenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_TIMEOUTENR` reader - 4:4\\]
Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
pub type Ch1TimeoutenrR = crate :: BitReader ; # [doc = "Field `CH1_TIMEOUTENR` writer - 4:4\\]
Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
pub type Ch1TimeoutenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 8:5\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 8:5\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CH2_CRCFAILENR` reader - 9:9\\]
Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
pub type Ch2CrcfailenrR = crate :: BitReader ; # [doc = "Field `CH2_CRCFAILENR` writer - 9:9\\]
Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
pub type Ch2CrcfailenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_OVERENR` reader - 10:10\\]
Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
pub type Ch2OverenrR = crate :: BitReader ; # [doc = "Field `CH2_OVERENR` writer - 10:10\\]
Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
pub type Ch2OverenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_UNDERENR` reader - 11:11\\]
Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
pub type Ch2UnderenrR = crate :: BitReader ; # [doc = "Field `CH2_UNDERENR` writer - 11:11\\]
Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
pub type Ch2UnderenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_TIMEOUTENR` reader - 12:12\\]
Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
pub type Ch2TimeoutenrR = crate :: BitReader ; # [doc = "Field `CH2_TIMEOUTENR` writer - 12:12\\]
Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
pub type Ch2TimeoutenrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 16:13\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 16:13\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU23` reader - 17:17\\]
Reserved"]
pub type Nu23R = crate :: BitReader ; # [doc = "Field `NU23` writer - 17:17\\]
Reserved"]
pub type Nu23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU24` reader - 18:18\\]
Reserved"]
pub type Nu24R = crate :: BitReader ; # [doc = "Field `NU24` writer - 18:18\\]
Reserved"]
pub type Nu24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU25` reader - 19:19\\]
Reserved"]
pub type Nu25R = crate :: BitReader ; # [doc = "Field `NU25` writer - 19:19\\]
Reserved"]
pub type Nu25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU26` reader - 20:20\\]
Reserved"]
pub type Nu26R = crate :: BitReader ; # [doc = "Field `NU26` writer - 20:20\\]
Reserved"]
pub type Nu26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 24:21\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 24:21\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU27` reader - 25:25\\]
Reserved"]
pub type Nu27R = crate :: BitReader ; # [doc = "Field `NU27` writer - 25:25\\]
Reserved"]
pub type Nu27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU28` reader - 26:26\\]
Reserved"]
pub type Nu28R = crate :: BitReader ; # [doc = "Field `NU28` writer - 26:26\\]
Reserved"]
pub type Nu28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU29` reader - 27:27\\]
Reserved"]
pub type Nu29R = crate :: BitReader ; # [doc = "Field `NU29` writer - 27:27\\]
Reserved"]
pub type Nu29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU30` reader - 28:28\\]
Reserved"]
pub type Nu30R = crate :: BitReader ; # [doc = "Field `NU30` writer - 28:28\\]
Reserved"]
pub type Nu30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved5` reader - 31:29\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `Reserved5` writer - 31:29\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
# [inline (always)]
pub fn ch1_crcfailenr (& self) -> Ch1CrcfailenrR { Ch1CrcfailenrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
# [inline (always)]
pub fn ch1_overenr (& self) -> Ch1OverenrR { Ch1OverenrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
# [inline (always)]
pub fn ch1_underenr (& self) -> Ch1UnderenrR { Ch1UnderenrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
# [inline (always)]
pub fn ch1_timeoutenr (& self) -> Ch1TimeoutenrR { Ch1TimeoutenrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:8 - 8:5\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bit 9 - 9:9\\]
Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
# [inline (always)]
pub fn ch2_crcfailenr (& self) -> Ch2CrcfailenrR { Ch2CrcfailenrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
# [inline (always)]
pub fn ch2_overenr (& self) -> Ch2OverenrR { Ch2OverenrR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
# [inline (always)]
pub fn ch2_underenr (& self) -> Ch2UnderenrR { Ch2UnderenrR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
# [inline (always)]
pub fn ch2_timeoutenr (& self) -> Ch2TimeoutenrR { Ch2TimeoutenrR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:16 - 16:13\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
pub fn nu23 (& self) -> Nu23R { Nu23R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
pub fn nu24 (& self) -> Nu24R { Nu24R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Reserved"]
# [inline (always)]
pub fn nu25 (& self) -> Nu25R { Nu25R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Reserved"]
# [inline (always)]
pub fn nu26 (& self) -> Nu26R { Nu26R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:24 - 24:21\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 21) & 0x0f) as u8) } # [doc = "Bit 25 - 25:25\\]
Reserved"]
# [inline (always)]
pub fn nu27 (& self) -> Nu27R { Nu27R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Reserved"]
# [inline (always)]
pub fn nu28 (& self) -> Nu28R { Nu28R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
pub fn nu29 (& self) -> Nu29R { Nu29R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Reserved"]
# [inline (always)]
pub fn nu30 (& self) -> Nu30R { Nu30R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcIntrSpec > { Reserved1W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch1_crcfailenr (& mut self) -> Ch1CrcfailenrW < CrcIntrSpec > { Ch1CrcfailenrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch1_overenr (& mut self) -> Ch1OverenrW < CrcIntrSpec > { Ch1OverenrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch1_underenr (& mut self) -> Ch1UnderenrW < CrcIntrSpec > { Ch1UnderenrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch1_timeoutenr (& mut self) -> Ch1TimeoutenrW < CrcIntrSpec > { Ch1TimeoutenrW :: new (self , 4) } # [doc = "Bits 5:8 - 8:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < CrcIntrSpec > { Reserved2W :: new (self , 5) } # [doc = "Bit 9 - 9:9\\]
Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch2_crcfailenr (& mut self) -> Ch2CrcfailenrW < CrcIntrSpec > { Ch2CrcfailenrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch2_overenr (& mut self) -> Ch2OverenrW < CrcIntrSpec > { Ch2OverenrW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch2_underenr (& mut self) -> Ch2UnderenrW < CrcIntrSpec > { Ch2UnderenrW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable"]
# [inline (always)]
# [must_use]
pub fn ch2_timeoutenr (& mut self) -> Ch2TimeoutenrW < CrcIntrSpec > { Ch2TimeoutenrW :: new (self , 12) } # [doc = "Bits 13:16 - 16:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < CrcIntrSpec > { Reserved3W :: new (self , 13) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu23 (& mut self) -> Nu23W < CrcIntrSpec > { Nu23W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu24 (& mut self) -> Nu24W < CrcIntrSpec > { Nu24W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu25 (& mut self) -> Nu25W < CrcIntrSpec > { Nu25W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu26 (& mut self) -> Nu26W < CrcIntrSpec > { Nu26W :: new (self , 20) } # [doc = "Bits 21:24 - 24:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < CrcIntrSpec > { Reserved4W :: new (self , 21) } # [doc = "Bit 25 - 25:25\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu27 (& mut self) -> Nu27W < CrcIntrSpec > { Nu27W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu28 (& mut self) -> Nu28W < CrcIntrSpec > { Nu28W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu29 (& mut self) -> Nu29W < CrcIntrSpec > { Nu29W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu30 (& mut self) -> Nu30W < CrcIntrSpec > { Nu30W :: new (self , 28) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < CrcIntrSpec > { Reserved5W :: new (self , 29) } } # [doc = "Write one to a bit to disable a interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcIntrSpec ; impl crate :: RegisterSpec for CrcIntrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_intr::R`](R) reader structure"]
impl crate :: Readable for CrcIntrSpec { } # [doc = "`write(|w| ..)` method takes [`crc_intr::W`](W) writer structure"]
impl crate :: Writable for CrcIntrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_INTR to value 0"]
impl crate :: Resettable for CrcIntrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_STATUS_REG (rw) register accessor: Contains interrupt flags for different types of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_status_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_status_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_status_reg`]
module"]
# [doc (alias = "CRC_STATUS_REG")]
pub type CrcStatusReg = crate :: Reg < crc_status_reg :: CrcStatusRegSpec > ; # [doc = "Contains interrupt flags for different types of interrupt"]
pub mod crc_status_reg { # [doc = "Register `CRC_STATUS_REG` reader"]
pub type R = crate :: R < CrcStatusRegSpec > ; # [doc = "Register `CRC_STATUS_REG` writer"]
pub type W = crate :: W < CrcStatusRegSpec > ; # [doc = "Field `Reserved1` reader - 0:0\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 0:0\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_CRCFAIL` reader - 1:1\\]
Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
pub type Ch1CrcfailR = crate :: BitReader ; # [doc = "Field `CH1_CRCFAIL` writer - 1:1\\]
Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
pub type Ch1CrcfailW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_OVER` reader - 2:2\\]
Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
pub type Ch1OverR = crate :: BitReader ; # [doc = "Field `CH1_OVER` writer - 2:2\\]
Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
pub type Ch1OverW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_UNDER` reader - 3:3\\]
Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
pub type Ch1UnderR = crate :: BitReader ; # [doc = "Field `CH1_UNDER` writer - 3:3\\]
Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
pub type Ch1UnderW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH1_TIMEOUT` reader - 4:4\\]
Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
pub type Ch1TimeoutR = crate :: BitReader ; # [doc = "Field `CH1_TIMEOUT` writer - 4:4\\]
Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
pub type Ch1TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 8:5\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 8:5\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CH2_CRCFAIL` reader - 9:9\\]
Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
pub type Ch2CrcfailR = crate :: BitReader ; # [doc = "Field `CH2_CRCFAIL` writer - 9:9\\]
Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
pub type Ch2CrcfailW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_OVER` reader - 10:10\\]
Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
pub type Ch2OverR = crate :: BitReader ; # [doc = "Field `CH2_OVER` writer - 10:10\\]
Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
pub type Ch2OverW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_UNDER` reader - 11:11\\]
Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
pub type Ch2UnderR = crate :: BitReader ; # [doc = "Field `CH2_UNDER` writer - 11:11\\]
Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
pub type Ch2UnderW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CH2_TIMEOUT` reader - 12:12\\]
Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
pub type Ch2TimeoutR = crate :: BitReader ; # [doc = "Field `CH2_TIMEOUT` writer - 12:12\\]
Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
pub type Ch2TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 16:13\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 16:13\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU31` reader - 17:17\\]
Reserved"]
pub type Nu31R = crate :: BitReader ; # [doc = "Field `NU31` writer - 17:17\\]
Reserved"]
pub type Nu31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU32` reader - 18:18\\]
Reserved"]
pub type Nu32R = crate :: BitReader ; # [doc = "Field `NU32` writer - 18:18\\]
Reserved"]
pub type Nu32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU33` reader - 19:19\\]
Reserved"]
pub type Nu33R = crate :: BitReader ; # [doc = "Field `NU33` writer - 19:19\\]
Reserved"]
pub type Nu33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU34` reader - 20:20\\]
Reserved"]
pub type Nu34R = crate :: BitReader ; # [doc = "Field `NU34` writer - 20:20\\]
Reserved"]
pub type Nu34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 24:21\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 24:21\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU35` reader - 25:25\\]
Reserved"]
pub type Nu35R = crate :: BitReader ; # [doc = "Field `NU35` writer - 25:25\\]
Reserved"]
pub type Nu35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU36` reader - 26:26\\]
Reserved"]
pub type Nu36R = crate :: BitReader ; # [doc = "Field `NU36` writer - 26:26\\]
Reserved"]
pub type Nu36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU37` reader - 27:27\\]
Reserved"]
pub type Nu37R = crate :: BitReader ; # [doc = "Field `NU37` writer - 27:27\\]
Reserved"]
pub type Nu37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU38` reader - 28:28\\]
Reserved"]
pub type Nu38R = crate :: BitReader ; # [doc = "Field `NU38` writer - 28:28\\]
Reserved"]
pub type Nu38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved5` reader - 31:29\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `Reserved5` writer - 31:29\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
# [inline (always)]
pub fn ch1_crcfail (& self) -> Ch1CrcfailR { Ch1CrcfailR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
# [inline (always)]
pub fn ch1_over (& self) -> Ch1OverR { Ch1OverR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
# [inline (always)]
pub fn ch1_under (& self) -> Ch1UnderR { Ch1UnderR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
# [inline (always)]
pub fn ch1_timeout (& self) -> Ch1TimeoutR { Ch1TimeoutR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:8 - 8:5\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 5) & 0x0f) as u8) } # [doc = "Bit 9 - 9:9\\]
Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
# [inline (always)]
pub fn ch2_crcfail (& self) -> Ch2CrcfailR { Ch2CrcfailR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
# [inline (always)]
pub fn ch2_over (& self) -> Ch2OverR { Ch2OverR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
# [inline (always)]
pub fn ch2_under (& self) -> Ch2UnderR { Ch2UnderR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
# [inline (always)]
pub fn ch2_timeout (& self) -> Ch2TimeoutR { Ch2TimeoutR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:16 - 16:13\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
pub fn nu31 (& self) -> Nu31R { Nu31R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
pub fn nu32 (& self) -> Nu32R { Nu32R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Reserved"]
# [inline (always)]
pub fn nu33 (& self) -> Nu33R { Nu33R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Reserved"]
# [inline (always)]
pub fn nu34 (& self) -> Nu34R { Nu34R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:24 - 24:21\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 21) & 0x0f) as u8) } # [doc = "Bit 25 - 25:25\\]
Reserved"]
# [inline (always)]
pub fn nu35 (& self) -> Nu35R { Nu35R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Reserved"]
# [inline (always)]
pub fn nu36 (& self) -> Nu36R { Nu36R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
pub fn nu37 (& self) -> Nu37R { Nu37R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Reserved"]
# [inline (always)]
pub fn nu38 (& self) -> Nu38R { Nu38R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcStatusRegSpec > { Reserved1W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch1_crcfail (& mut self) -> Ch1CrcfailW < CrcStatusRegSpec > { Ch1CrcfailW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch1_over (& mut self) -> Ch1OverW < CrcStatusRegSpec > { Ch1OverW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch1_under (& mut self) -> Ch1UnderW < CrcStatusRegSpec > { Ch1UnderW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch1_timeout (& mut self) -> Ch1TimeoutW < CrcStatusRegSpec > { Ch1TimeoutW :: new (self , 4) } # [doc = "Bits 5:8 - 8:5\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < CrcStatusRegSpec > { Reserved2W :: new (self , 5) } # [doc = "Bit 9 - 9:9\\]
Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch2_crcfail (& mut self) -> Ch2CrcfailW < CrcStatusRegSpec > { Ch2CrcfailW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch2_over (& mut self) -> Ch2OverW < CrcStatusRegSpec > { Ch2OverW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch2_under (& mut self) -> Ch2UnderW < CrcStatusRegSpec > { Ch2UnderW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a ΓÇÖ1ΓÇÖ to it only. Writing ΓÇÖ0ΓÇÖ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active"]
# [inline (always)]
# [must_use]
pub fn ch2_timeout (& mut self) -> Ch2TimeoutW < CrcStatusRegSpec > { Ch2TimeoutW :: new (self , 12) } # [doc = "Bits 13:16 - 16:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < CrcStatusRegSpec > { Reserved3W :: new (self , 13) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu31 (& mut self) -> Nu31W < CrcStatusRegSpec > { Nu31W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu32 (& mut self) -> Nu32W < CrcStatusRegSpec > { Nu32W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu33 (& mut self) -> Nu33W < CrcStatusRegSpec > { Nu33W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu34 (& mut self) -> Nu34W < CrcStatusRegSpec > { Nu34W :: new (self , 20) } # [doc = "Bits 21:24 - 24:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < CrcStatusRegSpec > { Reserved4W :: new (self , 21) } # [doc = "Bit 25 - 25:25\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu35 (& mut self) -> Nu35W < CrcStatusRegSpec > { Nu35W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu36 (& mut self) -> Nu36W < CrcStatusRegSpec > { Nu36W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu37 (& mut self) -> Nu37W < CrcStatusRegSpec > { Nu37W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu38 (& mut self) -> Nu38W < CrcStatusRegSpec > { Nu38W :: new (self , 28) } # [doc = "Bits 29:31 - 31:29\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < CrcStatusRegSpec > { Reserved5W :: new (self , 29) } } # [doc = "Contains interrupt flags for different types of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_status_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_status_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcStatusRegSpec ; impl crate :: RegisterSpec for CrcStatusRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_status_reg::R`](R) reader structure"]
impl crate :: Readable for CrcStatusRegSpec { } # [doc = "`write(|w| ..)` method takes [`crc_status_reg::W`](W) writer structure"]
impl crate :: Writable for CrcStatusRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_STATUS_REG to value 0"]
impl crate :: Resettable for CrcStatusRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_INT_OFFSET_REG (rw) register accessor: Contains the interrupt offset vector address\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_int_offset_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_int_offset_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_int_offset_reg`]
module"]
# [doc (alias = "CRC_INT_OFFSET_REG")]
pub type CrcIntOffsetReg = crate :: Reg < crc_int_offset_reg :: CrcIntOffsetRegSpec > ; # [doc = "Contains the interrupt offset vector address"]
pub mod crc_int_offset_reg { # [doc = "Register `CRC_INT_OFFSET_REG` reader"]
pub type R = crate :: R < CrcIntOffsetRegSpec > ; # [doc = "Register `CRC_INT_OFFSET_REG` writer"]
pub type W = crate :: W < CrcIntOffsetRegSpec > ; # [doc = "Field `OFSTREG` reader - 7:0\\]
CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1ΓÇô3. for details."]
pub type OfstregR = crate :: FieldReader ; # [doc = "Field `OFSTREG` writer - 7:0\\]
CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1ΓÇô3. for details."]
pub type OfstregW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `Reserved1` reader - 31:8\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved1` writer - 31:8\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1ΓÇô3. for details."]
# [inline (always)]
pub fn ofstreg (& self) -> OfstregR { OfstregR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1ΓÇô3. for details."]
# [inline (always)]
# [must_use]
pub fn ofstreg (& mut self) -> OfstregW < CrcIntOffsetRegSpec > { OfstregW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcIntOffsetRegSpec > { Reserved1W :: new (self , 8) } } # [doc = "Contains the interrupt offset vector address\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_int_offset_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_int_offset_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcIntOffsetRegSpec ; impl crate :: RegisterSpec for CrcIntOffsetRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_int_offset_reg::R`](R) reader structure"]
impl crate :: Readable for CrcIntOffsetRegSpec { } # [doc = "`write(|w| ..)` method takes [`crc_int_offset_reg::W`](W) writer structure"]
impl crate :: Writable for CrcIntOffsetRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_INT_OFFSET_REG to value 0"]
impl crate :: Resettable for CrcIntOffsetRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_BUSY (rw) register accessor: Contains the busy flag for each channel\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_busy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_busy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_busy`]
module"]
# [doc (alias = "CRC_BUSY")]
pub type CrcBusy = crate :: Reg < crc_busy :: CrcBusySpec > ; # [doc = "Contains the busy flag for each channel"]
pub mod crc_busy { # [doc = "Register `CRC_BUSY` reader"]
pub type R = crate :: R < CrcBusySpec > ; # [doc = "Register `CRC_BUSY` writer"]
pub type W = crate :: W < CrcBusySpec > ; # [doc = "Field `CH1_BUSY` reader - 0:0\\]
CH1_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
pub type Ch1BusyR = crate :: BitReader ; # [doc = "Field `CH1_BUSY` writer - 0:0\\]
CH1_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
pub type Ch1BusyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 7:1\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 7:1\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `Ch2_BUSY` reader - 8:8\\]
Ch2_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
pub type Ch2BusyR = crate :: BitReader ; # [doc = "Field `Ch2_BUSY` writer - 8:8\\]
Ch2_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
pub type Ch2BusyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 15:9\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 15:9\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU39` reader - 16:16\\]
Reserved"]
pub type Nu39R = crate :: BitReader ; # [doc = "Field `NU39` writer - 16:16\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 23:17\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 23:17\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `NU40` reader - 24:24\\]
Reserved"]
pub type Nu40R = crate :: BitReader ; # [doc = "Field `NU40` writer - 24:24\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 31:25\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 31:25\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CH1_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
# [inline (always)]
pub fn ch1_busy (& self) -> Ch1BusyR { Ch1BusyR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bit 8 - 8:8\\]
Ch2_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
# [inline (always)]
pub fn ch2_busy (& self) -> Ch2BusyR { Ch2BusyR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:15 - 15:9\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 9) & 0x7f) as u8) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:23 - 23:17\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 17) & 0x7f) as u8) } # [doc = "Bit 24 - 24:24\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
CH1_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
# [inline (always)]
# [must_use]
pub fn ch1_busy (& mut self) -> Ch1BusyW < CrcBusySpec > { Ch1BusyW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcBusySpec > { Reserved1W :: new (self , 1) } # [doc = "Bit 8 - 8:8\\]
Ch2_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed."]
# [inline (always)]
# [must_use]
pub fn ch2_busy (& mut self) -> Ch2BusyW < CrcBusySpec > { Ch2BusyW :: new (self , 8) } # [doc = "Bits 9:15 - 15:9\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < CrcBusySpec > { Reserved2W :: new (self , 9) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < CrcBusySpec > { Nu39W :: new (self , 16) } # [doc = "Bits 17:23 - 23:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < CrcBusySpec > { Reserved3W :: new (self , 17) } # [doc = "Bit 24 - 24:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < CrcBusySpec > { Nu40W :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < CrcBusySpec > { Reserved4W :: new (self , 25) } } # [doc = "Contains the busy flag for each channel\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_busy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_busy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcBusySpec ; impl crate :: RegisterSpec for CrcBusySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_busy::R`](R) reader structure"]
impl crate :: Readable for CrcBusySpec { } # [doc = "`write(|w| ..)` method takes [`crc_busy::W`](W) writer structure"]
impl crate :: Writable for CrcBusySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_BUSY to value 0"]
impl crate :: Resettable for CrcBusySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_PCOUNT_REG1 (rw) register accessor: Channel 1 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_pcount_reg1`]
module"]
# [doc (alias = "CRC_PCOUNT_REG1")]
pub type CrcPcountReg1 = crate :: Reg < crc_pcount_reg1 :: CrcPcountReg1Spec > ; # [doc = "Channel 1 preload register for the pattern count"]
pub mod crc_pcount_reg1 { # [doc = "Register `CRC_PCOUNT_REG1` reader"]
pub type R = crate :: R < CrcPcountReg1Spec > ; # [doc = "Register `CRC_PCOUNT_REG1` writer"]
pub type W = crate :: W < CrcPcountReg1Spec > ; # [doc = "Field `CRC_PAT_COUNT1` reader - 19:0\\]
Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
pub type CrcPatCount1R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC_PAT_COUNT1` writer - 19:0\\]
Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
pub type CrcPatCount1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `Reserved1` reader - 31:20\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:20\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
# [inline (always)]
pub fn crc_pat_count1 (& self) -> CrcPatCount1R { CrcPatCount1R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
# [inline (always)]
# [must_use]
pub fn crc_pat_count1 (& mut self) -> CrcPatCount1W < CrcPcountReg1Spec > { CrcPatCount1W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcPcountReg1Spec > { Reserved1W :: new (self , 20) } } # [doc = "Channel 1 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcPcountReg1Spec ; impl crate :: RegisterSpec for CrcPcountReg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_pcount_reg1::R`](R) reader structure"]
impl crate :: Readable for CrcPcountReg1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_pcount_reg1::W`](W) writer structure"]
impl crate :: Writable for CrcPcountReg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_PCOUNT_REG1 to value 0"]
impl crate :: Resettable for CrcPcountReg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_SCOUNT_REG1 (rw) register accessor: Channel 1 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_scount_reg1`]
module"]
# [doc (alias = "CRC_SCOUNT_REG1")]
pub type CrcScountReg1 = crate :: Reg < crc_scount_reg1 :: CrcScountReg1Spec > ; # [doc = "Channel 1 preload register for the sector count"]
pub mod crc_scount_reg1 { # [doc = "Register `CRC_SCOUNT_REG1` reader"]
pub type R = crate :: R < CrcScountReg1Spec > ; # [doc = "Register `CRC_SCOUNT_REG1` writer"]
pub type W = crate :: W < CrcScountReg1Spec > ; # [doc = "Field `CRC_SEC_COUNT1` reader - 15:0\\]
Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
pub type CrcSecCount1R = crate :: FieldReader < u16 > ; # [doc = "Field `CRC_SEC_COUNT1` writer - 15:0\\]
Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
pub type CrcSecCount1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
# [inline (always)]
pub fn crc_sec_count1 (& self) -> CrcSecCount1R { CrcSecCount1R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
# [inline (always)]
# [must_use]
pub fn crc_sec_count1 (& mut self) -> CrcSecCount1W < CrcScountReg1Spec > { CrcSecCount1W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcScountReg1Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 1 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcScountReg1Spec ; impl crate :: RegisterSpec for CrcScountReg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_scount_reg1::R`](R) reader structure"]
impl crate :: Readable for CrcScountReg1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_scount_reg1::W`](W) writer structure"]
impl crate :: Writable for CrcScountReg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_SCOUNT_REG1 to value 0"]
impl crate :: Resettable for CrcScountReg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_CURSEC_REG1 (rw) register accessor: Channel 1 current sector register contains the sector number which causes CRC failure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_cursec_reg1`]
module"]
# [doc (alias = "CRC_CURSEC_REG1")]
pub type CrcCursecReg1 = crate :: Reg < crc_cursec_reg1 :: CrcCursecReg1Spec > ; # [doc = "Channel 1 current sector register contains the sector number which causes CRC failure"]
pub mod crc_cursec_reg1 { # [doc = "Register `CRC_CURSEC_REG1` reader"]
pub type R = crate :: R < CrcCursecReg1Spec > ; # [doc = "Register `CRC_CURSEC_REG1` writer"]
pub type W = crate :: W < CrcCursecReg1Spec > ; # [doc = "Field `CRC_CURSEC1` reader - 15:0\\]
Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
pub type CrcCursec1R = crate :: FieldReader < u16 > ; # [doc = "Field `CRC_CURSEC1` writer - 15:0\\]
Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
pub type CrcCursec1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
# [inline (always)]
pub fn crc_cursec1 (& self) -> CrcCursec1R { CrcCursec1R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
# [inline (always)]
# [must_use]
pub fn crc_cursec1 (& mut self) -> CrcCursec1W < CrcCursecReg1Spec > { CrcCursec1W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcCursecReg1Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 1 current sector register contains the sector number which causes CRC failure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCursecReg1Spec ; impl crate :: RegisterSpec for CrcCursecReg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_cursec_reg1::R`](R) reader structure"]
impl crate :: Readable for CrcCursecReg1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_cursec_reg1::W`](W) writer structure"]
impl crate :: Writable for CrcCursecReg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CURSEC_REG1 to value 0"]
impl crate :: Resettable for CrcCursecReg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_WDTOPLD1 (rw) register accessor: Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_wdtopld1`]
module"]
# [doc (alias = "CRC_WDTOPLD1")]
pub type CrcWdtopld1 = crate :: Reg < crc_wdtopld1 :: CrcWdtopld1Spec > ; # [doc = "Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
pub mod crc_wdtopld1 { # [doc = "Register `CRC_WDTOPLD1` reader"]
pub type R = crate :: R < CrcWdtopld1Spec > ; # [doc = "Register `CRC_WDTOPLD1` writer"]
pub type W = crate :: W < CrcWdtopld1Spec > ; # [doc = "Field `CRC_WDTOPLD1` reader - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
pub type CrcWdtopld1R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC_WDTOPLD1` writer - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
pub type CrcWdtopld1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
# [inline (always)]
pub fn crc_wdtopld1 (& self) -> CrcWdtopld1R { CrcWdtopld1R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
# [inline (always)]
# [must_use]
pub fn crc_wdtopld1 (& mut self) -> CrcWdtopld1W < CrcWdtopld1Spec > { CrcWdtopld1W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcWdtopld1Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcWdtopld1Spec ; impl crate :: RegisterSpec for CrcWdtopld1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_wdtopld1::R`](R) reader structure"]
impl crate :: Readable for CrcWdtopld1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_wdtopld1::W`](W) writer structure"]
impl crate :: Writable for CrcWdtopld1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_WDTOPLD1 to value 0"]
impl crate :: Resettable for CrcWdtopld1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_BCTOPLD1 (rw) register accessor: Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_bctopld1`]
module"]
# [doc (alias = "CRC_BCTOPLD1")]
pub type CrcBctopld1 = crate :: Reg < crc_bctopld1 :: CrcBctopld1Spec > ; # [doc = "Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"]
pub mod crc_bctopld1 { # [doc = "Register `CRC_BCTOPLD1` reader"]
pub type R = crate :: R < CrcBctopld1Spec > ; # [doc = "Register `CRC_BCTOPLD1` writer"]
pub type W = crate :: W < CrcBctopld1Spec > ; # [doc = "Field `CRC_BCTOPLD1` reader - 23:0\\]
Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
pub type CrcBctopld1R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC_BCTOPLD1` writer - 23:0\\]
Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
pub type CrcBctopld1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
# [inline (always)]
pub fn crc_bctopld1 (& self) -> CrcBctopld1R { CrcBctopld1R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
# [inline (always)]
# [must_use]
pub fn crc_bctopld1 (& mut self) -> CrcBctopld1W < CrcBctopld1Spec > { CrcBctopld1W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcBctopld1Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcBctopld1Spec ; impl crate :: RegisterSpec for CrcBctopld1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_bctopld1::R`](R) reader structure"]
impl crate :: Readable for CrcBctopld1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_bctopld1::W`](W) writer structure"]
impl crate :: Writable for CrcBctopld1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_BCTOPLD1 to value 0"]
impl crate :: Resettable for CrcBctopld1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGL1 (rw) register accessor: Channel 1 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregl1`]
module"]
# [doc (alias = "PSA_SIGREGL1")]
pub type PsaSigregl1 = crate :: Reg < psa_sigregl1 :: PsaSigregl1Spec > ; # [doc = "Channel 1 PSA signature low register"]
pub mod psa_sigregl1 { # [doc = "Register `PSA_SIGREGL1` reader"]
pub type R = crate :: R < PsaSigregl1Spec > ; # [doc = "Register `PSA_SIGREGL1` writer"]
pub type W = crate :: W < PsaSigregl1Spec > ; # [doc = "Field `PSASIG1_31_0` reader - 31:0\\]
Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1\\[31:0\\]
register."]
pub type Psasig1_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `PSASIG1_31_0` writer - 31:0\\]
Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1\\[31:0\\]
register."]
pub type Psasig1_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1\\[31:0\\]
register."]
# [inline (always)]
pub fn psasig1_31_0 (& self) -> Psasig1_31_0R { Psasig1_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1\\[31:0\\]
register."]
# [inline (always)]
# [must_use]
pub fn psasig1_31_0 (& mut self) -> Psasig1_31_0W < PsaSigregl1Spec > { Psasig1_31_0W :: new (self , 0) } } # [doc = "Channel 1 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregl1Spec ; impl crate :: RegisterSpec for PsaSigregl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregl1::R`](R) reader structure"]
impl crate :: Readable for PsaSigregl1Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregl1::W`](W) writer structure"]
impl crate :: Writable for PsaSigregl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGL1 to value 0"]
impl crate :: Resettable for PsaSigregl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGH1 (rw) register accessor: Channel 1 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregh1`]
module"]
# [doc (alias = "PSA_SIGREGH1")]
pub type PsaSigregh1 = crate :: Reg < psa_sigregh1 :: PsaSigregh1Spec > ; # [doc = "Channel 1 PSA signature high register"]
pub mod psa_sigregh1 { # [doc = "Register `PSA_SIGREGH1` reader"]
pub type R = crate :: R < PsaSigregh1Spec > ; # [doc = "Register `PSA_SIGREGH1` writer"]
pub type W = crate :: W < PsaSigregh1Spec > ; # [doc = "Field `PSA_SIG1_63_32` reader - 31:0\\]
Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1\\[63:32\\]
register."]
pub type PsaSig1_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `PSA_SIG1_63_32` writer - 31:0\\]
Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1\\[63:32\\]
register."]
pub type PsaSig1_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1\\[63:32\\]
register."]
# [inline (always)]
pub fn psa_sig1_63_32 (& self) -> PsaSig1_63_32R { PsaSig1_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1\\[63:32\\]
register."]
# [inline (always)]
# [must_use]
pub fn psa_sig1_63_32 (& mut self) -> PsaSig1_63_32W < PsaSigregh1Spec > { PsaSig1_63_32W :: new (self , 0) } } # [doc = "Channel 1 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregh1Spec ; impl crate :: RegisterSpec for PsaSigregh1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregh1::R`](R) reader structure"]
impl crate :: Readable for PsaSigregh1Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregh1::W`](W) writer structure"]
impl crate :: Writable for PsaSigregh1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGH1 to value 0"]
impl crate :: Resettable for PsaSigregh1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGL1 (rw) register accessor: Channel 1 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regl1`]
module"]
# [doc (alias = "CRC_REGL1")]
pub type CrcRegl1 = crate :: Reg < crc_regl1 :: CrcRegl1Spec > ; # [doc = "Channel 1 CRC value low register"]
pub mod crc_regl1 { # [doc = "Register `CRC_REGL1` reader"]
pub type R = crate :: R < CrcRegl1Spec > ; # [doc = "Register `CRC_REGL1` writer"]
pub type W = crate :: W < CrcRegl1Spec > ; # [doc = "Field `CRC1_31_0` reader - 31:0\\]
Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1\\[31:0\\]
regis- ter."]
pub type Crc1_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC1_31_0` writer - 31:0\\]
Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1\\[31:0\\]
regis- ter."]
pub type Crc1_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1\\[31:0\\]
regis- ter."]
# [inline (always)]
pub fn crc1_31_0 (& self) -> Crc1_31_0R { Crc1_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1\\[31:0\\]
regis- ter."]
# [inline (always)]
# [must_use]
pub fn crc1_31_0 (& mut self) -> Crc1_31_0W < CrcRegl1Spec > { Crc1_31_0W :: new (self , 0) } } # [doc = "Channel 1 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegl1Spec ; impl crate :: RegisterSpec for CrcRegl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regl1::R`](R) reader structure"]
impl crate :: Readable for CrcRegl1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regl1::W`](W) writer structure"]
impl crate :: Writable for CrcRegl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGL1 to value 0"]
impl crate :: Resettable for CrcRegl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGH1 (rw) register accessor: Channel 1 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regh1`]
module"]
# [doc (alias = "CRC_REGH1")]
pub type CrcRegh1 = crate :: Reg < crc_regh1 :: CrcRegh1Spec > ; # [doc = "Channel 1 CRC value high register"]
pub mod crc_regh1 { # [doc = "Register `CRC_REGH1` reader"]
pub type R = crate :: R < CrcRegh1Spec > ; # [doc = "Register `CRC_REGH1` writer"]
pub type W = crate :: W < CrcRegh1Spec > ; # [doc = "Field `CRC1_63_32` reader - 31:0\\]
Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1\\[63:32\\]
regis- ter."]
pub type Crc1_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC1_63_32` writer - 31:0\\]
Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1\\[63:32\\]
regis- ter."]
pub type Crc1_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1\\[63:32\\]
regis- ter."]
# [inline (always)]
pub fn crc1_63_32 (& self) -> Crc1_63_32R { Crc1_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1\\[63:32\\]
regis- ter."]
# [inline (always)]
# [must_use]
pub fn crc1_63_32 (& mut self) -> Crc1_63_32W < CrcRegh1Spec > { Crc1_63_32W :: new (self , 0) } } # [doc = "Channel 1 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegh1Spec ; impl crate :: RegisterSpec for CrcRegh1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regh1::R`](R) reader structure"]
impl crate :: Readable for CrcRegh1Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regh1::W`](W) writer structure"]
impl crate :: Writable for CrcRegh1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGH1 to value 0"]
impl crate :: Resettable for CrcRegh1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGL1 (rw) register accessor: Channel 1 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregl1`]
module"]
# [doc (alias = "PSA_SECSIGREGL1")]
pub type PsaSecsigregl1 = crate :: Reg < psa_secsigregl1 :: PsaSecsigregl1Spec > ; # [doc = "Channel 1 PSA sector signature low regis-ter"]
pub mod psa_secsigregl1 { # [doc = "Register `PSA_SECSIGREGL1` reader"]
pub type R = crate :: R < PsaSecsigregl1Spec > ; # [doc = "Register `PSA_SECSIGREGL1` writer"]
pub type W = crate :: W < PsaSecsigregl1Spec > ; # [doc = "Field `PSASECSIG1_31_0` reader - 31:0\\]
Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1\\[31:0\\]
register."]
pub type Psasecsig1_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `PSASECSIG1_31_0` writer - 31:0\\]
Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1\\[31:0\\]
register."]
pub type Psasecsig1_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1\\[31:0\\]
register."]
# [inline (always)]
pub fn psasecsig1_31_0 (& self) -> Psasecsig1_31_0R { Psasecsig1_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1\\[31:0\\]
register."]
# [inline (always)]
# [must_use]
pub fn psasecsig1_31_0 (& mut self) -> Psasecsig1_31_0W < PsaSecsigregl1Spec > { Psasecsig1_31_0W :: new (self , 0) } } # [doc = "Channel 1 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregl1Spec ; impl crate :: RegisterSpec for PsaSecsigregl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregl1::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregl1Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregl1::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGL1 to value 0"]
impl crate :: Resettable for PsaSecsigregl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGH1 (rw) register accessor: Channel 1 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregh1`]
module"]
# [doc (alias = "PSA_SECSIGREGH1")]
pub type PsaSecsigregh1 = crate :: Reg < psa_secsigregh1 :: PsaSecsigregh1Spec > ; # [doc = "Channel 1 PSA sector signature high regis-ter"]
pub mod psa_secsigregh1 { # [doc = "Register `PSA_SECSIGREGH1` reader"]
pub type R = crate :: R < PsaSecsigregh1Spec > ; # [doc = "Register `PSA_SECSIGREGH1` writer"]
pub type W = crate :: W < PsaSecsigregh1Spec > ; # [doc = "Field `PSASECSIG1_63_32` reader - 31:0\\]
Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1\\[63:32\\]
register."]
pub type Psasecsig1_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `PSASECSIG1_63_32` writer - 31:0\\]
Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1\\[63:32\\]
register."]
pub type Psasecsig1_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1\\[63:32\\]
register."]
# [inline (always)]
pub fn psasecsig1_63_32 (& self) -> Psasecsig1_63_32R { Psasecsig1_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1\\[63:32\\]
register."]
# [inline (always)]
# [must_use]
pub fn psasecsig1_63_32 (& mut self) -> Psasecsig1_63_32W < PsaSecsigregh1Spec > { Psasecsig1_63_32W :: new (self , 0) } } # [doc = "Channel 1 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregh1Spec ; impl crate :: RegisterSpec for PsaSecsigregh1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregh1::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregh1Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregh1::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregh1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGH1 to value 0"]
impl crate :: Resettable for PsaSecsigregh1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGL1 (rw) register accessor: Channel 1 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregl1`]
module"]
# [doc (alias = "RAW_DATAREGL1")]
pub type RawDataregl1 = crate :: Reg < raw_dataregl1 :: RawDataregl1Spec > ; # [doc = "Channel 1 un-compressed raw data low register"]
pub mod raw_dataregl1 { # [doc = "Register `RAW_DATAREGL1` reader"]
pub type R = crate :: R < RawDataregl1Spec > ; # [doc = "Register `RAW_DATAREGL1` writer"]
pub type W = crate :: W < RawDataregl1Spec > ; # [doc = "Field `RAW_DATA1_31_0` reader - 31:0\\]
Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
pub type RawData1_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `RAW_DATA1_31_0` writer - 31:0\\]
Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
pub type RawData1_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
# [inline (always)]
pub fn raw_data1_31_0 (& self) -> RawData1_31_0R { RawData1_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
# [inline (always)]
# [must_use]
pub fn raw_data1_31_0 (& mut self) -> RawData1_31_0W < RawDataregl1Spec > { RawData1_31_0W :: new (self , 0) } } # [doc = "Channel 1 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregl1Spec ; impl crate :: RegisterSpec for RawDataregl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregl1::R`](R) reader structure"]
impl crate :: Readable for RawDataregl1Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregl1::W`](W) writer structure"]
impl crate :: Writable for RawDataregl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGL1 to value 0"]
impl crate :: Resettable for RawDataregl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGH1 (rw) register accessor: Channel 1 un-compressed raw data high register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregh1`]
module"]
# [doc (alias = "RAW_DATAREGH1")]
pub type RawDataregh1 = crate :: Reg < raw_dataregh1 :: RawDataregh1Spec > ; # [doc = "Channel 1 un-compressed raw data high register"]
pub mod raw_dataregh1 { # [doc = "Register `RAW_DATAREGH1` reader"]
pub type R = crate :: R < RawDataregh1Spec > ; # [doc = "Register `RAW_DATAREGH1` writer"]
pub type W = crate :: W < RawDataregh1Spec > ; # [doc = "Field `RAW_DATA1_63_32` reader - 31:0\\]
Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
pub type RawData1_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `RAW_DATA1_63_32` writer - 31:0\\]
Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
pub type RawData1_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
# [inline (always)]
pub fn raw_data1_63_32 (& self) -> RawData1_63_32R { RawData1_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
# [inline (always)]
# [must_use]
pub fn raw_data1_63_32 (& mut self) -> RawData1_63_32W < RawDataregh1Spec > { RawData1_63_32W :: new (self , 0) } } # [doc = "Channel 1 un-compressed raw data high register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregh1Spec ; impl crate :: RegisterSpec for RawDataregh1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregh1::R`](R) reader structure"]
impl crate :: Readable for RawDataregh1Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregh1::W`](W) writer structure"]
impl crate :: Writable for RawDataregh1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGH1 to value 0"]
impl crate :: Resettable for RawDataregh1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_PCOUNT_REG2 (rw) register accessor: Channel 2 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_pcount_reg2`]
module"]
# [doc (alias = "CRC_PCOUNT_REG2")]
pub type CrcPcountReg2 = crate :: Reg < crc_pcount_reg2 :: CrcPcountReg2Spec > ; # [doc = "Channel 2 preload register for the pattern count"]
pub mod crc_pcount_reg2 { # [doc = "Register `CRC_PCOUNT_REG2` reader"]
pub type R = crate :: R < CrcPcountReg2Spec > ; # [doc = "Register `CRC_PCOUNT_REG2` writer"]
pub type W = crate :: W < CrcPcountReg2Spec > ; # [doc = "Field `CRC_PAT_COUNT2` reader - 19:0\\]
Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
pub type CrcPatCount2R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC_PAT_COUNT2` writer - 19:0\\]
Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
pub type CrcPatCount2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `Reserved1` reader - 31:20\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:20\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
# [inline (always)]
pub fn crc_pat_count2 (& self) -> CrcPatCount2R { CrcPatCount2R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."]
# [inline (always)]
# [must_use]
pub fn crc_pat_count2 (& mut self) -> CrcPatCount2W < CrcPcountReg2Spec > { CrcPatCount2W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcPcountReg2Spec > { Reserved1W :: new (self , 20) } } # [doc = "Channel 2 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcPcountReg2Spec ; impl crate :: RegisterSpec for CrcPcountReg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_pcount_reg2::R`](R) reader structure"]
impl crate :: Readable for CrcPcountReg2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_pcount_reg2::W`](W) writer structure"]
impl crate :: Writable for CrcPcountReg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_PCOUNT_REG2 to value 0"]
impl crate :: Resettable for CrcPcountReg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_SCOUNT_REG2 (rw) register accessor: Channel 2 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_scount_reg2`]
module"]
# [doc (alias = "CRC_SCOUNT_REG2")]
pub type CrcScountReg2 = crate :: Reg < crc_scount_reg2 :: CrcScountReg2Spec > ; # [doc = "Channel 2 preload register for the sector count"]
pub mod crc_scount_reg2 { # [doc = "Register `CRC_SCOUNT_REG2` reader"]
pub type R = crate :: R < CrcScountReg2Spec > ; # [doc = "Register `CRC_SCOUNT_REG2` writer"]
pub type W = crate :: W < CrcScountReg2Spec > ; # [doc = "Field `CRC_SEC_COUNT2` reader - 15:0\\]
Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
pub type CrcSecCount2R = crate :: FieldReader < u16 > ; # [doc = "Field `CRC_SEC_COUNT2` writer - 15:0\\]
Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
pub type CrcSecCount2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
# [inline (always)]
pub fn crc_sec_count2 (& self) -> CrcSecCount2R { CrcSecCount2R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."]
# [inline (always)]
# [must_use]
pub fn crc_sec_count2 (& mut self) -> CrcSecCount2W < CrcScountReg2Spec > { CrcSecCount2W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcScountReg2Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 2 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcScountReg2Spec ; impl crate :: RegisterSpec for CrcScountReg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_scount_reg2::R`](R) reader structure"]
impl crate :: Readable for CrcScountReg2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_scount_reg2::W`](W) writer structure"]
impl crate :: Writable for CrcScountReg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_SCOUNT_REG2 to value 0"]
impl crate :: Resettable for CrcScountReg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_CURSEC_REG2 (rw) register accessor: Channel 2 current sector register contains the sector number which causes CRC fail-ure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_cursec_reg2`]
module"]
# [doc (alias = "CRC_CURSEC_REG2")]
pub type CrcCursecReg2 = crate :: Reg < crc_cursec_reg2 :: CrcCursecReg2Spec > ; # [doc = "Channel 2 current sector register contains the sector number which causes CRC fail-ure"]
pub mod crc_cursec_reg2 { # [doc = "Register `CRC_CURSEC_REG2` reader"]
pub type R = crate :: R < CrcCursecReg2Spec > ; # [doc = "Register `CRC_CURSEC_REG2` writer"]
pub type W = crate :: W < CrcCursecReg2Spec > ; # [doc = "Field `CRC_CURSEC2` reader - 15:0\\]
Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
pub type CrcCursec2R = crate :: FieldReader < u16 > ; # [doc = "Field `CRC_CURSEC2` writer - 15:0\\]
Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
pub type CrcCursec2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
# [inline (always)]
pub fn crc_cursec2 (& self) -> CrcCursec2R { CrcCursec2R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number."]
# [inline (always)]
# [must_use]
pub fn crc_cursec2 (& mut self) -> CrcCursec2W < CrcCursecReg2Spec > { CrcCursec2W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcCursecReg2Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 2 current sector register contains the sector number which causes CRC fail-ure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCursecReg2Spec ; impl crate :: RegisterSpec for CrcCursecReg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_cursec_reg2::R`](R) reader structure"]
impl crate :: Readable for CrcCursecReg2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_cursec_reg2::W`](W) writer structure"]
impl crate :: Writable for CrcCursecReg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CURSEC_REG2 to value 0"]
impl crate :: Resettable for CrcCursecReg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_WDTOPLD2 (rw) register accessor: Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_wdtopld2`]
module"]
# [doc (alias = "CRC_WDTOPLD2")]
pub type CrcWdtopld2 = crate :: Reg < crc_wdtopld2 :: CrcWdtopld2Spec > ; # [doc = "Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
pub mod crc_wdtopld2 { # [doc = "Register `CRC_WDTOPLD2` reader"]
pub type R = crate :: R < CrcWdtopld2Spec > ; # [doc = "Register `CRC_WDTOPLD2` writer"]
pub type W = crate :: W < CrcWdtopld2Spec > ; # [doc = "Field `CRC_WDTOPLD2` reader - 23:0\\]
Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
pub type CrcWdtopld2R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC_WDTOPLD2` writer - 23:0\\]
Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
pub type CrcWdtopld2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
# [inline (always)]
pub fn crc_wdtopld2 (& self) -> CrcWdtopld2R { CrcWdtopld2R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
# [inline (always)]
# [must_use]
pub fn crc_wdtopld2 (& mut self) -> CrcWdtopld2W < CrcWdtopld2Spec > { CrcWdtopld2W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcWdtopld2Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcWdtopld2Spec ; impl crate :: RegisterSpec for CrcWdtopld2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_wdtopld2::R`](R) reader structure"]
impl crate :: Readable for CrcWdtopld2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_wdtopld2::W`](W) writer structure"]
impl crate :: Writable for CrcWdtopld2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_WDTOPLD2 to value 0"]
impl crate :: Resettable for CrcWdtopld2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_BCTOPLD2 (rw) register accessor: Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_bctopld2`]
module"]
# [doc (alias = "CRC_BCTOPLD2")]
pub type CrcBctopld2 = crate :: Reg < crc_bctopld2 :: CrcBctopld2Spec > ; # [doc = "Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"]
pub mod crc_bctopld2 { # [doc = "Register `CRC_BCTOPLD2` reader"]
pub type R = crate :: R < CrcBctopld2Spec > ; # [doc = "Register `CRC_BCTOPLD2` writer"]
pub type W = crate :: W < CrcBctopld2Spec > ; # [doc = "Field `CRC_BCTOPLD2` reader - 23:0\\]
Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
pub type CrcBctopld2R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC_BCTOPLD2` writer - 23:0\\]
Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
pub type CrcBctopld2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
# [inline (always)]
pub fn crc_bctopld2 (& self) -> CrcBctopld2R { CrcBctopld2R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."]
# [inline (always)]
# [must_use]
pub fn crc_bctopld2 (& mut self) -> CrcBctopld2W < CrcBctopld2Spec > { CrcBctopld2W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcBctopld2Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcBctopld2Spec ; impl crate :: RegisterSpec for CrcBctopld2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_bctopld2::R`](R) reader structure"]
impl crate :: Readable for CrcBctopld2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_bctopld2::W`](W) writer structure"]
impl crate :: Writable for CrcBctopld2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_BCTOPLD2 to value 0"]
impl crate :: Resettable for CrcBctopld2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGL2 (rw) register accessor: Channel 2 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregl2`]
module"]
# [doc (alias = "PSA_SIGREGL2")]
pub type PsaSigregl2 = crate :: Reg < psa_sigregl2 :: PsaSigregl2Spec > ; # [doc = "Channel 2 PSA signature low register"]
pub mod psa_sigregl2 { # [doc = "Register `PSA_SIGREGL2` reader"]
pub type R = crate :: R < PsaSigregl2Spec > ; # [doc = "Register `PSA_SIGREGL2` writer"]
pub type W = crate :: W < PsaSigregl2Spec > ; # [doc = "Field `PSASIG2_31_0` reader - 31:0\\]
Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2\\[31:0\\]
register."]
pub type Psasig2_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `PSASIG2_31_0` writer - 31:0\\]
Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2\\[31:0\\]
register."]
pub type Psasig2_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2\\[31:0\\]
register."]
# [inline (always)]
pub fn psasig2_31_0 (& self) -> Psasig2_31_0R { Psasig2_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2\\[31:0\\]
register."]
# [inline (always)]
# [must_use]
pub fn psasig2_31_0 (& mut self) -> Psasig2_31_0W < PsaSigregl2Spec > { Psasig2_31_0W :: new (self , 0) } } # [doc = "Channel 2 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregl2Spec ; impl crate :: RegisterSpec for PsaSigregl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregl2::R`](R) reader structure"]
impl crate :: Readable for PsaSigregl2Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregl2::W`](W) writer structure"]
impl crate :: Writable for PsaSigregl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGL2 to value 0"]
impl crate :: Resettable for PsaSigregl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGH2 (rw) register accessor: Channel 2 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregh2`]
module"]
# [doc (alias = "PSA_SIGREGH2")]
pub type PsaSigregh2 = crate :: Reg < psa_sigregh2 :: PsaSigregh2Spec > ; # [doc = "Channel 2 PSA signature high register"]
pub mod psa_sigregh2 { # [doc = "Register `PSA_SIGREGH2` reader"]
pub type R = crate :: R < PsaSigregh2Spec > ; # [doc = "Register `PSA_SIGREGH2` writer"]
pub type W = crate :: W < PsaSigregh2Spec > ; # [doc = "Field `PSA_SIG2_63_32` reader - 31:0\\]
Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2\\[63:32\\]
register."]
pub type PsaSig2_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `PSA_SIG2_63_32` writer - 31:0\\]
Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2\\[63:32\\]
register."]
pub type PsaSig2_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2\\[63:32\\]
register."]
# [inline (always)]
pub fn psa_sig2_63_32 (& self) -> PsaSig2_63_32R { PsaSig2_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2\\[63:32\\]
register."]
# [inline (always)]
# [must_use]
pub fn psa_sig2_63_32 (& mut self) -> PsaSig2_63_32W < PsaSigregh2Spec > { PsaSig2_63_32W :: new (self , 0) } } # [doc = "Channel 2 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregh2Spec ; impl crate :: RegisterSpec for PsaSigregh2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregh2::R`](R) reader structure"]
impl crate :: Readable for PsaSigregh2Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregh2::W`](W) writer structure"]
impl crate :: Writable for PsaSigregh2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGH2 to value 0"]
impl crate :: Resettable for PsaSigregh2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGL2 (rw) register accessor: Channel 2 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regl2`]
module"]
# [doc (alias = "CRC_REGL2")]
pub type CrcRegl2 = crate :: Reg < crc_regl2 :: CrcRegl2Spec > ; # [doc = "Channel 2 CRC value low register"]
pub mod crc_regl2 { # [doc = "Register `CRC_REGL2` reader"]
pub type R = crate :: R < CrcRegl2Spec > ; # [doc = "Register `CRC_REGL2` writer"]
pub type W = crate :: W < CrcRegl2Spec > ; # [doc = "Field `CRC2_31_0` reader - 31:0\\]
Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2\\[31:0\\]
regis- ter."]
pub type Crc2_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC2_31_0` writer - 31:0\\]
Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2\\[31:0\\]
regis- ter."]
pub type Crc2_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2\\[31:0\\]
regis- ter."]
# [inline (always)]
pub fn crc2_31_0 (& self) -> Crc2_31_0R { Crc2_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2\\[31:0\\]
regis- ter."]
# [inline (always)]
# [must_use]
pub fn crc2_31_0 (& mut self) -> Crc2_31_0W < CrcRegl2Spec > { Crc2_31_0W :: new (self , 0) } } # [doc = "Channel 2 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegl2Spec ; impl crate :: RegisterSpec for CrcRegl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regl2::R`](R) reader structure"]
impl crate :: Readable for CrcRegl2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regl2::W`](W) writer structure"]
impl crate :: Writable for CrcRegl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGL2 to value 0"]
impl crate :: Resettable for CrcRegl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGH2 (rw) register accessor: Channel 2 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regh2`]
module"]
# [doc (alias = "CRC_REGH2")]
pub type CrcRegh2 = crate :: Reg < crc_regh2 :: CrcRegh2Spec > ; # [doc = "Channel 2 CRC value high register"]
pub mod crc_regh2 { # [doc = "Register `CRC_REGH2` reader"]
pub type R = crate :: R < CrcRegh2Spec > ; # [doc = "Register `CRC_REGH2` writer"]
pub type W = crate :: W < CrcRegh2Spec > ; # [doc = "Field `CRC2_63_32` reader - 31:0\\]
Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2\\[63:32\\]
regis- ter."]
pub type Crc2_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `CRC2_63_32` writer - 31:0\\]
Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2\\[63:32\\]
regis- ter."]
pub type Crc2_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2\\[63:32\\]
regis- ter."]
# [inline (always)]
pub fn crc2_63_32 (& self) -> Crc2_63_32R { Crc2_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2\\[63:32\\]
regis- ter."]
# [inline (always)]
# [must_use]
pub fn crc2_63_32 (& mut self) -> Crc2_63_32W < CrcRegh2Spec > { Crc2_63_32W :: new (self , 0) } } # [doc = "Channel 2 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegh2Spec ; impl crate :: RegisterSpec for CrcRegh2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regh2::R`](R) reader structure"]
impl crate :: Readable for CrcRegh2Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regh2::W`](W) writer structure"]
impl crate :: Writable for CrcRegh2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGH2 to value 0"]
impl crate :: Resettable for CrcRegh2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGL2 (rw) register accessor: Channel 2 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregl2`]
module"]
# [doc (alias = "PSA_SECSIGREGL2")]
pub type PsaSecsigregl2 = crate :: Reg < psa_secsigregl2 :: PsaSecsigregl2Spec > ; # [doc = "Channel 2 PSA sector signature low regis-ter"]
pub mod psa_secsigregl2 { # [doc = "Register `PSA_SECSIGREGL2` reader"]
pub type R = crate :: R < PsaSecsigregl2Spec > ; # [doc = "Register `PSA_SECSIGREGL2` writer"]
pub type W = crate :: W < PsaSecsigregl2Spec > ; # [doc = "Field `PSASECSIG2_31_0` reader - 31:0\\]
Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2\\[31:0\\]
register."]
pub type Psasecsig2_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `PSASECSIG2_31_0` writer - 31:0\\]
Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2\\[31:0\\]
register."]
pub type Psasecsig2_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2\\[31:0\\]
register."]
# [inline (always)]
pub fn psasecsig2_31_0 (& self) -> Psasecsig2_31_0R { Psasecsig2_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2\\[31:0\\]
register."]
# [inline (always)]
# [must_use]
pub fn psasecsig2_31_0 (& mut self) -> Psasecsig2_31_0W < PsaSecsigregl2Spec > { Psasecsig2_31_0W :: new (self , 0) } } # [doc = "Channel 2 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregl2Spec ; impl crate :: RegisterSpec for PsaSecsigregl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregl2::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregl2Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregl2::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGL2 to value 0"]
impl crate :: Resettable for PsaSecsigregl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGH2 (rw) register accessor: Channel 2 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregh2`]
module"]
# [doc (alias = "PSA_SECSIGREGH2")]
pub type PsaSecsigregh2 = crate :: Reg < psa_secsigregh2 :: PsaSecsigregh2Spec > ; # [doc = "Channel 2 PSA sector signature high regis-ter"]
pub mod psa_secsigregh2 { # [doc = "Register `PSA_SECSIGREGH2` reader"]
pub type R = crate :: R < PsaSecsigregh2Spec > ; # [doc = "Register `PSA_SECSIGREGH2` writer"]
pub type W = crate :: W < PsaSecsigregh2Spec > ; # [doc = "Field `PSASECSIG2_63_32` reader - 31:0\\]
Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2\\[63:32\\]
register."]
pub type Psasecsig2_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `PSASECSIG2_63_32` writer - 31:0\\]
Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2\\[63:32\\]
register."]
pub type Psasecsig2_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2\\[63:32\\]
register."]
# [inline (always)]
pub fn psasecsig2_63_32 (& self) -> Psasecsig2_63_32R { Psasecsig2_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2\\[63:32\\]
register."]
# [inline (always)]
# [must_use]
pub fn psasecsig2_63_32 (& mut self) -> Psasecsig2_63_32W < PsaSecsigregh2Spec > { Psasecsig2_63_32W :: new (self , 0) } } # [doc = "Channel 2 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregh2Spec ; impl crate :: RegisterSpec for PsaSecsigregh2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregh2::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregh2Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregh2::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregh2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGH2 to value 0"]
impl crate :: Resettable for PsaSecsigregh2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGL2 (rw) register accessor: Channel 2 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregl2`]
module"]
# [doc (alias = "RAW_DATAREGL2")]
pub type RawDataregl2 = crate :: Reg < raw_dataregl2 :: RawDataregl2Spec > ; # [doc = "Channel 2 un-compressed raw data low register"]
pub mod raw_dataregl2 { # [doc = "Register `RAW_DATAREGL2` reader"]
pub type R = crate :: R < RawDataregl2Spec > ; # [doc = "Register `RAW_DATAREGL2` writer"]
pub type W = crate :: W < RawDataregl2Spec > ; # [doc = "Field `RAW_DATA2_31_0` reader - 31:0\\]
Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
pub type RawData2_31_0R = crate :: FieldReader < u32 > ; # [doc = "Field `RAW_DATA2_31_0` writer - 31:0\\]
Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
pub type RawData2_31_0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
# [inline (always)]
pub fn raw_data2_31_0 (& self) -> RawData2_31_0R { RawData2_31_0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."]
# [inline (always)]
# [must_use]
pub fn raw_data2_31_0 (& mut self) -> RawData2_31_0W < RawDataregl2Spec > { RawData2_31_0W :: new (self , 0) } } # [doc = "Channel 2 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregl2Spec ; impl crate :: RegisterSpec for RawDataregl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregl2::R`](R) reader structure"]
impl crate :: Readable for RawDataregl2Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregl2::W`](W) writer structure"]
impl crate :: Writable for RawDataregl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGL2 to value 0"]
impl crate :: Resettable for RawDataregl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGH2 (rw) register accessor: Channel 2 un-compressed raw data high Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregh2`]
module"]
# [doc (alias = "RAW_DATAREGH2")]
pub type RawDataregh2 = crate :: Reg < raw_dataregh2 :: RawDataregh2Spec > ; # [doc = "Channel 2 un-compressed raw data high Register"]
pub mod raw_dataregh2 { # [doc = "Register `RAW_DATAREGH2` reader"]
pub type R = crate :: R < RawDataregh2Spec > ; # [doc = "Register `RAW_DATAREGH2` writer"]
pub type W = crate :: W < RawDataregh2Spec > ; # [doc = "Field `RAW_DATA2_63_32` reader - 31:0\\]
Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
pub type RawData2_63_32R = crate :: FieldReader < u32 > ; # [doc = "Field `RAW_DATA2_63_32` writer - 31:0\\]
Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
pub type RawData2_63_32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
# [inline (always)]
pub fn raw_data2_63_32 (& self) -> RawData2_63_32R { RawData2_63_32R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."]
# [inline (always)]
# [must_use]
pub fn raw_data2_63_32 (& mut self) -> RawData2_63_32W < RawDataregh2Spec > { RawData2_63_32W :: new (self , 0) } } # [doc = "Channel 2 un-compressed raw data high Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregh2Spec ; impl crate :: RegisterSpec for RawDataregh2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregh2::R`](R) reader structure"]
impl crate :: Readable for RawDataregh2Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregh2::W`](W) writer structure"]
impl crate :: Writable for RawDataregh2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGH2 to value 0"]
impl crate :: Resettable for RawDataregh2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_PCOUNT_REG3 (rw) register accessor: Channel 3 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_pcount_reg3`]
module"]
# [doc (alias = "CRC_PCOUNT_REG3")]
pub type CrcPcountReg3 = crate :: Reg < crc_pcount_reg3 :: CrcPcountReg3Spec > ; # [doc = "Channel 3 preload register for the pattern count"]
pub mod crc_pcount_reg3 { # [doc = "Register `CRC_PCOUNT_REG3` reader"]
pub type R = crate :: R < CrcPcountReg3Spec > ; # [doc = "Register `CRC_PCOUNT_REG3` writer"]
pub type W = crate :: W < CrcPcountReg3Spec > ; # [doc = "Field `NU41` reader - 19:0\\]
Reserved"]
pub type Nu41R = crate :: FieldReader < u32 > ; # [doc = "Field `NU41` writer - 19:0\\]
Reserved"]
pub type Nu41W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `Reserved1` reader - 31:20\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:20\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
Reserved"]
# [inline (always)]
pub fn nu41 (& self) -> Nu41R { Nu41R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu41 (& mut self) -> Nu41W < CrcPcountReg3Spec > { Nu41W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcPcountReg3Spec > { Reserved1W :: new (self , 20) } } # [doc = "Channel 3 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcPcountReg3Spec ; impl crate :: RegisterSpec for CrcPcountReg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_pcount_reg3::R`](R) reader structure"]
impl crate :: Readable for CrcPcountReg3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_pcount_reg3::W`](W) writer structure"]
impl crate :: Writable for CrcPcountReg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_PCOUNT_REG3 to value 0"]
impl crate :: Resettable for CrcPcountReg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_SCOUNT_REG3 (rw) register accessor: Channel 3 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_scount_reg3`]
module"]
# [doc (alias = "CRC_SCOUNT_REG3")]
pub type CrcScountReg3 = crate :: Reg < crc_scount_reg3 :: CrcScountReg3Spec > ; # [doc = "Channel 3 preload register for the sector count"]
pub mod crc_scount_reg3 { # [doc = "Register `CRC_SCOUNT_REG3` reader"]
pub type R = crate :: R < CrcScountReg3Spec > ; # [doc = "Register `CRC_SCOUNT_REG3` writer"]
pub type W = crate :: W < CrcScountReg3Spec > ; # [doc = "Field `NU42` reader - 15:0\\]
Reserved"]
pub type Nu42R = crate :: FieldReader < u16 > ; # [doc = "Field `NU42` writer - 15:0\\]
Reserved"]
pub type Nu42W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
pub fn nu42 (& self) -> Nu42R { Nu42R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu42 (& mut self) -> Nu42W < CrcScountReg3Spec > { Nu42W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcScountReg3Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 3 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcScountReg3Spec ; impl crate :: RegisterSpec for CrcScountReg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_scount_reg3::R`](R) reader structure"]
impl crate :: Readable for CrcScountReg3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_scount_reg3::W`](W) writer structure"]
impl crate :: Writable for CrcScountReg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_SCOUNT_REG3 to value 0"]
impl crate :: Resettable for CrcScountReg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_CURSEC_REG3 (rw) register accessor: Channel 3 current sector register contains the sector number which causes CRC fail-ure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_cursec_reg3`]
module"]
# [doc (alias = "CRC_CURSEC_REG3")]
pub type CrcCursecReg3 = crate :: Reg < crc_cursec_reg3 :: CrcCursecReg3Spec > ; # [doc = "Channel 3 current sector register contains the sector number which causes CRC fail-ure"]
pub mod crc_cursec_reg3 { # [doc = "Register `CRC_CURSEC_REG3` reader"]
pub type R = crate :: R < CrcCursecReg3Spec > ; # [doc = "Register `CRC_CURSEC_REG3` writer"]
pub type W = crate :: W < CrcCursecReg3Spec > ; # [doc = "Field `NU43` reader - 15:0\\]
Reserved"]
pub type Nu43R = crate :: FieldReader < u16 > ; # [doc = "Field `NU43` writer - 15:0\\]
Reserved"]
pub type Nu43W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
pub fn nu43 (& self) -> Nu43R { Nu43R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu43 (& mut self) -> Nu43W < CrcCursecReg3Spec > { Nu43W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcCursecReg3Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 3 current sector register contains the sector number which causes CRC fail-ure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCursecReg3Spec ; impl crate :: RegisterSpec for CrcCursecReg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_cursec_reg3::R`](R) reader structure"]
impl crate :: Readable for CrcCursecReg3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_cursec_reg3::W`](W) writer structure"]
impl crate :: Writable for CrcCursecReg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CURSEC_REG3 to value 0"]
impl crate :: Resettable for CrcCursecReg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_WDTOPLD3 (rw) register accessor: Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_wdtopld3`]
module"]
# [doc (alias = "CRC_WDTOPLD3")]
pub type CrcWdtopld3 = crate :: Reg < crc_wdtopld3 :: CrcWdtopld3Spec > ; # [doc = "Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
pub mod crc_wdtopld3 { # [doc = "Register `CRC_WDTOPLD3` reader"]
pub type R = crate :: R < CrcWdtopld3Spec > ; # [doc = "Register `CRC_WDTOPLD3` writer"]
pub type W = crate :: W < CrcWdtopld3Spec > ; # [doc = "Field `NU44` reader - 23:0\\]
Reserved"]
pub type Nu44R = crate :: FieldReader < u32 > ; # [doc = "Field `NU44` writer - 23:0\\]
Reserved"]
pub type Nu44W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
pub fn nu44 (& self) -> Nu44R { Nu44R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu44 (& mut self) -> Nu44W < CrcWdtopld3Spec > { Nu44W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcWdtopld3Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcWdtopld3Spec ; impl crate :: RegisterSpec for CrcWdtopld3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_wdtopld3::R`](R) reader structure"]
impl crate :: Readable for CrcWdtopld3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_wdtopld3::W`](W) writer structure"]
impl crate :: Writable for CrcWdtopld3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_WDTOPLD3 to value 0"]
impl crate :: Resettable for CrcWdtopld3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_BCTOPLD3 (rw) register accessor: Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_bctopld3`]
module"]
# [doc (alias = "CRC_BCTOPLD3")]
pub type CrcBctopld3 = crate :: Reg < crc_bctopld3 :: CrcBctopld3Spec > ; # [doc = "Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"]
pub mod crc_bctopld3 { # [doc = "Register `CRC_BCTOPLD3` reader"]
pub type R = crate :: R < CrcBctopld3Spec > ; # [doc = "Register `CRC_BCTOPLD3` writer"]
pub type W = crate :: W < CrcBctopld3Spec > ; # [doc = "Field `NU45` reader - 23:0\\]
Reserved"]
pub type Nu45R = crate :: FieldReader < u32 > ; # [doc = "Field `NU45` writer - 23:0\\]
Reserved"]
pub type Nu45W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
pub fn nu45 (& self) -> Nu45R { Nu45R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu45 (& mut self) -> Nu45W < CrcBctopld3Spec > { Nu45W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcBctopld3Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcBctopld3Spec ; impl crate :: RegisterSpec for CrcBctopld3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_bctopld3::R`](R) reader structure"]
impl crate :: Readable for CrcBctopld3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_bctopld3::W`](W) writer structure"]
impl crate :: Writable for CrcBctopld3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_BCTOPLD3 to value 0"]
impl crate :: Resettable for CrcBctopld3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGL3 (rw) register accessor: Channel 3 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregl3`]
module"]
# [doc (alias = "PSA_SIGREGL3")]
pub type PsaSigregl3 = crate :: Reg < psa_sigregl3 :: PsaSigregl3Spec > ; # [doc = "Channel 3 PSA signature low register"]
pub mod psa_sigregl3 { # [doc = "Register `PSA_SIGREGL3` reader"]
pub type R = crate :: R < PsaSigregl3Spec > ; # [doc = "Register `PSA_SIGREGL3` writer"]
pub type W = crate :: W < PsaSigregl3Spec > ; # [doc = "Field `NU46` reader - 31:0\\]
Reserved"]
pub type Nu46R = crate :: FieldReader < u32 > ; # [doc = "Field `NU46` writer - 31:0\\]
Reserved"]
pub type Nu46W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu46 (& self) -> Nu46R { Nu46R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu46 (& mut self) -> Nu46W < PsaSigregl3Spec > { Nu46W :: new (self , 0) } } # [doc = "Channel 3 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregl3Spec ; impl crate :: RegisterSpec for PsaSigregl3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregl3::R`](R) reader structure"]
impl crate :: Readable for PsaSigregl3Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregl3::W`](W) writer structure"]
impl crate :: Writable for PsaSigregl3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGL3 to value 0"]
impl crate :: Resettable for PsaSigregl3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGH3 (rw) register accessor: Channel 3 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregh3`]
module"]
# [doc (alias = "PSA_SIGREGH3")]
pub type PsaSigregh3 = crate :: Reg < psa_sigregh3 :: PsaSigregh3Spec > ; # [doc = "Channel 3 PSA signature high register"]
pub mod psa_sigregh3 { # [doc = "Register `PSA_SIGREGH3` reader"]
pub type R = crate :: R < PsaSigregh3Spec > ; # [doc = "Register `PSA_SIGREGH3` writer"]
pub type W = crate :: W < PsaSigregh3Spec > ; # [doc = "Field `NU47` reader - 31:0\\]
Reserved"]
pub type Nu47R = crate :: FieldReader < u32 > ; # [doc = "Field `NU47` writer - 31:0\\]
Reserved"]
pub type Nu47W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu47 (& self) -> Nu47R { Nu47R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu47 (& mut self) -> Nu47W < PsaSigregh3Spec > { Nu47W :: new (self , 0) } } # [doc = "Channel 3 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregh3Spec ; impl crate :: RegisterSpec for PsaSigregh3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregh3::R`](R) reader structure"]
impl crate :: Readable for PsaSigregh3Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregh3::W`](W) writer structure"]
impl crate :: Writable for PsaSigregh3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGH3 to value 0"]
impl crate :: Resettable for PsaSigregh3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGL3 (rw) register accessor: Channel 3 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regl3`]
module"]
# [doc (alias = "CRC_REGL3")]
pub type CrcRegl3 = crate :: Reg < crc_regl3 :: CrcRegl3Spec > ; # [doc = "Channel 3 CRC value low register"]
pub mod crc_regl3 { # [doc = "Register `CRC_REGL3` reader"]
pub type R = crate :: R < CrcRegl3Spec > ; # [doc = "Register `CRC_REGL3` writer"]
pub type W = crate :: W < CrcRegl3Spec > ; # [doc = "Field `NU48` reader - 31:0\\]
Reserved"]
pub type Nu48R = crate :: FieldReader < u32 > ; # [doc = "Field `NU48` writer - 31:0\\]
Reserved"]
pub type Nu48W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu48 (& self) -> Nu48R { Nu48R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu48 (& mut self) -> Nu48W < CrcRegl3Spec > { Nu48W :: new (self , 0) } } # [doc = "Channel 3 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegl3Spec ; impl crate :: RegisterSpec for CrcRegl3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regl3::R`](R) reader structure"]
impl crate :: Readable for CrcRegl3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regl3::W`](W) writer structure"]
impl crate :: Writable for CrcRegl3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGL3 to value 0"]
impl crate :: Resettable for CrcRegl3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGH3 (rw) register accessor: Channel 3 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regh3`]
module"]
# [doc (alias = "CRC_REGH3")]
pub type CrcRegh3 = crate :: Reg < crc_regh3 :: CrcRegh3Spec > ; # [doc = "Channel 3 CRC value high register"]
pub mod crc_regh3 { # [doc = "Register `CRC_REGH3` reader"]
pub type R = crate :: R < CrcRegh3Spec > ; # [doc = "Register `CRC_REGH3` writer"]
pub type W = crate :: W < CrcRegh3Spec > ; # [doc = "Field `NU49` reader - 31:0\\]
Reserved"]
pub type Nu49R = crate :: FieldReader < u32 > ; # [doc = "Field `NU49` writer - 31:0\\]
Reserved"]
pub type Nu49W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu49 (& self) -> Nu49R { Nu49R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu49 (& mut self) -> Nu49W < CrcRegh3Spec > { Nu49W :: new (self , 0) } } # [doc = "Channel 3 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegh3Spec ; impl crate :: RegisterSpec for CrcRegh3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regh3::R`](R) reader structure"]
impl crate :: Readable for CrcRegh3Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regh3::W`](W) writer structure"]
impl crate :: Writable for CrcRegh3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGH3 to value 0"]
impl crate :: Resettable for CrcRegh3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGL3 (rw) register accessor: Channel 3 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregl3`]
module"]
# [doc (alias = "PSA_SECSIGREGL3")]
pub type PsaSecsigregl3 = crate :: Reg < psa_secsigregl3 :: PsaSecsigregl3Spec > ; # [doc = "Channel 3 PSA sector signature low regis-ter"]
pub mod psa_secsigregl3 { # [doc = "Register `PSA_SECSIGREGL3` reader"]
pub type R = crate :: R < PsaSecsigregl3Spec > ; # [doc = "Register `PSA_SECSIGREGL3` writer"]
pub type W = crate :: W < PsaSecsigregl3Spec > ; # [doc = "Field `NU50` reader - 31:0\\]
Reserved"]
pub type Nu50R = crate :: FieldReader < u32 > ; # [doc = "Field `NU50` writer - 31:0\\]
Reserved"]
pub type Nu50W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu50 (& self) -> Nu50R { Nu50R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu50 (& mut self) -> Nu50W < PsaSecsigregl3Spec > { Nu50W :: new (self , 0) } } # [doc = "Channel 3 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregl3Spec ; impl crate :: RegisterSpec for PsaSecsigregl3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregl3::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregl3Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregl3::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregl3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGL3 to value 0"]
impl crate :: Resettable for PsaSecsigregl3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGH3 (rw) register accessor: Channel 3 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregh3`]
module"]
# [doc (alias = "PSA_SECSIGREGH3")]
pub type PsaSecsigregh3 = crate :: Reg < psa_secsigregh3 :: PsaSecsigregh3Spec > ; # [doc = "Channel 3 PSA sector signature high regis-ter"]
pub mod psa_secsigregh3 { # [doc = "Register `PSA_SECSIGREGH3` reader"]
pub type R = crate :: R < PsaSecsigregh3Spec > ; # [doc = "Register `PSA_SECSIGREGH3` writer"]
pub type W = crate :: W < PsaSecsigregh3Spec > ; # [doc = "Field `NU51` reader - 31:0\\]
Reserved"]
pub type Nu51R = crate :: FieldReader < u32 > ; # [doc = "Field `NU51` writer - 31:0\\]
Reserved"]
pub type Nu51W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu51 (& self) -> Nu51R { Nu51R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu51 (& mut self) -> Nu51W < PsaSecsigregh3Spec > { Nu51W :: new (self , 0) } } # [doc = "Channel 3 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregh3Spec ; impl crate :: RegisterSpec for PsaSecsigregh3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregh3::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregh3Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregh3::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregh3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGH3 to value 0"]
impl crate :: Resettable for PsaSecsigregh3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGL3 (rw) register accessor: Channel 3 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregl3`]
module"]
# [doc (alias = "RAW_DATAREGL3")]
pub type RawDataregl3 = crate :: Reg < raw_dataregl3 :: RawDataregl3Spec > ; # [doc = "Channel 3 un-compressed raw data low register"]
pub mod raw_dataregl3 { # [doc = "Register `RAW_DATAREGL3` reader"]
pub type R = crate :: R < RawDataregl3Spec > ; # [doc = "Register `RAW_DATAREGL3` writer"]
pub type W = crate :: W < RawDataregl3Spec > ; # [doc = "Field `NU52` reader - 31:0\\]
Reserved"]
pub type Nu52R = crate :: FieldReader < u32 > ; # [doc = "Field `NU52` writer - 31:0\\]
Reserved"]
pub type Nu52W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu52 (& self) -> Nu52R { Nu52R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu52 (& mut self) -> Nu52W < RawDataregl3Spec > { Nu52W :: new (self , 0) } } # [doc = "Channel 3 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregl3Spec ; impl crate :: RegisterSpec for RawDataregl3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregl3::R`](R) reader structure"]
impl crate :: Readable for RawDataregl3Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregl3::W`](W) writer structure"]
impl crate :: Writable for RawDataregl3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGL3 to value 0"]
impl crate :: Resettable for RawDataregl3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGH3 (rw) register accessor: Channel 3 un-compressed raw data high Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregh3`]
module"]
# [doc (alias = "RAW_DATAREGH3")]
pub type RawDataregh3 = crate :: Reg < raw_dataregh3 :: RawDataregh3Spec > ; # [doc = "Channel 3 un-compressed raw data high Register"]
pub mod raw_dataregh3 { # [doc = "Register `RAW_DATAREGH3` reader"]
pub type R = crate :: R < RawDataregh3Spec > ; # [doc = "Register `RAW_DATAREGH3` writer"]
pub type W = crate :: W < RawDataregh3Spec > ; # [doc = "Field `NU53` reader - 31:0\\]
Reserved"]
pub type Nu53R = crate :: FieldReader < u32 > ; # [doc = "Field `NU53` writer - 31:0\\]
Reserved"]
pub type Nu53W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu53 (& self) -> Nu53R { Nu53R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu53 (& mut self) -> Nu53W < RawDataregh3Spec > { Nu53W :: new (self , 0) } } # [doc = "Channel 3 un-compressed raw data high Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregh3Spec ; impl crate :: RegisterSpec for RawDataregh3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregh3::R`](R) reader structure"]
impl crate :: Readable for RawDataregh3Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregh3::W`](W) writer structure"]
impl crate :: Writable for RawDataregh3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGH3 to value 0"]
impl crate :: Resettable for RawDataregh3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_PCOUNT_REG4 (rw) register accessor: Channel 4 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_pcount_reg4`]
module"]
# [doc (alias = "CRC_PCOUNT_REG4")]
pub type CrcPcountReg4 = crate :: Reg < crc_pcount_reg4 :: CrcPcountReg4Spec > ; # [doc = "Channel 4 preload register for the pattern count"]
pub mod crc_pcount_reg4 { # [doc = "Register `CRC_PCOUNT_REG4` reader"]
pub type R = crate :: R < CrcPcountReg4Spec > ; # [doc = "Register `CRC_PCOUNT_REG4` writer"]
pub type W = crate :: W < CrcPcountReg4Spec > ; # [doc = "Field `NU54` reader - 19:0\\]
Reserved"]
pub type Nu54R = crate :: FieldReader < u32 > ; # [doc = "Field `NU54` writer - 19:0\\]
Reserved"]
pub type Nu54W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `Reserved1` reader - 31:20\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:20\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
Reserved"]
# [inline (always)]
pub fn nu54 (& self) -> Nu54R { Nu54R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu54 (& mut self) -> Nu54W < CrcPcountReg4Spec > { Nu54W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcPcountReg4Spec > { Reserved1W :: new (self , 20) } } # [doc = "Channel 4 preload register for the pattern count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_pcount_reg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_pcount_reg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcPcountReg4Spec ; impl crate :: RegisterSpec for CrcPcountReg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_pcount_reg4::R`](R) reader structure"]
impl crate :: Readable for CrcPcountReg4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_pcount_reg4::W`](W) writer structure"]
impl crate :: Writable for CrcPcountReg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_PCOUNT_REG4 to value 0"]
impl crate :: Resettable for CrcPcountReg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_SCOUNT_REG4 (rw) register accessor: Channel 4 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_scount_reg4`]
module"]
# [doc (alias = "CRC_SCOUNT_REG4")]
pub type CrcScountReg4 = crate :: Reg < crc_scount_reg4 :: CrcScountReg4Spec > ; # [doc = "Channel 4 preload register for the sector count"]
pub mod crc_scount_reg4 { # [doc = "Register `CRC_SCOUNT_REG4` reader"]
pub type R = crate :: R < CrcScountReg4Spec > ; # [doc = "Register `CRC_SCOUNT_REG4` writer"]
pub type W = crate :: W < CrcScountReg4Spec > ; # [doc = "Field `NU55` reader - 15:0\\]
Reserved"]
pub type Nu55R = crate :: FieldReader < u16 > ; # [doc = "Field `NU55` writer - 15:0\\]
Reserved"]
pub type Nu55W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
pub fn nu55 (& self) -> Nu55R { Nu55R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu55 (& mut self) -> Nu55W < CrcScountReg4Spec > { Nu55W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcScountReg4Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 4 preload register for the sector count\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_scount_reg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_scount_reg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcScountReg4Spec ; impl crate :: RegisterSpec for CrcScountReg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_scount_reg4::R`](R) reader structure"]
impl crate :: Readable for CrcScountReg4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_scount_reg4::W`](W) writer structure"]
impl crate :: Writable for CrcScountReg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_SCOUNT_REG4 to value 0"]
impl crate :: Resettable for CrcScountReg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_CURSEC_REG4 (rw) register accessor: Channel 4 current sector register contains the sector number which causes CRC fail-ure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_cursec_reg4`]
module"]
# [doc (alias = "CRC_CURSEC_REG4")]
pub type CrcCursecReg4 = crate :: Reg < crc_cursec_reg4 :: CrcCursecReg4Spec > ; # [doc = "Channel 4 current sector register contains the sector number which causes CRC fail-ure"]
pub mod crc_cursec_reg4 { # [doc = "Register `CRC_CURSEC_REG4` reader"]
pub type R = crate :: R < CrcCursecReg4Spec > ; # [doc = "Register `CRC_CURSEC_REG4` writer"]
pub type W = crate :: W < CrcCursecReg4Spec > ; # [doc = "Field `NU56` reader - 15:0\\]
Reserved"]
pub type Nu56R = crate :: FieldReader < u16 > ; # [doc = "Field `NU56` writer - 15:0\\]
Reserved"]
pub type Nu56W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `Reserved1` reader - 31:16\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:16\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
pub fn nu56 (& self) -> Nu56R { Nu56R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu56 (& mut self) -> Nu56W < CrcCursecReg4Spec > { Nu56W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcCursecReg4Spec > { Reserved1W :: new (self , 16) } } # [doc = "Channel 4 current sector register contains the sector number which causes CRC fail-ure\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_cursec_reg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_cursec_reg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcCursecReg4Spec ; impl crate :: RegisterSpec for CrcCursecReg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_cursec_reg4::R`](R) reader structure"]
impl crate :: Readable for CrcCursecReg4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_cursec_reg4::W`](W) writer structure"]
impl crate :: Writable for CrcCursecReg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_CURSEC_REG4 to value 0"]
impl crate :: Resettable for CrcCursecReg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_WDTOPLD4 (rw) register accessor: Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_wdtopld4`]
module"]
# [doc (alias = "CRC_WDTOPLD4")]
pub type CrcWdtopld4 = crate :: Reg < crc_wdtopld4 :: CrcWdtopld4Spec > ; # [doc = "Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"]
pub mod crc_wdtopld4 { # [doc = "Register `CRC_WDTOPLD4` reader"]
pub type R = crate :: R < CrcWdtopld4Spec > ; # [doc = "Register `CRC_WDTOPLD4` writer"]
pub type W = crate :: W < CrcWdtopld4Spec > ; # [doc = "Field `NU57` reader - 23:0\\]
Reserved"]
pub type Nu57R = crate :: FieldReader < u32 > ; # [doc = "Field `NU57` writer - 23:0\\]
Reserved"]
pub type Nu57W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
pub fn nu57 (& self) -> Nu57R { Nu57R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu57 (& mut self) -> Nu57W < CrcWdtopld4Spec > { Nu57W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcWdtopld4Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcWdtopld4Spec ; impl crate :: RegisterSpec for CrcWdtopld4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_wdtopld4::R`](R) reader structure"]
impl crate :: Readable for CrcWdtopld4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_wdtopld4::W`](W) writer structure"]
impl crate :: Writable for CrcWdtopld4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_WDTOPLD4 to value 0"]
impl crate :: Resettable for CrcWdtopld4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_BCTOPLD4 (rw) register accessor: Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_bctopld4`]
module"]
# [doc (alias = "CRC_BCTOPLD4")]
pub type CrcBctopld4 = crate :: Reg < crc_bctopld4 :: CrcBctopld4Spec > ; # [doc = "Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"]
pub mod crc_bctopld4 { # [doc = "Register `CRC_BCTOPLD4` reader"]
pub type R = crate :: R < CrcBctopld4Spec > ; # [doc = "Register `CRC_BCTOPLD4` writer"]
pub type W = crate :: W < CrcBctopld4Spec > ; # [doc = "Field `NU58` reader - 23:0\\]
Reserved"]
pub type Nu58R = crate :: FieldReader < u32 > ; # [doc = "Field `NU58` writer - 23:0\\]
Reserved"]
pub type Nu58W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
pub fn nu58 (& self) -> Nu58R { Nu58R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu58 (& mut self) -> Nu58W < CrcBctopld4Spec > { Nu58W :: new (self , 0) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CrcBctopld4Spec > { Reserved1W :: new (self , 24) } } # [doc = "Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_bctopld4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_bctopld4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcBctopld4Spec ; impl crate :: RegisterSpec for CrcBctopld4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_bctopld4::R`](R) reader structure"]
impl crate :: Readable for CrcBctopld4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_bctopld4::W`](W) writer structure"]
impl crate :: Writable for CrcBctopld4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_BCTOPLD4 to value 0"]
impl crate :: Resettable for CrcBctopld4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGL4 (rw) register accessor: Channel 4 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregl4`]
module"]
# [doc (alias = "PSA_SIGREGL4")]
pub type PsaSigregl4 = crate :: Reg < psa_sigregl4 :: PsaSigregl4Spec > ; # [doc = "Channel 4 PSA signature low register"]
pub mod psa_sigregl4 { # [doc = "Register `PSA_SIGREGL4` reader"]
pub type R = crate :: R < PsaSigregl4Spec > ; # [doc = "Register `PSA_SIGREGL4` writer"]
pub type W = crate :: W < PsaSigregl4Spec > ; # [doc = "Field `NU59` reader - 31:0\\]
Reserved"]
pub type Nu59R = crate :: FieldReader < u32 > ; # [doc = "Field `NU59` writer - 31:0\\]
Reserved"]
pub type Nu59W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu59 (& self) -> Nu59R { Nu59R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu59 (& mut self) -> Nu59W < PsaSigregl4Spec > { Nu59W :: new (self , 0) } } # [doc = "Channel 4 PSA signature low register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregl4Spec ; impl crate :: RegisterSpec for PsaSigregl4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregl4::R`](R) reader structure"]
impl crate :: Readable for PsaSigregl4Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregl4::W`](W) writer structure"]
impl crate :: Writable for PsaSigregl4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGL4 to value 0"]
impl crate :: Resettable for PsaSigregl4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SIGREGH4 (rw) register accessor: Channel 4 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_sigregh4`]
module"]
# [doc (alias = "PSA_SIGREGH4")]
pub type PsaSigregh4 = crate :: Reg < psa_sigregh4 :: PsaSigregh4Spec > ; # [doc = "Channel 4 PSA signature high register"]
pub mod psa_sigregh4 { # [doc = "Register `PSA_SIGREGH4` reader"]
pub type R = crate :: R < PsaSigregh4Spec > ; # [doc = "Register `PSA_SIGREGH4` writer"]
pub type W = crate :: W < PsaSigregh4Spec > ; # [doc = "Field `NU60` reader - 31:0\\]
Reserved"]
pub type Nu60R = crate :: FieldReader < u32 > ; # [doc = "Field `NU60` writer - 31:0\\]
Reserved"]
pub type Nu60W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu60 (& self) -> Nu60R { Nu60R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu60 (& mut self) -> Nu60W < PsaSigregh4Spec > { Nu60W :: new (self , 0) } } # [doc = "Channel 4 PSA signature high register\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_sigregh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_sigregh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSigregh4Spec ; impl crate :: RegisterSpec for PsaSigregh4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_sigregh4::R`](R) reader structure"]
impl crate :: Readable for PsaSigregh4Spec { } # [doc = "`write(|w| ..)` method takes [`psa_sigregh4::W`](W) writer structure"]
impl crate :: Writable for PsaSigregh4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SIGREGH4 to value 0"]
impl crate :: Resettable for PsaSigregh4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGL4 (rw) register accessor: Channel 4 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regl4`]
module"]
# [doc (alias = "CRC_REGL4")]
pub type CrcRegl4 = crate :: Reg < crc_regl4 :: CrcRegl4Spec > ; # [doc = "Channel 4 CRC value low register"]
pub mod crc_regl4 { # [doc = "Register `CRC_REGL4` reader"]
pub type R = crate :: R < CrcRegl4Spec > ; # [doc = "Register `CRC_REGL4` writer"]
pub type W = crate :: W < CrcRegl4Spec > ; # [doc = "Field `NU61` reader - 31:0\\]
Reserved"]
pub type Nu61R = crate :: FieldReader < u32 > ; # [doc = "Field `NU61` writer - 31:0\\]
Reserved"]
pub type Nu61W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu61 (& self) -> Nu61R { Nu61R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu61 (& mut self) -> Nu61W < CrcRegl4Spec > { Nu61W :: new (self , 0) } } # [doc = "Channel 4 CRC value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegl4Spec ; impl crate :: RegisterSpec for CrcRegl4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regl4::R`](R) reader structure"]
impl crate :: Readable for CrcRegl4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regl4::W`](W) writer structure"]
impl crate :: Writable for CrcRegl4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGL4 to value 0"]
impl crate :: Resettable for CrcRegl4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRC_REGH4 (rw) register accessor: Channel 4 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crc_regh4`]
module"]
# [doc (alias = "CRC_REGH4")]
pub type CrcRegh4 = crate :: Reg < crc_regh4 :: CrcRegh4Spec > ; # [doc = "Channel 4 CRC value high register"]
pub mod crc_regh4 { # [doc = "Register `CRC_REGH4` reader"]
pub type R = crate :: R < CrcRegh4Spec > ; # [doc = "Register `CRC_REGH4` writer"]
pub type W = crate :: W < CrcRegh4Spec > ; # [doc = "Field `NU62` reader - 31:0\\]
Reserved"]
pub type Nu62R = crate :: FieldReader < u32 > ; # [doc = "Field `NU62` writer - 31:0\\]
Reserved"]
pub type Nu62W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu62 (& self) -> Nu62R { Nu62R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu62 (& mut self) -> Nu62W < CrcRegh4Spec > { Nu62W :: new (self , 0) } } # [doc = "Channel 4 CRC value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_regh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_regh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcRegh4Spec ; impl crate :: RegisterSpec for CrcRegh4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`crc_regh4::R`](R) reader structure"]
impl crate :: Readable for CrcRegh4Spec { } # [doc = "`write(|w| ..)` method takes [`crc_regh4::W`](W) writer structure"]
impl crate :: Writable for CrcRegh4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRC_REGH4 to value 0"]
impl crate :: Resettable for CrcRegh4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGL4 (rw) register accessor: Channel 4 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregl4`]
module"]
# [doc (alias = "PSA_SECSIGREGL4")]
pub type PsaSecsigregl4 = crate :: Reg < psa_secsigregl4 :: PsaSecsigregl4Spec > ; # [doc = "Channel 4 PSA sector signature low regis-ter"]
pub mod psa_secsigregl4 { # [doc = "Register `PSA_SECSIGREGL4` reader"]
pub type R = crate :: R < PsaSecsigregl4Spec > ; # [doc = "Register `PSA_SECSIGREGL4` writer"]
pub type W = crate :: W < PsaSecsigregl4Spec > ; # [doc = "Field `NU63` reader - 31:0\\]
Reserved"]
pub type Nu63R = crate :: FieldReader < u32 > ; # [doc = "Field `NU63` writer - 31:0\\]
Reserved"]
pub type Nu63W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu63 (& self) -> Nu63R { Nu63R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu63 (& mut self) -> Nu63W < PsaSecsigregl4Spec > { Nu63W :: new (self , 0) } } # [doc = "Channel 4 PSA sector signature low regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregl4Spec ; impl crate :: RegisterSpec for PsaSecsigregl4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregl4::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregl4Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregl4::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregl4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGL4 to value 0"]
impl crate :: Resettable for PsaSecsigregl4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSA_SECSIGREGH4 (rw) register accessor: Channel 4 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psa_secsigregh4`]
module"]
# [doc (alias = "PSA_SECSIGREGH4")]
pub type PsaSecsigregh4 = crate :: Reg < psa_secsigregh4 :: PsaSecsigregh4Spec > ; # [doc = "Channel 4 PSA sector signature high regis-ter"]
pub mod psa_secsigregh4 { # [doc = "Register `PSA_SECSIGREGH4` reader"]
pub type R = crate :: R < PsaSecsigregh4Spec > ; # [doc = "Register `PSA_SECSIGREGH4` writer"]
pub type W = crate :: W < PsaSecsigregh4Spec > ; # [doc = "Field `NU64` reader - 31:0\\]
Reserved"]
pub type Nu64R = crate :: FieldReader < u32 > ; # [doc = "Field `NU64` writer - 31:0\\]
Reserved"]
pub type Nu64W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu64 (& self) -> Nu64R { Nu64R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu64 (& mut self) -> Nu64W < PsaSecsigregh4Spec > { Nu64W :: new (self , 0) } } # [doc = "Channel 4 PSA sector signature high regis-ter\n\nYou can [`read`](crate::Reg::read) this register and get [`psa_secsigregh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psa_secsigregh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsaSecsigregh4Spec ; impl crate :: RegisterSpec for PsaSecsigregh4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`psa_secsigregh4::R`](R) reader structure"]
impl crate :: Readable for PsaSecsigregh4Spec { } # [doc = "`write(|w| ..)` method takes [`psa_secsigregh4::W`](W) writer structure"]
impl crate :: Writable for PsaSecsigregh4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSA_SECSIGREGH4 to value 0"]
impl crate :: Resettable for PsaSecsigregh4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGL4 (rw) register accessor: Channel 4 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregl4`]
module"]
# [doc (alias = "RAW_DATAREGL4")]
pub type RawDataregl4 = crate :: Reg < raw_dataregl4 :: RawDataregl4Spec > ; # [doc = "Channel 4 un-compressed raw data low register"]
pub mod raw_dataregl4 { # [doc = "Register `RAW_DATAREGL4` reader"]
pub type R = crate :: R < RawDataregl4Spec > ; # [doc = "Register `RAW_DATAREGL4` writer"]
pub type W = crate :: W < RawDataregl4Spec > ; # [doc = "Field `NU65` reader - 31:0\\]
Reserved"]
pub type Nu65R = crate :: FieldReader < u32 > ; # [doc = "Field `NU65` writer - 31:0\\]
Reserved"]
pub type Nu65W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu65 (& self) -> Nu65R { Nu65R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu65 (& mut self) -> Nu65W < RawDataregl4Spec > { Nu65W :: new (self , 0) } } # [doc = "Channel 4 un-compressed raw data low register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregl4Spec ; impl crate :: RegisterSpec for RawDataregl4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregl4::R`](R) reader structure"]
impl crate :: Readable for RawDataregl4Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregl4::W`](W) writer structure"]
impl crate :: Writable for RawDataregl4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGL4 to value 0"]
impl crate :: Resettable for RawDataregl4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RAW_DATAREGH4 (rw) register accessor: Channel 4 un-compressed raw data high Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_dataregh4`]
module"]
# [doc (alias = "RAW_DATAREGH4")]
pub type RawDataregh4 = crate :: Reg < raw_dataregh4 :: RawDataregh4Spec > ; # [doc = "Channel 4 un-compressed raw data high Register"]
pub mod raw_dataregh4 { # [doc = "Register `RAW_DATAREGH4` reader"]
pub type R = crate :: R < RawDataregh4Spec > ; # [doc = "Register `RAW_DATAREGH4` writer"]
pub type W = crate :: W < RawDataregh4Spec > ; # [doc = "Field `NU66` reader - 31:0\\]
Reserved"]
pub type Nu66R = crate :: FieldReader < u32 > ; # [doc = "Field `NU66` writer - 31:0\\]
Reserved"]
pub type Nu66W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn nu66 (& self) -> Nu66R { Nu66R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu66 (& mut self) -> Nu66W < RawDataregh4Spec > { Nu66W :: new (self , 0) } } # [doc = "Channel 4 un-compressed raw data high Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_dataregh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_dataregh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawDataregh4Spec ; impl crate :: RegisterSpec for RawDataregh4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`raw_dataregh4::R`](R) reader structure"]
impl crate :: Readable for RawDataregh4Spec { } # [doc = "`write(|w| ..)` method takes [`raw_dataregh4::W`](W) writer structure"]
impl crate :: Writable for RawDataregh4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RAW_DATAREGH4 to value 0"]
impl crate :: Resettable for RawDataregh4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MCRC_BUS_SEL (rw) register accessor: Disables either or all tracing of data buses\n\nYou can [`read`](crate::Reg::read) this register and get [`mcrc_bus_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcrc_bus_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcrc_bus_sel`]
module"]
# [doc (alias = "MCRC_BUS_SEL")]
pub type McrcBusSel = crate :: Reg < mcrc_bus_sel :: McrcBusSelSpec > ; # [doc = "Disables either or all tracing of data buses"]
pub mod mcrc_bus_sel { # [doc = "Register `MCRC_BUS_SEL` reader"]
pub type R = crate :: R < McrcBusSelSpec > ; # [doc = "Register `MCRC_BUS_SEL` writer"]
pub type W = crate :: W < McrcBusSelSpec > ; # [doc = "Field `ITCMEn` reader - 0:0\\]
ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled"]
pub type ItcmenR = crate :: BitReader ; # [doc = "Field `ITCMEn` writer - 0:0\\]
ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled"]
pub type ItcmenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DTCMEn` reader - 1:1\\]
DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled"]
pub type DtcmenR = crate :: BitReader ; # [doc = "Field `DTCMEn` writer - 1:1\\]
DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled"]
pub type DtcmenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MEn` reader - 2:2\\]
MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled"]
pub type MenR = crate :: BitReader ; # [doc = "Field `MEn` writer - 2:2\\]
MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled"]
pub type MenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU67` reader - 31:3\\]
Reserved"]
pub type Nu67R = crate :: FieldReader < u32 > ; # [doc = "Field `NU67` writer - 31:3\\]
Reserved"]
pub type Nu67W < 'a , REG > = crate :: FieldWriter < 'a , REG , 29 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled"]
# [inline (always)]
pub fn itcmen (& self) -> ItcmenR { ItcmenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled"]
# [inline (always)]
pub fn dtcmen (& self) -> DtcmenR { DtcmenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled"]
# [inline (always)]
pub fn men (& self) -> MenR { MenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:31 - 31:3\\]
Reserved"]
# [inline (always)]
pub fn nu67 (& self) -> Nu67R { Nu67R :: new ((self . bits >> 3) & 0x1fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled"]
# [inline (always)]
# [must_use]
pub fn itcmen (& mut self) -> ItcmenW < McrcBusSelSpec > { ItcmenW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled"]
# [inline (always)]
# [must_use]
pub fn dtcmen (& mut self) -> DtcmenW < McrcBusSelSpec > { DtcmenW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled"]
# [inline (always)]
# [must_use]
pub fn men (& mut self) -> MenW < McrcBusSelSpec > { MenW :: new (self , 2) } # [doc = "Bits 3:31 - 31:3\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu67 (& mut self) -> Nu67W < McrcBusSelSpec > { Nu67W :: new (self , 3) } } # [doc = "Disables either or all tracing of data buses\n\nYou can [`read`](crate::Reg::read) this register and get [`mcrc_bus_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcrc_bus_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct McrcBusSelSpec ; impl crate :: RegisterSpec for McrcBusSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`mcrc_bus_sel::R`](R) reader structure"]
impl crate :: Readable for McrcBusSelSpec { } # [doc = "`write(|w| ..)` method takes [`mcrc_bus_sel::W`](W) writer structure"]
impl crate :: Writable for McrcBusSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MCRC_BUS_SEL to value 0"]
impl crate :: Resettable for McrcBusSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MCRC_RESERVED (rw) register accessor: 0x144 to 0x1FF is reserved area.\n\nYou can [`read`](crate::Reg::read) this register and get [`mcrc_reserved::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcrc_reserved::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcrc_reserved`]
module"]
# [doc (alias = "MCRC_RESERVED")]
pub type McrcReserved = crate :: Reg < mcrc_reserved :: McrcReservedSpec > ; # [doc = "0x144 to 0x1FF is reserved area."]
pub mod mcrc_reserved { # [doc = "Register `MCRC_RESERVED` reader"]
pub type R = crate :: R < McrcReservedSpec > ; # [doc = "Register `MCRC_RESERVED` writer"]
pub type W = crate :: W < McrcReservedSpec > ; # [doc = "Field `NU68` reader - 31:0\\]
0x144 to 0x1FF is reserved area."]
pub type Nu68R = crate :: FieldReader < u32 > ; # [doc = "Field `NU68` writer - 31:0\\]
0x144 to 0x1FF is reserved area."]
pub type Nu68W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
0x144 to 0x1FF is reserved area."]
# [inline (always)]
pub fn nu68 (& self) -> Nu68R { Nu68R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
0x144 to 0x1FF is reserved area."]
# [inline (always)]
# [must_use]
pub fn nu68 (& mut self) -> Nu68W < McrcReservedSpec > { Nu68W :: new (self , 0) } } # [doc = "0x144 to 0x1FF is reserved area.\n\nYou can [`read`](crate::Reg::read) this register and get [`mcrc_reserved::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcrc_reserved::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct McrcReservedSpec ; impl crate :: RegisterSpec for McrcReservedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`mcrc_reserved::R`](R) reader structure"]
impl crate :: Readable for McrcReservedSpec { } # [doc = "`write(|w| ..)` method takes [`mcrc_reserved::W`](W) writer structure"]
impl crate :: Writable for McrcReservedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MCRC_RESERVED to value 0"]
impl crate :: Resettable for McrcReservedSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "HWA_CFG"]
pub struct HwaCfg { _marker : PhantomData < * const () > } unsafe impl Send for HwaCfg { } impl HwaCfg { # [doc = r"Pointer to the register block"]
pub const PTR : * const hwa_cfg :: RegisterBlock = 0x5501_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const hwa_cfg :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for HwaCfg { type Target = hwa_cfg :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for HwaCfg { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("HwaCfg") . finish () } } # [doc = "HWA_CFG"]
pub mod hwa_cfg { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { hwaccreg1 : Hwaccreg1 , hwaccreg2 : Hwaccreg2 , hwaccreg3 : Hwaccreg3 , hwaccreg4 : Hwaccreg4 , hwaccreg5 : Hwaccreg5 , hwaccreg6 : Hwaccreg6 , hwaccreg7 : Hwaccreg7 , hwaccreg8 : Hwaccreg8 , hwaccreg11 : Hwaccreg11 , hwaccreg12 : Hwaccreg12 , hwaccreg13 : Hwaccreg13 , hwaccreg14 : Hwaccreg14 , hwaccreg15 : Hwaccreg15 , cfar_det_thr : CfarDetThr , max1value : Max1value , max1index : Max1index , isum1lsb : Isum1lsb , isum1msb : Isum1msb , qsum1lsb : Qsum1lsb , qsum1msb : Qsum1msb , max2value : Max2value , max2index : Max2index , isum2lsb : Isum2lsb , isum2msb : Isum2msb , qsum2lsb : Qsum2lsb , qsum2msb : Qsum2msb , max3value : Max3value , max3index : Max3index , isum3lsb : Isum3lsb , isum3msb : Isum3msb , qsum3lsb : Qsum3lsb , qsum3msb : Qsum3msb , max4value : Max4value , max4index : Max4index , isum4lsb : Isum4lsb , isum4msb : Isum4msb , qsum4lsb : Qsum4lsb , qsum4msb : Qsum4msb , cfartest : Cfartest , rdstatus : Rdstatus , sigdmach1done : Sigdmach1done , sigdmach2done : Sigdmach2done , sigdmach3done : Sigdmach3done , sigdmach4done : Sigdmach4done , sigdmach5done : Sigdmach5done , sigdmach6done : Sigdmach6done , sigdmach7done : Sigdmach7done , sigdmach8done : Sigdmach8done , sigdmach9done : Sigdmach9done , sigdmach10done : Sigdmach10done , sigdmach11done : Sigdmach11done , sigdmach12done : Sigdmach12done , sigdmach13done : Sigdmach13done , sigdmach14done : Sigdmach14done , sigdmach15done : Sigdmach15done , sigdmach16done : Sigdmach16done , memaccesserr : Memaccesserr , fftclip : Fftclip , fftpeakcnt : Fftpeakcnt , hwaccreg1rd : Hwaccreg1rd , hwaccreg2rd : Hwaccreg2rd , hwaccreg3rd : Hwaccreg3rd , cmp_ege_k0123 : CmpEgeK0123 , cmp_ege_k4567 : CmpEgeK4567 , hwa_safety_enable : HwaSafetyEnable , meminit : Meminit , meminitdone : Meminitdone , hwa_safety_win_ram_err_loc : HwaSafetyWinRamErrLoc , hwa_safety_param_ram_err_loc : HwaSafetyParamRamErrLoc , hwa_safety_iping_err_loc : HwaSafetyIpingErrLoc , hwa_safety_ipong_err_loc : HwaSafetyIpongErrLoc , hwa_safety_oping_err_loc : HwaSafetyOpingErrLoc , hwa_safety_opong_err_loc : HwaSafetyOpongErrLoc , fftintmemwrdata : Fftintmemwrdata , fftintmemrddata : Fftintmemrddata , hwaccreg16 : Hwaccreg16 , dcest1i_sw : Dcest1iSw , dcest2i_sw : Dcest2iSw , dcest3i_sw : Dcest3iSw , dcest4i_sw : Dcest4iSw , dcest5i_sw : Dcest5iSw , dcest6i_sw : Dcest6iSw , dcest1i : Dcest1i , dcest2i : Dcest2i , dcest3i : Dcest3i , dcest4i : Dcest4i , dcest5i : Dcest5i , dcest6i : Dcest6i , dc_acc1i_lsb : DcAcc1iLsb , dc_acc1i_msb : DcAcc1iMsb , dc_acc2i_lsb : DcAcc2iLsb , dc_acc2i_msb : DcAcc2iMsb , dc_acc3i_lsb : DcAcc3iLsb , dc_acc3i_msb : DcAcc3iMsb , dc_acc4i_lsb : DcAcc4iLsb , dc_acc4i_msb : DcAcc4iMsb , dc_acc5i_lsb : DcAcc5iLsb , dc_acc5i_msb : DcAcc5iMsb , dc_acc6i_lsb : DcAcc6iLsb , dc_acc6i_msb : DcAcc6iMsb , dcest1q_sw : Dcest1qSw , dcest2q_sw : Dcest2qSw , dcest3q_sw : Dcest3qSw , dcest4q_sw : Dcest4qSw , dcest5q_sw : Dcest5qSw , dcest6q_sw : Dcest6qSw , dcest1q : Dcest1q , dcest2q : Dcest2q , dcest3q : Dcest3q , dcest4q : Dcest4q , dcest5q : Dcest5q , dcest6q : Dcest6q , dc_acc1q_lsb : DcAcc1qLsb , dc_acc1q_msb : DcAcc1qMsb , dc_acc2q_lsb : DcAcc2qLsb , dc_acc2q_msb : DcAcc2qMsb , dc_acc3q_lsb : DcAcc3qLsb , dc_acc3q_msb : DcAcc3qMsb , dc_acc4q_lsb : DcAcc4qLsb , dc_acc4q_msb : DcAcc4qMsb , dc_acc5q_lsb : DcAcc5qLsb , dc_acc5q_msb : DcAcc5qMsb , dc_acc6q_lsb : DcAcc6qLsb , dc_acc6q_msb : DcAcc6qMsb , dcacc1_clip : Dcacc1Clip , dcacc2_clip : Dcacc2Clip , dcacc3_clip : Dcacc3Clip , dcacc4_clip : Dcacc4Clip , dcacc5_clip : Dcacc5Clip , dcacc6_clip : Dcacc6Clip , dcest1_clip : Dcest1Clip , dcest2_clip : Dcest2Clip , dcest3_clip : Dcest3Clip , dcest4_clip : Dcest4Clip , dcest5_clip : Dcest5Clip , dcest6_clip : Dcest6Clip , dcsub1_clip : Dcsub1Clip , dcsub2_clip : Dcsub2Clip , dcsub3_clip : Dcsub3Clip , dcsub4_clip : Dcsub4Clip , dcsub5_clip : Dcsub5Clip , dcsub6_clip : Dcsub6Clip , dcest_shift : DcestShift , dcest_scale : DcestScale , intf_mag_scale : IntfMagScale , intf_mag_shift : IntfMagShift , intf_magdiff_scale : IntfMagdiffScale , intf_magdiff_shift : IntfMagdiffShift , intf_frame_zerocount : IntfFrameZerocount , intf_chirp_zerocount : IntfChirpZerocount , intf_magthresh1_sw : IntfMagthresh1Sw , intf_magthresh2_sw : IntfMagthresh2Sw , intf_magthresh3_sw : IntfMagthresh3Sw , intf_magthresh4_sw : IntfMagthresh4Sw , intf_magthresh5_sw : IntfMagthresh5Sw , intf_magthresh6_sw : IntfMagthresh6Sw , intf_magdiffthresh1_sw : IntfMagdiffthresh1Sw , intf_magdiffthresh2_sw : IntfMagdiffthresh2Sw , intf_magdiffthresh3_sw : IntfMagdiffthresh3Sw , intf_magdiffthresh4_sw : IntfMagdiffthresh4Sw , intf_magdiffthresh5_sw : IntfMagdiffthresh5Sw , intf_magdiffthresh6_sw : IntfMagdiffthresh6Sw , intf_magacc1_lsb : IntfMagacc1Lsb , intf_magacc1_msb : IntfMagacc1Msb , intf_magacc2_lsb : IntfMagacc2Lsb , intf_magacc2_msb : IntfMagacc2Msb , intf_magacc3_lsb : IntfMagacc3Lsb , intf_magacc3_msb : IntfMagacc3Msb , intf_magacc4_lsb : IntfMagacc4Lsb , intf_magacc4_msb : IntfMagacc4Msb , intf_magacc5_lsb : IntfMagacc5Lsb , intf_magacc5_msb : IntfMagacc5Msb , intf_magacc6_lsb : IntfMagacc6Lsb , intf_magacc6_msb : IntfMagacc6Msb , intf_magdiffacc1_lsb : IntfMagdiffacc1Lsb , intf_magdiffacc1_msb : IntfMagdiffacc1Msb , intf_magdiffacc2_lsb : IntfMagdiffacc2Lsb , intf_magdiffacc2_msb : IntfMagdiffacc2Msb , intf_magdiffacc3_lsb : IntfMagdiffacc3Lsb , intf_magdiffacc3_msb : IntfMagdiffacc3Msb , intf_magdiffacc4_lsb : IntfMagdiffacc4Lsb , intf_magdiffacc4_msb : IntfMagdiffacc4Msb , intf_magdiffacc5_lsb : IntfMagdiffacc5Lsb , intf_magdiffacc5_msb : IntfMagdiffacc5Msb , intf_magdiffacc6_lsb : IntfMagdiffacc6Lsb , intf_magdiffacc6_msb : IntfMagdiffacc6Msb , intf_magacc1_clip : IntfMagacc1Clip , intf_magacc2_clip : IntfMagacc2Clip , intf_magacc3_clip : IntfMagacc3Clip , intf_magacc4_clip : IntfMagacc4Clip , intf_magacc5_clip : IntfMagacc5Clip , intf_magacc6_clip : IntfMagacc6Clip , intf_magdiffacc1_clip : IntfMagdiffacc1Clip , intf_magdiffacc2_clip : IntfMagdiffacc2Clip , intf_magdiffacc3_clip : IntfMagdiffacc3Clip , intf_magdiffacc4_clip : IntfMagdiffacc4Clip , intf_magdiffacc5_clip : IntfMagdiffacc5Clip , intf_magdiffacc6_clip : IntfMagdiffacc6Clip , intf_magthresh1 : IntfMagthresh1 , intf_magthresh2 : IntfMagthresh2 , intf_magthresh3 : IntfMagthresh3 , intf_magthresh4 : IntfMagthresh4 , intf_magthresh5 : IntfMagthresh5 , intf_magthresh6 : IntfMagthresh6 , intf_magdiffthresh1 : IntfMagdiffthresh1 , intf_magdiffthresh2 : IntfMagdiffthresh2 , intf_magdiffthresh3 : IntfMagdiffthresh3 , intf_magdiffthresh4 : IntfMagdiffthresh4 , intf_magdiffthresh5 : IntfMagdiffthresh5 , intf_magdiffthresh6 : IntfMagdiffthresh6 , intf_summagthresh : IntfSummagthresh , intf_summagdiffthresh : IntfSummagdiffthresh , intf_summagthresh_clip : IntfSummagthreshClip , intf_summagdiffthresh_clip : IntfSummagdiffthreshClip , cmultscale1i : Cmultscale1i , cmultscale2i : Cmultscale2i , cmultscale3i : Cmultscale3i , cmultscale4i : Cmultscale4i , cmultscale5i : Cmultscale5i , cmultscale6i : Cmultscale6i , cmultscale1q : Cmultscale1q , cmultscale2q : Cmultscale2q , cmultscale3q : Cmultscale3q , cmultscale4q : Cmultscale4q , cmultscale5q : Cmultscale5q , cmultscale6q : Cmultscale6q , clr_misc_clip : ClrMiscClip , fftintmemaddr : Fftintmemaddr , intf_stats_reset_sw : IntfStatsResetSw , dcest_reset_sw : DcestResetSw , ip_op_formatter_clip_status : IpOpFormatterClipStatus , intf_magthresh1_clip : IntfMagthresh1Clip , intf_magthresh2_clip : IntfMagthresh2Clip , intf_magthresh3_clip : IntfMagthresh3Clip , intf_magthresh4_clip : IntfMagthresh4Clip , intf_magthresh5_clip : IntfMagthresh5Clip , intf_magthresh6_clip : IntfMagthresh6Clip , intf_magdiffthresh1_clip : IntfMagdiffthresh1Clip , intf_magdiffthresh2_clip : IntfMagdiffthresh2Clip , intf_magdiffthresh3_clip : IntfMagdiffthresh3Clip , intf_magdiffthresh4_clip : IntfMagdiffthresh4Clip , intf_magdiffthresh5_clip : IntfMagdiffthresh5Clip , intf_magdiffthresh6_clip : IntfMagdiffthresh6Clip , hwa_safety_err_mask : HwaSafetyErrMask , hwa_safety_err_status : HwaSafetyErrStatus , hwa_safety_err_status_raw : HwaSafetyErrStatusRaw , } impl RegisterBlock { # [doc = "0x00 - HWACCREG1"]
# [inline (always)]
pub const fn hwaccreg1 (& self) -> & Hwaccreg1 { & self . hwaccreg1 } # [doc = "0x04 - HWACCREG2"]
# [inline (always)]
pub const fn hwaccreg2 (& self) -> & Hwaccreg2 { & self . hwaccreg2 } # [doc = "0x08 - HWACCREG3"]
# [inline (always)]
pub const fn hwaccreg3 (& self) -> & Hwaccreg3 { & self . hwaccreg3 } # [doc = "0x0c - HWACCREG4"]
# [inline (always)]
pub const fn hwaccreg4 (& self) -> & Hwaccreg4 { & self . hwaccreg4 } # [doc = "0x10 - HWACCREG5"]
# [inline (always)]
pub const fn hwaccreg5 (& self) -> & Hwaccreg5 { & self . hwaccreg5 } # [doc = "0x14 - HWACCREG6"]
# [inline (always)]
pub const fn hwaccreg6 (& self) -> & Hwaccreg6 { & self . hwaccreg6 } # [doc = "0x18 - HWACCREG7"]
# [inline (always)]
pub const fn hwaccreg7 (& self) -> & Hwaccreg7 { & self . hwaccreg7 } # [doc = "0x1c - HWACCREG8"]
# [inline (always)]
pub const fn hwaccreg8 (& self) -> & Hwaccreg8 { & self . hwaccreg8 } # [doc = "0x20 - HWACCREG11"]
# [inline (always)]
pub const fn hwaccreg11 (& self) -> & Hwaccreg11 { & self . hwaccreg11 } # [doc = "0x24 - HWACCREG12"]
# [inline (always)]
pub const fn hwaccreg12 (& self) -> & Hwaccreg12 { & self . hwaccreg12 } # [doc = "0x28 - HWACCREG13"]
# [inline (always)]
pub const fn hwaccreg13 (& self) -> & Hwaccreg13 { & self . hwaccreg13 } # [doc = "0x2c - HWACCREG14"]
# [inline (always)]
pub const fn hwaccreg14 (& self) -> & Hwaccreg14 { & self . hwaccreg14 } # [doc = "0x30 - HWACCREG15"]
# [inline (always)]
pub const fn hwaccreg15 (& self) -> & Hwaccreg15 { & self . hwaccreg15 } # [doc = "0x34 - CFAR_DET_THR"]
# [inline (always)]
pub const fn cfar_det_thr (& self) -> & CfarDetThr { & self . cfar_det_thr } # [doc = "0x38 - MAX1VALUE"]
# [inline (always)]
pub const fn max1value (& self) -> & Max1value { & self . max1value } # [doc = "0x3c - MAX1INDEX"]
# [inline (always)]
pub const fn max1index (& self) -> & Max1index { & self . max1index } # [doc = "0x40 - ISUM1LSB"]
# [inline (always)]
pub const fn isum1lsb (& self) -> & Isum1lsb { & self . isum1lsb } # [doc = "0x44 - ISUM1MSB"]
# [inline (always)]
pub const fn isum1msb (& self) -> & Isum1msb { & self . isum1msb } # [doc = "0x48 - QSUM1LSB"]
# [inline (always)]
pub const fn qsum1lsb (& self) -> & Qsum1lsb { & self . qsum1lsb } # [doc = "0x4c - QSUM1MSB"]
# [inline (always)]
pub const fn qsum1msb (& self) -> & Qsum1msb { & self . qsum1msb } # [doc = "0x50 - MAX2VALUE"]
# [inline (always)]
pub const fn max2value (& self) -> & Max2value { & self . max2value } # [doc = "0x54 - MAX2INDEX"]
# [inline (always)]
pub const fn max2index (& self) -> & Max2index { & self . max2index } # [doc = "0x58 - ISUM2LSB"]
# [inline (always)]
pub const fn isum2lsb (& self) -> & Isum2lsb { & self . isum2lsb } # [doc = "0x5c - ISUM2MSB"]
# [inline (always)]
pub const fn isum2msb (& self) -> & Isum2msb { & self . isum2msb } # [doc = "0x60 - QSUM2LSB"]
# [inline (always)]
pub const fn qsum2lsb (& self) -> & Qsum2lsb { & self . qsum2lsb } # [doc = "0x64 - QSUM2MSB"]
# [inline (always)]
pub const fn qsum2msb (& self) -> & Qsum2msb { & self . qsum2msb } # [doc = "0x68 - MAX3VALUE"]
# [inline (always)]
pub const fn max3value (& self) -> & Max3value { & self . max3value } # [doc = "0x6c - MAX3INDEX"]
# [inline (always)]
pub const fn max3index (& self) -> & Max3index { & self . max3index } # [doc = "0x70 - ISUM3LSB"]
# [inline (always)]
pub const fn isum3lsb (& self) -> & Isum3lsb { & self . isum3lsb } # [doc = "0x74 - ISUM3MSB"]
# [inline (always)]
pub const fn isum3msb (& self) -> & Isum3msb { & self . isum3msb } # [doc = "0x78 - QSUM3LSB"]
# [inline (always)]
pub const fn qsum3lsb (& self) -> & Qsum3lsb { & self . qsum3lsb } # [doc = "0x7c - QSUM3MSB"]
# [inline (always)]
pub const fn qsum3msb (& self) -> & Qsum3msb { & self . qsum3msb } # [doc = "0x80 - MAX4VALUE"]
# [inline (always)]
pub const fn max4value (& self) -> & Max4value { & self . max4value } # [doc = "0x84 - MAX4INDEX"]
# [inline (always)]
pub const fn max4index (& self) -> & Max4index { & self . max4index } # [doc = "0x88 - ISUM4LSB"]
# [inline (always)]
pub const fn isum4lsb (& self) -> & Isum4lsb { & self . isum4lsb } # [doc = "0x8c - ISUM4MSB"]
# [inline (always)]
pub const fn isum4msb (& self) -> & Isum4msb { & self . isum4msb } # [doc = "0x90 - QSUM4LSB"]
# [inline (always)]
pub const fn qsum4lsb (& self) -> & Qsum4lsb { & self . qsum4lsb } # [doc = "0x94 - QSUM4MSB"]
# [inline (always)]
pub const fn qsum4msb (& self) -> & Qsum4msb { & self . qsum4msb } # [doc = "0x98 - CFARTEST"]
# [inline (always)]
pub const fn cfartest (& self) -> & Cfartest { & self . cfartest } # [doc = "0x9c - RDSTATUS"]
# [inline (always)]
pub const fn rdstatus (& self) -> & Rdstatus { & self . rdstatus } # [doc = "0xa0 - SIGDMACH1DONE"]
# [inline (always)]
pub const fn sigdmach1done (& self) -> & Sigdmach1done { & self . sigdmach1done } # [doc = "0xa4 - SIGDMACH2DONE"]
# [inline (always)]
pub const fn sigdmach2done (& self) -> & Sigdmach2done { & self . sigdmach2done } # [doc = "0xa8 - SIGDMACH3DONE"]
# [inline (always)]
pub const fn sigdmach3done (& self) -> & Sigdmach3done { & self . sigdmach3done } # [doc = "0xac - SIGDMACH4DONE"]
# [inline (always)]
pub const fn sigdmach4done (& self) -> & Sigdmach4done { & self . sigdmach4done } # [doc = "0xb0 - SIGDMACH5DONE"]
# [inline (always)]
pub const fn sigdmach5done (& self) -> & Sigdmach5done { & self . sigdmach5done } # [doc = "0xb4 - SIGDMACH6DONE"]
# [inline (always)]
pub const fn sigdmach6done (& self) -> & Sigdmach6done { & self . sigdmach6done } # [doc = "0xb8 - SIGDMACH7DONE"]
# [inline (always)]
pub const fn sigdmach7done (& self) -> & Sigdmach7done { & self . sigdmach7done } # [doc = "0xbc - SIGDMACH8DONE"]
# [inline (always)]
pub const fn sigdmach8done (& self) -> & Sigdmach8done { & self . sigdmach8done } # [doc = "0xc0 - SIGDMACH9DONE"]
# [inline (always)]
pub const fn sigdmach9done (& self) -> & Sigdmach9done { & self . sigdmach9done } # [doc = "0xc4 - SIGDMACH10DONE"]
# [inline (always)]
pub const fn sigdmach10done (& self) -> & Sigdmach10done { & self . sigdmach10done } # [doc = "0xc8 - SIGDMACH11DONE"]
# [inline (always)]
pub const fn sigdmach11done (& self) -> & Sigdmach11done { & self . sigdmach11done } # [doc = "0xcc - SIGDMACH12DONE"]
# [inline (always)]
pub const fn sigdmach12done (& self) -> & Sigdmach12done { & self . sigdmach12done } # [doc = "0xd0 - SIGDMACH13DONE"]
# [inline (always)]
pub const fn sigdmach13done (& self) -> & Sigdmach13done { & self . sigdmach13done } # [doc = "0xd4 - SIGDMACH14DONE"]
# [inline (always)]
pub const fn sigdmach14done (& self) -> & Sigdmach14done { & self . sigdmach14done } # [doc = "0xd8 - SIGDMACH15DONE"]
# [inline (always)]
pub const fn sigdmach15done (& self) -> & Sigdmach15done { & self . sigdmach15done } # [doc = "0xdc - SIGDMACH16DONE"]
# [inline (always)]
pub const fn sigdmach16done (& self) -> & Sigdmach16done { & self . sigdmach16done } # [doc = "0xe0 - MEMACCESSERR"]
# [inline (always)]
pub const fn memaccesserr (& self) -> & Memaccesserr { & self . memaccesserr } # [doc = "0xe4 - FFTCLIP"]
# [inline (always)]
pub const fn fftclip (& self) -> & Fftclip { & self . fftclip } # [doc = "0xe8 - FFTPEAKCNT"]
# [inline (always)]
pub const fn fftpeakcnt (& self) -> & Fftpeakcnt { & self . fftpeakcnt } # [doc = "0xec - HWACCREG1RD"]
# [inline (always)]
pub const fn hwaccreg1rd (& self) -> & Hwaccreg1rd { & self . hwaccreg1rd } # [doc = "0xf0 - HWACCREG2RD"]
# [inline (always)]
pub const fn hwaccreg2rd (& self) -> & Hwaccreg2rd { & self . hwaccreg2rd } # [doc = "0xf4 - HWACCREG3RD"]
# [inline (always)]
pub const fn hwaccreg3rd (& self) -> & Hwaccreg3rd { & self . hwaccreg3rd } # [doc = "0xf8 - CMP_EGE_K0123"]
# [inline (always)]
pub const fn cmp_ege_k0123 (& self) -> & CmpEgeK0123 { & self . cmp_ege_k0123 } # [doc = "0xfc - CMP_EGE_K4567"]
# [inline (always)]
pub const fn cmp_ege_k4567 (& self) -> & CmpEgeK4567 { & self . cmp_ege_k4567 } # [doc = "0x100 - HWA_SAFETY_ENABLE"]
# [inline (always)]
pub const fn hwa_safety_enable (& self) -> & HwaSafetyEnable { & self . hwa_safety_enable } # [doc = "0x104 - MEMINIT"]
# [inline (always)]
pub const fn meminit (& self) -> & Meminit { & self . meminit } # [doc = "0x108 - MEMINITDONE"]
# [inline (always)]
pub const fn meminitdone (& self) -> & Meminitdone { & self . meminitdone } # [doc = "0x10c - HWA_SAFETY_WIN_RAM_ERR_LOC"]
# [inline (always)]
pub const fn hwa_safety_win_ram_err_loc (& self) -> & HwaSafetyWinRamErrLoc { & self . hwa_safety_win_ram_err_loc } # [doc = "0x110 - HWA_SAFETY_PARAM_RAM_ERR_LOC"]
# [inline (always)]
pub const fn hwa_safety_param_ram_err_loc (& self) -> & HwaSafetyParamRamErrLoc { & self . hwa_safety_param_ram_err_loc } # [doc = "0x114 - HWA_SAFETY_IPING_ERR_LOC"]
# [inline (always)]
pub const fn hwa_safety_iping_err_loc (& self) -> & HwaSafetyIpingErrLoc { & self . hwa_safety_iping_err_loc } # [doc = "0x118 - HWA_SAFETY_IPONG_ERR_LOC"]
# [inline (always)]
pub const fn hwa_safety_ipong_err_loc (& self) -> & HwaSafetyIpongErrLoc { & self . hwa_safety_ipong_err_loc } # [doc = "0x11c - HWA_SAFETY_OPING_ERR_LOC"]
# [inline (always)]
pub const fn hwa_safety_oping_err_loc (& self) -> & HwaSafetyOpingErrLoc { & self . hwa_safety_oping_err_loc } # [doc = "0x120 - HWA_SAFETY_OPONG_ERR_LOC"]
# [inline (always)]
pub const fn hwa_safety_opong_err_loc (& self) -> & HwaSafetyOpongErrLoc { & self . hwa_safety_opong_err_loc } # [doc = "0x124 - FFTINTMEMWRDATA"]
# [inline (always)]
pub const fn fftintmemwrdata (& self) -> & Fftintmemwrdata { & self . fftintmemwrdata } # [doc = "0x128 - FFTINTMEMRDDATA"]
# [inline (always)]
pub const fn fftintmemrddata (& self) -> & Fftintmemrddata { & self . fftintmemrddata } # [doc = "0x12c - HWACCREG16"]
# [inline (always)]
pub const fn hwaccreg16 (& self) -> & Hwaccreg16 { & self . hwaccreg16 } # [doc = "0x130 - DCEST1I_SW"]
# [inline (always)]
pub const fn dcest1i_sw (& self) -> & Dcest1iSw { & self . dcest1i_sw } # [doc = "0x134 - DCEST2I_SW"]
# [inline (always)]
pub const fn dcest2i_sw (& self) -> & Dcest2iSw { & self . dcest2i_sw } # [doc = "0x138 - DCEST3I_SW"]
# [inline (always)]
pub const fn dcest3i_sw (& self) -> & Dcest3iSw { & self . dcest3i_sw } # [doc = "0x13c - DCEST4I_SW"]
# [inline (always)]
pub const fn dcest4i_sw (& self) -> & Dcest4iSw { & self . dcest4i_sw } # [doc = "0x140 - DCEST5I_SW"]
# [inline (always)]
pub const fn dcest5i_sw (& self) -> & Dcest5iSw { & self . dcest5i_sw } # [doc = "0x144 - DCEST6I_SW"]
# [inline (always)]
pub const fn dcest6i_sw (& self) -> & Dcest6iSw { & self . dcest6i_sw } # [doc = "0x148 - DCEST1I"]
# [inline (always)]
pub const fn dcest1i (& self) -> & Dcest1i { & self . dcest1i } # [doc = "0x14c - DCEST2I"]
# [inline (always)]
pub const fn dcest2i (& self) -> & Dcest2i { & self . dcest2i } # [doc = "0x150 - DCEST3I"]
# [inline (always)]
pub const fn dcest3i (& self) -> & Dcest3i { & self . dcest3i } # [doc = "0x154 - DCEST4I"]
# [inline (always)]
pub const fn dcest4i (& self) -> & Dcest4i { & self . dcest4i } # [doc = "0x158 - DCEST5I"]
# [inline (always)]
pub const fn dcest5i (& self) -> & Dcest5i { & self . dcest5i } # [doc = "0x15c - DCEST6I"]
# [inline (always)]
pub const fn dcest6i (& self) -> & Dcest6i { & self . dcest6i } # [doc = "0x160 - DC_ACC1I_LSB"]
# [inline (always)]
pub const fn dc_acc1i_lsb (& self) -> & DcAcc1iLsb { & self . dc_acc1i_lsb } # [doc = "0x164 - DC_ACC1I_MSB"]
# [inline (always)]
pub const fn dc_acc1i_msb (& self) -> & DcAcc1iMsb { & self . dc_acc1i_msb } # [doc = "0x168 - DC_ACC2I_LSB"]
# [inline (always)]
pub const fn dc_acc2i_lsb (& self) -> & DcAcc2iLsb { & self . dc_acc2i_lsb } # [doc = "0x16c - DC_ACC2I_MSB"]
# [inline (always)]
pub const fn dc_acc2i_msb (& self) -> & DcAcc2iMsb { & self . dc_acc2i_msb } # [doc = "0x170 - DC_ACC3I_LSB"]
# [inline (always)]
pub const fn dc_acc3i_lsb (& self) -> & DcAcc3iLsb { & self . dc_acc3i_lsb } # [doc = "0x174 - DC_ACC3I_MSB"]
# [inline (always)]
pub const fn dc_acc3i_msb (& self) -> & DcAcc3iMsb { & self . dc_acc3i_msb } # [doc = "0x178 - DC_ACC4I_LSB"]
# [inline (always)]
pub const fn dc_acc4i_lsb (& self) -> & DcAcc4iLsb { & self . dc_acc4i_lsb } # [doc = "0x17c - DC_ACC4I_MSB"]
# [inline (always)]
pub const fn dc_acc4i_msb (& self) -> & DcAcc4iMsb { & self . dc_acc4i_msb } # [doc = "0x180 - DC_ACC5I_LSB"]
# [inline (always)]
pub const fn dc_acc5i_lsb (& self) -> & DcAcc5iLsb { & self . dc_acc5i_lsb } # [doc = "0x184 - DC_ACC5I_MSB"]
# [inline (always)]
pub const fn dc_acc5i_msb (& self) -> & DcAcc5iMsb { & self . dc_acc5i_msb } # [doc = "0x188 - DC_ACC6I_LSB"]
# [inline (always)]
pub const fn dc_acc6i_lsb (& self) -> & DcAcc6iLsb { & self . dc_acc6i_lsb } # [doc = "0x18c - DC_ACC6I_MSB"]
# [inline (always)]
pub const fn dc_acc6i_msb (& self) -> & DcAcc6iMsb { & self . dc_acc6i_msb } # [doc = "0x190 - DCEST1Q_SW"]
# [inline (always)]
pub const fn dcest1q_sw (& self) -> & Dcest1qSw { & self . dcest1q_sw } # [doc = "0x194 - DCEST2Q_SW"]
# [inline (always)]
pub const fn dcest2q_sw (& self) -> & Dcest2qSw { & self . dcest2q_sw } # [doc = "0x198 - DCEST3Q_SW"]
# [inline (always)]
pub const fn dcest3q_sw (& self) -> & Dcest3qSw { & self . dcest3q_sw } # [doc = "0x19c - DCEST4Q_SW"]
# [inline (always)]
pub const fn dcest4q_sw (& self) -> & Dcest4qSw { & self . dcest4q_sw } # [doc = "0x1a0 - DCEST5Q_SW"]
# [inline (always)]
pub const fn dcest5q_sw (& self) -> & Dcest5qSw { & self . dcest5q_sw } # [doc = "0x1a4 - DCEST6Q_SW"]
# [inline (always)]
pub const fn dcest6q_sw (& self) -> & Dcest6qSw { & self . dcest6q_sw } # [doc = "0x1a8 - DCEST1Q"]
# [inline (always)]
pub const fn dcest1q (& self) -> & Dcest1q { & self . dcest1q } # [doc = "0x1ac - DCEST2Q"]
# [inline (always)]
pub const fn dcest2q (& self) -> & Dcest2q { & self . dcest2q } # [doc = "0x1b0 - DCEST3Q"]
# [inline (always)]
pub const fn dcest3q (& self) -> & Dcest3q { & self . dcest3q } # [doc = "0x1b4 - DCEST4Q"]
# [inline (always)]
pub const fn dcest4q (& self) -> & Dcest4q { & self . dcest4q } # [doc = "0x1b8 - DCEST5Q"]
# [inline (always)]
pub const fn dcest5q (& self) -> & Dcest5q { & self . dcest5q } # [doc = "0x1bc - DCEST6Q"]
# [inline (always)]
pub const fn dcest6q (& self) -> & Dcest6q { & self . dcest6q } # [doc = "0x1c0 - DC_ACC1Q_LSB"]
# [inline (always)]
pub const fn dc_acc1q_lsb (& self) -> & DcAcc1qLsb { & self . dc_acc1q_lsb } # [doc = "0x1c4 - DC_ACC1Q_MSB"]
# [inline (always)]
pub const fn dc_acc1q_msb (& self) -> & DcAcc1qMsb { & self . dc_acc1q_msb } # [doc = "0x1c8 - DC_ACC2Q_LSB"]
# [inline (always)]
pub const fn dc_acc2q_lsb (& self) -> & DcAcc2qLsb { & self . dc_acc2q_lsb } # [doc = "0x1cc - DC_ACC2Q_MSB"]
# [inline (always)]
pub const fn dc_acc2q_msb (& self) -> & DcAcc2qMsb { & self . dc_acc2q_msb } # [doc = "0x1d0 - DC_ACC3Q_LSB"]
# [inline (always)]
pub const fn dc_acc3q_lsb (& self) -> & DcAcc3qLsb { & self . dc_acc3q_lsb } # [doc = "0x1d4 - DC_ACC3Q_MSB"]
# [inline (always)]
pub const fn dc_acc3q_msb (& self) -> & DcAcc3qMsb { & self . dc_acc3q_msb } # [doc = "0x1d8 - DC_ACC4Q_LSB"]
# [inline (always)]
pub const fn dc_acc4q_lsb (& self) -> & DcAcc4qLsb { & self . dc_acc4q_lsb } # [doc = "0x1dc - DC_ACC4Q_MSB"]
# [inline (always)]
pub const fn dc_acc4q_msb (& self) -> & DcAcc4qMsb { & self . dc_acc4q_msb } # [doc = "0x1e0 - DC_ACC5Q_LSB"]
# [inline (always)]
pub const fn dc_acc5q_lsb (& self) -> & DcAcc5qLsb { & self . dc_acc5q_lsb } # [doc = "0x1e4 - DC_ACC5Q_MSB"]
# [inline (always)]
pub const fn dc_acc5q_msb (& self) -> & DcAcc5qMsb { & self . dc_acc5q_msb } # [doc = "0x1e8 - DC_ACC6Q_LSB"]
# [inline (always)]
pub const fn dc_acc6q_lsb (& self) -> & DcAcc6qLsb { & self . dc_acc6q_lsb } # [doc = "0x1ec - DC_ACC6Q_MSB"]
# [inline (always)]
pub const fn dc_acc6q_msb (& self) -> & DcAcc6qMsb { & self . dc_acc6q_msb } # [doc = "0x1f0 - DCACC1_CLIP"]
# [inline (always)]
pub const fn dcacc1_clip (& self) -> & Dcacc1Clip { & self . dcacc1_clip } # [doc = "0x1f4 - DCACC2_CLIP"]
# [inline (always)]
pub const fn dcacc2_clip (& self) -> & Dcacc2Clip { & self . dcacc2_clip } # [doc = "0x1f8 - DCACC3_CLIP"]
# [inline (always)]
pub const fn dcacc3_clip (& self) -> & Dcacc3Clip { & self . dcacc3_clip } # [doc = "0x1fc - DCACC4_CLIP"]
# [inline (always)]
pub const fn dcacc4_clip (& self) -> & Dcacc4Clip { & self . dcacc4_clip } # [doc = "0x200 - DCACC5_CLIP"]
# [inline (always)]
pub const fn dcacc5_clip (& self) -> & Dcacc5Clip { & self . dcacc5_clip } # [doc = "0x204 - DCACC6_CLIP"]
# [inline (always)]
pub const fn dcacc6_clip (& self) -> & Dcacc6Clip { & self . dcacc6_clip } # [doc = "0x208 - DCEST1_CLIP"]
# [inline (always)]
pub const fn dcest1_clip (& self) -> & Dcest1Clip { & self . dcest1_clip } # [doc = "0x20c - DCEST2_CLIP"]
# [inline (always)]
pub const fn dcest2_clip (& self) -> & Dcest2Clip { & self . dcest2_clip } # [doc = "0x210 - DCEST3_CLIP"]
# [inline (always)]
pub const fn dcest3_clip (& self) -> & Dcest3Clip { & self . dcest3_clip } # [doc = "0x214 - DCEST4_CLIP"]
# [inline (always)]
pub const fn dcest4_clip (& self) -> & Dcest4Clip { & self . dcest4_clip } # [doc = "0x218 - DCEST5_CLIP"]
# [inline (always)]
pub const fn dcest5_clip (& self) -> & Dcest5Clip { & self . dcest5_clip } # [doc = "0x21c - DCEST6_CLIP"]
# [inline (always)]
pub const fn dcest6_clip (& self) -> & Dcest6Clip { & self . dcest6_clip } # [doc = "0x220 - DCSUB1_CLIP"]
# [inline (always)]
pub const fn dcsub1_clip (& self) -> & Dcsub1Clip { & self . dcsub1_clip } # [doc = "0x224 - DCSUB2_CLIP"]
# [inline (always)]
pub const fn dcsub2_clip (& self) -> & Dcsub2Clip { & self . dcsub2_clip } # [doc = "0x228 - DCSUB3_CLIP"]
# [inline (always)]
pub const fn dcsub3_clip (& self) -> & Dcsub3Clip { & self . dcsub3_clip } # [doc = "0x22c - DCSUB4_CLIP"]
# [inline (always)]
pub const fn dcsub4_clip (& self) -> & Dcsub4Clip { & self . dcsub4_clip } # [doc = "0x230 - DCSUB5_CLIP"]
# [inline (always)]
pub const fn dcsub5_clip (& self) -> & Dcsub5Clip { & self . dcsub5_clip } # [doc = "0x234 - DCSUB6_CLIP"]
# [inline (always)]
pub const fn dcsub6_clip (& self) -> & Dcsub6Clip { & self . dcsub6_clip } # [doc = "0x238 - DCEST_SHIFT"]
# [inline (always)]
pub const fn dcest_shift (& self) -> & DcestShift { & self . dcest_shift } # [doc = "0x23c - DCEST_SCALE"]
# [inline (always)]
pub const fn dcest_scale (& self) -> & DcestScale { & self . dcest_scale } # [doc = "0x240 - INTF_MAG_SCALE"]
# [inline (always)]
pub const fn intf_mag_scale (& self) -> & IntfMagScale { & self . intf_mag_scale } # [doc = "0x244 - INTF_MAG_SHIFT"]
# [inline (always)]
pub const fn intf_mag_shift (& self) -> & IntfMagShift { & self . intf_mag_shift } # [doc = "0x248 - INTF_MAGDIFF_SCALE"]
# [inline (always)]
pub const fn intf_magdiff_scale (& self) -> & IntfMagdiffScale { & self . intf_magdiff_scale } # [doc = "0x24c - INTF_MAGDIFF_SHIFT"]
# [inline (always)]
pub const fn intf_magdiff_shift (& self) -> & IntfMagdiffShift { & self . intf_magdiff_shift } # [doc = "0x250 - INTF_FRAME_ZEROCOUNT"]
# [inline (always)]
pub const fn intf_frame_zerocount (& self) -> & IntfFrameZerocount { & self . intf_frame_zerocount } # [doc = "0x254 - INTF_CHIRP_ZEROCOUNT"]
# [inline (always)]
pub const fn intf_chirp_zerocount (& self) -> & IntfChirpZerocount { & self . intf_chirp_zerocount } # [doc = "0x258 - INTF_MAGTHRESH1_SW"]
# [inline (always)]
pub const fn intf_magthresh1_sw (& self) -> & IntfMagthresh1Sw { & self . intf_magthresh1_sw } # [doc = "0x25c - INTF_MAGTHRESH2_SW"]
# [inline (always)]
pub const fn intf_magthresh2_sw (& self) -> & IntfMagthresh2Sw { & self . intf_magthresh2_sw } # [doc = "0x260 - INTF_MAGTHRESH3_SW"]
# [inline (always)]
pub const fn intf_magthresh3_sw (& self) -> & IntfMagthresh3Sw { & self . intf_magthresh3_sw } # [doc = "0x264 - INTF_MAGTHRESH4_SW"]
# [inline (always)]
pub const fn intf_magthresh4_sw (& self) -> & IntfMagthresh4Sw { & self . intf_magthresh4_sw } # [doc = "0x268 - INTF_MAGTHRESH5_SW"]
# [inline (always)]
pub const fn intf_magthresh5_sw (& self) -> & IntfMagthresh5Sw { & self . intf_magthresh5_sw } # [doc = "0x26c - INTF_MAGTHRESH6_SW"]
# [inline (always)]
pub const fn intf_magthresh6_sw (& self) -> & IntfMagthresh6Sw { & self . intf_magthresh6_sw } # [doc = "0x270 - INTF_MAGDIFFTHRESH1_SW"]
# [inline (always)]
pub const fn intf_magdiffthresh1_sw (& self) -> & IntfMagdiffthresh1Sw { & self . intf_magdiffthresh1_sw } # [doc = "0x274 - INTF_MAGDIFFTHRESH2_SW"]
# [inline (always)]
pub const fn intf_magdiffthresh2_sw (& self) -> & IntfMagdiffthresh2Sw { & self . intf_magdiffthresh2_sw } # [doc = "0x278 - INTF_MAGDIFFTHRESH3_SW"]
# [inline (always)]
pub const fn intf_magdiffthresh3_sw (& self) -> & IntfMagdiffthresh3Sw { & self . intf_magdiffthresh3_sw } # [doc = "0x27c - INTF_MAGDIFFTHRESH4_SW"]
# [inline (always)]
pub const fn intf_magdiffthresh4_sw (& self) -> & IntfMagdiffthresh4Sw { & self . intf_magdiffthresh4_sw } # [doc = "0x280 - INTF_MAGDIFFTHRESH5_SW"]
# [inline (always)]
pub const fn intf_magdiffthresh5_sw (& self) -> & IntfMagdiffthresh5Sw { & self . intf_magdiffthresh5_sw } # [doc = "0x284 - INTF_MAGDIFFTHRESH6_SW"]
# [inline (always)]
pub const fn intf_magdiffthresh6_sw (& self) -> & IntfMagdiffthresh6Sw { & self . intf_magdiffthresh6_sw } # [doc = "0x288 - INTF_MAGACC1_LSB"]
# [inline (always)]
pub const fn intf_magacc1_lsb (& self) -> & IntfMagacc1Lsb { & self . intf_magacc1_lsb } # [doc = "0x28c - INTF_MAGACC1_MSB"]
# [inline (always)]
pub const fn intf_magacc1_msb (& self) -> & IntfMagacc1Msb { & self . intf_magacc1_msb } # [doc = "0x290 - INTF_MAGACC2_LSB"]
# [inline (always)]
pub const fn intf_magacc2_lsb (& self) -> & IntfMagacc2Lsb { & self . intf_magacc2_lsb } # [doc = "0x294 - INTF_MAGACC2_MSB"]
# [inline (always)]
pub const fn intf_magacc2_msb (& self) -> & IntfMagacc2Msb { & self . intf_magacc2_msb } # [doc = "0x298 - INTF_MAGACC3_LSB"]
# [inline (always)]
pub const fn intf_magacc3_lsb (& self) -> & IntfMagacc3Lsb { & self . intf_magacc3_lsb } # [doc = "0x29c - INTF_MAGACC3_MSB"]
# [inline (always)]
pub const fn intf_magacc3_msb (& self) -> & IntfMagacc3Msb { & self . intf_magacc3_msb } # [doc = "0x2a0 - INTF_MAGACC4_LSB"]
# [inline (always)]
pub const fn intf_magacc4_lsb (& self) -> & IntfMagacc4Lsb { & self . intf_magacc4_lsb } # [doc = "0x2a4 - INTF_MAGACC4_MSB"]
# [inline (always)]
pub const fn intf_magacc4_msb (& self) -> & IntfMagacc4Msb { & self . intf_magacc4_msb } # [doc = "0x2a8 - INTF_MAGACC5_LSB"]
# [inline (always)]
pub const fn intf_magacc5_lsb (& self) -> & IntfMagacc5Lsb { & self . intf_magacc5_lsb } # [doc = "0x2ac - INTF_MAGACC5_MSB"]
# [inline (always)]
pub const fn intf_magacc5_msb (& self) -> & IntfMagacc5Msb { & self . intf_magacc5_msb } # [doc = "0x2b0 - INTF_MAGACC6_LSB"]
# [inline (always)]
pub const fn intf_magacc6_lsb (& self) -> & IntfMagacc6Lsb { & self . intf_magacc6_lsb } # [doc = "0x2b4 - INTF_MAGACC6_MSB"]
# [inline (always)]
pub const fn intf_magacc6_msb (& self) -> & IntfMagacc6Msb { & self . intf_magacc6_msb } # [doc = "0x2b8 - INTF_MAGDIFFACC1_LSB"]
# [inline (always)]
pub const fn intf_magdiffacc1_lsb (& self) -> & IntfMagdiffacc1Lsb { & self . intf_magdiffacc1_lsb } # [doc = "0x2bc - INTF_MAGDIFFACC1_MSB"]
# [inline (always)]
pub const fn intf_magdiffacc1_msb (& self) -> & IntfMagdiffacc1Msb { & self . intf_magdiffacc1_msb } # [doc = "0x2c0 - INTF_MAGDIFFACC2_LSB"]
# [inline (always)]
pub const fn intf_magdiffacc2_lsb (& self) -> & IntfMagdiffacc2Lsb { & self . intf_magdiffacc2_lsb } # [doc = "0x2c4 - INTF_MAGDIFFACC2_MSB"]
# [inline (always)]
pub const fn intf_magdiffacc2_msb (& self) -> & IntfMagdiffacc2Msb { & self . intf_magdiffacc2_msb } # [doc = "0x2c8 - INTF_MAGDIFFACC3_LSB"]
# [inline (always)]
pub const fn intf_magdiffacc3_lsb (& self) -> & IntfMagdiffacc3Lsb { & self . intf_magdiffacc3_lsb } # [doc = "0x2cc - INTF_MAGDIFFACC3_MSB"]
# [inline (always)]
pub const fn intf_magdiffacc3_msb (& self) -> & IntfMagdiffacc3Msb { & self . intf_magdiffacc3_msb } # [doc = "0x2d0 - INTF_MAGDIFFACC4_LSB"]
# [inline (always)]
pub const fn intf_magdiffacc4_lsb (& self) -> & IntfMagdiffacc4Lsb { & self . intf_magdiffacc4_lsb } # [doc = "0x2d4 - INTF_MAGDIFFACC4_MSB"]
# [inline (always)]
pub const fn intf_magdiffacc4_msb (& self) -> & IntfMagdiffacc4Msb { & self . intf_magdiffacc4_msb } # [doc = "0x2d8 - INTF_MAGDIFFACC5_LSB"]
# [inline (always)]
pub const fn intf_magdiffacc5_lsb (& self) -> & IntfMagdiffacc5Lsb { & self . intf_magdiffacc5_lsb } # [doc = "0x2dc - INTF_MAGDIFFACC5_MSB"]
# [inline (always)]
pub const fn intf_magdiffacc5_msb (& self) -> & IntfMagdiffacc5Msb { & self . intf_magdiffacc5_msb } # [doc = "0x2e0 - INTF_MAGDIFFACC6_LSB"]
# [inline (always)]
pub const fn intf_magdiffacc6_lsb (& self) -> & IntfMagdiffacc6Lsb { & self . intf_magdiffacc6_lsb } # [doc = "0x2e4 - INTF_MAGDIFFACC6_MSB"]
# [inline (always)]
pub const fn intf_magdiffacc6_msb (& self) -> & IntfMagdiffacc6Msb { & self . intf_magdiffacc6_msb } # [doc = "0x2e8 - INTF_MAGACC1_CLIP"]
# [inline (always)]
pub const fn intf_magacc1_clip (& self) -> & IntfMagacc1Clip { & self . intf_magacc1_clip } # [doc = "0x2ec - INTF_MAGACC2_CLIP"]
# [inline (always)]
pub const fn intf_magacc2_clip (& self) -> & IntfMagacc2Clip { & self . intf_magacc2_clip } # [doc = "0x2f0 - INTF_MAGACC3_CLIP"]
# [inline (always)]
pub const fn intf_magacc3_clip (& self) -> & IntfMagacc3Clip { & self . intf_magacc3_clip } # [doc = "0x2f4 - INTF_MAGACC4_CLIP"]
# [inline (always)]
pub const fn intf_magacc4_clip (& self) -> & IntfMagacc4Clip { & self . intf_magacc4_clip } # [doc = "0x2f8 - INTF_MAGACC5_CLIP"]
# [inline (always)]
pub const fn intf_magacc5_clip (& self) -> & IntfMagacc5Clip { & self . intf_magacc5_clip } # [doc = "0x2fc - INTF_MAGACC6_CLIP"]
# [inline (always)]
pub const fn intf_magacc6_clip (& self) -> & IntfMagacc6Clip { & self . intf_magacc6_clip } # [doc = "0x300 - INTF_MAGDIFFACC1_CLIP"]
# [inline (always)]
pub const fn intf_magdiffacc1_clip (& self) -> & IntfMagdiffacc1Clip { & self . intf_magdiffacc1_clip } # [doc = "0x304 - INTF_MAGDIFFACC2_CLIP"]
# [inline (always)]
pub const fn intf_magdiffacc2_clip (& self) -> & IntfMagdiffacc2Clip { & self . intf_magdiffacc2_clip } # [doc = "0x308 - INTF_MAGDIFFACC3_CLIP"]
# [inline (always)]
pub const fn intf_magdiffacc3_clip (& self) -> & IntfMagdiffacc3Clip { & self . intf_magdiffacc3_clip } # [doc = "0x30c - INTF_MAGDIFFACC4_CLIP"]
# [inline (always)]
pub const fn intf_magdiffacc4_clip (& self) -> & IntfMagdiffacc4Clip { & self . intf_magdiffacc4_clip } # [doc = "0x310 - INTF_MAGDIFFACC5_CLIP"]
# [inline (always)]
pub const fn intf_magdiffacc5_clip (& self) -> & IntfMagdiffacc5Clip { & self . intf_magdiffacc5_clip } # [doc = "0x314 - INTF_MAGDIFFACC6_CLIP"]
# [inline (always)]
pub const fn intf_magdiffacc6_clip (& self) -> & IntfMagdiffacc6Clip { & self . intf_magdiffacc6_clip } # [doc = "0x318 - INTF_MAGTHRESH1"]
# [inline (always)]
pub const fn intf_magthresh1 (& self) -> & IntfMagthresh1 { & self . intf_magthresh1 } # [doc = "0x31c - INTF_MAGTHRESH2"]
# [inline (always)]
pub const fn intf_magthresh2 (& self) -> & IntfMagthresh2 { & self . intf_magthresh2 } # [doc = "0x320 - INTF_MAGTHRESH3"]
# [inline (always)]
pub const fn intf_magthresh3 (& self) -> & IntfMagthresh3 { & self . intf_magthresh3 } # [doc = "0x324 - INTF_MAGTHRESH4"]
# [inline (always)]
pub const fn intf_magthresh4 (& self) -> & IntfMagthresh4 { & self . intf_magthresh4 } # [doc = "0x328 - INTF_MAGTHRESH5"]
# [inline (always)]
pub const fn intf_magthresh5 (& self) -> & IntfMagthresh5 { & self . intf_magthresh5 } # [doc = "0x32c - INTF_MAGTHRESH6"]
# [inline (always)]
pub const fn intf_magthresh6 (& self) -> & IntfMagthresh6 { & self . intf_magthresh6 } # [doc = "0x330 - INTF_MAGDIFFTHRESH1"]
# [inline (always)]
pub const fn intf_magdiffthresh1 (& self) -> & IntfMagdiffthresh1 { & self . intf_magdiffthresh1 } # [doc = "0x334 - INTF_MAGDIFFTHRESH2"]
# [inline (always)]
pub const fn intf_magdiffthresh2 (& self) -> & IntfMagdiffthresh2 { & self . intf_magdiffthresh2 } # [doc = "0x338 - INTF_MAGDIFFTHRESH3"]
# [inline (always)]
pub const fn intf_magdiffthresh3 (& self) -> & IntfMagdiffthresh3 { & self . intf_magdiffthresh3 } # [doc = "0x33c - INTF_MAGDIFFTHRESH4"]
# [inline (always)]
pub const fn intf_magdiffthresh4 (& self) -> & IntfMagdiffthresh4 { & self . intf_magdiffthresh4 } # [doc = "0x340 - INTF_MAGDIFFTHRESH5"]
# [inline (always)]
pub const fn intf_magdiffthresh5 (& self) -> & IntfMagdiffthresh5 { & self . intf_magdiffthresh5 } # [doc = "0x344 - INTF_MAGDIFFTHRESH6"]
# [inline (always)]
pub const fn intf_magdiffthresh6 (& self) -> & IntfMagdiffthresh6 { & self . intf_magdiffthresh6 } # [doc = "0x348 - INTF_SUMMAGTHRESH"]
# [inline (always)]
pub const fn intf_summagthresh (& self) -> & IntfSummagthresh { & self . intf_summagthresh } # [doc = "0x34c - INTF_SUMMAGDIFFTHRESH"]
# [inline (always)]
pub const fn intf_summagdiffthresh (& self) -> & IntfSummagdiffthresh { & self . intf_summagdiffthresh } # [doc = "0x350 - INTF_SUMMAGTHRESH_CLIP"]
# [inline (always)]
pub const fn intf_summagthresh_clip (& self) -> & IntfSummagthreshClip { & self . intf_summagthresh_clip } # [doc = "0x354 - INTF_SUMMAGDIFFTHRESH_CLIP"]
# [inline (always)]
pub const fn intf_summagdiffthresh_clip (& self) -> & IntfSummagdiffthreshClip { & self . intf_summagdiffthresh_clip } # [doc = "0x358 - CMULTSCALE1I"]
# [inline (always)]
pub const fn cmultscale1i (& self) -> & Cmultscale1i { & self . cmultscale1i } # [doc = "0x35c - CMULTSCALE2I"]
# [inline (always)]
pub const fn cmultscale2i (& self) -> & Cmultscale2i { & self . cmultscale2i } # [doc = "0x360 - CMULTSCALE3I"]
# [inline (always)]
pub const fn cmultscale3i (& self) -> & Cmultscale3i { & self . cmultscale3i } # [doc = "0x364 - CMULTSCALE4I"]
# [inline (always)]
pub const fn cmultscale4i (& self) -> & Cmultscale4i { & self . cmultscale4i } # [doc = "0x368 - CMULTSCALE5I"]
# [inline (always)]
pub const fn cmultscale5i (& self) -> & Cmultscale5i { & self . cmultscale5i } # [doc = "0x36c - CMULTSCALE6I"]
# [inline (always)]
pub const fn cmultscale6i (& self) -> & Cmultscale6i { & self . cmultscale6i } # [doc = "0x370 - CMULTSCALE1Q"]
# [inline (always)]
pub const fn cmultscale1q (& self) -> & Cmultscale1q { & self . cmultscale1q } # [doc = "0x374 - CMULTSCALE2Q"]
# [inline (always)]
pub const fn cmultscale2q (& self) -> & Cmultscale2q { & self . cmultscale2q } # [doc = "0x378 - CMULTSCALE3Q"]
# [inline (always)]
pub const fn cmultscale3q (& self) -> & Cmultscale3q { & self . cmultscale3q } # [doc = "0x37c - CMULTSCALE4Q"]
# [inline (always)]
pub const fn cmultscale4q (& self) -> & Cmultscale4q { & self . cmultscale4q } # [doc = "0x380 - CMULTSCALE5Q"]
# [inline (always)]
pub const fn cmultscale5q (& self) -> & Cmultscale5q { & self . cmultscale5q } # [doc = "0x384 - CMULTSCALE6Q"]
# [inline (always)]
pub const fn cmultscale6q (& self) -> & Cmultscale6q { & self . cmultscale6q } # [doc = "0x388 - CLR_MISC_CLIP"]
# [inline (always)]
pub const fn clr_misc_clip (& self) -> & ClrMiscClip { & self . clr_misc_clip } # [doc = "0x38c - FFTINTMEMADDR"]
# [inline (always)]
pub const fn fftintmemaddr (& self) -> & Fftintmemaddr { & self . fftintmemaddr } # [doc = "0x390 - INTF_STATS_RESET_SW"]
# [inline (always)]
pub const fn intf_stats_reset_sw (& self) -> & IntfStatsResetSw { & self . intf_stats_reset_sw } # [doc = "0x394 - DCEST_RESET_SW"]
# [inline (always)]
pub const fn dcest_reset_sw (& self) -> & DcestResetSw { & self . dcest_reset_sw } # [doc = "0x398 - IP_OP_FORMATTER_CLIP_STATUS"]
# [inline (always)]
pub const fn ip_op_formatter_clip_status (& self) -> & IpOpFormatterClipStatus { & self . ip_op_formatter_clip_status } # [doc = "0x39c - INTF_MAGTHRESH1_CLIP"]
# [inline (always)]
pub const fn intf_magthresh1_clip (& self) -> & IntfMagthresh1Clip { & self . intf_magthresh1_clip } # [doc = "0x3a0 - INTF_MAGTHRESH2_CLIP"]
# [inline (always)]
pub const fn intf_magthresh2_clip (& self) -> & IntfMagthresh2Clip { & self . intf_magthresh2_clip } # [doc = "0x3a4 - INTF_MAGTHRESH3_CLIP"]
# [inline (always)]
pub const fn intf_magthresh3_clip (& self) -> & IntfMagthresh3Clip { & self . intf_magthresh3_clip } # [doc = "0x3a8 - INTF_MAGTHRESH4_CLIP"]
# [inline (always)]
pub const fn intf_magthresh4_clip (& self) -> & IntfMagthresh4Clip { & self . intf_magthresh4_clip } # [doc = "0x3ac - INTF_MAGTHRESH5_CLIP"]
# [inline (always)]
pub const fn intf_magthresh5_clip (& self) -> & IntfMagthresh5Clip { & self . intf_magthresh5_clip } # [doc = "0x3b0 - INTF_MAGTHRESH6_CLIP"]
# [inline (always)]
pub const fn intf_magthresh6_clip (& self) -> & IntfMagthresh6Clip { & self . intf_magthresh6_clip } # [doc = "0x3b4 - INTF_MAGDIFFTHRESH1_CLIP"]
# [inline (always)]
pub const fn intf_magdiffthresh1_clip (& self) -> & IntfMagdiffthresh1Clip { & self . intf_magdiffthresh1_clip } # [doc = "0x3b8 - INTF_MAGDIFFTHRESH2_CLIP"]
# [inline (always)]
pub const fn intf_magdiffthresh2_clip (& self) -> & IntfMagdiffthresh2Clip { & self . intf_magdiffthresh2_clip } # [doc = "0x3bc - INTF_MAGDIFFTHRESH3_CLIP"]
# [inline (always)]
pub const fn intf_magdiffthresh3_clip (& self) -> & IntfMagdiffthresh3Clip { & self . intf_magdiffthresh3_clip } # [doc = "0x3c0 - INTF_MAGDIFFTHRESH4_CLIP"]
# [inline (always)]
pub const fn intf_magdiffthresh4_clip (& self) -> & IntfMagdiffthresh4Clip { & self . intf_magdiffthresh4_clip } # [doc = "0x3c4 - INTF_MAGDIFFTHRESH5_CLIP"]
# [inline (always)]
pub const fn intf_magdiffthresh5_clip (& self) -> & IntfMagdiffthresh5Clip { & self . intf_magdiffthresh5_clip } # [doc = "0x3c8 - INTF_MAGDIFFTHRESH6_CLIP"]
# [inline (always)]
pub const fn intf_magdiffthresh6_clip (& self) -> & IntfMagdiffthresh6Clip { & self . intf_magdiffthresh6_clip } # [doc = "0x3cc - HWA_SAFETY_ERR_MASK"]
# [inline (always)]
pub const fn hwa_safety_err_mask (& self) -> & HwaSafetyErrMask { & self . hwa_safety_err_mask } # [doc = "0x3d0 - HWA_SAFETY_ERR_STATUS"]
# [inline (always)]
pub const fn hwa_safety_err_status (& self) -> & HwaSafetyErrStatus { & self . hwa_safety_err_status } # [doc = "0x3d4 - HWA_SAFETY_ERR_STATUS_RAW"]
# [inline (always)]
pub const fn hwa_safety_err_status_raw (& self) -> & HwaSafetyErrStatusRaw { & self . hwa_safety_err_status_raw } } # [doc = "HWACCREG1 (rw) register accessor: HWACCREG1\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg1`]
module"]
# [doc (alias = "HWACCREG1")]
pub type Hwaccreg1 = crate :: Reg < hwaccreg1 :: Hwaccreg1Spec > ; # [doc = "HWACCREG1"]
pub mod hwaccreg1 { # [doc = "Register `HWACCREG1` reader"]
pub type R = crate :: R < Hwaccreg1Spec > ; # [doc = "Register `HWACCREG1` writer"]
pub type W = crate :: W < Hwaccreg1Spec > ; # [doc = "Field `ACCENABLE` reader - 2:0\\]
Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state."]
pub type AccenableR = crate :: FieldReader ; # [doc = "Field `ACCENABLE` writer - 2:0\\]
Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state."]
pub type AccenableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ACCCLKEN` reader - 5:3\\]
Clock-gating Control: This register bit controls the enable/disable for the clock of the Radar Accelerator. This register bit can be set to 0 to clock-gate the accelerator when not using the accelerator. Before enabling the accelerator or before configuring the registers of accelerator, this register bit should be set to 111b first, so that the clock is available."]
pub type AccclkenR = crate :: FieldReader ; # [doc = "Field `ACCCLKEN` writer - 5:3\\]
Clock-gating Control: This register bit controls the enable/disable for the clock of the Radar Accelerator. This register bit can be set to 0 to clock-gate the accelerator when not using the accelerator. Before enabling the accelerator or before configuring the registers of accelerator, this register bit should be set to 111b first, so that the clock is available."]
pub type AccclkenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ACCRESET` reader - 8:6\\]
Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator. The assertion of these register bits by the main processor will bring the Accelerator Engine to a known reset state. This is mostly applicable for resetting the accelerator in case of unexpected behavior. The sequence to be followed in case software reset is to write 111b to this register and then a 000b"]
pub type AccresetR = crate :: FieldReader ; # [doc = "Field `ACCRESET` writer - 8:6\\]
Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator. The assertion of these register bits by the main processor will bring the Accelerator Engine to a known reset state. This is mostly applicable for resetting the accelerator in case of unexpected behavior. The sequence to be followed in case software reset is to write 111b to this register and then a 000b"]
pub type AccresetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: BitReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFT1DEN` reader - 10:10\\]
ADC buffer sharing mode This register is relevant where the Radar Hardware Accelerator is included in a single device along with the mmWave RF front-end. In such a case, during active chirp transmission and inline 1st dimension FFT processing, the ACCEL_MEM0 and ACCEL_MEM1 memories of the accelerator are shared as ping-pong ADC buffers. This register bit needs to be set during this time, so that while the Digital Front End writes ADC samples to the ping buffer, the accelerator automatically accesses (only) the pong buffer, and vice versa. At the end of the active transmission portion of a frame, this bit can be cleared, so that the accelerator has access to all the four local memories independently."]
pub type Fft1denR = crate :: BitReader ; # [doc = "Field `FFT1DEN` writer - 10:10\\]
ADC buffer sharing mode This register is relevant where the Radar Hardware Accelerator is included in a single device along with the mmWave RF front-end. In such a case, during active chirp transmission and inline 1st dimension FFT processing, the ACCEL_MEM0 and ACCEL_MEM1 memories of the accelerator are shared as ping-pong ADC buffers. This register bit needs to be set during this time, so that while the Digital Front End writes ADC samples to the ping buffer, the accelerator automatically accesses (only) the pong buffer, and vice versa. At the end of the active transmission portion of a frame, this bit can be cleared, so that the accelerator has access to all the four local memories independently."]
pub type Fft1denW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ACCDYNCLKEN` reader - 11:11\\]
Dynamic Clock-gating Control:Setting this register bit to 1 enables the capability to clock gate the Radar Accelerator core IPs (FFT and CFAR-CA datapath,CFAR-OS datapath, memory compression datapath) based on the ParamSet being executed."]
pub type AccdynclkenR = crate :: BitReader ; # [doc = "Field `ACCDYNCLKEN` writer - 11:11\\]
Dynamic Clock-gating Control:Setting this register bit to 1 enables the capability to clock gate the Radar Accelerator core IPs (FFT and CFAR-CA datapath,CFAR-OS datapath, memory compression datapath) based on the ParamSet being executed."]
pub type AccdynclkenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ACCDYNCLKEN_LEVEL2` reader - 12:12\\]
Level 2 dynamic clock-gating control :- Setting this register bit to 1 will lead to further power saving by disabling clock during FSM wait state."]
pub type AccdynclkenLevel2R = crate :: BitReader ; # [doc = "Field `ACCDYNCLKEN_LEVEL2` writer - 12:12\\]
Level 2 dynamic clock-gating control :- Setting this register bit to 1 will lead to further power saving by disabling clock during FSM wait state."]
pub type AccdynclkenLevel2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader < u32 > ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 19 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state."]
# [inline (always)]
pub fn accenable (& self) -> AccenableR { AccenableR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
Clock-gating Control: This register bit controls the enable/disable for the clock of the Radar Accelerator. This register bit can be set to 0 to clock-gate the accelerator when not using the accelerator. Before enabling the accelerator or before configuring the registers of accelerator, this register bit should be set to 111b first, so that the clock is available."]
# [inline (always)]
pub fn accclken (& self) -> AccclkenR { AccclkenR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator. The assertion of these register bits by the main processor will bring the Accelerator Engine to a known reset state. This is mostly applicable for resetting the accelerator in case of unexpected behavior. The sequence to be followed in case software reset is to write 111b to this register and then a 000b"]
# [inline (always)]
pub fn accreset (& self) -> AccresetR { AccresetR :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bit 9"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
ADC buffer sharing mode This register is relevant where the Radar Hardware Accelerator is included in a single device along with the mmWave RF front-end. In such a case, during active chirp transmission and inline 1st dimension FFT processing, the ACCEL_MEM0 and ACCEL_MEM1 memories of the accelerator are shared as ping-pong ADC buffers. This register bit needs to be set during this time, so that while the Digital Front End writes ADC samples to the ping buffer, the accelerator automatically accesses (only) the pong buffer, and vice versa. At the end of the active transmission portion of a frame, this bit can be cleared, so that the accelerator has access to all the four local memories independently."]
# [inline (always)]
pub fn fft1den (& self) -> Fft1denR { Fft1denR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Dynamic Clock-gating Control:Setting this register bit to 1 enables the capability to clock gate the Radar Accelerator core IPs (FFT and CFAR-CA datapath,CFAR-OS datapath, memory compression datapath) based on the ParamSet being executed."]
# [inline (always)]
pub fn accdynclken (& self) -> AccdynclkenR { AccdynclkenR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Level 2 dynamic clock-gating control :- Setting this register bit to 1 will lead to further power saving by disabling clock during FSM wait state."]
# [inline (always)]
pub fn accdynclken_level2 (& self) -> AccdynclkenLevel2R { AccdynclkenLevel2R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:31"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new ((self . bits >> 13) & 0x0007_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state."]
# [inline (always)]
# [must_use]
pub fn accenable (& mut self) -> AccenableW < Hwaccreg1Spec > { AccenableW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
Clock-gating Control: This register bit controls the enable/disable for the clock of the Radar Accelerator. This register bit can be set to 0 to clock-gate the accelerator when not using the accelerator. Before enabling the accelerator or before configuring the registers of accelerator, this register bit should be set to 111b first, so that the clock is available."]
# [inline (always)]
# [must_use]
pub fn accclken (& mut self) -> AccclkenW < Hwaccreg1Spec > { AccclkenW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator. The assertion of these register bits by the main processor will bring the Accelerator Engine to a known reset state. This is mostly applicable for resetting the accelerator in case of unexpected behavior. The sequence to be followed in case software reset is to write 111b to this register and then a 000b"]
# [inline (always)]
# [must_use]
pub fn accreset (& mut self) -> AccresetW < Hwaccreg1Spec > { AccresetW :: new (self , 6) } # [doc = "Bit 9"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Hwaccreg1Spec > { Nu1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
ADC buffer sharing mode This register is relevant where the Radar Hardware Accelerator is included in a single device along with the mmWave RF front-end. In such a case, during active chirp transmission and inline 1st dimension FFT processing, the ACCEL_MEM0 and ACCEL_MEM1 memories of the accelerator are shared as ping-pong ADC buffers. This register bit needs to be set during this time, so that while the Digital Front End writes ADC samples to the ping buffer, the accelerator automatically accesses (only) the pong buffer, and vice versa. At the end of the active transmission portion of a frame, this bit can be cleared, so that the accelerator has access to all the four local memories independently."]
# [inline (always)]
# [must_use]
pub fn fft1den (& mut self) -> Fft1denW < Hwaccreg1Spec > { Fft1denW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Dynamic Clock-gating Control:Setting this register bit to 1 enables the capability to clock gate the Radar Accelerator core IPs (FFT and CFAR-CA datapath,CFAR-OS datapath, memory compression datapath) based on the ParamSet being executed."]
# [inline (always)]
# [must_use]
pub fn accdynclken (& mut self) -> AccdynclkenW < Hwaccreg1Spec > { AccdynclkenW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Level 2 dynamic clock-gating control :- Setting this register bit to 1 will lead to further power saving by disabling clock during FSM wait state."]
# [inline (always)]
# [must_use]
pub fn accdynclken_level2 (& mut self) -> AccdynclkenLevel2W < Hwaccreg1Spec > { AccdynclkenLevel2W :: new (self , 12) } # [doc = "Bits 13:31"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Hwaccreg1Spec > { Nu2W :: new (self , 13) } } # [doc = "HWACCREG1\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg1Spec ; impl crate :: RegisterSpec for Hwaccreg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg1::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg1Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg1::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG1 to value 0"]
impl crate :: Resettable for Hwaccreg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG2 (rw) register accessor: HWACCREG2\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg2`]
module"]
# [doc (alias = "HWACCREG2")]
pub type Hwaccreg2 = crate :: Reg < hwaccreg2 :: Hwaccreg2Spec > ; # [doc = "HWACCREG2"]
pub mod hwaccreg2 { # [doc = "Register `HWACCREG2` reader"]
pub type R = crate :: R < Hwaccreg2Spec > ; # [doc = "Register `HWACCREG2` writer"]
pub type W = crate :: W < Hwaccreg2Spec > ; # [doc = "Field `DMA2ACCTRIG` reader - 15:0\\]
DMA trigger register: This register is relevant whenever DMA triggered mode is used (i.e., TRIGMODE = 011b). Whenever a DMA channel has finished copying input samples into the local memory of the accelerator and wants to trigger the accelerator, the procedure to follow is to use a second linked DMA channel to write a 16-bit one-hot signature into this register to trigger the accelerator. In DMA triggered mode, the State Machine keeps monitoring this 16-bit register and waits as long as a specific bit (see DMA2ACC_CHANNEL_TRIGSRC) in this register is zero. The second linked DMA channel writes a one-hot signature that sets the specific bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
pub type Dma2acctrigR = crate :: FieldReader < u16 > ; # [doc = "Field `DMA2ACCTRIG` writer - 15:0\\]
DMA trigger register: This register is relevant whenever DMA triggered mode is used (i.e., TRIGMODE = 011b). Whenever a DMA channel has finished copying input samples into the local memory of the accelerator and wants to trigger the accelerator, the procedure to follow is to use a second linked DMA channel to write a 16-bit one-hot signature into this register to trigger the accelerator. In DMA triggered mode, the State Machine keeps monitoring this 16-bit register and waits as long as a specific bit (see DMA2ACC_CHANNEL_TRIGSRC) in this register is zero. The second linked DMA channel writes a one-hot signature that sets the specific bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
pub type Dma2acctrigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
DMA trigger register: This register is relevant whenever DMA triggered mode is used (i.e., TRIGMODE = 011b). Whenever a DMA channel has finished copying input samples into the local memory of the accelerator and wants to trigger the accelerator, the procedure to follow is to use a second linked DMA channel to write a 16-bit one-hot signature into this register to trigger the accelerator. In DMA triggered mode, the State Machine keeps monitoring this 16-bit register and waits as long as a specific bit (see DMA2ACC_CHANNEL_TRIGSRC) in this register is zero. The second linked DMA channel writes a one-hot signature that sets the specific bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
# [inline (always)]
pub fn dma2acctrig (& self) -> Dma2acctrigR { Dma2acctrigR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
DMA trigger register: This register is relevant whenever DMA triggered mode is used (i.e., TRIGMODE = 011b). Whenever a DMA channel has finished copying input samples into the local memory of the accelerator and wants to trigger the accelerator, the procedure to follow is to use a second linked DMA channel to write a 16-bit one-hot signature into this register to trigger the accelerator. In DMA triggered mode, the State Machine keeps monitoring this 16-bit register and waits as long as a specific bit (see DMA2ACC_CHANNEL_TRIGSRC) in this register is zero. The second linked DMA channel writes a one-hot signature that sets the specific bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
# [inline (always)]
# [must_use]
pub fn dma2acctrig (& mut self) -> Dma2acctrigW < Hwaccreg2Spec > { Dma2acctrigW :: new (self , 0) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Hwaccreg2Spec > { NuW :: new (self , 16) } } # [doc = "HWACCREG2\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg2Spec ; impl crate :: RegisterSpec for Hwaccreg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg2::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg2Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg2::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG2 to value 0"]
impl crate :: Resettable for Hwaccreg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG3 (rw) register accessor: HWACCREG3\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg3`]
module"]
# [doc (alias = "HWACCREG3")]
pub type Hwaccreg3 = crate :: Reg < hwaccreg3 :: Hwaccreg3Spec > ; # [doc = "HWACCREG3"]
pub mod hwaccreg3 { # [doc = "Register `HWACCREG3` reader"]
pub type R = crate :: R < Hwaccreg3Spec > ; # [doc = "Register `HWACCREG3` writer"]
pub type W = crate :: W < Hwaccreg3Spec > ; # [doc = "Field `CM42ACCTRIG` reader - 0:0\\]
Software trigger bit: This register bit is relevant whenever software triggered mode is used (i.e., TRIGMODE = 001b). The main processor software can set this register bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
pub type Cm42acctrigR = crate :: BitReader ; # [doc = "Field `CM42ACCTRIG` writer - 0:0\\]
Software trigger bit: This register bit is relevant whenever software triggered mode is used (i.e., TRIGMODE = 001b). The main processor software can set this register bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
pub type Cm42acctrigW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; # [doc = "Field `CM42DMATRIG` reader - 31:16\\]
Override accelerator Trigger to DMA.Can be used for triggering the first and second DMA transfer thorugh processor"]
pub type Cm42dmatrigR = crate :: FieldReader < u16 > ; # [doc = "Field `CM42DMATRIG` writer - 31:16\\]
Override accelerator Trigger to DMA.Can be used for triggering the first and second DMA transfer thorugh processor"]
pub type Cm42dmatrigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Software trigger bit: This register bit is relevant whenever software triggered mode is used (i.e., TRIGMODE = 001b). The main processor software can set this register bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
# [inline (always)]
pub fn cm42acctrig (& self) -> Cm42acctrigR { Cm42acctrigR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:15"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 1) & 0x7fff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Override accelerator Trigger to DMA.Can be used for triggering the first and second DMA transfer thorugh processor"]
# [inline (always)]
pub fn cm42dmatrig (& self) -> Cm42dmatrigR { Cm42dmatrigR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Software trigger bit: This register bit is relevant whenever software triggered mode is used (i.e., TRIGMODE = 001b). The main processor software can set this register bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set."]
# [inline (always)]
# [must_use]
pub fn cm42acctrig (& mut self) -> Cm42acctrigW < Hwaccreg3Spec > { Cm42acctrigW :: new (self , 0) } # [doc = "Bits 1:15"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Hwaccreg3Spec > { NuW :: new (self , 1) } # [doc = "Bits 16:31 - 31:16\\]
Override accelerator Trigger to DMA.Can be used for triggering the first and second DMA transfer thorugh processor"]
# [inline (always)]
# [must_use]
pub fn cm42dmatrig (& mut self) -> Cm42dmatrigW < Hwaccreg3Spec > { Cm42dmatrigW :: new (self , 16) } } # [doc = "HWACCREG3\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg3Spec ; impl crate :: RegisterSpec for Hwaccreg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg3::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg3Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg3::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG3 to value 0"]
impl crate :: Resettable for Hwaccreg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG4 (rw) register accessor: HWACCREG4\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg4`]
module"]
# [doc (alias = "HWACCREG4")]
pub type Hwaccreg4 = crate :: Reg < hwaccreg4 :: Hwaccreg4Spec > ; # [doc = "HWACCREG4"]
pub mod hwaccreg4 { # [doc = "Register `HWACCREG4` reader"]
pub type R = crate :: R < Hwaccreg4Spec > ; # [doc = "Register `HWACCREG4` writer"]
pub type W = crate :: W < Hwaccreg4Spec > ; # [doc = "Field `SPARE` reader - 31:0\\]
Spare register"]
pub type SpareR = crate :: FieldReader < u32 > ; # [doc = "Field `SPARE` writer - 31:0\\]
Spare register"]
pub type SpareW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Spare register"]
# [inline (always)]
pub fn spare (& self) -> SpareR { SpareR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Spare register"]
# [inline (always)]
# [must_use]
pub fn spare (& mut self) -> SpareW < Hwaccreg4Spec > { SpareW :: new (self , 0) } } # [doc = "HWACCREG4\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg4Spec ; impl crate :: RegisterSpec for Hwaccreg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg4::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg4Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg4::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG4 to value 0"]
impl crate :: Resettable for Hwaccreg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG5 (rw) register accessor: HWACCREG5\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg5`]
module"]
# [doc (alias = "HWACCREG5")]
pub type Hwaccreg5 = crate :: Reg < hwaccreg5 :: Hwaccreg5Spec > ; # [doc = "HWACCREG5"]
pub mod hwaccreg5 { # [doc = "Register `HWACCREG5` reader"]
pub type R = crate :: R < Hwaccreg5Spec > ; # [doc = "Register `HWACCREG5` writer"]
pub type W = crate :: W < Hwaccreg5Spec > ; # [doc = "Field `BPMPATTERNMSB` reader - 31:0\\]
BPM pattern MSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
pub type BpmpatternmsbR = crate :: FieldReader < u32 > ; # [doc = "Field `BPMPATTERNMSB` writer - 31:0\\]
BPM pattern MSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
pub type BpmpatternmsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
BPM pattern MSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
# [inline (always)]
pub fn bpmpatternmsb (& self) -> BpmpatternmsbR { BpmpatternmsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
BPM pattern MSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
# [inline (always)]
# [must_use]
pub fn bpmpatternmsb (& mut self) -> BpmpatternmsbW < Hwaccreg5Spec > { BpmpatternmsbW :: new (self , 0) } } # [doc = "HWACCREG5\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg5Spec ; impl crate :: RegisterSpec for Hwaccreg5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg5::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg5Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg5::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG5 to value 0"]
impl crate :: Resettable for Hwaccreg5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG6 (rw) register accessor: HWACCREG6\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg6`]
module"]
# [doc (alias = "HWACCREG6")]
pub type Hwaccreg6 = crate :: Reg < hwaccreg6 :: Hwaccreg6Spec > ; # [doc = "HWACCREG6"]
pub mod hwaccreg6 { # [doc = "Register `HWACCREG6` reader"]
pub type R = crate :: R < Hwaccreg6Spec > ; # [doc = "Register `HWACCREG6` writer"]
pub type W = crate :: W < Hwaccreg6Spec > ; # [doc = "Field `BPMPATTERNLSB` reader - 31:0\\]
BPM pattern LSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
pub type BpmpatternlsbR = crate :: FieldReader < u32 > ; # [doc = "Field `BPMPATTERNLSB` writer - 31:0\\]
BPM pattern LSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
pub type BpmpatternlsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
BPM pattern LSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
# [inline (always)]
pub fn bpmpatternlsb (& self) -> BpmpatternlsbR { BpmpatternlsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
BPM pattern LSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"]
# [inline (always)]
# [must_use]
pub fn bpmpatternlsb (& mut self) -> BpmpatternlsbW < Hwaccreg6Spec > { BpmpatternlsbW :: new (self , 0) } } # [doc = "HWACCREG6\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg6Spec ; impl crate :: RegisterSpec for Hwaccreg6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg6::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg6Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg6::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG6 to value 0"]
impl crate :: Resettable for Hwaccreg6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG7 (rw) register accessor: HWACCREG7\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg7`]
module"]
# [doc (alias = "HWACCREG7")]
pub type Hwaccreg7 = crate :: Reg < hwaccreg7 :: Hwaccreg7Spec > ; # [doc = "HWACCREG7"]
pub mod hwaccreg7 { # [doc = "Register `HWACCREG7` reader"]
pub type R = crate :: R < Hwaccreg7Spec > ; # [doc = "Register `HWACCREG7` writer"]
pub type W = crate :: W < Hwaccreg7Spec > ; # [doc = "Field `BPMRATE` reader - 9:0\\]
BPM rate: Specifies the number of input samples corresponding to each BPM bit. Minimum valid value for this register is 1."]
pub type BpmrateR = crate :: FieldReader < u16 > ; # [doc = "Field `BPMRATE` writer - 9:0\\]
BPM rate: Specifies the number of input samples corresponding to each BPM bit. Minimum valid value for this register is 1."]
pub type BpmrateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `DITHERTWIDEN` reader - 16:16\\]
Twiddle factor dithering enable: This register-bit is used to enable/disable dithering of twiddle factors in the FFT."]
pub type DithertwidenR = crate :: BitReader ; # [doc = "Field `DITHERTWIDEN` writer - 16:16\\]
Twiddle factor dithering enable: This register-bit is used to enable/disable dithering of twiddle factors in the FFT."]
pub type DithertwidenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `STG1LUTSELWR` reader - 24:24\\]
Select Window RAM or Internal RAM: The Internal RAM for Vector Multiplication mode is mapped to the same address space as the Window RAM. Hence, this register bit is required to specify which of these two needs to be selected, when loading the co-efficients via DMA or M4. 0 - Window RAM is selected 1 - Internal RAM for Vector Multiplication mode is selected. Keep this register bit as 0 always, except during the period when Internal RAM needs to be loaded."]
pub type Stg1lutselwrR = crate :: BitReader ; # [doc = "Field `STG1LUTSELWR` writer - 24:24\\]
Select Window RAM or Internal RAM: The Internal RAM for Vector Multiplication mode is mapped to the same address space as the Window RAM. Hence, this register bit is required to specify which of these two needs to be selected, when loading the co-efficients via DMA or M4. 0 - Window RAM is selected 1 - Internal RAM for Vector Multiplication mode is selected. Keep this register bit as 0 always, except during the period when Internal RAM needs to be loaded."]
pub type Stg1lutselwrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU3` reader - "]
pub type Nu3R = crate :: FieldReader ; # [doc = "Field `NU3` writer - "]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
BPM rate: Specifies the number of input samples corresponding to each BPM bit. Minimum valid value for this register is 1."]
# [inline (always)]
pub fn bpmrate (& self) -> BpmrateR { BpmrateR :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:15"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Twiddle factor dithering enable: This register-bit is used to enable/disable dithering of twiddle factors in the FFT."]
# [inline (always)]
pub fn dithertwiden (& self) -> DithertwidenR { DithertwidenR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:23"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 17) & 0x7f) as u8) } # [doc = "Bit 24 - 24:24\\]
Select Window RAM or Internal RAM: The Internal RAM for Vector Multiplication mode is mapped to the same address space as the Window RAM. Hence, this register bit is required to specify which of these two needs to be selected, when loading the co-efficients via DMA or M4. 0 - Window RAM is selected 1 - Internal RAM for Vector Multiplication mode is selected. Keep this register bit as 0 always, except during the period when Internal RAM needs to be loaded."]
# [inline (always)]
pub fn stg1lutselwr (& self) -> Stg1lutselwrR { Stg1lutselwrR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
BPM rate: Specifies the number of input samples corresponding to each BPM bit. Minimum valid value for this register is 1."]
# [inline (always)]
# [must_use]
pub fn bpmrate (& mut self) -> BpmrateW < Hwaccreg7Spec > { BpmrateW :: new (self , 0) } # [doc = "Bits 10:15"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Hwaccreg7Spec > { Nu1W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
Twiddle factor dithering enable: This register-bit is used to enable/disable dithering of twiddle factors in the FFT."]
# [inline (always)]
# [must_use]
pub fn dithertwiden (& mut self) -> DithertwidenW < Hwaccreg7Spec > { DithertwidenW :: new (self , 16) } # [doc = "Bits 17:23"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Hwaccreg7Spec > { Nu2W :: new (self , 17) } # [doc = "Bit 24 - 24:24\\]
Select Window RAM or Internal RAM: The Internal RAM for Vector Multiplication mode is mapped to the same address space as the Window RAM. Hence, this register bit is required to specify which of these two needs to be selected, when loading the co-efficients via DMA or M4. 0 - Window RAM is selected 1 - Internal RAM for Vector Multiplication mode is selected. Keep this register bit as 0 always, except during the period when Internal RAM needs to be loaded."]
# [inline (always)]
# [must_use]
pub fn stg1lutselwr (& mut self) -> Stg1lutselwrW < Hwaccreg7Spec > { Stg1lutselwrW :: new (self , 24) } # [doc = "Bits 25:31"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < Hwaccreg7Spec > { Nu3W :: new (self , 25) } } # [doc = "HWACCREG7\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg7Spec ; impl crate :: RegisterSpec for Hwaccreg7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg7::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg7Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg7::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG7 to value 0"]
impl crate :: Resettable for Hwaccreg7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG8 (rw) register accessor: HWACCREG8\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg8`]
module"]
# [doc (alias = "HWACCREG8")]
pub type Hwaccreg8 = crate :: Reg < hwaccreg8 :: Hwaccreg8Spec > ; # [doc = "HWACCREG8"]
pub mod hwaccreg8 { # [doc = "Register `HWACCREG8` reader"]
pub type R = crate :: R < Hwaccreg8Spec > ; # [doc = "Register `HWACCREG8` writer"]
pub type W = crate :: W < Hwaccreg8Spec > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `FFTSUMDIV` reader - 28:24\\]
Right-shifting for Sum Statistic: This register specifies how many LSBs to drop to convert the sum statistics to 24-bit value going to the Output Formatter"]
pub type FftsumdivR = crate :: FieldReader ; # [doc = "Field `FFTSUMDIV` writer - 28:24\\]
Right-shifting for Sum Statistic: This register specifies how many LSBs to drop to convert the sum statistics to 24-bit value going to the Output Formatter"]
pub type FftsumdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:23"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:28 - 28:24\\]
Right-shifting for Sum Statistic: This register specifies how many LSBs to drop to convert the sum statistics to 24-bit value going to the Output Formatter"]
# [inline (always)]
pub fn fftsumdiv (& self) -> FftsumdivR { FftsumdivR :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:23"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Hwaccreg8Spec > { Nu1W :: new (self , 0) } # [doc = "Bits 24:28 - 28:24\\]
Right-shifting for Sum Statistic: This register specifies how many LSBs to drop to convert the sum statistics to 24-bit value going to the Output Formatter"]
# [inline (always)]
# [must_use]
pub fn fftsumdiv (& mut self) -> FftsumdivW < Hwaccreg8Spec > { FftsumdivW :: new (self , 24) } # [doc = "Bits 29:31"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Hwaccreg8Spec > { Nu2W :: new (self , 29) } } # [doc = "HWACCREG8\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg8Spec ; impl crate :: RegisterSpec for Hwaccreg8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg8::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg8Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg8::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG8 to value 0"]
impl crate :: Resettable for Hwaccreg8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG11 (rw) register accessor: HWACCREG11\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg11`]
module"]
# [doc (alias = "HWACCREG11")]
pub type Hwaccreg11 = crate :: Reg < hwaccreg11 :: Hwaccreg11Spec > ; # [doc = "HWACCREG11"]
pub mod hwaccreg11 { # [doc = "Register `HWACCREG11` reader"]
pub type R = crate :: R < Hwaccreg11Spec > ; # [doc = "Register `HWACCREG11` writer"]
pub type W = crate :: W < Hwaccreg11Spec > ; # [doc = "Field `LFSRSEED` reader - 28:0\\]
LFSR seed value (random pattern) for twiddle factor dithering,"]
pub type LfsrseedR = crate :: FieldReader < u32 > ; # [doc = "Field `LFSRSEED` writer - 28:0\\]
LFSR seed value (random pattern) for twiddle factor dithering,"]
pub type LfsrseedW < 'a , REG > = crate :: FieldWriter < 'a , REG , 29 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `LFSRLOAD` reader - 31:31\\]
To load the LFSR seed, a pulse signal needs to be provided, by writing a 1 to the LFSR_LOAD register-bit. Self clearing"]
pub type LfsrloadR = crate :: BitReader ; # [doc = "Field `LFSRLOAD` writer - 31:31\\]
To load the LFSR seed, a pulse signal needs to be provided, by writing a 1 to the LFSR_LOAD register-bit. Self clearing"]
pub type LfsrloadW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:28 - 28:0\\]
LFSR seed value (random pattern) for twiddle factor dithering,"]
# [inline (always)]
pub fn lfsrseed (& self) -> LfsrseedR { LfsrseedR :: new (self . bits & 0x1fff_ffff) } # [doc = "Bits 29:30"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 29) & 3) as u8) } # [doc = "Bit 31 - 31:31\\]
To load the LFSR seed, a pulse signal needs to be provided, by writing a 1 to the LFSR_LOAD register-bit. Self clearing"]
# [inline (always)]
pub fn lfsrload (& self) -> LfsrloadR { LfsrloadR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:28 - 28:0\\]
LFSR seed value (random pattern) for twiddle factor dithering,"]
# [inline (always)]
# [must_use]
pub fn lfsrseed (& mut self) -> LfsrseedW < Hwaccreg11Spec > { LfsrseedW :: new (self , 0) } # [doc = "Bits 29:30"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Hwaccreg11Spec > { NuW :: new (self , 29) } # [doc = "Bit 31 - 31:31\\]
To load the LFSR seed, a pulse signal needs to be provided, by writing a 1 to the LFSR_LOAD register-bit. Self clearing"]
# [inline (always)]
# [must_use]
pub fn lfsrload (& mut self) -> LfsrloadW < Hwaccreg11Spec > { LfsrloadW :: new (self , 31) } } # [doc = "HWACCREG11\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg11Spec ; impl crate :: RegisterSpec for Hwaccreg11Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg11::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg11Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg11::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg11Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG11 to value 0"]
impl crate :: Resettable for Hwaccreg11Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG12 (rw) register accessor: HWACCREG12\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg12`]
module"]
# [doc (alias = "HWACCREG12")]
pub type Hwaccreg12 = crate :: Reg < hwaccreg12 :: Hwaccreg12Spec > ; # [doc = "HWACCREG12"]
pub mod hwaccreg12 { # [doc = "Register `HWACCREG12` reader"]
pub type R = crate :: R < Hwaccreg12Spec > ; # [doc = "Register `HWACCREG12` writer"]
pub type W = crate :: W < Hwaccreg12Spec > ; # [doc = "Field `ACC_TRIGGER_IN_STAT` reader - 18:0\\]
Debug register for trigger status: This is a read-only status register, which indicates the trigger status of the accelerator, i.e., whether a specific DMA trigger or a Ping-pong trigger or a SW trigger was ever received (refer TRIGMODE in HW_ACC_PARAM register set). The MSB 16 bits of this register indicate whether a trigger was received via DMA trigger method. The next two bits (i.e., bit indices 2 and 1) indicate the status of DFE ping-pong switch-based trigger and SW trigger respectively. The LSB bit is always 1 and can be ignored {DMA2ACCTRIG\\[15:0\\],adc_buffer_done,CM42ACCTRIG,1}"]
pub type AccTriggerInStatR = crate :: FieldReader < u32 > ; # [doc = "Field `ACC_TRIGGER_IN_STAT` writer - 18:0\\]
Debug register for trigger status: This is a read-only status register, which indicates the trigger status of the accelerator, i.e., whether a specific DMA trigger or a Ping-pong trigger or a SW trigger was ever received (refer TRIGMODE in HW_ACC_PARAM register set). The MSB 16 bits of this register indicate whether a trigger was received via DMA trigger method. The next two bits (i.e., bit indices 2 and 1) indicate the status of DFE ping-pong switch-based trigger and SW trigger respectively. The LSB bit is always 1 and can be ignored {DMA2ACCTRIG\\[15:0\\],adc_buffer_done,CM42ACCTRIG,1}"]
pub type AccTriggerInStatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 19 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `ACC_TRIGGER_IN_CLR` reader - 24:24\\]
Clear trigger status read-only register: This register-bit when set clears the trigger status register ACC_TRIG_IN_STAT described above"]
pub type AccTriggerInClrR = crate :: BitReader ; # [doc = "Field `ACC_TRIGGER_IN_CLR` writer - 24:24\\]
Clear trigger status read-only register: This register-bit when set clears the trigger status register ACC_TRIG_IN_STAT described above"]
pub type AccTriggerInClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:18 - 18:0\\]
Debug register for trigger status: This is a read-only status register, which indicates the trigger status of the accelerator, i.e., whether a specific DMA trigger or a Ping-pong trigger or a SW trigger was ever received (refer TRIGMODE in HW_ACC_PARAM register set). The MSB 16 bits of this register indicate whether a trigger was received via DMA trigger method. The next two bits (i.e., bit indices 2 and 1) indicate the status of DFE ping-pong switch-based trigger and SW trigger respectively. The LSB bit is always 1 and can be ignored {DMA2ACCTRIG\\[15:0\\],adc_buffer_done,CM42ACCTRIG,1}"]
# [inline (always)]
pub fn acc_trigger_in_stat (& self) -> AccTriggerInStatR { AccTriggerInStatR :: new (self . bits & 0x0007_ffff) } # [doc = "Bits 19:23"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear trigger status read-only register: This register-bit when set clears the trigger status register ACC_TRIG_IN_STAT described above"]
# [inline (always)]
pub fn acc_trigger_in_clr (& self) -> AccTriggerInClrR { AccTriggerInClrR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:18 - 18:0\\]
Debug register for trigger status: This is a read-only status register, which indicates the trigger status of the accelerator, i.e., whether a specific DMA trigger or a Ping-pong trigger or a SW trigger was ever received (refer TRIGMODE in HW_ACC_PARAM register set). The MSB 16 bits of this register indicate whether a trigger was received via DMA trigger method. The next two bits (i.e., bit indices 2 and 1) indicate the status of DFE ping-pong switch-based trigger and SW trigger respectively. The LSB bit is always 1 and can be ignored {DMA2ACCTRIG\\[15:0\\],adc_buffer_done,CM42ACCTRIG,1}"]
# [inline (always)]
# [must_use]
pub fn acc_trigger_in_stat (& mut self) -> AccTriggerInStatW < Hwaccreg12Spec > { AccTriggerInStatW :: new (self , 0) } # [doc = "Bits 19:23"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Hwaccreg12Spec > { Nu1W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear trigger status read-only register: This register-bit when set clears the trigger status register ACC_TRIG_IN_STAT described above"]
# [inline (always)]
# [must_use]
pub fn acc_trigger_in_clr (& mut self) -> AccTriggerInClrW < Hwaccreg12Spec > { AccTriggerInClrW :: new (self , 24) } # [doc = "Bits 25:31"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < Hwaccreg12Spec > { Nu2W :: new (self , 25) } } # [doc = "HWACCREG12\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg12Spec ; impl crate :: RegisterSpec for Hwaccreg12Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg12::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg12Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg12::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg12Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG12 to value 0"]
impl crate :: Resettable for Hwaccreg12Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG13 (rw) register accessor: HWACCREG13\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg13`]
module"]
# [doc (alias = "HWACCREG13")]
pub type Hwaccreg13 = crate :: Reg < hwaccreg13 :: Hwaccreg13Spec > ; # [doc = "HWACCREG13"]
pub mod hwaccreg13 { # [doc = "Register `HWACCREG13` reader"]
pub type R = crate :: R < Hwaccreg13Spec > ; # [doc = "Register `HWACCREG13` writer"]
pub type W = crate :: W < Hwaccreg13Spec > ; # [doc = "Field `CFAR_THRESH` reader - 17:0\\]
CFAR Threshold scale factor: This value is used to either multiply or add to the surrounding noise average to determine the threshold used for detection of the present cell under test. If logarithmic CFAR mode is disabled (i.e., in magnitude or magnitude-squared mode), then the register value is multiplied with the surrounding noise average to determine the threshold, else it is added to the surrounding noise average. In the former case, this 18-bit register is interpreted as a 14.4 value. In the latter case (i.e., logarithmic mode), the 18-bit register is interpreted as a 7.11 value."]
pub type CfarThreshR = crate :: FieldReader < u32 > ; # [doc = "Field `CFAR_THRESH` writer - 17:0\\]
CFAR Threshold scale factor: This value is used to either multiply or add to the surrounding noise average to determine the threshold used for detection of the present cell under test. If logarithmic CFAR mode is disabled (i.e., in magnitude or magnitude-squared mode), then the register value is multiplied with the surrounding noise average to determine the threshold, else it is added to the surrounding noise average. In the former case, this 18-bit register is interpreted as a 14.4 value. In the latter case (i.e., logarithmic mode), the 18-bit register is interpreted as a 7.11 value."]
pub type CfarThreshW < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bits 0:17 - 17:0\\]
CFAR Threshold scale factor: This value is used to either multiply or add to the surrounding noise average to determine the threshold used for detection of the present cell under test. If logarithmic CFAR mode is disabled (i.e., in magnitude or magnitude-squared mode), then the register value is multiplied with the surrounding noise average to determine the threshold, else it is added to the surrounding noise average. In the former case, this 18-bit register is interpreted as a 14.4 value. In the latter case (i.e., logarithmic mode), the 18-bit register is interpreted as a 7.11 value."]
# [inline (always)]
pub fn cfar_thresh (& self) -> CfarThreshR { CfarThreshR :: new (self . bits & 0x0003_ffff) } # [doc = "Bits 18:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bits 0:17 - 17:0\\]
CFAR Threshold scale factor: This value is used to either multiply or add to the surrounding noise average to determine the threshold used for detection of the present cell under test. If logarithmic CFAR mode is disabled (i.e., in magnitude or magnitude-squared mode), then the register value is multiplied with the surrounding noise average to determine the threshold, else it is added to the surrounding noise average. In the former case, this 18-bit register is interpreted as a 14.4 value. In the latter case (i.e., logarithmic mode), the 18-bit register is interpreted as a 7.11 value."]
# [inline (always)]
# [must_use]
pub fn cfar_thresh (& mut self) -> CfarThreshW < Hwaccreg13Spec > { CfarThreshW :: new (self , 0) } # [doc = "Bits 18:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Hwaccreg13Spec > { NuW :: new (self , 18) } } # [doc = "HWACCREG13\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg13Spec ; impl crate :: RegisterSpec for Hwaccreg13Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg13::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg13Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg13::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg13Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG13 to value 0"]
impl crate :: Resettable for Hwaccreg13Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG14 (rw) register accessor: HWACCREG14\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg14`]
module"]
# [doc (alias = "HWACCREG14")]
pub type Hwaccreg14 = crate :: Reg < hwaccreg14 :: Hwaccreg14Spec > ; # [doc = "HWACCREG14"]
pub mod hwaccreg14 { # [doc = "Register `HWACCREG14` reader"]
pub type R = crate :: R < Hwaccreg14Spec > ; # [doc = "Register `HWACCREG14` writer"]
pub type W = crate :: W < Hwaccreg14Spec > ; # [doc = "Field `PARAMDONESTAT` reader - 31:0\\]
Parameter-set done status: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 32-bit status register indicate which of the 32 parameter-sets have completed."]
pub type ParamdonestatR = crate :: FieldReader < u32 > ; # [doc = "Field `PARAMDONESTAT` writer - 31:0\\]
Parameter-set done status: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 32-bit status register indicate which of the 32 parameter-sets have completed."]
pub type ParamdonestatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Parameter-set done status: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 32-bit status register indicate which of the 32 parameter-sets have completed."]
# [inline (always)]
pub fn paramdonestat (& self) -> ParamdonestatR { ParamdonestatR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Parameter-set done status: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 32-bit status register indicate which of the 32 parameter-sets have completed."]
# [inline (always)]
# [must_use]
pub fn paramdonestat (& mut self) -> ParamdonestatW < Hwaccreg14Spec > { ParamdonestatW :: new (self , 0) } } # [doc = "HWACCREG14\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg14Spec ; impl crate :: RegisterSpec for Hwaccreg14Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg14::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg14Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg14::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg14Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG14 to value 0"]
impl crate :: Resettable for Hwaccreg14Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG15 (rw) register accessor: HWACCREG15\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg15`]
module"]
# [doc (alias = "HWACCREG15")]
pub type Hwaccreg15 = crate :: Reg < hwaccreg15 :: Hwaccreg15Spec > ; # [doc = "HWACCREG15"]
pub mod hwaccreg15 { # [doc = "Register `HWACCREG15` reader"]
pub type R = crate :: R < Hwaccreg15Spec > ; # [doc = "Register `HWACCREG15` writer"]
pub type W = crate :: W < Hwaccreg15Spec > ; # [doc = "Field `PARAMDONECLR` reader - 31:0\\]
Status bits in PARAMDONESTAT are not automatically cleared, but they can be individually cleared by writing to 32-bit register PARAMDONECLR."]
pub type ParamdoneclrR = crate :: FieldReader < u32 > ; # [doc = "Field `PARAMDONECLR` writer - 31:0\\]
Status bits in PARAMDONESTAT are not automatically cleared, but they can be individually cleared by writing to 32-bit register PARAMDONECLR."]
pub type ParamdoneclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Status bits in PARAMDONESTAT are not automatically cleared, but they can be individually cleared by writing to 32-bit register PARAMDONECLR."]
# [inline (always)]
pub fn paramdoneclr (& self) -> ParamdoneclrR { ParamdoneclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Status bits in PARAMDONESTAT are not automatically cleared, but they can be individually cleared by writing to 32-bit register PARAMDONECLR."]
# [inline (always)]
# [must_use]
pub fn paramdoneclr (& mut self) -> ParamdoneclrW < Hwaccreg15Spec > { ParamdoneclrW :: new (self , 0) } } # [doc = "HWACCREG15\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg15Spec ; impl crate :: RegisterSpec for Hwaccreg15Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg15::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg15Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg15::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg15Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG15 to value 0"]
impl crate :: Resettable for Hwaccreg15Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFAR_DET_THR (rw) register accessor: CFAR_DET_THR\n\nYou can [`read`](crate::Reg::read) this register and get [`cfar_det_thr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfar_det_thr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfar_det_thr`]
module"]
# [doc (alias = "CFAR_DET_THR")]
pub type CfarDetThr = crate :: Reg < cfar_det_thr :: CfarDetThrSpec > ; # [doc = "CFAR_DET_THR"]
pub mod cfar_det_thr { # [doc = "Register `CFAR_DET_THR` reader"]
pub type R = crate :: R < CfarDetThrSpec > ; # [doc = "Register `CFAR_DET_THR` writer"]
pub type W = crate :: W < CfarDetThrSpec > ; # [doc = "Field `CFAR_DET_THR` reader - 23:0\\]
This register is used to specify the threshold used for the detection of the present cell under test during CFAR-CA mode when number of samples for left side and right side noise averaging is 0."]
pub type CfarDetThrR = crate :: FieldReader < u32 > ; # [doc = "Field `CFAR_DET_THR` writer - 23:0\\]
This register is used to specify the threshold used for the detection of the present cell under test during CFAR-CA mode when number of samples for left side and right side noise averaging is 0."]
pub type CfarDetThrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register is used to specify the threshold used for the detection of the present cell under test during CFAR-CA mode when number of samples for left side and right side noise averaging is 0."]
# [inline (always)]
pub fn cfar_det_thr (& self) -> CfarDetThrR { CfarDetThrR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register is used to specify the threshold used for the detection of the present cell under test during CFAR-CA mode when number of samples for left side and right side noise averaging is 0."]
# [inline (always)]
# [must_use]
pub fn cfar_det_thr (& mut self) -> CfarDetThrW < CfarDetThrSpec > { CfarDetThrW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < CfarDetThrSpec > { NuW :: new (self , 24) } } # [doc = "CFAR_DET_THR\n\nYou can [`read`](crate::Reg::read) this register and get [`cfar_det_thr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfar_det_thr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfarDetThrSpec ; impl crate :: RegisterSpec for CfarDetThrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfar_det_thr::R`](R) reader structure"]
impl crate :: Readable for CfarDetThrSpec { } # [doc = "`write(|w| ..)` method takes [`cfar_det_thr::W`](W) writer structure"]
impl crate :: Writable for CfarDetThrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFAR_DET_THR to value 0"]
impl crate :: Resettable for CfarDetThrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX1VALUE (rw) register accessor: MAX1VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max1value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max1value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max1value`]
module"]
# [doc (alias = "MAX1VALUE")]
pub type Max1value = crate :: Reg < max1value :: Max1valueSpec > ; # [doc = "MAX1VALUE"]
pub mod max1value { # [doc = "Register `MAX1VALUE` reader"]
pub type R = crate :: R < Max1valueSpec > ; # [doc = "Register `MAX1VALUE` writer"]
pub type W = crate :: W < Max1valueSpec > ; # [doc = "Field `MAX1VALUE` reader - 23:0\\]
Max value: These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
pub type Max1valueR = crate :: FieldReader < u32 > ; # [doc = "Field `MAX1VALUE` writer - 23:0\\]
Max value: These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
pub type Max1valueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Max value: These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
# [inline (always)]
pub fn max1value (& self) -> Max1valueR { Max1valueR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Max value: These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
# [inline (always)]
# [must_use]
pub fn max1value (& mut self) -> Max1valueW < Max1valueSpec > { Max1valueW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max1valueSpec > { NuW :: new (self , 24) } } # [doc = "MAX1VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max1value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max1value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max1valueSpec ; impl crate :: RegisterSpec for Max1valueSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max1value::R`](R) reader structure"]
impl crate :: Readable for Max1valueSpec { } # [doc = "`write(|w| ..)` method takes [`max1value::W`](W) writer structure"]
impl crate :: Writable for Max1valueSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX1VALUE to value 0"]
impl crate :: Resettable for Max1valueSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX1INDEX (rw) register accessor: MAX1INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max1index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max1index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max1index`]
module"]
# [doc (alias = "MAX1INDEX")]
pub type Max1index = crate :: Reg < max1index :: Max1indexSpec > ; # [doc = "MAX1INDEX"]
pub mod max1index { # [doc = "Register `MAX1INDEX` reader"]
pub type R = crate :: R < Max1indexSpec > ; # [doc = "Register `MAX1INDEX` writer"]
pub type W = crate :: W < Max1indexSpec > ; # [doc = "Field `MAX1INDEX` reader - 11:0\\]
Max index: These registers contain the max index on a per-iteration basis, corresponding to each max value in the MAXn_VALUE registers."]
pub type Max1indexR = crate :: FieldReader < u16 > ; # [doc = "Field `MAX1INDEX` writer - 11:0\\]
Max index: These registers contain the max index on a per-iteration basis, corresponding to each max value in the MAXn_VALUE registers."]
pub type Max1indexW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Max index: These registers contain the max index on a per-iteration basis, corresponding to each max value in the MAXn_VALUE registers."]
# [inline (always)]
pub fn max1index (& self) -> Max1indexR { Max1indexR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Max index: These registers contain the max index on a per-iteration basis, corresponding to each max value in the MAXn_VALUE registers."]
# [inline (always)]
# [must_use]
pub fn max1index (& mut self) -> Max1indexW < Max1indexSpec > { Max1indexW :: new (self , 0) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max1indexSpec > { NuW :: new (self , 12) } } # [doc = "MAX1INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max1index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max1index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max1indexSpec ; impl crate :: RegisterSpec for Max1indexSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max1index::R`](R) reader structure"]
impl crate :: Readable for Max1indexSpec { } # [doc = "`write(|w| ..)` method takes [`max1index::W`](W) writer structure"]
impl crate :: Writable for Max1indexSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX1INDEX to value 0"]
impl crate :: Resettable for Max1indexSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM1LSB (rw) register accessor: ISUM1LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum1lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum1lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum1lsb`]
module"]
# [doc (alias = "ISUM1LSB")]
pub type Isum1lsb = crate :: Reg < isum1lsb :: Isum1lsbSpec > ; # [doc = "ISUM1LSB"]
pub mod isum1lsb { # [doc = "Register `ISUM1LSB` reader"]
pub type R = crate :: R < Isum1lsbSpec > ; # [doc = "Register `ISUM1LSB` writer"]
pub type W = crate :: W < Isum1lsbSpec > ; # [doc = "Field `ISUM1LSB` reader - 31:0\\]
Sum statistics: These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
pub type Isum1lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `ISUM1LSB` writer - 31:0\\]
Sum statistics: These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
pub type Isum1lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Sum statistics: These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
# [inline (always)]
pub fn isum1lsb (& self) -> Isum1lsbR { Isum1lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Sum statistics: These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set)."]
# [inline (always)]
# [must_use]
pub fn isum1lsb (& mut self) -> Isum1lsbW < Isum1lsbSpec > { Isum1lsbW :: new (self , 0) } } # [doc = "ISUM1LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum1lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum1lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum1lsbSpec ; impl crate :: RegisterSpec for Isum1lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum1lsb::R`](R) reader structure"]
impl crate :: Readable for Isum1lsbSpec { } # [doc = "`write(|w| ..)` method takes [`isum1lsb::W`](W) writer structure"]
impl crate :: Writable for Isum1lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM1LSB to value 0"]
impl crate :: Resettable for Isum1lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM1MSB (rw) register accessor: ISUM1MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum1msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum1msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum1msb`]
module"]
# [doc (alias = "ISUM1MSB")]
pub type Isum1msb = crate :: Reg < isum1msb :: Isum1msbSpec > ; # [doc = "ISUM1MSB"]
pub mod isum1msb { # [doc = "Register `ISUM1MSB` reader"]
pub type R = crate :: R < Isum1msbSpec > ; # [doc = "Register `ISUM1MSB` writer"]
pub type W = crate :: W < Isum1msbSpec > ; # [doc = "Field `ISUM1MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Isum1msbR = crate :: FieldReader ; # [doc = "Field `ISUM1MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Isum1msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum1msb (& self) -> Isum1msbR { Isum1msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum1msb (& mut self) -> Isum1msbW < Isum1msbSpec > { Isum1msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Isum1msbSpec > { NuW :: new (self , 4) } } # [doc = "ISUM1MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum1msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum1msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum1msbSpec ; impl crate :: RegisterSpec for Isum1msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum1msb::R`](R) reader structure"]
impl crate :: Readable for Isum1msbSpec { } # [doc = "`write(|w| ..)` method takes [`isum1msb::W`](W) writer structure"]
impl crate :: Writable for Isum1msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM1MSB to value 0"]
impl crate :: Resettable for Isum1msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM1LSB (rw) register accessor: QSUM1LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum1lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum1lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum1lsb`]
module"]
# [doc (alias = "QSUM1LSB")]
pub type Qsum1lsb = crate :: Reg < qsum1lsb :: Qsum1lsbSpec > ; # [doc = "QSUM1LSB"]
pub mod qsum1lsb { # [doc = "Register `QSUM1LSB` reader"]
pub type R = crate :: R < Qsum1lsbSpec > ; # [doc = "Register `QSUM1LSB` writer"]
pub type W = crate :: W < Qsum1lsbSpec > ; # [doc = "Field `QSUM1LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum1lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `QSUM1LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum1lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum1lsb (& self) -> Qsum1lsbR { Qsum1lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum1lsb (& mut self) -> Qsum1lsbW < Qsum1lsbSpec > { Qsum1lsbW :: new (self , 0) } } # [doc = "QSUM1LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum1lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum1lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum1lsbSpec ; impl crate :: RegisterSpec for Qsum1lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum1lsb::R`](R) reader structure"]
impl crate :: Readable for Qsum1lsbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum1lsb::W`](W) writer structure"]
impl crate :: Writable for Qsum1lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM1LSB to value 0"]
impl crate :: Resettable for Qsum1lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM1MSB (rw) register accessor: QSUM1MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum1msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum1msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum1msb`]
module"]
# [doc (alias = "QSUM1MSB")]
pub type Qsum1msb = crate :: Reg < qsum1msb :: Qsum1msbSpec > ; # [doc = "QSUM1MSB"]
pub mod qsum1msb { # [doc = "Register `QSUM1MSB` reader"]
pub type R = crate :: R < Qsum1msbSpec > ; # [doc = "Register `QSUM1MSB` writer"]
pub type W = crate :: W < Qsum1msbSpec > ; # [doc = "Field `QSUM1MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum1msbR = crate :: FieldReader ; # [doc = "Field `QSUM1MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum1msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum1msb (& self) -> Qsum1msbR { Qsum1msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum1msb (& mut self) -> Qsum1msbW < Qsum1msbSpec > { Qsum1msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Qsum1msbSpec > { NuW :: new (self , 4) } } # [doc = "QSUM1MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum1msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum1msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum1msbSpec ; impl crate :: RegisterSpec for Qsum1msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum1msb::R`](R) reader structure"]
impl crate :: Readable for Qsum1msbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum1msb::W`](W) writer structure"]
impl crate :: Writable for Qsum1msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM1MSB to value 0"]
impl crate :: Resettable for Qsum1msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX2VALUE (rw) register accessor: MAX2VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max2value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max2value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max2value`]
module"]
# [doc (alias = "MAX2VALUE")]
pub type Max2value = crate :: Reg < max2value :: Max2valueSpec > ; # [doc = "MAX2VALUE"]
pub mod max2value { # [doc = "Register `MAX2VALUE` reader"]
pub type R = crate :: R < Max2valueSpec > ; # [doc = "Register `MAX2VALUE` writer"]
pub type W = crate :: W < Max2valueSpec > ; # [doc = "Field `MAX2VALUE` reader - 23:0\\]
Refer MAX1VALUE"]
pub type Max2valueR = crate :: FieldReader < u32 > ; # [doc = "Field `MAX2VALUE` writer - 23:0\\]
Refer MAX1VALUE"]
pub type Max2valueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Refer MAX1VALUE"]
# [inline (always)]
pub fn max2value (& self) -> Max2valueR { Max2valueR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Refer MAX1VALUE"]
# [inline (always)]
# [must_use]
pub fn max2value (& mut self) -> Max2valueW < Max2valueSpec > { Max2valueW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max2valueSpec > { NuW :: new (self , 24) } } # [doc = "MAX2VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max2value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max2value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max2valueSpec ; impl crate :: RegisterSpec for Max2valueSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max2value::R`](R) reader structure"]
impl crate :: Readable for Max2valueSpec { } # [doc = "`write(|w| ..)` method takes [`max2value::W`](W) writer structure"]
impl crate :: Writable for Max2valueSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX2VALUE to value 0"]
impl crate :: Resettable for Max2valueSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX2INDEX (rw) register accessor: MAX2INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max2index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max2index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max2index`]
module"]
# [doc (alias = "MAX2INDEX")]
pub type Max2index = crate :: Reg < max2index :: Max2indexSpec > ; # [doc = "MAX2INDEX"]
pub mod max2index { # [doc = "Register `MAX2INDEX` reader"]
pub type R = crate :: R < Max2indexSpec > ; # [doc = "Register `MAX2INDEX` writer"]
pub type W = crate :: W < Max2indexSpec > ; # [doc = "Field `MAX2INDEX` reader - 11:0\\]
Refer MAX1INDEX"]
pub type Max2indexR = crate :: FieldReader < u16 > ; # [doc = "Field `MAX2INDEX` writer - 11:0\\]
Refer MAX1INDEX"]
pub type Max2indexW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Refer MAX1INDEX"]
# [inline (always)]
pub fn max2index (& self) -> Max2indexR { Max2indexR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Refer MAX1INDEX"]
# [inline (always)]
# [must_use]
pub fn max2index (& mut self) -> Max2indexW < Max2indexSpec > { Max2indexW :: new (self , 0) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max2indexSpec > { NuW :: new (self , 12) } } # [doc = "MAX2INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max2index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max2index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max2indexSpec ; impl crate :: RegisterSpec for Max2indexSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max2index::R`](R) reader structure"]
impl crate :: Readable for Max2indexSpec { } # [doc = "`write(|w| ..)` method takes [`max2index::W`](W) writer structure"]
impl crate :: Writable for Max2indexSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX2INDEX to value 0"]
impl crate :: Resettable for Max2indexSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM2LSB (rw) register accessor: ISUM2LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum2lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum2lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum2lsb`]
module"]
# [doc (alias = "ISUM2LSB")]
pub type Isum2lsb = crate :: Reg < isum2lsb :: Isum2lsbSpec > ; # [doc = "ISUM2LSB"]
pub mod isum2lsb { # [doc = "Register `ISUM2LSB` reader"]
pub type R = crate :: R < Isum2lsbSpec > ; # [doc = "Register `ISUM2LSB` writer"]
pub type W = crate :: W < Isum2lsbSpec > ; # [doc = "Field `ISUM2LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Isum2lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `ISUM2LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Isum2lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum2lsb (& self) -> Isum2lsbR { Isum2lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum2lsb (& mut self) -> Isum2lsbW < Isum2lsbSpec > { Isum2lsbW :: new (self , 0) } } # [doc = "ISUM2LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum2lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum2lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum2lsbSpec ; impl crate :: RegisterSpec for Isum2lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum2lsb::R`](R) reader structure"]
impl crate :: Readable for Isum2lsbSpec { } # [doc = "`write(|w| ..)` method takes [`isum2lsb::W`](W) writer structure"]
impl crate :: Writable for Isum2lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM2LSB to value 0"]
impl crate :: Resettable for Isum2lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM2MSB (rw) register accessor: ISUM2MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum2msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum2msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum2msb`]
module"]
# [doc (alias = "ISUM2MSB")]
pub type Isum2msb = crate :: Reg < isum2msb :: Isum2msbSpec > ; # [doc = "ISUM2MSB"]
pub mod isum2msb { # [doc = "Register `ISUM2MSB` reader"]
pub type R = crate :: R < Isum2msbSpec > ; # [doc = "Register `ISUM2MSB` writer"]
pub type W = crate :: W < Isum2msbSpec > ; # [doc = "Field `ISUM2MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Isum2msbR = crate :: FieldReader ; # [doc = "Field `ISUM2MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Isum2msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum2msb (& self) -> Isum2msbR { Isum2msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum2msb (& mut self) -> Isum2msbW < Isum2msbSpec > { Isum2msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Isum2msbSpec > { NuW :: new (self , 4) } } # [doc = "ISUM2MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum2msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum2msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum2msbSpec ; impl crate :: RegisterSpec for Isum2msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum2msb::R`](R) reader structure"]
impl crate :: Readable for Isum2msbSpec { } # [doc = "`write(|w| ..)` method takes [`isum2msb::W`](W) writer structure"]
impl crate :: Writable for Isum2msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM2MSB to value 0"]
impl crate :: Resettable for Isum2msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM2LSB (rw) register accessor: QSUM2LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum2lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum2lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum2lsb`]
module"]
# [doc (alias = "QSUM2LSB")]
pub type Qsum2lsb = crate :: Reg < qsum2lsb :: Qsum2lsbSpec > ; # [doc = "QSUM2LSB"]
pub mod qsum2lsb { # [doc = "Register `QSUM2LSB` reader"]
pub type R = crate :: R < Qsum2lsbSpec > ; # [doc = "Register `QSUM2LSB` writer"]
pub type W = crate :: W < Qsum2lsbSpec > ; # [doc = "Field `QSUM2LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum2lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `QSUM2LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum2lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum2lsb (& self) -> Qsum2lsbR { Qsum2lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum2lsb (& mut self) -> Qsum2lsbW < Qsum2lsbSpec > { Qsum2lsbW :: new (self , 0) } } # [doc = "QSUM2LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum2lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum2lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum2lsbSpec ; impl crate :: RegisterSpec for Qsum2lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum2lsb::R`](R) reader structure"]
impl crate :: Readable for Qsum2lsbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum2lsb::W`](W) writer structure"]
impl crate :: Writable for Qsum2lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM2LSB to value 0"]
impl crate :: Resettable for Qsum2lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM2MSB (rw) register accessor: QSUM2MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum2msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum2msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum2msb`]
module"]
# [doc (alias = "QSUM2MSB")]
pub type Qsum2msb = crate :: Reg < qsum2msb :: Qsum2msbSpec > ; # [doc = "QSUM2MSB"]
pub mod qsum2msb { # [doc = "Register `QSUM2MSB` reader"]
pub type R = crate :: R < Qsum2msbSpec > ; # [doc = "Register `QSUM2MSB` writer"]
pub type W = crate :: W < Qsum2msbSpec > ; # [doc = "Field `QSUM2MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum2msbR = crate :: FieldReader ; # [doc = "Field `QSUM2MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum2msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum2msb (& self) -> Qsum2msbR { Qsum2msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum2msb (& mut self) -> Qsum2msbW < Qsum2msbSpec > { Qsum2msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Qsum2msbSpec > { NuW :: new (self , 4) } } # [doc = "QSUM2MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum2msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum2msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum2msbSpec ; impl crate :: RegisterSpec for Qsum2msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum2msb::R`](R) reader structure"]
impl crate :: Readable for Qsum2msbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum2msb::W`](W) writer structure"]
impl crate :: Writable for Qsum2msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM2MSB to value 0"]
impl crate :: Resettable for Qsum2msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX3VALUE (rw) register accessor: MAX3VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max3value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max3value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max3value`]
module"]
# [doc (alias = "MAX3VALUE")]
pub type Max3value = crate :: Reg < max3value :: Max3valueSpec > ; # [doc = "MAX3VALUE"]
pub mod max3value { # [doc = "Register `MAX3VALUE` reader"]
pub type R = crate :: R < Max3valueSpec > ; # [doc = "Register `MAX3VALUE` writer"]
pub type W = crate :: W < Max3valueSpec > ; # [doc = "Field `MAX3VALUE` reader - 23:0\\]
Refer MAX1VALUE"]
pub type Max3valueR = crate :: FieldReader < u32 > ; # [doc = "Field `MAX3VALUE` writer - 23:0\\]
Refer MAX1VALUE"]
pub type Max3valueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Refer MAX1VALUE"]
# [inline (always)]
pub fn max3value (& self) -> Max3valueR { Max3valueR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Refer MAX1VALUE"]
# [inline (always)]
# [must_use]
pub fn max3value (& mut self) -> Max3valueW < Max3valueSpec > { Max3valueW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max3valueSpec > { NuW :: new (self , 24) } } # [doc = "MAX3VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max3value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max3value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max3valueSpec ; impl crate :: RegisterSpec for Max3valueSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max3value::R`](R) reader structure"]
impl crate :: Readable for Max3valueSpec { } # [doc = "`write(|w| ..)` method takes [`max3value::W`](W) writer structure"]
impl crate :: Writable for Max3valueSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX3VALUE to value 0"]
impl crate :: Resettable for Max3valueSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX3INDEX (rw) register accessor: MAX3INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max3index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max3index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max3index`]
module"]
# [doc (alias = "MAX3INDEX")]
pub type Max3index = crate :: Reg < max3index :: Max3indexSpec > ; # [doc = "MAX3INDEX"]
pub mod max3index { # [doc = "Register `MAX3INDEX` reader"]
pub type R = crate :: R < Max3indexSpec > ; # [doc = "Register `MAX3INDEX` writer"]
pub type W = crate :: W < Max3indexSpec > ; # [doc = "Field `MAX3INDEX` reader - 11:0\\]
Refer MAX1INDEX"]
pub type Max3indexR = crate :: FieldReader < u16 > ; # [doc = "Field `MAX3INDEX` writer - 11:0\\]
Refer MAX1INDEX"]
pub type Max3indexW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Refer MAX1INDEX"]
# [inline (always)]
pub fn max3index (& self) -> Max3indexR { Max3indexR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Refer MAX1INDEX"]
# [inline (always)]
# [must_use]
pub fn max3index (& mut self) -> Max3indexW < Max3indexSpec > { Max3indexW :: new (self , 0) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max3indexSpec > { NuW :: new (self , 12) } } # [doc = "MAX3INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max3index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max3index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max3indexSpec ; impl crate :: RegisterSpec for Max3indexSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max3index::R`](R) reader structure"]
impl crate :: Readable for Max3indexSpec { } # [doc = "`write(|w| ..)` method takes [`max3index::W`](W) writer structure"]
impl crate :: Writable for Max3indexSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX3INDEX to value 0"]
impl crate :: Resettable for Max3indexSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM3LSB (rw) register accessor: ISUM3LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum3lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum3lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum3lsb`]
module"]
# [doc (alias = "ISUM3LSB")]
pub type Isum3lsb = crate :: Reg < isum3lsb :: Isum3lsbSpec > ; # [doc = "ISUM3LSB"]
pub mod isum3lsb { # [doc = "Register `ISUM3LSB` reader"]
pub type R = crate :: R < Isum3lsbSpec > ; # [doc = "Register `ISUM3LSB` writer"]
pub type W = crate :: W < Isum3lsbSpec > ; # [doc = "Field `ISUM3LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Isum3lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `ISUM3LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Isum3lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum3lsb (& self) -> Isum3lsbR { Isum3lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum3lsb (& mut self) -> Isum3lsbW < Isum3lsbSpec > { Isum3lsbW :: new (self , 0) } } # [doc = "ISUM3LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum3lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum3lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum3lsbSpec ; impl crate :: RegisterSpec for Isum3lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum3lsb::R`](R) reader structure"]
impl crate :: Readable for Isum3lsbSpec { } # [doc = "`write(|w| ..)` method takes [`isum3lsb::W`](W) writer structure"]
impl crate :: Writable for Isum3lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM3LSB to value 0"]
impl crate :: Resettable for Isum3lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM3MSB (rw) register accessor: ISUM3MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum3msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum3msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum3msb`]
module"]
# [doc (alias = "ISUM3MSB")]
pub type Isum3msb = crate :: Reg < isum3msb :: Isum3msbSpec > ; # [doc = "ISUM3MSB"]
pub mod isum3msb { # [doc = "Register `ISUM3MSB` reader"]
pub type R = crate :: R < Isum3msbSpec > ; # [doc = "Register `ISUM3MSB` writer"]
pub type W = crate :: W < Isum3msbSpec > ; # [doc = "Field `ISUM3MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Isum3msbR = crate :: FieldReader ; # [doc = "Field `ISUM3MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Isum3msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum3msb (& self) -> Isum3msbR { Isum3msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum3msb (& mut self) -> Isum3msbW < Isum3msbSpec > { Isum3msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Isum3msbSpec > { NuW :: new (self , 4) } } # [doc = "ISUM3MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum3msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum3msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum3msbSpec ; impl crate :: RegisterSpec for Isum3msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum3msb::R`](R) reader structure"]
impl crate :: Readable for Isum3msbSpec { } # [doc = "`write(|w| ..)` method takes [`isum3msb::W`](W) writer structure"]
impl crate :: Writable for Isum3msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM3MSB to value 0"]
impl crate :: Resettable for Isum3msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM3LSB (rw) register accessor: QSUM3LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum3lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum3lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum3lsb`]
module"]
# [doc (alias = "QSUM3LSB")]
pub type Qsum3lsb = crate :: Reg < qsum3lsb :: Qsum3lsbSpec > ; # [doc = "QSUM3LSB"]
pub mod qsum3lsb { # [doc = "Register `QSUM3LSB` reader"]
pub type R = crate :: R < Qsum3lsbSpec > ; # [doc = "Register `QSUM3LSB` writer"]
pub type W = crate :: W < Qsum3lsbSpec > ; # [doc = "Field `QSUM3LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum3lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `QSUM3LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum3lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum3lsb (& self) -> Qsum3lsbR { Qsum3lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum3lsb (& mut self) -> Qsum3lsbW < Qsum3lsbSpec > { Qsum3lsbW :: new (self , 0) } } # [doc = "QSUM3LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum3lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum3lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum3lsbSpec ; impl crate :: RegisterSpec for Qsum3lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum3lsb::R`](R) reader structure"]
impl crate :: Readable for Qsum3lsbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum3lsb::W`](W) writer structure"]
impl crate :: Writable for Qsum3lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM3LSB to value 0"]
impl crate :: Resettable for Qsum3lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM3MSB (rw) register accessor: QSUM3MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum3msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum3msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum3msb`]
module"]
# [doc (alias = "QSUM3MSB")]
pub type Qsum3msb = crate :: Reg < qsum3msb :: Qsum3msbSpec > ; # [doc = "QSUM3MSB"]
pub mod qsum3msb { # [doc = "Register `QSUM3MSB` reader"]
pub type R = crate :: R < Qsum3msbSpec > ; # [doc = "Register `QSUM3MSB` writer"]
pub type W = crate :: W < Qsum3msbSpec > ; # [doc = "Field `QSUM3MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum3msbR = crate :: FieldReader ; # [doc = "Field `QSUM3MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum3msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum3msb (& self) -> Qsum3msbR { Qsum3msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum3msb (& mut self) -> Qsum3msbW < Qsum3msbSpec > { Qsum3msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Qsum3msbSpec > { NuW :: new (self , 4) } } # [doc = "QSUM3MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum3msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum3msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum3msbSpec ; impl crate :: RegisterSpec for Qsum3msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum3msb::R`](R) reader structure"]
impl crate :: Readable for Qsum3msbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum3msb::W`](W) writer structure"]
impl crate :: Writable for Qsum3msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM3MSB to value 0"]
impl crate :: Resettable for Qsum3msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX4VALUE (rw) register accessor: MAX4VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max4value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max4value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max4value`]
module"]
# [doc (alias = "MAX4VALUE")]
pub type Max4value = crate :: Reg < max4value :: Max4valueSpec > ; # [doc = "MAX4VALUE"]
pub mod max4value { # [doc = "Register `MAX4VALUE` reader"]
pub type R = crate :: R < Max4valueSpec > ; # [doc = "Register `MAX4VALUE` writer"]
pub type W = crate :: W < Max4valueSpec > ; # [doc = "Field `MAX4VALUE` reader - 23:0\\]
Refer MAX1INDEX"]
pub type Max4valueR = crate :: FieldReader < u32 > ; # [doc = "Field `MAX4VALUE` writer - 23:0\\]
Refer MAX1INDEX"]
pub type Max4valueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Refer MAX1INDEX"]
# [inline (always)]
pub fn max4value (& self) -> Max4valueR { Max4valueR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Refer MAX1INDEX"]
# [inline (always)]
# [must_use]
pub fn max4value (& mut self) -> Max4valueW < Max4valueSpec > { Max4valueW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max4valueSpec > { NuW :: new (self , 24) } } # [doc = "MAX4VALUE\n\nYou can [`read`](crate::Reg::read) this register and get [`max4value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max4value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max4valueSpec ; impl crate :: RegisterSpec for Max4valueSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max4value::R`](R) reader structure"]
impl crate :: Readable for Max4valueSpec { } # [doc = "`write(|w| ..)` method takes [`max4value::W`](W) writer structure"]
impl crate :: Writable for Max4valueSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX4VALUE to value 0"]
impl crate :: Resettable for Max4valueSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MAX4INDEX (rw) register accessor: MAX4INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max4index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max4index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max4index`]
module"]
# [doc (alias = "MAX4INDEX")]
pub type Max4index = crate :: Reg < max4index :: Max4indexSpec > ; # [doc = "MAX4INDEX"]
pub mod max4index { # [doc = "Register `MAX4INDEX` reader"]
pub type R = crate :: R < Max4indexSpec > ; # [doc = "Register `MAX4INDEX` writer"]
pub type W = crate :: W < Max4indexSpec > ; # [doc = "Field `MAX4INDEX` reader - 11:0\\]
Refer MAX1VALUE"]
pub type Max4indexR = crate :: FieldReader < u16 > ; # [doc = "Field `MAX4INDEX` writer - 11:0\\]
Refer MAX1VALUE"]
pub type Max4indexW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Refer MAX1VALUE"]
# [inline (always)]
pub fn max4index (& self) -> Max4indexR { Max4indexR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Refer MAX1VALUE"]
# [inline (always)]
# [must_use]
pub fn max4index (& mut self) -> Max4indexW < Max4indexSpec > { Max4indexW :: new (self , 0) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Max4indexSpec > { NuW :: new (self , 12) } } # [doc = "MAX4INDEX\n\nYou can [`read`](crate::Reg::read) this register and get [`max4index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max4index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Max4indexSpec ; impl crate :: RegisterSpec for Max4indexSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`max4index::R`](R) reader structure"]
impl crate :: Readable for Max4indexSpec { } # [doc = "`write(|w| ..)` method takes [`max4index::W`](W) writer structure"]
impl crate :: Writable for Max4indexSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MAX4INDEX to value 0"]
impl crate :: Resettable for Max4indexSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM4LSB (rw) register accessor: ISUM4LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum4lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum4lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum4lsb`]
module"]
# [doc (alias = "ISUM4LSB")]
pub type Isum4lsb = crate :: Reg < isum4lsb :: Isum4lsbSpec > ; # [doc = "ISUM4LSB"]
pub mod isum4lsb { # [doc = "Register `ISUM4LSB` reader"]
pub type R = crate :: R < Isum4lsbSpec > ; # [doc = "Register `ISUM4LSB` writer"]
pub type W = crate :: W < Isum4lsbSpec > ; # [doc = "Field `ISUM4LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Isum4lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `ISUM4LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Isum4lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum4lsb (& self) -> Isum4lsbR { Isum4lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum4lsb (& mut self) -> Isum4lsbW < Isum4lsbSpec > { Isum4lsbW :: new (self , 0) } } # [doc = "ISUM4LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum4lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum4lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum4lsbSpec ; impl crate :: RegisterSpec for Isum4lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum4lsb::R`](R) reader structure"]
impl crate :: Readable for Isum4lsbSpec { } # [doc = "`write(|w| ..)` method takes [`isum4lsb::W`](W) writer structure"]
impl crate :: Writable for Isum4lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM4LSB to value 0"]
impl crate :: Resettable for Isum4lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISUM4MSB (rw) register accessor: ISUM4MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum4msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum4msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isum4msb`]
module"]
# [doc (alias = "ISUM4MSB")]
pub type Isum4msb = crate :: Reg < isum4msb :: Isum4msbSpec > ; # [doc = "ISUM4MSB"]
pub mod isum4msb { # [doc = "Register `ISUM4MSB` reader"]
pub type R = crate :: R < Isum4msbSpec > ; # [doc = "Register `ISUM4MSB` writer"]
pub type W = crate :: W < Isum4msbSpec > ; # [doc = "Field `ISUM4MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Isum4msbR = crate :: FieldReader ; # [doc = "Field `ISUM4MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Isum4msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn isum4msb (& self) -> Isum4msbR { Isum4msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn isum4msb (& mut self) -> Isum4msbW < Isum4msbSpec > { Isum4msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Isum4msbSpec > { NuW :: new (self , 4) } } # [doc = "ISUM4MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`isum4msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isum4msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isum4msbSpec ; impl crate :: RegisterSpec for Isum4msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`isum4msb::R`](R) reader structure"]
impl crate :: Readable for Isum4msbSpec { } # [doc = "`write(|w| ..)` method takes [`isum4msb::W`](W) writer structure"]
impl crate :: Writable for Isum4msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISUM4MSB to value 0"]
impl crate :: Resettable for Isum4msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM4LSB (rw) register accessor: QSUM4LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum4lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum4lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum4lsb`]
module"]
# [doc (alias = "QSUM4LSB")]
pub type Qsum4lsb = crate :: Reg < qsum4lsb :: Qsum4lsbSpec > ; # [doc = "QSUM4LSB"]
pub mod qsum4lsb { # [doc = "Register `QSUM4LSB` reader"]
pub type R = crate :: R < Qsum4lsbSpec > ; # [doc = "Register `QSUM4LSB` writer"]
pub type W = crate :: W < Qsum4lsbSpec > ; # [doc = "Field `QSUM4LSB` reader - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum4lsbR = crate :: FieldReader < u32 > ; # [doc = "Field `QSUM4LSB` writer - 31:0\\]
Refer ISUM1LSB"]
pub type Qsum4lsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum4lsb (& self) -> Qsum4lsbR { Qsum4lsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum4lsb (& mut self) -> Qsum4lsbW < Qsum4lsbSpec > { Qsum4lsbW :: new (self , 0) } } # [doc = "QSUM4LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum4lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum4lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum4lsbSpec ; impl crate :: RegisterSpec for Qsum4lsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum4lsb::R`](R) reader structure"]
impl crate :: Readable for Qsum4lsbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum4lsb::W`](W) writer structure"]
impl crate :: Writable for Qsum4lsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM4LSB to value 0"]
impl crate :: Resettable for Qsum4lsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSUM4MSB (rw) register accessor: QSUM4MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum4msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum4msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsum4msb`]
module"]
# [doc (alias = "QSUM4MSB")]
pub type Qsum4msb = crate :: Reg < qsum4msb :: Qsum4msbSpec > ; # [doc = "QSUM4MSB"]
pub mod qsum4msb { # [doc = "Register `QSUM4MSB` reader"]
pub type R = crate :: R < Qsum4msbSpec > ; # [doc = "Register `QSUM4MSB` writer"]
pub type W = crate :: W < Qsum4msbSpec > ; # [doc = "Field `QSUM4MSB` reader - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum4msbR = crate :: FieldReader ; # [doc = "Field `QSUM4MSB` writer - 3:0\\]
Refer ISUM1LSB"]
pub type Qsum4msbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
pub fn qsum4msb (& self) -> Qsum4msbR { Qsum4msbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Refer ISUM1LSB"]
# [inline (always)]
# [must_use]
pub fn qsum4msb (& mut self) -> Qsum4msbW < Qsum4msbSpec > { Qsum4msbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Qsum4msbSpec > { NuW :: new (self , 4) } } # [doc = "QSUM4MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`qsum4msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsum4msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qsum4msbSpec ; impl crate :: RegisterSpec for Qsum4msbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsum4msb::R`](R) reader structure"]
impl crate :: Readable for Qsum4msbSpec { } # [doc = "`write(|w| ..)` method takes [`qsum4msb::W`](W) writer structure"]
impl crate :: Writable for Qsum4msbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSUM4MSB to value 0"]
impl crate :: Resettable for Qsum4msbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFARTEST (rw) register accessor: CFARTEST\n\nYou can [`read`](crate::Reg::read) this register and get [`cfartest::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfartest::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfartest`]
module"]
# [doc (alias = "CFARTEST")]
pub type Cfartest = crate :: Reg < cfartest :: CfartestSpec > ; # [doc = "CFARTEST"]
pub mod cfartest { # [doc = "Register `CFARTEST` reader"]
pub type R = crate :: R < CfartestSpec > ; # [doc = "Register `CFARTEST` writer"]
pub type W = crate :: W < CfartestSpec > ; # [doc = "Field `CFARTEST` reader - 23:0\\]
Reserved.TI internal"]
pub type CfartestR = crate :: FieldReader < u32 > ; # [doc = "Field `CFARTEST` writer - 23:0\\]
Reserved.TI internal"]
pub type CfartestW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn cfartest (& self) -> CfartestR { CfartestR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn cfartest (& mut self) -> CfartestW < CfartestSpec > { CfartestW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < CfartestSpec > { NuW :: new (self , 24) } } # [doc = "CFARTEST\n\nYou can [`read`](crate::Reg::read) this register and get [`cfartest::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfartest::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfartestSpec ; impl crate :: RegisterSpec for CfartestSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfartest::R`](R) reader structure"]
impl crate :: Readable for CfartestSpec { } # [doc = "`write(|w| ..)` method takes [`cfartest::W`](W) writer structure"]
impl crate :: Writable for CfartestSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFARTEST to value 0"]
impl crate :: Resettable for CfartestSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RDSTATUS (rw) register accessor: RDSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`rdstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdstatus`]
module"]
# [doc (alias = "RDSTATUS")]
pub type Rdstatus = crate :: Reg < rdstatus :: RdstatusSpec > ; # [doc = "RDSTATUS"]
pub mod rdstatus { # [doc = "Register `RDSTATUS` reader"]
pub type R = crate :: R < RdstatusSpec > ; # [doc = "Register `RDSTATUS` writer"]
pub type W = crate :: W < RdstatusSpec > ; # [doc = "Field `PARAMADDR` reader - 4:0\\]
Index of the current parameter set being executed from PARAM RAM . For Debug only"]
pub type ParamaddrR = crate :: FieldReader ; # [doc = "Field `PARAMADDR` writer - 4:0\\]
Index of the current parameter set being executed from PARAM RAM . For Debug only"]
pub type ParamaddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `LOOPCNT` reader - 16:5\\]
Running value of the loop count when the HWA is executing from PARAM RAM . For Debug only"]
pub type LoopcntR = crate :: FieldReader < u16 > ; # [doc = "Field `LOOPCNT` writer - 16:5\\]
Running value of the loop count when the HWA is executing from PARAM RAM . For Debug only"]
pub type LoopcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Index of the current parameter set being executed from PARAM RAM . For Debug only"]
# [inline (always)]
pub fn paramaddr (& self) -> ParamaddrR { ParamaddrR :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:16 - 16:5\\]
Running value of the loop count when the HWA is executing from PARAM RAM . For Debug only"]
# [inline (always)]
pub fn loopcnt (& self) -> LoopcntR { LoopcntR :: new (((self . bits >> 5) & 0x0fff) as u16) } # [doc = "Bits 17:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Index of the current parameter set being executed from PARAM RAM . For Debug only"]
# [inline (always)]
# [must_use]
pub fn paramaddr (& mut self) -> ParamaddrW < RdstatusSpec > { ParamaddrW :: new (self , 0) } # [doc = "Bits 5:16 - 16:5\\]
Running value of the loop count when the HWA is executing from PARAM RAM . For Debug only"]
# [inline (always)]
# [must_use]
pub fn loopcnt (& mut self) -> LoopcntW < RdstatusSpec > { LoopcntW :: new (self , 5) } # [doc = "Bits 17:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < RdstatusSpec > { NuW :: new (self , 17) } } # [doc = "RDSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`rdstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdstatusSpec ; impl crate :: RegisterSpec for RdstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rdstatus::R`](R) reader structure"]
impl crate :: Readable for RdstatusSpec { } # [doc = "`write(|w| ..)` method takes [`rdstatus::W`](W) writer structure"]
impl crate :: Writable for RdstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RDSTATUS to value 0"]
impl crate :: Resettable for RdstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH1DONE (rw) register accessor: SIGDMACH1DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach1done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach1done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach1done`]
module"]
# [doc (alias = "SIGDMACH1DONE")]
pub type Sigdmach1done = crate :: Reg < sigdmach1done :: Sigdmach1doneSpec > ; # [doc = "SIGDMACH1DONE"]
pub mod sigdmach1done { # [doc = "Register `SIGDMACH1DONE` reader"]
pub type R = crate :: R < Sigdmach1doneSpec > ; # [doc = "Register `SIGDMACH1DONE` writer"]
pub type W = crate :: W < Sigdmach1doneSpec > ; # [doc = "Field `SIGDMACH1DONE` reader - 31:0\\]
Signature for DMA channel 1 completion (tied to 0x0001 in HW). Linked DMA can copy from one of these SIG_DMACHx_DONE registers into DMA2ACC_TRIG register to set the appropriate register bit to signal the completion of DMA and trigger the accelerator"]
pub type Sigdmach1doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH1DONE` writer - 31:0\\]
Signature for DMA channel 1 completion (tied to 0x0001 in HW). Linked DMA can copy from one of these SIG_DMACHx_DONE registers into DMA2ACC_TRIG register to set the appropriate register bit to signal the completion of DMA and trigger the accelerator"]
pub type Sigdmach1doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 1 completion (tied to 0x0001 in HW). Linked DMA can copy from one of these SIG_DMACHx_DONE registers into DMA2ACC_TRIG register to set the appropriate register bit to signal the completion of DMA and trigger the accelerator"]
# [inline (always)]
pub fn sigdmach1done (& self) -> Sigdmach1doneR { Sigdmach1doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 1 completion (tied to 0x0001 in HW). Linked DMA can copy from one of these SIG_DMACHx_DONE registers into DMA2ACC_TRIG register to set the appropriate register bit to signal the completion of DMA and trigger the accelerator"]
# [inline (always)]
# [must_use]
pub fn sigdmach1done (& mut self) -> Sigdmach1doneW < Sigdmach1doneSpec > { Sigdmach1doneW :: new (self , 0) } } # [doc = "SIGDMACH1DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach1done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach1done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach1doneSpec ; impl crate :: RegisterSpec for Sigdmach1doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach1done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach1doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach1done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach1doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH1DONE to value 0"]
impl crate :: Resettable for Sigdmach1doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH2DONE (rw) register accessor: SIGDMACH2DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach2done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach2done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach2done`]
module"]
# [doc (alias = "SIGDMACH2DONE")]
pub type Sigdmach2done = crate :: Reg < sigdmach2done :: Sigdmach2doneSpec > ; # [doc = "SIGDMACH2DONE"]
pub mod sigdmach2done { # [doc = "Register `SIGDMACH2DONE` reader"]
pub type R = crate :: R < Sigdmach2doneSpec > ; # [doc = "Register `SIGDMACH2DONE` writer"]
pub type W = crate :: W < Sigdmach2doneSpec > ; # [doc = "Field `SIGDMACH2DONE` reader - 31:0\\]
Signature for DMA channel 2 completion (tied to 0x0002 in HW)"]
pub type Sigdmach2doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH2DONE` writer - 31:0\\]
Signature for DMA channel 2 completion (tied to 0x0002 in HW)"]
pub type Sigdmach2doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 2 completion (tied to 0x0002 in HW)"]
# [inline (always)]
pub fn sigdmach2done (& self) -> Sigdmach2doneR { Sigdmach2doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 2 completion (tied to 0x0002 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach2done (& mut self) -> Sigdmach2doneW < Sigdmach2doneSpec > { Sigdmach2doneW :: new (self , 0) } } # [doc = "SIGDMACH2DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach2done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach2done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach2doneSpec ; impl crate :: RegisterSpec for Sigdmach2doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach2done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach2doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach2done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach2doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH2DONE to value 0"]
impl crate :: Resettable for Sigdmach2doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH3DONE (rw) register accessor: SIGDMACH3DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach3done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach3done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach3done`]
module"]
# [doc (alias = "SIGDMACH3DONE")]
pub type Sigdmach3done = crate :: Reg < sigdmach3done :: Sigdmach3doneSpec > ; # [doc = "SIGDMACH3DONE"]
pub mod sigdmach3done { # [doc = "Register `SIGDMACH3DONE` reader"]
pub type R = crate :: R < Sigdmach3doneSpec > ; # [doc = "Register `SIGDMACH3DONE` writer"]
pub type W = crate :: W < Sigdmach3doneSpec > ; # [doc = "Field `SIGDMACH3DONE` reader - 31:0\\]
Signature for DMA channel 3 completion (tied to 0x0004 in HW)"]
pub type Sigdmach3doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH3DONE` writer - 31:0\\]
Signature for DMA channel 3 completion (tied to 0x0004 in HW)"]
pub type Sigdmach3doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 3 completion (tied to 0x0004 in HW)"]
# [inline (always)]
pub fn sigdmach3done (& self) -> Sigdmach3doneR { Sigdmach3doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 3 completion (tied to 0x0004 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach3done (& mut self) -> Sigdmach3doneW < Sigdmach3doneSpec > { Sigdmach3doneW :: new (self , 0) } } # [doc = "SIGDMACH3DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach3done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach3done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach3doneSpec ; impl crate :: RegisterSpec for Sigdmach3doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach3done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach3doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach3done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach3doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH3DONE to value 0"]
impl crate :: Resettable for Sigdmach3doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH4DONE (rw) register accessor: SIGDMACH4DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach4done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach4done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach4done`]
module"]
# [doc (alias = "SIGDMACH4DONE")]
pub type Sigdmach4done = crate :: Reg < sigdmach4done :: Sigdmach4doneSpec > ; # [doc = "SIGDMACH4DONE"]
pub mod sigdmach4done { # [doc = "Register `SIGDMACH4DONE` reader"]
pub type R = crate :: R < Sigdmach4doneSpec > ; # [doc = "Register `SIGDMACH4DONE` writer"]
pub type W = crate :: W < Sigdmach4doneSpec > ; # [doc = "Field `SIGDMACH4DONE` reader - 31:0\\]
Signature for DMA channel 4 completion (tied to 0x0008 in HW)"]
pub type Sigdmach4doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH4DONE` writer - 31:0\\]
Signature for DMA channel 4 completion (tied to 0x0008 in HW)"]
pub type Sigdmach4doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 4 completion (tied to 0x0008 in HW)"]
# [inline (always)]
pub fn sigdmach4done (& self) -> Sigdmach4doneR { Sigdmach4doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 4 completion (tied to 0x0008 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach4done (& mut self) -> Sigdmach4doneW < Sigdmach4doneSpec > { Sigdmach4doneW :: new (self , 0) } } # [doc = "SIGDMACH4DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach4done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach4done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach4doneSpec ; impl crate :: RegisterSpec for Sigdmach4doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach4done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach4doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach4done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach4doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH4DONE to value 0"]
impl crate :: Resettable for Sigdmach4doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH5DONE (rw) register accessor: SIGDMACH5DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach5done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach5done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach5done`]
module"]
# [doc (alias = "SIGDMACH5DONE")]
pub type Sigdmach5done = crate :: Reg < sigdmach5done :: Sigdmach5doneSpec > ; # [doc = "SIGDMACH5DONE"]
pub mod sigdmach5done { # [doc = "Register `SIGDMACH5DONE` reader"]
pub type R = crate :: R < Sigdmach5doneSpec > ; # [doc = "Register `SIGDMACH5DONE` writer"]
pub type W = crate :: W < Sigdmach5doneSpec > ; # [doc = "Field `SIGDMACH5DONE` reader - 31:0\\]
Signature for DMA channel 5 completion (tied to 0x0010 in HW)"]
pub type Sigdmach5doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH5DONE` writer - 31:0\\]
Signature for DMA channel 5 completion (tied to 0x0010 in HW)"]
pub type Sigdmach5doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 5 completion (tied to 0x0010 in HW)"]
# [inline (always)]
pub fn sigdmach5done (& self) -> Sigdmach5doneR { Sigdmach5doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 5 completion (tied to 0x0010 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach5done (& mut self) -> Sigdmach5doneW < Sigdmach5doneSpec > { Sigdmach5doneW :: new (self , 0) } } # [doc = "SIGDMACH5DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach5done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach5done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach5doneSpec ; impl crate :: RegisterSpec for Sigdmach5doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach5done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach5doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach5done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach5doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH5DONE to value 0"]
impl crate :: Resettable for Sigdmach5doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH6DONE (rw) register accessor: SIGDMACH6DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach6done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach6done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach6done`]
module"]
# [doc (alias = "SIGDMACH6DONE")]
pub type Sigdmach6done = crate :: Reg < sigdmach6done :: Sigdmach6doneSpec > ; # [doc = "SIGDMACH6DONE"]
pub mod sigdmach6done { # [doc = "Register `SIGDMACH6DONE` reader"]
pub type R = crate :: R < Sigdmach6doneSpec > ; # [doc = "Register `SIGDMACH6DONE` writer"]
pub type W = crate :: W < Sigdmach6doneSpec > ; # [doc = "Field `SIGDMACH6DONE` reader - 31:0\\]
Signature for DMA channel 6 completion (tied to 0x0020 in HW)"]
pub type Sigdmach6doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH6DONE` writer - 31:0\\]
Signature for DMA channel 6 completion (tied to 0x0020 in HW)"]
pub type Sigdmach6doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 6 completion (tied to 0x0020 in HW)"]
# [inline (always)]
pub fn sigdmach6done (& self) -> Sigdmach6doneR { Sigdmach6doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 6 completion (tied to 0x0020 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach6done (& mut self) -> Sigdmach6doneW < Sigdmach6doneSpec > { Sigdmach6doneW :: new (self , 0) } } # [doc = "SIGDMACH6DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach6done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach6done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach6doneSpec ; impl crate :: RegisterSpec for Sigdmach6doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach6done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach6doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach6done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach6doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH6DONE to value 0"]
impl crate :: Resettable for Sigdmach6doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH7DONE (rw) register accessor: SIGDMACH7DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach7done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach7done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach7done`]
module"]
# [doc (alias = "SIGDMACH7DONE")]
pub type Sigdmach7done = crate :: Reg < sigdmach7done :: Sigdmach7doneSpec > ; # [doc = "SIGDMACH7DONE"]
pub mod sigdmach7done { # [doc = "Register `SIGDMACH7DONE` reader"]
pub type R = crate :: R < Sigdmach7doneSpec > ; # [doc = "Register `SIGDMACH7DONE` writer"]
pub type W = crate :: W < Sigdmach7doneSpec > ; # [doc = "Field `SIGDMACH7DONE` reader - 31:0\\]
Signature for DMA channel 7 completion (tied to 0x0040 in HW)"]
pub type Sigdmach7doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH7DONE` writer - 31:0\\]
Signature for DMA channel 7 completion (tied to 0x0040 in HW)"]
pub type Sigdmach7doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 7 completion (tied to 0x0040 in HW)"]
# [inline (always)]
pub fn sigdmach7done (& self) -> Sigdmach7doneR { Sigdmach7doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 7 completion (tied to 0x0040 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach7done (& mut self) -> Sigdmach7doneW < Sigdmach7doneSpec > { Sigdmach7doneW :: new (self , 0) } } # [doc = "SIGDMACH7DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach7done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach7done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach7doneSpec ; impl crate :: RegisterSpec for Sigdmach7doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach7done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach7doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach7done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach7doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH7DONE to value 0"]
impl crate :: Resettable for Sigdmach7doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH8DONE (rw) register accessor: SIGDMACH8DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach8done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach8done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach8done`]
module"]
# [doc (alias = "SIGDMACH8DONE")]
pub type Sigdmach8done = crate :: Reg < sigdmach8done :: Sigdmach8doneSpec > ; # [doc = "SIGDMACH8DONE"]
pub mod sigdmach8done { # [doc = "Register `SIGDMACH8DONE` reader"]
pub type R = crate :: R < Sigdmach8doneSpec > ; # [doc = "Register `SIGDMACH8DONE` writer"]
pub type W = crate :: W < Sigdmach8doneSpec > ; # [doc = "Field `SIGDMACH8DONE` reader - 31:0\\]
Signature for DMA channel 8 completion (tied to 0x0080 in HW)"]
pub type Sigdmach8doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH8DONE` writer - 31:0\\]
Signature for DMA channel 8 completion (tied to 0x0080 in HW)"]
pub type Sigdmach8doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 8 completion (tied to 0x0080 in HW)"]
# [inline (always)]
pub fn sigdmach8done (& self) -> Sigdmach8doneR { Sigdmach8doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 8 completion (tied to 0x0080 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach8done (& mut self) -> Sigdmach8doneW < Sigdmach8doneSpec > { Sigdmach8doneW :: new (self , 0) } } # [doc = "SIGDMACH8DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach8done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach8done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach8doneSpec ; impl crate :: RegisterSpec for Sigdmach8doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach8done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach8doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach8done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach8doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH8DONE to value 0"]
impl crate :: Resettable for Sigdmach8doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH9DONE (rw) register accessor: SIGDMACH9DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach9done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach9done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach9done`]
module"]
# [doc (alias = "SIGDMACH9DONE")]
pub type Sigdmach9done = crate :: Reg < sigdmach9done :: Sigdmach9doneSpec > ; # [doc = "SIGDMACH9DONE"]
pub mod sigdmach9done { # [doc = "Register `SIGDMACH9DONE` reader"]
pub type R = crate :: R < Sigdmach9doneSpec > ; # [doc = "Register `SIGDMACH9DONE` writer"]
pub type W = crate :: W < Sigdmach9doneSpec > ; # [doc = "Field `SIGDMACH9DONE` reader - 31:0\\]
Signature for DMA channel 9 completion (tied to 0x0100 in HW)"]
pub type Sigdmach9doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH9DONE` writer - 31:0\\]
Signature for DMA channel 9 completion (tied to 0x0100 in HW)"]
pub type Sigdmach9doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 9 completion (tied to 0x0100 in HW)"]
# [inline (always)]
pub fn sigdmach9done (& self) -> Sigdmach9doneR { Sigdmach9doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 9 completion (tied to 0x0100 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach9done (& mut self) -> Sigdmach9doneW < Sigdmach9doneSpec > { Sigdmach9doneW :: new (self , 0) } } # [doc = "SIGDMACH9DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach9done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach9done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach9doneSpec ; impl crate :: RegisterSpec for Sigdmach9doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach9done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach9doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach9done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach9doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH9DONE to value 0"]
impl crate :: Resettable for Sigdmach9doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH10DONE (rw) register accessor: SIGDMACH10DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach10done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach10done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach10done`]
module"]
# [doc (alias = "SIGDMACH10DONE")]
pub type Sigdmach10done = crate :: Reg < sigdmach10done :: Sigdmach10doneSpec > ; # [doc = "SIGDMACH10DONE"]
pub mod sigdmach10done { # [doc = "Register `SIGDMACH10DONE` reader"]
pub type R = crate :: R < Sigdmach10doneSpec > ; # [doc = "Register `SIGDMACH10DONE` writer"]
pub type W = crate :: W < Sigdmach10doneSpec > ; # [doc = "Field `SIGDMACH10DONE` reader - 31:0\\]
Signature for DMA channel 10 completion (tied to 0x0200 in HW)"]
pub type Sigdmach10doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH10DONE` writer - 31:0\\]
Signature for DMA channel 10 completion (tied to 0x0200 in HW)"]
pub type Sigdmach10doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 10 completion (tied to 0x0200 in HW)"]
# [inline (always)]
pub fn sigdmach10done (& self) -> Sigdmach10doneR { Sigdmach10doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 10 completion (tied to 0x0200 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach10done (& mut self) -> Sigdmach10doneW < Sigdmach10doneSpec > { Sigdmach10doneW :: new (self , 0) } } # [doc = "SIGDMACH10DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach10done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach10done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach10doneSpec ; impl crate :: RegisterSpec for Sigdmach10doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach10done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach10doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach10done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach10doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH10DONE to value 0"]
impl crate :: Resettable for Sigdmach10doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH11DONE (rw) register accessor: SIGDMACH11DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach11done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach11done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach11done`]
module"]
# [doc (alias = "SIGDMACH11DONE")]
pub type Sigdmach11done = crate :: Reg < sigdmach11done :: Sigdmach11doneSpec > ; # [doc = "SIGDMACH11DONE"]
pub mod sigdmach11done { # [doc = "Register `SIGDMACH11DONE` reader"]
pub type R = crate :: R < Sigdmach11doneSpec > ; # [doc = "Register `SIGDMACH11DONE` writer"]
pub type W = crate :: W < Sigdmach11doneSpec > ; # [doc = "Field `SIGDMACH11DONE` reader - 31:0\\]
Signature for DMA channel 11 completion (tied to 0x0040 in HW)"]
pub type Sigdmach11doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH11DONE` writer - 31:0\\]
Signature for DMA channel 11 completion (tied to 0x0040 in HW)"]
pub type Sigdmach11doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 11 completion (tied to 0x0040 in HW)"]
# [inline (always)]
pub fn sigdmach11done (& self) -> Sigdmach11doneR { Sigdmach11doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 11 completion (tied to 0x0040 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach11done (& mut self) -> Sigdmach11doneW < Sigdmach11doneSpec > { Sigdmach11doneW :: new (self , 0) } } # [doc = "SIGDMACH11DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach11done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach11done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach11doneSpec ; impl crate :: RegisterSpec for Sigdmach11doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach11done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach11doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach11done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach11doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH11DONE to value 0"]
impl crate :: Resettable for Sigdmach11doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH12DONE (rw) register accessor: SIGDMACH12DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach12done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach12done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach12done`]
module"]
# [doc (alias = "SIGDMACH12DONE")]
pub type Sigdmach12done = crate :: Reg < sigdmach12done :: Sigdmach12doneSpec > ; # [doc = "SIGDMACH12DONE"]
pub mod sigdmach12done { # [doc = "Register `SIGDMACH12DONE` reader"]
pub type R = crate :: R < Sigdmach12doneSpec > ; # [doc = "Register `SIGDMACH12DONE` writer"]
pub type W = crate :: W < Sigdmach12doneSpec > ; # [doc = "Field `SIGDMACH12DONE` reader - 31:0\\]
Signature for DMA channel 12 completion (tied to 0x0080 in HW)"]
pub type Sigdmach12doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH12DONE` writer - 31:0\\]
Signature for DMA channel 12 completion (tied to 0x0080 in HW)"]
pub type Sigdmach12doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 12 completion (tied to 0x0080 in HW)"]
# [inline (always)]
pub fn sigdmach12done (& self) -> Sigdmach12doneR { Sigdmach12doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 12 completion (tied to 0x0080 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach12done (& mut self) -> Sigdmach12doneW < Sigdmach12doneSpec > { Sigdmach12doneW :: new (self , 0) } } # [doc = "SIGDMACH12DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach12done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach12done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach12doneSpec ; impl crate :: RegisterSpec for Sigdmach12doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach12done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach12doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach12done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach12doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH12DONE to value 0"]
impl crate :: Resettable for Sigdmach12doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH13DONE (rw) register accessor: SIGDMACH13DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach13done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach13done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach13done`]
module"]
# [doc (alias = "SIGDMACH13DONE")]
pub type Sigdmach13done = crate :: Reg < sigdmach13done :: Sigdmach13doneSpec > ; # [doc = "SIGDMACH13DONE"]
pub mod sigdmach13done { # [doc = "Register `SIGDMACH13DONE` reader"]
pub type R = crate :: R < Sigdmach13doneSpec > ; # [doc = "Register `SIGDMACH13DONE` writer"]
pub type W = crate :: W < Sigdmach13doneSpec > ; # [doc = "Field `SIGDMACH13DONE` reader - 31:0\\]
Signature for DMA channel 13 completion (tied to 0x1000 in HW)"]
pub type Sigdmach13doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH13DONE` writer - 31:0\\]
Signature for DMA channel 13 completion (tied to 0x1000 in HW)"]
pub type Sigdmach13doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 13 completion (tied to 0x1000 in HW)"]
# [inline (always)]
pub fn sigdmach13done (& self) -> Sigdmach13doneR { Sigdmach13doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 13 completion (tied to 0x1000 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach13done (& mut self) -> Sigdmach13doneW < Sigdmach13doneSpec > { Sigdmach13doneW :: new (self , 0) } } # [doc = "SIGDMACH13DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach13done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach13done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach13doneSpec ; impl crate :: RegisterSpec for Sigdmach13doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach13done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach13doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach13done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach13doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH13DONE to value 0"]
impl crate :: Resettable for Sigdmach13doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH14DONE (rw) register accessor: SIGDMACH14DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach14done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach14done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach14done`]
module"]
# [doc (alias = "SIGDMACH14DONE")]
pub type Sigdmach14done = crate :: Reg < sigdmach14done :: Sigdmach14doneSpec > ; # [doc = "SIGDMACH14DONE"]
pub mod sigdmach14done { # [doc = "Register `SIGDMACH14DONE` reader"]
pub type R = crate :: R < Sigdmach14doneSpec > ; # [doc = "Register `SIGDMACH14DONE` writer"]
pub type W = crate :: W < Sigdmach14doneSpec > ; # [doc = "Field `SIGDMACH14DONE` reader - 31:0\\]
Signature for DMA channel 14 completion (tied to 0x2000 in HW)"]
pub type Sigdmach14doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH14DONE` writer - 31:0\\]
Signature for DMA channel 14 completion (tied to 0x2000 in HW)"]
pub type Sigdmach14doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 14 completion (tied to 0x2000 in HW)"]
# [inline (always)]
pub fn sigdmach14done (& self) -> Sigdmach14doneR { Sigdmach14doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 14 completion (tied to 0x2000 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach14done (& mut self) -> Sigdmach14doneW < Sigdmach14doneSpec > { Sigdmach14doneW :: new (self , 0) } } # [doc = "SIGDMACH14DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach14done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach14done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach14doneSpec ; impl crate :: RegisterSpec for Sigdmach14doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach14done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach14doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach14done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach14doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH14DONE to value 0"]
impl crate :: Resettable for Sigdmach14doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH15DONE (rw) register accessor: SIGDMACH15DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach15done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach15done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach15done`]
module"]
# [doc (alias = "SIGDMACH15DONE")]
pub type Sigdmach15done = crate :: Reg < sigdmach15done :: Sigdmach15doneSpec > ; # [doc = "SIGDMACH15DONE"]
pub mod sigdmach15done { # [doc = "Register `SIGDMACH15DONE` reader"]
pub type R = crate :: R < Sigdmach15doneSpec > ; # [doc = "Register `SIGDMACH15DONE` writer"]
pub type W = crate :: W < Sigdmach15doneSpec > ; # [doc = "Field `SIGDMACH15DONE` reader - 31:0\\]
Signature for DMA channel 15 completion (tied to 0x4000 in HW)"]
pub type Sigdmach15doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH15DONE` writer - 31:0\\]
Signature for DMA channel 15 completion (tied to 0x4000 in HW)"]
pub type Sigdmach15doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 15 completion (tied to 0x4000 in HW)"]
# [inline (always)]
pub fn sigdmach15done (& self) -> Sigdmach15doneR { Sigdmach15doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 15 completion (tied to 0x4000 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach15done (& mut self) -> Sigdmach15doneW < Sigdmach15doneSpec > { Sigdmach15doneW :: new (self , 0) } } # [doc = "SIGDMACH15DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach15done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach15done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach15doneSpec ; impl crate :: RegisterSpec for Sigdmach15doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach15done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach15doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach15done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach15doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH15DONE to value 0"]
impl crate :: Resettable for Sigdmach15doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SIGDMACH16DONE (rw) register accessor: SIGDMACH16DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach16done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach16done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigdmach16done`]
module"]
# [doc (alias = "SIGDMACH16DONE")]
pub type Sigdmach16done = crate :: Reg < sigdmach16done :: Sigdmach16doneSpec > ; # [doc = "SIGDMACH16DONE"]
pub mod sigdmach16done { # [doc = "Register `SIGDMACH16DONE` reader"]
pub type R = crate :: R < Sigdmach16doneSpec > ; # [doc = "Register `SIGDMACH16DONE` writer"]
pub type W = crate :: W < Sigdmach16doneSpec > ; # [doc = "Field `SIGDMACH16DONE` reader - 31:0\\]
Signature for DMA channel 16 completion (tied to 0x8000 in HW)"]
pub type Sigdmach16doneR = crate :: FieldReader < u32 > ; # [doc = "Field `SIGDMACH16DONE` writer - 31:0\\]
Signature for DMA channel 16 completion (tied to 0x8000 in HW)"]
pub type Sigdmach16doneW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 16 completion (tied to 0x8000 in HW)"]
# [inline (always)]
pub fn sigdmach16done (& self) -> Sigdmach16doneR { Sigdmach16doneR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Signature for DMA channel 16 completion (tied to 0x8000 in HW)"]
# [inline (always)]
# [must_use]
pub fn sigdmach16done (& mut self) -> Sigdmach16doneW < Sigdmach16doneSpec > { Sigdmach16doneW :: new (self , 0) } } # [doc = "SIGDMACH16DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`sigdmach16done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigdmach16done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sigdmach16doneSpec ; impl crate :: RegisterSpec for Sigdmach16doneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sigdmach16done::R`](R) reader structure"]
impl crate :: Readable for Sigdmach16doneSpec { } # [doc = "`write(|w| ..)` method takes [`sigdmach16done::W`](W) writer structure"]
impl crate :: Writable for Sigdmach16doneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SIGDMACH16DONE to value 0"]
impl crate :: Resettable for Sigdmach16doneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MEMACCESSERR (rw) register accessor: MEMACCESSERR\n\nYou can [`read`](crate::Reg::read) this register and get [`memaccesserr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`memaccesserr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@memaccesserr`]
module"]
# [doc (alias = "MEMACCESSERR")]
pub type Memaccesserr = crate :: Reg < memaccesserr :: MemaccesserrSpec > ; # [doc = "MEMACCESSERR"]
pub mod memaccesserr { # [doc = "Register `MEMACCESSERR` reader"]
pub type R = crate :: R < MemaccesserrSpec > ; # [doc = "Register `MEMACCESSERR` writer"]
pub type W = crate :: W < MemaccesserrSpec > ; # [doc = "Field `ERRCODECLR` reader - 3:0\\]
Reserved.TI internal"]
pub type ErrcodeclrR = crate :: FieldReader ; # [doc = "Field `ERRCODECLR` writer - 3:0\\]
Reserved.TI internal"]
pub type ErrcodeclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ERRCODEMASK` reader - 11:8\\]
Reserved.TI internal"]
pub type ErrcodemaskR = crate :: FieldReader ; # [doc = "Field `ERRCODEMASK` writer - 11:8\\]
Reserved.TI internal"]
pub type ErrcodemaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STATERRCODE` reader - 19:16\\]
Reserved.TI internal"]
pub type StaterrcodeR = crate :: FieldReader ; # [doc = "Field `STATERRCODE` writer - 19:16\\]
Reserved.TI internal"]
pub type StaterrcodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU3` reader - "]
pub type Nu3R = crate :: FieldReader < u16 > ; # [doc = "Field `NU3` writer - "]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn errcodeclr (& self) -> ErrcodeclrR { ErrcodeclrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Reserved.TI internal"]
# [inline (always)]
pub fn errcodemask (& self) -> ErrcodemaskR { ErrcodemaskR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - 19:16\\]
Reserved.TI internal"]
# [inline (always)]
pub fn staterrcode (& self) -> StaterrcodeR { StaterrcodeR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:31"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn errcodeclr (& mut self) -> ErrcodeclrW < MemaccesserrSpec > { ErrcodeclrW :: new (self , 0) } # [doc = "Bits 4:7"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < MemaccesserrSpec > { Nu1W :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn errcodemask (& mut self) -> ErrcodemaskW < MemaccesserrSpec > { ErrcodemaskW :: new (self , 8) } # [doc = "Bits 12:15"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < MemaccesserrSpec > { Nu2W :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn staterrcode (& mut self) -> StaterrcodeW < MemaccesserrSpec > { StaterrcodeW :: new (self , 16) } # [doc = "Bits 20:31"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < MemaccesserrSpec > { Nu3W :: new (self , 20) } } # [doc = "MEMACCESSERR\n\nYou can [`read`](crate::Reg::read) this register and get [`memaccesserr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`memaccesserr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MemaccesserrSpec ; impl crate :: RegisterSpec for MemaccesserrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`memaccesserr::R`](R) reader structure"]
impl crate :: Readable for MemaccesserrSpec { } # [doc = "`write(|w| ..)` method takes [`memaccesserr::W`](W) writer structure"]
impl crate :: Writable for MemaccesserrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MEMACCESSERR to value 0"]
impl crate :: Resettable for MemaccesserrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FFTCLIP (rw) register accessor: FFTCLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`fftclip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftclip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fftclip`]
module"]
# [doc (alias = "FFTCLIP")]
pub type Fftclip = crate :: Reg < fftclip :: FftclipSpec > ; # [doc = "FFTCLIP"]
pub mod fftclip { # [doc = "Register `FFTCLIP` reader"]
pub type R = crate :: R < FftclipSpec > ; # [doc = "Register `FFTCLIP` writer"]
pub type W = crate :: W < FftclipSpec > ; # [doc = "Field `FFTCLIPSTAT` reader - 9:0\\]
FFT Clip Status (read-only): This is a read-only status register, which indicates any saturation/clipping events that have happened in the FFT butterfly stages. Note that each of the 10 butterfly stages in the FFT can be programmed to either saturate the MSB or round the LSB. Whenever saturation of MSB is used in any stage, there is a possibility that that stage can saturate/clip samples. In that case, this saturation event is indicated in the corresponding bit in this status registert. If multiple FFTs are performed, this status register includes any saturation events happening in any of them."]
pub type FftclipstatR = crate :: FieldReader < u16 > ; # [doc = "Field `FFTCLIPSTAT` writer - 9:0\\]
FFT Clip Status (read-only): This is a read-only status register, which indicates any saturation/clipping events that have happened in the FFT butterfly stages. Note that each of the 10 butterfly stages in the FFT can be programmed to either saturate the MSB or round the LSB. Whenever saturation of MSB is used in any stage, there is a possibility that that stage can saturate/clip samples. In that case, this saturation event is indicated in the corresponding bit in this status registert. If multiple FFTs are performed, this status register includes any saturation events happening in any of them."]
pub type FftclipstatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLRFFTCLIPSTAT` reader - 16:16\\]
FFTCLIPSTAT can be cleared by setting single-bit register CLRFFTCLIPSTAT, so that the saturation status indication gets cleared back to 0 and any subsequent saturation events can be freshly monitored."]
pub type ClrfftclipstatR = crate :: BitReader ; # [doc = "Field `CLRFFTCLIPSTAT` writer - 16:16\\]
FFTCLIPSTAT can be cleared by setting single-bit register CLRFFTCLIPSTAT, so that the saturation status indication gets cleared back to 0 and any subsequent saturation events can be freshly monitored."]
pub type ClrfftclipstatW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader < u16 > ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
FFT Clip Status (read-only): This is a read-only status register, which indicates any saturation/clipping events that have happened in the FFT butterfly stages. Note that each of the 10 butterfly stages in the FFT can be programmed to either saturate the MSB or round the LSB. Whenever saturation of MSB is used in any stage, there is a possibility that that stage can saturate/clip samples. In that case, this saturation event is indicated in the corresponding bit in this status registert. If multiple FFTs are performed, this status register includes any saturation events happening in any of them."]
# [inline (always)]
pub fn fftclipstat (& self) -> FftclipstatR { FftclipstatR :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:15"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
FFTCLIPSTAT can be cleared by setting single-bit register CLRFFTCLIPSTAT, so that the saturation status indication gets cleared back to 0 and any subsequent saturation events can be freshly monitored."]
# [inline (always)]
pub fn clrfftclipstat (& self) -> ClrfftclipstatR { ClrfftclipstatR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
FFT Clip Status (read-only): This is a read-only status register, which indicates any saturation/clipping events that have happened in the FFT butterfly stages. Note that each of the 10 butterfly stages in the FFT can be programmed to either saturate the MSB or round the LSB. Whenever saturation of MSB is used in any stage, there is a possibility that that stage can saturate/clip samples. In that case, this saturation event is indicated in the corresponding bit in this status registert. If multiple FFTs are performed, this status register includes any saturation events happening in any of them."]
# [inline (always)]
# [must_use]
pub fn fftclipstat (& mut self) -> FftclipstatW < FftclipSpec > { FftclipstatW :: new (self , 0) } # [doc = "Bits 10:15"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < FftclipSpec > { Nu1W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
FFTCLIPSTAT can be cleared by setting single-bit register CLRFFTCLIPSTAT, so that the saturation status indication gets cleared back to 0 and any subsequent saturation events can be freshly monitored."]
# [inline (always)]
# [must_use]
pub fn clrfftclipstat (& mut self) -> ClrfftclipstatW < FftclipSpec > { ClrfftclipstatW :: new (self , 16) } # [doc = "Bits 17:31"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < FftclipSpec > { Nu2W :: new (self , 17) } } # [doc = "FFTCLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`fftclip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftclip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FftclipSpec ; impl crate :: RegisterSpec for FftclipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fftclip::R`](R) reader structure"]
impl crate :: Readable for FftclipSpec { } # [doc = "`write(|w| ..)` method takes [`fftclip::W`](W) writer structure"]
impl crate :: Writable for FftclipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FFTCLIP to value 0"]
impl crate :: Resettable for FftclipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FFTPEAKCNT (rw) register accessor: FFTPEAKCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`fftpeakcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftpeakcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fftpeakcnt`]
module"]
# [doc (alias = "FFTPEAKCNT")]
pub type Fftpeakcnt = crate :: Reg < fftpeakcnt :: FftpeakcntSpec > ; # [doc = "FFTPEAKCNT"]
pub mod fftpeakcnt { # [doc = "Register `FFTPEAKCNT` reader"]
pub type R = crate :: R < FftpeakcntSpec > ; # [doc = "Register `FFTPEAKCNT` writer"]
pub type W = crate :: W < FftpeakcntSpec > ; # [doc = "Field `FFTPEAKCNT` reader - 11:0\\]
CFAR Detected Peak Count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory, when CFAR Engine is configured in Detected Peaks List mode."]
pub type FftpeakcntR = crate :: FieldReader < u16 > ; # [doc = "Field `FFTPEAKCNT` writer - 11:0\\]
CFAR Detected Peak Count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory, when CFAR Engine is configured in Detected Peaks List mode."]
pub type FftpeakcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
CFAR Detected Peak Count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory, when CFAR Engine is configured in Detected Peaks List mode."]
# [inline (always)]
pub fn fftpeakcnt (& self) -> FftpeakcntR { FftpeakcntR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
CFAR Detected Peak Count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory, when CFAR Engine is configured in Detected Peaks List mode."]
# [inline (always)]
# [must_use]
pub fn fftpeakcnt (& mut self) -> FftpeakcntW < FftpeakcntSpec > { FftpeakcntW :: new (self , 0) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < FftpeakcntSpec > { NuW :: new (self , 12) } } # [doc = "FFTPEAKCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`fftpeakcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftpeakcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FftpeakcntSpec ; impl crate :: RegisterSpec for FftpeakcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fftpeakcnt::R`](R) reader structure"]
impl crate :: Readable for FftpeakcntSpec { } # [doc = "`write(|w| ..)` method takes [`fftpeakcnt::W`](W) writer structure"]
impl crate :: Writable for FftpeakcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FFTPEAKCNT to value 0"]
impl crate :: Resettable for FftpeakcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG1RD (rw) register accessor: HWACCREG1RD\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg1rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg1rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg1rd`]
module"]
# [doc (alias = "HWACCREG1RD")]
pub type Hwaccreg1rd = crate :: Reg < hwaccreg1rd :: Hwaccreg1rdSpec > ; # [doc = "HWACCREG1RD"]
pub mod hwaccreg1rd { # [doc = "Register `HWACCREG1RD` reader"]
pub type R = crate :: R < Hwaccreg1rdSpec > ; # [doc = "Register `HWACCREG1RD` writer"]
pub type W = crate :: W < Hwaccreg1rdSpec > ; # [doc = "Field `HWACCREG1RD` reader - 31:0\\]
Reserved.TI internal"]
pub type Hwaccreg1rdR = crate :: FieldReader < u32 > ; # [doc = "Field `HWACCREG1RD` writer - 31:0\\]
Reserved.TI internal"]
pub type Hwaccreg1rdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn hwaccreg1rd (& self) -> Hwaccreg1rdR { Hwaccreg1rdR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn hwaccreg1rd (& mut self) -> Hwaccreg1rdW < Hwaccreg1rdSpec > { Hwaccreg1rdW :: new (self , 0) } } # [doc = "HWACCREG1RD\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg1rd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg1rd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg1rdSpec ; impl crate :: RegisterSpec for Hwaccreg1rdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg1rd::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg1rdSpec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg1rd::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg1rdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG1RD to value 0"]
impl crate :: Resettable for Hwaccreg1rdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG2RD (rw) register accessor: HWACCREG2RD\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg2rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg2rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg2rd`]
module"]
# [doc (alias = "HWACCREG2RD")]
pub type Hwaccreg2rd = crate :: Reg < hwaccreg2rd :: Hwaccreg2rdSpec > ; # [doc = "HWACCREG2RD"]
pub mod hwaccreg2rd { # [doc = "Register `HWACCREG2RD` reader"]
pub type R = crate :: R < Hwaccreg2rdSpec > ; # [doc = "Register `HWACCREG2RD` writer"]
pub type W = crate :: W < Hwaccreg2rdSpec > ; # [doc = "Field `HWACCREG2RD` reader - 31:0\\]
Reserved.TI internal"]
pub type Hwaccreg2rdR = crate :: FieldReader < u32 > ; # [doc = "Field `HWACCREG2RD` writer - 31:0\\]
Reserved.TI internal"]
pub type Hwaccreg2rdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn hwaccreg2rd (& self) -> Hwaccreg2rdR { Hwaccreg2rdR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn hwaccreg2rd (& mut self) -> Hwaccreg2rdW < Hwaccreg2rdSpec > { Hwaccreg2rdW :: new (self , 0) } } # [doc = "HWACCREG2RD\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg2rd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg2rd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg2rdSpec ; impl crate :: RegisterSpec for Hwaccreg2rdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg2rd::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg2rdSpec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg2rd::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg2rdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG2RD to value 0"]
impl crate :: Resettable for Hwaccreg2rdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG3RD (rw) register accessor: HWACCREG3RD\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg3rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg3rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg3rd`]
module"]
# [doc (alias = "HWACCREG3RD")]
pub type Hwaccreg3rd = crate :: Reg < hwaccreg3rd :: Hwaccreg3rdSpec > ; # [doc = "HWACCREG3RD"]
pub mod hwaccreg3rd { # [doc = "Register `HWACCREG3RD` reader"]
pub type R = crate :: R < Hwaccreg3rdSpec > ; # [doc = "Register `HWACCREG3RD` writer"]
pub type W = crate :: W < Hwaccreg3rdSpec > ; # [doc = "Field `HWACCREG3RD` reader - 31:0\\]
Reserved.TI internal"]
pub type Hwaccreg3rdR = crate :: FieldReader < u32 > ; # [doc = "Field `HWACCREG3RD` writer - 31:0\\]
Reserved.TI internal"]
pub type Hwaccreg3rdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn hwaccreg3rd (& self) -> Hwaccreg3rdR { Hwaccreg3rdR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn hwaccreg3rd (& mut self) -> Hwaccreg3rdW < Hwaccreg3rdSpec > { Hwaccreg3rdW :: new (self , 0) } } # [doc = "HWACCREG3RD\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg3rd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg3rd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg3rdSpec ; impl crate :: RegisterSpec for Hwaccreg3rdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg3rd::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg3rdSpec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg3rd::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg3rdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG3RD to value 0"]
impl crate :: Resettable for Hwaccreg3rdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMP_EGE_K0123 (rw) register accessor: CMP_EGE_K0123\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp_ege_k0123::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp_ege_k0123::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp_ege_k0123`]
module"]
# [doc (alias = "CMP_EGE_K0123")]
pub type CmpEgeK0123 = crate :: Reg < cmp_ege_k0123 :: CmpEgeK0123Spec > ; # [doc = "CMP_EGE_K0123"]
pub mod cmp_ege_k0123 { # [doc = "Register `CMP_EGE_K0123` reader"]
pub type R = crate :: R < CmpEgeK0123Spec > ; # [doc = "Register `CMP_EGE_K0123` writer"]
pub type W = crate :: W < CmpEgeK0123Spec > ; # [doc = "Field `CMP_EGE_K0` reader - 4:0\\]
EGE K-param for the 1st accumulator"]
pub type CmpEgeK0R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K0` writer - 4:0\\]
EGE K-param for the 1st accumulator"]
pub type CmpEgeK0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU1` reader - 7:5\\]
Reserved.TI internal"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:5\\]
Reserved.TI internal"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CMP_EGE_K1` reader - 12:8\\]
EGE K-param for the 2nd accumulator"]
pub type CmpEgeK1R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K1` writer - 12:8\\]
EGE K-param for the 2nd accumulator"]
pub type CmpEgeK1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU2` reader - 15:13\\]
Reserved.TI internal"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 15:13\\]
Reserved.TI internal"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CMP_EGE_K2` reader - 20:16\\]
EGE K-param for the 3rd accumulator"]
pub type CmpEgeK2R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K2` writer - 20:16\\]
EGE K-param for the 3rd accumulator"]
pub type CmpEgeK2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU3` reader - 23:21\\]
Reserved.TI internal"]
pub type Nu3R = crate :: FieldReader ; # [doc = "Field `NU3` writer - 23:21\\]
Reserved.TI internal"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CMP_EGE_K3` reader - 28:24\\]
EGE K-param for the 4th accumulator"]
pub type CmpEgeK3R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K3` writer - 28:24\\]
EGE K-param for the 4th accumulator"]
pub type CmpEgeK3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU4` reader - 31:29\\]
Reserved.TI internal"]
pub type Nu4R = crate :: FieldReader ; # [doc = "Field `NU4` writer - 31:29\\]
Reserved.TI internal"]
pub type Nu4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
EGE K-param for the 1st accumulator"]
# [inline (always)]
pub fn cmp_ege_k0 (& self) -> CmpEgeK0R { CmpEgeK0R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:7 - 7:5\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:12 - 12:8\\]
EGE K-param for the 2nd accumulator"]
# [inline (always)]
pub fn cmp_ege_k1 (& self) -> CmpEgeK1R { CmpEgeK1R :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
EGE K-param for the 3rd accumulator"]
# [inline (always)]
pub fn cmp_ege_k2 (& self) -> CmpEgeK2R { CmpEgeK2R :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:28 - 28:24\\]
EGE K-param for the 4th accumulator"]
# [inline (always)]
pub fn cmp_ege_k3 (& self) -> CmpEgeK3R { CmpEgeK3R :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
EGE K-param for the 1st accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k0 (& mut self) -> CmpEgeK0W < CmpEgeK0123Spec > { CmpEgeK0W :: new (self , 0) } # [doc = "Bits 5:7 - 7:5\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < CmpEgeK0123Spec > { Nu1W :: new (self , 5) } # [doc = "Bits 8:12 - 12:8\\]
EGE K-param for the 2nd accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k1 (& mut self) -> CmpEgeK1W < CmpEgeK0123Spec > { CmpEgeK1W :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < CmpEgeK0123Spec > { Nu2W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
EGE K-param for the 3rd accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k2 (& mut self) -> CmpEgeK2W < CmpEgeK0123Spec > { CmpEgeK2W :: new (self , 16) } # [doc = "Bits 21:23 - 23:21\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < CmpEgeK0123Spec > { Nu3W :: new (self , 21) } # [doc = "Bits 24:28 - 28:24\\]
EGE K-param for the 4th accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k3 (& mut self) -> CmpEgeK3W < CmpEgeK0123Spec > { CmpEgeK3W :: new (self , 24) } # [doc = "Bits 29:31 - 31:29\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < CmpEgeK0123Spec > { Nu4W :: new (self , 29) } } # [doc = "CMP_EGE_K0123\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp_ege_k0123::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp_ege_k0123::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpEgeK0123Spec ; impl crate :: RegisterSpec for CmpEgeK0123Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmp_ege_k0123::R`](R) reader structure"]
impl crate :: Readable for CmpEgeK0123Spec { } # [doc = "`write(|w| ..)` method takes [`cmp_ege_k0123::W`](W) writer structure"]
impl crate :: Writable for CmpEgeK0123Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMP_EGE_K0123 to value 0"]
impl crate :: Resettable for CmpEgeK0123Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMP_EGE_K4567 (rw) register accessor: CMP_EGE_K4567\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp_ege_k4567::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp_ege_k4567::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp_ege_k4567`]
module"]
# [doc (alias = "CMP_EGE_K4567")]
pub type CmpEgeK4567 = crate :: Reg < cmp_ege_k4567 :: CmpEgeK4567Spec > ; # [doc = "CMP_EGE_K4567"]
pub mod cmp_ege_k4567 { # [doc = "Register `CMP_EGE_K4567` reader"]
pub type R = crate :: R < CmpEgeK4567Spec > ; # [doc = "Register `CMP_EGE_K4567` writer"]
pub type W = crate :: W < CmpEgeK4567Spec > ; # [doc = "Field `CMP_EGE_K4` reader - 4:0\\]
EGE K-param for the 5th accumulator"]
pub type CmpEgeK4R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K4` writer - 4:0\\]
EGE K-param for the 5th accumulator"]
pub type CmpEgeK4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU1` reader - 7:5\\]
Reserved.TI internal"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:5\\]
Reserved.TI internal"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CMP_EGE_K5` reader - 12:8\\]
EGE K-param for the 6th accumulator"]
pub type CmpEgeK5R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K5` writer - 12:8\\]
EGE K-param for the 6th accumulator"]
pub type CmpEgeK5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU2` reader - 15:13\\]
Reserved.TI internal"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 15:13\\]
Reserved.TI internal"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CMP_EGE_K6` reader - 20:16\\]
EGE K-param for the 7th accumulator"]
pub type CmpEgeK6R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K6` writer - 20:16\\]
EGE K-param for the 7th accumulator"]
pub type CmpEgeK6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU3` reader - 23:21\\]
Reserved.TI internal"]
pub type Nu3R = crate :: FieldReader ; # [doc = "Field `NU3` writer - 23:21\\]
Reserved.TI internal"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CMP_EGE_K7` reader - 28:24\\]
EGE K-param for the 8th accumulator"]
pub type CmpEgeK7R = crate :: FieldReader ; # [doc = "Field `CMP_EGE_K7` writer - 28:24\\]
EGE K-param for the 8th accumulator"]
pub type CmpEgeK7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU4` reader - 31:29\\]
Reserved.TI internal"]
pub type Nu4R = crate :: FieldReader ; # [doc = "Field `NU4` writer - 31:29\\]
Reserved.TI internal"]
pub type Nu4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
EGE K-param for the 5th accumulator"]
# [inline (always)]
pub fn cmp_ege_k4 (& self) -> CmpEgeK4R { CmpEgeK4R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:7 - 7:5\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:12 - 12:8\\]
EGE K-param for the 6th accumulator"]
# [inline (always)]
pub fn cmp_ege_k5 (& self) -> CmpEgeK5R { CmpEgeK5R :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
EGE K-param for the 7th accumulator"]
# [inline (always)]
pub fn cmp_ege_k6 (& self) -> CmpEgeK6R { CmpEgeK6R :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:28 - 28:24\\]
EGE K-param for the 8th accumulator"]
# [inline (always)]
pub fn cmp_ege_k7 (& self) -> CmpEgeK7R { CmpEgeK7R :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
EGE K-param for the 5th accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k4 (& mut self) -> CmpEgeK4W < CmpEgeK4567Spec > { CmpEgeK4W :: new (self , 0) } # [doc = "Bits 5:7 - 7:5\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < CmpEgeK4567Spec > { Nu1W :: new (self , 5) } # [doc = "Bits 8:12 - 12:8\\]
EGE K-param for the 6th accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k5 (& mut self) -> CmpEgeK5W < CmpEgeK4567Spec > { CmpEgeK5W :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < CmpEgeK4567Spec > { Nu2W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
EGE K-param for the 7th accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k6 (& mut self) -> CmpEgeK6W < CmpEgeK4567Spec > { CmpEgeK6W :: new (self , 16) } # [doc = "Bits 21:23 - 23:21\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < CmpEgeK4567Spec > { Nu3W :: new (self , 21) } # [doc = "Bits 24:28 - 28:24\\]
EGE K-param for the 8th accumulator"]
# [inline (always)]
# [must_use]
pub fn cmp_ege_k7 (& mut self) -> CmpEgeK7W < CmpEgeK4567Spec > { CmpEgeK7W :: new (self , 24) } # [doc = "Bits 29:31 - 31:29\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < CmpEgeK4567Spec > { Nu4W :: new (self , 29) } } # [doc = "CMP_EGE_K4567\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp_ege_k4567::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp_ege_k4567::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpEgeK4567Spec ; impl crate :: RegisterSpec for CmpEgeK4567Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmp_ege_k4567::R`](R) reader structure"]
impl crate :: Readable for CmpEgeK4567Spec { } # [doc = "`write(|w| ..)` method takes [`cmp_ege_k4567::W`](W) writer structure"]
impl crate :: Writable for CmpEgeK4567Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMP_EGE_K4567 to value 0"]
impl crate :: Resettable for CmpEgeK4567Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_ENABLE (rw) register accessor: HWA_SAFETY_ENABLE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_enable`]
module"]
# [doc (alias = "HWA_SAFETY_ENABLE")]
pub type HwaSafetyEnable = crate :: Reg < hwa_safety_enable :: HwaSafetyEnableSpec > ; # [doc = "HWA_SAFETY_ENABLE"]
pub mod hwa_safety_enable { # [doc = "Register `HWA_SAFETY_ENABLE` reader"]
pub type R = crate :: R < HwaSafetyEnableSpec > ; # [doc = "Register `HWA_SAFETY_ENABLE` writer"]
pub type W = crate :: W < HwaSafetyEnableSpec > ; # [doc = "Field `WIN_RAM_PARITY_EN` reader - 0:0\\]
1: Enable PARITY for Window RAM"]
pub type WinRamParityEnR = crate :: BitReader ; # [doc = "Field `WIN_RAM_PARITY_EN` writer - 0:0\\]
1: Enable PARITY for Window RAM"]
pub type WinRamParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARAM_ECC_EN` reader - 1:1\\]
Not used."]
pub type ParamEccEnR = crate :: BitReader ; # [doc = "Field `PARAM_ECC_EN` writer - 1:1\\]
Not used."]
pub type ParamEccEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `IPING_PARITY_EN` reader - 12:12\\]
1: Enable PARITY for ACCEL_MEM0"]
pub type IpingParityEnR = crate :: BitReader ; # [doc = "Field `IPING_PARITY_EN` writer - 12:12\\]
1: Enable PARITY for ACCEL_MEM0"]
pub type IpingParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IPONG_PARITY_EN` reader - 13:13\\]
1: Enable PARITY for ACCEL_MEM1"]
pub type IpongParityEnR = crate :: BitReader ; # [doc = "Field `IPONG_PARITY_EN` writer - 13:13\\]
1: Enable PARITY for ACCEL_MEM1"]
pub type IpongParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPING_PARITY_EN` reader - 14:14\\]
1: Enable PARITY for ACCEL_MEM2"]
pub type OpingParityEnR = crate :: BitReader ; # [doc = "Field `OPING_PARITY_EN` writer - 14:14\\]
1: Enable PARITY for ACCEL_MEM2"]
pub type OpingParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPONG_PARITY_EN` reader - 15:15\\]
1: Enable PARITY for ACCEL_MEM3"]
pub type OpongParityEnR = crate :: BitReader ; # [doc = "Field `OPONG_PARITY_EN` writer - 15:15\\]
1: Enable PARITY for ACCEL_MEM3"]
pub type OpongParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FSM_LOCKSTEP_EN` reader - 16:16\\]
1: Enable Lockstep for Accelerator FSM"]
pub type FsmLockstepEnR = crate :: BitReader ; # [doc = "Field `FSM_LOCKSTEP_EN` writer - 16:16\\]
1: Enable Lockstep for Accelerator FSM"]
pub type FsmLockstepEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FSM_LOCKSTEP_SELFTEST_EN` reader - 17:17\\]
1: Enable Selftest for Accelerator FSM"]
pub type FsmLockstepSelftestEnR = crate :: BitReader ; # [doc = "Field `FSM_LOCKSTEP_SELFTEST_EN` writer - 17:17\\]
1: Enable Selftest for Accelerator FSM"]
pub type FsmLockstepSelftestEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader < u16 > ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
1: Enable PARITY for Window RAM"]
# [inline (always)]
pub fn win_ram_parity_en (& self) -> WinRamParityEnR { WinRamParityEnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Not used."]
# [inline (always)]
pub fn param_ecc_en (& self) -> ParamEccEnR { ParamEccEnR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:11"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 2) & 0x03ff) as u16) } # [doc = "Bit 12 - 12:12\\]
1: Enable PARITY for ACCEL_MEM0"]
# [inline (always)]
pub fn iping_parity_en (& self) -> IpingParityEnR { IpingParityEnR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
1: Enable PARITY for ACCEL_MEM1"]
# [inline (always)]
pub fn ipong_parity_en (& self) -> IpongParityEnR { IpongParityEnR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
1: Enable PARITY for ACCEL_MEM2"]
# [inline (always)]
pub fn oping_parity_en (& self) -> OpingParityEnR { OpingParityEnR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
1: Enable PARITY for ACCEL_MEM3"]
# [inline (always)]
pub fn opong_parity_en (& self) -> OpongParityEnR { OpongParityEnR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
1: Enable Lockstep for Accelerator FSM"]
# [inline (always)]
pub fn fsm_lockstep_en (& self) -> FsmLockstepEnR { FsmLockstepEnR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
1: Enable Selftest for Accelerator FSM"]
# [inline (always)]
pub fn fsm_lockstep_selftest_en (& self) -> FsmLockstepSelftestEnR { FsmLockstepSelftestEnR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:31"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
1: Enable PARITY for Window RAM"]
# [inline (always)]
# [must_use]
pub fn win_ram_parity_en (& mut self) -> WinRamParityEnW < HwaSafetyEnableSpec > { WinRamParityEnW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Not used."]
# [inline (always)]
# [must_use]
pub fn param_ecc_en (& mut self) -> ParamEccEnW < HwaSafetyEnableSpec > { ParamEccEnW :: new (self , 1) } # [doc = "Bits 2:11"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < HwaSafetyEnableSpec > { Nu1W :: new (self , 2) } # [doc = "Bit 12 - 12:12\\]
1: Enable PARITY for ACCEL_MEM0"]
# [inline (always)]
# [must_use]
pub fn iping_parity_en (& mut self) -> IpingParityEnW < HwaSafetyEnableSpec > { IpingParityEnW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
1: Enable PARITY for ACCEL_MEM1"]
# [inline (always)]
# [must_use]
pub fn ipong_parity_en (& mut self) -> IpongParityEnW < HwaSafetyEnableSpec > { IpongParityEnW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
1: Enable PARITY for ACCEL_MEM2"]
# [inline (always)]
# [must_use]
pub fn oping_parity_en (& mut self) -> OpingParityEnW < HwaSafetyEnableSpec > { OpingParityEnW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
1: Enable PARITY for ACCEL_MEM3"]
# [inline (always)]
# [must_use]
pub fn opong_parity_en (& mut self) -> OpongParityEnW < HwaSafetyEnableSpec > { OpongParityEnW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
1: Enable Lockstep for Accelerator FSM"]
# [inline (always)]
# [must_use]
pub fn fsm_lockstep_en (& mut self) -> FsmLockstepEnW < HwaSafetyEnableSpec > { FsmLockstepEnW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
1: Enable Selftest for Accelerator FSM"]
# [inline (always)]
# [must_use]
pub fn fsm_lockstep_selftest_en (& mut self) -> FsmLockstepSelftestEnW < HwaSafetyEnableSpec > { FsmLockstepSelftestEnW :: new (self , 17) } # [doc = "Bits 18:31"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < HwaSafetyEnableSpec > { Nu2W :: new (self , 18) } } # [doc = "HWA_SAFETY_ENABLE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyEnableSpec ; impl crate :: RegisterSpec for HwaSafetyEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_enable::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyEnableSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_enable::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_ENABLE to value 0"]
impl crate :: Resettable for HwaSafetyEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MEMINIT (rw) register accessor: MEMINIT\n\nYou can [`read`](crate::Reg::read) this register and get [`meminit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`meminit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meminit`]
module"]
# [doc (alias = "MEMINIT")]
pub type Meminit = crate :: Reg < meminit :: MeminitSpec > ; # [doc = "MEMINIT"]
pub mod meminit { # [doc = "Register `MEMINIT` reader"]
pub type R = crate :: R < MeminitSpec > ; # [doc = "Register `MEMINIT` writer"]
pub type W = crate :: W < MeminitSpec > ; # [doc = "Field `WIN_RAM_INIT` reader - 0:0\\]
1: Start initialising Window RAM with all '0's"]
pub type WinRamInitR = crate :: BitReader ; # [doc = "Field `WIN_RAM_INIT` writer - 0:0\\]
1: Start initialising Window RAM with all '0's"]
pub type WinRamInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARAM_INIT` reader - 1:1\\]
1: Start initialising Parameter set RAM with all '0's"]
pub type ParamInitR = crate :: BitReader ; # [doc = "Field `PARAM_INIT` writer - 1:1\\]
1: Start initialising Parameter set RAM with all '0's"]
pub type ParamInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IPING_INIT` reader - 2:2\\]
1: Start initialising ACCEL_MEM0 with all '0's"]
pub type IpingInitR = crate :: BitReader ; # [doc = "Field `IPING_INIT` writer - 2:2\\]
1: Start initialising ACCEL_MEM0 with all '0's"]
pub type IpingInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IPONG_INIT` reader - 3:3\\]
1: Start initialising ACCEL_MEM1 with all '0's"]
pub type IpongInitR = crate :: BitReader ; # [doc = "Field `IPONG_INIT` writer - 3:3\\]
1: Start initialising ACCEL_MEM1 with all '0's"]
pub type IpongInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPING_INIT` reader - 4:4\\]
1: Start initialising ACCEL_MEM2 with all '0's"]
pub type OpingInitR = crate :: BitReader ; # [doc = "Field `OPING_INIT` writer - 4:4\\]
1: Start initialising ACCEL_MEM2 with all '0's"]
pub type OpingInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPONG_INIT` reader - 5:5\\]
1: Start initialising ACCEL_MEM3 with all '0's"]
pub type OpongInitR = crate :: BitReader ; # [doc = "Field `OPONG_INIT` writer - 5:5\\]
1: Start initialising ACCEL_MEM3 with all '0's"]
pub type OpongInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MC_EVEN_INIT` reader - 6:6\\]
1: Start initialising MEM_COMPRESSION_EVEN_RAM with all '0's"]
pub type McEvenInitR = crate :: BitReader ; # [doc = "Field `MC_EVEN_INIT` writer - 6:6\\]
1: Start initialising MEM_COMPRESSION_EVEN_RAM with all '0's"]
pub type McEvenInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MC_ODD_INIT` reader - 7:7\\]
1: Start initialising MEM_COMPRESSION_ODD_RAM with all '0's"]
pub type McOddInitR = crate :: BitReader ; # [doc = "Field `MC_ODD_INIT` writer - 7:7\\]
1: Start initialising MEM_COMPRESSION_ODD_RAM with all '0's"]
pub type McOddInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
1: Start initialising Window RAM with all '0's"]
# [inline (always)]
pub fn win_ram_init (& self) -> WinRamInitR { WinRamInitR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1: Start initialising Parameter set RAM with all '0's"]
# [inline (always)]
pub fn param_init (& self) -> ParamInitR { ParamInitR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
1: Start initialising ACCEL_MEM0 with all '0's"]
# [inline (always)]
pub fn iping_init (& self) -> IpingInitR { IpingInitR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
1: Start initialising ACCEL_MEM1 with all '0's"]
# [inline (always)]
pub fn ipong_init (& self) -> IpongInitR { IpongInitR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
1: Start initialising ACCEL_MEM2 with all '0's"]
# [inline (always)]
pub fn oping_init (& self) -> OpingInitR { OpingInitR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
1: Start initialising ACCEL_MEM3 with all '0's"]
# [inline (always)]
pub fn opong_init (& self) -> OpongInitR { OpongInitR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
1: Start initialising MEM_COMPRESSION_EVEN_RAM with all '0's"]
# [inline (always)]
pub fn mc_even_init (& self) -> McEvenInitR { McEvenInitR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
1: Start initialising MEM_COMPRESSION_ODD_RAM with all '0's"]
# [inline (always)]
pub fn mc_odd_init (& self) -> McOddInitR { McOddInitR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
1: Start initialising Window RAM with all '0's"]
# [inline (always)]
# [must_use]
pub fn win_ram_init (& mut self) -> WinRamInitW < MeminitSpec > { WinRamInitW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1: Start initialising Parameter set RAM with all '0's"]
# [inline (always)]
# [must_use]
pub fn param_init (& mut self) -> ParamInitW < MeminitSpec > { ParamInitW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
1: Start initialising ACCEL_MEM0 with all '0's"]
# [inline (always)]
# [must_use]
pub fn iping_init (& mut self) -> IpingInitW < MeminitSpec > { IpingInitW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
1: Start initialising ACCEL_MEM1 with all '0's"]
# [inline (always)]
# [must_use]
pub fn ipong_init (& mut self) -> IpongInitW < MeminitSpec > { IpongInitW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
1: Start initialising ACCEL_MEM2 with all '0's"]
# [inline (always)]
# [must_use]
pub fn oping_init (& mut self) -> OpingInitW < MeminitSpec > { OpingInitW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
1: Start initialising ACCEL_MEM3 with all '0's"]
# [inline (always)]
# [must_use]
pub fn opong_init (& mut self) -> OpongInitW < MeminitSpec > { OpongInitW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
1: Start initialising MEM_COMPRESSION_EVEN_RAM with all '0's"]
# [inline (always)]
# [must_use]
pub fn mc_even_init (& mut self) -> McEvenInitW < MeminitSpec > { McEvenInitW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
1: Start initialising MEM_COMPRESSION_ODD_RAM with all '0's"]
# [inline (always)]
# [must_use]
pub fn mc_odd_init (& mut self) -> McOddInitW < MeminitSpec > { McOddInitW :: new (self , 7) } # [doc = "Bits 8:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < MeminitSpec > { NuW :: new (self , 8) } } # [doc = "MEMINIT\n\nYou can [`read`](crate::Reg::read) this register and get [`meminit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`meminit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MeminitSpec ; impl crate :: RegisterSpec for MeminitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`meminit::R`](R) reader structure"]
impl crate :: Readable for MeminitSpec { } # [doc = "`write(|w| ..)` method takes [`meminit::W`](W) writer structure"]
impl crate :: Writable for MeminitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MEMINIT to value 0"]
impl crate :: Resettable for MeminitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MEMINITDONE (rw) register accessor: MEMINITDONE\n\nYou can [`read`](crate::Reg::read) this register and get [`meminitdone::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`meminitdone::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meminitdone`]
module"]
# [doc (alias = "MEMINITDONE")]
pub type Meminitdone = crate :: Reg < meminitdone :: MeminitdoneSpec > ; # [doc = "MEMINITDONE"]
pub mod meminitdone { # [doc = "Register `MEMINITDONE` reader"]
pub type R = crate :: R < MeminitdoneSpec > ; # [doc = "Register `MEMINITDONE` writer"]
pub type W = crate :: W < MeminitdoneSpec > ; # [doc = "Field `WIN_RAM_INITDONE` reader - 0:0\\]
1: Init done status for Window RAM"]
pub type WinRamInitdoneR = crate :: BitReader ; # [doc = "Field `WIN_RAM_INITDONE` writer - 0:0\\]
1: Init done status for Window RAM"]
pub type WinRamInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARAM_INITDONE` reader - 1:1\\]
1: Init done status for Parameter set RAM"]
pub type ParamInitdoneR = crate :: BitReader ; # [doc = "Field `PARAM_INITDONE` writer - 1:1\\]
1: Init done status for Parameter set RAM"]
pub type ParamInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IPING_INITDONE` reader - 2:2\\]
1: Init done status for ACCEL_MEM0"]
pub type IpingInitdoneR = crate :: BitReader ; # [doc = "Field `IPING_INITDONE` writer - 2:2\\]
1: Init done status for ACCEL_MEM0"]
pub type IpingInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IPONG_INITDONE` reader - 3:3\\]
1: Init done status for ACCEL_MEM1"]
pub type IpongInitdoneR = crate :: BitReader ; # [doc = "Field `IPONG_INITDONE` writer - 3:3\\]
1: Init done status for ACCEL_MEM1"]
pub type IpongInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPING_INITDONE` reader - 4:4\\]
1: Init done status for ACCEL_MEM2"]
pub type OpingInitdoneR = crate :: BitReader ; # [doc = "Field `OPING_INITDONE` writer - 4:4\\]
1: Init done status for ACCEL_MEM2"]
pub type OpingInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPONG_INITDONE` reader - 5:5\\]
1: Init done status for ACCEL_MEM3"]
pub type OpongInitdoneR = crate :: BitReader ; # [doc = "Field `OPONG_INITDONE` writer - 5:5\\]
1: Init done status for ACCEL_MEM3"]
pub type OpongInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MC_EVEN_INITDONE` reader - 6:6\\]
1: Init done status for MEM_COMPRESSION_EVEN_RAM"]
pub type McEvenInitdoneR = crate :: BitReader ; # [doc = "Field `MC_EVEN_INITDONE` writer - 6:6\\]
1: Init done status for MEM_COMPRESSION_EVEN_RAM"]
pub type McEvenInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MC_ODD_INITDONE` reader - 7:7\\]
1: Init done status for MEM_COMPRESSION_ODD_RAM"]
pub type McOddInitdoneR = crate :: BitReader ; # [doc = "Field `MC_ODD_INITDONE` writer - 7:7\\]
1: Init done status for MEM_COMPRESSION_ODD_RAM"]
pub type McOddInitdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
1: Init done status for Window RAM"]
# [inline (always)]
pub fn win_ram_initdone (& self) -> WinRamInitdoneR { WinRamInitdoneR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1: Init done status for Parameter set RAM"]
# [inline (always)]
pub fn param_initdone (& self) -> ParamInitdoneR { ParamInitdoneR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
1: Init done status for ACCEL_MEM0"]
# [inline (always)]
pub fn iping_initdone (& self) -> IpingInitdoneR { IpingInitdoneR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
1: Init done status for ACCEL_MEM1"]
# [inline (always)]
pub fn ipong_initdone (& self) -> IpongInitdoneR { IpongInitdoneR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
1: Init done status for ACCEL_MEM2"]
# [inline (always)]
pub fn oping_initdone (& self) -> OpingInitdoneR { OpingInitdoneR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
1: Init done status for ACCEL_MEM3"]
# [inline (always)]
pub fn opong_initdone (& self) -> OpongInitdoneR { OpongInitdoneR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
1: Init done status for MEM_COMPRESSION_EVEN_RAM"]
# [inline (always)]
pub fn mc_even_initdone (& self) -> McEvenInitdoneR { McEvenInitdoneR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
1: Init done status for MEM_COMPRESSION_ODD_RAM"]
# [inline (always)]
pub fn mc_odd_initdone (& self) -> McOddInitdoneR { McOddInitdoneR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
1: Init done status for Window RAM"]
# [inline (always)]
# [must_use]
pub fn win_ram_initdone (& mut self) -> WinRamInitdoneW < MeminitdoneSpec > { WinRamInitdoneW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1: Init done status for Parameter set RAM"]
# [inline (always)]
# [must_use]
pub fn param_initdone (& mut self) -> ParamInitdoneW < MeminitdoneSpec > { ParamInitdoneW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
1: Init done status for ACCEL_MEM0"]
# [inline (always)]
# [must_use]
pub fn iping_initdone (& mut self) -> IpingInitdoneW < MeminitdoneSpec > { IpingInitdoneW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
1: Init done status for ACCEL_MEM1"]
# [inline (always)]
# [must_use]
pub fn ipong_initdone (& mut self) -> IpongInitdoneW < MeminitdoneSpec > { IpongInitdoneW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
1: Init done status for ACCEL_MEM2"]
# [inline (always)]
# [must_use]
pub fn oping_initdone (& mut self) -> OpingInitdoneW < MeminitdoneSpec > { OpingInitdoneW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
1: Init done status for ACCEL_MEM3"]
# [inline (always)]
# [must_use]
pub fn opong_initdone (& mut self) -> OpongInitdoneW < MeminitdoneSpec > { OpongInitdoneW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
1: Init done status for MEM_COMPRESSION_EVEN_RAM"]
# [inline (always)]
# [must_use]
pub fn mc_even_initdone (& mut self) -> McEvenInitdoneW < MeminitdoneSpec > { McEvenInitdoneW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
1: Init done status for MEM_COMPRESSION_ODD_RAM"]
# [inline (always)]
# [must_use]
pub fn mc_odd_initdone (& mut self) -> McOddInitdoneW < MeminitdoneSpec > { McOddInitdoneW :: new (self , 7) } # [doc = "Bits 8:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < MeminitdoneSpec > { NuW :: new (self , 8) } } # [doc = "MEMINITDONE\n\nYou can [`read`](crate::Reg::read) this register and get [`meminitdone::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`meminitdone::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MeminitdoneSpec ; impl crate :: RegisterSpec for MeminitdoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`meminitdone::R`](R) reader structure"]
impl crate :: Readable for MeminitdoneSpec { } # [doc = "`write(|w| ..)` method takes [`meminitdone::W`](W) writer structure"]
impl crate :: Writable for MeminitdoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MEMINITDONE to value 0"]
impl crate :: Resettable for MeminitdoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_WIN_RAM_ERR_LOC (rw) register accessor: HWA_SAFETY_WIN_RAM_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_win_ram_err_loc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_win_ram_err_loc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_win_ram_err_loc`]
module"]
# [doc (alias = "HWA_SAFETY_WIN_RAM_ERR_LOC")]
pub type HwaSafetyWinRamErrLoc = crate :: Reg < hwa_safety_win_ram_err_loc :: HwaSafetyWinRamErrLocSpec > ; # [doc = "HWA_SAFETY_WIN_RAM_ERR_LOC"]
pub mod hwa_safety_win_ram_err_loc { # [doc = "Register `HWA_SAFETY_WIN_RAM_ERR_LOC` reader"]
pub type R = crate :: R < HwaSafetyWinRamErrLocSpec > ; # [doc = "Register `HWA_SAFETY_WIN_RAM_ERR_LOC` writer"]
pub type W = crate :: W < HwaSafetyWinRamErrLocSpec > ; # [doc = "Field `HWA_SAFETY_WIN_RAM_ERR_ADDR` reader - 15:0\\]
\\[Debug\\]
Address of parity error location within Window RAM"]
pub type HwaSafetyWinRamErrAddrR = crate :: FieldReader < u16 > ; # [doc = "Field `HWA_SAFETY_WIN_RAM_ERR_ADDR` writer - 15:0\\]
\\[Debug\\]
Address of parity error location within Window RAM"]
pub type HwaSafetyWinRamErrAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug\\]
Address of parity error location within Window RAM"]
# [inline (always)]
pub fn hwa_safety_win_ram_err_addr (& self) -> HwaSafetyWinRamErrAddrR { HwaSafetyWinRamErrAddrR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug\\]
Address of parity error location within Window RAM"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_win_ram_err_addr (& mut self) -> HwaSafetyWinRamErrAddrW < HwaSafetyWinRamErrLocSpec > { HwaSafetyWinRamErrAddrW :: new (self , 0) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwaSafetyWinRamErrLocSpec > { NuW :: new (self , 16) } } # [doc = "HWA_SAFETY_WIN_RAM_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_win_ram_err_loc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_win_ram_err_loc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyWinRamErrLocSpec ; impl crate :: RegisterSpec for HwaSafetyWinRamErrLocSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_win_ram_err_loc::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyWinRamErrLocSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_win_ram_err_loc::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyWinRamErrLocSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_WIN_RAM_ERR_LOC to value 0"]
impl crate :: Resettable for HwaSafetyWinRamErrLocSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_PARAM_RAM_ERR_LOC (rw) register accessor: HWA_SAFETY_PARAM_RAM_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_param_ram_err_loc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_param_ram_err_loc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_param_ram_err_loc`]
module"]
# [doc (alias = "HWA_SAFETY_PARAM_RAM_ERR_LOC")]
pub type HwaSafetyParamRamErrLoc = crate :: Reg < hwa_safety_param_ram_err_loc :: HwaSafetyParamRamErrLocSpec > ; # [doc = "HWA_SAFETY_PARAM_RAM_ERR_LOC"]
pub mod hwa_safety_param_ram_err_loc { # [doc = "Register `HWA_SAFETY_PARAM_RAM_ERR_LOC` reader"]
pub type R = crate :: R < HwaSafetyParamRamErrLocSpec > ; # [doc = "Register `HWA_SAFETY_PARAM_RAM_ERR_LOC` writer"]
pub type W = crate :: W < HwaSafetyParamRamErrLocSpec > ; # [doc = "Field `SPARE` reader - 31:0\\]
Reserved.TI internal"]
pub type SpareR = crate :: FieldReader < u32 > ; # [doc = "Field `SPARE` writer - 31:0\\]
Reserved.TI internal"]
pub type SpareW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn spare (& self) -> SpareR { SpareR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn spare (& mut self) -> SpareW < HwaSafetyParamRamErrLocSpec > { SpareW :: new (self , 0) } } # [doc = "HWA_SAFETY_PARAM_RAM_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_param_ram_err_loc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_param_ram_err_loc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyParamRamErrLocSpec ; impl crate :: RegisterSpec for HwaSafetyParamRamErrLocSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_param_ram_err_loc::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyParamRamErrLocSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_param_ram_err_loc::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyParamRamErrLocSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_PARAM_RAM_ERR_LOC to value 0"]
impl crate :: Resettable for HwaSafetyParamRamErrLocSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_IPING_ERR_LOC (rw) register accessor: HWA_SAFETY_IPING_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_iping_err_loc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_iping_err_loc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_iping_err_loc`]
module"]
# [doc (alias = "HWA_SAFETY_IPING_ERR_LOC")]
pub type HwaSafetyIpingErrLoc = crate :: Reg < hwa_safety_iping_err_loc :: HwaSafetyIpingErrLocSpec > ; # [doc = "HWA_SAFETY_IPING_ERR_LOC"]
pub mod hwa_safety_iping_err_loc { # [doc = "Register `HWA_SAFETY_IPING_ERR_LOC` reader"]
pub type R = crate :: R < HwaSafetyIpingErrLocSpec > ; # [doc = "Register `HWA_SAFETY_IPING_ERR_LOC` writer"]
pub type W = crate :: W < HwaSafetyIpingErrLocSpec > ; # [doc = "Field `HWA_SAFETY_IPING_ERR_ADDR` reader - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM0 (rows 0-1023)"]
pub type HwaSafetyIpingErrAddrR = crate :: FieldReader < u16 > ; # [doc = "Field `HWA_SAFETY_IPING_ERR_ADDR` writer - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM0 (rows 0-1023)"]
pub type HwaSafetyIpingErrAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM0 (rows 0-1023)"]
# [inline (always)]
pub fn hwa_safety_iping_err_addr (& self) -> HwaSafetyIpingErrAddrR { HwaSafetyIpingErrAddrR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM0 (rows 0-1023)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_iping_err_addr (& mut self) -> HwaSafetyIpingErrAddrW < HwaSafetyIpingErrLocSpec > { HwaSafetyIpingErrAddrW :: new (self , 0) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwaSafetyIpingErrLocSpec > { NuW :: new (self , 16) } } # [doc = "HWA_SAFETY_IPING_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_iping_err_loc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_iping_err_loc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyIpingErrLocSpec ; impl crate :: RegisterSpec for HwaSafetyIpingErrLocSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_iping_err_loc::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyIpingErrLocSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_iping_err_loc::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyIpingErrLocSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_IPING_ERR_LOC to value 0"]
impl crate :: Resettable for HwaSafetyIpingErrLocSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_IPONG_ERR_LOC (rw) register accessor: HWA_SAFETY_IPONG_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_ipong_err_loc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_ipong_err_loc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_ipong_err_loc`]
module"]
# [doc (alias = "HWA_SAFETY_IPONG_ERR_LOC")]
pub type HwaSafetyIpongErrLoc = crate :: Reg < hwa_safety_ipong_err_loc :: HwaSafetyIpongErrLocSpec > ; # [doc = "HWA_SAFETY_IPONG_ERR_LOC"]
pub mod hwa_safety_ipong_err_loc { # [doc = "Register `HWA_SAFETY_IPONG_ERR_LOC` reader"]
pub type R = crate :: R < HwaSafetyIpongErrLocSpec > ; # [doc = "Register `HWA_SAFETY_IPONG_ERR_LOC` writer"]
pub type W = crate :: W < HwaSafetyIpongErrLocSpec > ; # [doc = "Field `HWA_SAFETY_IPONG_ERR_ADDR` reader - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM1 (rows 0-1023)"]
pub type HwaSafetyIpongErrAddrR = crate :: FieldReader < u16 > ; # [doc = "Field `HWA_SAFETY_IPONG_ERR_ADDR` writer - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM1 (rows 0-1023)"]
pub type HwaSafetyIpongErrAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM1 (rows 0-1023)"]
# [inline (always)]
pub fn hwa_safety_ipong_err_addr (& self) -> HwaSafetyIpongErrAddrR { HwaSafetyIpongErrAddrR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM1 (rows 0-1023)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_ipong_err_addr (& mut self) -> HwaSafetyIpongErrAddrW < HwaSafetyIpongErrLocSpec > { HwaSafetyIpongErrAddrW :: new (self , 0) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwaSafetyIpongErrLocSpec > { NuW :: new (self , 16) } } # [doc = "HWA_SAFETY_IPONG_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_ipong_err_loc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_ipong_err_loc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyIpongErrLocSpec ; impl crate :: RegisterSpec for HwaSafetyIpongErrLocSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_ipong_err_loc::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyIpongErrLocSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_ipong_err_loc::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyIpongErrLocSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_IPONG_ERR_LOC to value 0"]
impl crate :: Resettable for HwaSafetyIpongErrLocSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_OPING_ERR_LOC (rw) register accessor: HWA_SAFETY_OPING_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_oping_err_loc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_oping_err_loc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_oping_err_loc`]
module"]
# [doc (alias = "HWA_SAFETY_OPING_ERR_LOC")]
pub type HwaSafetyOpingErrLoc = crate :: Reg < hwa_safety_oping_err_loc :: HwaSafetyOpingErrLocSpec > ; # [doc = "HWA_SAFETY_OPING_ERR_LOC"]
pub mod hwa_safety_oping_err_loc { # [doc = "Register `HWA_SAFETY_OPING_ERR_LOC` reader"]
pub type R = crate :: R < HwaSafetyOpingErrLocSpec > ; # [doc = "Register `HWA_SAFETY_OPING_ERR_LOC` writer"]
pub type W = crate :: W < HwaSafetyOpingErrLocSpec > ; # [doc = "Field `HWA_SAFETY_OPING_ERR_ADDR` reader - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM2 (rows 0-1023)"]
pub type HwaSafetyOpingErrAddrR = crate :: FieldReader < u16 > ; # [doc = "Field `HWA_SAFETY_OPING_ERR_ADDR` writer - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM2 (rows 0-1023)"]
pub type HwaSafetyOpingErrAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM2 (rows 0-1023)"]
# [inline (always)]
pub fn hwa_safety_oping_err_addr (& self) -> HwaSafetyOpingErrAddrR { HwaSafetyOpingErrAddrR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM2 (rows 0-1023)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_oping_err_addr (& mut self) -> HwaSafetyOpingErrAddrW < HwaSafetyOpingErrLocSpec > { HwaSafetyOpingErrAddrW :: new (self , 0) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwaSafetyOpingErrLocSpec > { NuW :: new (self , 16) } } # [doc = "HWA_SAFETY_OPING_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_oping_err_loc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_oping_err_loc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyOpingErrLocSpec ; impl crate :: RegisterSpec for HwaSafetyOpingErrLocSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_oping_err_loc::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyOpingErrLocSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_oping_err_loc::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyOpingErrLocSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_OPING_ERR_LOC to value 0"]
impl crate :: Resettable for HwaSafetyOpingErrLocSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_OPONG_ERR_LOC (rw) register accessor: HWA_SAFETY_OPONG_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_opong_err_loc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_opong_err_loc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_opong_err_loc`]
module"]
# [doc (alias = "HWA_SAFETY_OPONG_ERR_LOC")]
pub type HwaSafetyOpongErrLoc = crate :: Reg < hwa_safety_opong_err_loc :: HwaSafetyOpongErrLocSpec > ; # [doc = "HWA_SAFETY_OPONG_ERR_LOC"]
pub mod hwa_safety_opong_err_loc { # [doc = "Register `HWA_SAFETY_OPONG_ERR_LOC` reader"]
pub type R = crate :: R < HwaSafetyOpongErrLocSpec > ; # [doc = "Register `HWA_SAFETY_OPONG_ERR_LOC` writer"]
pub type W = crate :: W < HwaSafetyOpongErrLocSpec > ; # [doc = "Field `HWA_SAFETY_OPONG_ERR_ADDR` reader - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM3 (rows 0-1023)"]
pub type HwaSafetyOpongErrAddrR = crate :: FieldReader < u16 > ; # [doc = "Field `HWA_SAFETY_OPONG_ERR_ADDR` writer - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM3 (rows 0-1023)"]
pub type HwaSafetyOpongErrAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM3 (rows 0-1023)"]
# [inline (always)]
pub fn hwa_safety_opong_err_addr (& self) -> HwaSafetyOpongErrAddrR { HwaSafetyOpongErrAddrR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
\\[Debug \\]Address of parity error location within ACCEL_MEM3 (rows 0-1023)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_opong_err_addr (& mut self) -> HwaSafetyOpongErrAddrW < HwaSafetyOpongErrLocSpec > { HwaSafetyOpongErrAddrW :: new (self , 0) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwaSafetyOpongErrLocSpec > { NuW :: new (self , 16) } } # [doc = "HWA_SAFETY_OPONG_ERR_LOC\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_opong_err_loc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_opong_err_loc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyOpongErrLocSpec ; impl crate :: RegisterSpec for HwaSafetyOpongErrLocSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_opong_err_loc::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyOpongErrLocSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_opong_err_loc::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyOpongErrLocSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_OPONG_ERR_LOC to value 0"]
impl crate :: Resettable for HwaSafetyOpongErrLocSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FFTINTMEMWRDATA (rw) register accessor: FFTINTMEMWRDATA\n\nYou can [`read`](crate::Reg::read) this register and get [`fftintmemwrdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftintmemwrdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fftintmemwrdata`]
module"]
# [doc (alias = "FFTINTMEMWRDATA")]
pub type Fftintmemwrdata = crate :: Reg < fftintmemwrdata :: FftintmemwrdataSpec > ; # [doc = "FFTINTMEMWRDATA"]
pub mod fftintmemwrdata { # [doc = "Register `FFTINTMEMWRDATA` reader"]
pub type R = crate :: R < FftintmemwrdataSpec > ; # [doc = "Register `FFTINTMEMWRDATA` writer"]
pub type W = crate :: W < FftintmemwrdataSpec > ; # [doc = "Field `FFTINTMEMWRDATA` reader - 31:0\\]
Reserved.TI internal"]
pub type FftintmemwrdataR = crate :: FieldReader < u32 > ; # [doc = "Field `FFTINTMEMWRDATA` writer - 31:0\\]
Reserved.TI internal"]
pub type FftintmemwrdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn fftintmemwrdata (& self) -> FftintmemwrdataR { FftintmemwrdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn fftintmemwrdata (& mut self) -> FftintmemwrdataW < FftintmemwrdataSpec > { FftintmemwrdataW :: new (self , 0) } } # [doc = "FFTINTMEMWRDATA\n\nYou can [`read`](crate::Reg::read) this register and get [`fftintmemwrdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftintmemwrdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FftintmemwrdataSpec ; impl crate :: RegisterSpec for FftintmemwrdataSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fftintmemwrdata::R`](R) reader structure"]
impl crate :: Readable for FftintmemwrdataSpec { } # [doc = "`write(|w| ..)` method takes [`fftintmemwrdata::W`](W) writer structure"]
impl crate :: Writable for FftintmemwrdataSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FFTINTMEMWRDATA to value 0"]
impl crate :: Resettable for FftintmemwrdataSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FFTINTMEMRDDATA (rw) register accessor: FFTINTMEMRDDATA\n\nYou can [`read`](crate::Reg::read) this register and get [`fftintmemrddata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftintmemrddata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fftintmemrddata`]
module"]
# [doc (alias = "FFTINTMEMRDDATA")]
pub type Fftintmemrddata = crate :: Reg < fftintmemrddata :: FftintmemrddataSpec > ; # [doc = "FFTINTMEMRDDATA"]
pub mod fftintmemrddata { # [doc = "Register `FFTINTMEMRDDATA` reader"]
pub type R = crate :: R < FftintmemrddataSpec > ; # [doc = "Register `FFTINTMEMRDDATA` writer"]
pub type W = crate :: W < FftintmemrddataSpec > ; # [doc = "Field `FFTINTMEMRDDATA` reader - 31:0\\]
Reserved.TI internal"]
pub type FftintmemrddataR = crate :: FieldReader < u32 > ; # [doc = "Field `FFTINTMEMRDDATA` writer - 31:0\\]
Reserved.TI internal"]
pub type FftintmemrddataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn fftintmemrddata (& self) -> FftintmemrddataR { FftintmemrddataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn fftintmemrddata (& mut self) -> FftintmemrddataW < FftintmemrddataSpec > { FftintmemrddataW :: new (self , 0) } } # [doc = "FFTINTMEMRDDATA\n\nYou can [`read`](crate::Reg::read) this register and get [`fftintmemrddata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftintmemrddata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FftintmemrddataSpec ; impl crate :: RegisterSpec for FftintmemrddataSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fftintmemrddata::R`](R) reader structure"]
impl crate :: Readable for FftintmemrddataSpec { } # [doc = "`write(|w| ..)` method takes [`fftintmemrddata::W`](W) writer structure"]
impl crate :: Writable for FftintmemrddataSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FFTINTMEMRDDATA to value 0"]
impl crate :: Resettable for FftintmemrddataSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWACCREG16 (rw) register accessor: HWACCREG16\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwaccreg16`]
module"]
# [doc (alias = "HWACCREG16")]
pub type Hwaccreg16 = crate :: Reg < hwaccreg16 :: Hwaccreg16Spec > ; # [doc = "HWACCREG16"]
pub mod hwaccreg16 { # [doc = "Register `HWACCREG16` reader"]
pub type R = crate :: R < Hwaccreg16Spec > ; # [doc = "Register `HWACCREG16` writer"]
pub type W = crate :: W < Hwaccreg16Spec > ; # [doc = "Field `NLOOPS` reader - 11:0\\]
Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them. The maximum number of times the loop can be made is run is 4094. A value of zero programmed in this register means that the looping mechanism is disabled."]
pub type NloopsR = crate :: FieldReader < u16 > ; # [doc = "Field `NLOOPS` writer - 11:0\\]
Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them. The maximum number of times the loop can be made is run is 4094. A value of zero programmed in this register means that the looping mechanism is disabled."]
pub type NloopsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `PARAMSTART` reader - 16:12\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
pub type ParamstartR = crate :: FieldReader ; # [doc = "Field `PARAMSTART` writer - 16:12\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
pub type ParamstartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PARAMSTOP` reader - 21:17\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
pub type ParamstopR = crate :: FieldReader ; # [doc = "Field `PARAMSTOP` writer - 21:17\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
pub type ParamstopW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them. The maximum number of times the loop can be made is run is 4094. A value of zero programmed in this register means that the looping mechanism is disabled."]
# [inline (always)]
pub fn nloops (& self) -> NloopsR { NloopsR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:16 - 16:12\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
# [inline (always)]
pub fn paramstart (& self) -> ParamstartR { ParamstartR :: new (((self . bits >> 12) & 0x1f) as u8) } # [doc = "Bits 17:21 - 21:17\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
# [inline (always)]
pub fn paramstop (& self) -> ParamstopR { ParamstopR :: new (((self . bits >> 17) & 0x1f) as u8) } # [doc = "Bits 22:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 22) & 0x03ff) as u16) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them. The maximum number of times the loop can be made is run is 4094. A value of zero programmed in this register means that the looping mechanism is disabled."]
# [inline (always)]
# [must_use]
pub fn nloops (& mut self) -> NloopsW < Hwaccreg16Spec > { NloopsW :: new (self , 0) } # [doc = "Bits 12:16 - 16:12\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
# [inline (always)]
# [must_use]
pub fn paramstart (& mut self) -> ParamstartW < Hwaccreg16Spec > { ParamstartW :: new (self , 12) } # [doc = "Bits 17:21 - 21:17\\]
These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START."]
# [inline (always)]
# [must_use]
pub fn paramstop (& mut self) -> ParamstopW < Hwaccreg16Spec > { ParamstopW :: new (self , 17) } # [doc = "Bits 22:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Hwaccreg16Spec > { Nu1W :: new (self , 22) } } # [doc = "HWACCREG16\n\nYou can [`read`](crate::Reg::read) this register and get [`hwaccreg16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwaccreg16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hwaccreg16Spec ; impl crate :: RegisterSpec for Hwaccreg16Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwaccreg16::R`](R) reader structure"]
impl crate :: Readable for Hwaccreg16Spec { } # [doc = "`write(|w| ..)` method takes [`hwaccreg16::W`](W) writer structure"]
impl crate :: Writable for Hwaccreg16Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWACCREG16 to value 0"]
impl crate :: Resettable for Hwaccreg16Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST1I_SW (rw) register accessor: DCEST1I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1i_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1i_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest1i_sw`]
module"]
# [doc (alias = "DCEST1I_SW")]
pub type Dcest1iSw = crate :: Reg < dcest1i_sw :: Dcest1iSwSpec > ; # [doc = "DCEST1I_SW"]
pub mod dcest1i_sw { # [doc = "Register `DCEST1I_SW` reader"]
pub type R = crate :: R < Dcest1iSwSpec > ; # [doc = "Register `DCEST1I_SW` writer"]
pub type W = crate :: W < Dcest1iSwSpec > ; # [doc = "Field `DCEST1I_SW` reader - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 0."]
pub type Dcest1iSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST1I_SW` writer - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 0."]
pub type Dcest1iSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 0."]
# [inline (always)]
pub fn dcest1i_sw (& self) -> Dcest1iSwR { Dcest1iSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 0."]
# [inline (always)]
# [must_use]
pub fn dcest1i_sw (& mut self) -> Dcest1iSwW < Dcest1iSwSpec > { Dcest1iSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest1iSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST1I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1i_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1i_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest1iSwSpec ; impl crate :: RegisterSpec for Dcest1iSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest1i_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest1iSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest1i_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest1iSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST1I_SW to value 0"]
impl crate :: Resettable for Dcest1iSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST2I_SW (rw) register accessor: DCEST2I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2i_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2i_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest2i_sw`]
module"]
# [doc (alias = "DCEST2I_SW")]
pub type Dcest2iSw = crate :: Reg < dcest2i_sw :: Dcest2iSwSpec > ; # [doc = "DCEST2I_SW"]
pub mod dcest2i_sw { # [doc = "Register `DCEST2I_SW` reader"]
pub type R = crate :: R < Dcest2iSwSpec > ; # [doc = "Register `DCEST2I_SW` writer"]
pub type W = crate :: W < Dcest2iSwSpec > ; # [doc = "Field `DCEST2I_SW` reader - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 1."]
pub type Dcest2iSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST2I_SW` writer - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 1."]
pub type Dcest2iSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 1."]
# [inline (always)]
pub fn dcest2i_sw (& self) -> Dcest2iSwR { Dcest2iSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 1."]
# [inline (always)]
# [must_use]
pub fn dcest2i_sw (& mut self) -> Dcest2iSwW < Dcest2iSwSpec > { Dcest2iSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest2iSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST2I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2i_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2i_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest2iSwSpec ; impl crate :: RegisterSpec for Dcest2iSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest2i_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest2iSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest2i_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest2iSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST2I_SW to value 0"]
impl crate :: Resettable for Dcest2iSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST3I_SW (rw) register accessor: DCEST3I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3i_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3i_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest3i_sw`]
module"]
# [doc (alias = "DCEST3I_SW")]
pub type Dcest3iSw = crate :: Reg < dcest3i_sw :: Dcest3iSwSpec > ; # [doc = "DCEST3I_SW"]
pub mod dcest3i_sw { # [doc = "Register `DCEST3I_SW` reader"]
pub type R = crate :: R < Dcest3iSwSpec > ; # [doc = "Register `DCEST3I_SW` writer"]
pub type W = crate :: W < Dcest3iSwSpec > ; # [doc = "Field `DCEST3I_SW` reader - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 2."]
pub type Dcest3iSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST3I_SW` writer - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 2."]
pub type Dcest3iSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 2."]
# [inline (always)]
pub fn dcest3i_sw (& self) -> Dcest3iSwR { Dcest3iSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 2."]
# [inline (always)]
# [must_use]
pub fn dcest3i_sw (& mut self) -> Dcest3iSwW < Dcest3iSwSpec > { Dcest3iSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest3iSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST3I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3i_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3i_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest3iSwSpec ; impl crate :: RegisterSpec for Dcest3iSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest3i_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest3iSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest3i_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest3iSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST3I_SW to value 0"]
impl crate :: Resettable for Dcest3iSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST4I_SW (rw) register accessor: DCEST4I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4i_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4i_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest4i_sw`]
module"]
# [doc (alias = "DCEST4I_SW")]
pub type Dcest4iSw = crate :: Reg < dcest4i_sw :: Dcest4iSwSpec > ; # [doc = "DCEST4I_SW"]
pub mod dcest4i_sw { # [doc = "Register `DCEST4I_SW` reader"]
pub type R = crate :: R < Dcest4iSwSpec > ; # [doc = "Register `DCEST4I_SW` writer"]
pub type W = crate :: W < Dcest4iSwSpec > ; # [doc = "Field `DCEST4I_SW` reader - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 3."]
pub type Dcest4iSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST4I_SW` writer - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 3."]
pub type Dcest4iSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 3."]
# [inline (always)]
pub fn dcest4i_sw (& self) -> Dcest4iSwR { Dcest4iSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 3."]
# [inline (always)]
# [must_use]
pub fn dcest4i_sw (& mut self) -> Dcest4iSwW < Dcest4iSwSpec > { Dcest4iSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest4iSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST4I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4i_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4i_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest4iSwSpec ; impl crate :: RegisterSpec for Dcest4iSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest4i_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest4iSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest4i_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest4iSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST4I_SW to value 0"]
impl crate :: Resettable for Dcest4iSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST5I_SW (rw) register accessor: DCEST5I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5i_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5i_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest5i_sw`]
module"]
# [doc (alias = "DCEST5I_SW")]
pub type Dcest5iSw = crate :: Reg < dcest5i_sw :: Dcest5iSwSpec > ; # [doc = "DCEST5I_SW"]
pub mod dcest5i_sw { # [doc = "Register `DCEST5I_SW` reader"]
pub type R = crate :: R < Dcest5iSwSpec > ; # [doc = "Register `DCEST5I_SW` writer"]
pub type W = crate :: W < Dcest5iSwSpec > ; # [doc = "Field `DCEST5I_SW` reader - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 4."]
pub type Dcest5iSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST5I_SW` writer - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 4."]
pub type Dcest5iSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 4."]
# [inline (always)]
pub fn dcest5i_sw (& self) -> Dcest5iSwR { Dcest5iSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 4."]
# [inline (always)]
# [must_use]
pub fn dcest5i_sw (& mut self) -> Dcest5iSwW < Dcest5iSwSpec > { Dcest5iSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest5iSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST5I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5i_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5i_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest5iSwSpec ; impl crate :: RegisterSpec for Dcest5iSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest5i_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest5iSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest5i_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest5iSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST5I_SW to value 0"]
impl crate :: Resettable for Dcest5iSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST6I_SW (rw) register accessor: DCEST6I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6i_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6i_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest6i_sw`]
module"]
# [doc (alias = "DCEST6I_SW")]
pub type Dcest6iSw = crate :: Reg < dcest6i_sw :: Dcest6iSwSpec > ; # [doc = "DCEST6I_SW"]
pub mod dcest6i_sw { # [doc = "Register `DCEST6I_SW` reader"]
pub type R = crate :: R < Dcest6iSwSpec > ; # [doc = "Register `DCEST6I_SW` writer"]
pub type W = crate :: W < Dcest6iSwSpec > ; # [doc = "Field `DCEST6I_SW` reader - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 5."]
pub type Dcest6iSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST6I_SW` writer - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 5."]
pub type Dcest6iSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 5."]
# [inline (always)]
pub fn dcest6i_sw (& self) -> Dcest6iSwR { Dcest6iSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 5."]
# [inline (always)]
# [must_use]
pub fn dcest6i_sw (& mut self) -> Dcest6iSwW < Dcest6iSwSpec > { Dcest6iSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest6iSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST6I_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6i_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6i_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest6iSwSpec ; impl crate :: RegisterSpec for Dcest6iSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest6i_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest6iSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest6i_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest6iSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST6I_SW to value 0"]
impl crate :: Resettable for Dcest6iSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST1I (rw) register accessor: DCEST1I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest1i`]
module"]
# [doc (alias = "DCEST1I")]
pub type Dcest1i = crate :: Reg < dcest1i :: Dcest1iSpec > ; # [doc = "DCEST1I"]
pub mod dcest1i { # [doc = "Register `DCEST1I` reader"]
pub type R = crate :: R < Dcest1iSpec > ; # [doc = "Register `DCEST1I` writer"]
pub type W = crate :: W < Dcest1iSpec > ; # [doc = "Field `DCEST1I` reader - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =0 ."]
pub type Dcest1iR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST1I` writer - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =0 ."]
pub type Dcest1iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =0 ."]
# [inline (always)]
pub fn dcest1i (& self) -> Dcest1iR { Dcest1iR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =0 ."]
# [inline (always)]
# [must_use]
pub fn dcest1i (& mut self) -> Dcest1iW < Dcest1iSpec > { Dcest1iW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest1iSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST1I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest1iSpec ; impl crate :: RegisterSpec for Dcest1iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest1i::R`](R) reader structure"]
impl crate :: Readable for Dcest1iSpec { } # [doc = "`write(|w| ..)` method takes [`dcest1i::W`](W) writer structure"]
impl crate :: Writable for Dcest1iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST1I to value 0"]
impl crate :: Resettable for Dcest1iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST2I (rw) register accessor: DCEST2I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest2i`]
module"]
# [doc (alias = "DCEST2I")]
pub type Dcest2i = crate :: Reg < dcest2i :: Dcest2iSpec > ; # [doc = "DCEST2I"]
pub mod dcest2i { # [doc = "Register `DCEST2I` reader"]
pub type R = crate :: R < Dcest2iSpec > ; # [doc = "Register `DCEST2I` writer"]
pub type W = crate :: W < Dcest2iSpec > ; # [doc = "Field `DCEST2I` reader - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =1 ."]
pub type Dcest2iR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST2I` writer - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =1 ."]
pub type Dcest2iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =1 ."]
# [inline (always)]
pub fn dcest2i (& self) -> Dcest2iR { Dcest2iR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =1 ."]
# [inline (always)]
# [must_use]
pub fn dcest2i (& mut self) -> Dcest2iW < Dcest2iSpec > { Dcest2iW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest2iSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST2I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest2iSpec ; impl crate :: RegisterSpec for Dcest2iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest2i::R`](R) reader structure"]
impl crate :: Readable for Dcest2iSpec { } # [doc = "`write(|w| ..)` method takes [`dcest2i::W`](W) writer structure"]
impl crate :: Writable for Dcest2iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST2I to value 0"]
impl crate :: Resettable for Dcest2iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST3I (rw) register accessor: DCEST3I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest3i`]
module"]
# [doc (alias = "DCEST3I")]
pub type Dcest3i = crate :: Reg < dcest3i :: Dcest3iSpec > ; # [doc = "DCEST3I"]
pub mod dcest3i { # [doc = "Register `DCEST3I` reader"]
pub type R = crate :: R < Dcest3iSpec > ; # [doc = "Register `DCEST3I` writer"]
pub type W = crate :: W < Dcest3iSpec > ; # [doc = "Field `DCEST3I` reader - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =2 ."]
pub type Dcest3iR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST3I` writer - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =2 ."]
pub type Dcest3iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =2 ."]
# [inline (always)]
pub fn dcest3i (& self) -> Dcest3iR { Dcest3iR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =2 ."]
# [inline (always)]
# [must_use]
pub fn dcest3i (& mut self) -> Dcest3iW < Dcest3iSpec > { Dcest3iW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest3iSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST3I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest3iSpec ; impl crate :: RegisterSpec for Dcest3iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest3i::R`](R) reader structure"]
impl crate :: Readable for Dcest3iSpec { } # [doc = "`write(|w| ..)` method takes [`dcest3i::W`](W) writer structure"]
impl crate :: Writable for Dcest3iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST3I to value 0"]
impl crate :: Resettable for Dcest3iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST4I (rw) register accessor: DCEST4I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest4i`]
module"]
# [doc (alias = "DCEST4I")]
pub type Dcest4i = crate :: Reg < dcest4i :: Dcest4iSpec > ; # [doc = "DCEST4I"]
pub mod dcest4i { # [doc = "Register `DCEST4I` reader"]
pub type R = crate :: R < Dcest4iSpec > ; # [doc = "Register `DCEST4I` writer"]
pub type W = crate :: W < Dcest4iSpec > ; # [doc = "Field `DCEST4I` reader - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =3."]
pub type Dcest4iR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST4I` writer - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =3."]
pub type Dcest4iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =3."]
# [inline (always)]
pub fn dcest4i (& self) -> Dcest4iR { Dcest4iR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =3."]
# [inline (always)]
# [must_use]
pub fn dcest4i (& mut self) -> Dcest4iW < Dcest4iSpec > { Dcest4iW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest4iSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST4I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest4iSpec ; impl crate :: RegisterSpec for Dcest4iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest4i::R`](R) reader structure"]
impl crate :: Readable for Dcest4iSpec { } # [doc = "`write(|w| ..)` method takes [`dcest4i::W`](W) writer structure"]
impl crate :: Writable for Dcest4iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST4I to value 0"]
impl crate :: Resettable for Dcest4iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST5I (rw) register accessor: DCEST5I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest5i`]
module"]
# [doc (alias = "DCEST5I")]
pub type Dcest5i = crate :: Reg < dcest5i :: Dcest5iSpec > ; # [doc = "DCEST5I"]
pub mod dcest5i { # [doc = "Register `DCEST5I` reader"]
pub type R = crate :: R < Dcest5iSpec > ; # [doc = "Register `DCEST5I` writer"]
pub type W = crate :: W < Dcest5iSpec > ; # [doc = "Field `DCEST5I` reader - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =4 ."]
pub type Dcest5iR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST5I` writer - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =4 ."]
pub type Dcest5iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =4 ."]
# [inline (always)]
pub fn dcest5i (& self) -> Dcest5iR { Dcest5iR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =4 ."]
# [inline (always)]
# [must_use]
pub fn dcest5i (& mut self) -> Dcest5iW < Dcest5iSpec > { Dcest5iW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest5iSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST5I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest5iSpec ; impl crate :: RegisterSpec for Dcest5iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest5i::R`](R) reader structure"]
impl crate :: Readable for Dcest5iSpec { } # [doc = "`write(|w| ..)` method takes [`dcest5i::W`](W) writer structure"]
impl crate :: Writable for Dcest5iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST5I to value 0"]
impl crate :: Resettable for Dcest5iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST6I (rw) register accessor: DCEST6I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest6i`]
module"]
# [doc (alias = "DCEST6I")]
pub type Dcest6i = crate :: Reg < dcest6i :: Dcest6iSpec > ; # [doc = "DCEST6I"]
pub mod dcest6i { # [doc = "Register `DCEST6I` reader"]
pub type R = crate :: R < Dcest6iSpec > ; # [doc = "Register `DCEST6I` writer"]
pub type W = crate :: W < Dcest6iSpec > ; # [doc = "Field `DCEST6I` reader - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =5 ."]
pub type Dcest6iR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST6I` writer - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =5 ."]
pub type Dcest6iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =5 ."]
# [inline (always)]
pub fn dcest6i (& self) -> Dcest6iR { Dcest6iR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =5 ."]
# [inline (always)]
# [must_use]
pub fn dcest6i (& mut self) -> Dcest6iW < Dcest6iSpec > { Dcest6iW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest6iSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST6I\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest6iSpec ; impl crate :: RegisterSpec for Dcest6iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest6i::R`](R) reader structure"]
impl crate :: Readable for Dcest6iSpec { } # [doc = "`write(|w| ..)` method takes [`dcest6i::W`](W) writer structure"]
impl crate :: Writable for Dcest6iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST6I to value 0"]
impl crate :: Resettable for Dcest6iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC1I_LSB (rw) register accessor: DC_ACC1I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1i_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1i_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc1i_lsb`]
module"]
# [doc (alias = "DC_ACC1I_LSB")]
pub type DcAcc1iLsb = crate :: Reg < dc_acc1i_lsb :: DcAcc1iLsbSpec > ; # [doc = "DC_ACC1I_LSB"]
pub mod dc_acc1i_lsb { # [doc = "Register `DC_ACC1I_LSB` reader"]
pub type R = crate :: R < DcAcc1iLsbSpec > ; # [doc = "Register `DC_ACC1I_LSB` writer"]
pub type W = crate :: W < DcAcc1iLsbSpec > ; # [doc = "Field `DC_ACC1I_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=0"]
pub type DcAcc1iLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC1I_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=0"]
pub type DcAcc1iLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=0"]
# [inline (always)]
pub fn dc_acc1i_lsb (& self) -> DcAcc1iLsbR { DcAcc1iLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=0"]
# [inline (always)]
# [must_use]
pub fn dc_acc1i_lsb (& mut self) -> DcAcc1iLsbW < DcAcc1iLsbSpec > { DcAcc1iLsbW :: new (self , 0) } } # [doc = "DC_ACC1I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1i_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1i_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc1iLsbSpec ; impl crate :: RegisterSpec for DcAcc1iLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc1i_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc1iLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc1i_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc1iLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC1I_LSB to value 0"]
impl crate :: Resettable for DcAcc1iLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC1I_MSB (rw) register accessor: DC_ACC1I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1i_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1i_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc1i_msb`]
module"]
# [doc (alias = "DC_ACC1I_MSB")]
pub type DcAcc1iMsb = crate :: Reg < dc_acc1i_msb :: DcAcc1iMsbSpec > ; # [doc = "DC_ACC1I_MSB"]
pub mod dc_acc1i_msb { # [doc = "Register `DC_ACC1I_MSB` reader"]
pub type R = crate :: R < DcAcc1iMsbSpec > ; # [doc = "Register `DC_ACC1I_MSB` writer"]
pub type W = crate :: W < DcAcc1iMsbSpec > ; # [doc = "Field `DC_ACC1I_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=0"]
pub type DcAcc1iMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC1I_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=0"]
pub type DcAcc1iMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=0"]
# [inline (always)]
pub fn dc_acc1i_msb (& self) -> DcAcc1iMsbR { DcAcc1iMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=0"]
# [inline (always)]
# [must_use]
pub fn dc_acc1i_msb (& mut self) -> DcAcc1iMsbW < DcAcc1iMsbSpec > { DcAcc1iMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc1iMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC1I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1i_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1i_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc1iMsbSpec ; impl crate :: RegisterSpec for DcAcc1iMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc1i_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc1iMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc1i_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc1iMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC1I_MSB to value 0"]
impl crate :: Resettable for DcAcc1iMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC2I_LSB (rw) register accessor: DC_ACC2I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2i_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2i_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc2i_lsb`]
module"]
# [doc (alias = "DC_ACC2I_LSB")]
pub type DcAcc2iLsb = crate :: Reg < dc_acc2i_lsb :: DcAcc2iLsbSpec > ; # [doc = "DC_ACC2I_LSB"]
pub mod dc_acc2i_lsb { # [doc = "Register `DC_ACC2I_LSB` reader"]
pub type R = crate :: R < DcAcc2iLsbSpec > ; # [doc = "Register `DC_ACC2I_LSB` writer"]
pub type W = crate :: W < DcAcc2iLsbSpec > ; # [doc = "Field `DC_ACC2I_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=1"]
pub type DcAcc2iLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC2I_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=1"]
pub type DcAcc2iLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=1"]
# [inline (always)]
pub fn dc_acc2i_lsb (& self) -> DcAcc2iLsbR { DcAcc2iLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=1"]
# [inline (always)]
# [must_use]
pub fn dc_acc2i_lsb (& mut self) -> DcAcc2iLsbW < DcAcc2iLsbSpec > { DcAcc2iLsbW :: new (self , 0) } } # [doc = "DC_ACC2I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2i_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2i_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc2iLsbSpec ; impl crate :: RegisterSpec for DcAcc2iLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc2i_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc2iLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc2i_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc2iLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC2I_LSB to value 0"]
impl crate :: Resettable for DcAcc2iLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC2I_MSB (rw) register accessor: DC_ACC2I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2i_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2i_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc2i_msb`]
module"]
# [doc (alias = "DC_ACC2I_MSB")]
pub type DcAcc2iMsb = crate :: Reg < dc_acc2i_msb :: DcAcc2iMsbSpec > ; # [doc = "DC_ACC2I_MSB"]
pub mod dc_acc2i_msb { # [doc = "Register `DC_ACC2I_MSB` reader"]
pub type R = crate :: R < DcAcc2iMsbSpec > ; # [doc = "Register `DC_ACC2I_MSB` writer"]
pub type W = crate :: W < DcAcc2iMsbSpec > ; # [doc = "Field `DC_ACC2I_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=1"]
pub type DcAcc2iMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC2I_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=1"]
pub type DcAcc2iMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=1"]
# [inline (always)]
pub fn dc_acc2i_msb (& self) -> DcAcc2iMsbR { DcAcc2iMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=1"]
# [inline (always)]
# [must_use]
pub fn dc_acc2i_msb (& mut self) -> DcAcc2iMsbW < DcAcc2iMsbSpec > { DcAcc2iMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc2iMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC2I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2i_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2i_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc2iMsbSpec ; impl crate :: RegisterSpec for DcAcc2iMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc2i_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc2iMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc2i_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc2iMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC2I_MSB to value 0"]
impl crate :: Resettable for DcAcc2iMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC3I_LSB (rw) register accessor: DC_ACC3I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3i_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3i_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc3i_lsb`]
module"]
# [doc (alias = "DC_ACC3I_LSB")]
pub type DcAcc3iLsb = crate :: Reg < dc_acc3i_lsb :: DcAcc3iLsbSpec > ; # [doc = "DC_ACC3I_LSB"]
pub mod dc_acc3i_lsb { # [doc = "Register `DC_ACC3I_LSB` reader"]
pub type R = crate :: R < DcAcc3iLsbSpec > ; # [doc = "Register `DC_ACC3I_LSB` writer"]
pub type W = crate :: W < DcAcc3iLsbSpec > ; # [doc = "Field `DC_ACC3I_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=2"]
pub type DcAcc3iLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC3I_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=2"]
pub type DcAcc3iLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=2"]
# [inline (always)]
pub fn dc_acc3i_lsb (& self) -> DcAcc3iLsbR { DcAcc3iLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=2"]
# [inline (always)]
# [must_use]
pub fn dc_acc3i_lsb (& mut self) -> DcAcc3iLsbW < DcAcc3iLsbSpec > { DcAcc3iLsbW :: new (self , 0) } } # [doc = "DC_ACC3I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3i_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3i_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc3iLsbSpec ; impl crate :: RegisterSpec for DcAcc3iLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc3i_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc3iLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc3i_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc3iLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC3I_LSB to value 0"]
impl crate :: Resettable for DcAcc3iLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC3I_MSB (rw) register accessor: DC_ACC3I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3i_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3i_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc3i_msb`]
module"]
# [doc (alias = "DC_ACC3I_MSB")]
pub type DcAcc3iMsb = crate :: Reg < dc_acc3i_msb :: DcAcc3iMsbSpec > ; # [doc = "DC_ACC3I_MSB"]
pub mod dc_acc3i_msb { # [doc = "Register `DC_ACC3I_MSB` reader"]
pub type R = crate :: R < DcAcc3iMsbSpec > ; # [doc = "Register `DC_ACC3I_MSB` writer"]
pub type W = crate :: W < DcAcc3iMsbSpec > ; # [doc = "Field `DC_ACC3I_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=2"]
pub type DcAcc3iMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC3I_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=2"]
pub type DcAcc3iMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=2"]
# [inline (always)]
pub fn dc_acc3i_msb (& self) -> DcAcc3iMsbR { DcAcc3iMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=2"]
# [inline (always)]
# [must_use]
pub fn dc_acc3i_msb (& mut self) -> DcAcc3iMsbW < DcAcc3iMsbSpec > { DcAcc3iMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc3iMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC3I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3i_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3i_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc3iMsbSpec ; impl crate :: RegisterSpec for DcAcc3iMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc3i_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc3iMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc3i_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc3iMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC3I_MSB to value 0"]
impl crate :: Resettable for DcAcc3iMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC4I_LSB (rw) register accessor: DC_ACC4I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4i_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4i_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc4i_lsb`]
module"]
# [doc (alias = "DC_ACC4I_LSB")]
pub type DcAcc4iLsb = crate :: Reg < dc_acc4i_lsb :: DcAcc4iLsbSpec > ; # [doc = "DC_ACC4I_LSB"]
pub mod dc_acc4i_lsb { # [doc = "Register `DC_ACC4I_LSB` reader"]
pub type R = crate :: R < DcAcc4iLsbSpec > ; # [doc = "Register `DC_ACC4I_LSB` writer"]
pub type W = crate :: W < DcAcc4iLsbSpec > ; # [doc = "Field `DC_ACC4I_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=3"]
pub type DcAcc4iLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC4I_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=3"]
pub type DcAcc4iLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=3"]
# [inline (always)]
pub fn dc_acc4i_lsb (& self) -> DcAcc4iLsbR { DcAcc4iLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=3"]
# [inline (always)]
# [must_use]
pub fn dc_acc4i_lsb (& mut self) -> DcAcc4iLsbW < DcAcc4iLsbSpec > { DcAcc4iLsbW :: new (self , 0) } } # [doc = "DC_ACC4I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4i_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4i_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc4iLsbSpec ; impl crate :: RegisterSpec for DcAcc4iLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc4i_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc4iLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc4i_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc4iLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC4I_LSB to value 0"]
impl crate :: Resettable for DcAcc4iLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC4I_MSB (rw) register accessor: DC_ACC4I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4i_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4i_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc4i_msb`]
module"]
# [doc (alias = "DC_ACC4I_MSB")]
pub type DcAcc4iMsb = crate :: Reg < dc_acc4i_msb :: DcAcc4iMsbSpec > ; # [doc = "DC_ACC4I_MSB"]
pub mod dc_acc4i_msb { # [doc = "Register `DC_ACC4I_MSB` reader"]
pub type R = crate :: R < DcAcc4iMsbSpec > ; # [doc = "Register `DC_ACC4I_MSB` writer"]
pub type W = crate :: W < DcAcc4iMsbSpec > ; # [doc = "Field `DC_ACC4I_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=3"]
pub type DcAcc4iMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC4I_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=3"]
pub type DcAcc4iMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=3"]
# [inline (always)]
pub fn dc_acc4i_msb (& self) -> DcAcc4iMsbR { DcAcc4iMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=3"]
# [inline (always)]
# [must_use]
pub fn dc_acc4i_msb (& mut self) -> DcAcc4iMsbW < DcAcc4iMsbSpec > { DcAcc4iMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc4iMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC4I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4i_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4i_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc4iMsbSpec ; impl crate :: RegisterSpec for DcAcc4iMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc4i_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc4iMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc4i_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc4iMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC4I_MSB to value 0"]
impl crate :: Resettable for DcAcc4iMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC5I_LSB (rw) register accessor: DC_ACC5I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5i_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5i_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc5i_lsb`]
module"]
# [doc (alias = "DC_ACC5I_LSB")]
pub type DcAcc5iLsb = crate :: Reg < dc_acc5i_lsb :: DcAcc5iLsbSpec > ; # [doc = "DC_ACC5I_LSB"]
pub mod dc_acc5i_lsb { # [doc = "Register `DC_ACC5I_LSB` reader"]
pub type R = crate :: R < DcAcc5iLsbSpec > ; # [doc = "Register `DC_ACC5I_LSB` writer"]
pub type W = crate :: W < DcAcc5iLsbSpec > ; # [doc = "Field `DC_ACC5I_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=4"]
pub type DcAcc5iLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC5I_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=4"]
pub type DcAcc5iLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=4"]
# [inline (always)]
pub fn dc_acc5i_lsb (& self) -> DcAcc5iLsbR { DcAcc5iLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=4"]
# [inline (always)]
# [must_use]
pub fn dc_acc5i_lsb (& mut self) -> DcAcc5iLsbW < DcAcc5iLsbSpec > { DcAcc5iLsbW :: new (self , 0) } } # [doc = "DC_ACC5I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5i_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5i_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc5iLsbSpec ; impl crate :: RegisterSpec for DcAcc5iLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc5i_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc5iLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc5i_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc5iLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC5I_LSB to value 0"]
impl crate :: Resettable for DcAcc5iLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC5I_MSB (rw) register accessor: DC_ACC5I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5i_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5i_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc5i_msb`]
module"]
# [doc (alias = "DC_ACC5I_MSB")]
pub type DcAcc5iMsb = crate :: Reg < dc_acc5i_msb :: DcAcc5iMsbSpec > ; # [doc = "DC_ACC5I_MSB"]
pub mod dc_acc5i_msb { # [doc = "Register `DC_ACC5I_MSB` reader"]
pub type R = crate :: R < DcAcc5iMsbSpec > ; # [doc = "Register `DC_ACC5I_MSB` writer"]
pub type W = crate :: W < DcAcc5iMsbSpec > ; # [doc = "Field `DC_ACC5I_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=4"]
pub type DcAcc5iMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC5I_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=4"]
pub type DcAcc5iMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=4"]
# [inline (always)]
pub fn dc_acc5i_msb (& self) -> DcAcc5iMsbR { DcAcc5iMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=4"]
# [inline (always)]
# [must_use]
pub fn dc_acc5i_msb (& mut self) -> DcAcc5iMsbW < DcAcc5iMsbSpec > { DcAcc5iMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc5iMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC5I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5i_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5i_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc5iMsbSpec ; impl crate :: RegisterSpec for DcAcc5iMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc5i_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc5iMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc5i_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc5iMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC5I_MSB to value 0"]
impl crate :: Resettable for DcAcc5iMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC6I_LSB (rw) register accessor: DC_ACC6I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6i_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6i_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc6i_lsb`]
module"]
# [doc (alias = "DC_ACC6I_LSB")]
pub type DcAcc6iLsb = crate :: Reg < dc_acc6i_lsb :: DcAcc6iLsbSpec > ; # [doc = "DC_ACC6I_LSB"]
pub mod dc_acc6i_lsb { # [doc = "Register `DC_ACC6I_LSB` reader"]
pub type R = crate :: R < DcAcc6iLsbSpec > ; # [doc = "Register `DC_ACC6I_LSB` writer"]
pub type W = crate :: W < DcAcc6iLsbSpec > ; # [doc = "Field `DC_ACC6I_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=5"]
pub type DcAcc6iLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC6I_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=5"]
pub type DcAcc6iLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=5"]
# [inline (always)]
pub fn dc_acc6i_lsb (& self) -> DcAcc6iLsbR { DcAcc6iLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=5"]
# [inline (always)]
# [must_use]
pub fn dc_acc6i_lsb (& mut self) -> DcAcc6iLsbW < DcAcc6iLsbSpec > { DcAcc6iLsbW :: new (self , 0) } } # [doc = "DC_ACC6I_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6i_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6i_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc6iLsbSpec ; impl crate :: RegisterSpec for DcAcc6iLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc6i_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc6iLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc6i_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc6iLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC6I_LSB to value 0"]
impl crate :: Resettable for DcAcc6iLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC6I_MSB (rw) register accessor: DC_ACC6I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6i_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6i_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc6i_msb`]
module"]
# [doc (alias = "DC_ACC6I_MSB")]
pub type DcAcc6iMsb = crate :: Reg < dc_acc6i_msb :: DcAcc6iMsbSpec > ; # [doc = "DC_ACC6I_MSB"]
pub mod dc_acc6i_msb { # [doc = "Register `DC_ACC6I_MSB` reader"]
pub type R = crate :: R < DcAcc6iMsbSpec > ; # [doc = "Register `DC_ACC6I_MSB` writer"]
pub type W = crate :: W < DcAcc6iMsbSpec > ; # [doc = "Field `DC_ACC6I_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=5"]
pub type DcAcc6iMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC6I_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=5"]
pub type DcAcc6iMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=5"]
# [inline (always)]
pub fn dc_acc6i_msb (& self) -> DcAcc6iMsbR { DcAcc6iMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=5"]
# [inline (always)]
# [must_use]
pub fn dc_acc6i_msb (& mut self) -> DcAcc6iMsbW < DcAcc6iMsbSpec > { DcAcc6iMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc6iMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC6I_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6i_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6i_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc6iMsbSpec ; impl crate :: RegisterSpec for DcAcc6iMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc6i_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc6iMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc6i_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc6iMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC6I_MSB to value 0"]
impl crate :: Resettable for DcAcc6iMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST1Q_SW (rw) register accessor: DCEST1Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1q_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1q_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest1q_sw`]
module"]
# [doc (alias = "DCEST1Q_SW")]
pub type Dcest1qSw = crate :: Reg < dcest1q_sw :: Dcest1qSwSpec > ; # [doc = "DCEST1Q_SW"]
pub mod dcest1q_sw { # [doc = "Register `DCEST1Q_SW` reader"]
pub type R = crate :: R < Dcest1qSwSpec > ; # [doc = "Register `DCEST1Q_SW` writer"]
pub type W = crate :: W < Dcest1qSwSpec > ; # [doc = "Field `DCEST1Q_SW` reader - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 0."]
pub type Dcest1qSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST1Q_SW` writer - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 0."]
pub type Dcest1qSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 0."]
# [inline (always)]
pub fn dcest1q_sw (& self) -> Dcest1qSwR { Dcest1qSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 0."]
# [inline (always)]
# [must_use]
pub fn dcest1q_sw (& mut self) -> Dcest1qSwW < Dcest1qSwSpec > { Dcest1qSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest1qSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST1Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1q_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1q_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest1qSwSpec ; impl crate :: RegisterSpec for Dcest1qSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest1q_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest1qSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest1q_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest1qSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST1Q_SW to value 0"]
impl crate :: Resettable for Dcest1qSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST2Q_SW (rw) register accessor: DCEST2Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2q_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2q_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest2q_sw`]
module"]
# [doc (alias = "DCEST2Q_SW")]
pub type Dcest2qSw = crate :: Reg < dcest2q_sw :: Dcest2qSwSpec > ; # [doc = "DCEST2Q_SW"]
pub mod dcest2q_sw { # [doc = "Register `DCEST2Q_SW` reader"]
pub type R = crate :: R < Dcest2qSwSpec > ; # [doc = "Register `DCEST2Q_SW` writer"]
pub type W = crate :: W < Dcest2qSwSpec > ; # [doc = "Field `DCEST2Q_SW` reader - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 1."]
pub type Dcest2qSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST2Q_SW` writer - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 1."]
pub type Dcest2qSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 1."]
# [inline (always)]
pub fn dcest2q_sw (& self) -> Dcest2qSwR { Dcest2qSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 1."]
# [inline (always)]
# [must_use]
pub fn dcest2q_sw (& mut self) -> Dcest2qSwW < Dcest2qSwSpec > { Dcest2qSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest2qSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST2Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2q_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2q_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest2qSwSpec ; impl crate :: RegisterSpec for Dcest2qSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest2q_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest2qSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest2q_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest2qSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST2Q_SW to value 0"]
impl crate :: Resettable for Dcest2qSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST3Q_SW (rw) register accessor: DCEST3Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3q_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3q_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest3q_sw`]
module"]
# [doc (alias = "DCEST3Q_SW")]
pub type Dcest3qSw = crate :: Reg < dcest3q_sw :: Dcest3qSwSpec > ; # [doc = "DCEST3Q_SW"]
pub mod dcest3q_sw { # [doc = "Register `DCEST3Q_SW` reader"]
pub type R = crate :: R < Dcest3qSwSpec > ; # [doc = "Register `DCEST3Q_SW` writer"]
pub type W = crate :: W < Dcest3qSwSpec > ; # [doc = "Field `DCEST3Q_SW` reader - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 2."]
pub type Dcest3qSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST3Q_SW` writer - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 2."]
pub type Dcest3qSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 2."]
# [inline (always)]
pub fn dcest3q_sw (& self) -> Dcest3qSwR { Dcest3qSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 2."]
# [inline (always)]
# [must_use]
pub fn dcest3q_sw (& mut self) -> Dcest3qSwW < Dcest3qSwSpec > { Dcest3qSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest3qSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST3Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3q_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3q_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest3qSwSpec ; impl crate :: RegisterSpec for Dcest3qSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest3q_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest3qSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest3q_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest3qSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST3Q_SW to value 0"]
impl crate :: Resettable for Dcest3qSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST4Q_SW (rw) register accessor: DCEST4Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4q_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4q_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest4q_sw`]
module"]
# [doc (alias = "DCEST4Q_SW")]
pub type Dcest4qSw = crate :: Reg < dcest4q_sw :: Dcest4qSwSpec > ; # [doc = "DCEST4Q_SW"]
pub mod dcest4q_sw { # [doc = "Register `DCEST4Q_SW` reader"]
pub type R = crate :: R < Dcest4qSwSpec > ; # [doc = "Register `DCEST4Q_SW` writer"]
pub type W = crate :: W < Dcest4qSwSpec > ; # [doc = "Field `DCEST4Q_SW` reader - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 3."]
pub type Dcest4qSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST4Q_SW` writer - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 3."]
pub type Dcest4qSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 3."]
# [inline (always)]
pub fn dcest4q_sw (& self) -> Dcest4qSwR { Dcest4qSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 3."]
# [inline (always)]
# [must_use]
pub fn dcest4q_sw (& mut self) -> Dcest4qSwW < Dcest4qSwSpec > { Dcest4qSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest4qSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST4Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4q_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4q_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest4qSwSpec ; impl crate :: RegisterSpec for Dcest4qSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest4q_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest4qSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest4q_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest4qSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST4Q_SW to value 0"]
impl crate :: Resettable for Dcest4qSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST5Q_SW (rw) register accessor: DCEST5Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5q_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5q_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest5q_sw`]
module"]
# [doc (alias = "DCEST5Q_SW")]
pub type Dcest5qSw = crate :: Reg < dcest5q_sw :: Dcest5qSwSpec > ; # [doc = "DCEST5Q_SW"]
pub mod dcest5q_sw { # [doc = "Register `DCEST5Q_SW` reader"]
pub type R = crate :: R < Dcest5qSwSpec > ; # [doc = "Register `DCEST5Q_SW` writer"]
pub type W = crate :: W < Dcest5qSwSpec > ; # [doc = "Field `DCEST5Q_SW` reader - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 4."]
pub type Dcest5qSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST5Q_SW` writer - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 4."]
pub type Dcest5qSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 4."]
# [inline (always)]
pub fn dcest5q_sw (& self) -> Dcest5qSwR { Dcest5qSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 4."]
# [inline (always)]
# [must_use]
pub fn dcest5q_sw (& mut self) -> Dcest5qSwW < Dcest5qSwSpec > { Dcest5qSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest5qSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST5Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5q_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5q_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest5qSwSpec ; impl crate :: RegisterSpec for Dcest5qSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest5q_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest5qSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest5q_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest5qSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST5Q_SW to value 0"]
impl crate :: Resettable for Dcest5qSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST6Q_SW (rw) register accessor: DCEST6Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6q_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6q_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest6q_sw`]
module"]
# [doc (alias = "DCEST6Q_SW")]
pub type Dcest6qSw = crate :: Reg < dcest6q_sw :: Dcest6qSwSpec > ; # [doc = "DCEST6Q_SW"]
pub mod dcest6q_sw { # [doc = "Register `DCEST6Q_SW` reader"]
pub type R = crate :: R < Dcest6qSwSpec > ; # [doc = "Register `DCEST6Q_SW` writer"]
pub type W = crate :: W < Dcest6qSwSpec > ; # [doc = "Field `DCEST6Q_SW` reader - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 5."]
pub type Dcest6qSwR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST6Q_SW` writer - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 5."]
pub type Dcest6qSwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 5."]
# [inline (always)]
pub fn dcest6q_sw (& self) -> Dcest6qSwR { Dcest6qSwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 5."]
# [inline (always)]
# [must_use]
pub fn dcest6q_sw (& mut self) -> Dcest6qSwW < Dcest6qSwSpec > { Dcest6qSwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest6qSwSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST6Q_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6q_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6q_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest6qSwSpec ; impl crate :: RegisterSpec for Dcest6qSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest6q_sw::R`](R) reader structure"]
impl crate :: Readable for Dcest6qSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest6q_sw::W`](W) writer structure"]
impl crate :: Writable for Dcest6qSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST6Q_SW to value 0"]
impl crate :: Resettable for Dcest6qSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST1Q (rw) register accessor: DCEST1Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest1q`]
module"]
# [doc (alias = "DCEST1Q")]
pub type Dcest1q = crate :: Reg < dcest1q :: Dcest1qSpec > ; # [doc = "DCEST1Q"]
pub mod dcest1q { # [doc = "Register `DCEST1Q` reader"]
pub type R = crate :: R < Dcest1qSpec > ; # [doc = "Register `DCEST1Q` writer"]
pub type W = crate :: W < Dcest1qSpec > ; # [doc = "Field `DCEST1Q` reader - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =0 ."]
pub type Dcest1qR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST1Q` writer - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =0 ."]
pub type Dcest1qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =0 ."]
# [inline (always)]
pub fn dcest1q (& self) -> Dcest1qR { Dcest1qR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =0 ."]
# [inline (always)]
# [must_use]
pub fn dcest1q (& mut self) -> Dcest1qW < Dcest1qSpec > { Dcest1qW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest1qSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST1Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest1qSpec ; impl crate :: RegisterSpec for Dcest1qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest1q::R`](R) reader structure"]
impl crate :: Readable for Dcest1qSpec { } # [doc = "`write(|w| ..)` method takes [`dcest1q::W`](W) writer structure"]
impl crate :: Writable for Dcest1qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST1Q to value 0"]
impl crate :: Resettable for Dcest1qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST2Q (rw) register accessor: DCEST2Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest2q`]
module"]
# [doc (alias = "DCEST2Q")]
pub type Dcest2q = crate :: Reg < dcest2q :: Dcest2qSpec > ; # [doc = "DCEST2Q"]
pub mod dcest2q { # [doc = "Register `DCEST2Q` reader"]
pub type R = crate :: R < Dcest2qSpec > ; # [doc = "Register `DCEST2Q` writer"]
pub type W = crate :: W < Dcest2qSpec > ; # [doc = "Field `DCEST2Q` reader - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =1 ."]
pub type Dcest2qR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST2Q` writer - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =1 ."]
pub type Dcest2qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =1 ."]
# [inline (always)]
pub fn dcest2q (& self) -> Dcest2qR { Dcest2qR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =1 ."]
# [inline (always)]
# [must_use]
pub fn dcest2q (& mut self) -> Dcest2qW < Dcest2qSpec > { Dcest2qW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest2qSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST2Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest2qSpec ; impl crate :: RegisterSpec for Dcest2qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest2q::R`](R) reader structure"]
impl crate :: Readable for Dcest2qSpec { } # [doc = "`write(|w| ..)` method takes [`dcest2q::W`](W) writer structure"]
impl crate :: Writable for Dcest2qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST2Q to value 0"]
impl crate :: Resettable for Dcest2qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST3Q (rw) register accessor: DCEST3Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest3q`]
module"]
# [doc (alias = "DCEST3Q")]
pub type Dcest3q = crate :: Reg < dcest3q :: Dcest3qSpec > ; # [doc = "DCEST3Q"]
pub mod dcest3q { # [doc = "Register `DCEST3Q` reader"]
pub type R = crate :: R < Dcest3qSpec > ; # [doc = "Register `DCEST3Q` writer"]
pub type W = crate :: W < Dcest3qSpec > ; # [doc = "Field `DCEST3Q` reader - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =2 ."]
pub type Dcest3qR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST3Q` writer - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =2 ."]
pub type Dcest3qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =2 ."]
# [inline (always)]
pub fn dcest3q (& self) -> Dcest3qR { Dcest3qR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =2 ."]
# [inline (always)]
# [must_use]
pub fn dcest3q (& mut self) -> Dcest3qW < Dcest3qSpec > { Dcest3qW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest3qSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST3Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest3qSpec ; impl crate :: RegisterSpec for Dcest3qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest3q::R`](R) reader structure"]
impl crate :: Readable for Dcest3qSpec { } # [doc = "`write(|w| ..)` method takes [`dcest3q::W`](W) writer structure"]
impl crate :: Writable for Dcest3qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST3Q to value 0"]
impl crate :: Resettable for Dcest3qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST4Q (rw) register accessor: DCEST4Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest4q`]
module"]
# [doc (alias = "DCEST4Q")]
pub type Dcest4q = crate :: Reg < dcest4q :: Dcest4qSpec > ; # [doc = "DCEST4Q"]
pub mod dcest4q { # [doc = "Register `DCEST4Q` reader"]
pub type R = crate :: R < Dcest4qSpec > ; # [doc = "Register `DCEST4Q` writer"]
pub type W = crate :: W < Dcest4qSpec > ; # [doc = "Field `DCEST4Q` reader - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =3."]
pub type Dcest4qR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST4Q` writer - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =3."]
pub type Dcest4qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =3."]
# [inline (always)]
pub fn dcest4q (& self) -> Dcest4qR { Dcest4qR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =3."]
# [inline (always)]
# [must_use]
pub fn dcest4q (& mut self) -> Dcest4qW < Dcest4qSpec > { Dcest4qW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest4qSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST4Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest4qSpec ; impl crate :: RegisterSpec for Dcest4qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest4q::R`](R) reader structure"]
impl crate :: Readable for Dcest4qSpec { } # [doc = "`write(|w| ..)` method takes [`dcest4q::W`](W) writer structure"]
impl crate :: Writable for Dcest4qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST4Q to value 0"]
impl crate :: Resettable for Dcest4qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST5Q (rw) register accessor: DCEST5Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest5q`]
module"]
# [doc (alias = "DCEST5Q")]
pub type Dcest5q = crate :: Reg < dcest5q :: Dcest5qSpec > ; # [doc = "DCEST5Q"]
pub mod dcest5q { # [doc = "Register `DCEST5Q` reader"]
pub type R = crate :: R < Dcest5qSpec > ; # [doc = "Register `DCEST5Q` writer"]
pub type W = crate :: W < Dcest5qSpec > ; # [doc = "Field `DCEST5Q` reader - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =4 ."]
pub type Dcest5qR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST5Q` writer - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =4 ."]
pub type Dcest5qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =4 ."]
# [inline (always)]
pub fn dcest5q (& self) -> Dcest5qR { Dcest5qR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =4 ."]
# [inline (always)]
# [must_use]
pub fn dcest5q (& mut self) -> Dcest5qW < Dcest5qSpec > { Dcest5qW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest5qSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST5Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest5qSpec ; impl crate :: RegisterSpec for Dcest5qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest5q::R`](R) reader structure"]
impl crate :: Readable for Dcest5qSpec { } # [doc = "`write(|w| ..)` method takes [`dcest5q::W`](W) writer structure"]
impl crate :: Writable for Dcest5qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST5Q to value 0"]
impl crate :: Resettable for Dcest5qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST6Q (rw) register accessor: DCEST6Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest6q`]
module"]
# [doc (alias = "DCEST6Q")]
pub type Dcest6q = crate :: Reg < dcest6q :: Dcest6qSpec > ; # [doc = "DCEST6Q"]
pub mod dcest6q { # [doc = "Register `DCEST6Q` reader"]
pub type R = crate :: R < Dcest6qSpec > ; # [doc = "Register `DCEST6Q` writer"]
pub type W = crate :: W < Dcest6qSpec > ; # [doc = "Field `DCEST6Q` reader - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =5 ."]
pub type Dcest6qR = crate :: FieldReader < u32 > ; # [doc = "Field `DCEST6Q` writer - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =5 ."]
pub type Dcest6qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =5 ."]
# [inline (always)]
pub fn dcest6q (& self) -> Dcest6qR { Dcest6qR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =5 ."]
# [inline (always)]
# [must_use]
pub fn dcest6q (& mut self) -> Dcest6qW < Dcest6qSpec > { Dcest6qW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest6qSpec > { Nu1W :: new (self , 24) } } # [doc = "DCEST6Q\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest6qSpec ; impl crate :: RegisterSpec for Dcest6qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest6q::R`](R) reader structure"]
impl crate :: Readable for Dcest6qSpec { } # [doc = "`write(|w| ..)` method takes [`dcest6q::W`](W) writer structure"]
impl crate :: Writable for Dcest6qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST6Q to value 0"]
impl crate :: Resettable for Dcest6qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC1Q_LSB (rw) register accessor: DC_ACC1Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1q_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1q_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc1q_lsb`]
module"]
# [doc (alias = "DC_ACC1Q_LSB")]
pub type DcAcc1qLsb = crate :: Reg < dc_acc1q_lsb :: DcAcc1qLsbSpec > ; # [doc = "DC_ACC1Q_LSB"]
pub mod dc_acc1q_lsb { # [doc = "Register `DC_ACC1Q_LSB` reader"]
pub type R = crate :: R < DcAcc1qLsbSpec > ; # [doc = "Register `DC_ACC1Q_LSB` writer"]
pub type W = crate :: W < DcAcc1qLsbSpec > ; # [doc = "Field `DC_ACC1Q_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=0"]
pub type DcAcc1qLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC1Q_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=0"]
pub type DcAcc1qLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=0"]
# [inline (always)]
pub fn dc_acc1q_lsb (& self) -> DcAcc1qLsbR { DcAcc1qLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=0"]
# [inline (always)]
# [must_use]
pub fn dc_acc1q_lsb (& mut self) -> DcAcc1qLsbW < DcAcc1qLsbSpec > { DcAcc1qLsbW :: new (self , 0) } } # [doc = "DC_ACC1Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1q_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1q_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc1qLsbSpec ; impl crate :: RegisterSpec for DcAcc1qLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc1q_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc1qLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc1q_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc1qLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC1Q_LSB to value 0"]
impl crate :: Resettable for DcAcc1qLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC1Q_MSB (rw) register accessor: DC_ACC1Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1q_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1q_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc1q_msb`]
module"]
# [doc (alias = "DC_ACC1Q_MSB")]
pub type DcAcc1qMsb = crate :: Reg < dc_acc1q_msb :: DcAcc1qMsbSpec > ; # [doc = "DC_ACC1Q_MSB"]
pub mod dc_acc1q_msb { # [doc = "Register `DC_ACC1Q_MSB` reader"]
pub type R = crate :: R < DcAcc1qMsbSpec > ; # [doc = "Register `DC_ACC1Q_MSB` writer"]
pub type W = crate :: W < DcAcc1qMsbSpec > ; # [doc = "Field `DC_ACC1Q_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=0"]
pub type DcAcc1qMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC1Q_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=0"]
pub type DcAcc1qMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=0"]
# [inline (always)]
pub fn dc_acc1q_msb (& self) -> DcAcc1qMsbR { DcAcc1qMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=0"]
# [inline (always)]
# [must_use]
pub fn dc_acc1q_msb (& mut self) -> DcAcc1qMsbW < DcAcc1qMsbSpec > { DcAcc1qMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc1qMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC1Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc1q_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc1q_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc1qMsbSpec ; impl crate :: RegisterSpec for DcAcc1qMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc1q_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc1qMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc1q_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc1qMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC1Q_MSB to value 0"]
impl crate :: Resettable for DcAcc1qMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC2Q_LSB (rw) register accessor: DC_ACC2Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2q_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2q_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc2q_lsb`]
module"]
# [doc (alias = "DC_ACC2Q_LSB")]
pub type DcAcc2qLsb = crate :: Reg < dc_acc2q_lsb :: DcAcc2qLsbSpec > ; # [doc = "DC_ACC2Q_LSB"]
pub mod dc_acc2q_lsb { # [doc = "Register `DC_ACC2Q_LSB` reader"]
pub type R = crate :: R < DcAcc2qLsbSpec > ; # [doc = "Register `DC_ACC2Q_LSB` writer"]
pub type W = crate :: W < DcAcc2qLsbSpec > ; # [doc = "Field `DC_ACC2Q_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=1"]
pub type DcAcc2qLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC2Q_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=1"]
pub type DcAcc2qLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=1"]
# [inline (always)]
pub fn dc_acc2q_lsb (& self) -> DcAcc2qLsbR { DcAcc2qLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=1"]
# [inline (always)]
# [must_use]
pub fn dc_acc2q_lsb (& mut self) -> DcAcc2qLsbW < DcAcc2qLsbSpec > { DcAcc2qLsbW :: new (self , 0) } } # [doc = "DC_ACC2Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2q_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2q_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc2qLsbSpec ; impl crate :: RegisterSpec for DcAcc2qLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc2q_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc2qLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc2q_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc2qLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC2Q_LSB to value 0"]
impl crate :: Resettable for DcAcc2qLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC2Q_MSB (rw) register accessor: DC_ACC2Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2q_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2q_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc2q_msb`]
module"]
# [doc (alias = "DC_ACC2Q_MSB")]
pub type DcAcc2qMsb = crate :: Reg < dc_acc2q_msb :: DcAcc2qMsbSpec > ; # [doc = "DC_ACC2Q_MSB"]
pub mod dc_acc2q_msb { # [doc = "Register `DC_ACC2Q_MSB` reader"]
pub type R = crate :: R < DcAcc2qMsbSpec > ; # [doc = "Register `DC_ACC2Q_MSB` writer"]
pub type W = crate :: W < DcAcc2qMsbSpec > ; # [doc = "Field `DC_ACC2Q_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=1"]
pub type DcAcc2qMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC2Q_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=1"]
pub type DcAcc2qMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=1"]
# [inline (always)]
pub fn dc_acc2q_msb (& self) -> DcAcc2qMsbR { DcAcc2qMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=1"]
# [inline (always)]
# [must_use]
pub fn dc_acc2q_msb (& mut self) -> DcAcc2qMsbW < DcAcc2qMsbSpec > { DcAcc2qMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc2qMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC2Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc2q_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc2q_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc2qMsbSpec ; impl crate :: RegisterSpec for DcAcc2qMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc2q_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc2qMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc2q_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc2qMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC2Q_MSB to value 0"]
impl crate :: Resettable for DcAcc2qMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC3Q_LSB (rw) register accessor: DC_ACC3Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3q_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3q_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc3q_lsb`]
module"]
# [doc (alias = "DC_ACC3Q_LSB")]
pub type DcAcc3qLsb = crate :: Reg < dc_acc3q_lsb :: DcAcc3qLsbSpec > ; # [doc = "DC_ACC3Q_LSB"]
pub mod dc_acc3q_lsb { # [doc = "Register `DC_ACC3Q_LSB` reader"]
pub type R = crate :: R < DcAcc3qLsbSpec > ; # [doc = "Register `DC_ACC3Q_LSB` writer"]
pub type W = crate :: W < DcAcc3qLsbSpec > ; # [doc = "Field `DC_ACC3Q_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=2"]
pub type DcAcc3qLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC3Q_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=2"]
pub type DcAcc3qLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=2"]
# [inline (always)]
pub fn dc_acc3q_lsb (& self) -> DcAcc3qLsbR { DcAcc3qLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=2"]
# [inline (always)]
# [must_use]
pub fn dc_acc3q_lsb (& mut self) -> DcAcc3qLsbW < DcAcc3qLsbSpec > { DcAcc3qLsbW :: new (self , 0) } } # [doc = "DC_ACC3Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3q_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3q_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc3qLsbSpec ; impl crate :: RegisterSpec for DcAcc3qLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc3q_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc3qLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc3q_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc3qLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC3Q_LSB to value 0"]
impl crate :: Resettable for DcAcc3qLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC3Q_MSB (rw) register accessor: DC_ACC3Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3q_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3q_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc3q_msb`]
module"]
# [doc (alias = "DC_ACC3Q_MSB")]
pub type DcAcc3qMsb = crate :: Reg < dc_acc3q_msb :: DcAcc3qMsbSpec > ; # [doc = "DC_ACC3Q_MSB"]
pub mod dc_acc3q_msb { # [doc = "Register `DC_ACC3Q_MSB` reader"]
pub type R = crate :: R < DcAcc3qMsbSpec > ; # [doc = "Register `DC_ACC3Q_MSB` writer"]
pub type W = crate :: W < DcAcc3qMsbSpec > ; # [doc = "Field `DC_ACC3Q_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=2"]
pub type DcAcc3qMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC3Q_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=2"]
pub type DcAcc3qMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=2"]
# [inline (always)]
pub fn dc_acc3q_msb (& self) -> DcAcc3qMsbR { DcAcc3qMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=2"]
# [inline (always)]
# [must_use]
pub fn dc_acc3q_msb (& mut self) -> DcAcc3qMsbW < DcAcc3qMsbSpec > { DcAcc3qMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc3qMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC3Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc3q_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc3q_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc3qMsbSpec ; impl crate :: RegisterSpec for DcAcc3qMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc3q_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc3qMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc3q_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc3qMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC3Q_MSB to value 0"]
impl crate :: Resettable for DcAcc3qMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC4Q_LSB (rw) register accessor: DC_ACC4Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4q_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4q_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc4q_lsb`]
module"]
# [doc (alias = "DC_ACC4Q_LSB")]
pub type DcAcc4qLsb = crate :: Reg < dc_acc4q_lsb :: DcAcc4qLsbSpec > ; # [doc = "DC_ACC4Q_LSB"]
pub mod dc_acc4q_lsb { # [doc = "Register `DC_ACC4Q_LSB` reader"]
pub type R = crate :: R < DcAcc4qLsbSpec > ; # [doc = "Register `DC_ACC4Q_LSB` writer"]
pub type W = crate :: W < DcAcc4qLsbSpec > ; # [doc = "Field `DC_ACC4Q_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=3"]
pub type DcAcc4qLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC4Q_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=3"]
pub type DcAcc4qLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=3"]
# [inline (always)]
pub fn dc_acc4q_lsb (& self) -> DcAcc4qLsbR { DcAcc4qLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=3"]
# [inline (always)]
# [must_use]
pub fn dc_acc4q_lsb (& mut self) -> DcAcc4qLsbW < DcAcc4qLsbSpec > { DcAcc4qLsbW :: new (self , 0) } } # [doc = "DC_ACC4Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4q_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4q_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc4qLsbSpec ; impl crate :: RegisterSpec for DcAcc4qLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc4q_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc4qLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc4q_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc4qLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC4Q_LSB to value 0"]
impl crate :: Resettable for DcAcc4qLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC4Q_MSB (rw) register accessor: DC_ACC4Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4q_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4q_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc4q_msb`]
module"]
# [doc (alias = "DC_ACC4Q_MSB")]
pub type DcAcc4qMsb = crate :: Reg < dc_acc4q_msb :: DcAcc4qMsbSpec > ; # [doc = "DC_ACC4Q_MSB"]
pub mod dc_acc4q_msb { # [doc = "Register `DC_ACC4Q_MSB` reader"]
pub type R = crate :: R < DcAcc4qMsbSpec > ; # [doc = "Register `DC_ACC4Q_MSB` writer"]
pub type W = crate :: W < DcAcc4qMsbSpec > ; # [doc = "Field `DC_ACC4Q_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=3"]
pub type DcAcc4qMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC4Q_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=3"]
pub type DcAcc4qMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=3"]
# [inline (always)]
pub fn dc_acc4q_msb (& self) -> DcAcc4qMsbR { DcAcc4qMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=3"]
# [inline (always)]
# [must_use]
pub fn dc_acc4q_msb (& mut self) -> DcAcc4qMsbW < DcAcc4qMsbSpec > { DcAcc4qMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc4qMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC4Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc4q_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc4q_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc4qMsbSpec ; impl crate :: RegisterSpec for DcAcc4qMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc4q_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc4qMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc4q_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc4qMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC4Q_MSB to value 0"]
impl crate :: Resettable for DcAcc4qMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC5Q_LSB (rw) register accessor: DC_ACC5Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5q_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5q_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc5q_lsb`]
module"]
# [doc (alias = "DC_ACC5Q_LSB")]
pub type DcAcc5qLsb = crate :: Reg < dc_acc5q_lsb :: DcAcc5qLsbSpec > ; # [doc = "DC_ACC5Q_LSB"]
pub mod dc_acc5q_lsb { # [doc = "Register `DC_ACC5Q_LSB` reader"]
pub type R = crate :: R < DcAcc5qLsbSpec > ; # [doc = "Register `DC_ACC5Q_LSB` writer"]
pub type W = crate :: W < DcAcc5qLsbSpec > ; # [doc = "Field `DC_ACC5Q_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=4"]
pub type DcAcc5qLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC5Q_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=4"]
pub type DcAcc5qLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=4"]
# [inline (always)]
pub fn dc_acc5q_lsb (& self) -> DcAcc5qLsbR { DcAcc5qLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=4"]
# [inline (always)]
# [must_use]
pub fn dc_acc5q_lsb (& mut self) -> DcAcc5qLsbW < DcAcc5qLsbSpec > { DcAcc5qLsbW :: new (self , 0) } } # [doc = "DC_ACC5Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5q_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5q_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc5qLsbSpec ; impl crate :: RegisterSpec for DcAcc5qLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc5q_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc5qLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc5q_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc5qLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC5Q_LSB to value 0"]
impl crate :: Resettable for DcAcc5qLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC5Q_MSB (rw) register accessor: DC_ACC5Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5q_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5q_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc5q_msb`]
module"]
# [doc (alias = "DC_ACC5Q_MSB")]
pub type DcAcc5qMsb = crate :: Reg < dc_acc5q_msb :: DcAcc5qMsbSpec > ; # [doc = "DC_ACC5Q_MSB"]
pub mod dc_acc5q_msb { # [doc = "Register `DC_ACC5Q_MSB` reader"]
pub type R = crate :: R < DcAcc5qMsbSpec > ; # [doc = "Register `DC_ACC5Q_MSB` writer"]
pub type W = crate :: W < DcAcc5qMsbSpec > ; # [doc = "Field `DC_ACC5Q_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=4"]
pub type DcAcc5qMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC5Q_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=4"]
pub type DcAcc5qMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=4"]
# [inline (always)]
pub fn dc_acc5q_msb (& self) -> DcAcc5qMsbR { DcAcc5qMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=4"]
# [inline (always)]
# [must_use]
pub fn dc_acc5q_msb (& mut self) -> DcAcc5qMsbW < DcAcc5qMsbSpec > { DcAcc5qMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc5qMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC5Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc5q_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc5q_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc5qMsbSpec ; impl crate :: RegisterSpec for DcAcc5qMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc5q_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc5qMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc5q_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc5qMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC5Q_MSB to value 0"]
impl crate :: Resettable for DcAcc5qMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC6Q_LSB (rw) register accessor: DC_ACC6Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6q_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6q_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc6q_lsb`]
module"]
# [doc (alias = "DC_ACC6Q_LSB")]
pub type DcAcc6qLsb = crate :: Reg < dc_acc6q_lsb :: DcAcc6qLsbSpec > ; # [doc = "DC_ACC6Q_LSB"]
pub mod dc_acc6q_lsb { # [doc = "Register `DC_ACC6Q_LSB` reader"]
pub type R = crate :: R < DcAcc6qLsbSpec > ; # [doc = "Register `DC_ACC6Q_LSB` writer"]
pub type W = crate :: W < DcAcc6qLsbSpec > ; # [doc = "Field `DC_ACC6Q_LSB` reader - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=5"]
pub type DcAcc6qLsbR = crate :: FieldReader < u32 > ; # [doc = "Field `DC_ACC6Q_LSB` writer - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=5"]
pub type DcAcc6qLsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=5"]
# [inline (always)]
pub fn dc_acc6q_lsb (& self) -> DcAcc6qLsbR { DcAcc6qLsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=5"]
# [inline (always)]
# [must_use]
pub fn dc_acc6q_lsb (& mut self) -> DcAcc6qLsbW < DcAcc6qLsbSpec > { DcAcc6qLsbW :: new (self , 0) } } # [doc = "DC_ACC6Q_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6q_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6q_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc6qLsbSpec ; impl crate :: RegisterSpec for DcAcc6qLsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc6q_lsb::R`](R) reader structure"]
impl crate :: Readable for DcAcc6qLsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc6q_lsb::W`](W) writer structure"]
impl crate :: Writable for DcAcc6qLsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC6Q_LSB to value 0"]
impl crate :: Resettable for DcAcc6qLsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DC_ACC6Q_MSB (rw) register accessor: DC_ACC6Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6q_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6q_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_acc6q_msb`]
module"]
# [doc (alias = "DC_ACC6Q_MSB")]
pub type DcAcc6qMsb = crate :: Reg < dc_acc6q_msb :: DcAcc6qMsbSpec > ; # [doc = "DC_ACC6Q_MSB"]
pub mod dc_acc6q_msb { # [doc = "Register `DC_ACC6Q_MSB` reader"]
pub type R = crate :: R < DcAcc6qMsbSpec > ; # [doc = "Register `DC_ACC6Q_MSB` writer"]
pub type W = crate :: W < DcAcc6qMsbSpec > ; # [doc = "Field `DC_ACC6Q_MSB` reader - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=5"]
pub type DcAcc6qMsbR = crate :: FieldReader ; # [doc = "Field `DC_ACC6Q_MSB` writer - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=5"]
pub type DcAcc6qMsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=5"]
# [inline (always)]
pub fn dc_acc6q_msb (& self) -> DcAcc6qMsbR { DcAcc6qMsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=5"]
# [inline (always)]
# [must_use]
pub fn dc_acc6q_msb (& mut self) -> DcAcc6qMsbW < DcAcc6qMsbSpec > { DcAcc6qMsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcAcc6qMsbSpec > { Nu1W :: new (self , 4) } } # [doc = "DC_ACC6Q_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_acc6q_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_acc6q_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcAcc6qMsbSpec ; impl crate :: RegisterSpec for DcAcc6qMsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dc_acc6q_msb::R`](R) reader structure"]
impl crate :: Readable for DcAcc6qMsbSpec { } # [doc = "`write(|w| ..)` method takes [`dc_acc6q_msb::W`](W) writer structure"]
impl crate :: Writable for DcAcc6qMsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DC_ACC6Q_MSB to value 0"]
impl crate :: Resettable for DcAcc6qMsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCACC1_CLIP (rw) register accessor: DCACC1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcacc1_clip`]
module"]
# [doc (alias = "DCACC1_CLIP")]
pub type Dcacc1Clip = crate :: Reg < dcacc1_clip :: Dcacc1ClipSpec > ; # [doc = "DCACC1_CLIP"]
pub mod dcacc1_clip { # [doc = "Register `DCACC1_CLIP` reader"]
pub type R = crate :: R < Dcacc1ClipSpec > ; # [doc = "Register `DCACC1_CLIP` writer"]
pub type W = crate :: W < Dcacc1ClipSpec > ; # [doc = "Field `DCACC1_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =0"]
pub type Dcacc1ClipR = crate :: BitReader ; # [doc = "Field `DCACC1_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =0"]
pub type Dcacc1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =0"]
# [inline (always)]
pub fn dcacc1_clip (& self) -> Dcacc1ClipR { Dcacc1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn dcacc1_clip (& mut self) -> Dcacc1ClipW < Dcacc1ClipSpec > { Dcacc1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcacc1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCACC1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcacc1ClipSpec ; impl crate :: RegisterSpec for Dcacc1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcacc1_clip::R`](R) reader structure"]
impl crate :: Readable for Dcacc1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcacc1_clip::W`](W) writer structure"]
impl crate :: Writable for Dcacc1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCACC1_CLIP to value 0"]
impl crate :: Resettable for Dcacc1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCACC2_CLIP (rw) register accessor: DCACC2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcacc2_clip`]
module"]
# [doc (alias = "DCACC2_CLIP")]
pub type Dcacc2Clip = crate :: Reg < dcacc2_clip :: Dcacc2ClipSpec > ; # [doc = "DCACC2_CLIP"]
pub mod dcacc2_clip { # [doc = "Register `DCACC2_CLIP` reader"]
pub type R = crate :: R < Dcacc2ClipSpec > ; # [doc = "Register `DCACC2_CLIP` writer"]
pub type W = crate :: W < Dcacc2ClipSpec > ; # [doc = "Field `DCACC2_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =1"]
pub type Dcacc2ClipR = crate :: BitReader ; # [doc = "Field `DCACC2_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =1"]
pub type Dcacc2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =1"]
# [inline (always)]
pub fn dcacc2_clip (& self) -> Dcacc2ClipR { Dcacc2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn dcacc2_clip (& mut self) -> Dcacc2ClipW < Dcacc2ClipSpec > { Dcacc2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcacc2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCACC2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcacc2ClipSpec ; impl crate :: RegisterSpec for Dcacc2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcacc2_clip::R`](R) reader structure"]
impl crate :: Readable for Dcacc2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcacc2_clip::W`](W) writer structure"]
impl crate :: Writable for Dcacc2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCACC2_CLIP to value 0"]
impl crate :: Resettable for Dcacc2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCACC3_CLIP (rw) register accessor: DCACC3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcacc3_clip`]
module"]
# [doc (alias = "DCACC3_CLIP")]
pub type Dcacc3Clip = crate :: Reg < dcacc3_clip :: Dcacc3ClipSpec > ; # [doc = "DCACC3_CLIP"]
pub mod dcacc3_clip { # [doc = "Register `DCACC3_CLIP` reader"]
pub type R = crate :: R < Dcacc3ClipSpec > ; # [doc = "Register `DCACC3_CLIP` writer"]
pub type W = crate :: W < Dcacc3ClipSpec > ; # [doc = "Field `DCACC3_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =2"]
pub type Dcacc3ClipR = crate :: BitReader ; # [doc = "Field `DCACC3_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =2"]
pub type Dcacc3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =2"]
# [inline (always)]
pub fn dcacc3_clip (& self) -> Dcacc3ClipR { Dcacc3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn dcacc3_clip (& mut self) -> Dcacc3ClipW < Dcacc3ClipSpec > { Dcacc3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcacc3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCACC3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcacc3ClipSpec ; impl crate :: RegisterSpec for Dcacc3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcacc3_clip::R`](R) reader structure"]
impl crate :: Readable for Dcacc3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcacc3_clip::W`](W) writer structure"]
impl crate :: Writable for Dcacc3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCACC3_CLIP to value 0"]
impl crate :: Resettable for Dcacc3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCACC4_CLIP (rw) register accessor: DCACC4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcacc4_clip`]
module"]
# [doc (alias = "DCACC4_CLIP")]
pub type Dcacc4Clip = crate :: Reg < dcacc4_clip :: Dcacc4ClipSpec > ; # [doc = "DCACC4_CLIP"]
pub mod dcacc4_clip { # [doc = "Register `DCACC4_CLIP` reader"]
pub type R = crate :: R < Dcacc4ClipSpec > ; # [doc = "Register `DCACC4_CLIP` writer"]
pub type W = crate :: W < Dcacc4ClipSpec > ; # [doc = "Field `DCACC4_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =3"]
pub type Dcacc4ClipR = crate :: BitReader ; # [doc = "Field `DCACC4_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =3"]
pub type Dcacc4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =3"]
# [inline (always)]
pub fn dcacc4_clip (& self) -> Dcacc4ClipR { Dcacc4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn dcacc4_clip (& mut self) -> Dcacc4ClipW < Dcacc4ClipSpec > { Dcacc4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcacc4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCACC4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcacc4ClipSpec ; impl crate :: RegisterSpec for Dcacc4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcacc4_clip::R`](R) reader structure"]
impl crate :: Readable for Dcacc4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcacc4_clip::W`](W) writer structure"]
impl crate :: Writable for Dcacc4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCACC4_CLIP to value 0"]
impl crate :: Resettable for Dcacc4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCACC5_CLIP (rw) register accessor: DCACC5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcacc5_clip`]
module"]
# [doc (alias = "DCACC5_CLIP")]
pub type Dcacc5Clip = crate :: Reg < dcacc5_clip :: Dcacc5ClipSpec > ; # [doc = "DCACC5_CLIP"]
pub mod dcacc5_clip { # [doc = "Register `DCACC5_CLIP` reader"]
pub type R = crate :: R < Dcacc5ClipSpec > ; # [doc = "Register `DCACC5_CLIP` writer"]
pub type W = crate :: W < Dcacc5ClipSpec > ; # [doc = "Field `DCACC5_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =4"]
pub type Dcacc5ClipR = crate :: BitReader ; # [doc = "Field `DCACC5_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =4"]
pub type Dcacc5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =4"]
# [inline (always)]
pub fn dcacc5_clip (& self) -> Dcacc5ClipR { Dcacc5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn dcacc5_clip (& mut self) -> Dcacc5ClipW < Dcacc5ClipSpec > { Dcacc5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcacc5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCACC5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcacc5ClipSpec ; impl crate :: RegisterSpec for Dcacc5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcacc5_clip::R`](R) reader structure"]
impl crate :: Readable for Dcacc5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcacc5_clip::W`](W) writer structure"]
impl crate :: Writable for Dcacc5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCACC5_CLIP to value 0"]
impl crate :: Resettable for Dcacc5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCACC6_CLIP (rw) register accessor: DCACC6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcacc6_clip`]
module"]
# [doc (alias = "DCACC6_CLIP")]
pub type Dcacc6Clip = crate :: Reg < dcacc6_clip :: Dcacc6ClipSpec > ; # [doc = "DCACC6_CLIP"]
pub mod dcacc6_clip { # [doc = "Register `DCACC6_CLIP` reader"]
pub type R = crate :: R < Dcacc6ClipSpec > ; # [doc = "Register `DCACC6_CLIP` writer"]
pub type W = crate :: W < Dcacc6ClipSpec > ; # [doc = "Field `DCACC6_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =5"]
pub type Dcacc6ClipR = crate :: BitReader ; # [doc = "Field `DCACC6_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =5"]
pub type Dcacc6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =5"]
# [inline (always)]
pub fn dcacc6_clip (& self) -> Dcacc6ClipR { Dcacc6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q of DC accumulators for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn dcacc6_clip (& mut self) -> Dcacc6ClipW < Dcacc6ClipSpec > { Dcacc6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcacc6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCACC6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcacc6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcacc6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcacc6ClipSpec ; impl crate :: RegisterSpec for Dcacc6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcacc6_clip::R`](R) reader structure"]
impl crate :: Readable for Dcacc6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcacc6_clip::W`](W) writer structure"]
impl crate :: Writable for Dcacc6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCACC6_CLIP to value 0"]
impl crate :: Resettable for Dcacc6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST1_CLIP (rw) register accessor: DCEST1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest1_clip`]
module"]
# [doc (alias = "DCEST1_CLIP")]
pub type Dcest1Clip = crate :: Reg < dcest1_clip :: Dcest1ClipSpec > ; # [doc = "DCEST1_CLIP"]
pub mod dcest1_clip { # [doc = "Register `DCEST1_CLIP` reader"]
pub type R = crate :: R < Dcest1ClipSpec > ; # [doc = "Register `DCEST1_CLIP` writer"]
pub type W = crate :: W < Dcest1ClipSpec > ; # [doc = "Field `DCEST1_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =0"]
pub type Dcest1ClipR = crate :: BitReader ; # [doc = "Field `DCEST1_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =0"]
pub type Dcest1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =0"]
# [inline (always)]
pub fn dcest1_clip (& self) -> Dcest1ClipR { Dcest1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn dcest1_clip (& mut self) -> Dcest1ClipW < Dcest1ClipSpec > { Dcest1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest1ClipSpec ; impl crate :: RegisterSpec for Dcest1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest1_clip::R`](R) reader structure"]
impl crate :: Readable for Dcest1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcest1_clip::W`](W) writer structure"]
impl crate :: Writable for Dcest1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST1_CLIP to value 0"]
impl crate :: Resettable for Dcest1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST2_CLIP (rw) register accessor: DCEST2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest2_clip`]
module"]
# [doc (alias = "DCEST2_CLIP")]
pub type Dcest2Clip = crate :: Reg < dcest2_clip :: Dcest2ClipSpec > ; # [doc = "DCEST2_CLIP"]
pub mod dcest2_clip { # [doc = "Register `DCEST2_CLIP` reader"]
pub type R = crate :: R < Dcest2ClipSpec > ; # [doc = "Register `DCEST2_CLIP` writer"]
pub type W = crate :: W < Dcest2ClipSpec > ; # [doc = "Field `DCEST2_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =1"]
pub type Dcest2ClipR = crate :: BitReader ; # [doc = "Field `DCEST2_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =1"]
pub type Dcest2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =1"]
# [inline (always)]
pub fn dcest2_clip (& self) -> Dcest2ClipR { Dcest2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn dcest2_clip (& mut self) -> Dcest2ClipW < Dcest2ClipSpec > { Dcest2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest2ClipSpec ; impl crate :: RegisterSpec for Dcest2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest2_clip::R`](R) reader structure"]
impl crate :: Readable for Dcest2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcest2_clip::W`](W) writer structure"]
impl crate :: Writable for Dcest2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST2_CLIP to value 0"]
impl crate :: Resettable for Dcest2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST3_CLIP (rw) register accessor: DCEST3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest3_clip`]
module"]
# [doc (alias = "DCEST3_CLIP")]
pub type Dcest3Clip = crate :: Reg < dcest3_clip :: Dcest3ClipSpec > ; # [doc = "DCEST3_CLIP"]
pub mod dcest3_clip { # [doc = "Register `DCEST3_CLIP` reader"]
pub type R = crate :: R < Dcest3ClipSpec > ; # [doc = "Register `DCEST3_CLIP` writer"]
pub type W = crate :: W < Dcest3ClipSpec > ; # [doc = "Field `DCEST3_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =2"]
pub type Dcest3ClipR = crate :: BitReader ; # [doc = "Field `DCEST3_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =2"]
pub type Dcest3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =2"]
# [inline (always)]
pub fn dcest3_clip (& self) -> Dcest3ClipR { Dcest3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn dcest3_clip (& mut self) -> Dcest3ClipW < Dcest3ClipSpec > { Dcest3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest3ClipSpec ; impl crate :: RegisterSpec for Dcest3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest3_clip::R`](R) reader structure"]
impl crate :: Readable for Dcest3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcest3_clip::W`](W) writer structure"]
impl crate :: Writable for Dcest3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST3_CLIP to value 0"]
impl crate :: Resettable for Dcest3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST4_CLIP (rw) register accessor: DCEST4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest4_clip`]
module"]
# [doc (alias = "DCEST4_CLIP")]
pub type Dcest4Clip = crate :: Reg < dcest4_clip :: Dcest4ClipSpec > ; # [doc = "DCEST4_CLIP"]
pub mod dcest4_clip { # [doc = "Register `DCEST4_CLIP` reader"]
pub type R = crate :: R < Dcest4ClipSpec > ; # [doc = "Register `DCEST4_CLIP` writer"]
pub type W = crate :: W < Dcest4ClipSpec > ; # [doc = "Field `DCEST4_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =3"]
pub type Dcest4ClipR = crate :: BitReader ; # [doc = "Field `DCEST4_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =3"]
pub type Dcest4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =3"]
# [inline (always)]
pub fn dcest4_clip (& self) -> Dcest4ClipR { Dcest4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn dcest4_clip (& mut self) -> Dcest4ClipW < Dcest4ClipSpec > { Dcest4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest4ClipSpec ; impl crate :: RegisterSpec for Dcest4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest4_clip::R`](R) reader structure"]
impl crate :: Readable for Dcest4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcest4_clip::W`](W) writer structure"]
impl crate :: Writable for Dcest4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST4_CLIP to value 0"]
impl crate :: Resettable for Dcest4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST5_CLIP (rw) register accessor: DCEST5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest5_clip`]
module"]
# [doc (alias = "DCEST5_CLIP")]
pub type Dcest5Clip = crate :: Reg < dcest5_clip :: Dcest5ClipSpec > ; # [doc = "DCEST5_CLIP"]
pub mod dcest5_clip { # [doc = "Register `DCEST5_CLIP` reader"]
pub type R = crate :: R < Dcest5ClipSpec > ; # [doc = "Register `DCEST5_CLIP` writer"]
pub type W = crate :: W < Dcest5ClipSpec > ; # [doc = "Field `DCEST5_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =4"]
pub type Dcest5ClipR = crate :: BitReader ; # [doc = "Field `DCEST5_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =4"]
pub type Dcest5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =4"]
# [inline (always)]
pub fn dcest5_clip (& self) -> Dcest5ClipR { Dcest5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn dcest5_clip (& mut self) -> Dcest5ClipW < Dcest5ClipSpec > { Dcest5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest5ClipSpec ; impl crate :: RegisterSpec for Dcest5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest5_clip::R`](R) reader structure"]
impl crate :: Readable for Dcest5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcest5_clip::W`](W) writer structure"]
impl crate :: Writable for Dcest5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST5_CLIP to value 0"]
impl crate :: Resettable for Dcest5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST6_CLIP (rw) register accessor: DCEST6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest6_clip`]
module"]
# [doc (alias = "DCEST6_CLIP")]
pub type Dcest6Clip = crate :: Reg < dcest6_clip :: Dcest6ClipSpec > ; # [doc = "DCEST6_CLIP"]
pub mod dcest6_clip { # [doc = "Register `DCEST6_CLIP` reader"]
pub type R = crate :: R < Dcest6ClipSpec > ; # [doc = "Register `DCEST6_CLIP` writer"]
pub type W = crate :: W < Dcest6ClipSpec > ; # [doc = "Field `DCEST6_CLIP` reader - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =5"]
pub type Dcest6ClipR = crate :: BitReader ; # [doc = "Field `DCEST6_CLIP` writer - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =5"]
pub type Dcest6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =5"]
# [inline (always)]
pub fn dcest6_clip (& self) -> Dcest6ClipR { Dcest6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This register contains the clip status of both I/Q DC estimates for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn dcest6_clip (& mut self) -> Dcest6ClipW < Dcest6ClipSpec > { Dcest6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcest6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcest6ClipSpec ; impl crate :: RegisterSpec for Dcest6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest6_clip::R`](R) reader structure"]
impl crate :: Readable for Dcest6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcest6_clip::W`](W) writer structure"]
impl crate :: Writable for Dcest6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST6_CLIP to value 0"]
impl crate :: Resettable for Dcest6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCSUB1_CLIP (rw) register accessor: DCSUB1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcsub1_clip`]
module"]
# [doc (alias = "DCSUB1_CLIP")]
pub type Dcsub1Clip = crate :: Reg < dcsub1_clip :: Dcsub1ClipSpec > ; # [doc = "DCSUB1_CLIP"]
pub mod dcsub1_clip { # [doc = "Register `DCSUB1_CLIP` reader"]
pub type R = crate :: R < Dcsub1ClipSpec > ; # [doc = "Register `DCSUB1_CLIP` writer"]
pub type W = crate :: W < Dcsub1ClipSpec > ; # [doc = "Field `DCSUB1_CLIP` reader - 0:0\\]
Indicates the DC subtraction clip status for bcnt =0"]
pub type Dcsub1ClipR = crate :: BitReader ; # [doc = "Field `DCSUB1_CLIP` writer - 0:0\\]
Indicates the DC subtraction clip status for bcnt =0"]
pub type Dcsub1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =0"]
# [inline (always)]
pub fn dcsub1_clip (& self) -> Dcsub1ClipR { Dcsub1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn dcsub1_clip (& mut self) -> Dcsub1ClipW < Dcsub1ClipSpec > { Dcsub1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcsub1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCSUB1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcsub1ClipSpec ; impl crate :: RegisterSpec for Dcsub1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcsub1_clip::R`](R) reader structure"]
impl crate :: Readable for Dcsub1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcsub1_clip::W`](W) writer structure"]
impl crate :: Writable for Dcsub1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCSUB1_CLIP to value 0"]
impl crate :: Resettable for Dcsub1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCSUB2_CLIP (rw) register accessor: DCSUB2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcsub2_clip`]
module"]
# [doc (alias = "DCSUB2_CLIP")]
pub type Dcsub2Clip = crate :: Reg < dcsub2_clip :: Dcsub2ClipSpec > ; # [doc = "DCSUB2_CLIP"]
pub mod dcsub2_clip { # [doc = "Register `DCSUB2_CLIP` reader"]
pub type R = crate :: R < Dcsub2ClipSpec > ; # [doc = "Register `DCSUB2_CLIP` writer"]
pub type W = crate :: W < Dcsub2ClipSpec > ; # [doc = "Field `DCSUB2_CLIP` reader - 0:0\\]
Indicates the DC subtraction clip status for bcnt =1"]
pub type Dcsub2ClipR = crate :: BitReader ; # [doc = "Field `DCSUB2_CLIP` writer - 0:0\\]
Indicates the DC subtraction clip status for bcnt =1"]
pub type Dcsub2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =1"]
# [inline (always)]
pub fn dcsub2_clip (& self) -> Dcsub2ClipR { Dcsub2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn dcsub2_clip (& mut self) -> Dcsub2ClipW < Dcsub2ClipSpec > { Dcsub2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcsub2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCSUB2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcsub2ClipSpec ; impl crate :: RegisterSpec for Dcsub2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcsub2_clip::R`](R) reader structure"]
impl crate :: Readable for Dcsub2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcsub2_clip::W`](W) writer structure"]
impl crate :: Writable for Dcsub2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCSUB2_CLIP to value 0"]
impl crate :: Resettable for Dcsub2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCSUB3_CLIP (rw) register accessor: DCSUB3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcsub3_clip`]
module"]
# [doc (alias = "DCSUB3_CLIP")]
pub type Dcsub3Clip = crate :: Reg < dcsub3_clip :: Dcsub3ClipSpec > ; # [doc = "DCSUB3_CLIP"]
pub mod dcsub3_clip { # [doc = "Register `DCSUB3_CLIP` reader"]
pub type R = crate :: R < Dcsub3ClipSpec > ; # [doc = "Register `DCSUB3_CLIP` writer"]
pub type W = crate :: W < Dcsub3ClipSpec > ; # [doc = "Field `DCSUB3_CLIP` reader - 0:0\\]
Indicates the DC subtraction clip status for bcnt =2"]
pub type Dcsub3ClipR = crate :: BitReader ; # [doc = "Field `DCSUB3_CLIP` writer - 0:0\\]
Indicates the DC subtraction clip status for bcnt =2"]
pub type Dcsub3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =2"]
# [inline (always)]
pub fn dcsub3_clip (& self) -> Dcsub3ClipR { Dcsub3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn dcsub3_clip (& mut self) -> Dcsub3ClipW < Dcsub3ClipSpec > { Dcsub3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcsub3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCSUB3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcsub3ClipSpec ; impl crate :: RegisterSpec for Dcsub3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcsub3_clip::R`](R) reader structure"]
impl crate :: Readable for Dcsub3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcsub3_clip::W`](W) writer structure"]
impl crate :: Writable for Dcsub3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCSUB3_CLIP to value 0"]
impl crate :: Resettable for Dcsub3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCSUB4_CLIP (rw) register accessor: DCSUB4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcsub4_clip`]
module"]
# [doc (alias = "DCSUB4_CLIP")]
pub type Dcsub4Clip = crate :: Reg < dcsub4_clip :: Dcsub4ClipSpec > ; # [doc = "DCSUB4_CLIP"]
pub mod dcsub4_clip { # [doc = "Register `DCSUB4_CLIP` reader"]
pub type R = crate :: R < Dcsub4ClipSpec > ; # [doc = "Register `DCSUB4_CLIP` writer"]
pub type W = crate :: W < Dcsub4ClipSpec > ; # [doc = "Field `DCSUB4_CLIP` reader - 0:0\\]
Indicates the DC subtraction clip status for bcnt =3"]
pub type Dcsub4ClipR = crate :: BitReader ; # [doc = "Field `DCSUB4_CLIP` writer - 0:0\\]
Indicates the DC subtraction clip status for bcnt =3"]
pub type Dcsub4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =3"]
# [inline (always)]
pub fn dcsub4_clip (& self) -> Dcsub4ClipR { Dcsub4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn dcsub4_clip (& mut self) -> Dcsub4ClipW < Dcsub4ClipSpec > { Dcsub4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcsub4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCSUB4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcsub4ClipSpec ; impl crate :: RegisterSpec for Dcsub4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcsub4_clip::R`](R) reader structure"]
impl crate :: Readable for Dcsub4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcsub4_clip::W`](W) writer structure"]
impl crate :: Writable for Dcsub4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCSUB4_CLIP to value 0"]
impl crate :: Resettable for Dcsub4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCSUB5_CLIP (rw) register accessor: DCSUB5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcsub5_clip`]
module"]
# [doc (alias = "DCSUB5_CLIP")]
pub type Dcsub5Clip = crate :: Reg < dcsub5_clip :: Dcsub5ClipSpec > ; # [doc = "DCSUB5_CLIP"]
pub mod dcsub5_clip { # [doc = "Register `DCSUB5_CLIP` reader"]
pub type R = crate :: R < Dcsub5ClipSpec > ; # [doc = "Register `DCSUB5_CLIP` writer"]
pub type W = crate :: W < Dcsub5ClipSpec > ; # [doc = "Field `DCSUB5_CLIP` reader - 0:0\\]
Indicates the DC subtraction clip status for bcnt =4"]
pub type Dcsub5ClipR = crate :: BitReader ; # [doc = "Field `DCSUB5_CLIP` writer - 0:0\\]
Indicates the DC subtraction clip status for bcnt =4"]
pub type Dcsub5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =4"]
# [inline (always)]
pub fn dcsub5_clip (& self) -> Dcsub5ClipR { Dcsub5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn dcsub5_clip (& mut self) -> Dcsub5ClipW < Dcsub5ClipSpec > { Dcsub5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcsub5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCSUB5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcsub5ClipSpec ; impl crate :: RegisterSpec for Dcsub5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcsub5_clip::R`](R) reader structure"]
impl crate :: Readable for Dcsub5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcsub5_clip::W`](W) writer structure"]
impl crate :: Writable for Dcsub5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCSUB5_CLIP to value 0"]
impl crate :: Resettable for Dcsub5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCSUB6_CLIP (rw) register accessor: DCSUB6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcsub6_clip`]
module"]
# [doc (alias = "DCSUB6_CLIP")]
pub type Dcsub6Clip = crate :: Reg < dcsub6_clip :: Dcsub6ClipSpec > ; # [doc = "DCSUB6_CLIP"]
pub mod dcsub6_clip { # [doc = "Register `DCSUB6_CLIP` reader"]
pub type R = crate :: R < Dcsub6ClipSpec > ; # [doc = "Register `DCSUB6_CLIP` writer"]
pub type W = crate :: W < Dcsub6ClipSpec > ; # [doc = "Field `DCSUB6_CLIP` reader - 0:0\\]
Indicates the DC subtraction clip status for bcnt =5"]
pub type Dcsub6ClipR = crate :: BitReader ; # [doc = "Field `DCSUB6_CLIP` writer - 0:0\\]
Indicates the DC subtraction clip status for bcnt =5"]
pub type Dcsub6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =5"]
# [inline (always)]
pub fn dcsub6_clip (& self) -> Dcsub6ClipR { Dcsub6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the DC subtraction clip status for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn dcsub6_clip (& mut self) -> Dcsub6ClipW < Dcsub6ClipSpec > { Dcsub6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Dcsub6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "DCSUB6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`dcsub6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcsub6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcsub6ClipSpec ; impl crate :: RegisterSpec for Dcsub6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcsub6_clip::R`](R) reader structure"]
impl crate :: Readable for Dcsub6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`dcsub6_clip::W`](W) writer structure"]
impl crate :: Writable for Dcsub6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCSUB6_CLIP to value 0"]
impl crate :: Resettable for Dcsub6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST_SHIFT (rw) register accessor: DCEST_SHIFT\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest_shift::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest_shift::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest_shift`]
module"]
# [doc (alias = "DCEST_SHIFT")]
pub type DcestShift = crate :: Reg < dcest_shift :: DcestShiftSpec > ; # [doc = "DCEST_SHIFT"]
pub mod dcest_shift { # [doc = "Register `DCEST_SHIFT` reader"]
pub type R = crate :: R < DcestShiftSpec > ; # [doc = "Register `DCEST_SHIFT` writer"]
pub type W = crate :: W < DcestShiftSpec > ; # [doc = "Field `DCEST_SHIFT` reader - 3:0\\]
Programmable shift applied to all 6 accumulator outputs. Cannot be bypassed. Scaled accumulator output is shifted by 2^( 2+DCEST_SHIFT). For DCEST_SHIFT = 15 also gives 2^(24) and not 25 (saturate at 24)"]
pub type DcestShiftR = crate :: FieldReader ; # [doc = "Field `DCEST_SHIFT` writer - 3:0\\]
Programmable shift applied to all 6 accumulator outputs. Cannot be bypassed. Scaled accumulator output is shifted by 2^( 2+DCEST_SHIFT). For DCEST_SHIFT = 15 also gives 2^(24) and not 25 (saturate at 24)"]
pub type DcestShiftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Programmable shift applied to all 6 accumulator outputs. Cannot be bypassed. Scaled accumulator output is shifted by 2^( 2+DCEST_SHIFT). For DCEST_SHIFT = 15 also gives 2^(24) and not 25 (saturate at 24)"]
# [inline (always)]
pub fn dcest_shift (& self) -> DcestShiftR { DcestShiftR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Programmable shift applied to all 6 accumulator outputs. Cannot be bypassed. Scaled accumulator output is shifted by 2^( 2+DCEST_SHIFT). For DCEST_SHIFT = 15 also gives 2^(24) and not 25 (saturate at 24)"]
# [inline (always)]
# [must_use]
pub fn dcest_shift (& mut self) -> DcestShiftW < DcestShiftSpec > { DcestShiftW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcestShiftSpec > { Nu1W :: new (self , 4) } } # [doc = "DCEST_SHIFT\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest_shift::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest_shift::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcestShiftSpec ; impl crate :: RegisterSpec for DcestShiftSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest_shift::R`](R) reader structure"]
impl crate :: Readable for DcestShiftSpec { } # [doc = "`write(|w| ..)` method takes [`dcest_shift::W`](W) writer structure"]
impl crate :: Writable for DcestShiftSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST_SHIFT to value 0"]
impl crate :: Resettable for DcestShiftSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST_SCALE (rw) register accessor: DCEST_SCALE\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest_scale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest_scale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest_scale`]
module"]
# [doc (alias = "DCEST_SCALE")]
pub type DcestScale = crate :: Reg < dcest_scale :: DcestScaleSpec > ; # [doc = "DCEST_SCALE"]
pub mod dcest_scale { # [doc = "Register `DCEST_SCALE` reader"]
pub type R = crate :: R < DcestScaleSpec > ; # [doc = "Register `DCEST_SCALE` writer"]
pub type W = crate :: W < DcestScaleSpec > ; # [doc = "Field `DCEST_SCALE` reader - 8:0\\]
9-bit scale applied to all 6 accumulators. Multiplies the accumulator output by DCEST_SCALE/256.This is followed by right shift and truncation.Default value is 256 giving a scale of 1.0. Setting it to 128, gives a scale of 0.5"]
pub type DcestScaleR = crate :: FieldReader < u16 > ; # [doc = "Field `DCEST_SCALE` writer - 8:0\\]
9-bit scale applied to all 6 accumulators. Multiplies the accumulator output by DCEST_SCALE/256.This is followed by right shift and truncation.Default value is 256 giving a scale of 1.0. Setting it to 128, gives a scale of 0.5"]
pub type DcestScaleW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:8 - 8:0\\]
9-bit scale applied to all 6 accumulators. Multiplies the accumulator output by DCEST_SCALE/256.This is followed by right shift and truncation.Default value is 256 giving a scale of 1.0. Setting it to 128, gives a scale of 0.5"]
# [inline (always)]
pub fn dcest_scale (& self) -> DcestScaleR { DcestScaleR :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bits 9:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 9) & 0x007f_ffff) } } impl W { # [doc = "Bits 0:8 - 8:0\\]
9-bit scale applied to all 6 accumulators. Multiplies the accumulator output by DCEST_SCALE/256.This is followed by right shift and truncation.Default value is 256 giving a scale of 1.0. Setting it to 128, gives a scale of 0.5"]
# [inline (always)]
# [must_use]
pub fn dcest_scale (& mut self) -> DcestScaleW < DcestScaleSpec > { DcestScaleW :: new (self , 0) } # [doc = "Bits 9:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcestScaleSpec > { Nu1W :: new (self , 9) } } # [doc = "DCEST_SCALE\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest_scale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest_scale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcestScaleSpec ; impl crate :: RegisterSpec for DcestScaleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest_scale::R`](R) reader structure"]
impl crate :: Readable for DcestScaleSpec { } # [doc = "`write(|w| ..)` method takes [`dcest_scale::W`](W) writer structure"]
impl crate :: Writable for DcestScaleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST_SCALE to value 0"]
impl crate :: Resettable for DcestScaleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAG_SCALE (rw) register accessor: INTF_MAG_SCALE\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_mag_scale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_mag_scale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_mag_scale`]
module"]
# [doc (alias = "INTF_MAG_SCALE")]
pub type IntfMagScale = crate :: Reg < intf_mag_scale :: IntfMagScaleSpec > ; # [doc = "INTF_MAG_SCALE"]
pub mod intf_mag_scale { # [doc = "Register `INTF_MAG_SCALE` reader"]
pub type R = crate :: R < IntfMagScaleSpec > ; # [doc = "Register `INTF_MAG_SCALE` writer"]
pub type W = crate :: W < IntfMagScaleSpec > ; # [doc = "Field `INTF_MAG_SCALE` reader - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block.Default 8= scale of 1.0"]
pub type IntfMagScaleR = crate :: FieldReader ; # [doc = "Field `INTF_MAG_SCALE` writer - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block.Default 8= scale of 1.0"]
pub type IntfMagScaleW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block.Default 8= scale of 1.0"]
# [inline (always)]
pub fn intf_mag_scale (& self) -> IntfMagScaleR { IntfMagScaleR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block.Default 8= scale of 1.0"]
# [inline (always)]
# [must_use]
pub fn intf_mag_scale (& mut self) -> IntfMagScaleW < IntfMagScaleSpec > { IntfMagScaleW :: new (self , 0) } # [doc = "Bits 8:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagScaleSpec > { Nu1W :: new (self , 8) } } # [doc = "INTF_MAG_SCALE\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_mag_scale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_mag_scale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagScaleSpec ; impl crate :: RegisterSpec for IntfMagScaleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_mag_scale::R`](R) reader structure"]
impl crate :: Readable for IntfMagScaleSpec { } # [doc = "`write(|w| ..)` method takes [`intf_mag_scale::W`](W) writer structure"]
impl crate :: Writable for IntfMagScaleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAG_SCALE to value 0"]
impl crate :: Resettable for IntfMagScaleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAG_SHIFT (rw) register accessor: INTF_MAG_SHIFT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_mag_shift::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_mag_shift::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_mag_shift`]
module"]
# [doc (alias = "INTF_MAG_SHIFT")]
pub type IntfMagShift = crate :: Reg < intf_mag_shift :: IntfMagShiftSpec > ; # [doc = "INTF_MAG_SHIFT"]
pub mod intf_mag_shift { # [doc = "Register `INTF_MAG_SHIFT` reader"]
pub type R = crate :: R < IntfMagShiftSpec > ; # [doc = "Register `INTF_MAG_SHIFT` writer"]
pub type W = crate :: W < IntfMagShiftSpec > ; # [doc = "Field `INTF_MAG_SHIFT` reader - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAG_SHIFT). Can t be more than 2^(17)."]
pub type IntfMagShiftR = crate :: FieldReader ; # [doc = "Field `INTF_MAG_SHIFT` writer - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAG_SHIFT). Can t be more than 2^(17)."]
pub type IntfMagShiftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAG_SHIFT). Can t be more than 2^(17)."]
# [inline (always)]
pub fn intf_mag_shift (& self) -> IntfMagShiftR { IntfMagShiftR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAG_SHIFT). Can t be more than 2^(17)."]
# [inline (always)]
# [must_use]
pub fn intf_mag_shift (& mut self) -> IntfMagShiftW < IntfMagShiftSpec > { IntfMagShiftW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagShiftSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAG_SHIFT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_mag_shift::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_mag_shift::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagShiftSpec ; impl crate :: RegisterSpec for IntfMagShiftSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_mag_shift::R`](R) reader structure"]
impl crate :: Readable for IntfMagShiftSpec { } # [doc = "`write(|w| ..)` method takes [`intf_mag_shift::W`](W) writer structure"]
impl crate :: Writable for IntfMagShiftSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAG_SHIFT to value 0"]
impl crate :: Resettable for IntfMagShiftSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFF_SCALE (rw) register accessor: INTF_MAGDIFF_SCALE\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiff_scale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiff_scale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiff_scale`]
module"]
# [doc (alias = "INTF_MAGDIFF_SCALE")]
pub type IntfMagdiffScale = crate :: Reg < intf_magdiff_scale :: IntfMagdiffScaleSpec > ; # [doc = "INTF_MAGDIFF_SCALE"]
pub mod intf_magdiff_scale { # [doc = "Register `INTF_MAGDIFF_SCALE` reader"]
pub type R = crate :: R < IntfMagdiffScaleSpec > ; # [doc = "Register `INTF_MAGDIFF_SCALE` writer"]
pub type W = crate :: W < IntfMagdiffScaleSpec > ; # [doc = "Field `INTF_MAGDIFF_SCALE` reader - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block.Default 8= scale of 1.0"]
pub type IntfMagdiffScaleR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFF_SCALE` writer - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block.Default 8= scale of 1.0"]
pub type IntfMagdiffScaleW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block.Default 8= scale of 1.0"]
# [inline (always)]
pub fn intf_magdiff_scale (& self) -> IntfMagdiffScaleR { IntfMagdiffScaleR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block.Default 8= scale of 1.0"]
# [inline (always)]
# [must_use]
pub fn intf_magdiff_scale (& mut self) -> IntfMagdiffScaleW < IntfMagdiffScaleSpec > { IntfMagdiffScaleW :: new (self , 0) } # [doc = "Bits 8:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffScaleSpec > { Nu1W :: new (self , 8) } } # [doc = "INTF_MAGDIFF_SCALE\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiff_scale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiff_scale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffScaleSpec ; impl crate :: RegisterSpec for IntfMagdiffScaleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiff_scale::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffScaleSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiff_scale::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffScaleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFF_SCALE to value 0"]
impl crate :: Resettable for IntfMagdiffScaleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFF_SHIFT (rw) register accessor: INTF_MAGDIFF_SHIFT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiff_shift::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiff_shift::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiff_shift`]
module"]
# [doc (alias = "INTF_MAGDIFF_SHIFT")]
pub type IntfMagdiffShift = crate :: Reg < intf_magdiff_shift :: IntfMagdiffShiftSpec > ; # [doc = "INTF_MAGDIFF_SHIFT"]
pub mod intf_magdiff_shift { # [doc = "Register `INTF_MAGDIFF_SHIFT` reader"]
pub type R = crate :: R < IntfMagdiffShiftSpec > ; # [doc = "Register `INTF_MAGDIFF_SHIFT` writer"]
pub type W = crate :: W < IntfMagdiffShiftSpec > ; # [doc = "Field `INTF_MAGDIFF_SHIFT` reader - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAGDIFF_SHIFT). Can t be more than 2^(17)."]
pub type IntfMagdiffShiftR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFF_SHIFT` writer - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAGDIFF_SHIFT). Can t be more than 2^(17)."]
pub type IntfMagdiffShiftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAGDIFF_SHIFT). Can t be more than 2^(17)."]
# [inline (always)]
pub fn intf_magdiff_shift (& self) -> IntfMagdiffShiftR { IntfMagdiffShiftR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Right shift applied after scaling ΓÇô 2^(4+INTERFSUM_MAGDIFF_SHIFT). Can t be more than 2^(17)."]
# [inline (always)]
# [must_use]
pub fn intf_magdiff_shift (& mut self) -> IntfMagdiffShiftW < IntfMagdiffShiftSpec > { IntfMagdiffShiftW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffShiftSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFF_SHIFT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiff_shift::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiff_shift::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffShiftSpec ; impl crate :: RegisterSpec for IntfMagdiffShiftSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiff_shift::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffShiftSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiff_shift::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffShiftSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFF_SHIFT to value 0"]
impl crate :: Resettable for IntfMagdiffShiftSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_FRAME_ZEROCOUNT (rw) register accessor: INTF_FRAME_ZEROCOUNT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_frame_zerocount::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_frame_zerocount::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_frame_zerocount`]
module"]
# [doc (alias = "INTF_FRAME_ZEROCOUNT")]
pub type IntfFrameZerocount = crate :: Reg < intf_frame_zerocount :: IntfFrameZerocountSpec > ; # [doc = "INTF_FRAME_ZEROCOUNT"]
pub mod intf_frame_zerocount { # [doc = "Register `INTF_FRAME_ZEROCOUNT` reader"]
pub type R = crate :: R < IntfFrameZerocountSpec > ; # [doc = "Register `INTF_FRAME_ZEROCOUNT` writer"]
pub type W = crate :: W < IntfFrameZerocountSpec > ; # [doc = "Field `INTF_FRAME_ZEROCOUNT` reader - 19:0\\]
Number of samples that exceeded the threshold in a frame"]
pub type IntfFrameZerocountR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_FRAME_ZEROCOUNT` writer - 19:0\\]
Number of samples that exceeded the threshold in a frame"]
pub type IntfFrameZerocountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
Number of samples that exceeded the threshold in a frame"]
# [inline (always)]
pub fn intf_frame_zerocount (& self) -> IntfFrameZerocountR { IntfFrameZerocountR :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
Number of samples that exceeded the threshold in a frame"]
# [inline (always)]
# [must_use]
pub fn intf_frame_zerocount (& mut self) -> IntfFrameZerocountW < IntfFrameZerocountSpec > { IntfFrameZerocountW :: new (self , 0) } # [doc = "Bits 20:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfFrameZerocountSpec > { Nu1W :: new (self , 20) } } # [doc = "INTF_FRAME_ZEROCOUNT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_frame_zerocount::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_frame_zerocount::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfFrameZerocountSpec ; impl crate :: RegisterSpec for IntfFrameZerocountSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_frame_zerocount::R`](R) reader structure"]
impl crate :: Readable for IntfFrameZerocountSpec { } # [doc = "`write(|w| ..)` method takes [`intf_frame_zerocount::W`](W) writer structure"]
impl crate :: Writable for IntfFrameZerocountSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_FRAME_ZEROCOUNT to value 0"]
impl crate :: Resettable for IntfFrameZerocountSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_CHIRP_ZEROCOUNT (rw) register accessor: INTF_CHIRP_ZEROCOUNT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_chirp_zerocount::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_chirp_zerocount::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_chirp_zerocount`]
module"]
# [doc (alias = "INTF_CHIRP_ZEROCOUNT")]
pub type IntfChirpZerocount = crate :: Reg < intf_chirp_zerocount :: IntfChirpZerocountSpec > ; # [doc = "INTF_CHIRP_ZEROCOUNT"]
pub mod intf_chirp_zerocount { # [doc = "Register `INTF_CHIRP_ZEROCOUNT` reader"]
pub type R = crate :: R < IntfChirpZerocountSpec > ; # [doc = "Register `INTF_CHIRP_ZEROCOUNT` writer"]
pub type W = crate :: W < IntfChirpZerocountSpec > ; # [doc = "Field `INTF_CHIRP_ZEROCOUNT` reader - 11:0\\]
Number of samples that exceeded the threshold in a chirp"]
pub type IntfChirpZerocountR = crate :: FieldReader < u16 > ; # [doc = "Field `INTF_CHIRP_ZEROCOUNT` writer - 11:0\\]
Number of samples that exceeded the threshold in a chirp"]
pub type IntfChirpZerocountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Number of samples that exceeded the threshold in a chirp"]
# [inline (always)]
pub fn intf_chirp_zerocount (& self) -> IntfChirpZerocountR { IntfChirpZerocountR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Number of samples that exceeded the threshold in a chirp"]
# [inline (always)]
# [must_use]
pub fn intf_chirp_zerocount (& mut self) -> IntfChirpZerocountW < IntfChirpZerocountSpec > { IntfChirpZerocountW :: new (self , 0) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfChirpZerocountSpec > { Nu1W :: new (self , 12) } } # [doc = "INTF_CHIRP_ZEROCOUNT\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_chirp_zerocount::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_chirp_zerocount::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfChirpZerocountSpec ; impl crate :: RegisterSpec for IntfChirpZerocountSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_chirp_zerocount::R`](R) reader structure"]
impl crate :: Readable for IntfChirpZerocountSpec { } # [doc = "`write(|w| ..)` method takes [`intf_chirp_zerocount::W`](W) writer structure"]
impl crate :: Writable for IntfChirpZerocountSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_CHIRP_ZEROCOUNT to value 0"]
impl crate :: Resettable for IntfChirpZerocountSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH1_SW (rw) register accessor: INTF_MAGTHRESH1_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh1_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh1_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh1_sw`]
module"]
# [doc (alias = "INTF_MAGTHRESH1_SW")]
pub type IntfMagthresh1Sw = crate :: Reg < intf_magthresh1_sw :: IntfMagthresh1SwSpec > ; # [doc = "INTF_MAGTHRESH1_SW"]
pub mod intf_magthresh1_sw { # [doc = "Register `INTF_MAGTHRESH1_SW` reader"]
pub type R = crate :: R < IntfMagthresh1SwSpec > ; # [doc = "Register `INTF_MAGTHRESH1_SW` writer"]
pub type W = crate :: W < IntfMagthresh1SwSpec > ; # [doc = "Field `INTF_MAGTHRESH1_SW` reader - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =0"]
pub type IntfMagthresh1SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH1_SW` writer - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =0"]
pub type IntfMagthresh1SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =0"]
# [inline (always)]
pub fn intf_magthresh1_sw (& self) -> IntfMagthresh1SwR { IntfMagthresh1SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh1_sw (& mut self) -> IntfMagthresh1SwW < IntfMagthresh1SwSpec > { IntfMagthresh1SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh1SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH1_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh1_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh1_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh1SwSpec ; impl crate :: RegisterSpec for IntfMagthresh1SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh1_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh1SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh1_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh1SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH1_SW to value 0"]
impl crate :: Resettable for IntfMagthresh1SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH2_SW (rw) register accessor: INTF_MAGTHRESH2_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh2_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh2_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh2_sw`]
module"]
# [doc (alias = "INTF_MAGTHRESH2_SW")]
pub type IntfMagthresh2Sw = crate :: Reg < intf_magthresh2_sw :: IntfMagthresh2SwSpec > ; # [doc = "INTF_MAGTHRESH2_SW"]
pub mod intf_magthresh2_sw { # [doc = "Register `INTF_MAGTHRESH2_SW` reader"]
pub type R = crate :: R < IntfMagthresh2SwSpec > ; # [doc = "Register `INTF_MAGTHRESH2_SW` writer"]
pub type W = crate :: W < IntfMagthresh2SwSpec > ; # [doc = "Field `INTF_MAGTHRESH2_SW` reader - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =1"]
pub type IntfMagthresh2SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH2_SW` writer - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =1"]
pub type IntfMagthresh2SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =1"]
# [inline (always)]
pub fn intf_magthresh2_sw (& self) -> IntfMagthresh2SwR { IntfMagthresh2SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh2_sw (& mut self) -> IntfMagthresh2SwW < IntfMagthresh2SwSpec > { IntfMagthresh2SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh2SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH2_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh2_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh2_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh2SwSpec ; impl crate :: RegisterSpec for IntfMagthresh2SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh2_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh2SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh2_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh2SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH2_SW to value 0"]
impl crate :: Resettable for IntfMagthresh2SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH3_SW (rw) register accessor: INTF_MAGTHRESH3_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh3_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh3_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh3_sw`]
module"]
# [doc (alias = "INTF_MAGTHRESH3_SW")]
pub type IntfMagthresh3Sw = crate :: Reg < intf_magthresh3_sw :: IntfMagthresh3SwSpec > ; # [doc = "INTF_MAGTHRESH3_SW"]
pub mod intf_magthresh3_sw { # [doc = "Register `INTF_MAGTHRESH3_SW` reader"]
pub type R = crate :: R < IntfMagthresh3SwSpec > ; # [doc = "Register `INTF_MAGTHRESH3_SW` writer"]
pub type W = crate :: W < IntfMagthresh3SwSpec > ; # [doc = "Field `INTF_MAGTHRESH3_SW` reader - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =2"]
pub type IntfMagthresh3SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH3_SW` writer - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =2"]
pub type IntfMagthresh3SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =2"]
# [inline (always)]
pub fn intf_magthresh3_sw (& self) -> IntfMagthresh3SwR { IntfMagthresh3SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh3_sw (& mut self) -> IntfMagthresh3SwW < IntfMagthresh3SwSpec > { IntfMagthresh3SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh3SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH3_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh3_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh3_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh3SwSpec ; impl crate :: RegisterSpec for IntfMagthresh3SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh3_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh3SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh3_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh3SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH3_SW to value 0"]
impl crate :: Resettable for IntfMagthresh3SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH4_SW (rw) register accessor: INTF_MAGTHRESH4_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh4_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh4_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh4_sw`]
module"]
# [doc (alias = "INTF_MAGTHRESH4_SW")]
pub type IntfMagthresh4Sw = crate :: Reg < intf_magthresh4_sw :: IntfMagthresh4SwSpec > ; # [doc = "INTF_MAGTHRESH4_SW"]
pub mod intf_magthresh4_sw { # [doc = "Register `INTF_MAGTHRESH4_SW` reader"]
pub type R = crate :: R < IntfMagthresh4SwSpec > ; # [doc = "Register `INTF_MAGTHRESH4_SW` writer"]
pub type W = crate :: W < IntfMagthresh4SwSpec > ; # [doc = "Field `INTF_MAGTHRESH4_SW` reader - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =3"]
pub type IntfMagthresh4SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH4_SW` writer - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =3"]
pub type IntfMagthresh4SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =3"]
# [inline (always)]
pub fn intf_magthresh4_sw (& self) -> IntfMagthresh4SwR { IntfMagthresh4SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh4_sw (& mut self) -> IntfMagthresh4SwW < IntfMagthresh4SwSpec > { IntfMagthresh4SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh4SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH4_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh4_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh4_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh4SwSpec ; impl crate :: RegisterSpec for IntfMagthresh4SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh4_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh4SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh4_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh4SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH4_SW to value 0"]
impl crate :: Resettable for IntfMagthresh4SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH5_SW (rw) register accessor: INTF_MAGTHRESH5_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh5_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh5_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh5_sw`]
module"]
# [doc (alias = "INTF_MAGTHRESH5_SW")]
pub type IntfMagthresh5Sw = crate :: Reg < intf_magthresh5_sw :: IntfMagthresh5SwSpec > ; # [doc = "INTF_MAGTHRESH5_SW"]
pub mod intf_magthresh5_sw { # [doc = "Register `INTF_MAGTHRESH5_SW` reader"]
pub type R = crate :: R < IntfMagthresh5SwSpec > ; # [doc = "Register `INTF_MAGTHRESH5_SW` writer"]
pub type W = crate :: W < IntfMagthresh5SwSpec > ; # [doc = "Field `INTF_MAGTHRESH5_SW` reader - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =4"]
pub type IntfMagthresh5SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH5_SW` writer - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =4"]
pub type IntfMagthresh5SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =4"]
# [inline (always)]
pub fn intf_magthresh5_sw (& self) -> IntfMagthresh5SwR { IntfMagthresh5SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh5_sw (& mut self) -> IntfMagthresh5SwW < IntfMagthresh5SwSpec > { IntfMagthresh5SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh5SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH5_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh5_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh5_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh5SwSpec ; impl crate :: RegisterSpec for IntfMagthresh5SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh5_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh5SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh5_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh5SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH5_SW to value 0"]
impl crate :: Resettable for IntfMagthresh5SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH6_SW (rw) register accessor: INTF_MAGTHRESH6_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh6_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh6_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh6_sw`]
module"]
# [doc (alias = "INTF_MAGTHRESH6_SW")]
pub type IntfMagthresh6Sw = crate :: Reg < intf_magthresh6_sw :: IntfMagthresh6SwSpec > ; # [doc = "INTF_MAGTHRESH6_SW"]
pub mod intf_magthresh6_sw { # [doc = "Register `INTF_MAGTHRESH6_SW` reader"]
pub type R = crate :: R < IntfMagthresh6SwSpec > ; # [doc = "Register `INTF_MAGTHRESH6_SW` writer"]
pub type W = crate :: W < IntfMagthresh6SwSpec > ; # [doc = "Field `INTF_MAGTHRESH6_SW` reader - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =5"]
pub type IntfMagthresh6SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH6_SW` writer - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =5"]
pub type IntfMagthresh6SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =5"]
# [inline (always)]
pub fn intf_magthresh6_sw (& self) -> IntfMagthresh6SwR { IntfMagthresh6SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude threshold value for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh6_sw (& mut self) -> IntfMagthresh6SwW < IntfMagthresh6SwSpec > { IntfMagthresh6SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh6SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH6_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh6_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh6_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh6SwSpec ; impl crate :: RegisterSpec for IntfMagthresh6SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh6_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh6SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh6_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh6SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH6_SW to value 0"]
impl crate :: Resettable for IntfMagthresh6SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH1_SW (rw) register accessor: INTF_MAGDIFFTHRESH1_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh1_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh1_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh1_sw`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH1_SW")]
pub type IntfMagdiffthresh1Sw = crate :: Reg < intf_magdiffthresh1_sw :: IntfMagdiffthresh1SwSpec > ; # [doc = "INTF_MAGDIFFTHRESH1_SW"]
pub mod intf_magdiffthresh1_sw { # [doc = "Register `INTF_MAGDIFFTHRESH1_SW` reader"]
pub type R = crate :: R < IntfMagdiffthresh1SwSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH1_SW` writer"]
pub type W = crate :: W < IntfMagdiffthresh1SwSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH1_SW` reader - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =0"]
pub type IntfMagdiffthresh1SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH1_SW` writer - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =0"]
pub type IntfMagdiffthresh1SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =0"]
# [inline (always)]
pub fn intf_magdiffthresh1_sw (& self) -> IntfMagdiffthresh1SwR { IntfMagdiffthresh1SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh1_sw (& mut self) -> IntfMagdiffthresh1SwW < IntfMagdiffthresh1SwSpec > { IntfMagdiffthresh1SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh1SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH1_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh1_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh1_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh1SwSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh1SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh1_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh1SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh1_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh1SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH1_SW to value 0"]
impl crate :: Resettable for IntfMagdiffthresh1SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH2_SW (rw) register accessor: INTF_MAGDIFFTHRESH2_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh2_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh2_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh2_sw`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH2_SW")]
pub type IntfMagdiffthresh2Sw = crate :: Reg < intf_magdiffthresh2_sw :: IntfMagdiffthresh2SwSpec > ; # [doc = "INTF_MAGDIFFTHRESH2_SW"]
pub mod intf_magdiffthresh2_sw { # [doc = "Register `INTF_MAGDIFFTHRESH2_SW` reader"]
pub type R = crate :: R < IntfMagdiffthresh2SwSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH2_SW` writer"]
pub type W = crate :: W < IntfMagdiffthresh2SwSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH2_SW` reader - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =1"]
pub type IntfMagdiffthresh2SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH2_SW` writer - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =1"]
pub type IntfMagdiffthresh2SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =1"]
# [inline (always)]
pub fn intf_magdiffthresh2_sw (& self) -> IntfMagdiffthresh2SwR { IntfMagdiffthresh2SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh2_sw (& mut self) -> IntfMagdiffthresh2SwW < IntfMagdiffthresh2SwSpec > { IntfMagdiffthresh2SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh2SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH2_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh2_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh2_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh2SwSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh2SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh2_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh2SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh2_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh2SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH2_SW to value 0"]
impl crate :: Resettable for IntfMagdiffthresh2SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH3_SW (rw) register accessor: INTF_MAGDIFFTHRESH3_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh3_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh3_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh3_sw`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH3_SW")]
pub type IntfMagdiffthresh3Sw = crate :: Reg < intf_magdiffthresh3_sw :: IntfMagdiffthresh3SwSpec > ; # [doc = "INTF_MAGDIFFTHRESH3_SW"]
pub mod intf_magdiffthresh3_sw { # [doc = "Register `INTF_MAGDIFFTHRESH3_SW` reader"]
pub type R = crate :: R < IntfMagdiffthresh3SwSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH3_SW` writer"]
pub type W = crate :: W < IntfMagdiffthresh3SwSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH3_SW` reader - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =2"]
pub type IntfMagdiffthresh3SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH3_SW` writer - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =2"]
pub type IntfMagdiffthresh3SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =2"]
# [inline (always)]
pub fn intf_magdiffthresh3_sw (& self) -> IntfMagdiffthresh3SwR { IntfMagdiffthresh3SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh3_sw (& mut self) -> IntfMagdiffthresh3SwW < IntfMagdiffthresh3SwSpec > { IntfMagdiffthresh3SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh3SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH3_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh3_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh3_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh3SwSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh3SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh3_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh3SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh3_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh3SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH3_SW to value 0"]
impl crate :: Resettable for IntfMagdiffthresh3SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH4_SW (rw) register accessor: INTF_MAGDIFFTHRESH4_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh4_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh4_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh4_sw`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH4_SW")]
pub type IntfMagdiffthresh4Sw = crate :: Reg < intf_magdiffthresh4_sw :: IntfMagdiffthresh4SwSpec > ; # [doc = "INTF_MAGDIFFTHRESH4_SW"]
pub mod intf_magdiffthresh4_sw { # [doc = "Register `INTF_MAGDIFFTHRESH4_SW` reader"]
pub type R = crate :: R < IntfMagdiffthresh4SwSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH4_SW` writer"]
pub type W = crate :: W < IntfMagdiffthresh4SwSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH4_SW` reader - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =3"]
pub type IntfMagdiffthresh4SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH4_SW` writer - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =3"]
pub type IntfMagdiffthresh4SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =3"]
# [inline (always)]
pub fn intf_magdiffthresh4_sw (& self) -> IntfMagdiffthresh4SwR { IntfMagdiffthresh4SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh4_sw (& mut self) -> IntfMagdiffthresh4SwW < IntfMagdiffthresh4SwSpec > { IntfMagdiffthresh4SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh4SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH4_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh4_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh4_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh4SwSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh4SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh4_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh4SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh4_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh4SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH4_SW to value 0"]
impl crate :: Resettable for IntfMagdiffthresh4SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH5_SW (rw) register accessor: INTF_MAGDIFFTHRESH5_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh5_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh5_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh5_sw`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH5_SW")]
pub type IntfMagdiffthresh5Sw = crate :: Reg < intf_magdiffthresh5_sw :: IntfMagdiffthresh5SwSpec > ; # [doc = "INTF_MAGDIFFTHRESH5_SW"]
pub mod intf_magdiffthresh5_sw { # [doc = "Register `INTF_MAGDIFFTHRESH5_SW` reader"]
pub type R = crate :: R < IntfMagdiffthresh5SwSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH5_SW` writer"]
pub type W = crate :: W < IntfMagdiffthresh5SwSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH5_SW` reader - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =4"]
pub type IntfMagdiffthresh5SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH5_SW` writer - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =4"]
pub type IntfMagdiffthresh5SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =4"]
# [inline (always)]
pub fn intf_magdiffthresh5_sw (& self) -> IntfMagdiffthresh5SwR { IntfMagdiffthresh5SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh5_sw (& mut self) -> IntfMagdiffthresh5SwW < IntfMagdiffthresh5SwSpec > { IntfMagdiffthresh5SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh5SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH5_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh5_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh5_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh5SwSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh5SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh5_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh5SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh5_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh5SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH5_SW to value 0"]
impl crate :: Resettable for IntfMagdiffthresh5SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH6_SW (rw) register accessor: INTF_MAGDIFFTHRESH6_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh6_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh6_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh6_sw`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH6_SW")]
pub type IntfMagdiffthresh6Sw = crate :: Reg < intf_magdiffthresh6_sw :: IntfMagdiffthresh6SwSpec > ; # [doc = "INTF_MAGDIFFTHRESH6_SW"]
pub mod intf_magdiffthresh6_sw { # [doc = "Register `INTF_MAGDIFFTHRESH6_SW` reader"]
pub type R = crate :: R < IntfMagdiffthresh6SwSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH6_SW` writer"]
pub type W = crate :: W < IntfMagdiffthresh6SwSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH6_SW` reader - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =5"]
pub type IntfMagdiffthresh6SwR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH6_SW` writer - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =5"]
pub type IntfMagdiffthresh6SwW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =5"]
# [inline (always)]
pub fn intf_magdiffthresh6_sw (& self) -> IntfMagdiffthresh6SwR { IntfMagdiffthresh6SwR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
This register provides software programmed interference magnitude difference threshold value for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh6_sw (& mut self) -> IntfMagdiffthresh6SwW < IntfMagdiffthresh6SwSpec > { IntfMagdiffthresh6SwW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh6SwSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH6_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh6_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh6_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh6SwSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh6SwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh6_sw::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh6SwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh6_sw::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh6SwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH6_SW to value 0"]
impl crate :: Resettable for IntfMagdiffthresh6SwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC1_LSB (rw) register accessor: INTF_MAGACC1_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc1_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc1_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc1_lsb`]
module"]
# [doc (alias = "INTF_MAGACC1_LSB")]
pub type IntfMagacc1Lsb = crate :: Reg < intf_magacc1_lsb :: IntfMagacc1LsbSpec > ; # [doc = "INTF_MAGACC1_LSB"]
pub mod intf_magacc1_lsb { # [doc = "Register `INTF_MAGACC1_LSB` reader"]
pub type R = crate :: R < IntfMagacc1LsbSpec > ; # [doc = "Register `INTF_MAGACC1_LSB` writer"]
pub type W = crate :: W < IntfMagacc1LsbSpec > ; # [doc = "Field `INTF_MAGACC1_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 0"]
pub type IntfMagacc1LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGACC1_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 0"]
pub type IntfMagacc1LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 0"]
# [inline (always)]
pub fn intf_magacc1_lsb (& self) -> IntfMagacc1LsbR { IntfMagacc1LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 0"]
# [inline (always)]
# [must_use]
pub fn intf_magacc1_lsb (& mut self) -> IntfMagacc1LsbW < IntfMagacc1LsbSpec > { IntfMagacc1LsbW :: new (self , 0) } } # [doc = "INTF_MAGACC1_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc1_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc1_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc1LsbSpec ; impl crate :: RegisterSpec for IntfMagacc1LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc1_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc1LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc1_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc1LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC1_LSB to value 0"]
impl crate :: Resettable for IntfMagacc1LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC1_MSB (rw) register accessor: INTF_MAGACC1_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc1_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc1_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc1_msb`]
module"]
# [doc (alias = "INTF_MAGACC1_MSB")]
pub type IntfMagacc1Msb = crate :: Reg < intf_magacc1_msb :: IntfMagacc1MsbSpec > ; # [doc = "INTF_MAGACC1_MSB"]
pub mod intf_magacc1_msb { # [doc = "Register `INTF_MAGACC1_MSB` reader"]
pub type R = crate :: R < IntfMagacc1MsbSpec > ; # [doc = "Register `INTF_MAGACC1_MSB` writer"]
pub type W = crate :: W < IntfMagacc1MsbSpec > ; # [doc = "Field `INTF_MAGACC1_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 0"]
pub type IntfMagacc1MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGACC1_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 0"]
pub type IntfMagacc1MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 0"]
# [inline (always)]
pub fn intf_magacc1_msb (& self) -> IntfMagacc1MsbR { IntfMagacc1MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 0"]
# [inline (always)]
# [must_use]
pub fn intf_magacc1_msb (& mut self) -> IntfMagacc1MsbW < IntfMagacc1MsbSpec > { IntfMagacc1MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc1MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGACC1_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc1_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc1_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc1MsbSpec ; impl crate :: RegisterSpec for IntfMagacc1MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc1_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc1MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc1_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc1MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC1_MSB to value 0"]
impl crate :: Resettable for IntfMagacc1MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC2_LSB (rw) register accessor: INTF_MAGACC2_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc2_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc2_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc2_lsb`]
module"]
# [doc (alias = "INTF_MAGACC2_LSB")]
pub type IntfMagacc2Lsb = crate :: Reg < intf_magacc2_lsb :: IntfMagacc2LsbSpec > ; # [doc = "INTF_MAGACC2_LSB"]
pub mod intf_magacc2_lsb { # [doc = "Register `INTF_MAGACC2_LSB` reader"]
pub type R = crate :: R < IntfMagacc2LsbSpec > ; # [doc = "Register `INTF_MAGACC2_LSB` writer"]
pub type W = crate :: W < IntfMagacc2LsbSpec > ; # [doc = "Field `INTF_MAGACC2_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 1"]
pub type IntfMagacc2LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGACC2_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 1"]
pub type IntfMagacc2LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 1"]
# [inline (always)]
pub fn intf_magacc2_lsb (& self) -> IntfMagacc2LsbR { IntfMagacc2LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 1"]
# [inline (always)]
# [must_use]
pub fn intf_magacc2_lsb (& mut self) -> IntfMagacc2LsbW < IntfMagacc2LsbSpec > { IntfMagacc2LsbW :: new (self , 0) } } # [doc = "INTF_MAGACC2_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc2_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc2_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc2LsbSpec ; impl crate :: RegisterSpec for IntfMagacc2LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc2_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc2LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc2_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc2LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC2_LSB to value 0"]
impl crate :: Resettable for IntfMagacc2LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC2_MSB (rw) register accessor: INTF_MAGACC2_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc2_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc2_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc2_msb`]
module"]
# [doc (alias = "INTF_MAGACC2_MSB")]
pub type IntfMagacc2Msb = crate :: Reg < intf_magacc2_msb :: IntfMagacc2MsbSpec > ; # [doc = "INTF_MAGACC2_MSB"]
pub mod intf_magacc2_msb { # [doc = "Register `INTF_MAGACC2_MSB` reader"]
pub type R = crate :: R < IntfMagacc2MsbSpec > ; # [doc = "Register `INTF_MAGACC2_MSB` writer"]
pub type W = crate :: W < IntfMagacc2MsbSpec > ; # [doc = "Field `INTF_MAGACC2_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 1"]
pub type IntfMagacc2MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGACC2_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 1"]
pub type IntfMagacc2MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 1"]
# [inline (always)]
pub fn intf_magacc2_msb (& self) -> IntfMagacc2MsbR { IntfMagacc2MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 1"]
# [inline (always)]
# [must_use]
pub fn intf_magacc2_msb (& mut self) -> IntfMagacc2MsbW < IntfMagacc2MsbSpec > { IntfMagacc2MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc2MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGACC2_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc2_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc2_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc2MsbSpec ; impl crate :: RegisterSpec for IntfMagacc2MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc2_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc2MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc2_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc2MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC2_MSB to value 0"]
impl crate :: Resettable for IntfMagacc2MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC3_LSB (rw) register accessor: INTF_MAGACC3_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc3_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc3_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc3_lsb`]
module"]
# [doc (alias = "INTF_MAGACC3_LSB")]
pub type IntfMagacc3Lsb = crate :: Reg < intf_magacc3_lsb :: IntfMagacc3LsbSpec > ; # [doc = "INTF_MAGACC3_LSB"]
pub mod intf_magacc3_lsb { # [doc = "Register `INTF_MAGACC3_LSB` reader"]
pub type R = crate :: R < IntfMagacc3LsbSpec > ; # [doc = "Register `INTF_MAGACC3_LSB` writer"]
pub type W = crate :: W < IntfMagacc3LsbSpec > ; # [doc = "Field `INTF_MAGACC3_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 2"]
pub type IntfMagacc3LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGACC3_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 2"]
pub type IntfMagacc3LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 2"]
# [inline (always)]
pub fn intf_magacc3_lsb (& self) -> IntfMagacc3LsbR { IntfMagacc3LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 2"]
# [inline (always)]
# [must_use]
pub fn intf_magacc3_lsb (& mut self) -> IntfMagacc3LsbW < IntfMagacc3LsbSpec > { IntfMagacc3LsbW :: new (self , 0) } } # [doc = "INTF_MAGACC3_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc3_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc3_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc3LsbSpec ; impl crate :: RegisterSpec for IntfMagacc3LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc3_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc3LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc3_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc3LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC3_LSB to value 0"]
impl crate :: Resettable for IntfMagacc3LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC3_MSB (rw) register accessor: INTF_MAGACC3_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc3_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc3_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc3_msb`]
module"]
# [doc (alias = "INTF_MAGACC3_MSB")]
pub type IntfMagacc3Msb = crate :: Reg < intf_magacc3_msb :: IntfMagacc3MsbSpec > ; # [doc = "INTF_MAGACC3_MSB"]
pub mod intf_magacc3_msb { # [doc = "Register `INTF_MAGACC3_MSB` reader"]
pub type R = crate :: R < IntfMagacc3MsbSpec > ; # [doc = "Register `INTF_MAGACC3_MSB` writer"]
pub type W = crate :: W < IntfMagacc3MsbSpec > ; # [doc = "Field `INTF_MAGACC3_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 2"]
pub type IntfMagacc3MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGACC3_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 2"]
pub type IntfMagacc3MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 2"]
# [inline (always)]
pub fn intf_magacc3_msb (& self) -> IntfMagacc3MsbR { IntfMagacc3MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 2"]
# [inline (always)]
# [must_use]
pub fn intf_magacc3_msb (& mut self) -> IntfMagacc3MsbW < IntfMagacc3MsbSpec > { IntfMagacc3MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc3MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGACC3_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc3_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc3_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc3MsbSpec ; impl crate :: RegisterSpec for IntfMagacc3MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc3_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc3MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc3_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc3MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC3_MSB to value 0"]
impl crate :: Resettable for IntfMagacc3MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC4_LSB (rw) register accessor: INTF_MAGACC4_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc4_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc4_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc4_lsb`]
module"]
# [doc (alias = "INTF_MAGACC4_LSB")]
pub type IntfMagacc4Lsb = crate :: Reg < intf_magacc4_lsb :: IntfMagacc4LsbSpec > ; # [doc = "INTF_MAGACC4_LSB"]
pub mod intf_magacc4_lsb { # [doc = "Register `INTF_MAGACC4_LSB` reader"]
pub type R = crate :: R < IntfMagacc4LsbSpec > ; # [doc = "Register `INTF_MAGACC4_LSB` writer"]
pub type W = crate :: W < IntfMagacc4LsbSpec > ; # [doc = "Field `INTF_MAGACC4_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 3"]
pub type IntfMagacc4LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGACC4_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 3"]
pub type IntfMagacc4LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 3"]
# [inline (always)]
pub fn intf_magacc4_lsb (& self) -> IntfMagacc4LsbR { IntfMagacc4LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 3"]
# [inline (always)]
# [must_use]
pub fn intf_magacc4_lsb (& mut self) -> IntfMagacc4LsbW < IntfMagacc4LsbSpec > { IntfMagacc4LsbW :: new (self , 0) } } # [doc = "INTF_MAGACC4_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc4_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc4_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc4LsbSpec ; impl crate :: RegisterSpec for IntfMagacc4LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc4_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc4LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc4_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc4LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC4_LSB to value 0"]
impl crate :: Resettable for IntfMagacc4LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC4_MSB (rw) register accessor: INTF_MAGACC4_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc4_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc4_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc4_msb`]
module"]
# [doc (alias = "INTF_MAGACC4_MSB")]
pub type IntfMagacc4Msb = crate :: Reg < intf_magacc4_msb :: IntfMagacc4MsbSpec > ; # [doc = "INTF_MAGACC4_MSB"]
pub mod intf_magacc4_msb { # [doc = "Register `INTF_MAGACC4_MSB` reader"]
pub type R = crate :: R < IntfMagacc4MsbSpec > ; # [doc = "Register `INTF_MAGACC4_MSB` writer"]
pub type W = crate :: W < IntfMagacc4MsbSpec > ; # [doc = "Field `INTF_MAGACC4_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 3"]
pub type IntfMagacc4MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGACC4_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 3"]
pub type IntfMagacc4MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 3"]
# [inline (always)]
pub fn intf_magacc4_msb (& self) -> IntfMagacc4MsbR { IntfMagacc4MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 3"]
# [inline (always)]
# [must_use]
pub fn intf_magacc4_msb (& mut self) -> IntfMagacc4MsbW < IntfMagacc4MsbSpec > { IntfMagacc4MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc4MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGACC4_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc4_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc4_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc4MsbSpec ; impl crate :: RegisterSpec for IntfMagacc4MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc4_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc4MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc4_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc4MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC4_MSB to value 0"]
impl crate :: Resettable for IntfMagacc4MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC5_LSB (rw) register accessor: INTF_MAGACC5_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc5_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc5_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc5_lsb`]
module"]
# [doc (alias = "INTF_MAGACC5_LSB")]
pub type IntfMagacc5Lsb = crate :: Reg < intf_magacc5_lsb :: IntfMagacc5LsbSpec > ; # [doc = "INTF_MAGACC5_LSB"]
pub mod intf_magacc5_lsb { # [doc = "Register `INTF_MAGACC5_LSB` reader"]
pub type R = crate :: R < IntfMagacc5LsbSpec > ; # [doc = "Register `INTF_MAGACC5_LSB` writer"]
pub type W = crate :: W < IntfMagacc5LsbSpec > ; # [doc = "Field `INTF_MAGACC5_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 4"]
pub type IntfMagacc5LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGACC5_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 4"]
pub type IntfMagacc5LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 4"]
# [inline (always)]
pub fn intf_magacc5_lsb (& self) -> IntfMagacc5LsbR { IntfMagacc5LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 4"]
# [inline (always)]
# [must_use]
pub fn intf_magacc5_lsb (& mut self) -> IntfMagacc5LsbW < IntfMagacc5LsbSpec > { IntfMagacc5LsbW :: new (self , 0) } } # [doc = "INTF_MAGACC5_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc5_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc5_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc5LsbSpec ; impl crate :: RegisterSpec for IntfMagacc5LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc5_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc5LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc5_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc5LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC5_LSB to value 0"]
impl crate :: Resettable for IntfMagacc5LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC5_MSB (rw) register accessor: INTF_MAGACC5_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc5_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc5_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc5_msb`]
module"]
# [doc (alias = "INTF_MAGACC5_MSB")]
pub type IntfMagacc5Msb = crate :: Reg < intf_magacc5_msb :: IntfMagacc5MsbSpec > ; # [doc = "INTF_MAGACC5_MSB"]
pub mod intf_magacc5_msb { # [doc = "Register `INTF_MAGACC5_MSB` reader"]
pub type R = crate :: R < IntfMagacc5MsbSpec > ; # [doc = "Register `INTF_MAGACC5_MSB` writer"]
pub type W = crate :: W < IntfMagacc5MsbSpec > ; # [doc = "Field `INTF_MAGACC5_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 4"]
pub type IntfMagacc5MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGACC5_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 4"]
pub type IntfMagacc5MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 4"]
# [inline (always)]
pub fn intf_magacc5_msb (& self) -> IntfMagacc5MsbR { IntfMagacc5MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 4"]
# [inline (always)]
# [must_use]
pub fn intf_magacc5_msb (& mut self) -> IntfMagacc5MsbW < IntfMagacc5MsbSpec > { IntfMagacc5MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc5MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGACC5_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc5_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc5_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc5MsbSpec ; impl crate :: RegisterSpec for IntfMagacc5MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc5_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc5MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc5_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc5MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC5_MSB to value 0"]
impl crate :: Resettable for IntfMagacc5MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC6_LSB (rw) register accessor: INTF_MAGACC6_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc6_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc6_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc6_lsb`]
module"]
# [doc (alias = "INTF_MAGACC6_LSB")]
pub type IntfMagacc6Lsb = crate :: Reg < intf_magacc6_lsb :: IntfMagacc6LsbSpec > ; # [doc = "INTF_MAGACC6_LSB"]
pub mod intf_magacc6_lsb { # [doc = "Register `INTF_MAGACC6_LSB` reader"]
pub type R = crate :: R < IntfMagacc6LsbSpec > ; # [doc = "Register `INTF_MAGACC6_LSB` writer"]
pub type W = crate :: W < IntfMagacc6LsbSpec > ; # [doc = "Field `INTF_MAGACC6_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 5"]
pub type IntfMagacc6LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGACC6_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 5"]
pub type IntfMagacc6LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 5"]
# [inline (always)]
pub fn intf_magacc6_lsb (& self) -> IntfMagacc6LsbR { IntfMagacc6LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 5"]
# [inline (always)]
# [must_use]
pub fn intf_magacc6_lsb (& mut self) -> IntfMagacc6LsbW < IntfMagacc6LsbSpec > { IntfMagacc6LsbW :: new (self , 0) } } # [doc = "INTF_MAGACC6_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc6_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc6_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc6LsbSpec ; impl crate :: RegisterSpec for IntfMagacc6LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc6_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc6LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc6_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc6LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC6_LSB to value 0"]
impl crate :: Resettable for IntfMagacc6LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC6_MSB (rw) register accessor: INTF_MAGACC6_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc6_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc6_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc6_msb`]
module"]
# [doc (alias = "INTF_MAGACC6_MSB")]
pub type IntfMagacc6Msb = crate :: Reg < intf_magacc6_msb :: IntfMagacc6MsbSpec > ; # [doc = "INTF_MAGACC6_MSB"]
pub mod intf_magacc6_msb { # [doc = "Register `INTF_MAGACC6_MSB` reader"]
pub type R = crate :: R < IntfMagacc6MsbSpec > ; # [doc = "Register `INTF_MAGACC6_MSB` writer"]
pub type W = crate :: W < IntfMagacc6MsbSpec > ; # [doc = "Field `INTF_MAGACC6_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 5"]
pub type IntfMagacc6MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGACC6_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 5"]
pub type IntfMagacc6MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 5"]
# [inline (always)]
pub fn intf_magacc6_msb (& self) -> IntfMagacc6MsbR { IntfMagacc6MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 5"]
# [inline (always)]
# [must_use]
pub fn intf_magacc6_msb (& mut self) -> IntfMagacc6MsbW < IntfMagacc6MsbSpec > { IntfMagacc6MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc6MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGACC6_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc6_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc6_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc6MsbSpec ; impl crate :: RegisterSpec for IntfMagacc6MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc6_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc6MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc6_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc6MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC6_MSB to value 0"]
impl crate :: Resettable for IntfMagacc6MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC1_LSB (rw) register accessor: INTF_MAGDIFFACC1_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc1_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc1_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc1_lsb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC1_LSB")]
pub type IntfMagdiffacc1Lsb = crate :: Reg < intf_magdiffacc1_lsb :: IntfMagdiffacc1LsbSpec > ; # [doc = "INTF_MAGDIFFACC1_LSB"]
pub mod intf_magdiffacc1_lsb { # [doc = "Register `INTF_MAGDIFFACC1_LSB` reader"]
pub type R = crate :: R < IntfMagdiffacc1LsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC1_LSB` writer"]
pub type W = crate :: W < IntfMagdiffacc1LsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC1_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 0"]
pub type IntfMagdiffacc1LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFACC1_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 0"]
pub type IntfMagdiffacc1LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 0"]
# [inline (always)]
pub fn intf_magdiffacc1_lsb (& self) -> IntfMagdiffacc1LsbR { IntfMagdiffacc1LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 0"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc1_lsb (& mut self) -> IntfMagdiffacc1LsbW < IntfMagdiffacc1LsbSpec > { IntfMagdiffacc1LsbW :: new (self , 0) } } # [doc = "INTF_MAGDIFFACC1_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc1_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc1_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc1LsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc1LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc1_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc1LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc1_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc1LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC1_LSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc1LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC1_MSB (rw) register accessor: INTF_MAGDIFFACC1_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc1_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc1_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc1_msb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC1_MSB")]
pub type IntfMagdiffacc1Msb = crate :: Reg < intf_magdiffacc1_msb :: IntfMagdiffacc1MsbSpec > ; # [doc = "INTF_MAGDIFFACC1_MSB"]
pub mod intf_magdiffacc1_msb { # [doc = "Register `INTF_MAGDIFFACC1_MSB` reader"]
pub type R = crate :: R < IntfMagdiffacc1MsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC1_MSB` writer"]
pub type W = crate :: W < IntfMagdiffacc1MsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC1_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0"]
pub type IntfMagdiffacc1MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFFACC1_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0"]
pub type IntfMagdiffacc1MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0"]
# [inline (always)]
pub fn intf_magdiffacc1_msb (& self) -> IntfMagdiffacc1MsbR { IntfMagdiffacc1MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc1_msb (& mut self) -> IntfMagdiffacc1MsbW < IntfMagdiffacc1MsbSpec > { IntfMagdiffacc1MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc1MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFFACC1_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc1_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc1_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc1MsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc1MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc1_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc1MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc1_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc1MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC1_MSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc1MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC2_LSB (rw) register accessor: INTF_MAGDIFFACC2_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc2_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc2_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc2_lsb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC2_LSB")]
pub type IntfMagdiffacc2Lsb = crate :: Reg < intf_magdiffacc2_lsb :: IntfMagdiffacc2LsbSpec > ; # [doc = "INTF_MAGDIFFACC2_LSB"]
pub mod intf_magdiffacc2_lsb { # [doc = "Register `INTF_MAGDIFFACC2_LSB` reader"]
pub type R = crate :: R < IntfMagdiffacc2LsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC2_LSB` writer"]
pub type W = crate :: W < IntfMagdiffacc2LsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC2_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 1"]
pub type IntfMagdiffacc2LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFACC2_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 1"]
pub type IntfMagdiffacc2LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 1"]
# [inline (always)]
pub fn intf_magdiffacc2_lsb (& self) -> IntfMagdiffacc2LsbR { IntfMagdiffacc2LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 1"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc2_lsb (& mut self) -> IntfMagdiffacc2LsbW < IntfMagdiffacc2LsbSpec > { IntfMagdiffacc2LsbW :: new (self , 0) } } # [doc = "INTF_MAGDIFFACC2_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc2_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc2_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc2LsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc2LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc2_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc2LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc2_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc2LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC2_LSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc2LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC2_MSB (rw) register accessor: INTF_MAGDIFFACC2_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc2_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc2_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc2_msb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC2_MSB")]
pub type IntfMagdiffacc2Msb = crate :: Reg < intf_magdiffacc2_msb :: IntfMagdiffacc2MsbSpec > ; # [doc = "INTF_MAGDIFFACC2_MSB"]
pub mod intf_magdiffacc2_msb { # [doc = "Register `INTF_MAGDIFFACC2_MSB` reader"]
pub type R = crate :: R < IntfMagdiffacc2MsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC2_MSB` writer"]
pub type W = crate :: W < IntfMagdiffacc2MsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC2_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1"]
pub type IntfMagdiffacc2MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFFACC2_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1"]
pub type IntfMagdiffacc2MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1"]
# [inline (always)]
pub fn intf_magdiffacc2_msb (& self) -> IntfMagdiffacc2MsbR { IntfMagdiffacc2MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc2_msb (& mut self) -> IntfMagdiffacc2MsbW < IntfMagdiffacc2MsbSpec > { IntfMagdiffacc2MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc2MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFFACC2_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc2_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc2_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc2MsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc2MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc2_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc2MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc2_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc2MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC2_MSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc2MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC3_LSB (rw) register accessor: INTF_MAGDIFFACC3_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc3_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc3_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc3_lsb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC3_LSB")]
pub type IntfMagdiffacc3Lsb = crate :: Reg < intf_magdiffacc3_lsb :: IntfMagdiffacc3LsbSpec > ; # [doc = "INTF_MAGDIFFACC3_LSB"]
pub mod intf_magdiffacc3_lsb { # [doc = "Register `INTF_MAGDIFFACC3_LSB` reader"]
pub type R = crate :: R < IntfMagdiffacc3LsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC3_LSB` writer"]
pub type W = crate :: W < IntfMagdiffacc3LsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC3_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 2"]
pub type IntfMagdiffacc3LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFACC3_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 2"]
pub type IntfMagdiffacc3LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 2"]
# [inline (always)]
pub fn intf_magdiffacc3_lsb (& self) -> IntfMagdiffacc3LsbR { IntfMagdiffacc3LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 2"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc3_lsb (& mut self) -> IntfMagdiffacc3LsbW < IntfMagdiffacc3LsbSpec > { IntfMagdiffacc3LsbW :: new (self , 0) } } # [doc = "INTF_MAGDIFFACC3_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc3_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc3_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc3LsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc3LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc3_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc3LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc3_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc3LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC3_LSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc3LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC3_MSB (rw) register accessor: INTF_MAGDIFFACC3_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc3_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc3_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc3_msb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC3_MSB")]
pub type IntfMagdiffacc3Msb = crate :: Reg < intf_magdiffacc3_msb :: IntfMagdiffacc3MsbSpec > ; # [doc = "INTF_MAGDIFFACC3_MSB"]
pub mod intf_magdiffacc3_msb { # [doc = "Register `INTF_MAGDIFFACC3_MSB` reader"]
pub type R = crate :: R < IntfMagdiffacc3MsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC3_MSB` writer"]
pub type W = crate :: W < IntfMagdiffacc3MsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC3_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2"]
pub type IntfMagdiffacc3MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFFACC3_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2"]
pub type IntfMagdiffacc3MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2"]
# [inline (always)]
pub fn intf_magdiffacc3_msb (& self) -> IntfMagdiffacc3MsbR { IntfMagdiffacc3MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc3_msb (& mut self) -> IntfMagdiffacc3MsbW < IntfMagdiffacc3MsbSpec > { IntfMagdiffacc3MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc3MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFFACC3_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc3_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc3_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc3MsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc3MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc3_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc3MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc3_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc3MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC3_MSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc3MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC4_LSB (rw) register accessor: INTF_MAGDIFFACC4_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc4_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc4_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc4_lsb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC4_LSB")]
pub type IntfMagdiffacc4Lsb = crate :: Reg < intf_magdiffacc4_lsb :: IntfMagdiffacc4LsbSpec > ; # [doc = "INTF_MAGDIFFACC4_LSB"]
pub mod intf_magdiffacc4_lsb { # [doc = "Register `INTF_MAGDIFFACC4_LSB` reader"]
pub type R = crate :: R < IntfMagdiffacc4LsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC4_LSB` writer"]
pub type W = crate :: W < IntfMagdiffacc4LsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC4_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 3"]
pub type IntfMagdiffacc4LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFACC4_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 3"]
pub type IntfMagdiffacc4LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 3"]
# [inline (always)]
pub fn intf_magdiffacc4_lsb (& self) -> IntfMagdiffacc4LsbR { IntfMagdiffacc4LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 3"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc4_lsb (& mut self) -> IntfMagdiffacc4LsbW < IntfMagdiffacc4LsbSpec > { IntfMagdiffacc4LsbW :: new (self , 0) } } # [doc = "INTF_MAGDIFFACC4_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc4_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc4_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc4LsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc4LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc4_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc4LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc4_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc4LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC4_LSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc4LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC4_MSB (rw) register accessor: INTF_MAGDIFFACC4_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc4_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc4_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc4_msb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC4_MSB")]
pub type IntfMagdiffacc4Msb = crate :: Reg < intf_magdiffacc4_msb :: IntfMagdiffacc4MsbSpec > ; # [doc = "INTF_MAGDIFFACC4_MSB"]
pub mod intf_magdiffacc4_msb { # [doc = "Register `INTF_MAGDIFFACC4_MSB` reader"]
pub type R = crate :: R < IntfMagdiffacc4MsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC4_MSB` writer"]
pub type W = crate :: W < IntfMagdiffacc4MsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC4_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3"]
pub type IntfMagdiffacc4MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFFACC4_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3"]
pub type IntfMagdiffacc4MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3"]
# [inline (always)]
pub fn intf_magdiffacc4_msb (& self) -> IntfMagdiffacc4MsbR { IntfMagdiffacc4MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc4_msb (& mut self) -> IntfMagdiffacc4MsbW < IntfMagdiffacc4MsbSpec > { IntfMagdiffacc4MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc4MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFFACC4_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc4_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc4_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc4MsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc4MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc4_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc4MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc4_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc4MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC4_MSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc4MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC5_LSB (rw) register accessor: INTF_MAGDIFFACC5_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc5_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc5_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc5_lsb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC5_LSB")]
pub type IntfMagdiffacc5Lsb = crate :: Reg < intf_magdiffacc5_lsb :: IntfMagdiffacc5LsbSpec > ; # [doc = "INTF_MAGDIFFACC5_LSB"]
pub mod intf_magdiffacc5_lsb { # [doc = "Register `INTF_MAGDIFFACC5_LSB` reader"]
pub type R = crate :: R < IntfMagdiffacc5LsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC5_LSB` writer"]
pub type W = crate :: W < IntfMagdiffacc5LsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC5_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 4"]
pub type IntfMagdiffacc5LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFACC5_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 4"]
pub type IntfMagdiffacc5LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 4"]
# [inline (always)]
pub fn intf_magdiffacc5_lsb (& self) -> IntfMagdiffacc5LsbR { IntfMagdiffacc5LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 4"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc5_lsb (& mut self) -> IntfMagdiffacc5LsbW < IntfMagdiffacc5LsbSpec > { IntfMagdiffacc5LsbW :: new (self , 0) } } # [doc = "INTF_MAGDIFFACC5_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc5_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc5_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc5LsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc5LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc5_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc5LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc5_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc5LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC5_LSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc5LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC5_MSB (rw) register accessor: INTF_MAGDIFFACC5_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc5_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc5_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc5_msb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC5_MSB")]
pub type IntfMagdiffacc5Msb = crate :: Reg < intf_magdiffacc5_msb :: IntfMagdiffacc5MsbSpec > ; # [doc = "INTF_MAGDIFFACC5_MSB"]
pub mod intf_magdiffacc5_msb { # [doc = "Register `INTF_MAGDIFFACC5_MSB` reader"]
pub type R = crate :: R < IntfMagdiffacc5MsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC5_MSB` writer"]
pub type W = crate :: W < IntfMagdiffacc5MsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC5_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4"]
pub type IntfMagdiffacc5MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFFACC5_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4"]
pub type IntfMagdiffacc5MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4"]
# [inline (always)]
pub fn intf_magdiffacc5_msb (& self) -> IntfMagdiffacc5MsbR { IntfMagdiffacc5MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc5_msb (& mut self) -> IntfMagdiffacc5MsbW < IntfMagdiffacc5MsbSpec > { IntfMagdiffacc5MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc5MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFFACC5_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc5_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc5_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc5MsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc5MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc5_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc5MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc5_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc5MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC5_MSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc5MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC6_LSB (rw) register accessor: INTF_MAGDIFFACC6_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc6_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc6_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc6_lsb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC6_LSB")]
pub type IntfMagdiffacc6Lsb = crate :: Reg < intf_magdiffacc6_lsb :: IntfMagdiffacc6LsbSpec > ; # [doc = "INTF_MAGDIFFACC6_LSB"]
pub mod intf_magdiffacc6_lsb { # [doc = "Register `INTF_MAGDIFFACC6_LSB` reader"]
pub type R = crate :: R < IntfMagdiffacc6LsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC6_LSB` writer"]
pub type W = crate :: W < IntfMagdiffacc6LsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC6_LSB` reader - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 5"]
pub type IntfMagdiffacc6LsbR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFACC6_LSB` writer - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 5"]
pub type IntfMagdiffacc6LsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 5"]
# [inline (always)]
pub fn intf_magdiffacc6_lsb (& self) -> IntfMagdiffacc6LsbR { IntfMagdiffacc6LsbR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 5"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc6_lsb (& mut self) -> IntfMagdiffacc6LsbW < IntfMagdiffacc6LsbSpec > { IntfMagdiffacc6LsbW :: new (self , 0) } } # [doc = "INTF_MAGDIFFACC6_LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc6_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc6_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc6LsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc6LsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc6_lsb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc6LsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc6_lsb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc6LsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC6_LSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc6LsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC6_MSB (rw) register accessor: INTF_MAGDIFFACC6_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc6_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc6_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc6_msb`]
module"]
# [doc (alias = "INTF_MAGDIFFACC6_MSB")]
pub type IntfMagdiffacc6Msb = crate :: Reg < intf_magdiffacc6_msb :: IntfMagdiffacc6MsbSpec > ; # [doc = "INTF_MAGDIFFACC6_MSB"]
pub mod intf_magdiffacc6_msb { # [doc = "Register `INTF_MAGDIFFACC6_MSB` reader"]
pub type R = crate :: R < IntfMagdiffacc6MsbSpec > ; # [doc = "Register `INTF_MAGDIFFACC6_MSB` writer"]
pub type W = crate :: W < IntfMagdiffacc6MsbSpec > ; # [doc = "Field `INTF_MAGDIFFACC6_MSB` reader - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5"]
pub type IntfMagdiffacc6MsbR = crate :: FieldReader ; # [doc = "Field `INTF_MAGDIFFACC6_MSB` writer - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5"]
pub type IntfMagdiffacc6MsbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5"]
# [inline (always)]
pub fn intf_magdiffacc6_msb (& self) -> IntfMagdiffacc6MsbR { IntfMagdiffacc6MsbR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc6_msb (& mut self) -> IntfMagdiffacc6MsbW < IntfMagdiffacc6MsbSpec > { IntfMagdiffacc6MsbW :: new (self , 0) } # [doc = "Bits 4:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc6MsbSpec > { Nu1W :: new (self , 4) } } # [doc = "INTF_MAGDIFFACC6_MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc6_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc6_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc6MsbSpec ; impl crate :: RegisterSpec for IntfMagdiffacc6MsbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc6_msb::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc6MsbSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc6_msb::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc6MsbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC6_MSB to value 0"]
impl crate :: Resettable for IntfMagdiffacc6MsbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC1_CLIP (rw) register accessor: INTF_MAGACC1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc1_clip`]
module"]
# [doc (alias = "INTF_MAGACC1_CLIP")]
pub type IntfMagacc1Clip = crate :: Reg < intf_magacc1_clip :: IntfMagacc1ClipSpec > ; # [doc = "INTF_MAGACC1_CLIP"]
pub mod intf_magacc1_clip { # [doc = "Register `INTF_MAGACC1_CLIP` reader"]
pub type R = crate :: R < IntfMagacc1ClipSpec > ; # [doc = "Register `INTF_MAGACC1_CLIP` writer"]
pub type W = crate :: W < IntfMagacc1ClipSpec > ; # [doc = "Field `INTF_MAGACC1_CLIP` reader - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc1ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGACC1_CLIP` writer - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
pub fn intf_magacc1_clip (& self) -> IntfMagacc1ClipR { IntfMagacc1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magacc1_clip (& mut self) -> IntfMagacc1ClipW < IntfMagacc1ClipSpec > { IntfMagacc1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGACC1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc1ClipSpec ; impl crate :: RegisterSpec for IntfMagacc1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc1_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc1_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC1_CLIP to value 0"]
impl crate :: Resettable for IntfMagacc1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC2_CLIP (rw) register accessor: INTF_MAGACC2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc2_clip`]
module"]
# [doc (alias = "INTF_MAGACC2_CLIP")]
pub type IntfMagacc2Clip = crate :: Reg < intf_magacc2_clip :: IntfMagacc2ClipSpec > ; # [doc = "INTF_MAGACC2_CLIP"]
pub mod intf_magacc2_clip { # [doc = "Register `INTF_MAGACC2_CLIP` reader"]
pub type R = crate :: R < IntfMagacc2ClipSpec > ; # [doc = "Register `INTF_MAGACC2_CLIP` writer"]
pub type W = crate :: W < IntfMagacc2ClipSpec > ; # [doc = "Field `INTF_MAGACC2_CLIP` reader - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc2ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGACC2_CLIP` writer - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
pub fn intf_magacc2_clip (& self) -> IntfMagacc2ClipR { IntfMagacc2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magacc2_clip (& mut self) -> IntfMagacc2ClipW < IntfMagacc2ClipSpec > { IntfMagacc2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGACC2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc2ClipSpec ; impl crate :: RegisterSpec for IntfMagacc2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc2_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc2_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC2_CLIP to value 0"]
impl crate :: Resettable for IntfMagacc2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC3_CLIP (rw) register accessor: INTF_MAGACC3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc3_clip`]
module"]
# [doc (alias = "INTF_MAGACC3_CLIP")]
pub type IntfMagacc3Clip = crate :: Reg < intf_magacc3_clip :: IntfMagacc3ClipSpec > ; # [doc = "INTF_MAGACC3_CLIP"]
pub mod intf_magacc3_clip { # [doc = "Register `INTF_MAGACC3_CLIP` reader"]
pub type R = crate :: R < IntfMagacc3ClipSpec > ; # [doc = "Register `INTF_MAGACC3_CLIP` writer"]
pub type W = crate :: W < IntfMagacc3ClipSpec > ; # [doc = "Field `INTF_MAGACC3_CLIP` reader - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc3ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGACC3_CLIP` writer - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
pub fn intf_magacc3_clip (& self) -> IntfMagacc3ClipR { IntfMagacc3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magacc3_clip (& mut self) -> IntfMagacc3ClipW < IntfMagacc3ClipSpec > { IntfMagacc3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGACC3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc3ClipSpec ; impl crate :: RegisterSpec for IntfMagacc3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc3_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc3_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC3_CLIP to value 0"]
impl crate :: Resettable for IntfMagacc3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC4_CLIP (rw) register accessor: INTF_MAGACC4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc4_clip`]
module"]
# [doc (alias = "INTF_MAGACC4_CLIP")]
pub type IntfMagacc4Clip = crate :: Reg < intf_magacc4_clip :: IntfMagacc4ClipSpec > ; # [doc = "INTF_MAGACC4_CLIP"]
pub mod intf_magacc4_clip { # [doc = "Register `INTF_MAGACC4_CLIP` reader"]
pub type R = crate :: R < IntfMagacc4ClipSpec > ; # [doc = "Register `INTF_MAGACC4_CLIP` writer"]
pub type W = crate :: W < IntfMagacc4ClipSpec > ; # [doc = "Field `INTF_MAGACC4_CLIP` reader - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc4ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGACC4_CLIP` writer - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
pub fn intf_magacc4_clip (& self) -> IntfMagacc4ClipR { IntfMagacc4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magacc4_clip (& mut self) -> IntfMagacc4ClipW < IntfMagacc4ClipSpec > { IntfMagacc4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGACC4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc4ClipSpec ; impl crate :: RegisterSpec for IntfMagacc4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc4_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc4_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC4_CLIP to value 0"]
impl crate :: Resettable for IntfMagacc4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC5_CLIP (rw) register accessor: INTF_MAGACC5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc5_clip`]
module"]
# [doc (alias = "INTF_MAGACC5_CLIP")]
pub type IntfMagacc5Clip = crate :: Reg < intf_magacc5_clip :: IntfMagacc5ClipSpec > ; # [doc = "INTF_MAGACC5_CLIP"]
pub mod intf_magacc5_clip { # [doc = "Register `INTF_MAGACC5_CLIP` reader"]
pub type R = crate :: R < IntfMagacc5ClipSpec > ; # [doc = "Register `INTF_MAGACC5_CLIP` writer"]
pub type W = crate :: W < IntfMagacc5ClipSpec > ; # [doc = "Field `INTF_MAGACC5_CLIP` reader - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc5ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGACC5_CLIP` writer - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
pub fn intf_magacc5_clip (& self) -> IntfMagacc5ClipR { IntfMagacc5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magacc5_clip (& mut self) -> IntfMagacc5ClipW < IntfMagacc5ClipSpec > { IntfMagacc5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGACC5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc5ClipSpec ; impl crate :: RegisterSpec for IntfMagacc5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc5_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc5_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC5_CLIP to value 0"]
impl crate :: Resettable for IntfMagacc5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGACC6_CLIP (rw) register accessor: INTF_MAGACC6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magacc6_clip`]
module"]
# [doc (alias = "INTF_MAGACC6_CLIP")]
pub type IntfMagacc6Clip = crate :: Reg < intf_magacc6_clip :: IntfMagacc6ClipSpec > ; # [doc = "INTF_MAGACC6_CLIP"]
pub mod intf_magacc6_clip { # [doc = "Register `INTF_MAGACC6_CLIP` reader"]
pub type R = crate :: R < IntfMagacc6ClipSpec > ; # [doc = "Register `INTF_MAGACC6_CLIP` writer"]
pub type W = crate :: W < IntfMagacc6ClipSpec > ; # [doc = "Field `INTF_MAGACC6_CLIP` reader - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc6ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGACC6_CLIP` writer - 0:0\\]
Interference magnitude accumulator clip status"]
pub type IntfMagacc6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
pub fn intf_magacc6_clip (& self) -> IntfMagacc6ClipR { IntfMagacc6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magacc6_clip (& mut self) -> IntfMagacc6ClipW < IntfMagacc6ClipSpec > { IntfMagacc6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagacc6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGACC6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magacc6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magacc6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagacc6ClipSpec ; impl crate :: RegisterSpec for IntfMagacc6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magacc6_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagacc6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magacc6_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagacc6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGACC6_CLIP to value 0"]
impl crate :: Resettable for IntfMagacc6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC1_CLIP (rw) register accessor: INTF_MAGDIFFACC1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc1_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFACC1_CLIP")]
pub type IntfMagdiffacc1Clip = crate :: Reg < intf_magdiffacc1_clip :: IntfMagdiffacc1ClipSpec > ; # [doc = "INTF_MAGDIFFACC1_CLIP"]
pub mod intf_magdiffacc1_clip { # [doc = "Register `INTF_MAGDIFFACC1_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffacc1ClipSpec > ; # [doc = "Register `INTF_MAGDIFFACC1_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffacc1ClipSpec > ; # [doc = "Field `INTF_MAGDIFFACC1_CLIP` reader - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc1ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFACC1_CLIP` writer - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
pub fn intf_magdiffacc1_clip (& self) -> IntfMagdiffacc1ClipR { IntfMagdiffacc1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc1_clip (& mut self) -> IntfMagdiffacc1ClipW < IntfMagdiffacc1ClipSpec > { IntfMagdiffacc1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFACC1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc1ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffacc1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc1_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc1_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC1_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffacc1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC2_CLIP (rw) register accessor: INTF_MAGDIFFACC2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc2_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFACC2_CLIP")]
pub type IntfMagdiffacc2Clip = crate :: Reg < intf_magdiffacc2_clip :: IntfMagdiffacc2ClipSpec > ; # [doc = "INTF_MAGDIFFACC2_CLIP"]
pub mod intf_magdiffacc2_clip { # [doc = "Register `INTF_MAGDIFFACC2_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffacc2ClipSpec > ; # [doc = "Register `INTF_MAGDIFFACC2_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffacc2ClipSpec > ; # [doc = "Field `INTF_MAGDIFFACC2_CLIP` reader - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc2ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFACC2_CLIP` writer - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
pub fn intf_magdiffacc2_clip (& self) -> IntfMagdiffacc2ClipR { IntfMagdiffacc2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc2_clip (& mut self) -> IntfMagdiffacc2ClipW < IntfMagdiffacc2ClipSpec > { IntfMagdiffacc2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFACC2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc2ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffacc2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc2_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc2_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC2_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffacc2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC3_CLIP (rw) register accessor: INTF_MAGDIFFACC3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc3_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFACC3_CLIP")]
pub type IntfMagdiffacc3Clip = crate :: Reg < intf_magdiffacc3_clip :: IntfMagdiffacc3ClipSpec > ; # [doc = "INTF_MAGDIFFACC3_CLIP"]
pub mod intf_magdiffacc3_clip { # [doc = "Register `INTF_MAGDIFFACC3_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffacc3ClipSpec > ; # [doc = "Register `INTF_MAGDIFFACC3_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffacc3ClipSpec > ; # [doc = "Field `INTF_MAGDIFFACC3_CLIP` reader - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc3ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFACC3_CLIP` writer - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
pub fn intf_magdiffacc3_clip (& self) -> IntfMagdiffacc3ClipR { IntfMagdiffacc3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc3_clip (& mut self) -> IntfMagdiffacc3ClipW < IntfMagdiffacc3ClipSpec > { IntfMagdiffacc3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFACC3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc3ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffacc3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc3_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc3_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC3_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffacc3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC4_CLIP (rw) register accessor: INTF_MAGDIFFACC4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc4_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFACC4_CLIP")]
pub type IntfMagdiffacc4Clip = crate :: Reg < intf_magdiffacc4_clip :: IntfMagdiffacc4ClipSpec > ; # [doc = "INTF_MAGDIFFACC4_CLIP"]
pub mod intf_magdiffacc4_clip { # [doc = "Register `INTF_MAGDIFFACC4_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffacc4ClipSpec > ; # [doc = "Register `INTF_MAGDIFFACC4_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffacc4ClipSpec > ; # [doc = "Field `INTF_MAGDIFFACC4_CLIP` reader - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc4ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFACC4_CLIP` writer - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
pub fn intf_magdiffacc4_clip (& self) -> IntfMagdiffacc4ClipR { IntfMagdiffacc4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc4_clip (& mut self) -> IntfMagdiffacc4ClipW < IntfMagdiffacc4ClipSpec > { IntfMagdiffacc4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFACC4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc4ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffacc4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc4_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc4_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC4_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffacc4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC5_CLIP (rw) register accessor: INTF_MAGDIFFACC5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc5_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFACC5_CLIP")]
pub type IntfMagdiffacc5Clip = crate :: Reg < intf_magdiffacc5_clip :: IntfMagdiffacc5ClipSpec > ; # [doc = "INTF_MAGDIFFACC5_CLIP"]
pub mod intf_magdiffacc5_clip { # [doc = "Register `INTF_MAGDIFFACC5_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffacc5ClipSpec > ; # [doc = "Register `INTF_MAGDIFFACC5_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffacc5ClipSpec > ; # [doc = "Field `INTF_MAGDIFFACC5_CLIP` reader - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc5ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFACC5_CLIP` writer - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
pub fn intf_magdiffacc5_clip (& self) -> IntfMagdiffacc5ClipR { IntfMagdiffacc5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc5_clip (& mut self) -> IntfMagdiffacc5ClipW < IntfMagdiffacc5ClipSpec > { IntfMagdiffacc5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFACC5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc5ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffacc5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc5_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc5_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC5_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffacc5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFACC6_CLIP (rw) register accessor: INTF_MAGDIFFACC6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffacc6_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFACC6_CLIP")]
pub type IntfMagdiffacc6Clip = crate :: Reg < intf_magdiffacc6_clip :: IntfMagdiffacc6ClipSpec > ; # [doc = "INTF_MAGDIFFACC6_CLIP"]
pub mod intf_magdiffacc6_clip { # [doc = "Register `INTF_MAGDIFFACC6_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffacc6ClipSpec > ; # [doc = "Register `INTF_MAGDIFFACC6_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffacc6ClipSpec > ; # [doc = "Field `INTF_MAGDIFFACC6_CLIP` reader - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc6ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFACC6_CLIP` writer - 0:0\\]
Interference magnitude difference accumulator clip status"]
pub type IntfMagdiffacc6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
pub fn intf_magdiffacc6_clip (& self) -> IntfMagdiffacc6ClipR { IntfMagdiffacc6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference accumulator clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffacc6_clip (& mut self) -> IntfMagdiffacc6ClipW < IntfMagdiffacc6ClipSpec > { IntfMagdiffacc6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffacc6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFACC6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffacc6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffacc6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffacc6ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffacc6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffacc6_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffacc6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffacc6_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffacc6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFACC6_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffacc6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH1 (rw) register accessor: INTF_MAGTHRESH1\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh1`]
module"]
# [doc (alias = "INTF_MAGTHRESH1")]
pub type IntfMagthresh1 = crate :: Reg < intf_magthresh1 :: IntfMagthresh1Spec > ; # [doc = "INTF_MAGTHRESH1"]
pub mod intf_magthresh1 { # [doc = "Register `INTF_MAGTHRESH1` reader"]
pub type R = crate :: R < IntfMagthresh1Spec > ; # [doc = "Register `INTF_MAGTHRESH1` writer"]
pub type W = crate :: W < IntfMagthresh1Spec > ; # [doc = "Field `INTF_MAGTHRESH1` reader - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =0"]
pub type IntfMagthresh1R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH1` writer - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =0"]
pub type IntfMagthresh1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =0"]
# [inline (always)]
pub fn intf_magthresh1 (& self) -> IntfMagthresh1R { IntfMagthresh1R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh1 (& mut self) -> IntfMagthresh1W < IntfMagthresh1Spec > { IntfMagthresh1W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh1Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH1\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh1Spec ; impl crate :: RegisterSpec for IntfMagthresh1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh1::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh1Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh1::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH1 to value 0"]
impl crate :: Resettable for IntfMagthresh1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH2 (rw) register accessor: INTF_MAGTHRESH2\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh2`]
module"]
# [doc (alias = "INTF_MAGTHRESH2")]
pub type IntfMagthresh2 = crate :: Reg < intf_magthresh2 :: IntfMagthresh2Spec > ; # [doc = "INTF_MAGTHRESH2"]
pub mod intf_magthresh2 { # [doc = "Register `INTF_MAGTHRESH2` reader"]
pub type R = crate :: R < IntfMagthresh2Spec > ; # [doc = "Register `INTF_MAGTHRESH2` writer"]
pub type W = crate :: W < IntfMagthresh2Spec > ; # [doc = "Field `INTF_MAGTHRESH2` reader - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =1"]
pub type IntfMagthresh2R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH2` writer - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =1"]
pub type IntfMagthresh2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =1"]
# [inline (always)]
pub fn intf_magthresh2 (& self) -> IntfMagthresh2R { IntfMagthresh2R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh2 (& mut self) -> IntfMagthresh2W < IntfMagthresh2Spec > { IntfMagthresh2W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh2Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH2\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh2Spec ; impl crate :: RegisterSpec for IntfMagthresh2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh2::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh2Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh2::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH2 to value 0"]
impl crate :: Resettable for IntfMagthresh2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH3 (rw) register accessor: INTF_MAGTHRESH3\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh3`]
module"]
# [doc (alias = "INTF_MAGTHRESH3")]
pub type IntfMagthresh3 = crate :: Reg < intf_magthresh3 :: IntfMagthresh3Spec > ; # [doc = "INTF_MAGTHRESH3"]
pub mod intf_magthresh3 { # [doc = "Register `INTF_MAGTHRESH3` reader"]
pub type R = crate :: R < IntfMagthresh3Spec > ; # [doc = "Register `INTF_MAGTHRESH3` writer"]
pub type W = crate :: W < IntfMagthresh3Spec > ; # [doc = "Field `INTF_MAGTHRESH3` reader - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =2"]
pub type IntfMagthresh3R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH3` writer - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =2"]
pub type IntfMagthresh3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =2"]
# [inline (always)]
pub fn intf_magthresh3 (& self) -> IntfMagthresh3R { IntfMagthresh3R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh3 (& mut self) -> IntfMagthresh3W < IntfMagthresh3Spec > { IntfMagthresh3W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh3Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH3\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh3Spec ; impl crate :: RegisterSpec for IntfMagthresh3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh3::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh3Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh3::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH3 to value 0"]
impl crate :: Resettable for IntfMagthresh3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH4 (rw) register accessor: INTF_MAGTHRESH4\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh4`]
module"]
# [doc (alias = "INTF_MAGTHRESH4")]
pub type IntfMagthresh4 = crate :: Reg < intf_magthresh4 :: IntfMagthresh4Spec > ; # [doc = "INTF_MAGTHRESH4"]
pub mod intf_magthresh4 { # [doc = "Register `INTF_MAGTHRESH4` reader"]
pub type R = crate :: R < IntfMagthresh4Spec > ; # [doc = "Register `INTF_MAGTHRESH4` writer"]
pub type W = crate :: W < IntfMagthresh4Spec > ; # [doc = "Field `INTF_MAGTHRESH4` reader - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =3"]
pub type IntfMagthresh4R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH4` writer - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =3"]
pub type IntfMagthresh4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =3"]
# [inline (always)]
pub fn intf_magthresh4 (& self) -> IntfMagthresh4R { IntfMagthresh4R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh4 (& mut self) -> IntfMagthresh4W < IntfMagthresh4Spec > { IntfMagthresh4W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh4Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH4\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh4Spec ; impl crate :: RegisterSpec for IntfMagthresh4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh4::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh4Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh4::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH4 to value 0"]
impl crate :: Resettable for IntfMagthresh4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH5 (rw) register accessor: INTF_MAGTHRESH5\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh5`]
module"]
# [doc (alias = "INTF_MAGTHRESH5")]
pub type IntfMagthresh5 = crate :: Reg < intf_magthresh5 :: IntfMagthresh5Spec > ; # [doc = "INTF_MAGTHRESH5"]
pub mod intf_magthresh5 { # [doc = "Register `INTF_MAGTHRESH5` reader"]
pub type R = crate :: R < IntfMagthresh5Spec > ; # [doc = "Register `INTF_MAGTHRESH5` writer"]
pub type W = crate :: W < IntfMagthresh5Spec > ; # [doc = "Field `INTF_MAGTHRESH5` reader - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =4"]
pub type IntfMagthresh5R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH5` writer - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =4"]
pub type IntfMagthresh5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =4"]
# [inline (always)]
pub fn intf_magthresh5 (& self) -> IntfMagthresh5R { IntfMagthresh5R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh5 (& mut self) -> IntfMagthresh5W < IntfMagthresh5Spec > { IntfMagthresh5W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh5Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH5\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh5Spec ; impl crate :: RegisterSpec for IntfMagthresh5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh5::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh5Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh5::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH5 to value 0"]
impl crate :: Resettable for IntfMagthresh5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH6 (rw) register accessor: INTF_MAGTHRESH6\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh6`]
module"]
# [doc (alias = "INTF_MAGTHRESH6")]
pub type IntfMagthresh6 = crate :: Reg < intf_magthresh6 :: IntfMagthresh6Spec > ; # [doc = "INTF_MAGTHRESH6"]
pub mod intf_magthresh6 { # [doc = "Register `INTF_MAGTHRESH6` reader"]
pub type R = crate :: R < IntfMagthresh6Spec > ; # [doc = "Register `INTF_MAGTHRESH6` writer"]
pub type W = crate :: W < IntfMagthresh6Spec > ; # [doc = "Field `INTF_MAGTHRESH6` reader - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =5"]
pub type IntfMagthresh6R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGTHRESH6` writer - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =5"]
pub type IntfMagthresh6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =5"]
# [inline (always)]
pub fn intf_magthresh6 (& self) -> IntfMagthresh6R { IntfMagthresh6R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude threshold by interference statistics for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh6 (& mut self) -> IntfMagthresh6W < IntfMagthresh6Spec > { IntfMagthresh6W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh6Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGTHRESH6\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh6Spec ; impl crate :: RegisterSpec for IntfMagthresh6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh6::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh6Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh6::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH6 to value 0"]
impl crate :: Resettable for IntfMagthresh6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH1 (rw) register accessor: INTF_MAGDIFFTHRESH1\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh1`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH1")]
pub type IntfMagdiffthresh1 = crate :: Reg < intf_magdiffthresh1 :: IntfMagdiffthresh1Spec > ; # [doc = "INTF_MAGDIFFTHRESH1"]
pub mod intf_magdiffthresh1 { # [doc = "Register `INTF_MAGDIFFTHRESH1` reader"]
pub type R = crate :: R < IntfMagdiffthresh1Spec > ; # [doc = "Register `INTF_MAGDIFFTHRESH1` writer"]
pub type W = crate :: W < IntfMagdiffthresh1Spec > ; # [doc = "Field `INTF_MAGDIFFTHRESH1` reader - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =0"]
pub type IntfMagdiffthresh1R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH1` writer - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =0"]
pub type IntfMagdiffthresh1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =0"]
# [inline (always)]
pub fn intf_magdiffthresh1 (& self) -> IntfMagdiffthresh1R { IntfMagdiffthresh1R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =0"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh1 (& mut self) -> IntfMagdiffthresh1W < IntfMagdiffthresh1Spec > { IntfMagdiffthresh1W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh1Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH1\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh1Spec ; impl crate :: RegisterSpec for IntfMagdiffthresh1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh1::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh1Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh1::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH1 to value 0"]
impl crate :: Resettable for IntfMagdiffthresh1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH2 (rw) register accessor: INTF_MAGDIFFTHRESH2\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh2`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH2")]
pub type IntfMagdiffthresh2 = crate :: Reg < intf_magdiffthresh2 :: IntfMagdiffthresh2Spec > ; # [doc = "INTF_MAGDIFFTHRESH2"]
pub mod intf_magdiffthresh2 { # [doc = "Register `INTF_MAGDIFFTHRESH2` reader"]
pub type R = crate :: R < IntfMagdiffthresh2Spec > ; # [doc = "Register `INTF_MAGDIFFTHRESH2` writer"]
pub type W = crate :: W < IntfMagdiffthresh2Spec > ; # [doc = "Field `INTF_MAGDIFFTHRESH2` reader - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =1"]
pub type IntfMagdiffthresh2R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH2` writer - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =1"]
pub type IntfMagdiffthresh2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =1"]
# [inline (always)]
pub fn intf_magdiffthresh2 (& self) -> IntfMagdiffthresh2R { IntfMagdiffthresh2R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =1"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh2 (& mut self) -> IntfMagdiffthresh2W < IntfMagdiffthresh2Spec > { IntfMagdiffthresh2W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh2Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH2\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh2Spec ; impl crate :: RegisterSpec for IntfMagdiffthresh2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh2::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh2Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh2::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH2 to value 0"]
impl crate :: Resettable for IntfMagdiffthresh2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH3 (rw) register accessor: INTF_MAGDIFFTHRESH3\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh3`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH3")]
pub type IntfMagdiffthresh3 = crate :: Reg < intf_magdiffthresh3 :: IntfMagdiffthresh3Spec > ; # [doc = "INTF_MAGDIFFTHRESH3"]
pub mod intf_magdiffthresh3 { # [doc = "Register `INTF_MAGDIFFTHRESH3` reader"]
pub type R = crate :: R < IntfMagdiffthresh3Spec > ; # [doc = "Register `INTF_MAGDIFFTHRESH3` writer"]
pub type W = crate :: W < IntfMagdiffthresh3Spec > ; # [doc = "Field `INTF_MAGDIFFTHRESH3` reader - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =2"]
pub type IntfMagdiffthresh3R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH3` writer - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =2"]
pub type IntfMagdiffthresh3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =2"]
# [inline (always)]
pub fn intf_magdiffthresh3 (& self) -> IntfMagdiffthresh3R { IntfMagdiffthresh3R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =2"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh3 (& mut self) -> IntfMagdiffthresh3W < IntfMagdiffthresh3Spec > { IntfMagdiffthresh3W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh3Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH3\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh3Spec ; impl crate :: RegisterSpec for IntfMagdiffthresh3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh3::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh3Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh3::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH3 to value 0"]
impl crate :: Resettable for IntfMagdiffthresh3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH4 (rw) register accessor: INTF_MAGDIFFTHRESH4\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh4`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH4")]
pub type IntfMagdiffthresh4 = crate :: Reg < intf_magdiffthresh4 :: IntfMagdiffthresh4Spec > ; # [doc = "INTF_MAGDIFFTHRESH4"]
pub mod intf_magdiffthresh4 { # [doc = "Register `INTF_MAGDIFFTHRESH4` reader"]
pub type R = crate :: R < IntfMagdiffthresh4Spec > ; # [doc = "Register `INTF_MAGDIFFTHRESH4` writer"]
pub type W = crate :: W < IntfMagdiffthresh4Spec > ; # [doc = "Field `INTF_MAGDIFFTHRESH4` reader - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =3"]
pub type IntfMagdiffthresh4R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH4` writer - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =3"]
pub type IntfMagdiffthresh4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =3"]
# [inline (always)]
pub fn intf_magdiffthresh4 (& self) -> IntfMagdiffthresh4R { IntfMagdiffthresh4R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =3"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh4 (& mut self) -> IntfMagdiffthresh4W < IntfMagdiffthresh4Spec > { IntfMagdiffthresh4W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh4Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH4\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh4Spec ; impl crate :: RegisterSpec for IntfMagdiffthresh4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh4::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh4Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh4::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH4 to value 0"]
impl crate :: Resettable for IntfMagdiffthresh4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH5 (rw) register accessor: INTF_MAGDIFFTHRESH5\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh5`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH5")]
pub type IntfMagdiffthresh5 = crate :: Reg < intf_magdiffthresh5 :: IntfMagdiffthresh5Spec > ; # [doc = "INTF_MAGDIFFTHRESH5"]
pub mod intf_magdiffthresh5 { # [doc = "Register `INTF_MAGDIFFTHRESH5` reader"]
pub type R = crate :: R < IntfMagdiffthresh5Spec > ; # [doc = "Register `INTF_MAGDIFFTHRESH5` writer"]
pub type W = crate :: W < IntfMagdiffthresh5Spec > ; # [doc = "Field `INTF_MAGDIFFTHRESH5` reader - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =4"]
pub type IntfMagdiffthresh5R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH5` writer - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =4"]
pub type IntfMagdiffthresh5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =4"]
# [inline (always)]
pub fn intf_magdiffthresh5 (& self) -> IntfMagdiffthresh5R { IntfMagdiffthresh5R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =4"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh5 (& mut self) -> IntfMagdiffthresh5W < IntfMagdiffthresh5Spec > { IntfMagdiffthresh5W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh5Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH5\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh5Spec ; impl crate :: RegisterSpec for IntfMagdiffthresh5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh5::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh5Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh5::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH5 to value 0"]
impl crate :: Resettable for IntfMagdiffthresh5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH6 (rw) register accessor: INTF_MAGDIFFTHRESH6\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh6`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH6")]
pub type IntfMagdiffthresh6 = crate :: Reg < intf_magdiffthresh6 :: IntfMagdiffthresh6Spec > ; # [doc = "INTF_MAGDIFFTHRESH6"]
pub mod intf_magdiffthresh6 { # [doc = "Register `INTF_MAGDIFFTHRESH6` reader"]
pub type R = crate :: R < IntfMagdiffthresh6Spec > ; # [doc = "Register `INTF_MAGDIFFTHRESH6` writer"]
pub type W = crate :: W < IntfMagdiffthresh6Spec > ; # [doc = "Field `INTF_MAGDIFFTHRESH6` reader - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =5"]
pub type IntfMagdiffthresh6R = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_MAGDIFFTHRESH6` writer - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =5"]
pub type IntfMagdiffthresh6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =5"]
# [inline (always)]
pub fn intf_magdiffthresh6 (& self) -> IntfMagdiffthresh6R { IntfMagdiffthresh6R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates interference magnitude difference threshold by interference statistics for bcnt =5"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh6 (& mut self) -> IntfMagdiffthresh6W < IntfMagdiffthresh6Spec > { IntfMagdiffthresh6W :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh6Spec > { Nu1W :: new (self , 24) } } # [doc = "INTF_MAGDIFFTHRESH6\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh6Spec ; impl crate :: RegisterSpec for IntfMagdiffthresh6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh6::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh6Spec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh6::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH6 to value 0"]
impl crate :: Resettable for IntfMagdiffthresh6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_SUMMAGTHRESH (rw) register accessor: INTF_SUMMAGTHRESH\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagthresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagthresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_summagthresh`]
module"]
# [doc (alias = "INTF_SUMMAGTHRESH")]
pub type IntfSummagthresh = crate :: Reg < intf_summagthresh :: IntfSummagthreshSpec > ; # [doc = "INTF_SUMMAGTHRESH"]
pub mod intf_summagthresh { # [doc = "Register `INTF_SUMMAGTHRESH` reader"]
pub type R = crate :: R < IntfSummagthreshSpec > ; # [doc = "Register `INTF_SUMMAGTHRESH` writer"]
pub type W = crate :: W < IntfSummagthreshSpec > ; # [doc = "Field `INTF_SUMMAGTHRESH` reader - 23:0\\]
Indicates the sum of mag values ; only Configured BCNT mag values are added"]
pub type IntfSummagthreshR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_SUMMAGTHRESH` writer - 23:0\\]
Indicates the sum of mag values ; only Configured BCNT mag values are added"]
pub type IntfSummagthreshW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates the sum of mag values ; only Configured BCNT mag values are added"]
# [inline (always)]
pub fn intf_summagthresh (& self) -> IntfSummagthreshR { IntfSummagthreshR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates the sum of mag values ; only Configured BCNT mag values are added"]
# [inline (always)]
# [must_use]
pub fn intf_summagthresh (& mut self) -> IntfSummagthreshW < IntfSummagthreshSpec > { IntfSummagthreshW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfSummagthreshSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_SUMMAGTHRESH\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagthresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagthresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfSummagthreshSpec ; impl crate :: RegisterSpec for IntfSummagthreshSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_summagthresh::R`](R) reader structure"]
impl crate :: Readable for IntfSummagthreshSpec { } # [doc = "`write(|w| ..)` method takes [`intf_summagthresh::W`](W) writer structure"]
impl crate :: Writable for IntfSummagthreshSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_SUMMAGTHRESH to value 0"]
impl crate :: Resettable for IntfSummagthreshSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_SUMMAGDIFFTHRESH (rw) register accessor: INTF_SUMMAGDIFFTHRESH\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagdiffthresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagdiffthresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_summagdiffthresh`]
module"]
# [doc (alias = "INTF_SUMMAGDIFFTHRESH")]
pub type IntfSummagdiffthresh = crate :: Reg < intf_summagdiffthresh :: IntfSummagdiffthreshSpec > ; # [doc = "INTF_SUMMAGDIFFTHRESH"]
pub mod intf_summagdiffthresh { # [doc = "Register `INTF_SUMMAGDIFFTHRESH` reader"]
pub type R = crate :: R < IntfSummagdiffthreshSpec > ; # [doc = "Register `INTF_SUMMAGDIFFTHRESH` writer"]
pub type W = crate :: W < IntfSummagdiffthreshSpec > ; # [doc = "Field `INTF_SUMMAGDIFFTHRESH` reader - 23:0\\]
Indicates the sum of magdiff values ; only Configured BCNT magdiff values are added"]
pub type IntfSummagdiffthreshR = crate :: FieldReader < u32 > ; # [doc = "Field `INTF_SUMMAGDIFFTHRESH` writer - 23:0\\]
Indicates the sum of magdiff values ; only Configured BCNT magdiff values are added"]
pub type IntfSummagdiffthreshW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
Indicates the sum of magdiff values ; only Configured BCNT magdiff values are added"]
# [inline (always)]
pub fn intf_summagdiffthresh (& self) -> IntfSummagdiffthreshR { IntfSummagdiffthreshR :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
Indicates the sum of magdiff values ; only Configured BCNT magdiff values are added"]
# [inline (always)]
# [must_use]
pub fn intf_summagdiffthresh (& mut self) -> IntfSummagdiffthreshW < IntfSummagdiffthreshSpec > { IntfSummagdiffthreshW :: new (self , 0) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfSummagdiffthreshSpec > { Nu1W :: new (self , 24) } } # [doc = "INTF_SUMMAGDIFFTHRESH\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagdiffthresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagdiffthresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfSummagdiffthreshSpec ; impl crate :: RegisterSpec for IntfSummagdiffthreshSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_summagdiffthresh::R`](R) reader structure"]
impl crate :: Readable for IntfSummagdiffthreshSpec { } # [doc = "`write(|w| ..)` method takes [`intf_summagdiffthresh::W`](W) writer structure"]
impl crate :: Writable for IntfSummagdiffthreshSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_SUMMAGDIFFTHRESH to value 0"]
impl crate :: Resettable for IntfSummagdiffthreshSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_SUMMAGTHRESH_CLIP (rw) register accessor: INTF_SUMMAGTHRESH_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagthresh_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagthresh_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_summagthresh_clip`]
module"]
# [doc (alias = "INTF_SUMMAGTHRESH_CLIP")]
pub type IntfSummagthreshClip = crate :: Reg < intf_summagthresh_clip :: IntfSummagthreshClipSpec > ; # [doc = "INTF_SUMMAGTHRESH_CLIP"]
pub mod intf_summagthresh_clip { # [doc = "Register `INTF_SUMMAGTHRESH_CLIP` reader"]
pub type R = crate :: R < IntfSummagthreshClipSpec > ; # [doc = "Register `INTF_SUMMAGTHRESH_CLIP` writer"]
pub type W = crate :: W < IntfSummagthreshClipSpec > ; # [doc = "Field `INTF_SUMMAGTHRESH_CLIP` reader - 0:0\\]
Indicates the clip status of sum of magnitude threshold values"]
pub type IntfSummagthreshClipR = crate :: BitReader ; # [doc = "Field `INTF_SUMMAGTHRESH_CLIP` writer - 0:0\\]
Indicates the clip status of sum of magnitude threshold values"]
pub type IntfSummagthreshClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the clip status of sum of magnitude threshold values"]
# [inline (always)]
pub fn intf_summagthresh_clip (& self) -> IntfSummagthreshClipR { IntfSummagthreshClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the clip status of sum of magnitude threshold values"]
# [inline (always)]
# [must_use]
pub fn intf_summagthresh_clip (& mut self) -> IntfSummagthreshClipW < IntfSummagthreshClipSpec > { IntfSummagthreshClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfSummagthreshClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_SUMMAGTHRESH_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagthresh_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagthresh_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfSummagthreshClipSpec ; impl crate :: RegisterSpec for IntfSummagthreshClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_summagthresh_clip::R`](R) reader structure"]
impl crate :: Readable for IntfSummagthreshClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_summagthresh_clip::W`](W) writer structure"]
impl crate :: Writable for IntfSummagthreshClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_SUMMAGTHRESH_CLIP to value 0"]
impl crate :: Resettable for IntfSummagthreshClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_SUMMAGDIFFTHRESH_CLIP (rw) register accessor: INTF_SUMMAGDIFFTHRESH_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagdiffthresh_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagdiffthresh_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_summagdiffthresh_clip`]
module"]
# [doc (alias = "INTF_SUMMAGDIFFTHRESH_CLIP")]
pub type IntfSummagdiffthreshClip = crate :: Reg < intf_summagdiffthresh_clip :: IntfSummagdiffthreshClipSpec > ; # [doc = "INTF_SUMMAGDIFFTHRESH_CLIP"]
pub mod intf_summagdiffthresh_clip { # [doc = "Register `INTF_SUMMAGDIFFTHRESH_CLIP` reader"]
pub type R = crate :: R < IntfSummagdiffthreshClipSpec > ; # [doc = "Register `INTF_SUMMAGDIFFTHRESH_CLIP` writer"]
pub type W = crate :: W < IntfSummagdiffthreshClipSpec > ; # [doc = "Field `INTF_SUMMAGDIFFTHRESH_CLIP` reader - 0:0\\]
Indicates the clip status of sum of magnitude difference threshold values"]
pub type IntfSummagdiffthreshClipR = crate :: BitReader ; # [doc = "Field `INTF_SUMMAGDIFFTHRESH_CLIP` writer - 0:0\\]
Indicates the clip status of sum of magnitude difference threshold values"]
pub type IntfSummagdiffthreshClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the clip status of sum of magnitude difference threshold values"]
# [inline (always)]
pub fn intf_summagdiffthresh_clip (& self) -> IntfSummagdiffthreshClipR { IntfSummagdiffthreshClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the clip status of sum of magnitude difference threshold values"]
# [inline (always)]
# [must_use]
pub fn intf_summagdiffthresh_clip (& mut self) -> IntfSummagdiffthreshClipW < IntfSummagdiffthreshClipSpec > { IntfSummagdiffthreshClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfSummagdiffthreshClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_SUMMAGDIFFTHRESH_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_summagdiffthresh_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_summagdiffthresh_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfSummagdiffthreshClipSpec ; impl crate :: RegisterSpec for IntfSummagdiffthreshClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_summagdiffthresh_clip::R`](R) reader structure"]
impl crate :: Readable for IntfSummagdiffthreshClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_summagdiffthresh_clip::W`](W) writer structure"]
impl crate :: Writable for IntfSummagdiffthreshClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_SUMMAGDIFFTHRESH_CLIP to value 0"]
impl crate :: Resettable for IntfSummagdiffthreshClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE1I (rw) register accessor: CMULTSCALE1I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale1i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale1i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale1i`]
module"]
# [doc (alias = "CMULTSCALE1I")]
pub type Cmultscale1i = crate :: Reg < cmultscale1i :: Cmultscale1iSpec > ; # [doc = "CMULTSCALE1I"]
pub mod cmultscale1i { # [doc = "Register `CMULTSCALE1I` reader"]
pub type R = crate :: R < Cmultscale1iSpec > ; # [doc = "Register `CMULTSCALE1I` writer"]
pub type W = crate :: W < Cmultscale1iSpec > ; # [doc = "Field `CMULTSCALE1I` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale1iR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE1I` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale1iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale1i (& self) -> Cmultscale1iR { Cmultscale1iR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale1i (& mut self) -> Cmultscale1iW < Cmultscale1iSpec > { Cmultscale1iW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Cmultscale1iSpec > { NuW :: new (self , 21) } } # [doc = "CMULTSCALE1I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale1i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale1i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale1iSpec ; impl crate :: RegisterSpec for Cmultscale1iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale1i::R`](R) reader structure"]
impl crate :: Readable for Cmultscale1iSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale1i::W`](W) writer structure"]
impl crate :: Writable for Cmultscale1iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE1I to value 0"]
impl crate :: Resettable for Cmultscale1iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE2I (rw) register accessor: CMULTSCALE2I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale2i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale2i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale2i`]
module"]
# [doc (alias = "CMULTSCALE2I")]
pub type Cmultscale2i = crate :: Reg < cmultscale2i :: Cmultscale2iSpec > ; # [doc = "CMULTSCALE2I"]
pub mod cmultscale2i { # [doc = "Register `CMULTSCALE2I` reader"]
pub type R = crate :: R < Cmultscale2iSpec > ; # [doc = "Register `CMULTSCALE2I` writer"]
pub type W = crate :: W < Cmultscale2iSpec > ; # [doc = "Field `CMULTSCALE2I` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale2iR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE2I` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale2iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale2i (& self) -> Cmultscale2iR { Cmultscale2iR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale2i (& mut self) -> Cmultscale2iW < Cmultscale2iSpec > { Cmultscale2iW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale2iSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE2I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale2i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale2i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale2iSpec ; impl crate :: RegisterSpec for Cmultscale2iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale2i::R`](R) reader structure"]
impl crate :: Readable for Cmultscale2iSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale2i::W`](W) writer structure"]
impl crate :: Writable for Cmultscale2iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE2I to value 0"]
impl crate :: Resettable for Cmultscale2iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE3I (rw) register accessor: CMULTSCALE3I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale3i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale3i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale3i`]
module"]
# [doc (alias = "CMULTSCALE3I")]
pub type Cmultscale3i = crate :: Reg < cmultscale3i :: Cmultscale3iSpec > ; # [doc = "CMULTSCALE3I"]
pub mod cmultscale3i { # [doc = "Register `CMULTSCALE3I` reader"]
pub type R = crate :: R < Cmultscale3iSpec > ; # [doc = "Register `CMULTSCALE3I` writer"]
pub type W = crate :: W < Cmultscale3iSpec > ; # [doc = "Field `CMULTSCALE3I` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale3iR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE3I` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale3iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale3i (& self) -> Cmultscale3iR { Cmultscale3iR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale3i (& mut self) -> Cmultscale3iW < Cmultscale3iSpec > { Cmultscale3iW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale3iSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE3I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale3i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale3i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale3iSpec ; impl crate :: RegisterSpec for Cmultscale3iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale3i::R`](R) reader structure"]
impl crate :: Readable for Cmultscale3iSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale3i::W`](W) writer structure"]
impl crate :: Writable for Cmultscale3iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE3I to value 0"]
impl crate :: Resettable for Cmultscale3iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE4I (rw) register accessor: CMULTSCALE4I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale4i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale4i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale4i`]
module"]
# [doc (alias = "CMULTSCALE4I")]
pub type Cmultscale4i = crate :: Reg < cmultscale4i :: Cmultscale4iSpec > ; # [doc = "CMULTSCALE4I"]
pub mod cmultscale4i { # [doc = "Register `CMULTSCALE4I` reader"]
pub type R = crate :: R < Cmultscale4iSpec > ; # [doc = "Register `CMULTSCALE4I` writer"]
pub type W = crate :: W < Cmultscale4iSpec > ; # [doc = "Field `CMULTSCALE4I` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale4iR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE4I` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale4iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale4i (& self) -> Cmultscale4iR { Cmultscale4iR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale4i (& mut self) -> Cmultscale4iW < Cmultscale4iSpec > { Cmultscale4iW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale4iSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE4I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale4i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale4i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale4iSpec ; impl crate :: RegisterSpec for Cmultscale4iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale4i::R`](R) reader structure"]
impl crate :: Readable for Cmultscale4iSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale4i::W`](W) writer structure"]
impl crate :: Writable for Cmultscale4iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE4I to value 0"]
impl crate :: Resettable for Cmultscale4iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE5I (rw) register accessor: CMULTSCALE5I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale5i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale5i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale5i`]
module"]
# [doc (alias = "CMULTSCALE5I")]
pub type Cmultscale5i = crate :: Reg < cmultscale5i :: Cmultscale5iSpec > ; # [doc = "CMULTSCALE5I"]
pub mod cmultscale5i { # [doc = "Register `CMULTSCALE5I` reader"]
pub type R = crate :: R < Cmultscale5iSpec > ; # [doc = "Register `CMULTSCALE5I` writer"]
pub type W = crate :: W < Cmultscale5iSpec > ; # [doc = "Field `CMULTSCALE5I` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale5iR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE5I` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale5iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale5i (& self) -> Cmultscale5iR { Cmultscale5iR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale5i (& mut self) -> Cmultscale5iW < Cmultscale5iSpec > { Cmultscale5iW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale5iSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE5I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale5i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale5i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale5iSpec ; impl crate :: RegisterSpec for Cmultscale5iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale5i::R`](R) reader structure"]
impl crate :: Readable for Cmultscale5iSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale5i::W`](W) writer structure"]
impl crate :: Writable for Cmultscale5iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE5I to value 0"]
impl crate :: Resettable for Cmultscale5iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE6I (rw) register accessor: CMULTSCALE6I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale6i::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale6i::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale6i`]
module"]
# [doc (alias = "CMULTSCALE6I")]
pub type Cmultscale6i = crate :: Reg < cmultscale6i :: Cmultscale6iSpec > ; # [doc = "CMULTSCALE6I"]
pub mod cmultscale6i { # [doc = "Register `CMULTSCALE6I` reader"]
pub type R = crate :: R < Cmultscale6iSpec > ; # [doc = "Register `CMULTSCALE6I` writer"]
pub type W = crate :: W < Cmultscale6iSpec > ; # [doc = "Field `CMULTSCALE6I` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale6iR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE6I` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale6iW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale6i (& self) -> Cmultscale6iR { Cmultscale6iR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale6i (& mut self) -> Cmultscale6iW < Cmultscale6iSpec > { Cmultscale6iW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale6iSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE6I\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale6i::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale6i::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale6iSpec ; impl crate :: RegisterSpec for Cmultscale6iSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale6i::R`](R) reader structure"]
impl crate :: Readable for Cmultscale6iSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale6i::W`](W) writer structure"]
impl crate :: Writable for Cmultscale6iSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE6I to value 0"]
impl crate :: Resettable for Cmultscale6iSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE1Q (rw) register accessor: CMULTSCALE1Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale1q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale1q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale1q`]
module"]
# [doc (alias = "CMULTSCALE1Q")]
pub type Cmultscale1q = crate :: Reg < cmultscale1q :: Cmultscale1qSpec > ; # [doc = "CMULTSCALE1Q"]
pub mod cmultscale1q { # [doc = "Register `CMULTSCALE1Q` reader"]
pub type R = crate :: R < Cmultscale1qSpec > ; # [doc = "Register `CMULTSCALE1Q` writer"]
pub type W = crate :: W < Cmultscale1qSpec > ; # [doc = "Field `CMULTSCALE1Q` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale1qR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE1Q` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale1qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU` reader - "]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - "]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale1q (& self) -> Cmultscale1qR { Cmultscale1qR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale1q (& mut self) -> Cmultscale1qW < Cmultscale1qSpec > { Cmultscale1qW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Cmultscale1qSpec > { NuW :: new (self , 21) } } # [doc = "CMULTSCALE1Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale1q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale1q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale1qSpec ; impl crate :: RegisterSpec for Cmultscale1qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale1q::R`](R) reader structure"]
impl crate :: Readable for Cmultscale1qSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale1q::W`](W) writer structure"]
impl crate :: Writable for Cmultscale1qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE1Q to value 0"]
impl crate :: Resettable for Cmultscale1qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE2Q (rw) register accessor: CMULTSCALE2Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale2q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale2q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale2q`]
module"]
# [doc (alias = "CMULTSCALE2Q")]
pub type Cmultscale2q = crate :: Reg < cmultscale2q :: Cmultscale2qSpec > ; # [doc = "CMULTSCALE2Q"]
pub mod cmultscale2q { # [doc = "Register `CMULTSCALE2Q` reader"]
pub type R = crate :: R < Cmultscale2qSpec > ; # [doc = "Register `CMULTSCALE2Q` writer"]
pub type W = crate :: W < Cmultscale2qSpec > ; # [doc = "Field `CMULTSCALE2Q` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale2qR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE2Q` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale2qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale2q (& self) -> Cmultscale2qR { Cmultscale2qR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale2q (& mut self) -> Cmultscale2qW < Cmultscale2qSpec > { Cmultscale2qW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale2qSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE2Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale2q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale2q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale2qSpec ; impl crate :: RegisterSpec for Cmultscale2qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale2q::R`](R) reader structure"]
impl crate :: Readable for Cmultscale2qSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale2q::W`](W) writer structure"]
impl crate :: Writable for Cmultscale2qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE2Q to value 0"]
impl crate :: Resettable for Cmultscale2qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE3Q (rw) register accessor: CMULTSCALE3Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale3q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale3q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale3q`]
module"]
# [doc (alias = "CMULTSCALE3Q")]
pub type Cmultscale3q = crate :: Reg < cmultscale3q :: Cmultscale3qSpec > ; # [doc = "CMULTSCALE3Q"]
pub mod cmultscale3q { # [doc = "Register `CMULTSCALE3Q` reader"]
pub type R = crate :: R < Cmultscale3qSpec > ; # [doc = "Register `CMULTSCALE3Q` writer"]
pub type W = crate :: W < Cmultscale3qSpec > ; # [doc = "Field `CMULTSCALE3Q` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale3qR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE3Q` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale3qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale3q (& self) -> Cmultscale3qR { Cmultscale3qR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale3q (& mut self) -> Cmultscale3qW < Cmultscale3qSpec > { Cmultscale3qW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale3qSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE3Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale3q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale3q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale3qSpec ; impl crate :: RegisterSpec for Cmultscale3qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale3q::R`](R) reader structure"]
impl crate :: Readable for Cmultscale3qSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale3q::W`](W) writer structure"]
impl crate :: Writable for Cmultscale3qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE3Q to value 0"]
impl crate :: Resettable for Cmultscale3qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE4Q (rw) register accessor: CMULTSCALE4Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale4q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale4q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale4q`]
module"]
# [doc (alias = "CMULTSCALE4Q")]
pub type Cmultscale4q = crate :: Reg < cmultscale4q :: Cmultscale4qSpec > ; # [doc = "CMULTSCALE4Q"]
pub mod cmultscale4q { # [doc = "Register `CMULTSCALE4Q` reader"]
pub type R = crate :: R < Cmultscale4qSpec > ; # [doc = "Register `CMULTSCALE4Q` writer"]
pub type W = crate :: W < Cmultscale4qSpec > ; # [doc = "Field `CMULTSCALE4Q` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale4qR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE4Q` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale4qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale4q (& self) -> Cmultscale4qR { Cmultscale4qR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale4q (& mut self) -> Cmultscale4qW < Cmultscale4qSpec > { Cmultscale4qW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale4qSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE4Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale4q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale4q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale4qSpec ; impl crate :: RegisterSpec for Cmultscale4qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale4q::R`](R) reader structure"]
impl crate :: Readable for Cmultscale4qSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale4q::W`](W) writer structure"]
impl crate :: Writable for Cmultscale4qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE4Q to value 0"]
impl crate :: Resettable for Cmultscale4qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE5Q (rw) register accessor: CMULTSCALE5Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale5q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale5q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale5q`]
module"]
# [doc (alias = "CMULTSCALE5Q")]
pub type Cmultscale5q = crate :: Reg < cmultscale5q :: Cmultscale5qSpec > ; # [doc = "CMULTSCALE5Q"]
pub mod cmultscale5q { # [doc = "Register `CMULTSCALE5Q` reader"]
pub type R = crate :: R < Cmultscale5qSpec > ; # [doc = "Register `CMULTSCALE5Q` writer"]
pub type W = crate :: W < Cmultscale5qSpec > ; # [doc = "Field `CMULTSCALE5Q` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale5qR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE5Q` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale5qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale5q (& self) -> Cmultscale5qR { Cmultscale5qR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale5q (& mut self) -> Cmultscale5qW < Cmultscale5qSpec > { Cmultscale5qW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale5qSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE5Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale5q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale5q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale5qSpec ; impl crate :: RegisterSpec for Cmultscale5qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale5q::R`](R) reader structure"]
impl crate :: Readable for Cmultscale5qSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale5q::W`](W) writer structure"]
impl crate :: Writable for Cmultscale5qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE5Q to value 0"]
impl crate :: Resettable for Cmultscale5qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMULTSCALE6Q (rw) register accessor: CMULTSCALE6Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale6q::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale6q::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmultscale6q`]
module"]
# [doc (alias = "CMULTSCALE6Q")]
pub type Cmultscale6q = crate :: Reg < cmultscale6q :: Cmultscale6qSpec > ; # [doc = "CMULTSCALE6Q"]
pub mod cmultscale6q { # [doc = "Register `CMULTSCALE6Q` reader"]
pub type R = crate :: R < Cmultscale6qSpec > ; # [doc = "Register `CMULTSCALE6Q` writer"]
pub type W = crate :: W < Cmultscale6qSpec > ; # [doc = "Field `CMULTSCALE6Q` reader - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale6qR = crate :: FieldReader < u32 > ; # [doc = "Field `CMULTSCALE6Q` writer - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
pub type Cmultscale6qW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
pub fn cmultscale6q (& self) -> Cmultscale6qR { Cmultscale6qR :: new (self . bits & 0x001f_ffff) } # [doc = "Bits 21:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 21) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:20 - 20:0\\]
In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations."]
# [inline (always)]
# [must_use]
pub fn cmultscale6q (& mut self) -> Cmultscale6qW < Cmultscale6qSpec > { Cmultscale6qW :: new (self , 0) } # [doc = "Bits 21:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < Cmultscale6qSpec > { Nu1W :: new (self , 21) } } # [doc = "CMULTSCALE6Q\n\nYou can [`read`](crate::Reg::read) this register and get [`cmultscale6q::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmultscale6q::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmultscale6qSpec ; impl crate :: RegisterSpec for Cmultscale6qSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmultscale6q::R`](R) reader structure"]
impl crate :: Readable for Cmultscale6qSpec { } # [doc = "`write(|w| ..)` method takes [`cmultscale6q::W`](W) writer structure"]
impl crate :: Writable for Cmultscale6qSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMULTSCALE6Q to value 0"]
impl crate :: Resettable for Cmultscale6qSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CLR_MISC_CLIP (rw) register accessor: CLR_MISC_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`clr_misc_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr_misc_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_misc_clip`]
module"]
# [doc (alias = "CLR_MISC_CLIP")]
pub type ClrMiscClip = crate :: Reg < clr_misc_clip :: ClrMiscClipSpec > ; # [doc = "CLR_MISC_CLIP"]
pub mod clr_misc_clip { # [doc = "Register `CLR_MISC_CLIP` reader"]
pub type R = crate :: R < ClrMiscClipSpec > ; # [doc = "Register `CLR_MISC_CLIP` writer"]
pub type W = crate :: W < ClrMiscClipSpec > ; # [doc = "Field `CLR_MISC_CLIP` reader - 0:0\\]
This clears the following clip register :- dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status Intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status intf_stats_thresh_magdiff_clip_status ip_formatter_clip_status op_formatter_clip_status intf_stats_sum_mag_val_clip_status intf_stats_sum_magdiff_val_clip_status Its a self clearing bit"]
pub type ClrMiscClipR = crate :: BitReader ; # [doc = "Field `CLR_MISC_CLIP` writer - 0:0\\]
This clears the following clip register :- dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status Intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status intf_stats_thresh_magdiff_clip_status ip_formatter_clip_status op_formatter_clip_status intf_stats_sum_mag_val_clip_status intf_stats_sum_magdiff_val_clip_status Its a self clearing bit"]
pub type ClrMiscClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
This clears the following clip register :- dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status Intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status intf_stats_thresh_magdiff_clip_status ip_formatter_clip_status op_formatter_clip_status intf_stats_sum_mag_val_clip_status intf_stats_sum_magdiff_val_clip_status Its a self clearing bit"]
# [inline (always)]
pub fn clr_misc_clip (& self) -> ClrMiscClipR { ClrMiscClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
This clears the following clip register :- dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status Intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status intf_stats_thresh_magdiff_clip_status ip_formatter_clip_status op_formatter_clip_status intf_stats_sum_mag_val_clip_status intf_stats_sum_magdiff_val_clip_status Its a self clearing bit"]
# [inline (always)]
# [must_use]
pub fn clr_misc_clip (& mut self) -> ClrMiscClipW < ClrMiscClipSpec > { ClrMiscClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < ClrMiscClipSpec > { Nu1W :: new (self , 1) } } # [doc = "CLR_MISC_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`clr_misc_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr_misc_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClrMiscClipSpec ; impl crate :: RegisterSpec for ClrMiscClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`clr_misc_clip::R`](R) reader structure"]
impl crate :: Readable for ClrMiscClipSpec { } # [doc = "`write(|w| ..)` method takes [`clr_misc_clip::W`](W) writer structure"]
impl crate :: Writable for ClrMiscClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CLR_MISC_CLIP to value 0"]
impl crate :: Resettable for ClrMiscClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FFTINTMEMADDR (rw) register accessor: FFTINTMEMADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`fftintmemaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftintmemaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fftintmemaddr`]
module"]
# [doc (alias = "FFTINTMEMADDR")]
pub type Fftintmemaddr = crate :: Reg < fftintmemaddr :: FftintmemaddrSpec > ; # [doc = "FFTINTMEMADDR"]
pub mod fftintmemaddr { # [doc = "Register `FFTINTMEMADDR` reader"]
pub type R = crate :: R < FftintmemaddrSpec > ; # [doc = "Register `FFTINTMEMADDR` writer"]
pub type W = crate :: W < FftintmemaddrSpec > ; # [doc = "Field `FFT_INT_MEM_ADDR` reader - 8:0\\]
Reserved.TI internal"]
pub type FftIntMemAddrR = crate :: FieldReader < u16 > ; # [doc = "Field `FFT_INT_MEM_ADDR` writer - 8:0\\]
Reserved.TI internal"]
pub type FftIntMemAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `FFT_INT_MEM_SEL` reader - 11:9\\]
Reserved.TI internal"]
pub type FftIntMemSelR = crate :: FieldReader ; # [doc = "Field `FFT_INT_MEM_SEL` writer - 11:9\\]
Reserved.TI internal"]
pub type FftIntMemSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU1` reader - 15:12\\]
Reserved.TI internal"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 15:12\\]
Reserved.TI internal"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `FFT_INT_MEM_EN` reader - 16:16\\]
Reserved.TI internal"]
pub type FftIntMemEnR = crate :: BitReader ; # [doc = "Field `FFT_INT_MEM_EN` writer - 16:16\\]
Reserved.TI internal"]
pub type FftIntMemEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 23:17\\]
Reserved.TI internal"]
pub type Nu2R = crate :: FieldReader ; # [doc = "Field `NU2` writer - 23:17\\]
Reserved.TI internal"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `FFT_INT_MEM_RD` reader - 24:24\\]
Reserved.TI internal"]
pub type FftIntMemRdR = crate :: BitReader ; # [doc = "Field `FFT_INT_MEM_RD` writer - 24:24\\]
Reserved.TI internal"]
pub type FftIntMemRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU3` reader - 31:25\\]
Reserved.TI internal"]
pub type Nu3R = crate :: FieldReader ; # [doc = "Field `NU3` writer - 31:25\\]
Reserved.TI internal"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:8 - 8:0\\]
Reserved.TI internal"]
# [inline (always)]
pub fn fft_int_mem_addr (& self) -> FftIntMemAddrR { FftIntMemAddrR :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bits 9:11 - 11:9\\]
Reserved.TI internal"]
# [inline (always)]
pub fn fft_int_mem_sel (& self) -> FftIntMemSelR { FftIntMemSelR :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
Reserved.TI internal"]
# [inline (always)]
pub fn fft_int_mem_en (& self) -> FftIntMemEnR { FftIntMemEnR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:23 - 23:17\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 17) & 0x7f) as u8) } # [doc = "Bit 24 - 24:24\\]
Reserved.TI internal"]
# [inline (always)]
pub fn fft_int_mem_rd (& self) -> FftIntMemRdR { FftIntMemRdR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
Reserved.TI internal"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:8 - 8:0\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn fft_int_mem_addr (& mut self) -> FftIntMemAddrW < FftintmemaddrSpec > { FftIntMemAddrW :: new (self , 0) } # [doc = "Bits 9:11 - 11:9\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn fft_int_mem_sel (& mut self) -> FftIntMemSelW < FftintmemaddrSpec > { FftIntMemSelW :: new (self , 9) } # [doc = "Bits 12:15 - 15:12\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < FftintmemaddrSpec > { Nu1W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn fft_int_mem_en (& mut self) -> FftIntMemEnW < FftintmemaddrSpec > { FftIntMemEnW :: new (self , 16) } # [doc = "Bits 17:23 - 23:17\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < FftintmemaddrSpec > { Nu2W :: new (self , 17) } # [doc = "Bit 24 - 24:24\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn fft_int_mem_rd (& mut self) -> FftIntMemRdW < FftintmemaddrSpec > { FftIntMemRdW :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
Reserved.TI internal"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < FftintmemaddrSpec > { Nu3W :: new (self , 25) } } # [doc = "FFTINTMEMADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`fftintmemaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fftintmemaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FftintmemaddrSpec ; impl crate :: RegisterSpec for FftintmemaddrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fftintmemaddr::R`](R) reader structure"]
impl crate :: Readable for FftintmemaddrSpec { } # [doc = "`write(|w| ..)` method takes [`fftintmemaddr::W`](W) writer structure"]
impl crate :: Writable for FftintmemaddrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FFTINTMEMADDR to value 0"]
impl crate :: Resettable for FftintmemaddrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_STATS_RESET_SW (rw) register accessor: INTF_STATS_RESET_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_stats_reset_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_stats_reset_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_stats_reset_sw`]
module"]
# [doc (alias = "INTF_STATS_RESET_SW")]
pub type IntfStatsResetSw = crate :: Reg < intf_stats_reset_sw :: IntfStatsResetSwSpec > ; # [doc = "INTF_STATS_RESET_SW"]
pub mod intf_stats_reset_sw { # [doc = "Register `INTF_STATS_RESET_SW` reader"]
pub type R = crate :: R < IntfStatsResetSwSpec > ; # [doc = "Register `INTF_STATS_RESET_SW` writer"]
pub type W = crate :: W < IntfStatsResetSwSpec > ; # [doc = "Field `INTF_STATS_RESET_SW` reader - 0:0\\]
SW reset for Interference statistics module. Its a self clearing bit."]
pub type IntfStatsResetSwR = crate :: BitReader ; # [doc = "Field `INTF_STATS_RESET_SW` writer - 0:0\\]
SW reset for Interference statistics module. Its a self clearing bit."]
pub type IntfStatsResetSwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SW reset for Interference statistics module. Its a self clearing bit."]
# [inline (always)]
pub fn intf_stats_reset_sw (& self) -> IntfStatsResetSwR { IntfStatsResetSwR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
SW reset for Interference statistics module. Its a self clearing bit."]
# [inline (always)]
# [must_use]
pub fn intf_stats_reset_sw (& mut self) -> IntfStatsResetSwW < IntfStatsResetSwSpec > { IntfStatsResetSwW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfStatsResetSwSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_STATS_RESET_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_stats_reset_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_stats_reset_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfStatsResetSwSpec ; impl crate :: RegisterSpec for IntfStatsResetSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_stats_reset_sw::R`](R) reader structure"]
impl crate :: Readable for IntfStatsResetSwSpec { } # [doc = "`write(|w| ..)` method takes [`intf_stats_reset_sw::W`](W) writer structure"]
impl crate :: Writable for IntfStatsResetSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_STATS_RESET_SW to value 0"]
impl crate :: Resettable for IntfStatsResetSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCEST_RESET_SW (rw) register accessor: DCEST_RESET_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest_reset_sw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest_reset_sw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcest_reset_sw`]
module"]
# [doc (alias = "DCEST_RESET_SW")]
pub type DcestResetSw = crate :: Reg < dcest_reset_sw :: DcestResetSwSpec > ; # [doc = "DCEST_RESET_SW"]
pub mod dcest_reset_sw { # [doc = "Register `DCEST_RESET_SW` reader"]
pub type R = crate :: R < DcestResetSwSpec > ; # [doc = "Register `DCEST_RESET_SW` writer"]
pub type W = crate :: W < DcestResetSwSpec > ; # [doc = "Field `DCEST_RESET_SW` reader - 0:0\\]
Reset for all 6 DC estimation accumulators.Its a self clearing bit."]
pub type DcestResetSwR = crate :: BitReader ; # [doc = "Field `DCEST_RESET_SW` writer - 0:0\\]
Reset for all 6 DC estimation accumulators.Its a self clearing bit."]
pub type DcestResetSwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reset for all 6 DC estimation accumulators.Its a self clearing bit."]
# [inline (always)]
pub fn dcest_reset_sw (& self) -> DcestResetSwR { DcestResetSwR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reset for all 6 DC estimation accumulators.Its a self clearing bit."]
# [inline (always)]
# [must_use]
pub fn dcest_reset_sw (& mut self) -> DcestResetSwW < DcestResetSwSpec > { DcestResetSwW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DcestResetSwSpec > { Nu1W :: new (self , 1) } } # [doc = "DCEST_RESET_SW\n\nYou can [`read`](crate::Reg::read) this register and get [`dcest_reset_sw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcest_reset_sw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcestResetSwSpec ; impl crate :: RegisterSpec for DcestResetSwSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcest_reset_sw::R`](R) reader structure"]
impl crate :: Readable for DcestResetSwSpec { } # [doc = "`write(|w| ..)` method takes [`dcest_reset_sw::W`](W) writer structure"]
impl crate :: Writable for DcestResetSwSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCEST_RESET_SW to value 0"]
impl crate :: Resettable for DcestResetSwSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IP_OP_FORMATTER_CLIP_STATUS (rw) register accessor: IP_OP_FORMATTER_CLIP_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ip_op_formatter_clip_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ip_op_formatter_clip_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ip_op_formatter_clip_status`]
module"]
# [doc (alias = "IP_OP_FORMATTER_CLIP_STATUS")]
pub type IpOpFormatterClipStatus = crate :: Reg < ip_op_formatter_clip_status :: IpOpFormatterClipStatusSpec > ; # [doc = "IP_OP_FORMATTER_CLIP_STATUS"]
pub mod ip_op_formatter_clip_status { # [doc = "Register `IP_OP_FORMATTER_CLIP_STATUS` reader"]
pub type R = crate :: R < IpOpFormatterClipStatusSpec > ; # [doc = "Register `IP_OP_FORMATTER_CLIP_STATUS` writer"]
pub type W = crate :: W < IpOpFormatterClipStatusSpec > ; # [doc = "Field `IP_FORMATTER_CLIP_STATUS` reader - 0:0\\]
Indicates input formatter clip status"]
pub type IpFormatterClipStatusR = crate :: BitReader ; # [doc = "Field `IP_FORMATTER_CLIP_STATUS` writer - 0:0\\]
Indicates input formatter clip status"]
pub type IpFormatterClipStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u16 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; # [doc = "Field `OP_FORMATTER_CLIP_STATUS` reader - 16:16\\]
Indicates output formatter clip status"]
pub type OpFormatterClipStatusR = crate :: BitReader ; # [doc = "Field `OP_FORMATTER_CLIP_STATUS` writer - 16:16\\]
Indicates output formatter clip status"]
pub type OpFormatterClipStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - "]
pub type Nu2R = crate :: FieldReader < u16 > ; # [doc = "Field `NU2` writer - "]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates input formatter clip status"]
# [inline (always)]
pub fn ip_formatter_clip_status (& self) -> IpFormatterClipStatusR { IpFormatterClipStatusR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:15"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 1) & 0x7fff) as u16) } # [doc = "Bit 16 - 16:16\\]
Indicates output formatter clip status"]
# [inline (always)]
pub fn op_formatter_clip_status (& self) -> OpFormatterClipStatusR { OpFormatterClipStatusR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates input formatter clip status"]
# [inline (always)]
# [must_use]
pub fn ip_formatter_clip_status (& mut self) -> IpFormatterClipStatusW < IpOpFormatterClipStatusSpec > { IpFormatterClipStatusW :: new (self , 0) } # [doc = "Bits 1:15"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IpOpFormatterClipStatusSpec > { Nu1W :: new (self , 1) } # [doc = "Bit 16 - 16:16\\]
Indicates output formatter clip status"]
# [inline (always)]
# [must_use]
pub fn op_formatter_clip_status (& mut self) -> OpFormatterClipStatusW < IpOpFormatterClipStatusSpec > { OpFormatterClipStatusW :: new (self , 16) } # [doc = "Bits 17:31"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < IpOpFormatterClipStatusSpec > { Nu2W :: new (self , 17) } } # [doc = "IP_OP_FORMATTER_CLIP_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ip_op_formatter_clip_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ip_op_formatter_clip_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IpOpFormatterClipStatusSpec ; impl crate :: RegisterSpec for IpOpFormatterClipStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ip_op_formatter_clip_status::R`](R) reader structure"]
impl crate :: Readable for IpOpFormatterClipStatusSpec { } # [doc = "`write(|w| ..)` method takes [`ip_op_formatter_clip_status::W`](W) writer structure"]
impl crate :: Writable for IpOpFormatterClipStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IP_OP_FORMATTER_CLIP_STATUS to value 0"]
impl crate :: Resettable for IpOpFormatterClipStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH1_CLIP (rw) register accessor: INTF_MAGTHRESH1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh1_clip`]
module"]
# [doc (alias = "INTF_MAGTHRESH1_CLIP")]
pub type IntfMagthresh1Clip = crate :: Reg < intf_magthresh1_clip :: IntfMagthresh1ClipSpec > ; # [doc = "INTF_MAGTHRESH1_CLIP"]
pub mod intf_magthresh1_clip { # [doc = "Register `INTF_MAGTHRESH1_CLIP` reader"]
pub type R = crate :: R < IntfMagthresh1ClipSpec > ; # [doc = "Register `INTF_MAGTHRESH1_CLIP` writer"]
pub type W = crate :: W < IntfMagthresh1ClipSpec > ; # [doc = "Field `INTF_MAGTHRESH1_CLIP` reader - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh1ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGTHRESH1_CLIP` writer - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
pub fn intf_magthresh1_clip (& self) -> IntfMagthresh1ClipR { IntfMagthresh1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh1_clip (& mut self) -> IntfMagthresh1ClipW < IntfMagthresh1ClipSpec > { IntfMagthresh1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGTHRESH1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh1ClipSpec ; impl crate :: RegisterSpec for IntfMagthresh1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh1_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh1_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH1_CLIP to value 0"]
impl crate :: Resettable for IntfMagthresh1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH2_CLIP (rw) register accessor: INTF_MAGTHRESH2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh2_clip`]
module"]
# [doc (alias = "INTF_MAGTHRESH2_CLIP")]
pub type IntfMagthresh2Clip = crate :: Reg < intf_magthresh2_clip :: IntfMagthresh2ClipSpec > ; # [doc = "INTF_MAGTHRESH2_CLIP"]
pub mod intf_magthresh2_clip { # [doc = "Register `INTF_MAGTHRESH2_CLIP` reader"]
pub type R = crate :: R < IntfMagthresh2ClipSpec > ; # [doc = "Register `INTF_MAGTHRESH2_CLIP` writer"]
pub type W = crate :: W < IntfMagthresh2ClipSpec > ; # [doc = "Field `INTF_MAGTHRESH2_CLIP` reader - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh2ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGTHRESH2_CLIP` writer - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
pub fn intf_magthresh2_clip (& self) -> IntfMagthresh2ClipR { IntfMagthresh2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh2_clip (& mut self) -> IntfMagthresh2ClipW < IntfMagthresh2ClipSpec > { IntfMagthresh2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGTHRESH2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh2ClipSpec ; impl crate :: RegisterSpec for IntfMagthresh2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh2_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh2_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH2_CLIP to value 0"]
impl crate :: Resettable for IntfMagthresh2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH3_CLIP (rw) register accessor: INTF_MAGTHRESH3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh3_clip`]
module"]
# [doc (alias = "INTF_MAGTHRESH3_CLIP")]
pub type IntfMagthresh3Clip = crate :: Reg < intf_magthresh3_clip :: IntfMagthresh3ClipSpec > ; # [doc = "INTF_MAGTHRESH3_CLIP"]
pub mod intf_magthresh3_clip { # [doc = "Register `INTF_MAGTHRESH3_CLIP` reader"]
pub type R = crate :: R < IntfMagthresh3ClipSpec > ; # [doc = "Register `INTF_MAGTHRESH3_CLIP` writer"]
pub type W = crate :: W < IntfMagthresh3ClipSpec > ; # [doc = "Field `INTF_MAGTHRESH3_CLIP` reader - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh3ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGTHRESH3_CLIP` writer - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
pub fn intf_magthresh3_clip (& self) -> IntfMagthresh3ClipR { IntfMagthresh3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh3_clip (& mut self) -> IntfMagthresh3ClipW < IntfMagthresh3ClipSpec > { IntfMagthresh3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGTHRESH3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh3ClipSpec ; impl crate :: RegisterSpec for IntfMagthresh3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh3_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh3_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH3_CLIP to value 0"]
impl crate :: Resettable for IntfMagthresh3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH4_CLIP (rw) register accessor: INTF_MAGTHRESH4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh4_clip`]
module"]
# [doc (alias = "INTF_MAGTHRESH4_CLIP")]
pub type IntfMagthresh4Clip = crate :: Reg < intf_magthresh4_clip :: IntfMagthresh4ClipSpec > ; # [doc = "INTF_MAGTHRESH4_CLIP"]
pub mod intf_magthresh4_clip { # [doc = "Register `INTF_MAGTHRESH4_CLIP` reader"]
pub type R = crate :: R < IntfMagthresh4ClipSpec > ; # [doc = "Register `INTF_MAGTHRESH4_CLIP` writer"]
pub type W = crate :: W < IntfMagthresh4ClipSpec > ; # [doc = "Field `INTF_MAGTHRESH4_CLIP` reader - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh4ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGTHRESH4_CLIP` writer - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
pub fn intf_magthresh4_clip (& self) -> IntfMagthresh4ClipR { IntfMagthresh4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh4_clip (& mut self) -> IntfMagthresh4ClipW < IntfMagthresh4ClipSpec > { IntfMagthresh4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGTHRESH4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh4ClipSpec ; impl crate :: RegisterSpec for IntfMagthresh4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh4_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh4_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH4_CLIP to value 0"]
impl crate :: Resettable for IntfMagthresh4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH5_CLIP (rw) register accessor: INTF_MAGTHRESH5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh5_clip`]
module"]
# [doc (alias = "INTF_MAGTHRESH5_CLIP")]
pub type IntfMagthresh5Clip = crate :: Reg < intf_magthresh5_clip :: IntfMagthresh5ClipSpec > ; # [doc = "INTF_MAGTHRESH5_CLIP"]
pub mod intf_magthresh5_clip { # [doc = "Register `INTF_MAGTHRESH5_CLIP` reader"]
pub type R = crate :: R < IntfMagthresh5ClipSpec > ; # [doc = "Register `INTF_MAGTHRESH5_CLIP` writer"]
pub type W = crate :: W < IntfMagthresh5ClipSpec > ; # [doc = "Field `INTF_MAGTHRESH5_CLIP` reader - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh5ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGTHRESH5_CLIP` writer - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
pub fn intf_magthresh5_clip (& self) -> IntfMagthresh5ClipR { IntfMagthresh5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh5_clip (& mut self) -> IntfMagthresh5ClipW < IntfMagthresh5ClipSpec > { IntfMagthresh5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGTHRESH5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh5ClipSpec ; impl crate :: RegisterSpec for IntfMagthresh5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh5_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh5_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH5_CLIP to value 0"]
impl crate :: Resettable for IntfMagthresh5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGTHRESH6_CLIP (rw) register accessor: INTF_MAGTHRESH6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magthresh6_clip`]
module"]
# [doc (alias = "INTF_MAGTHRESH6_CLIP")]
pub type IntfMagthresh6Clip = crate :: Reg < intf_magthresh6_clip :: IntfMagthresh6ClipSpec > ; # [doc = "INTF_MAGTHRESH6_CLIP"]
pub mod intf_magthresh6_clip { # [doc = "Register `INTF_MAGTHRESH6_CLIP` reader"]
pub type R = crate :: R < IntfMagthresh6ClipSpec > ; # [doc = "Register `INTF_MAGTHRESH6_CLIP` writer"]
pub type W = crate :: W < IntfMagthresh6ClipSpec > ; # [doc = "Field `INTF_MAGTHRESH6_CLIP` reader - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh6ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGTHRESH6_CLIP` writer - 0:0\\]
Interference magnitude threshold clip status"]
pub type IntfMagthresh6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
pub fn intf_magthresh6_clip (& self) -> IntfMagthresh6ClipR { IntfMagthresh6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magthresh6_clip (& mut self) -> IntfMagthresh6ClipW < IntfMagthresh6ClipSpec > { IntfMagthresh6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagthresh6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGTHRESH6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magthresh6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magthresh6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagthresh6ClipSpec ; impl crate :: RegisterSpec for IntfMagthresh6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magthresh6_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagthresh6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magthresh6_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagthresh6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGTHRESH6_CLIP to value 0"]
impl crate :: Resettable for IntfMagthresh6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH1_CLIP (rw) register accessor: INTF_MAGDIFFTHRESH1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh1_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh1_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh1_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH1_CLIP")]
pub type IntfMagdiffthresh1Clip = crate :: Reg < intf_magdiffthresh1_clip :: IntfMagdiffthresh1ClipSpec > ; # [doc = "INTF_MAGDIFFTHRESH1_CLIP"]
pub mod intf_magdiffthresh1_clip { # [doc = "Register `INTF_MAGDIFFTHRESH1_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffthresh1ClipSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH1_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffthresh1ClipSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH1_CLIP` reader - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh1ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFTHRESH1_CLIP` writer - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh1ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
pub fn intf_magdiffthresh1_clip (& self) -> IntfMagdiffthresh1ClipR { IntfMagdiffthresh1ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh1_clip (& mut self) -> IntfMagdiffthresh1ClipW < IntfMagdiffthresh1ClipSpec > { IntfMagdiffthresh1ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh1ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFTHRESH1_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh1_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh1_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh1ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh1ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh1_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh1ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh1_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh1ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH1_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffthresh1ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH2_CLIP (rw) register accessor: INTF_MAGDIFFTHRESH2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh2_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh2_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh2_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH2_CLIP")]
pub type IntfMagdiffthresh2Clip = crate :: Reg < intf_magdiffthresh2_clip :: IntfMagdiffthresh2ClipSpec > ; # [doc = "INTF_MAGDIFFTHRESH2_CLIP"]
pub mod intf_magdiffthresh2_clip { # [doc = "Register `INTF_MAGDIFFTHRESH2_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffthresh2ClipSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH2_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffthresh2ClipSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH2_CLIP` reader - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh2ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFTHRESH2_CLIP` writer - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh2ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
pub fn intf_magdiffthresh2_clip (& self) -> IntfMagdiffthresh2ClipR { IntfMagdiffthresh2ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh2_clip (& mut self) -> IntfMagdiffthresh2ClipW < IntfMagdiffthresh2ClipSpec > { IntfMagdiffthresh2ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh2ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFTHRESH2_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh2_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh2_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh2ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh2ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh2_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh2ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh2_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh2ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH2_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffthresh2ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH3_CLIP (rw) register accessor: INTF_MAGDIFFTHRESH3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh3_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh3_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh3_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH3_CLIP")]
pub type IntfMagdiffthresh3Clip = crate :: Reg < intf_magdiffthresh3_clip :: IntfMagdiffthresh3ClipSpec > ; # [doc = "INTF_MAGDIFFTHRESH3_CLIP"]
pub mod intf_magdiffthresh3_clip { # [doc = "Register `INTF_MAGDIFFTHRESH3_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffthresh3ClipSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH3_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffthresh3ClipSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH3_CLIP` reader - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh3ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFTHRESH3_CLIP` writer - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh3ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
pub fn intf_magdiffthresh3_clip (& self) -> IntfMagdiffthresh3ClipR { IntfMagdiffthresh3ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh3_clip (& mut self) -> IntfMagdiffthresh3ClipW < IntfMagdiffthresh3ClipSpec > { IntfMagdiffthresh3ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh3ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFTHRESH3_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh3_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh3_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh3ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh3ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh3_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh3ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh3_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh3ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH3_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffthresh3ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH4_CLIP (rw) register accessor: INTF_MAGDIFFTHRESH4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh4_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh4_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh4_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH4_CLIP")]
pub type IntfMagdiffthresh4Clip = crate :: Reg < intf_magdiffthresh4_clip :: IntfMagdiffthresh4ClipSpec > ; # [doc = "INTF_MAGDIFFTHRESH4_CLIP"]
pub mod intf_magdiffthresh4_clip { # [doc = "Register `INTF_MAGDIFFTHRESH4_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffthresh4ClipSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH4_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffthresh4ClipSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH4_CLIP` reader - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh4ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFTHRESH4_CLIP` writer - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh4ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
pub fn intf_magdiffthresh4_clip (& self) -> IntfMagdiffthresh4ClipR { IntfMagdiffthresh4ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh4_clip (& mut self) -> IntfMagdiffthresh4ClipW < IntfMagdiffthresh4ClipSpec > { IntfMagdiffthresh4ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh4ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFTHRESH4_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh4_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh4_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh4ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh4ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh4_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh4ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh4_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh4ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH4_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffthresh4ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH5_CLIP (rw) register accessor: INTF_MAGDIFFTHRESH5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh5_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh5_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh5_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH5_CLIP")]
pub type IntfMagdiffthresh5Clip = crate :: Reg < intf_magdiffthresh5_clip :: IntfMagdiffthresh5ClipSpec > ; # [doc = "INTF_MAGDIFFTHRESH5_CLIP"]
pub mod intf_magdiffthresh5_clip { # [doc = "Register `INTF_MAGDIFFTHRESH5_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffthresh5ClipSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH5_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffthresh5ClipSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH5_CLIP` reader - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh5ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFTHRESH5_CLIP` writer - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh5ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
pub fn intf_magdiffthresh5_clip (& self) -> IntfMagdiffthresh5ClipR { IntfMagdiffthresh5ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh5_clip (& mut self) -> IntfMagdiffthresh5ClipW < IntfMagdiffthresh5ClipSpec > { IntfMagdiffthresh5ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh5ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFTHRESH5_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh5_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh5_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh5ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh5ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh5_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh5ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh5_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh5ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH5_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffthresh5ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTF_MAGDIFFTHRESH6_CLIP (rw) register accessor: INTF_MAGDIFFTHRESH6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh6_clip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh6_clip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf_magdiffthresh6_clip`]
module"]
# [doc (alias = "INTF_MAGDIFFTHRESH6_CLIP")]
pub type IntfMagdiffthresh6Clip = crate :: Reg < intf_magdiffthresh6_clip :: IntfMagdiffthresh6ClipSpec > ; # [doc = "INTF_MAGDIFFTHRESH6_CLIP"]
pub mod intf_magdiffthresh6_clip { # [doc = "Register `INTF_MAGDIFFTHRESH6_CLIP` reader"]
pub type R = crate :: R < IntfMagdiffthresh6ClipSpec > ; # [doc = "Register `INTF_MAGDIFFTHRESH6_CLIP` writer"]
pub type W = crate :: W < IntfMagdiffthresh6ClipSpec > ; # [doc = "Field `INTF_MAGDIFFTHRESH6_CLIP` reader - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh6ClipR = crate :: BitReader ; # [doc = "Field `INTF_MAGDIFFTHRESH6_CLIP` writer - 0:0\\]
Interference magnitude difference threshold clip status"]
pub type IntfMagdiffthresh6ClipW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
pub fn intf_magdiffthresh6_clip (& self) -> IntfMagdiffthresh6ClipR { IntfMagdiffthresh6ClipR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interference magnitude difference threshold clip status"]
# [inline (always)]
# [must_use]
pub fn intf_magdiffthresh6_clip (& mut self) -> IntfMagdiffthresh6ClipW < IntfMagdiffthresh6ClipSpec > { IntfMagdiffthresh6ClipW :: new (self , 0) } # [doc = "Bits 1:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IntfMagdiffthresh6ClipSpec > { Nu1W :: new (self , 1) } } # [doc = "INTF_MAGDIFFTHRESH6_CLIP\n\nYou can [`read`](crate::Reg::read) this register and get [`intf_magdiffthresh6_clip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf_magdiffthresh6_clip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntfMagdiffthresh6ClipSpec ; impl crate :: RegisterSpec for IntfMagdiffthresh6ClipSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intf_magdiffthresh6_clip::R`](R) reader structure"]
impl crate :: Readable for IntfMagdiffthresh6ClipSpec { } # [doc = "`write(|w| ..)` method takes [`intf_magdiffthresh6_clip::W`](W) writer structure"]
impl crate :: Writable for IntfMagdiffthresh6ClipSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTF_MAGDIFFTHRESH6_CLIP to value 0"]
impl crate :: Resettable for IntfMagdiffthresh6ClipSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_ERR_MASK (rw) register accessor: HWA_SAFETY_ERR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_err_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_err_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_err_mask`]
module"]
# [doc (alias = "HWA_SAFETY_ERR_MASK")]
pub type HwaSafetyErrMask = crate :: Reg < hwa_safety_err_mask :: HwaSafetyErrMaskSpec > ; # [doc = "HWA_SAFETY_ERR_MASK"]
pub mod hwa_safety_err_mask { # [doc = "Register `HWA_SAFETY_ERR_MASK` reader"]
pub type R = crate :: R < HwaSafetyErrMaskSpec > ; # [doc = "Register `HWA_SAFETY_ERR_MASK` writer"]
pub type W = crate :: W < HwaSafetyErrMaskSpec > ; # [doc = "Field `HWA_SAFETY_ERR_MASK_FSM_LOCKSTEP` reader - 0:0\\]
When 1'b1 : FSM lockstep error is masked.1'b0 : FSM lockstep error is not masked"]
pub type HwaSafetyErrMaskFsmLockstepR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ERR_MASK_FSM_LOCKSTEP` writer - 0:0\\]
When 1'b1 : FSM lockstep error is masked.1'b0 : FSM lockstep error is not masked"]
pub type HwaSafetyErrMaskFsmLockstepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_WINDOW_RAM` reader - 1:1\\]
When 1'b1 : Window RAM parity error is masked.1'b0 : Window RAM parity error is not masked"]
pub type HwaSafetyParityErrMaskWindowRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_WINDOW_RAM` writer - 1:1\\]
When 1'b1 : Window RAM parity error is masked.1'b0 : Window RAM parity error is not masked"]
pub type HwaSafetyParityErrMaskWindowRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_IPING_RAM` reader - 2:2\\]
When 1'b1 : ACCEL_MEM0 parity error is masked.1'b0 : ACCEL_MEM0 parity error is not masked"]
pub type HwaSafetyParityErrMaskIpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_IPING_RAM` writer - 2:2\\]
When 1'b1 : ACCEL_MEM0 parity error is masked.1'b0 : ACCEL_MEM0 parity error is not masked"]
pub type HwaSafetyParityErrMaskIpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_IPONG_RAM` reader - 3:3\\]
When 1'b1 : ACCEL_MEM1 parity error is masked.1'b0 : ACCEL_MEM1 parity error is not masked"]
pub type HwaSafetyParityErrMaskIpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_IPONG_RAM` writer - 3:3\\]
When 1'b1 : ACCEL_MEM1 parity error is masked.1'b0 : ACCEL_MEM1 parity error is not masked"]
pub type HwaSafetyParityErrMaskIpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_OPING_RAM` reader - 4:4\\]
When 1'b1 : ACCEL_MEM2 parity error is masked.1'b0 : ACCEL_MEM2 parity error is not masked"]
pub type HwaSafetyParityErrMaskOpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_OPING_RAM` writer - 4:4\\]
When 1'b1 : ACCEL_MEM2 parity error is masked.1'b0 : ACCEL_MEM2 parity error is not masked"]
pub type HwaSafetyParityErrMaskOpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_OPONG_RAM` reader - 5:5\\]
When 1'b1 : ACCEL_MEM3 parity error is masked.1'b0 : ACCEL_MEM03 parity error is not masked"]
pub type HwaSafetyParityErrMaskOpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_MASK_OPONG_RAM` writer - 5:5\\]
When 1'b1 : ACCEL_MEM3 parity error is masked.1'b0 : ACCEL_MEM03 parity error is not masked"]
pub type HwaSafetyParityErrMaskOpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_IPING_RAM` reader - 6:6\\]
When 1'b1 : ACCEL_MEM0 access error is masked.1'b0 : ACCEL_MEM0 access error is not masked"]
pub type HwaSafetyAccessErrMaskIpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_IPING_RAM` writer - 6:6\\]
When 1'b1 : ACCEL_MEM0 access error is masked.1'b0 : ACCEL_MEM0 access error is not masked"]
pub type HwaSafetyAccessErrMaskIpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_IPONG_RAM` reader - 7:7\\]
When 1'b1 : ACCEL_MEM1 access error is masked.1'b0 : ACCEL_MEM1 access error is not masked"]
pub type HwaSafetyAccessErrMaskIpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_IPONG_RAM` writer - 7:7\\]
When 1'b1 : ACCEL_MEM1 access error is masked.1'b0 : ACCEL_MEM1 access error is not masked"]
pub type HwaSafetyAccessErrMaskIpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_OPING_RAM` reader - 8:8\\]
When 1'b1 : ACCEL_MEM2 access error is masked.1'b0 : ACCEL_MEM2 access error is not masked"]
pub type HwaSafetyAccessErrMaskOpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_OPING_RAM` writer - 8:8\\]
When 1'b1 : ACCEL_MEM2 access error is masked.1'b0 : ACCEL_MEM2 access error is not masked"]
pub type HwaSafetyAccessErrMaskOpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_OPONG_RAM` reader - 9:9\\]
When 1'b1 : ACCEL_MEM3 access error is masked.1'b0 : ACCEL_MEM3 access error is not masked"]
pub type HwaSafetyAccessErrMaskOpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_MASK_OPONG_RAM` writer - 9:9\\]
When 1'b1 : ACCEL_MEM3 access error is masked.1'b0 : ACCEL_MEM3 access error is not masked"]
pub type HwaSafetyAccessErrMaskOpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
When 1'b1 : FSM lockstep error is masked.1'b0 : FSM lockstep error is not masked"]
# [inline (always)]
pub fn hwa_safety_err_mask_fsm_lockstep (& self) -> HwaSafetyErrMaskFsmLockstepR { HwaSafetyErrMaskFsmLockstepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
When 1'b1 : Window RAM parity error is masked.1'b0 : Window RAM parity error is not masked"]
# [inline (always)]
pub fn hwa_safety_parity_err_mask_window_ram (& self) -> HwaSafetyParityErrMaskWindowRamR { HwaSafetyParityErrMaskWindowRamR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
When 1'b1 : ACCEL_MEM0 parity error is masked.1'b0 : ACCEL_MEM0 parity error is not masked"]
# [inline (always)]
pub fn hwa_safety_parity_err_mask_iping_ram (& self) -> HwaSafetyParityErrMaskIpingRamR { HwaSafetyParityErrMaskIpingRamR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
When 1'b1 : ACCEL_MEM1 parity error is masked.1'b0 : ACCEL_MEM1 parity error is not masked"]
# [inline (always)]
pub fn hwa_safety_parity_err_mask_ipong_ram (& self) -> HwaSafetyParityErrMaskIpongRamR { HwaSafetyParityErrMaskIpongRamR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
When 1'b1 : ACCEL_MEM2 parity error is masked.1'b0 : ACCEL_MEM2 parity error is not masked"]
# [inline (always)]
pub fn hwa_safety_parity_err_mask_oping_ram (& self) -> HwaSafetyParityErrMaskOpingRamR { HwaSafetyParityErrMaskOpingRamR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
When 1'b1 : ACCEL_MEM3 parity error is masked.1'b0 : ACCEL_MEM03 parity error is not masked"]
# [inline (always)]
pub fn hwa_safety_parity_err_mask_opong_ram (& self) -> HwaSafetyParityErrMaskOpongRamR { HwaSafetyParityErrMaskOpongRamR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
When 1'b1 : ACCEL_MEM0 access error is masked.1'b0 : ACCEL_MEM0 access error is not masked"]
# [inline (always)]
pub fn hwa_safety_access_err_mask_iping_ram (& self) -> HwaSafetyAccessErrMaskIpingRamR { HwaSafetyAccessErrMaskIpingRamR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
When 1'b1 : ACCEL_MEM1 access error is masked.1'b0 : ACCEL_MEM1 access error is not masked"]
# [inline (always)]
pub fn hwa_safety_access_err_mask_ipong_ram (& self) -> HwaSafetyAccessErrMaskIpongRamR { HwaSafetyAccessErrMaskIpongRamR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
When 1'b1 : ACCEL_MEM2 access error is masked.1'b0 : ACCEL_MEM2 access error is not masked"]
# [inline (always)]
pub fn hwa_safety_access_err_mask_oping_ram (& self) -> HwaSafetyAccessErrMaskOpingRamR { HwaSafetyAccessErrMaskOpingRamR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
When 1'b1 : ACCEL_MEM3 access error is masked.1'b0 : ACCEL_MEM3 access error is not masked"]
# [inline (always)]
pub fn hwa_safety_access_err_mask_opong_ram (& self) -> HwaSafetyAccessErrMaskOpongRamR { HwaSafetyAccessErrMaskOpongRamR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
When 1'b1 : FSM lockstep error is masked.1'b0 : FSM lockstep error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_err_mask_fsm_lockstep (& mut self) -> HwaSafetyErrMaskFsmLockstepW < HwaSafetyErrMaskSpec > { HwaSafetyErrMaskFsmLockstepW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
When 1'b1 : Window RAM parity error is masked.1'b0 : Window RAM parity error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_mask_window_ram (& mut self) -> HwaSafetyParityErrMaskWindowRamW < HwaSafetyErrMaskSpec > { HwaSafetyParityErrMaskWindowRamW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
When 1'b1 : ACCEL_MEM0 parity error is masked.1'b0 : ACCEL_MEM0 parity error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_mask_iping_ram (& mut self) -> HwaSafetyParityErrMaskIpingRamW < HwaSafetyErrMaskSpec > { HwaSafetyParityErrMaskIpingRamW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
When 1'b1 : ACCEL_MEM1 parity error is masked.1'b0 : ACCEL_MEM1 parity error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_mask_ipong_ram (& mut self) -> HwaSafetyParityErrMaskIpongRamW < HwaSafetyErrMaskSpec > { HwaSafetyParityErrMaskIpongRamW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
When 1'b1 : ACCEL_MEM2 parity error is masked.1'b0 : ACCEL_MEM2 parity error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_mask_oping_ram (& mut self) -> HwaSafetyParityErrMaskOpingRamW < HwaSafetyErrMaskSpec > { HwaSafetyParityErrMaskOpingRamW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
When 1'b1 : ACCEL_MEM3 parity error is masked.1'b0 : ACCEL_MEM03 parity error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_mask_opong_ram (& mut self) -> HwaSafetyParityErrMaskOpongRamW < HwaSafetyErrMaskSpec > { HwaSafetyParityErrMaskOpongRamW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
When 1'b1 : ACCEL_MEM0 access error is masked.1'b0 : ACCEL_MEM0 access error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_mask_iping_ram (& mut self) -> HwaSafetyAccessErrMaskIpingRamW < HwaSafetyErrMaskSpec > { HwaSafetyAccessErrMaskIpingRamW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
When 1'b1 : ACCEL_MEM1 access error is masked.1'b0 : ACCEL_MEM1 access error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_mask_ipong_ram (& mut self) -> HwaSafetyAccessErrMaskIpongRamW < HwaSafetyErrMaskSpec > { HwaSafetyAccessErrMaskIpongRamW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
When 1'b1 : ACCEL_MEM2 access error is masked.1'b0 : ACCEL_MEM2 access error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_mask_oping_ram (& mut self) -> HwaSafetyAccessErrMaskOpingRamW < HwaSafetyErrMaskSpec > { HwaSafetyAccessErrMaskOpingRamW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
When 1'b1 : ACCEL_MEM3 access error is masked.1'b0 : ACCEL_MEM3 access error is not masked"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_mask_opong_ram (& mut self) -> HwaSafetyAccessErrMaskOpongRamW < HwaSafetyErrMaskSpec > { HwaSafetyAccessErrMaskOpongRamW :: new (self , 9) } # [doc = "Bits 10:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < HwaSafetyErrMaskSpec > { Nu1W :: new (self , 10) } } # [doc = "HWA_SAFETY_ERR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_err_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_err_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyErrMaskSpec ; impl crate :: RegisterSpec for HwaSafetyErrMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_err_mask::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyErrMaskSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_err_mask::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyErrMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_ERR_MASK to value 0"]
impl crate :: Resettable for HwaSafetyErrMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_ERR_STATUS (rw) register accessor: HWA_SAFETY_ERR_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_err_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_err_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_err_status`]
module"]
# [doc (alias = "HWA_SAFETY_ERR_STATUS")]
pub type HwaSafetyErrStatus = crate :: Reg < hwa_safety_err_status :: HwaSafetyErrStatusSpec > ; # [doc = "HWA_SAFETY_ERR_STATUS"]
pub mod hwa_safety_err_status { # [doc = "Register `HWA_SAFETY_ERR_STATUS` reader"]
pub type R = crate :: R < HwaSafetyErrStatusSpec > ; # [doc = "Register `HWA_SAFETY_ERR_STATUS` writer"]
pub type W = crate :: W < HwaSafetyErrStatusSpec > ; # [doc = "Field `HWA_SAFETY_ERR_STATUS_FSM_LOCKSTEP` reader - 0:0\\]
Indicates the FSM lockstep error (Masked status)"]
pub type HwaSafetyErrStatusFsmLockstepR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ERR_STATUS_FSM_LOCKSTEP` writer - 0:0\\]
Indicates the FSM lockstep error (Masked status)"]
pub type HwaSafetyErrStatusFsmLockstepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_WINDOW_RAM` reader - 1:1\\]
Indicates the Window RAM parity error (Masked status)"]
pub type HwaSafetyParityErrStatusWindowRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_WINDOW_RAM` writer - 1:1\\]
Indicates the Window RAM parity error (Masked status)"]
pub type HwaSafetyParityErrStatusWindowRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_IPING_RAM` reader - 2:2\\]
Indicates the ACCEL_MEM0 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusIpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_IPING_RAM` writer - 2:2\\]
Indicates the ACCEL_MEM0 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusIpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_IPONG_RAM` reader - 3:3\\]
Indicates the ACCEL_MEM1 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusIpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_IPONG_RAM` writer - 3:3\\]
Indicates the ACCEL_MEM1 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusIpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_OPING_RAM` reader - 4:4\\]
Indicates the ACCEL_MEM2 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusOpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_OPING_RAM` writer - 4:4\\]
Indicates the ACCEL_MEM2 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusOpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_OPONG_RAM` reader - 5:5\\]
Indicates the ACCEL_MEM3 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusOpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_OPONG_RAM` writer - 5:5\\]
Indicates the ACCEL_MEM3 parity error (Masked status)"]
pub type HwaSafetyParityErrStatusOpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_IPING_RAM` reader - 6:6\\]
Indicates the ACCEL_MEM0 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusIpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_IPING_RAM` writer - 6:6\\]
Indicates the ACCEL_MEM0 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusIpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_IPONG_RAM` reader - 7:7\\]
Indicates the ACCEL_MEM1 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusIpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_IPONG_RAM` writer - 7:7\\]
Indicates the ACCEL_MEM1 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusIpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_OPING_RAM` reader - 8:8\\]
Indicates the ACCEL_MEM2 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusOpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_OPING_RAM` writer - 8:8\\]
Indicates the ACCEL_MEM2 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusOpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_OPONG_RAM` reader - 9:9\\]
Indicates the ACCEL_MEM3 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusOpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_OPONG_RAM` writer - 9:9\\]
Indicates the ACCEL_MEM3 access error (Masked status)"]
pub type HwaSafetyAccessErrStatusOpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the FSM lockstep error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_err_status_fsm_lockstep (& self) -> HwaSafetyErrStatusFsmLockstepR { HwaSafetyErrStatusFsmLockstepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Indicates the Window RAM parity error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_window_ram (& self) -> HwaSafetyParityErrStatusWindowRamR { HwaSafetyParityErrStatusWindowRamR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Indicates the ACCEL_MEM0 parity error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_iping_ram (& self) -> HwaSafetyParityErrStatusIpingRamR { HwaSafetyParityErrStatusIpingRamR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Indicates the ACCEL_MEM1 parity error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_ipong_ram (& self) -> HwaSafetyParityErrStatusIpongRamR { HwaSafetyParityErrStatusIpongRamR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Indicates the ACCEL_MEM2 parity error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_oping_ram (& self) -> HwaSafetyParityErrStatusOpingRamR { HwaSafetyParityErrStatusOpingRamR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Indicates the ACCEL_MEM3 parity error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_opong_ram (& self) -> HwaSafetyParityErrStatusOpongRamR { HwaSafetyParityErrStatusOpongRamR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Indicates the ACCEL_MEM0 access error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_access_err_status_iping_ram (& self) -> HwaSafetyAccessErrStatusIpingRamR { HwaSafetyAccessErrStatusIpingRamR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Indicates the ACCEL_MEM1 access error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_access_err_status_ipong_ram (& self) -> HwaSafetyAccessErrStatusIpongRamR { HwaSafetyAccessErrStatusIpongRamR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Indicates the ACCEL_MEM2 access error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_access_err_status_oping_ram (& self) -> HwaSafetyAccessErrStatusOpingRamR { HwaSafetyAccessErrStatusOpingRamR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Indicates the ACCEL_MEM3 access error (Masked status)"]
# [inline (always)]
pub fn hwa_safety_access_err_status_opong_ram (& self) -> HwaSafetyAccessErrStatusOpongRamR { HwaSafetyAccessErrStatusOpongRamR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the FSM lockstep error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_err_status_fsm_lockstep (& mut self) -> HwaSafetyErrStatusFsmLockstepW < HwaSafetyErrStatusSpec > { HwaSafetyErrStatusFsmLockstepW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Indicates the Window RAM parity error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_window_ram (& mut self) -> HwaSafetyParityErrStatusWindowRamW < HwaSafetyErrStatusSpec > { HwaSafetyParityErrStatusWindowRamW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Indicates the ACCEL_MEM0 parity error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_iping_ram (& mut self) -> HwaSafetyParityErrStatusIpingRamW < HwaSafetyErrStatusSpec > { HwaSafetyParityErrStatusIpingRamW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Indicates the ACCEL_MEM1 parity error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_ipong_ram (& mut self) -> HwaSafetyParityErrStatusIpongRamW < HwaSafetyErrStatusSpec > { HwaSafetyParityErrStatusIpongRamW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Indicates the ACCEL_MEM2 parity error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_oping_ram (& mut self) -> HwaSafetyParityErrStatusOpingRamW < HwaSafetyErrStatusSpec > { HwaSafetyParityErrStatusOpingRamW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Indicates the ACCEL_MEM3 parity error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_opong_ram (& mut self) -> HwaSafetyParityErrStatusOpongRamW < HwaSafetyErrStatusSpec > { HwaSafetyParityErrStatusOpongRamW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Indicates the ACCEL_MEM0 access error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_iping_ram (& mut self) -> HwaSafetyAccessErrStatusIpingRamW < HwaSafetyErrStatusSpec > { HwaSafetyAccessErrStatusIpingRamW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Indicates the ACCEL_MEM1 access error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_ipong_ram (& mut self) -> HwaSafetyAccessErrStatusIpongRamW < HwaSafetyErrStatusSpec > { HwaSafetyAccessErrStatusIpongRamW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Indicates the ACCEL_MEM2 access error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_oping_ram (& mut self) -> HwaSafetyAccessErrStatusOpingRamW < HwaSafetyErrStatusSpec > { HwaSafetyAccessErrStatusOpingRamW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Indicates the ACCEL_MEM3 access error (Masked status)"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_opong_ram (& mut self) -> HwaSafetyAccessErrStatusOpongRamW < HwaSafetyErrStatusSpec > { HwaSafetyAccessErrStatusOpongRamW :: new (self , 9) } # [doc = "Bits 10:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < HwaSafetyErrStatusSpec > { Nu1W :: new (self , 10) } } # [doc = "HWA_SAFETY_ERR_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_err_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_err_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyErrStatusSpec ; impl crate :: RegisterSpec for HwaSafetyErrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_err_status::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyErrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_err_status::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyErrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_ERR_STATUS to value 0"]
impl crate :: Resettable for HwaSafetyErrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWA_SAFETY_ERR_STATUS_RAW (rw) register accessor: HWA_SAFETY_ERR_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_err_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_err_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwa_safety_err_status_raw`]
module"]
# [doc (alias = "HWA_SAFETY_ERR_STATUS_RAW")]
pub type HwaSafetyErrStatusRaw = crate :: Reg < hwa_safety_err_status_raw :: HwaSafetyErrStatusRawSpec > ; # [doc = "HWA_SAFETY_ERR_STATUS_RAW"]
pub mod hwa_safety_err_status_raw { # [doc = "Register `HWA_SAFETY_ERR_STATUS_RAW` reader"]
pub type R = crate :: R < HwaSafetyErrStatusRawSpec > ; # [doc = "Register `HWA_SAFETY_ERR_STATUS_RAW` writer"]
pub type W = crate :: W < HwaSafetyErrStatusRawSpec > ; # [doc = "Field `HWA_SAFETY_ERR_STATUS_RAW_FSM_LOCKSTEP` reader - 0:0\\]
Indicates the FSM lockstep error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 0"]
pub type HwaSafetyErrStatusRawFsmLockstepR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ERR_STATUS_RAW_FSM_LOCKSTEP` writer - 0:0\\]
Indicates the FSM lockstep error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 0"]
pub type HwaSafetyErrStatusRawFsmLockstepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_WINDOW_RAM` reader - 1:1\\]
Indicates the Window RAM parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 1"]
pub type HwaSafetyParityErrStatusRawWindowRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_WINDOW_RAM` writer - 1:1\\]
Indicates the Window RAM parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 1"]
pub type HwaSafetyParityErrStatusRawWindowRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_IPING_RAM` reader - 2:2\\]
Indicates the ACCEL_MEM0 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 2"]
pub type HwaSafetyParityErrStatusRawIpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_IPING_RAM` writer - 2:2\\]
Indicates the ACCEL_MEM0 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 2"]
pub type HwaSafetyParityErrStatusRawIpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_IPONG_RAM` reader - 3:3\\]
Indicates the ACCEL_MEM1 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 3"]
pub type HwaSafetyParityErrStatusRawIpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_IPONG_RAM` writer - 3:3\\]
Indicates the ACCEL_MEM1 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 3"]
pub type HwaSafetyParityErrStatusRawIpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_OPING_RAM` reader - 4:4\\]
Indicates the ACCEL_MEM2 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 4"]
pub type HwaSafetyParityErrStatusRawOpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_OPING_RAM` writer - 4:4\\]
Indicates the ACCEL_MEM2 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 4"]
pub type HwaSafetyParityErrStatusRawOpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_OPONG_RAM` reader - 5:5\\]
Indicates the ACCEL_MEM3 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 5"]
pub type HwaSafetyParityErrStatusRawOpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_PARITY_ERR_STATUS_RAW_OPONG_RAM` writer - 5:5\\]
Indicates the ACCEL_MEM3 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 5"]
pub type HwaSafetyParityErrStatusRawOpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_IPING_RAM` reader - 6:6\\]
Indicates the ACCEL_MEM0 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 6"]
pub type HwaSafetyAccessErrStatusRawIpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_IPING_RAM` writer - 6:6\\]
Indicates the ACCEL_MEM0 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 6"]
pub type HwaSafetyAccessErrStatusRawIpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_IPONG_RAM` reader - 7:7\\]
Indicates the ACCEL_MEM1 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 7"]
pub type HwaSafetyAccessErrStatusRawIpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_IPONG_RAM` writer - 7:7\\]
Indicates the ACCEL_MEM1 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 7"]
pub type HwaSafetyAccessErrStatusRawIpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_OPING_RAM` reader - 8:8\\]
Indicates the ACCEL_MEM2 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 8"]
pub type HwaSafetyAccessErrStatusRawOpingRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_OPING_RAM` writer - 8:8\\]
Indicates the ACCEL_MEM2 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 8"]
pub type HwaSafetyAccessErrStatusRawOpingRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_OPONG_RAM` reader - 9:9\\]
Indicates the ACCEL_MEM3 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 9"]
pub type HwaSafetyAccessErrStatusRawOpongRamR = crate :: BitReader ; # [doc = "Field `HWA_SAFETY_ACCESS_ERR_STATUS_RAW_OPONG_RAM` writer - 9:9\\]
Indicates the ACCEL_MEM3 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 9"]
pub type HwaSafetyAccessErrStatusRawOpongRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - "]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - "]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the FSM lockstep error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 0"]
# [inline (always)]
pub fn hwa_safety_err_status_raw_fsm_lockstep (& self) -> HwaSafetyErrStatusRawFsmLockstepR { HwaSafetyErrStatusRawFsmLockstepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Indicates the Window RAM parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 1"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_raw_window_ram (& self) -> HwaSafetyParityErrStatusRawWindowRamR { HwaSafetyParityErrStatusRawWindowRamR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Indicates the ACCEL_MEM0 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 2"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_raw_iping_ram (& self) -> HwaSafetyParityErrStatusRawIpingRamR { HwaSafetyParityErrStatusRawIpingRamR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Indicates the ACCEL_MEM1 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 3"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_raw_ipong_ram (& self) -> HwaSafetyParityErrStatusRawIpongRamR { HwaSafetyParityErrStatusRawIpongRamR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Indicates the ACCEL_MEM2 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 4"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_raw_oping_ram (& self) -> HwaSafetyParityErrStatusRawOpingRamR { HwaSafetyParityErrStatusRawOpingRamR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Indicates the ACCEL_MEM3 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 5"]
# [inline (always)]
pub fn hwa_safety_parity_err_status_raw_opong_ram (& self) -> HwaSafetyParityErrStatusRawOpongRamR { HwaSafetyParityErrStatusRawOpongRamR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Indicates the ACCEL_MEM0 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 6"]
# [inline (always)]
pub fn hwa_safety_access_err_status_raw_iping_ram (& self) -> HwaSafetyAccessErrStatusRawIpingRamR { HwaSafetyAccessErrStatusRawIpingRamR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Indicates the ACCEL_MEM1 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 7"]
# [inline (always)]
pub fn hwa_safety_access_err_status_raw_ipong_ram (& self) -> HwaSafetyAccessErrStatusRawIpongRamR { HwaSafetyAccessErrStatusRawIpongRamR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Indicates the ACCEL_MEM2 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 8"]
# [inline (always)]
pub fn hwa_safety_access_err_status_raw_oping_ram (& self) -> HwaSafetyAccessErrStatusRawOpingRamR { HwaSafetyAccessErrStatusRawOpingRamR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Indicates the ACCEL_MEM3 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 9"]
# [inline (always)]
pub fn hwa_safety_access_err_status_raw_opong_ram (& self) -> HwaSafetyAccessErrStatusRawOpongRamR { HwaSafetyAccessErrStatusRawOpongRamR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:31"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the FSM lockstep error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 0"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_err_status_raw_fsm_lockstep (& mut self) -> HwaSafetyErrStatusRawFsmLockstepW < HwaSafetyErrStatusRawSpec > { HwaSafetyErrStatusRawFsmLockstepW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Indicates the Window RAM parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 1"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_raw_window_ram (& mut self) -> HwaSafetyParityErrStatusRawWindowRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyParityErrStatusRawWindowRamW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Indicates the ACCEL_MEM0 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 2"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_raw_iping_ram (& mut self) -> HwaSafetyParityErrStatusRawIpingRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyParityErrStatusRawIpingRamW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Indicates the ACCEL_MEM1 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 3"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_raw_ipong_ram (& mut self) -> HwaSafetyParityErrStatusRawIpongRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyParityErrStatusRawIpongRamW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Indicates the ACCEL_MEM2 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 4"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_raw_oping_ram (& mut self) -> HwaSafetyParityErrStatusRawOpingRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyParityErrStatusRawOpingRamW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Indicates the ACCEL_MEM3 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 5"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_parity_err_status_raw_opong_ram (& mut self) -> HwaSafetyParityErrStatusRawOpongRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyParityErrStatusRawOpongRamW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Indicates the ACCEL_MEM0 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 6"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_raw_iping_ram (& mut self) -> HwaSafetyAccessErrStatusRawIpingRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyAccessErrStatusRawIpingRamW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Indicates the ACCEL_MEM1 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 7"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_raw_ipong_ram (& mut self) -> HwaSafetyAccessErrStatusRawIpongRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyAccessErrStatusRawIpongRamW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Indicates the ACCEL_MEM2 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 8"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_raw_oping_ram (& mut self) -> HwaSafetyAccessErrStatusRawOpingRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyAccessErrStatusRawOpingRamW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Indicates the ACCEL_MEM3 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 9"]
# [inline (always)]
# [must_use]
pub fn hwa_safety_access_err_status_raw_opong_ram (& mut self) -> HwaSafetyAccessErrStatusRawOpongRamW < HwaSafetyErrStatusRawSpec > { HwaSafetyAccessErrStatusRawOpongRamW :: new (self , 9) } # [doc = "Bits 10:31"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < HwaSafetyErrStatusRawSpec > { Nu1W :: new (self , 10) } } # [doc = "HWA_SAFETY_ERR_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`hwa_safety_err_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwa_safety_err_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwaSafetyErrStatusRawSpec ; impl crate :: RegisterSpec for HwaSafetyErrStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwa_safety_err_status_raw::R`](R) reader structure"]
impl crate :: Readable for HwaSafetyErrStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`hwa_safety_err_status_raw::W`](W) writer structure"]
impl crate :: Writable for HwaSafetyErrStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWA_SAFETY_ERR_STATUS_RAW to value 0"]
impl crate :: Resettable for HwaSafetyErrStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Register test environment"]
pub struct TptcB0 { _marker : PhantomData < * const () > } unsafe impl Send for TptcB0 { } impl TptcB0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tptc_b0 :: RegisterBlock = 0x5502_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tptc_b0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TptcB0 { type Target = tptc_b0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TptcB0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TptcB0") . finish () } } # [doc = "Register test environment"]
pub mod tptc_b0 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , tccfg : Tccfg , _reserved2 : [u8 ; 0xf8]
, tcstat : Tcstat , intstat : Intstat , inten : Inten , intclr : Intclr , intcmd : Intcmd , _reserved7 : [u8 ; 0x0c]
, errstat : Errstat , erren : Erren , errclr : Errclr , errdet : Errdet , errcmd : Errcmd , _reserved12 : [u8 ; 0x0c]
, rdrate : Rdrate , _reserved13 : [u8 ; 0xbc]
, popt : Popt , psrc : Psrc , pcnt : Pcnt , pdst : Pdst , pbidx : Pbidx , pmpprxy : Pmpprxy , _reserved19 : [u8 ; 0x28]
, saopt : Saopt , sasrc : Sasrc , sacnt : Sacnt , sadst : Sadst , sabidx : Sabidx , sampprxy : Sampprxy , sacntrld : Sacntrld , sasrcbref : Sasrcbref , sadstbref : Sadstbref , sabcnt : Sabcnt , _reserved29 : [u8 ; 0x18]
, dfcntrld : Dfcntrld , dfsrcbref : Dfsrcbref , _reserved31 : [u8 ; 0x78]
, dfopt0 : Dfopt0 , dfsrc0 : Dfsrc0 , dfacnt0 : Dfacnt0 , dfdst0 : Dfdst0 , dfbidx0 : Dfbidx0 , dfmpprxy0 : Dfmpprxy0 , dfbcnt0 : Dfbcnt0 , _reserved38 : [u8 ; 0x24]
, dfopt1 : Dfopt1 , dfsrc1 : Dfsrc1 , dfacnt1 : Dfacnt1 , dfdst1 : Dfdst1 , dfbidx1 : Dfbidx1 , dfmpprxy1 : Dfmpprxy1 , dfbcnt1 : Dfbcnt1 , } impl RegisterBlock { # [doc = "0x00 - Peripheral ID Register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - TC Configuration Register"]
# [inline (always)]
pub const fn tccfg (& self) -> & Tccfg { & self . tccfg } # [doc = "0x100 - TC Status Register"]
# [inline (always)]
pub const fn tcstat (& self) -> & Tcstat { & self . tcstat } # [doc = "0x104 - Interrupt Status Register"]
# [inline (always)]
pub const fn intstat (& self) -> & Intstat { & self . intstat } # [doc = "0x108 - Interrupt Enable Register"]
# [inline (always)]
pub const fn inten (& self) -> & Inten { & self . inten } # [doc = "0x10c - Interrupt Clear Register"]
# [inline (always)]
pub const fn intclr (& self) -> & Intclr { & self . intclr } # [doc = "0x110 - Interrupt Command Register"]
# [inline (always)]
pub const fn intcmd (& self) -> & Intcmd { & self . intcmd } # [doc = "0x120 - Error Status Register"]
# [inline (always)]
pub const fn errstat (& self) -> & Errstat { & self . errstat } # [doc = "0x124 - Error Enable Register"]
# [inline (always)]
pub const fn erren (& self) -> & Erren { & self . erren } # [doc = "0x128 - Error Clear Register"]
# [inline (always)]
pub const fn errclr (& self) -> & Errclr { & self . errclr } # [doc = "0x12c - Error Details Register"]
# [inline (always)]
pub const fn errdet (& self) -> & Errdet { & self . errdet } # [doc = "0x130 - Error Command Register"]
# [inline (always)]
pub const fn errcmd (& self) -> & Errcmd { & self . errcmd } # [doc = "0x140 - Read Rate Register"]
# [inline (always)]
pub const fn rdrate (& self) -> & Rdrate { & self . rdrate } # [doc = "0x200 - Prog Set Options"]
# [inline (always)]
pub const fn popt (& self) -> & Popt { & self . popt } # [doc = "0x204 - Prog Set Src Address"]
# [inline (always)]
pub const fn psrc (& self) -> & Psrc { & self . psrc } # [doc = "0x208 - Prog Set Count"]
# [inline (always)]
pub const fn pcnt (& self) -> & Pcnt { & self . pcnt } # [doc = "0x20c - Prog Set Dst Address"]
# [inline (always)]
pub const fn pdst (& self) -> & Pdst { & self . pdst } # [doc = "0x210 - Prog Set B-Dim Idx"]
# [inline (always)]
pub const fn pbidx (& self) -> & Pbidx { & self . pbidx } # [doc = "0x214 - Prog Set Mem Protect Proxy"]
# [inline (always)]
pub const fn pmpprxy (& self) -> & Pmpprxy { & self . pmpprxy } # [doc = "0x240 - Src Actv Set Options"]
# [inline (always)]
pub const fn saopt (& self) -> & Saopt { & self . saopt } # [doc = "0x244 - Src Actv Set Src Address"]
# [inline (always)]
pub const fn sasrc (& self) -> & Sasrc { & self . sasrc } # [doc = "0x248 - Src Actv Set A-Count"]
# [inline (always)]
pub const fn sacnt (& self) -> & Sacnt { & self . sacnt } # [doc = "0x24c - Src Actv Set Dst Address"]
# [inline (always)]
pub const fn sadst (& self) -> & Sadst { & self . sadst } # [doc = "0x250 - Src Actv Set B-Dim Idx"]
# [inline (always)]
pub const fn sabidx (& self) -> & Sabidx { & self . sabidx } # [doc = "0x254 - Src Actv Set Mem Protect Proxy"]
# [inline (always)]
pub const fn sampprxy (& self) -> & Sampprxy { & self . sampprxy } # [doc = "0x258 - Src Actv Set Cnt Reload"]
# [inline (always)]
pub const fn sacntrld (& self) -> & Sacntrld { & self . sacntrld } # [doc = "0x25c - Src Actv Set Src Addr B-Reference"]
# [inline (always)]
pub const fn sasrcbref (& self) -> & Sasrcbref { & self . sasrcbref } # [doc = "0x260 - Src Actv Set Dst Addr B-Reference"]
# [inline (always)]
pub const fn sadstbref (& self) -> & Sadstbref { & self . sadstbref } # [doc = "0x264 - Src Actv Set B-Count"]
# [inline (always)]
pub const fn sabcnt (& self) -> & Sabcnt { & self . sabcnt } # [doc = "0x280 - Dst FIFO Set Cnt Reload"]
# [inline (always)]
pub const fn dfcntrld (& self) -> & Dfcntrld { & self . dfcntrld } # [doc = "0x284 - Dst FIFO Set Src Addr B-Reference"]
# [inline (always)]
pub const fn dfsrcbref (& self) -> & Dfsrcbref { & self . dfsrcbref } # [doc = "0x300 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt0 (& self) -> & Dfopt0 { & self . dfopt0 } # [doc = "0x304 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc0 (& self) -> & Dfsrc0 { & self . dfsrc0 } # [doc = "0x308 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt0 (& self) -> & Dfacnt0 { & self . dfacnt0 } # [doc = "0x30c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst0 (& self) -> & Dfdst0 { & self . dfdst0 } # [doc = "0x310 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx0 (& self) -> & Dfbidx0 { & self . dfbidx0 } # [doc = "0x314 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy0 (& self) -> & Dfmpprxy0 { & self . dfmpprxy0 } # [doc = "0x318 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt0 (& self) -> & Dfbcnt0 { & self . dfbcnt0 } # [doc = "0x340 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt1 (& self) -> & Dfopt1 { & self . dfopt1 } # [doc = "0x344 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc1 (& self) -> & Dfsrc1 { & self . dfsrc1 } # [doc = "0x348 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt1 (& self) -> & Dfacnt1 { & self . dfacnt1 } # [doc = "0x34c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst1 (& self) -> & Dfdst1 { & self . dfdst1 } # [doc = "0x350 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx1 (& self) -> & Dfbidx1 { & self . dfbidx1 } # [doc = "0x354 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy1 (& self) -> & Dfmpprxy1 { & self . dfmpprxy1 } # [doc = "0x358 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt1 (& self) -> & Dfbcnt1 { & self . dfbcnt1 } } # [doc = "PID (rw) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "Peripheral ID Register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR_REVISION` reader - 5:0\\]
Minor Revision"]
pub type MinorRevisionR = crate :: FieldReader ; # [doc = "Field `MINOR_REVISION` writer - 5:0\\]
Minor Revision"]
pub type MinorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM_REVISION_FIELD` reader - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldR = crate :: FieldReader ; # [doc = "Field `CUSTOM_REVISION_FIELD` writer - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR_REVISION` reader - 10:8\\]
Major Revision"]
pub type MajorRevisionR = crate :: FieldReader ; # [doc = "Field `MAJOR_REVISION` writer - 10:8\\]
Major Revision"]
pub type MajorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL_VERSION` reader - 15:11\\]
RTL Version"]
pub type RtlVersionR = crate :: FieldReader ; # [doc = "Field `RTL_VERSION` writer - 15:11\\]
RTL Version"]
pub type RtlVersionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNCTION_INDICATES_A` reader - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNCTION_INDICATES_A` writer - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `PID_SCHEME` reader - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeR = crate :: FieldReader ; # [doc = "Field `PID_SCHEME` writer - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
pub fn minor_revision (& self) -> MinorRevisionR { MinorRevisionR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
pub fn custom_revision_field (& self) -> CustomRevisionFieldR { CustomRevisionFieldR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
pub fn major_revision (& self) -> MajorRevisionR { MajorRevisionR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
pub fn rtl_version (& self) -> RtlVersionR { RtlVersionR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
pub fn function_indicates_a (& self) -> FunctionIndicatesAR { FunctionIndicatesAR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
pub fn pid_scheme (& self) -> PidSchemeR { PidSchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
# [must_use]
pub fn minor_revision (& mut self) -> MinorRevisionW < PidSpec > { MinorRevisionW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
# [must_use]
pub fn custom_revision_field (& mut self) -> CustomRevisionFieldW < PidSpec > { CustomRevisionFieldW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
# [must_use]
pub fn major_revision (& mut self) -> MajorRevisionW < PidSpec > { MajorRevisionW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
# [must_use]
pub fn rtl_version (& mut self) -> RtlVersionW < PidSpec > { RtlVersionW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
# [must_use]
pub fn function_indicates_a (& mut self) -> FunctionIndicatesAW < PidSpec > { FunctionIndicatesAW :: new (self , 16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
# [must_use]
pub fn pid_scheme (& mut self) -> PidSchemeW < PidSpec > { PidSchemeW :: new (self , 30) } } # [doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCCFG (rw) register accessor: TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tccfg`]
module"]
# [doc (alias = "TCCFG")]
pub type Tccfg = crate :: Reg < tccfg :: TccfgSpec > ; # [doc = "TC Configuration Register"]
pub mod tccfg { # [doc = "Register `TCCFG` reader"]
pub type R = crate :: R < TccfgSpec > ; # [doc = "Register `TCCFG` writer"]
pub type W = crate :: W < TccfgSpec > ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` reader - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationR = crate :: FieldReader ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` writer - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` reader - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationR = crate :: FieldReader ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` writer - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DST_REGISTER_FIFO` reader - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoR = crate :: FieldReader ; # [doc = "Field `DST_REGISTER_FIFO` writer - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
pub fn fifo_size_parameterization (& self) -> FifoSizeParameterizationR { FifoSizeParameterizationR :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
pub fn bus_width_parameterization (& self) -> BusWidthParameterizationR { BusWidthParameterizationR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
pub fn dst_register_fifo (& self) -> DstRegisterFifoR { DstRegisterFifoR :: new (((self . bits >> 8) & 3) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
# [must_use]
pub fn fifo_size_parameterization (& mut self) -> FifoSizeParameterizationW < TccfgSpec > { FifoSizeParameterizationW :: new (self , 0) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
# [must_use]
pub fn bus_width_parameterization (& mut self) -> BusWidthParameterizationW < TccfgSpec > { BusWidthParameterizationW :: new (self , 4) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
# [must_use]
pub fn dst_register_fifo (& mut self) -> DstRegisterFifoW < TccfgSpec > { DstRegisterFifoW :: new (self , 8) } } # [doc = "TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TccfgSpec ; impl crate :: RegisterSpec for TccfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tccfg::R`](R) reader structure"]
impl crate :: Readable for TccfgSpec { } # [doc = "`write(|w| ..)` method takes [`tccfg::W`](W) writer structure"]
impl crate :: Writable for TccfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCCFG to value 0"]
impl crate :: Resettable for TccfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCSTAT (rw) register accessor: TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcstat`]
module"]
# [doc (alias = "TCSTAT")]
pub type Tcstat = crate :: Reg < tcstat :: TcstatSpec > ; # [doc = "TC Status Register"]
pub mod tcstat { # [doc = "Register `TCSTAT` reader"]
pub type R = crate :: R < TcstatSpec > ; # [doc = "Register `TCSTAT` writer"]
pub type W = crate :: W < TcstatSpec > ; # [doc = "Field `PROGRAM_REGISTER_SET` reader - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetR = crate :: BitReader ; # [doc = "Field `PROGRAM_REGISTER_SET` writer - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOURCE_ACTIVE_STATE` reader - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateR = crate :: BitReader ; # [doc = "Field `SOURCE_ACTIVE_STATE` writer - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WRITE_STATUS_ACTIVE` reader - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveR = crate :: BitReader ; # [doc = "Field `WRITE_STATUS_ACTIVE` writer - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ACTIVE_STATE` reader - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateR = crate :: FieldReader ; # [doc = "Field `DESTINATION_ACTIVE_STATE` writer - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CHANNEL_ACTIVE` reader - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveR = crate :: BitReader ; # [doc = "Field `CHANNEL_ACTIVE` writer - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DST_FIFO_START` reader - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartR = crate :: FieldReader ; # [doc = "Field `DST_FIFO_START` writer - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
pub fn program_register_set (& self) -> ProgramRegisterSetR { ProgramRegisterSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
pub fn source_active_state (& self) -> SourceActiveStateR { SourceActiveStateR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
pub fn write_status_active (& self) -> WriteStatusActiveR { WriteStatusActiveR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
pub fn destination_active_state (& self) -> DestinationActiveStateR { DestinationActiveStateR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
pub fn channel_active (& self) -> ChannelActiveR { ChannelActiveR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
pub fn dst_fifo_start (& self) -> DstFifoStartR { DstFifoStartR :: new (((self . bits >> 12) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
# [must_use]
pub fn program_register_set (& mut self) -> ProgramRegisterSetW < TcstatSpec > { ProgramRegisterSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
# [must_use]
pub fn source_active_state (& mut self) -> SourceActiveStateW < TcstatSpec > { SourceActiveStateW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
# [must_use]
pub fn write_status_active (& mut self) -> WriteStatusActiveW < TcstatSpec > { WriteStatusActiveW :: new (self , 2) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
# [must_use]
pub fn destination_active_state (& mut self) -> DestinationActiveStateW < TcstatSpec > { DestinationActiveStateW :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
# [must_use]
pub fn channel_active (& mut self) -> ChannelActiveW < TcstatSpec > { ChannelActiveW :: new (self , 8) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
# [must_use]
pub fn dst_fifo_start (& mut self) -> DstFifoStartW < TcstatSpec > { DstFifoStartW :: new (self , 12) } } # [doc = "TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcstatSpec ; impl crate :: RegisterSpec for TcstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tcstat::R`](R) reader structure"]
impl crate :: Readable for TcstatSpec { } # [doc = "`write(|w| ..)` method takes [`tcstat::W`](W) writer structure"]
impl crate :: Writable for TcstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCSTAT to value 0"]
impl crate :: Resettable for TcstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTSTAT (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstat`]
module"]
# [doc (alias = "INTSTAT")]
pub type Intstat = crate :: Reg < intstat :: IntstatSpec > ; # [doc = "Interrupt Status Register"]
pub mod intstat { # [doc = "Register `INTSTAT` reader"]
pub type R = crate :: R < IntstatSpec > ; # [doc = "Register `INTSTAT` writer"]
pub type W = crate :: W < IntstatSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntstatSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntstatSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntstatSpec ; impl crate :: RegisterSpec for IntstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intstat::R`](R) reader structure"]
impl crate :: Readable for IntstatSpec { } # [doc = "`write(|w| ..)` method takes [`intstat::W`](W) writer structure"]
impl crate :: Writable for IntstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTSTAT to value 0"]
impl crate :: Resettable for IntstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
# [doc (alias = "INTEN")]
pub type Inten = crate :: Reg < inten :: IntenSpec > ; # [doc = "Interrupt Enable Register"]
pub mod inten { # [doc = "Register `INTEN` reader"]
pub type R = crate :: R < IntenSpec > ; # [doc = "Register `INTEN` writer"]
pub type W = crate :: W < IntenSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntenSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntenSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenSpec ; impl crate :: RegisterSpec for IntenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`inten::R`](R) reader structure"]
impl crate :: Readable for IntenSpec { } # [doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
impl crate :: Writable for IntenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTEN to value 0"]
impl crate :: Resettable for IntenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCLR (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`]
module"]
# [doc (alias = "INTCLR")]
pub type Intclr = crate :: Reg < intclr :: IntclrSpec > ; # [doc = "Interrupt Clear Register"]
pub mod intclr { # [doc = "Register `INTCLR` reader"]
pub type R = crate :: R < IntclrSpec > ; # [doc = "Register `INTCLR` writer"]
pub type W = crate :: W < IntclrSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntclrSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntclrSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntclrSpec ; impl crate :: RegisterSpec for IntclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intclr::R`](R) reader structure"]
impl crate :: Readable for IntclrSpec { } # [doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"]
impl crate :: Writable for IntclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCLR to value 0"]
impl crate :: Resettable for IntclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCMD (rw) register accessor: Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intcmd`]
module"]
# [doc (alias = "INTCMD")]
pub type Intcmd = crate :: Reg < intcmd :: IntcmdSpec > ; # [doc = "Interrupt Command Register"]
pub mod intcmd { # [doc = "Register `INTCMD` reader"]
pub type R = crate :: R < IntcmdSpec > ; # [doc = "Register `INTCMD` writer"]
pub type W = crate :: W < IntcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_INTERRUPT` reader - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptR = crate :: BitReader ; # [doc = "Field `SET_TPTC_INTERRUPT` writer - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_interrupt (& self) -> SetTptcInterruptR { SetTptcInterruptR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < IntcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_interrupt (& mut self) -> SetTptcInterruptW < IntcmdSpec > { SetTptcInterruptW :: new (self , 1) } } # [doc = "Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntcmdSpec ; impl crate :: RegisterSpec for IntcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intcmd::R`](R) reader structure"]
impl crate :: Readable for IntcmdSpec { } # [doc = "`write(|w| ..)` method takes [`intcmd::W`](W) writer structure"]
impl crate :: Writable for IntcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCMD to value 0"]
impl crate :: Resettable for IntcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRSTAT (rw) register accessor: Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errstat`]
module"]
# [doc (alias = "ERRSTAT")]
pub type Errstat = crate :: Reg < errstat :: ErrstatSpec > ; # [doc = "Error Status Register"]
pub mod errstat { # [doc = "Register `ERRSTAT` reader"]
pub type R = crate :: R < ErrstatSpec > ; # [doc = "Register `ERRSTAT` writer"]
pub type W = crate :: W < ErrstatSpec > ; # [doc = "Field `BUS_ERROR_EVENT` reader - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventR = crate :: BitReader ; # [doc = "Field `BUS_ERROR_EVENT` writer - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_ERROR` reader - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorR = crate :: BitReader ; # [doc = "Field `TR_ERROR` writer - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMR_ADDRESS_ERROR` reader - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorR = crate :: BitReader ; # [doc = "Field `MMR_ADDRESS_ERROR` writer - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
pub fn bus_error_event (& self) -> BusErrorEventR { BusErrorEventR :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
pub fn tr_error (& self) -> TrErrorR { TrErrorR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
pub fn mmr_address_error (& self) -> MmrAddressErrorR { MmrAddressErrorR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
# [must_use]
pub fn bus_error_event (& mut self) -> BusErrorEventW < ErrstatSpec > { BusErrorEventW :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn tr_error (& mut self) -> TrErrorW < ErrstatSpec > { TrErrorW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn mmr_address_error (& mut self) -> MmrAddressErrorW < ErrstatSpec > { MmrAddressErrorW :: new (self , 3) } } # [doc = "Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrstatSpec ; impl crate :: RegisterSpec for ErrstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errstat::R`](R) reader structure"]
impl crate :: Readable for ErrstatSpec { } # [doc = "`write(|w| ..)` method takes [`errstat::W`](W) writer structure"]
impl crate :: Writable for ErrstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRSTAT to value 0"]
impl crate :: Resettable for ErrstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERREN (rw) register accessor: Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erren`]
module"]
# [doc (alias = "ERREN")]
pub type Erren = crate :: Reg < erren :: ErrenSpec > ; # [doc = "Error Enable Register"]
pub mod erren { # [doc = "Register `ERREN` reader"]
pub type R = crate :: R < ErrenSpec > ; # [doc = "Register `ERREN` writer"]
pub type W = crate :: W < ErrenSpec > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` reader - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` writer - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` reader - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` writer - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR` reader - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR` writer - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_2 (& self) -> InterruptEnableFor2R { InterruptEnableFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_1 (& self) -> InterruptEnableFor1R { InterruptEnableFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for (& self) -> InterruptEnableForR { InterruptEnableForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_2 (& mut self) -> InterruptEnableFor2W < ErrenSpec > { InterruptEnableFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_1 (& mut self) -> InterruptEnableFor1W < ErrenSpec > { InterruptEnableFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for (& mut self) -> InterruptEnableForW < ErrenSpec > { InterruptEnableForW :: new (self , 3) } } # [doc = "Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrenSpec ; impl crate :: RegisterSpec for ErrenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erren::R`](R) reader structure"]
impl crate :: Readable for ErrenSpec { } # [doc = "`write(|w| ..)` method takes [`erren::W`](W) writer structure"]
impl crate :: Writable for ErrenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERREN to value 0"]
impl crate :: Resettable for ErrenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCLR (rw) register accessor: Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errclr`]
module"]
# [doc (alias = "ERRCLR")]
pub type Errclr = crate :: Reg < errclr :: ErrclrSpec > ; # [doc = "Error Clear Register"]
pub mod errclr { # [doc = "Register `ERRCLR` reader"]
pub type R = crate :: R < ErrclrSpec > ; # [doc = "Register `ERRCLR` writer"]
pub type W = crate :: W < ErrclrSpec > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` reader - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` writer - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` reader - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` writer - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR` reader - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR` writer - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_2 (& self) -> InterruptClearFor2R { InterruptClearFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_1 (& self) -> InterruptClearFor1R { InterruptClearFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for (& self) -> InterruptClearForR { InterruptClearForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_2 (& mut self) -> InterruptClearFor2W < ErrclrSpec > { InterruptClearFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_1 (& mut self) -> InterruptClearFor1W < ErrclrSpec > { InterruptClearFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for (& mut self) -> InterruptClearForW < ErrclrSpec > { InterruptClearForW :: new (self , 3) } } # [doc = "Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrclrSpec ; impl crate :: RegisterSpec for ErrclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errclr::R`](R) reader structure"]
impl crate :: Readable for ErrclrSpec { } # [doc = "`write(|w| ..)` method takes [`errclr::W`](W) writer structure"]
impl crate :: Writable for ErrclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCLR to value 0"]
impl crate :: Resettable for ErrclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRDET (rw) register accessor: Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errdet`]
module"]
# [doc (alias = "ERRDET")]
pub type Errdet = crate :: Reg < errdet :: ErrdetSpec > ; # [doc = "Error Details Register"]
pub mod errdet { # [doc = "Register `ERRDET` reader"]
pub type R = crate :: R < ErrdetSpec > ; # [doc = "Register `ERRDET` writer"]
pub type W = crate :: W < ErrdetSpec > ; # [doc = "Field `TRANSACTION_STATUS` reader - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusR = crate :: FieldReader ; # [doc = "Field `TRANSACTION_STATUS` writer - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` reader - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` writer - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` reader - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` writer - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
pub fn transaction_status (& self) -> TransactionStatusR { TransactionStatusR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcinten (& self) -> ContainsTheOptTcintenR { ContainsTheOptTcintenR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcchen (& self) -> ContainsTheOptTcchenR { ContainsTheOptTcchenR :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
# [must_use]
pub fn transaction_status (& mut self) -> TransactionStatusW < ErrdetSpec > { TransactionStatusW :: new (self , 0) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < ErrdetSpec > { TransferCompleteCodeW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcinten (& mut self) -> ContainsTheOptTcintenW < ErrdetSpec > { ContainsTheOptTcintenW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcchen (& mut self) -> ContainsTheOptTcchenW < ErrdetSpec > { ContainsTheOptTcchenW :: new (self , 17) } } # [doc = "Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrdetSpec ; impl crate :: RegisterSpec for ErrdetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errdet::R`](R) reader structure"]
impl crate :: Readable for ErrdetSpec { } # [doc = "`write(|w| ..)` method takes [`errdet::W`](W) writer structure"]
impl crate :: Writable for ErrdetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRDET to value 0"]
impl crate :: Resettable for ErrdetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCMD (rw) register accessor: Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errcmd`]
module"]
# [doc (alias = "ERRCMD")]
pub type Errcmd = crate :: Reg < errcmd :: ErrcmdSpec > ; # [doc = "Error Command Register"]
pub mod errcmd { # [doc = "Register `ERRCMD` reader"]
pub type R = crate :: R < ErrcmdSpec > ; # [doc = "Register `ERRCMD` writer"]
pub type W = crate :: W < ErrcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_ERROR` reader - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorR = crate :: BitReader ; # [doc = "Field `SET_TPTC_ERROR` writer - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_error (& self) -> SetTptcErrorR { SetTptcErrorR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < ErrcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_error (& mut self) -> SetTptcErrorW < ErrcmdSpec > { SetTptcErrorW :: new (self , 1) } } # [doc = "Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrcmdSpec ; impl crate :: RegisterSpec for ErrcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errcmd::R`](R) reader structure"]
impl crate :: Readable for ErrcmdSpec { } # [doc = "`write(|w| ..)` method takes [`errcmd::W`](W) writer structure"]
impl crate :: Writable for ErrcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCMD to value 0"]
impl crate :: Resettable for ErrcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RDRATE (rw) register accessor: Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdrate`]
module"]
# [doc (alias = "RDRATE")]
pub type Rdrate = crate :: Reg < rdrate :: RdrateSpec > ; # [doc = "Read Rate Register"]
pub mod rdrate { # [doc = "Register `RDRATE` reader"]
pub type R = crate :: R < RdrateSpec > ; # [doc = "Register `RDRATE` writer"]
pub type W = crate :: W < RdrateSpec > ; # [doc = "Field `READ_RATE_CONTROL` reader - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlR = crate :: FieldReader ; # [doc = "Field `READ_RATE_CONTROL` writer - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
pub fn read_rate_control (& self) -> ReadRateControlR { ReadRateControlR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
# [must_use]
pub fn read_rate_control (& mut self) -> ReadRateControlW < RdrateSpec > { ReadRateControlW :: new (self , 0) } } # [doc = "Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrateSpec ; impl crate :: RegisterSpec for RdrateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rdrate::R`](R) reader structure"]
impl crate :: Readable for RdrateSpec { } # [doc = "`write(|w| ..)` method takes [`rdrate::W`](W) writer structure"]
impl crate :: Writable for RdrateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RDRATE to value 0"]
impl crate :: Resettable for RdrateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "POPT (rw) register accessor: Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@popt`]
module"]
# [doc (alias = "POPT")]
pub type Popt = crate :: Reg < popt :: PoptSpec > ; # [doc = "Prog Set Options"]
pub mod popt { # [doc = "Register `POPT` reader"]
pub type R = crate :: R < PoptSpec > ; # [doc = "Register `POPT` writer"]
pub type W = crate :: W < PoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < PoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < PoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < PoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < PoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < PoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < PoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < PoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < PoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PoptSpec ; impl crate :: RegisterSpec for PoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`popt::R`](R) reader structure"]
impl crate :: Readable for PoptSpec { } # [doc = "`write(|w| ..)` method takes [`popt::W`](W) writer structure"]
impl crate :: Writable for PoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets POPT to value 0"]
impl crate :: Resettable for PoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSRC (rw) register accessor: Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psrc`]
module"]
# [doc (alias = "PSRC")]
pub type Psrc = crate :: Reg < psrc :: PsrcSpec > ; # [doc = "Prog Set Src Address"]
pub mod psrc { # [doc = "Register `PSRC` reader"]
pub type R = crate :: R < PsrcSpec > ; # [doc = "Register `PSRC` writer"]
pub type W = crate :: W < PsrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR` reader - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR` writer - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
pub fn source_address_for (& self) -> SourceAddressForR { SourceAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for (& mut self) -> SourceAddressForW < PsrcSpec > { SourceAddressForW :: new (self , 0) } } # [doc = "Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsrcSpec ; impl crate :: RegisterSpec for PsrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`psrc::R`](R) reader structure"]
impl crate :: Readable for PsrcSpec { } # [doc = "`write(|w| ..)` method takes [`psrc::W`](W) writer structure"]
impl crate :: Writable for PsrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSRC to value 0"]
impl crate :: Resettable for PsrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCNT (rw) register accessor: Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcnt`]
module"]
# [doc (alias = "PCNT")]
pub type Pcnt = crate :: Reg < pcnt :: PcntSpec > ; # [doc = "Prog Set Count"]
pub mod pcnt { # [doc = "Register `PCNT` reader"]
pub type R = crate :: R < PcntSpec > ; # [doc = "Register `PCNT` writer"]
pub type W = crate :: W < PcntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` reader - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` writer - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
pub fn bdimension_count__number (& self) -> BdimensionCount_NumberR { BdimensionCount_NumberR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < PcntSpec > { AdimensionCount_NumberW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
# [must_use]
pub fn bdimension_count__number (& mut self) -> BdimensionCount_NumberW < PcntSpec > { BdimensionCount_NumberW :: new (self , 16) } } # [doc = "Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcntSpec ; impl crate :: RegisterSpec for PcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcnt::R`](R) reader structure"]
impl crate :: Readable for PcntSpec { } # [doc = "`write(|w| ..)` method takes [`pcnt::W`](W) writer structure"]
impl crate :: Writable for PcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCNT to value 0"]
impl crate :: Resettable for PcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PDST (rw) register accessor: Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdst`]
module"]
# [doc (alias = "PDST")]
pub type Pdst = crate :: Reg < pdst :: PdstSpec > ; # [doc = "Prog Set Dst Address"]
pub mod pdst { # [doc = "Register `PDST` reader"]
pub type R = crate :: R < PdstSpec > ; # [doc = "Register `PDST` writer"]
pub type W = crate :: W < PdstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` reader - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` writer - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
pub fn destination_address_for (& self) -> DestinationAddressForR { DestinationAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for (& mut self) -> DestinationAddressForW < PdstSpec > { DestinationAddressForW :: new (self , 0) } } # [doc = "Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PdstSpec ; impl crate :: RegisterSpec for PdstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pdst::R`](R) reader structure"]
impl crate :: Readable for PdstSpec { } # [doc = "`write(|w| ..)` method takes [`pdst::W`](W) writer structure"]
impl crate :: Writable for PdstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PDST to value 0"]
impl crate :: Resettable for PdstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIDX (rw) register accessor: Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbidx`]
module"]
# [doc (alias = "PBIDX")]
pub type Pbidx = crate :: Reg < pbidx :: PbidxSpec > ; # [doc = "Prog Set B-Dim Idx"]
pub mod pbidx { # [doc = "Register `PBIDX` reader"]
pub type R = crate :: R < PbidxSpec > ; # [doc = "Register `PBIDX` writer"]
pub type W = crate :: W < PbidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < PbidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < PbidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbidxSpec ; impl crate :: RegisterSpec for PbidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbidx::R`](R) reader structure"]
impl crate :: Readable for PbidxSpec { } # [doc = "`write(|w| ..)` method takes [`pbidx::W`](W) writer structure"]
impl crate :: Writable for PbidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIDX to value 0"]
impl crate :: Resettable for PbidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PMPPRXY (rw) register accessor: Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmpprxy`]
module"]
# [doc (alias = "PMPPRXY")]
pub type Pmpprxy = crate :: Reg < pmpprxy :: PmpprxySpec > ; # [doc = "Prog Set Mem Protect Proxy"]
pub mod pmpprxy { # [doc = "Register `PMPPRXY` reader"]
pub type R = crate :: R < PmpprxySpec > ; # [doc = "Register `PMPPRXY` writer"]
pub type W = crate :: W < PmpprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < PmpprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < PmpprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < PmpprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmpprxySpec ; impl crate :: RegisterSpec for PmpprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmpprxy::R`](R) reader structure"]
impl crate :: Readable for PmpprxySpec { } # [doc = "`write(|w| ..)` method takes [`pmpprxy::W`](W) writer structure"]
impl crate :: Writable for PmpprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PMPPRXY to value 0"]
impl crate :: Resettable for PmpprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAOPT (rw) register accessor: Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@saopt`]
module"]
# [doc (alias = "SAOPT")]
pub type Saopt = crate :: Reg < saopt :: SaoptSpec > ; # [doc = "Src Actv Set Options"]
pub mod saopt { # [doc = "Register `SAOPT` reader"]
pub type R = crate :: R < SaoptSpec > ; # [doc = "Register `SAOPT` writer"]
pub type W = crate :: W < SaoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < SaoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < SaoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < SaoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < SaoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < SaoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < SaoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < SaoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < SaoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SaoptSpec ; impl crate :: RegisterSpec for SaoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`saopt::R`](R) reader structure"]
impl crate :: Readable for SaoptSpec { } # [doc = "`write(|w| ..)` method takes [`saopt::W`](W) writer structure"]
impl crate :: Writable for SaoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAOPT to value 0"]
impl crate :: Resettable for SaoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRC (rw) register accessor: Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrc`]
module"]
# [doc (alias = "SASRC")]
pub type Sasrc = crate :: Reg < sasrc :: SasrcSpec > ; # [doc = "Src Actv Set Src Address"]
pub mod sasrc { # [doc = "Register `SASRC` reader"]
pub type R = crate :: R < SasrcSpec > ; # [doc = "Register `SASRC` writer"]
pub type W = crate :: W < SasrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` reader - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` writer - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
pub fn source_address_for_1 (& self) -> SourceAddressFor1R { SourceAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for_1 (& mut self) -> SourceAddressFor1W < SasrcSpec > { SourceAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcSpec ; impl crate :: RegisterSpec for SasrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrc::R`](R) reader structure"]
impl crate :: Readable for SasrcSpec { } # [doc = "`write(|w| ..)` method takes [`sasrc::W`](W) writer structure"]
impl crate :: Writable for SasrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRC to value 0"]
impl crate :: Resettable for SasrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNT (rw) register accessor: Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacnt`]
module"]
# [doc (alias = "SACNT")]
pub type Sacnt = crate :: Reg < sacnt :: SacntSpec > ; # [doc = "Src Actv Set A-Count"]
pub mod sacnt { # [doc = "Register `SACNT` reader"]
pub type R = crate :: R < SacntSpec > ; # [doc = "Register `SACNT` writer"]
pub type W = crate :: W < SacntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < SacntSpec > { AdimensionCount_NumberW :: new (self , 0) } } # [doc = "Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntSpec ; impl crate :: RegisterSpec for SacntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacnt::R`](R) reader structure"]
impl crate :: Readable for SacntSpec { } # [doc = "`write(|w| ..)` method takes [`sacnt::W`](W) writer structure"]
impl crate :: Writable for SacntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNT to value 0"]
impl crate :: Resettable for SacntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADST (rw) register accessor: Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadst`]
module"]
# [doc (alias = "SADST")]
pub type Sadst = crate :: Reg < sadst :: SadstSpec > ; # [doc = "Src Actv Set Dst Address"]
pub mod sadst { # [doc = "Register `SADST` reader"]
pub type R = crate :: R < SadstSpec > ; # [doc = "Register `SADST` writer"]
pub type W = crate :: W < SadstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` reader - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` writer - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
pub fn destination_address_for_1 (& self) -> DestinationAddressFor1R { DestinationAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for_1 (& mut self) -> DestinationAddressFor1W < SadstSpec > { DestinationAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstSpec ; impl crate :: RegisterSpec for SadstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadst::R`](R) reader structure"]
impl crate :: Readable for SadstSpec { } # [doc = "`write(|w| ..)` method takes [`sadst::W`](W) writer structure"]
impl crate :: Writable for SadstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADST to value 0"]
impl crate :: Resettable for SadstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABIDX (rw) register accessor: Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabidx`]
module"]
# [doc (alias = "SABIDX")]
pub type Sabidx = crate :: Reg < sabidx :: SabidxSpec > ; # [doc = "Src Actv Set B-Dim Idx"]
pub mod sabidx { # [doc = "Register `SABIDX` reader"]
pub type R = crate :: R < SabidxSpec > ; # [doc = "Register `SABIDX` writer"]
pub type W = crate :: W < SabidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < SabidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < SabidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabidxSpec ; impl crate :: RegisterSpec for SabidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabidx::R`](R) reader structure"]
impl crate :: Readable for SabidxSpec { } # [doc = "`write(|w| ..)` method takes [`sabidx::W`](W) writer structure"]
impl crate :: Writable for SabidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABIDX to value 0"]
impl crate :: Resettable for SabidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAMPPRXY (rw) register accessor: Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sampprxy`]
module"]
# [doc (alias = "SAMPPRXY")]
pub type Sampprxy = crate :: Reg < sampprxy :: SampprxySpec > ; # [doc = "Src Actv Set Mem Protect Proxy"]
pub mod sampprxy { # [doc = "Register `SAMPPRXY` reader"]
pub type R = crate :: R < SampprxySpec > ; # [doc = "Register `SAMPPRXY` writer"]
pub type W = crate :: W < SampprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < SampprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < SampprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < SampprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SampprxySpec ; impl crate :: RegisterSpec for SampprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sampprxy::R`](R) reader structure"]
impl crate :: Readable for SampprxySpec { } # [doc = "`write(|w| ..)` method takes [`sampprxy::W`](W) writer structure"]
impl crate :: Writable for SampprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAMPPRXY to value 0"]
impl crate :: Resettable for SampprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNTRLD (rw) register accessor: Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacntrld`]
module"]
# [doc (alias = "SACNTRLD")]
pub type Sacntrld = crate :: Reg < sacntrld :: SacntrldSpec > ; # [doc = "Src Actv Set Cnt Reload"]
pub mod sacntrld { # [doc = "Register `SACNTRLD` reader"]
pub type R = crate :: R < SacntrldSpec > ; # [doc = "Register `SACNTRLD` writer"]
pub type W = crate :: W < SacntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE` reader - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueR = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE` writer - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value (& self) -> AcntReloadValueR { AcntReloadValueR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value (& mut self) -> AcntReloadValueW < SacntrldSpec > { AcntReloadValueW :: new (self , 0) } } # [doc = "Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntrldSpec ; impl crate :: RegisterSpec for SacntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacntrld::R`](R) reader structure"]
impl crate :: Readable for SacntrldSpec { } # [doc = "`write(|w| ..)` method takes [`sacntrld::W`](W) writer structure"]
impl crate :: Writable for SacntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNTRLD to value 0"]
impl crate :: Resettable for SacntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRCBREF (rw) register accessor: Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrcbref`]
module"]
# [doc (alias = "SASRCBREF")]
pub type Sasrcbref = crate :: Reg < sasrcbref :: SasrcbrefSpec > ; # [doc = "Src Actv Set Src Addr B-Reference"]
pub mod sasrcbref { # [doc = "Register `SASRCBREF` reader"]
pub type R = crate :: R < SasrcbrefSpec > ; # [doc = "Register `SASRCBREF` writer"]
pub type W = crate :: W < SasrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` reader - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` writer - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference (& self) -> SourceAddressReferenceR { SourceAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference (& mut self) -> SourceAddressReferenceW < SasrcbrefSpec > { SourceAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcbrefSpec ; impl crate :: RegisterSpec for SasrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrcbref::R`](R) reader structure"]
impl crate :: Readable for SasrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sasrcbref::W`](W) writer structure"]
impl crate :: Writable for SasrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRCBREF to value 0"]
impl crate :: Resettable for SasrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADSTBREF (rw) register accessor: Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadstbref`]
module"]
# [doc (alias = "SADSTBREF")]
pub type Sadstbref = crate :: Reg < sadstbref :: SadstbrefSpec > ; # [doc = "Src Actv Set Dst Addr B-Reference"]
pub mod sadstbref { # [doc = "Register `SADSTBREF` reader"]
pub type R = crate :: R < SadstbrefSpec > ; # [doc = "Register `SADSTBREF` writer"]
pub type W = crate :: W < SadstbrefSpec > ; # [doc = "Field `DST_ADDRESS_REFERENCE` reader - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `DST_ADDRESS_REFERENCE` writer - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
pub fn dst_address_reference (& self) -> DstAddressReferenceR { DstAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn dst_address_reference (& mut self) -> DstAddressReferenceW < SadstbrefSpec > { DstAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstbrefSpec ; impl crate :: RegisterSpec for SadstbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadstbref::R`](R) reader structure"]
impl crate :: Readable for SadstbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sadstbref::W`](W) writer structure"]
impl crate :: Writable for SadstbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADSTBREF to value 0"]
impl crate :: Resettable for SadstbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABCNT (rw) register accessor: Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabcnt`]
module"]
# [doc (alias = "SABCNT")]
pub type Sabcnt = crate :: Reg < sabcnt :: SabcntSpec > ; # [doc = "Src Actv Set B-Count"]
pub mod sabcnt { # [doc = "Register `SABCNT` reader"]
pub type R = crate :: R < SabcntSpec > ; # [doc = "Register `SABCNT` writer"]
pub type W = crate :: W < SabcntSpec > ; # [doc = "Field `BDIMENSION_COUNT` reader - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT` writer - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bdimension_count (& self) -> BdimensionCountR { BdimensionCountR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bdimension_count (& mut self) -> BdimensionCountW < SabcntSpec > { BdimensionCountW :: new (self , 0) } } # [doc = "Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabcntSpec ; impl crate :: RegisterSpec for SabcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabcnt::R`](R) reader structure"]
impl crate :: Readable for SabcntSpec { } # [doc = "`write(|w| ..)` method takes [`sabcnt::W`](W) writer structure"]
impl crate :: Writable for SabcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABCNT to value 0"]
impl crate :: Resettable for SabcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFCNTRLD (rw) register accessor: Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfcntrld`]
module"]
# [doc (alias = "DFCNTRLD")]
pub type Dfcntrld = crate :: Reg < dfcntrld :: DfcntrldSpec > ; # [doc = "Dst FIFO Set Cnt Reload"]
pub mod dfcntrld { # [doc = "Register `DFCNTRLD` reader"]
pub type R = crate :: R < DfcntrldSpec > ; # [doc = "Register `DFCNTRLD` writer"]
pub type W = crate :: W < DfcntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` reader - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1R = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` writer - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value_1 (& self) -> AcntReloadValue1R { AcntReloadValue1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value_1 (& mut self) -> AcntReloadValue1W < DfcntrldSpec > { AcntReloadValue1W :: new (self , 0) } } # [doc = "Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfcntrldSpec ; impl crate :: RegisterSpec for DfcntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfcntrld::R`](R) reader structure"]
impl crate :: Readable for DfcntrldSpec { } # [doc = "`write(|w| ..)` method takes [`dfcntrld::W`](W) writer structure"]
impl crate :: Writable for DfcntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFCNTRLD to value 0"]
impl crate :: Resettable for DfcntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRCBREF (rw) register accessor: Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrcbref`]
module"]
# [doc (alias = "DFSRCBREF")]
pub type Dfsrcbref = crate :: Reg < dfsrcbref :: DfsrcbrefSpec > ; # [doc = "Dst FIFO Set Src Addr B-Reference"]
pub mod dfsrcbref { # [doc = "Register `DFSRCBREF` reader"]
pub type R = crate :: R < DfsrcbrefSpec > ; # [doc = "Register `DFSRCBREF` writer"]
pub type W = crate :: W < DfsrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` reader - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` writer - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference_1 (& self) -> SourceAddressReference1R { SourceAddressReference1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference_1 (& mut self) -> SourceAddressReference1W < DfsrcbrefSpec > { SourceAddressReference1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfsrcbrefSpec ; impl crate :: RegisterSpec for DfsrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrcbref::R`](R) reader structure"]
impl crate :: Readable for DfsrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`dfsrcbref::W`](W) writer structure"]
impl crate :: Writable for DfsrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRCBREF to value 0"]
impl crate :: Resettable for DfsrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT0 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt0`]
module"]
# [doc (alias = "DFOPT0")]
pub type Dfopt0 = crate :: Reg < dfopt0 :: Dfopt0Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt0 { # [doc = "Register `DFOPT0` reader"]
pub type R = crate :: R < Dfopt0Spec > ; # [doc = "Register `DFOPT0` writer"]
pub type W = crate :: W < Dfopt0Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt0Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt0Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt0Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt0Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt0Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt0Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt0Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt0Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt0Spec ; impl crate :: RegisterSpec for Dfopt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt0::R`](R) reader structure"]
impl crate :: Readable for Dfopt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt0::W`](W) writer structure"]
impl crate :: Writable for Dfopt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT0 to value 0"]
impl crate :: Resettable for Dfopt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC0 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc0`]
module"]
# [doc (alias = "DFSRC0")]
pub type Dfsrc0 = crate :: Reg < dfsrc0 :: Dfsrc0Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc0 { # [doc = "Register `DFSRC0` reader"]
pub type R = crate :: R < Dfsrc0Spec > ; # [doc = "Register `DFSRC0` writer"]
pub type W = crate :: W < Dfsrc0Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is (& self) -> SourceAddressIsR { SourceAddressIsR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is (& mut self) -> SourceAddressIsW < Dfsrc0Spec > { SourceAddressIsW :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc0Spec ; impl crate :: RegisterSpec for Dfsrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc0::R`](R) reader structure"]
impl crate :: Readable for Dfsrc0Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc0::W`](W) writer structure"]
impl crate :: Writable for Dfsrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC0 to value 0"]
impl crate :: Resettable for Dfsrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT0 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt0`]
module"]
# [doc (alias = "DFACNT0")]
pub type Dfacnt0 = crate :: Reg < dfacnt0 :: Dfacnt0Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt0 { # [doc = "Register `DFACNT0` reader"]
pub type R = crate :: R < Dfacnt0Spec > ; # [doc = "Register `DFACNT0` writer"]
pub type W = crate :: W < Dfacnt0Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_1 (& self) -> AdimensionCount_Number1R { AdimensionCount_Number1R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_1 (& mut self) -> AdimensionCount_Number1W < Dfacnt0Spec > { AdimensionCount_Number1W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt0Spec ; impl crate :: RegisterSpec for Dfacnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt0::R`](R) reader structure"]
impl crate :: Readable for Dfacnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt0::W`](W) writer structure"]
impl crate :: Writable for Dfacnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT0 to value 0"]
impl crate :: Resettable for Dfacnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST0 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst0`]
module"]
# [doc (alias = "DFDST0")]
pub type Dfdst0 = crate :: Reg < dfdst0 :: Dfdst0Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst0 { # [doc = "Register `DFDST0` reader"]
pub type R = crate :: R < Dfdst0Spec > ; # [doc = "Register `DFDST0` writer"]
pub type W = crate :: W < Dfdst0Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_2 (& self) -> DestinationAddressFor2R { DestinationAddressFor2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_2 (& mut self) -> DestinationAddressFor2W < Dfdst0Spec > { DestinationAddressFor2W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst0Spec ; impl crate :: RegisterSpec for Dfdst0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst0::R`](R) reader structure"]
impl crate :: Readable for Dfdst0Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst0::W`](W) writer structure"]
impl crate :: Writable for Dfdst0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST0 to value 0"]
impl crate :: Resettable for Dfdst0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX0 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx0`]
module"]
# [doc (alias = "DFBIDX0")]
pub type Dfbidx0 = crate :: Reg < dfbidx0 :: Dfbidx0Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx0 { # [doc = "Register `DFBIDX0` reader"]
pub type R = crate :: R < Dfbidx0Spec > ; # [doc = "Register `DFBIDX0` writer"]
pub type W = crate :: W < Dfbidx0Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx0Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx0Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx0Spec ; impl crate :: RegisterSpec for Dfbidx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx0::R`](R) reader structure"]
impl crate :: Readable for Dfbidx0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx0::W`](W) writer structure"]
impl crate :: Writable for Dfbidx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX0 to value 0"]
impl crate :: Resettable for Dfbidx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY0 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy0`]
module"]
# [doc (alias = "DFMPPRXY0")]
pub type Dfmpprxy0 = crate :: Reg < dfmpprxy0 :: Dfmpprxy0Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy0 { # [doc = "Register `DFMPPRXY0` reader"]
pub type R = crate :: R < Dfmpprxy0Spec > ; # [doc = "Register `DFMPPRXY0` writer"]
pub type W = crate :: W < Dfmpprxy0Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy0Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy0Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy0Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy0Spec ; impl crate :: RegisterSpec for Dfmpprxy0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy0::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy0Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy0::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY0 to value 0"]
impl crate :: Resettable for Dfmpprxy0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT0 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt0`]
module"]
# [doc (alias = "DFBCNT0")]
pub type Dfbcnt0 = crate :: Reg < dfbcnt0 :: Dfbcnt0Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt0 { # [doc = "Register `DFBCNT0` reader"]
pub type R = crate :: R < Dfbcnt0Spec > ; # [doc = "Register `DFBCNT0` writer"]
pub type W = crate :: W < Dfbcnt0Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForR = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for (& self) -> BcountRemainingForR { BcountRemainingForR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for (& mut self) -> BcountRemainingForW < Dfbcnt0Spec > { BcountRemainingForW :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt0Spec ; impl crate :: RegisterSpec for Dfbcnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt0::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt0::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT0 to value 0"]
impl crate :: Resettable for Dfbcnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT1 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt1`]
module"]
# [doc (alias = "DFOPT1")]
pub type Dfopt1 = crate :: Reg < dfopt1 :: Dfopt1Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt1 { # [doc = "Register `DFOPT1` reader"]
pub type R = crate :: R < Dfopt1Spec > ; # [doc = "Register `DFOPT1` writer"]
pub type W = crate :: W < Dfopt1Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt1Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt1Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt1Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt1Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt1Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt1Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt1Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt1Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt1Spec ; impl crate :: RegisterSpec for Dfopt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt1::R`](R) reader structure"]
impl crate :: Readable for Dfopt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt1::W`](W) writer structure"]
impl crate :: Writable for Dfopt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT1 to value 0"]
impl crate :: Resettable for Dfopt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC1 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc1`]
module"]
# [doc (alias = "DFSRC1")]
pub type Dfsrc1 = crate :: Reg < dfsrc1 :: Dfsrc1Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc1 { # [doc = "Register `DFSRC1` reader"]
pub type R = crate :: R < Dfsrc1Spec > ; # [doc = "Register `DFSRC1` writer"]
pub type W = crate :: W < Dfsrc1Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is_1 (& self) -> SourceAddressIs1R { SourceAddressIs1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is_1 (& mut self) -> SourceAddressIs1W < Dfsrc1Spec > { SourceAddressIs1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc1Spec ; impl crate :: RegisterSpec for Dfsrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc1::R`](R) reader structure"]
impl crate :: Readable for Dfsrc1Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc1::W`](W) writer structure"]
impl crate :: Writable for Dfsrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC1 to value 0"]
impl crate :: Resettable for Dfsrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT1 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt1`]
module"]
# [doc (alias = "DFACNT1")]
pub type Dfacnt1 = crate :: Reg < dfacnt1 :: Dfacnt1Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt1 { # [doc = "Register `DFACNT1` reader"]
pub type R = crate :: R < Dfacnt1Spec > ; # [doc = "Register `DFACNT1` writer"]
pub type W = crate :: W < Dfacnt1Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_2 (& self) -> AdimensionCount_Number2R { AdimensionCount_Number2R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_2 (& mut self) -> AdimensionCount_Number2W < Dfacnt1Spec > { AdimensionCount_Number2W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt1Spec ; impl crate :: RegisterSpec for Dfacnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt1::R`](R) reader structure"]
impl crate :: Readable for Dfacnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt1::W`](W) writer structure"]
impl crate :: Writable for Dfacnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT1 to value 0"]
impl crate :: Resettable for Dfacnt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST1 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst1`]
module"]
# [doc (alias = "DFDST1")]
pub type Dfdst1 = crate :: Reg < dfdst1 :: Dfdst1Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst1 { # [doc = "Register `DFDST1` reader"]
pub type R = crate :: R < Dfdst1Spec > ; # [doc = "Register `DFDST1` writer"]
pub type W = crate :: W < Dfdst1Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_3 (& self) -> DestinationAddressFor3R { DestinationAddressFor3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_3 (& mut self) -> DestinationAddressFor3W < Dfdst1Spec > { DestinationAddressFor3W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst1Spec ; impl crate :: RegisterSpec for Dfdst1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst1::R`](R) reader structure"]
impl crate :: Readable for Dfdst1Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst1::W`](W) writer structure"]
impl crate :: Writable for Dfdst1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST1 to value 0"]
impl crate :: Resettable for Dfdst1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX1 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx1`]
module"]
# [doc (alias = "DFBIDX1")]
pub type Dfbidx1 = crate :: Reg < dfbidx1 :: Dfbidx1Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx1 { # [doc = "Register `DFBIDX1` reader"]
pub type R = crate :: R < Dfbidx1Spec > ; # [doc = "Register `DFBIDX1` writer"]
pub type W = crate :: W < Dfbidx1Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx1Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx1Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx1Spec ; impl crate :: RegisterSpec for Dfbidx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx1::R`](R) reader structure"]
impl crate :: Readable for Dfbidx1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx1::W`](W) writer structure"]
impl crate :: Writable for Dfbidx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX1 to value 0"]
impl crate :: Resettable for Dfbidx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY1 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy1`]
module"]
# [doc (alias = "DFMPPRXY1")]
pub type Dfmpprxy1 = crate :: Reg < dfmpprxy1 :: Dfmpprxy1Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy1 { # [doc = "Register `DFMPPRXY1` reader"]
pub type R = crate :: R < Dfmpprxy1Spec > ; # [doc = "Register `DFMPPRXY1` writer"]
pub type W = crate :: W < Dfmpprxy1Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy1Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy1Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy1Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy1Spec ; impl crate :: RegisterSpec for Dfmpprxy1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy1::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy1Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy1::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY1 to value 0"]
impl crate :: Resettable for Dfmpprxy1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT1 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt1`]
module"]
# [doc (alias = "DFBCNT1")]
pub type Dfbcnt1 = crate :: Reg < dfbcnt1 :: Dfbcnt1Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt1 { # [doc = "Register `DFBCNT1` reader"]
pub type R = crate :: R < Dfbcnt1Spec > ; # [doc = "Register `DFBCNT1` writer"]
pub type W = crate :: W < Dfbcnt1Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1R = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for_1 (& self) -> BcountRemainingFor1R { BcountRemainingFor1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for_1 (& mut self) -> BcountRemainingFor1W < Dfbcnt1Spec > { BcountRemainingFor1W :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt1Spec ; impl crate :: RegisterSpec for Dfbcnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt1::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt1::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT1 to value 0"]
impl crate :: Resettable for Dfbcnt1Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Register test environment"]
pub struct TptcB0_1 { _marker : PhantomData < * const () > } unsafe impl Send for TptcB0_1 { } impl TptcB0_1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tptc_b0_1 :: RegisterBlock = 0x5504_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tptc_b0_1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TptcB0_1 { type Target = tptc_b0_1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TptcB0_1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TptcB0_1") . finish () } } # [doc = "Register test environment"]
pub mod tptc_b0_1 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , tccfg : Tccfg , _reserved2 : [u8 ; 0xf8]
, tcstat : Tcstat , intstat : Intstat , inten : Inten , intclr : Intclr , intcmd : Intcmd , _reserved7 : [u8 ; 0x0c]
, errstat : Errstat , erren : Erren , errclr : Errclr , errdet : Errdet , errcmd : Errcmd , _reserved12 : [u8 ; 0x0c]
, rdrate : Rdrate , _reserved13 : [u8 ; 0xbc]
, popt : Popt , psrc : Psrc , pcnt : Pcnt , pdst : Pdst , pbidx : Pbidx , pmpprxy : Pmpprxy , _reserved19 : [u8 ; 0x28]
, saopt : Saopt , sasrc : Sasrc , sacnt : Sacnt , sadst : Sadst , sabidx : Sabidx , sampprxy : Sampprxy , sacntrld : Sacntrld , sasrcbref : Sasrcbref , sadstbref : Sadstbref , sabcnt : Sabcnt , _reserved29 : [u8 ; 0x18]
, dfcntrld : Dfcntrld , dfsrcbref : Dfsrcbref , _reserved31 : [u8 ; 0x78]
, dfopt0 : Dfopt0 , dfsrc0 : Dfsrc0 , dfacnt0 : Dfacnt0 , dfdst0 : Dfdst0 , dfbidx0 : Dfbidx0 , dfmpprxy0 : Dfmpprxy0 , dfbcnt0 : Dfbcnt0 , _reserved38 : [u8 ; 0x24]
, dfopt1 : Dfopt1 , dfsrc1 : Dfsrc1 , dfacnt1 : Dfacnt1 , dfdst1 : Dfdst1 , dfbidx1 : Dfbidx1 , dfmpprxy1 : Dfmpprxy1 , dfbcnt1 : Dfbcnt1 , } impl RegisterBlock { # [doc = "0x00 - Peripheral ID Register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - TC Configuration Register"]
# [inline (always)]
pub const fn tccfg (& self) -> & Tccfg { & self . tccfg } # [doc = "0x100 - TC Status Register"]
# [inline (always)]
pub const fn tcstat (& self) -> & Tcstat { & self . tcstat } # [doc = "0x104 - Interrupt Status Register"]
# [inline (always)]
pub const fn intstat (& self) -> & Intstat { & self . intstat } # [doc = "0x108 - Interrupt Enable Register"]
# [inline (always)]
pub const fn inten (& self) -> & Inten { & self . inten } # [doc = "0x10c - Interrupt Clear Register"]
# [inline (always)]
pub const fn intclr (& self) -> & Intclr { & self . intclr } # [doc = "0x110 - Interrupt Command Register"]
# [inline (always)]
pub const fn intcmd (& self) -> & Intcmd { & self . intcmd } # [doc = "0x120 - Error Status Register"]
# [inline (always)]
pub const fn errstat (& self) -> & Errstat { & self . errstat } # [doc = "0x124 - Error Enable Register"]
# [inline (always)]
pub const fn erren (& self) -> & Erren { & self . erren } # [doc = "0x128 - Error Clear Register"]
# [inline (always)]
pub const fn errclr (& self) -> & Errclr { & self . errclr } # [doc = "0x12c - Error Details Register"]
# [inline (always)]
pub const fn errdet (& self) -> & Errdet { & self . errdet } # [doc = "0x130 - Error Command Register"]
# [inline (always)]
pub const fn errcmd (& self) -> & Errcmd { & self . errcmd } # [doc = "0x140 - Read Rate Register"]
# [inline (always)]
pub const fn rdrate (& self) -> & Rdrate { & self . rdrate } # [doc = "0x200 - Prog Set Options"]
# [inline (always)]
pub const fn popt (& self) -> & Popt { & self . popt } # [doc = "0x204 - Prog Set Src Address"]
# [inline (always)]
pub const fn psrc (& self) -> & Psrc { & self . psrc } # [doc = "0x208 - Prog Set Count"]
# [inline (always)]
pub const fn pcnt (& self) -> & Pcnt { & self . pcnt } # [doc = "0x20c - Prog Set Dst Address"]
# [inline (always)]
pub const fn pdst (& self) -> & Pdst { & self . pdst } # [doc = "0x210 - Prog Set B-Dim Idx"]
# [inline (always)]
pub const fn pbidx (& self) -> & Pbidx { & self . pbidx } # [doc = "0x214 - Prog Set Mem Protect Proxy"]
# [inline (always)]
pub const fn pmpprxy (& self) -> & Pmpprxy { & self . pmpprxy } # [doc = "0x240 - Src Actv Set Options"]
# [inline (always)]
pub const fn saopt (& self) -> & Saopt { & self . saopt } # [doc = "0x244 - Src Actv Set Src Address"]
# [inline (always)]
pub const fn sasrc (& self) -> & Sasrc { & self . sasrc } # [doc = "0x248 - Src Actv Set A-Count"]
# [inline (always)]
pub const fn sacnt (& self) -> & Sacnt { & self . sacnt } # [doc = "0x24c - Src Actv Set Dst Address"]
# [inline (always)]
pub const fn sadst (& self) -> & Sadst { & self . sadst } # [doc = "0x250 - Src Actv Set B-Dim Idx"]
# [inline (always)]
pub const fn sabidx (& self) -> & Sabidx { & self . sabidx } # [doc = "0x254 - Src Actv Set Mem Protect Proxy"]
# [inline (always)]
pub const fn sampprxy (& self) -> & Sampprxy { & self . sampprxy } # [doc = "0x258 - Src Actv Set Cnt Reload"]
# [inline (always)]
pub const fn sacntrld (& self) -> & Sacntrld { & self . sacntrld } # [doc = "0x25c - Src Actv Set Src Addr B-Reference"]
# [inline (always)]
pub const fn sasrcbref (& self) -> & Sasrcbref { & self . sasrcbref } # [doc = "0x260 - Src Actv Set Dst Addr B-Reference"]
# [inline (always)]
pub const fn sadstbref (& self) -> & Sadstbref { & self . sadstbref } # [doc = "0x264 - Src Actv Set B-Count"]
# [inline (always)]
pub const fn sabcnt (& self) -> & Sabcnt { & self . sabcnt } # [doc = "0x280 - Dst FIFO Set Cnt Reload"]
# [inline (always)]
pub const fn dfcntrld (& self) -> & Dfcntrld { & self . dfcntrld } # [doc = "0x284 - Dst FIFO Set Src Addr B-Reference"]
# [inline (always)]
pub const fn dfsrcbref (& self) -> & Dfsrcbref { & self . dfsrcbref } # [doc = "0x300 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt0 (& self) -> & Dfopt0 { & self . dfopt0 } # [doc = "0x304 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc0 (& self) -> & Dfsrc0 { & self . dfsrc0 } # [doc = "0x308 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt0 (& self) -> & Dfacnt0 { & self . dfacnt0 } # [doc = "0x30c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst0 (& self) -> & Dfdst0 { & self . dfdst0 } # [doc = "0x310 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx0 (& self) -> & Dfbidx0 { & self . dfbidx0 } # [doc = "0x314 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy0 (& self) -> & Dfmpprxy0 { & self . dfmpprxy0 } # [doc = "0x318 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt0 (& self) -> & Dfbcnt0 { & self . dfbcnt0 } # [doc = "0x340 - Dst FIFO Set Options"]
# [inline (always)]
pub const fn dfopt1 (& self) -> & Dfopt1 { & self . dfopt1 } # [doc = "0x344 - Dst FIFO Set Src Address"]
# [inline (always)]
pub const fn dfsrc1 (& self) -> & Dfsrc1 { & self . dfsrc1 } # [doc = "0x348 - Dst FIFO Set A-Count"]
# [inline (always)]
pub const fn dfacnt1 (& self) -> & Dfacnt1 { & self . dfacnt1 } # [doc = "0x34c - Dst FIFO Set Dst Address"]
# [inline (always)]
pub const fn dfdst1 (& self) -> & Dfdst1 { & self . dfdst1 } # [doc = "0x350 - Dst FIFO Set B-Dim Idx"]
# [inline (always)]
pub const fn dfbidx1 (& self) -> & Dfbidx1 { & self . dfbidx1 } # [doc = "0x354 - Dst FIFO Set Mem Protect Proxy"]
# [inline (always)]
pub const fn dfmpprxy1 (& self) -> & Dfmpprxy1 { & self . dfmpprxy1 } # [doc = "0x358 - Dst FIFO Set B-Count"]
# [inline (always)]
pub const fn dfbcnt1 (& self) -> & Dfbcnt1 { & self . dfbcnt1 } } # [doc = "PID (rw) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "Peripheral ID Register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR_REVISION` reader - 5:0\\]
Minor Revision"]
pub type MinorRevisionR = crate :: FieldReader ; # [doc = "Field `MINOR_REVISION` writer - 5:0\\]
Minor Revision"]
pub type MinorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM_REVISION_FIELD` reader - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldR = crate :: FieldReader ; # [doc = "Field `CUSTOM_REVISION_FIELD` writer - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomRevisionFieldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR_REVISION` reader - 10:8\\]
Major Revision"]
pub type MajorRevisionR = crate :: FieldReader ; # [doc = "Field `MAJOR_REVISION` writer - 10:8\\]
Major Revision"]
pub type MajorRevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL_VERSION` reader - 15:11\\]
RTL Version"]
pub type RtlVersionR = crate :: FieldReader ; # [doc = "Field `RTL_VERSION` writer - 15:11\\]
RTL Version"]
pub type RtlVersionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNCTION_INDICATES_A` reader - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNCTION_INDICATES_A` writer - 27:16\\]
Function indicates a software compatible module family."]
pub type FunctionIndicatesAW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `PID_SCHEME` reader - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeR = crate :: FieldReader ; # [doc = "Field `PID_SCHEME` writer - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type PidSchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
pub fn minor_revision (& self) -> MinorRevisionR { MinorRevisionR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
pub fn custom_revision_field (& self) -> CustomRevisionFieldR { CustomRevisionFieldR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
pub fn major_revision (& self) -> MajorRevisionR { MajorRevisionR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
pub fn rtl_version (& self) -> RtlVersionR { RtlVersionR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
pub fn function_indicates_a (& self) -> FunctionIndicatesAR { FunctionIndicatesAR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
pub fn pid_scheme (& self) -> PidSchemeR { PidSchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
# [must_use]
pub fn minor_revision (& mut self) -> MinorRevisionW < PidSpec > { MinorRevisionW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
# [must_use]
pub fn custom_revision_field (& mut self) -> CustomRevisionFieldW < PidSpec > { CustomRevisionFieldW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
# [must_use]
pub fn major_revision (& mut self) -> MajorRevisionW < PidSpec > { MajorRevisionW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
# [must_use]
pub fn rtl_version (& mut self) -> RtlVersionW < PidSpec > { RtlVersionW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
# [must_use]
pub fn function_indicates_a (& mut self) -> FunctionIndicatesAW < PidSpec > { FunctionIndicatesAW :: new (self , 16) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
# [must_use]
pub fn pid_scheme (& mut self) -> PidSchemeW < PidSpec > { PidSchemeW :: new (self , 30) } } # [doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCCFG (rw) register accessor: TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tccfg`]
module"]
# [doc (alias = "TCCFG")]
pub type Tccfg = crate :: Reg < tccfg :: TccfgSpec > ; # [doc = "TC Configuration Register"]
pub mod tccfg { # [doc = "Register `TCCFG` reader"]
pub type R = crate :: R < TccfgSpec > ; # [doc = "Register `TCCFG` writer"]
pub type W = crate :: W < TccfgSpec > ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` reader - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationR = crate :: FieldReader ; # [doc = "Field `FIFO_SIZE_PARAMETERIZATION` writer - 2:0\\]
Fifo Size Parameterization"]
pub type FifoSizeParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` reader - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationR = crate :: FieldReader ; # [doc = "Field `BUS_WIDTH_PARAMETERIZATION` writer - 5:4\\]
Bus Width Parameterization"]
pub type BusWidthParameterizationW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DST_REGISTER_FIFO` reader - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoR = crate :: FieldReader ; # [doc = "Field `DST_REGISTER_FIFO` writer - 9:8\\]
Dst Register FIFO Depth Parameterization"]
pub type DstRegisterFifoW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
pub fn fifo_size_parameterization (& self) -> FifoSizeParameterizationR { FifoSizeParameterizationR :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
pub fn bus_width_parameterization (& self) -> BusWidthParameterizationR { BusWidthParameterizationR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
pub fn dst_register_fifo (& self) -> DstRegisterFifoR { DstRegisterFifoR :: new (((self . bits >> 8) & 3) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Fifo Size Parameterization"]
# [inline (always)]
# [must_use]
pub fn fifo_size_parameterization (& mut self) -> FifoSizeParameterizationW < TccfgSpec > { FifoSizeParameterizationW :: new (self , 0) } # [doc = "Bits 4:5 - 5:4\\]
Bus Width Parameterization"]
# [inline (always)]
# [must_use]
pub fn bus_width_parameterization (& mut self) -> BusWidthParameterizationW < TccfgSpec > { BusWidthParameterizationW :: new (self , 4) } # [doc = "Bits 8:9 - 9:8\\]
Dst Register FIFO Depth Parameterization"]
# [inline (always)]
# [must_use]
pub fn dst_register_fifo (& mut self) -> DstRegisterFifoW < TccfgSpec > { DstRegisterFifoW :: new (self , 8) } } # [doc = "TC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TccfgSpec ; impl crate :: RegisterSpec for TccfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tccfg::R`](R) reader structure"]
impl crate :: Readable for TccfgSpec { } # [doc = "`write(|w| ..)` method takes [`tccfg::W`](W) writer structure"]
impl crate :: Writable for TccfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCCFG to value 0"]
impl crate :: Resettable for TccfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCSTAT (rw) register accessor: TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcstat`]
module"]
# [doc (alias = "TCSTAT")]
pub type Tcstat = crate :: Reg < tcstat :: TcstatSpec > ; # [doc = "TC Status Register"]
pub mod tcstat { # [doc = "Register `TCSTAT` reader"]
pub type R = crate :: R < TcstatSpec > ; # [doc = "Register `TCSTAT` writer"]
pub type W = crate :: W < TcstatSpec > ; # [doc = "Field `PROGRAM_REGISTER_SET` reader - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetR = crate :: BitReader ; # [doc = "Field `PROGRAM_REGISTER_SET` writer - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
pub type ProgramRegisterSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOURCE_ACTIVE_STATE` reader - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateR = crate :: BitReader ; # [doc = "Field `SOURCE_ACTIVE_STATE` writer - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
pub type SourceActiveStateW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WRITE_STATUS_ACTIVE` reader - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveR = crate :: BitReader ; # [doc = "Field `WRITE_STATUS_ACTIVE` writer - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
pub type WriteStatusActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ACTIVE_STATE` reader - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateR = crate :: FieldReader ; # [doc = "Field `DESTINATION_ACTIVE_STATE` writer - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
pub type DestinationActiveStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CHANNEL_ACTIVE` reader - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveR = crate :: BitReader ; # [doc = "Field `CHANNEL_ACTIVE` writer - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
pub type ChannelActiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DST_FIFO_START` reader - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartR = crate :: FieldReader ; # [doc = "Field `DST_FIFO_START` writer - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
pub type DstFifoStartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
pub fn program_register_set (& self) -> ProgramRegisterSetR { ProgramRegisterSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
pub fn source_active_state (& self) -> SourceActiveStateR { SourceActiveStateR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
pub fn write_status_active (& self) -> WriteStatusActiveR { WriteStatusActiveR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
pub fn destination_active_state (& self) -> DestinationActiveStateR { DestinationActiveStateR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
pub fn channel_active (& self) -> ChannelActiveR { ChannelActiveR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
pub fn dst_fifo_start (& self) -> DstFifoStartR { DstFifoStartR :: new (((self . bits >> 12) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set."]
# [inline (always)]
# [must_use]
pub fn program_register_set (& mut self) -> ProgramRegisterSetW < TcstatSpec > { ProgramRegisterSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full \\[DSTFULL == 1\\].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request."]
# [inline (always)]
# [must_use]
pub fn source_active_state (& mut self) -> SourceActiveStateW < TcstatSpec > { SourceActiveStateW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands."]
# [inline (always)]
# [must_use]
pub fn write_status_active (& mut self) -> WriteStatusActiveW < TcstatSpec > { WriteStatusActiveW :: new (self , 2) } # [doc = "Bits 4:6 - 6:4\\]
Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter."]
# [inline (always)]
# [must_use]
pub fn destination_active_state (& mut self) -> DestinationActiveStateW < TcstatSpec > { DestinationActiveStateW :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy."]
# [inline (always)]
# [must_use]
pub fn channel_active (& mut self) -> ChannelActiveW < TcstatSpec > { ChannelActiveW :: new (self , 8) } # [doc = "Bits 12:13 - 13:12\\]
Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3"]
# [inline (always)]
# [must_use]
pub fn dst_fifo_start (& mut self) -> DstFifoStartW < TcstatSpec > { DstFifoStartW :: new (self , 12) } } # [doc = "TC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcstatSpec ; impl crate :: RegisterSpec for TcstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tcstat::R`](R) reader structure"]
impl crate :: Readable for TcstatSpec { } # [doc = "`write(|w| ..)` method takes [`tcstat::W`](W) writer structure"]
impl crate :: Writable for TcstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TCSTAT to value 0"]
impl crate :: Resettable for TcstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTSTAT (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstat`]
module"]
# [doc (alias = "INTSTAT")]
pub type Intstat = crate :: Reg < intstat :: IntstatSpec > ; # [doc = "Interrupt Status Register"]
pub mod intstat { # [doc = "Register `INTSTAT` reader"]
pub type R = crate :: R < IntstatSpec > ; # [doc = "Register `INTSTAT` writer"]
pub type W = crate :: W < IntstatSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit."]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntstatSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit."]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntstatSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntstatSpec ; impl crate :: RegisterSpec for IntstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intstat::R`](R) reader structure"]
impl crate :: Readable for IntstatSpec { } # [doc = "`write(|w| ..)` method takes [`intstat::W`](W) writer structure"]
impl crate :: Writable for IntstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTSTAT to value 0"]
impl crate :: Resettable for IntstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
# [doc (alias = "INTEN")]
pub type Inten = crate :: Reg < inten :: IntenSpec > ; # [doc = "Interrupt Enable Register"]
pub mod inten { # [doc = "Register `INTEN` reader"]
pub type R = crate :: R < IntenSpec > ; # [doc = "Register `INTEN` writer"]
pub type W = crate :: W < IntenSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntenSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntenSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenSpec ; impl crate :: RegisterSpec for IntenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`inten::R`](R) reader structure"]
impl crate :: Readable for IntenSpec { } # [doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
impl crate :: Writable for IntenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTEN to value 0"]
impl crate :: Resettable for IntenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCLR (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`]
module"]
# [doc (alias = "INTCLR")]
pub type Intclr = crate :: Reg < intclr :: IntclrSpec > ; # [doc = "Interrupt Clear Register"]
pub mod intclr { # [doc = "Register `INTCLR` reader"]
pub type R = crate :: R < IntclrSpec > ; # [doc = "Register `INTCLR` writer"]
pub type W = crate :: W < IntclrSpec > ; # [doc = "Field `PROGRAM_SET_EMPTY` reader - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyR = crate :: BitReader ; # [doc = "Field `PROGRAM_SET_EMPTY` writer - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
pub type ProgramSetEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_DONE_EVENT` reader - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventR = crate :: BitReader ; # [doc = "Field `TR_DONE_EVENT` writer - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
pub type TrDoneEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
pub fn program_set_empty (& self) -> ProgramSetEmptyR { ProgramSetEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
pub fn tr_done_event (& self) -> TrDoneEventR { TrDoneEventR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit"]
# [inline (always)]
# [must_use]
pub fn program_set_empty (& mut self) -> ProgramSetEmptyW < IntclrSpec > { ProgramSetEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit"]
# [inline (always)]
# [must_use]
pub fn tr_done_event (& mut self) -> TrDoneEventW < IntclrSpec > { TrDoneEventW :: new (self , 1) } } # [doc = "Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntclrSpec ; impl crate :: RegisterSpec for IntclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intclr::R`](R) reader structure"]
impl crate :: Readable for IntclrSpec { } # [doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"]
impl crate :: Writable for IntclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCLR to value 0"]
impl crate :: Resettable for IntclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTCMD (rw) register accessor: Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intcmd`]
module"]
# [doc (alias = "INTCMD")]
pub type Intcmd = crate :: Reg < intcmd :: IntcmdSpec > ; # [doc = "Interrupt Command Register"]
pub mod intcmd { # [doc = "Register `INTCMD` reader"]
pub type R = crate :: R < IntcmdSpec > ; # [doc = "Register `INTCMD` writer"]
pub type W = crate :: W < IntcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_INTERRUPT` reader - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptR = crate :: BitReader ; # [doc = "Field `SET_TPTC_INTERRUPT` writer - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_interrupt (& self) -> SetTptcInterruptR { SetTptcInterruptR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < IntcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_interrupt (& mut self) -> SetTptcInterruptW < IntcmdSpec > { SetTptcInterruptW :: new (self , 1) } } # [doc = "Interrupt Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntcmdSpec ; impl crate :: RegisterSpec for IntcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intcmd::R`](R) reader structure"]
impl crate :: Readable for IntcmdSpec { } # [doc = "`write(|w| ..)` method takes [`intcmd::W`](W) writer structure"]
impl crate :: Writable for IntcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTCMD to value 0"]
impl crate :: Resettable for IntcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRSTAT (rw) register accessor: Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errstat`]
module"]
# [doc (alias = "ERRSTAT")]
pub type Errstat = crate :: Reg < errstat :: ErrstatSpec > ; # [doc = "Error Status Register"]
pub mod errstat { # [doc = "Register `ERRSTAT` reader"]
pub type R = crate :: R < ErrstatSpec > ; # [doc = "Register `ERRSTAT` writer"]
pub type W = crate :: W < ErrstatSpec > ; # [doc = "Field `BUS_ERROR_EVENT` reader - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventR = crate :: BitReader ; # [doc = "Field `BUS_ERROR_EVENT` writer - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
pub type BusErrorEventW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR_ERROR` reader - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorR = crate :: BitReader ; # [doc = "Field `TR_ERROR` writer - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
pub type TrErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMR_ADDRESS_ERROR` reader - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorR = crate :: BitReader ; # [doc = "Field `MMR_ADDRESS_ERROR` writer - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
pub type MmrAddressErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
pub fn bus_error_event (& self) -> BusErrorEventR { BusErrorEventR :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
pub fn tr_error (& self) -> TrErrorR { TrErrorR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
pub fn mmr_address_error (& self) -> MmrAddressErrorR { MmrAddressErrorR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register \\[ERRDET\\]."]
# [inline (always)]
# [must_use]
pub fn bus_error_event (& mut self) -> BusErrorEventW < ErrstatSpec > { BusErrorEventW :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
TR Error:#br#TR detected that violates FIFO Mode transfer \\[SAM or DAM is '1'\\]
alignment rules or has ACNT or BCNT == 0. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn tr_error (& mut self) -> TrErrorW < ErrstatSpec > { TrErrorW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. \\[Is only be set for non-emulation accesses\\]. No additional error information is recorded."]
# [inline (always)]
# [must_use]
pub fn mmr_address_error (& mut self) -> MmrAddressErrorW < ErrstatSpec > { MmrAddressErrorW :: new (self , 3) } } # [doc = "Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrstatSpec ; impl crate :: RegisterSpec for ErrstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errstat::R`](R) reader structure"]
impl crate :: Readable for ErrstatSpec { } # [doc = "`write(|w| ..)` method takes [`errstat::W`](W) writer structure"]
impl crate :: Writable for ErrstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRSTAT to value 0"]
impl crate :: Resettable for ErrstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERREN (rw) register accessor: Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erren`]
module"]
# [doc (alias = "ERREN")]
pub type Erren = crate :: Reg < erren :: ErrenSpec > ; # [doc = "Error Enable Register"]
pub mod erren { # [doc = "Register `ERREN` reader"]
pub type R = crate :: R < ErrenSpec > ; # [doc = "Register `ERREN` writer"]
pub type W = crate :: W < ErrenSpec > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` reader - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_2` writer - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` reader - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR_1` writer - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_ENABLE_FOR` reader - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_ENABLE_FOR` writer - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
pub type InterruptEnableForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_2 (& self) -> InterruptEnableFor2R { InterruptEnableFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for_1 (& self) -> InterruptEnableFor1R { InterruptEnableFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
pub fn interrupt_enable_for (& self) -> InterruptEnableForR { InterruptEnableForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_2 (& mut self) -> InterruptEnableFor2W < ErrenSpec > { InterruptEnableFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for_1 (& mut self) -> InterruptEnableFor1W < ErrenSpec > { InterruptEnableFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation."]
# [inline (always)]
# [must_use]
pub fn interrupt_enable_for (& mut self) -> InterruptEnableForW < ErrenSpec > { InterruptEnableForW :: new (self , 3) } } # [doc = "Error Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrenSpec ; impl crate :: RegisterSpec for ErrenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erren::R`](R) reader structure"]
impl crate :: Readable for ErrenSpec { } # [doc = "`write(|w| ..)` method takes [`erren::W`](W) writer structure"]
impl crate :: Writable for ErrenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERREN to value 0"]
impl crate :: Resettable for ErrenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCLR (rw) register accessor: Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errclr`]
module"]
# [doc (alias = "ERRCLR")]
pub type Errclr = crate :: Reg < errclr :: ErrclrSpec > ; # [doc = "Error Clear Register"]
pub mod errclr { # [doc = "Register `ERRCLR` reader"]
pub type R = crate :: R < ErrclrSpec > ; # [doc = "Register `ERRCLR` writer"]
pub type W = crate :: W < ErrclrSpec > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` reader - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_2` writer - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
pub type InterruptClearFor2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` reader - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1R = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR_1` writer - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
pub type InterruptClearFor1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INTERRUPT_CLEAR_FOR` reader - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForR = crate :: BitReader ; # [doc = "Field `INTERRUPT_CLEAR_FOR` writer - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
pub type InterruptClearForW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_2 (& self) -> InterruptClearFor2R { InterruptClearFor2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for_1 (& self) -> InterruptClearFor1R { InterruptClearFor1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
pub fn interrupt_clear_for (& self) -> InterruptClearForR { InterruptClearForR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_2 (& mut self) -> InterruptClearFor2W < ErrclrSpec > { InterruptClearFor2W :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for_1 (& mut self) -> InterruptClearFor1W < ErrclrSpec > { InterruptClearFor1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register."]
# [inline (always)]
# [must_use]
pub fn interrupt_clear_for (& mut self) -> InterruptClearForW < ErrclrSpec > { InterruptClearForW :: new (self , 3) } } # [doc = "Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrclrSpec ; impl crate :: RegisterSpec for ErrclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errclr::R`](R) reader structure"]
impl crate :: Readable for ErrclrSpec { } # [doc = "`write(|w| ..)` method takes [`errclr::W`](W) writer structure"]
impl crate :: Writable for ErrclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCLR to value 0"]
impl crate :: Resettable for ErrclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRDET (rw) register accessor: Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errdet`]
module"]
# [doc (alias = "ERRDET")]
pub type Errdet = crate :: Reg < errdet :: ErrdetSpec > ; # [doc = "Error Details Register"]
pub mod errdet { # [doc = "Register `ERRDET` reader"]
pub type R = crate :: R < ErrdetSpec > ; # [doc = "Register `ERRDET` writer"]
pub type W = crate :: W < ErrdetSpec > ; # [doc = "Field `TRANSACTION_STATUS` reader - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusR = crate :: FieldReader ; # [doc = "Field `TRANSACTION_STATUS` writer - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
pub type TransactionStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` reader - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCINTEN` writer - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` reader - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenR = crate :: BitReader ; # [doc = "Field `CONTAINS_THE_OPT_TCCHEN` writer - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
pub type ContainsTheOptTcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
pub fn transaction_status (& self) -> TransactionStatusR { TransactionStatusR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcinten (& self) -> ContainsTheOptTcintenR { ContainsTheOptTcintenR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
pub fn contains_the_opt_tcchen (& self) -> ContainsTheOptTcchenR { ContainsTheOptTcchenR :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec."]
# [inline (always)]
# [must_use]
pub fn transaction_status (& mut self) -> TransactionStatusW < ErrdetSpec > { TransactionStatusW :: new (self , 0) } # [doc = "Bits 8:13 - 13:8\\]
Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < ErrdetSpec > { TransferCompleteCodeW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcinten (& mut self) -> ContainsTheOptTcintenW < ErrdetSpec > { ContainsTheOptTcintenW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error."]
# [inline (always)]
# [must_use]
pub fn contains_the_opt_tcchen (& mut self) -> ContainsTheOptTcchenW < ErrdetSpec > { ContainsTheOptTcchenW :: new (self , 17) } } # [doc = "Error Details Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errdet::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errdet::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrdetSpec ; impl crate :: RegisterSpec for ErrdetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errdet::R`](R) reader structure"]
impl crate :: Readable for ErrdetSpec { } # [doc = "`write(|w| ..)` method takes [`errdet::W`](W) writer structure"]
impl crate :: Writable for ErrdetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRDET to value 0"]
impl crate :: Resettable for ErrdetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERRCMD (rw) register accessor: Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errcmd`]
module"]
# [doc (alias = "ERRCMD")]
pub type Errcmd = crate :: Reg < errcmd :: ErrcmdSpec > ; # [doc = "Error Command Register"]
pub mod errcmd { # [doc = "Register `ERRCMD` reader"]
pub type R = crate :: R < ErrcmdSpec > ; # [doc = "Register `ERRCMD` writer"]
pub type W = crate :: W < ErrcmdSpec > ; # [doc = "Field `EVALUATE_STATE_OF` reader - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfR = crate :: BitReader ; # [doc = "Field `EVALUATE_STATE_OF` writer - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
pub type EvaluateStateOfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_TPTC_ERROR` reader - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorR = crate :: BitReader ; # [doc = "Field `SET_TPTC_ERROR` writer - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
pub type SetTptcErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn evaluate_state_of (& self) -> EvaluateStateOfR { EvaluateStateOfR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
pub fn set_tptc_error (& self) -> SetTptcErrorR { SetTptcErrorR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn evaluate_state_of (& mut self) -> EvaluateStateOfW < ErrcmdSpec > { EvaluateStateOfW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn set_tptc_error (& mut self) -> SetTptcErrorW < ErrcmdSpec > { SetTptcErrorW :: new (self , 1) } } # [doc = "Error Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`errcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrcmdSpec ; impl crate :: RegisterSpec for ErrcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`errcmd::R`](R) reader structure"]
impl crate :: Readable for ErrcmdSpec { } # [doc = "`write(|w| ..)` method takes [`errcmd::W`](W) writer structure"]
impl crate :: Writable for ErrcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERRCMD to value 0"]
impl crate :: Resettable for ErrcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RDRATE (rw) register accessor: Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdrate`]
module"]
# [doc (alias = "RDRATE")]
pub type Rdrate = crate :: Reg < rdrate :: RdrateSpec > ; # [doc = "Read Rate Register"]
pub mod rdrate { # [doc = "Register `RDRATE` reader"]
pub type R = crate :: R < RdrateSpec > ; # [doc = "Register `RDRATE` writer"]
pub type W = crate :: W < RdrateSpec > ; # [doc = "Field `READ_RATE_CONTROL` reader - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlR = crate :: FieldReader ; # [doc = "Field `READ_RATE_CONTROL` writer - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
pub type ReadRateControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
pub fn read_rate_control (& self) -> ReadRateControlR { ReadRateControlR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC."]
# [inline (always)]
# [must_use]
pub fn read_rate_control (& mut self) -> ReadRateControlW < RdrateSpec > { ReadRateControlW :: new (self , 0) } } # [doc = "Read Rate Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rdrate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdrate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrateSpec ; impl crate :: RegisterSpec for RdrateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rdrate::R`](R) reader structure"]
impl crate :: Readable for RdrateSpec { } # [doc = "`write(|w| ..)` method takes [`rdrate::W`](W) writer structure"]
impl crate :: Writable for RdrateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RDRATE to value 0"]
impl crate :: Resettable for RdrateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "POPT (rw) register accessor: Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@popt`]
module"]
# [doc (alias = "POPT")]
pub type Popt = crate :: Reg < popt :: PoptSpec > ; # [doc = "Prog Set Options"]
pub mod popt { # [doc = "Register `POPT` reader"]
pub type R = crate :: R < PoptSpec > ; # [doc = "Register `POPT` writer"]
pub type W = crate :: W < PoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < PoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < PoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < PoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < PoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < PoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < PoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < PoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < PoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Prog Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`popt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`popt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PoptSpec ; impl crate :: RegisterSpec for PoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`popt::R`](R) reader structure"]
impl crate :: Readable for PoptSpec { } # [doc = "`write(|w| ..)` method takes [`popt::W`](W) writer structure"]
impl crate :: Writable for PoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets POPT to value 0"]
impl crate :: Resettable for PoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSRC (rw) register accessor: Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psrc`]
module"]
# [doc (alias = "PSRC")]
pub type Psrc = crate :: Reg < psrc :: PsrcSpec > ; # [doc = "Prog Set Src Address"]
pub mod psrc { # [doc = "Register `PSRC` reader"]
pub type R = crate :: R < PsrcSpec > ; # [doc = "Register `PSRC` writer"]
pub type W = crate :: W < PsrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR` reader - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR` writer - 31:0\\]
Source address for Program Register Set"]
pub type SourceAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
pub fn source_address_for (& self) -> SourceAddressForR { SourceAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for (& mut self) -> SourceAddressForW < PsrcSpec > { SourceAddressForW :: new (self , 0) } } # [doc = "Prog Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`psrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsrcSpec ; impl crate :: RegisterSpec for PsrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`psrc::R`](R) reader structure"]
impl crate :: Readable for PsrcSpec { } # [doc = "`write(|w| ..)` method takes [`psrc::W`](W) writer structure"]
impl crate :: Writable for PsrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSRC to value 0"]
impl crate :: Resettable for PsrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCNT (rw) register accessor: Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcnt`]
module"]
# [doc (alias = "PCNT")]
pub type Pcnt = crate :: Reg < pcnt :: PcntSpec > ; # [doc = "Prog Set Count"]
pub mod pcnt { # [doc = "Register `PCNT` reader"]
pub type R = crate :: R < PcntSpec > ; # [doc = "Register `PCNT` writer"]
pub type W = crate :: W < PcntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` reader - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT__NUMBER` writer - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
pub type BdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
pub fn bdimension_count__number (& self) -> BdimensionCount_NumberR { BdimensionCount_NumberR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < PcntSpec > { AdimensionCount_NumberW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."]
# [inline (always)]
# [must_use]
pub fn bdimension_count__number (& mut self) -> BdimensionCount_NumberW < PcntSpec > { BdimensionCount_NumberW :: new (self , 16) } } # [doc = "Prog Set Count\n\nYou can [`read`](crate::Reg::read) this register and get [`pcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcntSpec ; impl crate :: RegisterSpec for PcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcnt::R`](R) reader structure"]
impl crate :: Readable for PcntSpec { } # [doc = "`write(|w| ..)` method takes [`pcnt::W`](W) writer structure"]
impl crate :: Writable for PcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCNT to value 0"]
impl crate :: Resettable for PcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PDST (rw) register accessor: Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdst`]
module"]
# [doc (alias = "PDST")]
pub type Pdst = crate :: Reg < pdst :: PdstSpec > ; # [doc = "Prog Set Dst Address"]
pub mod pdst { # [doc = "Register `PDST` reader"]
pub type R = crate :: R < PdstSpec > ; # [doc = "Register `PDST` writer"]
pub type W = crate :: W < PdstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` reader - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForR = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR` writer - 31:0\\]
Destination address for Program Register Set"]
pub type DestinationAddressForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
pub fn destination_address_for (& self) -> DestinationAddressForR { DestinationAddressForR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Program Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for (& mut self) -> DestinationAddressForW < PdstSpec > { DestinationAddressForW :: new (self , 0) } } # [doc = "Prog Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`pdst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PdstSpec ; impl crate :: RegisterSpec for PdstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pdst::R`](R) reader structure"]
impl crate :: Readable for PdstSpec { } # [doc = "`write(|w| ..)` method takes [`pdst::W`](W) writer structure"]
impl crate :: Writable for PdstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PDST to value 0"]
impl crate :: Resettable for PdstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIDX (rw) register accessor: Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbidx`]
module"]
# [doc (alias = "PBIDX")]
pub type Pbidx = crate :: Reg < pbidx :: PbidxSpec > ; # [doc = "Prog Set B-Dim Idx"]
pub mod pbidx { # [doc = "Register `PBIDX` reader"]
pub type R = crate :: R < PbidxSpec > ; # [doc = "Register `PBIDX` writer"]
pub type W = crate :: W < PbidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < PbidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < PbidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Prog Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`pbidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbidxSpec ; impl crate :: RegisterSpec for PbidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbidx::R`](R) reader structure"]
impl crate :: Readable for PbidxSpec { } # [doc = "`write(|w| ..)` method takes [`pbidx::W`](W) writer structure"]
impl crate :: Writable for PbidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIDX to value 0"]
impl crate :: Resettable for PbidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PMPPRXY (rw) register accessor: Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmpprxy`]
module"]
# [doc (alias = "PMPPRXY")]
pub type Pmpprxy = crate :: Reg < pmpprxy :: PmpprxySpec > ; # [doc = "Prog Set Mem Protect Proxy"]
pub mod pmpprxy { # [doc = "Register `PMPPRXY` reader"]
pub type R = crate :: R < PmpprxySpec > ; # [doc = "Register `PMPPRXY` writer"]
pub type W = crate :: W < PmpprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < PmpprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < PmpprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < PmpprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Prog Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`pmpprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmpprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmpprxySpec ; impl crate :: RegisterSpec for PmpprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pmpprxy::R`](R) reader structure"]
impl crate :: Readable for PmpprxySpec { } # [doc = "`write(|w| ..)` method takes [`pmpprxy::W`](W) writer structure"]
impl crate :: Writable for PmpprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PMPPRXY to value 0"]
impl crate :: Resettable for PmpprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAOPT (rw) register accessor: Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@saopt`]
module"]
# [doc (alias = "SAOPT")]
pub type Saopt = crate :: Reg < saopt :: SaoptSpec > ; # [doc = "Src Actv Set Options"]
pub mod saopt { # [doc = "Register `SAOPT` reader"]
pub type R = crate :: R < SaoptSpec > ; # [doc = "Register `SAOPT` writer"]
pub type W = crate :: W < SaoptSpec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < SaoptSpec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < SaoptSpec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < SaoptSpec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < SaoptSpec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < SaoptSpec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < SaoptSpec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < SaoptSpec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < SaoptSpec > { DebugIdW :: new (self , 28) } } # [doc = "Src Actv Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`saopt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saopt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SaoptSpec ; impl crate :: RegisterSpec for SaoptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`saopt::R`](R) reader structure"]
impl crate :: Readable for SaoptSpec { } # [doc = "`write(|w| ..)` method takes [`saopt::W`](W) writer structure"]
impl crate :: Writable for SaoptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAOPT to value 0"]
impl crate :: Resettable for SaoptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRC (rw) register accessor: Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrc`]
module"]
# [doc (alias = "SASRC")]
pub type Sasrc = crate :: Reg < sasrc :: SasrcSpec > ; # [doc = "Src Actv Set Src Address"]
pub mod sasrc { # [doc = "Register `SASRC` reader"]
pub type R = crate :: R < SasrcSpec > ; # [doc = "Register `SASRC` writer"]
pub type W = crate :: W < SasrcSpec > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` reader - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_FOR_1` writer - 31:0\\]
Source address for Source Active Register Set"]
pub type SourceAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
pub fn source_address_for_1 (& self) -> SourceAddressFor1R { SourceAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn source_address_for_1 (& mut self) -> SourceAddressFor1W < SasrcSpec > { SourceAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcSpec ; impl crate :: RegisterSpec for SasrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrc::R`](R) reader structure"]
impl crate :: Readable for SasrcSpec { } # [doc = "`write(|w| ..)` method takes [`sasrc::W`](W) writer structure"]
impl crate :: Writable for SasrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRC to value 0"]
impl crate :: Resettable for SasrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNT (rw) register accessor: Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacnt`]
module"]
# [doc (alias = "SACNT")]
pub type Sacnt = crate :: Reg < sacnt :: SacntSpec > ; # [doc = "Src Actv Set A-Count"]
pub mod sacnt { # [doc = "Register `SACNT` reader"]
pub type R = crate :: R < SacntSpec > ; # [doc = "Register `SACNT` writer"]
pub type W = crate :: W < SacntSpec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberR = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
pub type AdimensionCount_NumberW < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
pub fn adimension_count__number (& self) -> AdimensionCount_NumberR { AdimensionCount_NumberR :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred in first dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number (& mut self) -> AdimensionCount_NumberW < SacntSpec > { AdimensionCount_NumberW :: new (self , 0) } } # [doc = "Src Actv Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sacnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntSpec ; impl crate :: RegisterSpec for SacntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacnt::R`](R) reader structure"]
impl crate :: Readable for SacntSpec { } # [doc = "`write(|w| ..)` method takes [`sacnt::W`](W) writer structure"]
impl crate :: Writable for SacntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNT to value 0"]
impl crate :: Resettable for SacntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADST (rw) register accessor: Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadst`]
module"]
# [doc (alias = "SADST")]
pub type Sadst = crate :: Reg < sadst :: SadstSpec > ; # [doc = "Src Actv Set Dst Address"]
pub mod sadst { # [doc = "Register `SADST` reader"]
pub type R = crate :: R < SadstSpec > ; # [doc = "Register `SADST` writer"]
pub type W = crate :: W < SadstSpec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` reader - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_1` writer - 31:0\\]
Destination address for Source Active Register Set"]
pub type DestinationAddressFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
pub fn destination_address_for_1 (& self) -> DestinationAddressFor1R { DestinationAddressFor1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Source Active Register Set"]
# [inline (always)]
# [must_use]
pub fn destination_address_for_1 (& mut self) -> DestinationAddressFor1W < SadstSpec > { DestinationAddressFor1W :: new (self , 0) } } # [doc = "Src Actv Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sadst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstSpec ; impl crate :: RegisterSpec for SadstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadst::R`](R) reader structure"]
impl crate :: Readable for SadstSpec { } # [doc = "`write(|w| ..)` method takes [`sadst::W`](W) writer structure"]
impl crate :: Writable for SadstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADST to value 0"]
impl crate :: Resettable for SadstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABIDX (rw) register accessor: Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabidx`]
module"]
# [doc (alias = "SABIDX")]
pub type Sabidx = crate :: Reg < sabidx :: SabidxSpec > ; # [doc = "Src Actv Set B-Dim Idx"]
pub mod sabidx { # [doc = "Register `SABIDX` reader"]
pub type R = crate :: R < SabidxSpec > ; # [doc = "Register `SABIDX` writer"]
pub type W = crate :: W < SabidxSpec > ; # [doc = "Field `SOURCE_BIDX_FOR` reader - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SOURCE_BIDX_FOR` writer - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SourceBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn source_bidx_for (& self) -> SourceBidxForR { SourceBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn source_bidx_for (& mut self) -> SourceBidxForW < SabidxSpec > { SourceBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < SabidxSpec > { DestBidxForW :: new (self , 16) } } # [doc = "Src Actv Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`sabidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabidxSpec ; impl crate :: RegisterSpec for SabidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabidx::R`](R) reader structure"]
impl crate :: Readable for SabidxSpec { } # [doc = "`write(|w| ..)` method takes [`sabidx::W`](W) writer structure"]
impl crate :: Writable for SabidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABIDX to value 0"]
impl crate :: Resettable for SabidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAMPPRXY (rw) register accessor: Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sampprxy`]
module"]
# [doc (alias = "SAMPPRXY")]
pub type Sampprxy = crate :: Reg < sampprxy :: SampprxySpec > ; # [doc = "Src Actv Set Mem Protect Proxy"]
pub mod sampprxy { # [doc = "Register `SAMPPRXY` reader"]
pub type R = crate :: R < SampprxySpec > ; # [doc = "Register `SAMPPRXY` writer"]
pub type W = crate :: W < SampprxySpec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < SampprxySpec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < SampprxySpec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < SampprxySpec > { SecureLevelW :: new (self , 9) } } # [doc = "Src Actv Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`sampprxy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sampprxy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SampprxySpec ; impl crate :: RegisterSpec for SampprxySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sampprxy::R`](R) reader structure"]
impl crate :: Readable for SampprxySpec { } # [doc = "`write(|w| ..)` method takes [`sampprxy::W`](W) writer structure"]
impl crate :: Writable for SampprxySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAMPPRXY to value 0"]
impl crate :: Resettable for SampprxySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SACNTRLD (rw) register accessor: Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sacntrld`]
module"]
# [doc (alias = "SACNTRLD")]
pub type Sacntrld = crate :: Reg < sacntrld :: SacntrldSpec > ; # [doc = "Src Actv Set Cnt Reload"]
pub mod sacntrld { # [doc = "Register `SACNTRLD` reader"]
pub type R = crate :: R < SacntrldSpec > ; # [doc = "Register `SACNTRLD` writer"]
pub type W = crate :: W < SacntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE` reader - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueR = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE` writer - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value (& self) -> AcntReloadValueR { AcntReloadValueR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value (& mut self) -> AcntReloadValueW < SacntrldSpec > { AcntReloadValueW :: new (self , 0) } } # [doc = "Src Actv Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`sacntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sacntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SacntrldSpec ; impl crate :: RegisterSpec for SacntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sacntrld::R`](R) reader structure"]
impl crate :: Readable for SacntrldSpec { } # [doc = "`write(|w| ..)` method takes [`sacntrld::W`](W) writer structure"]
impl crate :: Writable for SacntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SACNTRLD to value 0"]
impl crate :: Resettable for SacntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SASRCBREF (rw) register accessor: Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasrcbref`]
module"]
# [doc (alias = "SASRCBREF")]
pub type Sasrcbref = crate :: Reg < sasrcbref :: SasrcbrefSpec > ; # [doc = "Src Actv Set Src Addr B-Reference"]
pub mod sasrcbref { # [doc = "Register `SASRCBREF` reader"]
pub type R = crate :: R < SasrcbrefSpec > ; # [doc = "Register `SASRCBREF` writer"]
pub type W = crate :: W < SasrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` reader - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE` writer - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference (& self) -> SourceAddressReferenceR { SourceAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference (& mut self) -> SourceAddressReferenceW < SasrcbrefSpec > { SourceAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sasrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sasrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SasrcbrefSpec ; impl crate :: RegisterSpec for SasrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sasrcbref::R`](R) reader structure"]
impl crate :: Readable for SasrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sasrcbref::W`](W) writer structure"]
impl crate :: Writable for SasrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SASRCBREF to value 0"]
impl crate :: Resettable for SasrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SADSTBREF (rw) register accessor: Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sadstbref`]
module"]
# [doc (alias = "SADSTBREF")]
pub type Sadstbref = crate :: Reg < sadstbref :: SadstbrefSpec > ; # [doc = "Src Actv Set Dst Addr B-Reference"]
pub mod sadstbref { # [doc = "Register `SADSTBREF` reader"]
pub type R = crate :: R < SadstbrefSpec > ; # [doc = "Register `SADSTBREF` writer"]
pub type W = crate :: W < SadstbrefSpec > ; # [doc = "Field `DST_ADDRESS_REFERENCE` reader - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceR = crate :: FieldReader < u32 > ; # [doc = "Field `DST_ADDRESS_REFERENCE` writer - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
pub type DstAddressReferenceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
pub fn dst_address_reference (& self) -> DstAddressReferenceR { DstAddressReferenceR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn dst_address_reference (& mut self) -> DstAddressReferenceW < SadstbrefSpec > { DstAddressReferenceW :: new (self , 0) } } # [doc = "Src Actv Set Dst Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`sadstbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sadstbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SadstbrefSpec ; impl crate :: RegisterSpec for SadstbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sadstbref::R`](R) reader structure"]
impl crate :: Readable for SadstbrefSpec { } # [doc = "`write(|w| ..)` method takes [`sadstbref::W`](W) writer structure"]
impl crate :: Writable for SadstbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SADSTBREF to value 0"]
impl crate :: Resettable for SadstbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SABCNT (rw) register accessor: Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sabcnt`]
module"]
# [doc (alias = "SABCNT")]
pub type Sabcnt = crate :: Reg < sabcnt :: SabcntSpec > ; # [doc = "Src Actv Set B-Count"]
pub mod sabcnt { # [doc = "Register `SABCNT` reader"]
pub type R = crate :: R < SabcntSpec > ; # [doc = "Register `SABCNT` writer"]
pub type W = crate :: W < SabcntSpec > ; # [doc = "Field `BDIMENSION_COUNT` reader - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountR = crate :: FieldReader < u16 > ; # [doc = "Field `BDIMENSION_COUNT` writer - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
pub type BdimensionCountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bdimension_count (& self) -> BdimensionCountR { BdimensionCountR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bdimension_count (& mut self) -> BdimensionCountW < SabcntSpec > { BdimensionCountW :: new (self , 0) } } # [doc = "Src Actv Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`sabcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sabcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SabcntSpec ; impl crate :: RegisterSpec for SabcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sabcnt::R`](R) reader structure"]
impl crate :: Readable for SabcntSpec { } # [doc = "`write(|w| ..)` method takes [`sabcnt::W`](W) writer structure"]
impl crate :: Writable for SabcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SABCNT to value 0"]
impl crate :: Resettable for SabcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFCNTRLD (rw) register accessor: Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfcntrld`]
module"]
# [doc (alias = "DFCNTRLD")]
pub type Dfcntrld = crate :: Reg < dfcntrld :: DfcntrldSpec > ; # [doc = "Dst FIFO Set Cnt Reload"]
pub mod dfcntrld { # [doc = "Register `DFCNTRLD` reader"]
pub type R = crate :: R < DfcntrldSpec > ; # [doc = "Register `DFCNTRLD` writer"]
pub type W = crate :: W < DfcntrldSpec > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` reader - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1R = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT_RELOAD_VALUE_1` writer - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
pub type AcntReloadValue1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
pub fn acnt_reload_value_1 (& self) -> AcntReloadValue1R { AcntReloadValue1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced \\[i.e. ACNT decrements to 0\\]. by the Src offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT bytes\\]"]
# [inline (always)]
# [must_use]
pub fn acnt_reload_value_1 (& mut self) -> AcntReloadValue1W < DfcntrldSpec > { AcntReloadValue1W :: new (self , 0) } } # [doc = "Dst FIFO Set Cnt Reload\n\nYou can [`read`](crate::Reg::read) this register and get [`dfcntrld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfcntrld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfcntrldSpec ; impl crate :: RegisterSpec for DfcntrldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfcntrld::R`](R) reader structure"]
impl crate :: Readable for DfcntrldSpec { } # [doc = "`write(|w| ..)` method takes [`dfcntrld::W`](W) writer structure"]
impl crate :: Writable for DfcntrldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFCNTRLD to value 0"]
impl crate :: Resettable for DfcntrldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRCBREF (rw) register accessor: Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrcbref`]
module"]
# [doc (alias = "DFSRCBREF")]
pub type Dfsrcbref = crate :: Reg < dfsrcbref :: DfsrcbrefSpec > ; # [doc = "Dst FIFO Set Src Addr B-Reference"]
pub mod dfsrcbref { # [doc = "Register `DFSRCBREF` reader"]
pub type R = crate :: R < DfsrcbrefSpec > ; # [doc = "Register `DFSRCBREF` writer"]
pub type W = crate :: W < DfsrcbrefSpec > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` reader - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_REFERENCE_1` writer - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
pub type SourceAddressReference1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
pub fn source_address_reference_1 (& self) -> SourceAddressReference1R { SourceAddressReference1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."]
# [inline (always)]
# [must_use]
pub fn source_address_reference_1 (& mut self) -> SourceAddressReference1W < DfsrcbrefSpec > { SourceAddressReference1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Addr B-Reference\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrcbref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrcbref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DfsrcbrefSpec ; impl crate :: RegisterSpec for DfsrcbrefSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrcbref::R`](R) reader structure"]
impl crate :: Readable for DfsrcbrefSpec { } # [doc = "`write(|w| ..)` method takes [`dfsrcbref::W`](W) writer structure"]
impl crate :: Writable for DfsrcbrefSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRCBREF to value 0"]
impl crate :: Resettable for DfsrcbrefSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT0 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt0`]
module"]
# [doc (alias = "DFOPT0")]
pub type Dfopt0 = crate :: Reg < dfopt0 :: Dfopt0Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt0 { # [doc = "Register `DFOPT0` reader"]
pub type R = crate :: R < Dfopt0Spec > ; # [doc = "Register `DFOPT0` writer"]
pub type W = crate :: W < Dfopt0Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt0Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt0Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt0Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt0Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt0Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt0Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt0Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt0Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt0Spec ; impl crate :: RegisterSpec for Dfopt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt0::R`](R) reader structure"]
impl crate :: Readable for Dfopt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt0::W`](W) writer structure"]
impl crate :: Writable for Dfopt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT0 to value 0"]
impl crate :: Resettable for Dfopt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC0 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc0`]
module"]
# [doc (alias = "DFSRC0")]
pub type Dfsrc0 = crate :: Reg < dfsrc0 :: Dfsrc0Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc0 { # [doc = "Register `DFSRC0` reader"]
pub type R = crate :: R < Dfsrc0Spec > ; # [doc = "Register `DFSRC0` writer"]
pub type W = crate :: W < Dfsrc0Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsR = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is (& self) -> SourceAddressIsR { SourceAddressIsR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is (& mut self) -> SourceAddressIsW < Dfsrc0Spec > { SourceAddressIsW :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc0Spec ; impl crate :: RegisterSpec for Dfsrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc0::R`](R) reader structure"]
impl crate :: Readable for Dfsrc0Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc0::W`](W) writer structure"]
impl crate :: Writable for Dfsrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC0 to value 0"]
impl crate :: Resettable for Dfsrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT0 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt0`]
module"]
# [doc (alias = "DFACNT0")]
pub type Dfacnt0 = crate :: Reg < dfacnt0 :: Dfacnt0Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt0 { # [doc = "Register `DFACNT0` reader"]
pub type R = crate :: R < Dfacnt0Spec > ; # [doc = "Register `DFACNT0` writer"]
pub type W = crate :: W < Dfacnt0Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_1` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_1 (& self) -> AdimensionCount_Number1R { AdimensionCount_Number1R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_1 (& mut self) -> AdimensionCount_Number1W < Dfacnt0Spec > { AdimensionCount_Number1W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt0Spec ; impl crate :: RegisterSpec for Dfacnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt0::R`](R) reader structure"]
impl crate :: Readable for Dfacnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt0::W`](W) writer structure"]
impl crate :: Writable for Dfacnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT0 to value 0"]
impl crate :: Resettable for Dfacnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST0 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst0`]
module"]
# [doc (alias = "DFDST0")]
pub type Dfdst0 = crate :: Reg < dfdst0 :: Dfdst0Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst0 { # [doc = "Register `DFDST0` reader"]
pub type R = crate :: R < Dfdst0Spec > ; # [doc = "Register `DFDST0` writer"]
pub type W = crate :: W < Dfdst0Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_2` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_2 (& self) -> DestinationAddressFor2R { DestinationAddressFor2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_2 (& mut self) -> DestinationAddressFor2W < Dfdst0Spec > { DestinationAddressFor2W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst0Spec ; impl crate :: RegisterSpec for Dfdst0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst0::R`](R) reader structure"]
impl crate :: Readable for Dfdst0Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst0::W`](W) writer structure"]
impl crate :: Writable for Dfdst0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST0 to value 0"]
impl crate :: Resettable for Dfdst0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX0 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx0`]
module"]
# [doc (alias = "DFBIDX0")]
pub type Dfbidx0 = crate :: Reg < dfbidx0 :: Dfbidx0Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx0 { # [doc = "Register `DFBIDX0` reader"]
pub type R = crate :: R < Dfbidx0Spec > ; # [doc = "Register `DFBIDX0` writer"]
pub type W = crate :: W < Dfbidx0Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx0Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx0Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx0Spec ; impl crate :: RegisterSpec for Dfbidx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx0::R`](R) reader structure"]
impl crate :: Readable for Dfbidx0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx0::W`](W) writer structure"]
impl crate :: Writable for Dfbidx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX0 to value 0"]
impl crate :: Resettable for Dfbidx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY0 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy0`]
module"]
# [doc (alias = "DFMPPRXY0")]
pub type Dfmpprxy0 = crate :: Reg < dfmpprxy0 :: Dfmpprxy0Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy0 { # [doc = "Register `DFMPPRXY0` reader"]
pub type R = crate :: R < Dfmpprxy0Spec > ; # [doc = "Register `DFMPPRXY0` writer"]
pub type W = crate :: W < Dfmpprxy0Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy0Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy0Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy0Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy0Spec ; impl crate :: RegisterSpec for Dfmpprxy0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy0::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy0Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy0::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY0 to value 0"]
impl crate :: Resettable for Dfmpprxy0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT0 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt0`]
module"]
# [doc (alias = "DFBCNT0")]
pub type Dfbcnt0 = crate :: Reg < dfbcnt0 :: Dfbcnt0Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt0 { # [doc = "Register `DFBCNT0` reader"]
pub type R = crate :: R < Dfbcnt0Spec > ; # [doc = "Register `DFBCNT0` writer"]
pub type W = crate :: W < Dfbcnt0Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForR = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for (& self) -> BcountRemainingForR { BcountRemainingForR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for (& mut self) -> BcountRemainingForW < Dfbcnt0Spec > { BcountRemainingForW :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt0Spec ; impl crate :: RegisterSpec for Dfbcnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt0::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt0::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT0 to value 0"]
impl crate :: Resettable for Dfbcnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFOPT1 (rw) register accessor: Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfopt1`]
module"]
# [doc (alias = "DFOPT1")]
pub type Dfopt1 = crate :: Reg < dfopt1 :: Dfopt1Spec > ; # [doc = "Dst FIFO Set Options"]
pub mod dfopt1 { # [doc = "Register `DFOPT1` reader"]
pub type R = crate :: R < Dfopt1Spec > ; # [doc = "Register `DFOPT1` writer"]
pub type W = crate :: W < Dfopt1Spec > ; # [doc = "Field `SOURCE_ADDRESS_MODE` reader - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeR = crate :: BitReader ; # [doc = "Field `SOURCE_ADDRESS_MODE` writer - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SourceAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DESTINATION_ADDRESS_MODE` reader - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeR = crate :: BitReader ; # [doc = "Field `DESTINATION_ADDRESS_MODE` writer - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DestinationAddressModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_PRIORITY` reader - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityR = crate :: FieldReader ; # [doc = "Field `TRANSFER_PRIORITY` writer - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
pub type TransferPriorityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FIFO_WIDTH_CONTROL` reader - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlR = crate :: FieldReader ; # [doc = "Field `FIFO_WIDTH_CONTROL` writer - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
pub type FifoWidthControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TRANSFER_COMPLETE_CODE` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeR = crate :: FieldReader ; # [doc = "Field `TRANSFER_COMPLETE_CODE` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
pub type TransferCompleteCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` reader - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_INTERRUPT` writer - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
pub type TransferCompleteInterruptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` reader - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingR = crate :: BitReader ; # [doc = "Field `TRANSFER_COMPLETE_CHAINING` writer - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
pub type TransferCompleteChainingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEBUG_ID` reader - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdR = crate :: FieldReader ; # [doc = "Field `DEBUG_ID` writer - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
pub type DebugIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn source_address_mode (& self) -> SourceAddressModeR { SourceAddressModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn destination_address_mode (& self) -> DestinationAddressModeR { DestinationAddressModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
pub fn transfer_priority (& self) -> TransferPriorityR { TransferPriorityR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
pub fn fifo_width_control (& self) -> FifoWidthControlR { FifoWidthControlR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
pub fn transfer_complete_code (& self) -> TransferCompleteCodeR { TransferCompleteCodeR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
pub fn transfer_complete_interrupt (& self) -> TransferCompleteInterruptR { TransferCompleteInterruptR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn transfer_complete_chaining (& self) -> TransferCompleteChainingR { TransferCompleteChainingR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
pub fn debug_id (& self) -> DebugIdR { DebugIdR :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn source_address_mode (& mut self) -> SourceAddressModeW < Dfopt1Spec > { SourceAddressModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn destination_address_mode (& mut self) -> DestinationAddressModeW < Dfopt1Spec > { DestinationAddressModeW :: new (self , 1) } # [doc = "Bits 4:6 - 6:4\\]
Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority"]
# [inline (always)]
# [must_use]
pub fn transfer_priority (& mut self) -> TransferPriorityW < Dfopt1Spec > { TransferPriorityW :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width control: Applies if either SAM or DAM is set to FIFO mode."]
# [inline (always)]
# [must_use]
pub fn fifo_width_control (& mut self) -> FifoWidthControlW < Dfopt1Spec > { FifoWidthControlW :: new (self , 8) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_code (& mut self) -> TransferCompleteCodeW < Dfopt1Spec > { TransferCompleteCodeW :: new (self , 12) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_interrupt (& mut self) -> TransferCompleteInterruptW < Dfopt1Spec > { TransferCompleteInterruptW :: new (self , 20) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn transfer_complete_chaining (& mut self) -> TransferCompleteChainingW < Dfopt1Spec > { TransferCompleteChainingW :: new (self , 22) } # [doc = "Bits 28:29 - 29:28\\]
Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature."]
# [inline (always)]
# [must_use]
pub fn debug_id (& mut self) -> DebugIdW < Dfopt1Spec > { DebugIdW :: new (self , 28) } } # [doc = "Dst FIFO Set Options\n\nYou can [`read`](crate::Reg::read) this register and get [`dfopt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfopt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfopt1Spec ; impl crate :: RegisterSpec for Dfopt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfopt1::R`](R) reader structure"]
impl crate :: Readable for Dfopt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfopt1::W`](W) writer structure"]
impl crate :: Writable for Dfopt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFOPT1 to value 0"]
impl crate :: Resettable for Dfopt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFSRC1 (rw) register accessor: Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsrc1`]
module"]
# [doc (alias = "DFSRC1")]
pub type Dfsrc1 = crate :: Reg < dfsrc1 :: Dfsrc1Spec > ; # [doc = "Dst FIFO Set Src Address"]
pub mod dfsrc1 { # [doc = "Register `DFSRC1` reader"]
pub type R = crate :: R < Dfsrc1Spec > ; # [doc = "Register `DFSRC1` writer"]
pub type W = crate :: W < Dfsrc1Spec > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` reader - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1R = crate :: FieldReader < u32 > ; # [doc = "Field `SOURCE_ADDRESS_IS_1` writer - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
pub type SourceAddressIs1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
pub fn source_address_is_1 (& self) -> SourceAddressIs1R { SourceAddressIs1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."]
# [inline (always)]
# [must_use]
pub fn source_address_is_1 (& mut self) -> SourceAddressIs1W < Dfsrc1Spec > { SourceAddressIs1W :: new (self , 0) } } # [doc = "Dst FIFO Set Src Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfsrc1Spec ; impl crate :: RegisterSpec for Dfsrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfsrc1::R`](R) reader structure"]
impl crate :: Readable for Dfsrc1Spec { } # [doc = "`write(|w| ..)` method takes [`dfsrc1::W`](W) writer structure"]
impl crate :: Writable for Dfsrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFSRC1 to value 0"]
impl crate :: Resettable for Dfsrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFACNT1 (rw) register accessor: Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfacnt1`]
module"]
# [doc (alias = "DFACNT1")]
pub type Dfacnt1 = crate :: Reg < dfacnt1 :: Dfacnt1Spec > ; # [doc = "Dst FIFO Set A-Count"]
pub mod dfacnt1 { # [doc = "Register `DFACNT1` reader"]
pub type R = crate :: R < Dfacnt1Spec > ; # [doc = "Register `DFACNT1` writer"]
pub type W = crate :: W < Dfacnt1Spec > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` reader - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2R = crate :: FieldReader < u32 > ; # [doc = "Field `ADIMENSION_COUNT__NUMBER_2` writer - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
pub type AdimensionCount_Number2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
pub fn adimension_count__number_2 (& self) -> AdimensionCount_Number2R { AdimensionCount_Number2R :: new (self . bits & 0x007f_ffff) } } impl W { # [doc = "Bits 0:22 - 22:0\\]
A-Dimension count. Number of bytes to be transferred infirst dimension."]
# [inline (always)]
# [must_use]
pub fn adimension_count__number_2 (& mut self) -> AdimensionCount_Number2W < Dfacnt1Spec > { AdimensionCount_Number2W :: new (self , 0) } } # [doc = "Dst FIFO Set A-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfacnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfacnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfacnt1Spec ; impl crate :: RegisterSpec for Dfacnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfacnt1::R`](R) reader structure"]
impl crate :: Readable for Dfacnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfacnt1::W`](W) writer structure"]
impl crate :: Writable for Dfacnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFACNT1 to value 0"]
impl crate :: Resettable for Dfacnt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFDST1 (rw) register accessor: Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfdst1`]
module"]
# [doc (alias = "DFDST1")]
pub type Dfdst1 = crate :: Reg < dfdst1 :: Dfdst1Spec > ; # [doc = "Dst FIFO Set Dst Address"]
pub mod dfdst1 { # [doc = "Register `DFDST1` reader"]
pub type R = crate :: R < Dfdst1Spec > ; # [doc = "Register `DFDST1` writer"]
pub type W = crate :: W < Dfdst1Spec > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` reader - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3R = crate :: FieldReader < u32 > ; # [doc = "Field `DESTINATION_ADDRESS_FOR_3` writer - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
pub type DestinationAddressFor3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
pub fn destination_address_for_3 (& self) -> DestinationAddressFor3R { DestinationAddressFor3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode \\[OPT.SAM\\]
and/or dest index value \\[BIDX.DBIDX\\]
after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued."]
# [inline (always)]
# [must_use]
pub fn destination_address_for_3 (& mut self) -> DestinationAddressFor3W < Dfdst1Spec > { DestinationAddressFor3W :: new (self , 0) } } # [doc = "Dst FIFO Set Dst Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dfdst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfdst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfdst1Spec ; impl crate :: RegisterSpec for Dfdst1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfdst1::R`](R) reader structure"]
impl crate :: Readable for Dfdst1Spec { } # [doc = "`write(|w| ..)` method takes [`dfdst1::W`](W) writer structure"]
impl crate :: Writable for Dfdst1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFDST1 to value 0"]
impl crate :: Resettable for Dfdst1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBIDX1 (rw) register accessor: Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbidx1`]
module"]
# [doc (alias = "DFBIDX1")]
pub type Dfbidx1 = crate :: Reg < dfbidx1 :: Dfbidx1Spec > ; # [doc = "Dst FIFO Set B-Dim Idx"]
pub mod dfbidx1 { # [doc = "Register `DFBIDX1` reader"]
pub type R = crate :: R < Dfbidx1Spec > ; # [doc = "Register `DFBIDX1` writer"]
pub type W = crate :: W < Dfbidx1Spec > ; # [doc = "Field `SRC_BIDX_FOR` reader - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `SRC_BIDX_FOR` writer - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
pub type SrcBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DEST_BIDX_FOR` reader - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForR = crate :: FieldReader < u16 > ; # [doc = "Field `DEST_BIDX_FOR` writer - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
pub type DestBidxForW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
pub fn src_bidx_for (& self) -> SrcBidxForR { SrcBidxForR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
pub fn dest_bidx_for (& self) -> DestBidxForR { DestBidxForR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array \\[recall that there are BCNT arrays of ACNT elements\\].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn src_bidx_for (& mut self) -> SrcBidxForW < Dfbidx1Spec > { SrcBidxForW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array \\[recall that there are BCNT arrays of ACNT elements\\].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode."]
# [inline (always)]
# [must_use]
pub fn dest_bidx_for (& mut self) -> DestBidxForW < Dfbidx1Spec > { DestBidxForW :: new (self , 16) } } # [doc = "Dst FIFO Set B-Dim Idx\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbidx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbidx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbidx1Spec ; impl crate :: RegisterSpec for Dfbidx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbidx1::R`](R) reader structure"]
impl crate :: Readable for Dfbidx1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbidx1::W`](W) writer structure"]
impl crate :: Writable for Dfbidx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBIDX1 to value 0"]
impl crate :: Resettable for Dfbidx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFMPPRXY1 (rw) register accessor: Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfmpprxy1`]
module"]
# [doc (alias = "DFMPPRXY1")]
pub type Dfmpprxy1 = crate :: Reg < dfmpprxy1 :: Dfmpprxy1Spec > ; # [doc = "Dst FIFO Set Mem Protect Proxy"]
pub mod dfmpprxy1 { # [doc = "Register `DFMPPRXY1` reader"]
pub type R = crate :: R < Dfmpprxy1Spec > ; # [doc = "Register `DFMPPRXY1` writer"]
pub type W = crate :: W < Dfmpprxy1Spec > ; # [doc = "Field `PRIVILEGE_ID` reader - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdR = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID` writer - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
pub type PrivilegeIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PRIVILEGE_LEVEL` reader - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelR = crate :: BitReader ; # [doc = "Field `PRIVILEGE_LEVEL` writer - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
pub type PrivilegeLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SECURE_LEVEL` reader - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelR = crate :: BitReader ; # [doc = "Field `SECURE_LEVEL` writer - 9:9\\]
Secure Level: Deprecated, always read as 0."]
pub type SecureLevelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_id (& self) -> PrivilegeIdR { PrivilegeIdR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
pub fn privilege_level (& self) -> PrivilegeLevelR { PrivilegeLevelR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
pub fn secure_level (& self) -> SecureLevelR { SecureLevelR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_id (& mut self) -> PrivilegeIdW < Dfmpprxy1Spec > { PrivilegeIdW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register \\[trigger register\\].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction."]
# [inline (always)]
# [must_use]
pub fn privilege_level (& mut self) -> PrivilegeLevelW < Dfmpprxy1Spec > { PrivilegeLevelW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Secure Level: Deprecated, always read as 0."]
# [inline (always)]
# [must_use]
pub fn secure_level (& mut self) -> SecureLevelW < Dfmpprxy1Spec > { SecureLevelW :: new (self , 9) } } # [doc = "Dst FIFO Set Mem Protect Proxy\n\nYou can [`read`](crate::Reg::read) this register and get [`dfmpprxy1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfmpprxy1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfmpprxy1Spec ; impl crate :: RegisterSpec for Dfmpprxy1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfmpprxy1::R`](R) reader structure"]
impl crate :: Readable for Dfmpprxy1Spec { } # [doc = "`write(|w| ..)` method takes [`dfmpprxy1::W`](W) writer structure"]
impl crate :: Writable for Dfmpprxy1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFMPPRXY1 to value 0"]
impl crate :: Resettable for Dfmpprxy1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFBCNT1 (rw) register accessor: Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfbcnt1`]
module"]
# [doc (alias = "DFBCNT1")]
pub type Dfbcnt1 = crate :: Reg < dfbcnt1 :: Dfbcnt1Spec > ; # [doc = "Dst FIFO Set B-Count"]
pub mod dfbcnt1 { # [doc = "Register `DFBCNT1` reader"]
pub type R = crate :: R < Dfbcnt1Spec > ; # [doc = "Register `DFBCNT1` writer"]
pub type W = crate :: W < Dfbcnt1Spec > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` reader - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1R = crate :: FieldReader < u16 > ; # [doc = "Field `BCOUNT_REMAINING_FOR_1` writer - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
pub type BcountRemainingFor1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
pub fn bcount_remaining_for_1 (& self) -> BcountRemainingFor1R { BcountRemainingFor1R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete."]
# [inline (always)]
# [must_use]
pub fn bcount_remaining_for_1 (& mut self) -> BcountRemainingFor1W < Dfbcnt1Spec > { BcountRemainingFor1W :: new (self , 0) } } # [doc = "Dst FIFO Set B-Count\n\nYou can [`read`](crate::Reg::read) this register and get [`dfbcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfbcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dfbcnt1Spec ; impl crate :: RegisterSpec for Dfbcnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dfbcnt1::R`](R) reader structure"]
impl crate :: Readable for Dfbcnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dfbcnt1::W`](W) writer structure"]
impl crate :: Writable for Dfbcnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFBCNT1 to value 0"]
impl crate :: Resettable for Dfbcnt1Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "TPCC"]
pub struct TpccB { _marker : PhantomData < * const () > } unsafe impl Send for TpccB { } impl TpccB { # [doc = r"Pointer to the register block"]
pub const PTR : * const tpcc_b :: RegisterBlock = 0x5508_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tpcc_b :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TpccB { type Target = tpcc_b :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TpccB { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TpccB") . finish () } } # [doc = "TPCC"]
pub mod tpcc_b { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , cccfg : Cccfg , _reserved2 : [u8 ; 0x01f8]
, qchmapn : Qchmapn , _reserved3 : [u8 ; 0x3c]
, dmaqnumn : Dmaqnumn , _reserved4 : [u8 ; 0x1c]
, qdmaqnum : Qdmaqnum , _reserved5 : [u8 ; 0x1c]
, quetcmap : Quetcmap , quepri : Quepri , _reserved7 : [u8 ; 0x78]
, emr : Emr , emrh : Emrh , emcr : Emcr , emcrh : Emcrh , qemr : Qemr , qemcr : Qemcr , ccerr : Ccerr , ccerrclr : Ccerrclr , eeval : Eeval , _reserved16 : [u8 ; 0x1c]
, draem : Draem , draehm : Draehm , _reserved18 : [u8 ; 0x38]
, qraen : Qraen , _reserved19 : [u8 ; 0x7c]
, qne0 : Qne0 , qne1 : Qne1 , qne2 : Qne2 , qne3 : Qne3 , qne4 : Qne4 , qne5 : Qne5 , qne6 : Qne6 , qne7 : Qne7 , qne8 : Qne8 , qne9 : Qne9 , qne10 : Qne10 , qne11 : Qne11 , qne12 : Qne12 , qne13 : Qne13 , qne14 : Qne14 , qne15 : Qne15 , _reserved35 : [u8 ; 0x01c0]
, qstatn : Qstatn , _reserved36 : [u8 ; 0x1c]
, qwmthra : Qwmthra , _reserved37 : [u8 ; 0x1c]
, ccstat : Ccstat , _reserved38 : [u8 ; 0xbc]
, aetctl : Aetctl , aetstat : Aetstat , aetcmd : Aetcmd , _reserved41 : [u8 ; 0x08f4]
, er : Er , erh : Erh , ecr : Ecr , ecrh : Ecrh , esr : Esr , esrh : Esrh , cer : Cer , cerh : Cerh , eer : Eer , eerh : Eerh , eecr : Eecr , eecrh : Eecrh , eesr : Eesr , eesrh : Eesrh , ser : Ser , serh : Serh , secr : Secr , secrh : Secrh , _reserved59 : [u8 ; 0x08]
, ier : Ier , ierh : Ierh , iecr : Iecr , iecrh : Iecrh , iesr : Iesr , iesrh : Iesrh , ipr : Ipr , iprh : Iprh , icr : Icr , icrh : Icrh , ieval : Ieval , _reserved70 : [u8 ; 0x04]
, qer : Qer , qeer : Qeer , qeecr : Qeecr , qeesr : Qeesr , qser : Qser , qsecr : Qsecr , _reserved76 : [u8 ; 0x0f68]
, er_rn : ErRn , erh_rn : ErhRn , ecr_rn : EcrRn , ecrh_rn : EcrhRn , esr_rn : EsrRn , esrh_rn : EsrhRn , cer_rn : CerRn , cerh_rn : CerhRn , eer_rn : EerRn , eerh_rn : EerhRn , eecr_rn : EecrRn , eecrh_rn : EecrhRn , eesr_rn : EesrRn , eesrh_rn : EesrhRn , ser_rn : SerRn , serh_rn : SerhRn , secr_rn : SecrRn , secrh_rn : SecrhRn , _reserved94 : [u8 ; 0x08]
, ier_rn : IerRn , ierh_rn : IerhRn , iecr_rn : IecrRn , iecrh_rn : IecrhRn , iesr_rn : IesrRn , iesrh_rn : IesrhRn , ipr_rn : IprRn , iprh_rn : IprhRn , icr_rn : IcrRn , icrh_rn : IcrhRn , ieval_rn : IevalRn , _reserved105 : [u8 ; 0x04]
, qer_rn : QerRn , qeer_rn : QeerRn , qeecr_rn : QeecrRn , qeesr_rn : QeesrRn , qser_rn : QserRn , qsecr_rn : QsecrRn , _reserved111 : [u8 ; 0x1f68]
, opt : Opt , src : Src , abcnt : Abcnt , dst : Dst , bidx : Bidx , lnk : Lnk , cidx : Cidx , ccnt : Ccnt , } impl RegisterBlock { # [doc = "0x00 - Peripheral ID Register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - CC Configuration Register"]
# [inline (always)]
pub const fn cccfg (& self) -> & Cccfg { & self . cccfg } # [doc = "0x200 - QDMA Channel N Mapping Register"]
# [inline (always)]
pub const fn qchmapn (& self) -> & Qchmapn { & self . qchmapn } # [doc = "0x240 - DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."]
# [inline (always)]
pub const fn dmaqnumn (& self) -> & Dmaqnumn { & self . dmaqnumn } # [doc = "0x260 - QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."]
# [inline (always)]
pub const fn qdmaqnum (& self) -> & Qdmaqnum { & self . qdmaqnum } # [doc = "0x280 - Queue to TC Mapping"]
# [inline (always)]
pub const fn quetcmap (& self) -> & Quetcmap { & self . quetcmap } # [doc = "0x284 - Queue Priority"]
# [inline (always)]
pub const fn quepri (& self) -> & Quepri { & self . quepri } # [doc = "0x300 - Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub const fn emr (& self) -> & Emr { & self . emr } # [doc = "0x304 - Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub const fn emrh (& self) -> & Emrh { & self . emrh } # [doc = "0x308 - Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
# [inline (always)]
pub const fn emcr (& self) -> & Emcr { & self . emcr } # [doc = "0x30c - Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
# [inline (always)]
pub const fn emcrh (& self) -> & Emcrh { & self . emcrh } # [doc = "0x310 - QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub const fn qemr (& self) -> & Qemr { & self . qemr } # [doc = "0x314 - QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
# [inline (always)]
pub const fn qemcr (& self) -> & Qemcr { & self . qemcr } # [doc = "0x318 - CC Error Register"]
# [inline (always)]
pub const fn ccerr (& self) -> & Ccerr { & self . ccerr } # [doc = "0x31c - CC Error Clear Register"]
# [inline (always)]
pub const fn ccerrclr (& self) -> & Ccerrclr { & self . ccerrclr } # [doc = "0x320 - Error Eval Register"]
# [inline (always)]
pub const fn eeval (& self) -> & Eeval { & self . eeval } # [doc = "0x340 - DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
# [inline (always)]
pub const fn draem (& self) -> & Draem { & self . draem } # [doc = "0x344 - DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
# [inline (always)]
pub const fn draehm (& self) -> & Draehm { & self . draehm } # [doc = "0x380 - QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt."]
# [inline (always)]
pub const fn qraen (& self) -> & Qraen { & self . qraen } # [doc = "0x400 - Event Queue Entry Diagram for Queue n - Entry 0"]
# [inline (always)]
pub const fn qne0 (& self) -> & Qne0 { & self . qne0 } # [doc = "0x404 - Event Queue Entry Diagram for Queue n - Entry 1"]
# [inline (always)]
pub const fn qne1 (& self) -> & Qne1 { & self . qne1 } # [doc = "0x408 - Event Queue Entry Diagram for Queue n - Entry 2"]
# [inline (always)]
pub const fn qne2 (& self) -> & Qne2 { & self . qne2 } # [doc = "0x40c - Event Queue Entry Diagram for Queue n - Entry 3"]
# [inline (always)]
pub const fn qne3 (& self) -> & Qne3 { & self . qne3 } # [doc = "0x410 - Event Queue Entry Diagram for Queue n - Entry 4"]
# [inline (always)]
pub const fn qne4 (& self) -> & Qne4 { & self . qne4 } # [doc = "0x414 - Event Queue Entry Diagram for Queue n - Entry 5"]
# [inline (always)]
pub const fn qne5 (& self) -> & Qne5 { & self . qne5 } # [doc = "0x418 - Event Queue Entry Diagram for Queue n - Entry 6"]
# [inline (always)]
pub const fn qne6 (& self) -> & Qne6 { & self . qne6 } # [doc = "0x41c - Event Queue Entry Diagram for Queue n - Entry 7"]
# [inline (always)]
pub const fn qne7 (& self) -> & Qne7 { & self . qne7 } # [doc = "0x420 - Event Queue Entry Diagram for Queue n - Entry 8"]
# [inline (always)]
pub const fn qne8 (& self) -> & Qne8 { & self . qne8 } # [doc = "0x424 - Event Queue Entry Diagram for Queue n - Entry 9"]
# [inline (always)]
pub const fn qne9 (& self) -> & Qne9 { & self . qne9 } # [doc = "0x428 - Event Queue Entry Diagram for Queue n - Entry 0"]
# [inline (always)]
pub const fn qne10 (& self) -> & Qne10 { & self . qne10 } # [doc = "0x42c - Event Queue Entry Diagram for Queue n - Entry 11"]
# [inline (always)]
pub const fn qne11 (& self) -> & Qne11 { & self . qne11 } # [doc = "0x430 - Event Queue Entry Diagram for Queue n - Entry 12"]
# [inline (always)]
pub const fn qne12 (& self) -> & Qne12 { & self . qne12 } # [doc = "0x434 - Event Queue Entry Diagram for Queue n - Entry 13"]
# [inline (always)]
pub const fn qne13 (& self) -> & Qne13 { & self . qne13 } # [doc = "0x438 - Event Queue Entry Diagram for Queue n - Entry 14"]
# [inline (always)]
pub const fn qne14 (& self) -> & Qne14 { & self . qne14 } # [doc = "0x43c - Event Queue Entry Diagram for Queue n - Entry 15"]
# [inline (always)]
pub const fn qne15 (& self) -> & Qne15 { & self . qne15 } # [doc = "0x600 - QSTATn Register Set"]
# [inline (always)]
pub const fn qstatn (& self) -> & Qstatn { & self . qstatn } # [doc = "0x620 - Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors."]
# [inline (always)]
pub const fn qwmthra (& self) -> & Qwmthra { & self . qwmthra } # [doc = "0x640 - CC Status Register"]
# [inline (always)]
pub const fn ccstat (& self) -> & Ccstat { & self . ccstat } # [doc = "0x700 - Advanced Event Trigger Control"]
# [inline (always)]
pub const fn aetctl (& self) -> & Aetctl { & self . aetctl } # [doc = "0x704 - Advanced Event Trigger Stat"]
# [inline (always)]
pub const fn aetstat (& self) -> & Aetstat { & self . aetstat } # [doc = "0x708 - AET Command"]
# [inline (always)]
pub const fn aetcmd (& self) -> & Aetcmd { & self . aetcmd } # [doc = "0x1000 - Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
# [inline (always)]
pub const fn er (& self) -> & Er { & self . er } # [doc = "0x1004 - Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
# [inline (always)]
pub const fn erh (& self) -> & Erh { & self . erh } # [doc = "0x1008 - Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecr (& self) -> & Ecr { & self . ecr } # [doc = "0x100c - Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecrh (& self) -> & Ecrh { & self . ecrh } # [doc = "0x1010 - Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esr (& self) -> & Esr { & self . esr } # [doc = "0x1014 - Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esrh (& self) -> & Esrh { & self . esrh } # [doc = "0x1018 - Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cer (& self) -> & Cer { & self . cer } # [doc = "0x101c - Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cerh (& self) -> & Cerh { & self . cerh } # [doc = "0x1020 - Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eer (& self) -> & Eer { & self . eer } # [doc = "0x1024 - Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eerh (& self) -> & Eerh { & self . eerh } # [doc = "0x1028 - Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecr (& self) -> & Eecr { & self . eecr } # [doc = "0x102c - Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecrh (& self) -> & Eecrh { & self . eecrh } # [doc = "0x1030 - Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesr (& self) -> & Eesr { & self . eesr } # [doc = "0x1034 - Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesrh (& self) -> & Eesrh { & self . eesrh } # [doc = "0x1038 - Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn ser (& self) -> & Ser { & self . ser } # [doc = "0x103c - Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn serh (& self) -> & Serh { & self . serh } # [doc = "0x1040 - Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secr (& self) -> & Secr { & self . secr } # [doc = "0x1044 - Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secrh (& self) -> & Secrh { & self . secrh } # [doc = "0x1050 - Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ier (& self) -> & Ier { & self . ier } # [doc = "0x1054 - Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ierh (& self) -> & Ierh { & self . ierh } # [doc = "0x1058 - Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecr (& self) -> & Iecr { & self . iecr } # [doc = "0x105c - Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecrh (& self) -> & Iecrh { & self . iecrh } # [doc = "0x1060 - Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesr (& self) -> & Iesr { & self . iesr } # [doc = "0x1064 - Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesrh (& self) -> & Iesrh { & self . iesrh } # [doc = "0x1068 - Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
# [inline (always)]
pub const fn ipr (& self) -> & Ipr { & self . ipr } # [doc = "0x106c - Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
# [inline (always)]
pub const fn iprh (& self) -> & Iprh { & self . iprh } # [doc = "0x1070 - Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icr (& self) -> & Icr { & self . icr } # [doc = "0x1074 - Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icrh (& self) -> & Icrh { & self . icrh } # [doc = "0x1078 - Interrupt Eval Register"]
# [inline (always)]
pub const fn ieval (& self) -> & Ieval { & self . ieval } # [doc = "0x1080 - QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
# [inline (always)]
pub const fn qer (& self) -> & Qer { & self . qer } # [doc = "0x1084 - QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
# [inline (always)]
pub const fn qeer (& self) -> & Qeer { & self . qeer } # [doc = "0x1088 - QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeecr (& self) -> & Qeecr { & self . qeecr } # [doc = "0x108c - QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeesr (& self) -> & Qeesr { & self . qeesr } # [doc = "0x1090 - QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn qser (& self) -> & Qser { & self . qser } # [doc = "0x1094 - QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qsecr (& self) -> & Qsecr { & self . qsecr } # [doc = "0x2000 - Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
# [inline (always)]
pub const fn er_rn (& self) -> & ErRn { & self . er_rn } # [doc = "0x2004 - Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
# [inline (always)]
pub const fn erh_rn (& self) -> & ErhRn { & self . erh_rn } # [doc = "0x2008 - Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecr_rn (& self) -> & EcrRn { & self . ecr_rn } # [doc = "0x200c - Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecrh_rn (& self) -> & EcrhRn { & self . ecrh_rn } # [doc = "0x2010 - Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esr_rn (& self) -> & EsrRn { & self . esr_rn } # [doc = "0x2014 - Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esrh_rn (& self) -> & EsrhRn { & self . esrh_rn } # [doc = "0x2018 - Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cer_rn (& self) -> & CerRn { & self . cer_rn } # [doc = "0x201c - Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cerh_rn (& self) -> & CerhRn { & self . cerh_rn } # [doc = "0x2020 - Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eer_rn (& self) -> & EerRn { & self . eer_rn } # [doc = "0x2024 - Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eerh_rn (& self) -> & EerhRn { & self . eerh_rn } # [doc = "0x2028 - Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecr_rn (& self) -> & EecrRn { & self . eecr_rn } # [doc = "0x202c - Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecrh_rn (& self) -> & EecrhRn { & self . eecrh_rn } # [doc = "0x2030 - Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesr_rn (& self) -> & EesrRn { & self . eesr_rn } # [doc = "0x2034 - Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesrh_rn (& self) -> & EesrhRn { & self . eesrh_rn } # [doc = "0x2038 - Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn ser_rn (& self) -> & SerRn { & self . ser_rn } # [doc = "0x203c - Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn serh_rn (& self) -> & SerhRn { & self . serh_rn } # [doc = "0x2040 - Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secr_rn (& self) -> & SecrRn { & self . secr_rn } # [doc = "0x2044 - Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secrh_rn (& self) -> & SecrhRn { & self . secrh_rn } # [doc = "0x2050 - Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ier_rn (& self) -> & IerRn { & self . ier_rn } # [doc = "0x2054 - Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ierh_rn (& self) -> & IerhRn { & self . ierh_rn } # [doc = "0x2058 - Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecr_rn (& self) -> & IecrRn { & self . iecr_rn } # [doc = "0x205c - Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecrh_rn (& self) -> & IecrhRn { & self . iecrh_rn } # [doc = "0x2060 - Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesr_rn (& self) -> & IesrRn { & self . iesr_rn } # [doc = "0x2064 - Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesrh_rn (& self) -> & IesrhRn { & self . iesrh_rn } # [doc = "0x2068 - Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
# [inline (always)]
pub const fn ipr_rn (& self) -> & IprRn { & self . ipr_rn } # [doc = "0x206c - Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
# [inline (always)]
pub const fn iprh_rn (& self) -> & IprhRn { & self . iprh_rn } # [doc = "0x2070 - Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icr_rn (& self) -> & IcrRn { & self . icr_rn } # [doc = "0x2074 - Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icrh_rn (& self) -> & IcrhRn { & self . icrh_rn } # [doc = "0x2078 - Interrupt Eval Register"]
# [inline (always)]
pub const fn ieval_rn (& self) -> & IevalRn { & self . ieval_rn } # [doc = "0x2080 - QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
# [inline (always)]
pub const fn qer_rn (& self) -> & QerRn { & self . qer_rn } # [doc = "0x2084 - QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
# [inline (always)]
pub const fn qeer_rn (& self) -> & QeerRn { & self . qeer_rn } # [doc = "0x2088 - QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeecr_rn (& self) -> & QeecrRn { & self . qeecr_rn } # [doc = "0x208c - QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeesr_rn (& self) -> & QeesrRn { & self . qeesr_rn } # [doc = "0x2090 - QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn qser_rn (& self) -> & QserRn { & self . qser_rn } # [doc = "0x2094 - QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qsecr_rn (& self) -> & QsecrRn { & self . qsecr_rn } # [doc = "0x4000 - Options Parameter"]
# [inline (always)]
pub const fn opt (& self) -> & Opt { & self . opt } # [doc = "0x4004 - Source Address"]
# [inline (always)]
pub const fn src (& self) -> & Src { & self . src } # [doc = "0x4008 - A and B byte count"]
# [inline (always)]
pub const fn abcnt (& self) -> & Abcnt { & self . abcnt } # [doc = "0x400c - Destination Address"]
# [inline (always)]
pub const fn dst (& self) -> & Dst { & self . dst } # [doc = "0x4010 - Register description is not available"]
# [inline (always)]
pub const fn bidx (& self) -> & Bidx { & self . bidx } # [doc = "0x4014 - Link and Reload parameters"]
# [inline (always)]
pub const fn lnk (& self) -> & Lnk { & self . lnk } # [doc = "0x4018 - Register description is not available"]
# [inline (always)]
pub const fn cidx (& self) -> & Cidx { & self . cidx } # [doc = "0x401c - C byte count"]
# [inline (always)]
pub const fn ccnt (& self) -> & Ccnt { & self . ccnt } } # [doc = "PID (rw) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "Peripheral ID Register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR` reader - 5:0\\]
Minor Revision"]
pub type MinorR = crate :: FieldReader ; # [doc = "Field `MINOR` writer - 5:0\\]
Minor Revision"]
pub type MinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR` reader - 10:8\\]
Major Revision"]
pub type MajorR = crate :: FieldReader ; # [doc = "Field `MAJOR` writer - 10:8\\]
Major Revision"]
pub type MajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL` reader - 15:11\\]
RTL Version"]
pub type RtlR = crate :: FieldReader ; # [doc = "Field `RTL` writer - 15:11\\]
RTL Version"]
pub type RtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNC` reader - 27:16\\]
Function indicates a software compatible module family."]
pub type FuncR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNC` writer - 27:16\\]
Function indicates a software compatible module family."]
pub type FuncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `RES1` reader - 29:28\\]
RESERVE FIELD"]
pub type Res1R = crate :: FieldReader ; # [doc = "Field `RES1` writer - 29:28\\]
RESERVE FIELD"]
pub type Res1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
pub fn minor (& self) -> MinorR { MinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
pub fn major (& self) -> MajorR { MajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
pub fn rtl (& self) -> RtlR { RtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
pub fn func (& self) -> FuncR { FuncR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res1 (& self) -> Res1R { Res1R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
# [must_use]
pub fn minor (& mut self) -> MinorW < PidSpec > { MinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < PidSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
# [must_use]
pub fn major (& mut self) -> MajorW < PidSpec > { MajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
# [must_use]
pub fn rtl (& mut self) -> RtlW < PidSpec > { RtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
# [must_use]
pub fn func (& mut self) -> FuncW < PidSpec > { FuncW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res1 (& mut self) -> Res1W < PidSpec > { Res1W :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < PidSpec > { SchemeW :: new (self , 30) } } # [doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCCFG (rw) register accessor: CC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cccfg`]
module"]
# [doc (alias = "CCCFG")]
pub type Cccfg = crate :: Reg < cccfg :: CccfgSpec > ; # [doc = "CC Configuration Register"]
pub mod cccfg { # [doc = "Register `CCCFG` reader"]
pub type R = crate :: R < CccfgSpec > ; # [doc = "Register `CCCFG` writer"]
pub type W = crate :: W < CccfgSpec > ; # [doc = "Field `NUMDMACH` reader - 2:0\\]
Number of DMA Channels"]
pub type NumdmachR = crate :: FieldReader ; # [doc = "Field `NUMDMACH` writer - 2:0\\]
Number of DMA Channels"]
pub type NumdmachW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES8` reader - 3:3\\]
RESERVE FIELD"]
pub type Res8R = crate :: BitReader ; # [doc = "Field `RES8` writer - 3:3\\]
RESERVE FIELD"]
pub type Res8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMQDMACH` reader - 6:4\\]
Number of QDMA Channels"]
pub type NumqdmachR = crate :: FieldReader ; # [doc = "Field `NUMQDMACH` writer - 6:4\\]
Number of QDMA Channels"]
pub type NumqdmachW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES7` reader - 7:7\\]
RESERVE FIELD"]
pub type Res7R = crate :: BitReader ; # [doc = "Field `RES7` writer - 7:7\\]
RESERVE FIELD"]
pub type Res7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMINTCH` reader - 10:8\\]
Number of Interrupt Channels"]
pub type NumintchR = crate :: FieldReader ; # [doc = "Field `NUMINTCH` writer - 10:8\\]
Number of Interrupt Channels"]
pub type NumintchW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES6` reader - 11:11\\]
RESERVE FIELD"]
pub type Res6R = crate :: BitReader ; # [doc = "Field `RES6` writer - 11:11\\]
RESERVE FIELD"]
pub type Res6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMPAENTRY` reader - 14:12\\]
Number of PaRAM entries"]
pub type NumpaentryR = crate :: FieldReader ; # [doc = "Field `NUMPAENTRY` writer - 14:12\\]
Number of PaRAM entries"]
pub type NumpaentryW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES5` reader - 15:15\\]
RESERVE FIELD"]
pub type Res5R = crate :: BitReader ; # [doc = "Field `RES5` writer - 15:15\\]
RESERVE FIELD"]
pub type Res5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMTC` reader - 18:16\\]
Number of Queues/Number of TCs"]
pub type NumtcR = crate :: FieldReader ; # [doc = "Field `NUMTC` writer - 18:16\\]
Number of Queues/Number of TCs"]
pub type NumtcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES4` reader - 19:19\\]
RESERVE FIELD"]
pub type Res4R = crate :: BitReader ; # [doc = "Field `RES4` writer - 19:19\\]
RESERVE FIELD"]
pub type Res4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMREGN` reader - 21:20\\]
Number of MP and Shadow regions"]
pub type NumregnR = crate :: FieldReader ; # [doc = "Field `NUMREGN` writer - 21:20\\]
Number of MP and Shadow regions"]
pub type NumregnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES3` reader - 23:22\\]
RESERVE FIELD"]
pub type Res3R = crate :: FieldReader ; # [doc = "Field `RES3` writer - 23:22\\]
RESERVE FIELD"]
pub type Res3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CHMAPEXIST` reader - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
pub type ChmapexistR = crate :: BitReader ; # [doc = "Field `CHMAPEXIST` writer - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
pub type ChmapexistW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MPEXIST` reader - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
pub type MpexistR = crate :: BitReader ; # [doc = "Field `MPEXIST` writer - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
pub type MpexistW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES2` reader - 31:26\\]
RESERVE FIELD"]
pub type Res2R = crate :: FieldReader ; # [doc = "Field `RES2` writer - 31:26\\]
RESERVE FIELD"]
pub type Res2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Number of DMA Channels"]
# [inline (always)]
pub fn numdmach (& self) -> NumdmachR { NumdmachR :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res8 (& self) -> Res8R { Res8R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Number of QDMA Channels"]
# [inline (always)]
pub fn numqdmach (& self) -> NumqdmachR { NumqdmachR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res7 (& self) -> Res7R { Res7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
Number of Interrupt Channels"]
# [inline (always)]
pub fn numintch (& self) -> NumintchR { NumintchR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res6 (& self) -> Res6R { Res6R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - 14:12\\]
Number of PaRAM entries"]
# [inline (always)]
pub fn numpaentry (& self) -> NumpaentryR { NumpaentryR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res5 (& self) -> Res5R { Res5R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
Number of Queues/Number of TCs"]
# [inline (always)]
pub fn numtc (& self) -> NumtcR { NumtcR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res4 (& self) -> Res4R { Res4R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:21 - 21:20\\]
Number of MP and Shadow regions"]
# [inline (always)]
pub fn numregn (& self) -> NumregnR { NumregnR :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - 23:22\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res3 (& self) -> Res3R { Res3R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bit 24 - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
# [inline (always)]
pub fn chmapexist (& self) -> ChmapexistR { ChmapexistR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
# [inline (always)]
pub fn mpexist (& self) -> MpexistR { MpexistR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res2 (& self) -> Res2R { Res2R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Number of DMA Channels"]
# [inline (always)]
# [must_use]
pub fn numdmach (& mut self) -> NumdmachW < CccfgSpec > { NumdmachW :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res8 (& mut self) -> Res8W < CccfgSpec > { Res8W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Number of QDMA Channels"]
# [inline (always)]
# [must_use]
pub fn numqdmach (& mut self) -> NumqdmachW < CccfgSpec > { NumqdmachW :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res7 (& mut self) -> Res7W < CccfgSpec > { Res7W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
Number of Interrupt Channels"]
# [inline (always)]
# [must_use]
pub fn numintch (& mut self) -> NumintchW < CccfgSpec > { NumintchW :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res6 (& mut self) -> Res6W < CccfgSpec > { Res6W :: new (self , 11) } # [doc = "Bits 12:14 - 14:12\\]
Number of PaRAM entries"]
# [inline (always)]
# [must_use]
pub fn numpaentry (& mut self) -> NumpaentryW < CccfgSpec > { NumpaentryW :: new (self , 12) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res5 (& mut self) -> Res5W < CccfgSpec > { Res5W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
Number of Queues/Number of TCs"]
# [inline (always)]
# [must_use]
pub fn numtc (& mut self) -> NumtcW < CccfgSpec > { NumtcW :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res4 (& mut self) -> Res4W < CccfgSpec > { Res4W :: new (self , 19) } # [doc = "Bits 20:21 - 21:20\\]
Number of MP and Shadow regions"]
# [inline (always)]
# [must_use]
pub fn numregn (& mut self) -> NumregnW < CccfgSpec > { NumregnW :: new (self , 20) } # [doc = "Bits 22:23 - 23:22\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res3 (& mut self) -> Res3W < CccfgSpec > { Res3W :: new (self , 22) } # [doc = "Bit 24 - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
# [inline (always)]
# [must_use]
pub fn chmapexist (& mut self) -> ChmapexistW < CccfgSpec > { ChmapexistW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
# [inline (always)]
# [must_use]
pub fn mpexist (& mut self) -> MpexistW < CccfgSpec > { MpexistW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res2 (& mut self) -> Res2W < CccfgSpec > { Res2W :: new (self , 26) } } # [doc = "CC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CccfgSpec ; impl crate :: RegisterSpec for CccfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cccfg::R`](R) reader structure"]
impl crate :: Readable for CccfgSpec { } # [doc = "`write(|w| ..)` method takes [`cccfg::W`](W) writer structure"]
impl crate :: Writable for CccfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCCFG to value 0"]
impl crate :: Resettable for CccfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QCHMAPN (rw) register accessor: QDMA Channel N Mapping Register\n\nYou can [`read`](crate::Reg::read) this register and get [`qchmapn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qchmapn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qchmapn`]
module"]
# [doc (alias = "QCHMAPN")]
pub type Qchmapn = crate :: Reg < qchmapn :: QchmapnSpec > ; # [doc = "QDMA Channel N Mapping Register"]
pub mod qchmapn { # [doc = "Register `QCHMAPN` reader"]
pub type R = crate :: R < QchmapnSpec > ; # [doc = "Register `QCHMAPN` writer"]
pub type W = crate :: W < QchmapnSpec > ; # [doc = "Field `TRWORD` reader - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
pub type TrwordR = crate :: FieldReader ; # [doc = "Field `TRWORD` writer - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
pub type TrwordW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PAENTRY` reader - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
pub type PaentryR = crate :: FieldReader < u16 > ; # [doc = "Field `PAENTRY` writer - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
pub type PaentryW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `RES10` reader - 31:14\\]
RESERVE FIELD"]
pub type Res10R = crate :: FieldReader < u32 > ; # [doc = "Field `RES10` writer - 31:14\\]
RESERVE FIELD"]
pub type Res10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bits 2:4 - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
# [inline (always)]
pub fn trword (& self) -> TrwordR { TrwordR :: new (((self . bits >> 2) & 7) as u8) } # [doc = "Bits 5:13 - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
# [inline (always)]
pub fn paentry (& self) -> PaentryR { PaentryR :: new (((self . bits >> 5) & 0x01ff) as u16) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res10 (& self) -> Res10R { Res10R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bits 2:4 - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
# [inline (always)]
# [must_use]
pub fn trword (& mut self) -> TrwordW < QchmapnSpec > { TrwordW :: new (self , 2) } # [doc = "Bits 5:13 - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
# [inline (always)]
# [must_use]
pub fn paentry (& mut self) -> PaentryW < QchmapnSpec > { PaentryW :: new (self , 5) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res10 (& mut self) -> Res10W < QchmapnSpec > { Res10W :: new (self , 14) } } # [doc = "QDMA Channel N Mapping Register\n\nYou can [`read`](crate::Reg::read) this register and get [`qchmapn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qchmapn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QchmapnSpec ; impl crate :: RegisterSpec for QchmapnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qchmapn::R`](R) reader structure"]
impl crate :: Readable for QchmapnSpec { } # [doc = "`write(|w| ..)` method takes [`qchmapn::W`](W) writer structure"]
impl crate :: Writable for QchmapnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QCHMAPN to value 0"]
impl crate :: Resettable for QchmapnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMAQNUMN (rw) register accessor: DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaqnumn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaqnumn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaqnumn`]
module"]
# [doc (alias = "DMAQNUMN")]
pub type Dmaqnumn = crate :: Reg < dmaqnumn :: DmaqnumnSpec > ; # [doc = "DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."]
pub mod dmaqnumn { # [doc = "Register `DMAQNUMN` reader"]
pub type R = crate :: R < DmaqnumnSpec > ; # [doc = "Register `DMAQNUMN` writer"]
pub type W = crate :: W < DmaqnumnSpec > ; # [doc = "Field `E0` reader - 2:0\\]
DMA Queue Number for event #0"]
pub type E0R = crate :: FieldReader ; # [doc = "Field `E0` writer - 2:0\\]
DMA Queue Number for event #0"]
pub type E0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES18` reader - 3:3\\]
RESERVE FIELD"]
pub type Res18R = crate :: BitReader ; # [doc = "Field `RES18` writer - 3:3\\]
RESERVE FIELD"]
pub type Res18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 6:4\\]
DMA Queue Number for event #1"]
pub type E1R = crate :: FieldReader ; # [doc = "Field `E1` writer - 6:4\\]
DMA Queue Number for event #1"]
pub type E1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES17` reader - 7:7\\]
RESERVE FIELD"]
pub type Res17R = crate :: BitReader ; # [doc = "Field `RES17` writer - 7:7\\]
RESERVE FIELD"]
pub type Res17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 10:8\\]
DMA Queue Number for event #2"]
pub type E2R = crate :: FieldReader ; # [doc = "Field `E2` writer - 10:8\\]
DMA Queue Number for event #2"]
pub type E2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES16` reader - 11:11\\]
RESERVE FIELD"]
pub type Res16R = crate :: BitReader ; # [doc = "Field `RES16` writer - 11:11\\]
RESERVE FIELD"]
pub type Res16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 14:12\\]
DMA Queue Number for event #3"]
pub type E3R = crate :: FieldReader ; # [doc = "Field `E3` writer - 14:12\\]
DMA Queue Number for event #3"]
pub type E3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES15` reader - 15:15\\]
RESERVE FIELD"]
pub type Res15R = crate :: BitReader ; # [doc = "Field `RES15` writer - 15:15\\]
RESERVE FIELD"]
pub type Res15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 18:16\\]
DMA Queue Number for event #4"]
pub type E4R = crate :: FieldReader ; # [doc = "Field `E4` writer - 18:16\\]
DMA Queue Number for event #4"]
pub type E4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES14` reader - 19:19\\]
RESERVE FIELD"]
pub type Res14R = crate :: BitReader ; # [doc = "Field `RES14` writer - 19:19\\]
RESERVE FIELD"]
pub type Res14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 22:20\\]
DMA Queue Number for event #5"]
pub type E5R = crate :: FieldReader ; # [doc = "Field `E5` writer - 22:20\\]
DMA Queue Number for event #5"]
pub type E5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES13` reader - 23:23\\]
RESERVE FIELD"]
pub type Res13R = crate :: BitReader ; # [doc = "Field `RES13` writer - 23:23\\]
RESERVE FIELD"]
pub type Res13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 26:24\\]
DMA Queue Number for event #6"]
pub type E6R = crate :: FieldReader ; # [doc = "Field `E6` writer - 26:24\\]
DMA Queue Number for event #6"]
pub type E6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES12` reader - 27:27\\]
RESERVE FIELD"]
pub type Res12R = crate :: BitReader ; # [doc = "Field `RES12` writer - 27:27\\]
RESERVE FIELD"]
pub type Res12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 30:28\\]
DMA Queue Number for event #7"]
pub type E7R = crate :: FieldReader ; # [doc = "Field `E7` writer - 30:28\\]
DMA Queue Number for event #7"]
pub type E7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES11` reader - 31:31\\]
RESERVE FIELD"]
pub type Res11R = crate :: BitReader ; # [doc = "Field `RES11` writer - 31:31\\]
RESERVE FIELD"]
pub type Res11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
DMA Queue Number for event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res18 (& self) -> Res18R { Res18R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
DMA Queue Number for event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res17 (& self) -> Res17R { Res17R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
DMA Queue Number for event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res16 (& self) -> Res16R { Res16R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - 14:12\\]
DMA Queue Number for event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res15 (& self) -> Res15R { Res15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
DMA Queue Number for event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res14 (& self) -> Res14R { Res14R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:22 - 22:20\\]
DMA Queue Number for event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 20) & 7) as u8) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res13 (& self) -> Res13R { Res13R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - 26:24\\]
DMA Queue Number for event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res12 (& self) -> Res12R { Res12R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bits 28:30 - 30:28\\]
DMA Queue Number for event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res11 (& self) -> Res11R { Res11R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
DMA Queue Number for event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < DmaqnumnSpec > { E0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res18 (& mut self) -> Res18W < DmaqnumnSpec > { Res18W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
DMA Queue Number for event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < DmaqnumnSpec > { E1W :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res17 (& mut self) -> Res17W < DmaqnumnSpec > { Res17W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
DMA Queue Number for event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < DmaqnumnSpec > { E2W :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res16 (& mut self) -> Res16W < DmaqnumnSpec > { Res16W :: new (self , 11) } # [doc = "Bits 12:14 - 14:12\\]
DMA Queue Number for event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < DmaqnumnSpec > { E3W :: new (self , 12) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res15 (& mut self) -> Res15W < DmaqnumnSpec > { Res15W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
DMA Queue Number for event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < DmaqnumnSpec > { E4W :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res14 (& mut self) -> Res14W < DmaqnumnSpec > { Res14W :: new (self , 19) } # [doc = "Bits 20:22 - 22:20\\]
DMA Queue Number for event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < DmaqnumnSpec > { E5W :: new (self , 20) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res13 (& mut self) -> Res13W < DmaqnumnSpec > { Res13W :: new (self , 23) } # [doc = "Bits 24:26 - 26:24\\]
DMA Queue Number for event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < DmaqnumnSpec > { E6W :: new (self , 24) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res12 (& mut self) -> Res12W < DmaqnumnSpec > { Res12W :: new (self , 27) } # [doc = "Bits 28:30 - 30:28\\]
DMA Queue Number for event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < DmaqnumnSpec > { E7W :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res11 (& mut self) -> Res11W < DmaqnumnSpec > { Res11W :: new (self , 31) } } # [doc = "DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaqnumn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaqnumn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmaqnumnSpec ; impl crate :: RegisterSpec for DmaqnumnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dmaqnumn::R`](R) reader structure"]
impl crate :: Readable for DmaqnumnSpec { } # [doc = "`write(|w| ..)` method takes [`dmaqnumn::W`](W) writer structure"]
impl crate :: Writable for DmaqnumnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMAQNUMN to value 0"]
impl crate :: Resettable for DmaqnumnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QDMAQNUM (rw) register accessor: QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`qdmaqnum::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdmaqnum::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdmaqnum`]
module"]
# [doc (alias = "QDMAQNUM")]
pub type Qdmaqnum = crate :: Reg < qdmaqnum :: QdmaqnumSpec > ; # [doc = "QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."]
pub mod qdmaqnum { # [doc = "Register `QDMAQNUM` reader"]
pub type R = crate :: R < QdmaqnumSpec > ; # [doc = "Register `QDMAQNUM` writer"]
pub type W = crate :: W < QdmaqnumSpec > ; # [doc = "Field `E0` reader - 2:0\\]
QDMA Queue Number for event #0"]
pub type E0R = crate :: FieldReader ; # [doc = "Field `E0` writer - 2:0\\]
QDMA Queue Number for event #0"]
pub type E0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES26` reader - 3:3\\]
RESERVE FIELD"]
pub type Res26R = crate :: BitReader ; # [doc = "Field `RES26` writer - 3:3\\]
RESERVE FIELD"]
pub type Res26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 6:4\\]
QDMA Queue Number for event #1"]
pub type E1R = crate :: FieldReader ; # [doc = "Field `E1` writer - 6:4\\]
QDMA Queue Number for event #1"]
pub type E1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES25` reader - 7:7\\]
RESERVE FIELD"]
pub type Res25R = crate :: BitReader ; # [doc = "Field `RES25` writer - 7:7\\]
RESERVE FIELD"]
pub type Res25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 10:8\\]
QDMA Queue Number for event #2"]
pub type E2R = crate :: FieldReader ; # [doc = "Field `E2` writer - 10:8\\]
QDMA Queue Number for event #2"]
pub type E2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES24` reader - 11:11\\]
RESERVE FIELD"]
pub type Res24R = crate :: BitReader ; # [doc = "Field `RES24` writer - 11:11\\]
RESERVE FIELD"]
pub type Res24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 14:12\\]
QDMA Queue Number for event #3"]
pub type E3R = crate :: FieldReader ; # [doc = "Field `E3` writer - 14:12\\]
QDMA Queue Number for event #3"]
pub type E3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES23` reader - 15:15\\]
RESERVE FIELD"]
pub type Res23R = crate :: BitReader ; # [doc = "Field `RES23` writer - 15:15\\]
RESERVE FIELD"]
pub type Res23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 18:16\\]
QDMA Queue Number for event #4"]
pub type E4R = crate :: FieldReader ; # [doc = "Field `E4` writer - 18:16\\]
QDMA Queue Number for event #4"]
pub type E4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES22` reader - 19:19\\]
RESERVE FIELD"]
pub type Res22R = crate :: BitReader ; # [doc = "Field `RES22` writer - 19:19\\]
RESERVE FIELD"]
pub type Res22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 22:20\\]
QDMA Queue Number for event #5"]
pub type E5R = crate :: FieldReader ; # [doc = "Field `E5` writer - 22:20\\]
QDMA Queue Number for event #5"]
pub type E5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES21` reader - 23:23\\]
RESERVE FIELD"]
pub type Res21R = crate :: BitReader ; # [doc = "Field `RES21` writer - 23:23\\]
RESERVE FIELD"]
pub type Res21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 26:24\\]
QDMA Queue Number for event #6"]
pub type E6R = crate :: FieldReader ; # [doc = "Field `E6` writer - 26:24\\]
QDMA Queue Number for event #6"]
pub type E6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES20` reader - 27:27\\]
RESERVE FIELD"]
pub type Res20R = crate :: BitReader ; # [doc = "Field `RES20` writer - 27:27\\]
RESERVE FIELD"]
pub type Res20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 30:28\\]
QDMA Queue Number for event #7"]
pub type E7R = crate :: FieldReader ; # [doc = "Field `E7` writer - 30:28\\]
QDMA Queue Number for event #7"]
pub type E7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES19` reader - 31:31\\]
RESERVE FIELD"]
pub type Res19R = crate :: BitReader ; # [doc = "Field `RES19` writer - 31:31\\]
RESERVE FIELD"]
pub type Res19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
QDMA Queue Number for event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res26 (& self) -> Res26R { Res26R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
QDMA Queue Number for event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res25 (& self) -> Res25R { Res25R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
QDMA Queue Number for event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res24 (& self) -> Res24R { Res24R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - 14:12\\]
QDMA Queue Number for event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res23 (& self) -> Res23R { Res23R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
QDMA Queue Number for event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res22 (& self) -> Res22R { Res22R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:22 - 22:20\\]
QDMA Queue Number for event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 20) & 7) as u8) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res21 (& self) -> Res21R { Res21R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - 26:24\\]
QDMA Queue Number for event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res20 (& self) -> Res20R { Res20R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bits 28:30 - 30:28\\]
QDMA Queue Number for event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res19 (& self) -> Res19R { Res19R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
QDMA Queue Number for event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QdmaqnumSpec > { E0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res26 (& mut self) -> Res26W < QdmaqnumSpec > { Res26W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
QDMA Queue Number for event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QdmaqnumSpec > { E1W :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res25 (& mut self) -> Res25W < QdmaqnumSpec > { Res25W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
QDMA Queue Number for event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QdmaqnumSpec > { E2W :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res24 (& mut self) -> Res24W < QdmaqnumSpec > { Res24W :: new (self , 11) } # [doc = "Bits 12:14 - 14:12\\]
QDMA Queue Number for event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QdmaqnumSpec > { E3W :: new (self , 12) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res23 (& mut self) -> Res23W < QdmaqnumSpec > { Res23W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
QDMA Queue Number for event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QdmaqnumSpec > { E4W :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res22 (& mut self) -> Res22W < QdmaqnumSpec > { Res22W :: new (self , 19) } # [doc = "Bits 20:22 - 22:20\\]
QDMA Queue Number for event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QdmaqnumSpec > { E5W :: new (self , 20) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res21 (& mut self) -> Res21W < QdmaqnumSpec > { Res21W :: new (self , 23) } # [doc = "Bits 24:26 - 26:24\\]
QDMA Queue Number for event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QdmaqnumSpec > { E6W :: new (self , 24) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res20 (& mut self) -> Res20W < QdmaqnumSpec > { Res20W :: new (self , 27) } # [doc = "Bits 28:30 - 30:28\\]
QDMA Queue Number for event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QdmaqnumSpec > { E7W :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res19 (& mut self) -> Res19W < QdmaqnumSpec > { Res19W :: new (self , 31) } } # [doc = "QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`qdmaqnum::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdmaqnum::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QdmaqnumSpec ; impl crate :: RegisterSpec for QdmaqnumSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qdmaqnum::R`](R) reader structure"]
impl crate :: Readable for QdmaqnumSpec { } # [doc = "`write(|w| ..)` method takes [`qdmaqnum::W`](W) writer structure"]
impl crate :: Writable for QdmaqnumSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QDMAQNUM to value 0"]
impl crate :: Resettable for QdmaqnumSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QUETCMAP (rw) register accessor: Queue to TC Mapping\n\nYou can [`read`](crate::Reg::read) this register and get [`quetcmap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quetcmap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@quetcmap`]
module"]
# [doc (alias = "QUETCMAP")]
pub type Quetcmap = crate :: Reg < quetcmap :: QuetcmapSpec > ; # [doc = "Queue to TC Mapping"]
pub mod quetcmap { # [doc = "Register `QUETCMAP` reader"]
pub type R = crate :: R < QuetcmapSpec > ; # [doc = "Register `QUETCMAP` writer"]
pub type W = crate :: W < QuetcmapSpec > ; # [doc = "Field `TCNUMQ0` reader - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq0R = crate :: FieldReader ; # [doc = "Field `TCNUMQ0` writer - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES28` reader - 3:3\\]
RESERVE FIELD"]
pub type Res28R = crate :: BitReader ; # [doc = "Field `RES28` writer - 3:3\\]
RESERVE FIELD"]
pub type Res28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCNUMQ1` reader - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq1R = crate :: FieldReader ; # [doc = "Field `TCNUMQ1` writer - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES27` reader - 31:7\\]
RESERVE FIELD"]
pub type Res27R = crate :: FieldReader < u32 > ; # [doc = "Field `RES27` writer - 31:7\\]
RESERVE FIELD"]
pub type Res27W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
pub fn tcnumq0 (& self) -> Tcnumq0R { Tcnumq0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res28 (& self) -> Res28R { Res28R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
pub fn tcnumq1 (& self) -> Tcnumq1R { Tcnumq1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res27 (& self) -> Res27R { Res27R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
# [must_use]
pub fn tcnumq0 (& mut self) -> Tcnumq0W < QuetcmapSpec > { Tcnumq0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res28 (& mut self) -> Res28W < QuetcmapSpec > { Res28W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
# [must_use]
pub fn tcnumq1 (& mut self) -> Tcnumq1W < QuetcmapSpec > { Tcnumq1W :: new (self , 4) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res27 (& mut self) -> Res27W < QuetcmapSpec > { Res27W :: new (self , 7) } } # [doc = "Queue to TC Mapping\n\nYou can [`read`](crate::Reg::read) this register and get [`quetcmap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quetcmap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QuetcmapSpec ; impl crate :: RegisterSpec for QuetcmapSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`quetcmap::R`](R) reader structure"]
impl crate :: Readable for QuetcmapSpec { } # [doc = "`write(|w| ..)` method takes [`quetcmap::W`](W) writer structure"]
impl crate :: Writable for QuetcmapSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QUETCMAP to value 0"]
impl crate :: Resettable for QuetcmapSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QUEPRI (rw) register accessor: Queue Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`quepri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quepri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@quepri`]
module"]
# [doc (alias = "QUEPRI")]
pub type Quepri = crate :: Reg < quepri :: QuepriSpec > ; # [doc = "Queue Priority"]
pub mod quepri { # [doc = "Register `QUEPRI` reader"]
pub type R = crate :: R < QuepriSpec > ; # [doc = "Register `QUEPRI` writer"]
pub type W = crate :: W < QuepriSpec > ; # [doc = "Field `PRIQ0` reader - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq0R = crate :: FieldReader ; # [doc = "Field `PRIQ0` writer - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES30` reader - 3:3\\]
RESERVE FIELD"]
pub type Res30R = crate :: BitReader ; # [doc = "Field `RES30` writer - 3:3\\]
RESERVE FIELD"]
pub type Res30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PRIQ1` reader - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq1R = crate :: FieldReader ; # [doc = "Field `PRIQ1` writer - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES29` reader - 31:7\\]
RESERVE FIELD"]
pub type Res29R = crate :: FieldReader < u32 > ; # [doc = "Field `RES29` writer - 31:7\\]
RESERVE FIELD"]
pub type Res29W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
pub fn priq0 (& self) -> Priq0R { Priq0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res30 (& self) -> Res30R { Res30R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
pub fn priq1 (& self) -> Priq1R { Priq1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res29 (& self) -> Res29R { Res29R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
# [must_use]
pub fn priq0 (& mut self) -> Priq0W < QuepriSpec > { Priq0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res30 (& mut self) -> Res30W < QuepriSpec > { Res30W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
# [must_use]
pub fn priq1 (& mut self) -> Priq1W < QuepriSpec > { Priq1W :: new (self , 4) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res29 (& mut self) -> Res29W < QuepriSpec > { Res29W :: new (self , 7) } } # [doc = "Queue Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`quepri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quepri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QuepriSpec ; impl crate :: RegisterSpec for QuepriSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`quepri::R`](R) reader structure"]
impl crate :: Readable for QuepriSpec { } # [doc = "`write(|w| ..)` method takes [`quepri::W`](W) writer structure"]
impl crate :: Writable for QuepriSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QUEPRI to value 0"]
impl crate :: Resettable for QuepriSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMR (rw) register accessor: Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
module"]
# [doc (alias = "EMR")]
pub type Emr = crate :: Reg < emr :: EmrSpec > ; # [doc = "Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
pub mod emr { # [doc = "Register `EMR` reader"]
pub type R = crate :: R < EmrSpec > ; # [doc = "Register `EMR` writer"]
pub type W = crate :: W < EmrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event Missed #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event Missed #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event Missed #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event Missed #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event Missed #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event Missed #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event Missed #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event Missed #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event Missed #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event Missed #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event Missed #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event Missed #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event Missed #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event Missed #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event Missed #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event Missed #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event Missed #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event Missed #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event Missed #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event Missed #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event Missed #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event Missed #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event Missed #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event Missed #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event Missed #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event Missed #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event Missed #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event Missed #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event Missed #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event Missed #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event Missed #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event Missed #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event Missed #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event Missed #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event Missed #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event Missed #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event Missed #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event Missed #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event Missed #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event Missed #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event Missed #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event Missed #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event Missed #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event Missed #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event Missed #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event Missed #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event Missed #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event Missed #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EmrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EmrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EmrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EmrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EmrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EmrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EmrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EmrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EmrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EmrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EmrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EmrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EmrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EmrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EmrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EmrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EmrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EmrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EmrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EmrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EmrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EmrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EmrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EmrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EmrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EmrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EmrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EmrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EmrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EmrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EmrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EmrSpec > { E31W :: new (self , 31) } } # [doc = "Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmrSpec ; impl crate :: RegisterSpec for EmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emr::R`](R) reader structure"]
impl crate :: Readable for EmrSpec { } # [doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"]
impl crate :: Writable for EmrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMR to value 0"]
impl crate :: Resettable for EmrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMRH (rw) register accessor: Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emrh`]
module"]
# [doc (alias = "EMRH")]
pub type Emrh = crate :: Reg < emrh :: EmrhSpec > ; # [doc = "Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
pub mod emrh { # [doc = "Register `EMRH` reader"]
pub type R = crate :: R < EmrhSpec > ; # [doc = "Register `EMRH` writer"]
pub type W = crate :: W < EmrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event Missed #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event Missed #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event Missed #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event Missed #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event Missed #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event Missed #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event Missed #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event Missed #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event Missed #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event Missed #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event Missed #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event Missed #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event Missed #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event Missed #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event Missed #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event Missed #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event Missed #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event Missed #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event Missed #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event Missed #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event Missed #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event Missed #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event Missed #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event Missed #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event Missed #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event Missed #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event Missed #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event Missed #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event Missed #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event Missed #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event Missed #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event Missed #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event Missed #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event Missed #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event Missed #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event Missed #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event Missed #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event Missed #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event Missed #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event Missed #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event Missed #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event Missed #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event Missed #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event Missed #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event Missed #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event Missed #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event Missed #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event Missed #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event Missed #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event Missed #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event Missed #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event Missed #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event Missed #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event Missed #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event Missed #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event Missed #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event Missed #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event Missed #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event Missed #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event Missed #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event Missed #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event Missed #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event Missed #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event Missed #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EmrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EmrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EmrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EmrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EmrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EmrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EmrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EmrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EmrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EmrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EmrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EmrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EmrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EmrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EmrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EmrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EmrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EmrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EmrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EmrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EmrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EmrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EmrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EmrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EmrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EmrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EmrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EmrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EmrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EmrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EmrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EmrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmrhSpec ; impl crate :: RegisterSpec for EmrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emrh::R`](R) reader structure"]
impl crate :: Readable for EmrhSpec { } # [doc = "`write(|w| ..)` method takes [`emrh::W`](W) writer structure"]
impl crate :: Writable for EmrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMRH to value 0"]
impl crate :: Resettable for EmrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMCR (rw) register accessor: Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emcr`]
module"]
# [doc (alias = "EMCR")]
pub type Emcr = crate :: Reg < emcr :: EmcrSpec > ; # [doc = "Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
pub mod emcr { # [doc = "Register `EMCR` reader"]
pub type R = crate :: R < EmcrSpec > ; # [doc = "Register `EMCR` writer"]
pub type W = crate :: W < EmcrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed Clear #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed Clear #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed Clear #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed Clear #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed Clear #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed Clear #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed Clear #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed Clear #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed Clear #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed Clear #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed Clear #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed Clear #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed Clear #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed Clear #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed Clear #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed Clear #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event Missed Clear #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event Missed Clear #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event Missed Clear #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event Missed Clear #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event Missed Clear #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event Missed Clear #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event Missed Clear #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event Missed Clear #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event Missed Clear #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event Missed Clear #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event Missed Clear #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event Missed Clear #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event Missed Clear #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event Missed Clear #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event Missed Clear #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event Missed Clear #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event Missed Clear #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event Missed Clear #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event Missed Clear #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event Missed Clear #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event Missed Clear #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event Missed Clear #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event Missed Clear #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event Missed Clear #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event Missed Clear #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event Missed Clear #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event Missed Clear #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event Missed Clear #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event Missed Clear #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event Missed Clear #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event Missed Clear #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event Missed Clear #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event Missed Clear #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event Missed Clear #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event Missed Clear #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event Missed Clear #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event Missed Clear #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event Missed Clear #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event Missed Clear #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event Missed Clear #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event Missed Clear #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event Missed Clear #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event Missed Clear #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event Missed Clear #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event Missed Clear #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event Missed Clear #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event Missed Clear #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event Missed Clear #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EmcrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EmcrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EmcrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EmcrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EmcrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EmcrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EmcrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EmcrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EmcrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EmcrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EmcrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EmcrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EmcrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EmcrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EmcrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EmcrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EmcrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EmcrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EmcrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EmcrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EmcrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EmcrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EmcrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EmcrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EmcrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EmcrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EmcrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EmcrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EmcrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EmcrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EmcrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EmcrSpec > { E31W :: new (self , 31) } } # [doc = "Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmcrSpec ; impl crate :: RegisterSpec for EmcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emcr::R`](R) reader structure"]
impl crate :: Readable for EmcrSpec { } # [doc = "`write(|w| ..)` method takes [`emcr::W`](W) writer structure"]
impl crate :: Writable for EmcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMCR to value 0"]
impl crate :: Resettable for EmcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMCRH (rw) register accessor: Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emcrh`]
module"]
# [doc (alias = "EMCRH")]
pub type Emcrh = crate :: Reg < emcrh :: EmcrhSpec > ; # [doc = "Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
pub mod emcrh { # [doc = "Register `EMCRH` reader"]
pub type R = crate :: R < EmcrhSpec > ; # [doc = "Register `EMCRH` writer"]
pub type W = crate :: W < EmcrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event Missed Clear #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event Missed Clear #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event Missed Clear #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event Missed Clear #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event Missed Clear #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event Missed Clear #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event Missed Clear #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event Missed Clear #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event Missed Clear #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event Missed Clear #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event Missed Clear #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event Missed Clear #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event Missed Clear #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event Missed Clear #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event Missed Clear #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event Missed Clear #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event Missed Clear #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event Missed Clear #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event Missed Clear #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event Missed Clear #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event Missed Clear #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event Missed Clear #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event Missed Clear #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event Missed Clear #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event Missed Clear #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event Missed Clear #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event Missed Clear #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event Missed Clear #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event Missed Clear #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event Missed Clear #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event Missed Clear #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event Missed Clear #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event Missed Clear #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event Missed Clear #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event Missed Clear #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event Missed Clear #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event Missed Clear #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event Missed Clear #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event Missed Clear #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event Missed Clear #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event Missed Clear #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event Missed Clear #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event Missed Clear #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event Missed Clear #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event Missed Clear #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event Missed Clear #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event Missed Clear #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event Missed Clear #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event Missed Clear #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event Missed Clear #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event Missed Clear #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event Missed Clear #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event Missed Clear #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event Missed Clear #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event Missed Clear #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event Missed Clear #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event Missed Clear #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event Missed Clear #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event Missed Clear #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event Missed Clear #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event Missed Clear #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event Missed Clear #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event Missed Clear #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event Missed Clear #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EmcrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EmcrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EmcrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EmcrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EmcrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EmcrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EmcrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EmcrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EmcrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EmcrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EmcrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EmcrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EmcrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EmcrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EmcrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EmcrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EmcrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EmcrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EmcrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EmcrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EmcrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EmcrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EmcrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EmcrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EmcrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EmcrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EmcrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EmcrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EmcrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EmcrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EmcrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EmcrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmcrhSpec ; impl crate :: RegisterSpec for EmcrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emcrh::R`](R) reader structure"]
impl crate :: Readable for EmcrhSpec { } # [doc = "`write(|w| ..)` method takes [`emcrh::W`](W) writer structure"]
impl crate :: Writable for EmcrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMCRH to value 0"]
impl crate :: Resettable for EmcrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEMR (rw) register accessor: QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qemr`]
module"]
# [doc (alias = "QEMR")]
pub type Qemr = crate :: Reg < qemr :: QemrSpec > ; # [doc = "QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
pub mod qemr { # [doc = "Register `QEMR` reader"]
pub type R = crate :: R < QemrSpec > ; # [doc = "Register `QEMR` writer"]
pub type W = crate :: W < QemrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES31` reader - 31:8\\]
RESERVE FIELD"]
pub type Res31R = crate :: FieldReader < u32 > ; # [doc = "Field `RES31` writer - 31:8\\]
RESERVE FIELD"]
pub type Res31W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res31 (& self) -> Res31R { Res31R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QemrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QemrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QemrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QemrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QemrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QemrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QemrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QemrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res31 (& mut self) -> Res31W < QemrSpec > { Res31W :: new (self , 8) } } # [doc = "QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QemrSpec ; impl crate :: RegisterSpec for QemrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qemr::R`](R) reader structure"]
impl crate :: Readable for QemrSpec { } # [doc = "`write(|w| ..)` method takes [`qemr::W`](W) writer structure"]
impl crate :: Writable for QemrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEMR to value 0"]
impl crate :: Resettable for QemrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEMCR (rw) register accessor: QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qemcr`]
module"]
# [doc (alias = "QEMCR")]
pub type Qemcr = crate :: Reg < qemcr :: QemcrSpec > ; # [doc = "QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
pub mod qemcr { # [doc = "Register `QEMCR` reader"]
pub type R = crate :: R < QemcrSpec > ; # [doc = "Register `QEMCR` writer"]
pub type W = crate :: W < QemcrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed Clear #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed Clear #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed Clear #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed Clear #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed Clear #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed Clear #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed Clear #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed Clear #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed Clear #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed Clear #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed Clear #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed Clear #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed Clear #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed Clear #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed Clear #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed Clear #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES32` reader - 31:8\\]
RESERVE FIELD"]
pub type Res32R = crate :: FieldReader < u32 > ; # [doc = "Field `RES32` writer - 31:8\\]
RESERVE FIELD"]
pub type Res32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res32 (& self) -> Res32R { Res32R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QemcrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QemcrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QemcrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QemcrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QemcrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QemcrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QemcrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QemcrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res32 (& mut self) -> Res32W < QemcrSpec > { Res32W :: new (self , 8) } } # [doc = "QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QemcrSpec ; impl crate :: RegisterSpec for QemcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qemcr::R`](R) reader structure"]
impl crate :: Readable for QemcrSpec { } # [doc = "`write(|w| ..)` method takes [`qemcr::W`](W) writer structure"]
impl crate :: Writable for QemcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEMCR to value 0"]
impl crate :: Resettable for QemcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCERR (rw) register accessor: CC Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccerr`]
module"]
# [doc (alias = "CCERR")]
pub type Ccerr = crate :: Reg < ccerr :: CcerrSpec > ; # [doc = "CC Error Register"]
pub mod ccerr { # [doc = "Register `CCERR` reader"]
pub type R = crate :: R < CcerrSpec > ; # [doc = "Register `CCERR` writer"]
pub type W = crate :: W < CcerrSpec > ; # [doc = "Field `QTHRXCD0` reader - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd0R = crate :: BitReader ; # [doc = "Field `QTHRXCD0` writer - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD1` reader - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd1R = crate :: BitReader ; # [doc = "Field `QTHRXCD1` writer - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD2` reader - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd2R = crate :: BitReader ; # [doc = "Field `QTHRXCD2` writer - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD3` reader - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd3R = crate :: BitReader ; # [doc = "Field `QTHRXCD3` writer - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD4` reader - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd4R = crate :: BitReader ; # [doc = "Field `QTHRXCD4` writer - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD5` reader - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd5R = crate :: BitReader ; # [doc = "Field `QTHRXCD5` writer - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD6` reader - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd6R = crate :: BitReader ; # [doc = "Field `QTHRXCD6` writer - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD7` reader - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd7R = crate :: BitReader ; # [doc = "Field `QTHRXCD7` writer - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES34` reader - 15:8\\]
RESERVE FIELD"]
pub type Res34R = crate :: FieldReader ; # [doc = "Field `RES34` writer - 15:8\\]
RESERVE FIELD"]
pub type Res34W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TCERR` reader - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
pub type TcerrR = crate :: BitReader ; # [doc = "Field `TCERR` writer - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
pub type TcerrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES33` reader - 31:17\\]
RESERVE FIELD"]
pub type Res33R = crate :: FieldReader < u16 > ; # [doc = "Field `RES33` writer - 31:17\\]
RESERVE FIELD"]
pub type Res33W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd0 (& self) -> Qthrxcd0R { Qthrxcd0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd1 (& self) -> Qthrxcd1R { Qthrxcd1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd2 (& self) -> Qthrxcd2R { Qthrxcd2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd3 (& self) -> Qthrxcd3R { Qthrxcd3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd4 (& self) -> Qthrxcd4R { Qthrxcd4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd5 (& self) -> Qthrxcd5R { Qthrxcd5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd6 (& self) -> Qthrxcd6R { Qthrxcd6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd7 (& self) -> Qthrxcd7R { Qthrxcd7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res34 (& self) -> Res34R { Res34R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub fn tcerr (& self) -> TcerrR { TcerrR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res33 (& self) -> Res33R { Res33R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd0 (& mut self) -> Qthrxcd0W < CcerrSpec > { Qthrxcd0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd1 (& mut self) -> Qthrxcd1W < CcerrSpec > { Qthrxcd1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd2 (& mut self) -> Qthrxcd2W < CcerrSpec > { Qthrxcd2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd3 (& mut self) -> Qthrxcd3W < CcerrSpec > { Qthrxcd3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd4 (& mut self) -> Qthrxcd4W < CcerrSpec > { Qthrxcd4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd5 (& mut self) -> Qthrxcd5W < CcerrSpec > { Qthrxcd5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd6 (& mut self) -> Qthrxcd6W < CcerrSpec > { Qthrxcd6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd7 (& mut self) -> Qthrxcd7W < CcerrSpec > { Qthrxcd7W :: new (self , 7) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res34 (& mut self) -> Res34W < CcerrSpec > { Res34W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn tcerr (& mut self) -> TcerrW < CcerrSpec > { TcerrW :: new (self , 16) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res33 (& mut self) -> Res33W < CcerrSpec > { Res33W :: new (self , 17) } } # [doc = "CC Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcerrSpec ; impl crate :: RegisterSpec for CcerrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccerr::R`](R) reader structure"]
impl crate :: Readable for CcerrSpec { } # [doc = "`write(|w| ..)` method takes [`ccerr::W`](W) writer structure"]
impl crate :: Writable for CcerrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCERR to value 0"]
impl crate :: Resettable for CcerrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCERRCLR (rw) register accessor: CC Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerrclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerrclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccerrclr`]
module"]
# [doc (alias = "CCERRCLR")]
pub type Ccerrclr = crate :: Reg < ccerrclr :: CcerrclrSpec > ; # [doc = "CC Error Clear Register"]
pub mod ccerrclr { # [doc = "Register `CCERRCLR` reader"]
pub type R = crate :: R < CcerrclrSpec > ; # [doc = "Register `CCERRCLR` writer"]
pub type W = crate :: W < CcerrclrSpec > ; # [doc = "Field `QTHRXCD0` reader - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
pub type Qthrxcd0R = crate :: BitReader ; # [doc = "Field `QTHRXCD0` writer - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
pub type Qthrxcd0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD1` reader - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
pub type Qthrxcd1R = crate :: BitReader ; # [doc = "Field `QTHRXCD1` writer - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
pub type Qthrxcd1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD2` reader - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
pub type Qthrxcd2R = crate :: BitReader ; # [doc = "Field `QTHRXCD2` writer - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
pub type Qthrxcd2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD3` reader - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
pub type Qthrxcd3R = crate :: BitReader ; # [doc = "Field `QTHRXCD3` writer - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
pub type Qthrxcd3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD4` reader - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
pub type Qthrxcd4R = crate :: BitReader ; # [doc = "Field `QTHRXCD4` writer - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
pub type Qthrxcd4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD5` reader - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
pub type Qthrxcd5R = crate :: BitReader ; # [doc = "Field `QTHRXCD5` writer - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
pub type Qthrxcd5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD6` reader - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
pub type Qthrxcd6R = crate :: BitReader ; # [doc = "Field `QTHRXCD6` writer - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
pub type Qthrxcd6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD7` reader - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
pub type Qthrxcd7R = crate :: BitReader ; # [doc = "Field `QTHRXCD7` writer - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
pub type Qthrxcd7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES36` reader - 15:8\\]
RESERVE FIELD"]
pub type Res36R = crate :: FieldReader ; # [doc = "Field `RES36` writer - 15:8\\]
RESERVE FIELD"]
pub type Res36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TCERR` reader - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
pub type TcerrR = crate :: BitReader ; # [doc = "Field `TCERR` writer - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
pub type TcerrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES35` reader - 31:17\\]
RESERVE FIELD"]
pub type Res35R = crate :: FieldReader < u16 > ; # [doc = "Field `RES35` writer - 31:17\\]
RESERVE FIELD"]
pub type Res35W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd0 (& self) -> Qthrxcd0R { Qthrxcd0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd1 (& self) -> Qthrxcd1R { Qthrxcd1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd2 (& self) -> Qthrxcd2R { Qthrxcd2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd3 (& self) -> Qthrxcd3R { Qthrxcd3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd4 (& self) -> Qthrxcd4R { Qthrxcd4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd5 (& self) -> Qthrxcd5R { Qthrxcd5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd6 (& self) -> Qthrxcd6R { Qthrxcd6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd7 (& self) -> Qthrxcd7R { Qthrxcd7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res36 (& self) -> Res36R { Res36R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
# [inline (always)]
pub fn tcerr (& self) -> TcerrR { TcerrR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res35 (& self) -> Res35R { Res35R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd0 (& mut self) -> Qthrxcd0W < CcerrclrSpec > { Qthrxcd0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd1 (& mut self) -> Qthrxcd1W < CcerrclrSpec > { Qthrxcd1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd2 (& mut self) -> Qthrxcd2W < CcerrclrSpec > { Qthrxcd2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd3 (& mut self) -> Qthrxcd3W < CcerrclrSpec > { Qthrxcd3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd4 (& mut self) -> Qthrxcd4W < CcerrclrSpec > { Qthrxcd4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd5 (& mut self) -> Qthrxcd5W < CcerrclrSpec > { Qthrxcd5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd6 (& mut self) -> Qthrxcd6W < CcerrclrSpec > { Qthrxcd6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd7 (& mut self) -> Qthrxcd7W < CcerrclrSpec > { Qthrxcd7W :: new (self , 7) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res36 (& mut self) -> Res36W < CcerrclrSpec > { Res36W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn tcerr (& mut self) -> TcerrW < CcerrclrSpec > { TcerrW :: new (self , 16) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res35 (& mut self) -> Res35W < CcerrclrSpec > { Res35W :: new (self , 17) } } # [doc = "CC Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerrclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerrclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcerrclrSpec ; impl crate :: RegisterSpec for CcerrclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccerrclr::R`](R) reader structure"]
impl crate :: Readable for CcerrclrSpec { } # [doc = "`write(|w| ..)` method takes [`ccerrclr::W`](W) writer structure"]
impl crate :: Writable for CcerrclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCERRCLR to value 0"]
impl crate :: Resettable for CcerrclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EEVAL (rw) register accessor: Error Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eeval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eeval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eeval`]
module"]
# [doc (alias = "EEVAL")]
pub type Eeval = crate :: Reg < eeval :: EevalSpec > ; # [doc = "Error Eval Register"]
pub mod eeval { # [doc = "Register `EEVAL` reader"]
pub type R = crate :: R < EevalSpec > ; # [doc = "Register `EEVAL` writer"]
pub type W = crate :: W < EevalSpec > ; # [doc = "Field `EVAL` reader - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
pub type EvalR = crate :: BitReader ; # [doc = "Field `EVAL` writer - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
pub type EvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET` reader - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
pub type SetR = crate :: BitReader ; # [doc = "Field `SET` writer - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES37` reader - 31:2\\]
RESERVE FIELD"]
pub type Res37R = crate :: FieldReader < u32 > ; # [doc = "Field `RES37` writer - 31:2\\]
RESERVE FIELD"]
pub type Res37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
# [inline (always)]
pub fn eval (& self) -> EvalR { EvalR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res37 (& self) -> Res37R { Res37R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn eval (& mut self) -> EvalW < EevalSpec > { EvalW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < EevalSpec > { SetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res37 (& mut self) -> Res37W < EevalSpec > { Res37W :: new (self , 2) } } # [doc = "Error Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eeval::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eeval::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EevalSpec ; impl crate :: RegisterSpec for EevalSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eeval::R`](R) reader structure"]
impl crate :: Readable for EevalSpec { } # [doc = "`write(|w| ..)` method takes [`eeval::W`](W) writer structure"]
impl crate :: Writable for EevalSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EEVAL to value 0"]
impl crate :: Resettable for EevalSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DRAEM (rw) register accessor: DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@draem`]
module"]
# [doc (alias = "DRAEM")]
pub type Draem = crate :: Reg < draem :: DraemSpec > ; # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
pub mod draem { # [doc = "Register `DRAEM` reader"]
pub type R = crate :: R < DraemSpec > ; # [doc = "Register `DRAEM` writer"]
pub type W = crate :: W < DraemSpec > ; # [doc = "Field `E0` reader - 0:0\\]
DMA Region Access enable for Region M bit #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
DMA Region Access enable for Region M bit #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
DMA Region Access enable for Region M bit #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
DMA Region Access enable for Region M bit #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
DMA Region Access enable for Region M bit #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
DMA Region Access enable for Region M bit #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
DMA Region Access enable for Region M bit #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
DMA Region Access enable for Region M bit #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
DMA Region Access enable for Region M bit #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
DMA Region Access enable for Region M bit #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
DMA Region Access enable for Region M bit #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
DMA Region Access enable for Region M bit #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
DMA Region Access enable for Region M bit #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
DMA Region Access enable for Region M bit #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
DMA Region Access enable for Region M bit #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
DMA Region Access enable for Region M bit #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
DMA Region Access enable for Region M bit #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
DMA Region Access enable for Region M bit #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
DMA Region Access enable for Region M bit #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
DMA Region Access enable for Region M bit #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
DMA Region Access enable for Region M bit #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
DMA Region Access enable for Region M bit #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
DMA Region Access enable for Region M bit #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
DMA Region Access enable for Region M bit #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
DMA Region Access enable for Region M bit #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
DMA Region Access enable for Region M bit #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
DMA Region Access enable for Region M bit #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
DMA Region Access enable for Region M bit #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
DMA Region Access enable for Region M bit #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
DMA Region Access enable for Region M bit #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
DMA Region Access enable for Region M bit #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
DMA Region Access enable for Region M bit #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
DMA Region Access enable for Region M bit #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
DMA Region Access enable for Region M bit #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
DMA Region Access enable for Region M bit #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
DMA Region Access enable for Region M bit #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
DMA Region Access enable for Region M bit #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
DMA Region Access enable for Region M bit #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
DMA Region Access enable for Region M bit #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
DMA Region Access enable for Region M bit #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
DMA Region Access enable for Region M bit #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
DMA Region Access enable for Region M bit #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
DMA Region Access enable for Region M bit #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
DMA Region Access enable for Region M bit #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
DMA Region Access enable for Region M bit #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
DMA Region Access enable for Region M bit #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
DMA Region Access enable for Region M bit #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
DMA Region Access enable for Region M bit #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
DMA Region Access enable for Region M bit #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
DMA Region Access enable for Region M bit #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
DMA Region Access enable for Region M bit #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
DMA Region Access enable for Region M bit #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
DMA Region Access enable for Region M bit #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
DMA Region Access enable for Region M bit #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
DMA Region Access enable for Region M bit #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
DMA Region Access enable for Region M bit #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
DMA Region Access enable for Region M bit #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
DMA Region Access enable for Region M bit #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
DMA Region Access enable for Region M bit #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
DMA Region Access enable for Region M bit #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
DMA Region Access enable for Region M bit #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
DMA Region Access enable for Region M bit #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
DMA Region Access enable for Region M bit #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
DMA Region Access enable for Region M bit #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < DraemSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < DraemSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < DraemSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < DraemSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < DraemSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < DraemSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < DraemSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < DraemSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < DraemSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < DraemSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < DraemSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < DraemSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < DraemSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < DraemSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < DraemSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < DraemSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < DraemSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < DraemSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < DraemSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < DraemSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < DraemSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < DraemSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < DraemSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < DraemSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < DraemSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < DraemSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < DraemSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < DraemSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < DraemSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < DraemSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < DraemSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < DraemSpec > { E31W :: new (self , 31) } } # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DraemSpec ; impl crate :: RegisterSpec for DraemSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`draem::R`](R) reader structure"]
impl crate :: Readable for DraemSpec { } # [doc = "`write(|w| ..)` method takes [`draem::W`](W) writer structure"]
impl crate :: Writable for DraemSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DRAEM to value 0"]
impl crate :: Resettable for DraemSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DRAEHM (rw) register accessor: DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draehm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draehm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@draehm`]
module"]
# [doc (alias = "DRAEHM")]
pub type Draehm = crate :: Reg < draehm :: DraehmSpec > ; # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
pub mod draehm { # [doc = "Register `DRAEHM` reader"]
pub type R = crate :: R < DraehmSpec > ; # [doc = "Register `DRAEHM` writer"]
pub type W = crate :: W < DraehmSpec > ; # [doc = "Field `E32` reader - 0:0\\]
DMA Region Access enable for Region M bit #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
DMA Region Access enable for Region M bit #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
DMA Region Access enable for Region M bit #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
DMA Region Access enable for Region M bit #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
DMA Region Access enable for Region M bit #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
DMA Region Access enable for Region M bit #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
DMA Region Access enable for Region M bit #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
DMA Region Access enable for Region M bit #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
DMA Region Access enable for Region M bit #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
DMA Region Access enable for Region M bit #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
DMA Region Access enable for Region M bit #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
DMA Region Access enable for Region M bit #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
DMA Region Access enable for Region M bit #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
DMA Region Access enable for Region M bit #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
DMA Region Access enable for Region M bit #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
DMA Region Access enable for Region M bit #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
DMA Region Access enable for Region M bit #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
DMA Region Access enable for Region M bit #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
DMA Region Access enable for Region M bit #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
DMA Region Access enable for Region M bit #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
DMA Region Access enable for Region M bit #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
DMA Region Access enable for Region M bit #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
DMA Region Access enable for Region M bit #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
DMA Region Access enable for Region M bit #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
DMA Region Access enable for Region M bit #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
DMA Region Access enable for Region M bit #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
DMA Region Access enable for Region M bit #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
DMA Region Access enable for Region M bit #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
DMA Region Access enable for Region M bit #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
DMA Region Access enable for Region M bit #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
DMA Region Access enable for Region M bit #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
DMA Region Access enable for Region M bit #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
DMA Region Access enable for Region M bit #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
DMA Region Access enable for Region M bit #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
DMA Region Access enable for Region M bit #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
DMA Region Access enable for Region M bit #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
DMA Region Access enable for Region M bit #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
DMA Region Access enable for Region M bit #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
DMA Region Access enable for Region M bit #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
DMA Region Access enable for Region M bit #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
DMA Region Access enable for Region M bit #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
DMA Region Access enable for Region M bit #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
DMA Region Access enable for Region M bit #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
DMA Region Access enable for Region M bit #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
DMA Region Access enable for Region M bit #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
DMA Region Access enable for Region M bit #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
DMA Region Access enable for Region M bit #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
DMA Region Access enable for Region M bit #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
DMA Region Access enable for Region M bit #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
DMA Region Access enable for Region M bit #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
DMA Region Access enable for Region M bit #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
DMA Region Access enable for Region M bit #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
DMA Region Access enable for Region M bit #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
DMA Region Access enable for Region M bit #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
DMA Region Access enable for Region M bit #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
DMA Region Access enable for Region M bit #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
DMA Region Access enable for Region M bit #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
DMA Region Access enable for Region M bit #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
DMA Region Access enable for Region M bit #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
DMA Region Access enable for Region M bit #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
DMA Region Access enable for Region M bit #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
DMA Region Access enable for Region M bit #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
DMA Region Access enable for Region M bit #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
DMA Region Access enable for Region M bit #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < DraehmSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < DraehmSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < DraehmSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < DraehmSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < DraehmSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < DraehmSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < DraehmSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < DraehmSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < DraehmSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < DraehmSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < DraehmSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < DraehmSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < DraehmSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < DraehmSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < DraehmSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < DraehmSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < DraehmSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < DraehmSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < DraehmSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < DraehmSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < DraehmSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < DraehmSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < DraehmSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < DraehmSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < DraehmSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < DraehmSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < DraehmSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < DraehmSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < DraehmSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < DraehmSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < DraehmSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < DraehmSpec > { E63W :: new (self , 31) } } # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draehm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draehm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DraehmSpec ; impl crate :: RegisterSpec for DraehmSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`draehm::R`](R) reader structure"]
impl crate :: Readable for DraehmSpec { } # [doc = "`write(|w| ..)` method takes [`draehm::W`](W) writer structure"]
impl crate :: Writable for DraehmSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DRAEHM to value 0"]
impl crate :: Resettable for DraehmSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QRAEN (rw) register accessor: QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qraen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qraen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qraen`]
module"]
# [doc (alias = "QRAEN")]
pub type Qraen = crate :: Reg < qraen :: QraenSpec > ; # [doc = "QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt."]
pub mod qraen { # [doc = "Register `QRAEN` reader"]
pub type R = crate :: R < QraenSpec > ; # [doc = "Register `QRAEN` writer"]
pub type W = crate :: W < QraenSpec > ; # [doc = "Field `E0` reader - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES38` reader - 31:8\\]
RESERVE FIELD"]
pub type Res38R = crate :: FieldReader < u32 > ; # [doc = "Field `RES38` writer - 31:8\\]
RESERVE FIELD"]
pub type Res38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res38 (& self) -> Res38R { Res38R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QraenSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QraenSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QraenSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QraenSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QraenSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QraenSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QraenSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QraenSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res38 (& mut self) -> Res38W < QraenSpec > { Res38W :: new (self , 8) } } # [doc = "QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qraen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qraen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QraenSpec ; impl crate :: RegisterSpec for QraenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qraen::R`](R) reader structure"]
impl crate :: Readable for QraenSpec { } # [doc = "`write(|w| ..)` method takes [`qraen::W`](W) writer structure"]
impl crate :: Writable for QraenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QRAEN to value 0"]
impl crate :: Resettable for QraenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE0 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne0`]
module"]
# [doc (alias = "QNE0")]
pub type Qne0 = crate :: Reg < qne0 :: Qne0Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 0"]
pub mod qne0 { # [doc = "Register `QNE0` reader"]
pub type R = crate :: R < Qne0Spec > ; # [doc = "Register `QNE0` writer"]
pub type W = crate :: W < Qne0Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES39` reader - 31:8\\]
RESERVE FIELD"]
pub type Res39R = crate :: FieldReader < u32 > ; # [doc = "Field `RES39` writer - 31:8\\]
RESERVE FIELD"]
pub type Res39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res39 (& self) -> Res39R { Res39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne0Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne0Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res39 (& mut self) -> Res39W < Qne0Spec > { Res39W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne0Spec ; impl crate :: RegisterSpec for Qne0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne0::R`](R) reader structure"]
impl crate :: Readable for Qne0Spec { } # [doc = "`write(|w| ..)` method takes [`qne0::W`](W) writer structure"]
impl crate :: Writable for Qne0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE0 to value 0"]
impl crate :: Resettable for Qne0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE1 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 1\n\nYou can [`read`](crate::Reg::read) this register and get [`qne1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne1`]
module"]
# [doc (alias = "QNE1")]
pub type Qne1 = crate :: Reg < qne1 :: Qne1Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 1"]
pub mod qne1 { # [doc = "Register `QNE1` reader"]
pub type R = crate :: R < Qne1Spec > ; # [doc = "Register `QNE1` writer"]
pub type W = crate :: W < Qne1Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES40` reader - 31:8\\]
RESERVE FIELD"]
pub type Res40R = crate :: FieldReader < u32 > ; # [doc = "Field `RES40` writer - 31:8\\]
RESERVE FIELD"]
pub type Res40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res40 (& self) -> Res40R { Res40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne1Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne1Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res40 (& mut self) -> Res40W < Qne1Spec > { Res40W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 1\n\nYou can [`read`](crate::Reg::read) this register and get [`qne1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne1Spec ; impl crate :: RegisterSpec for Qne1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne1::R`](R) reader structure"]
impl crate :: Readable for Qne1Spec { } # [doc = "`write(|w| ..)` method takes [`qne1::W`](W) writer structure"]
impl crate :: Writable for Qne1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE1 to value 0"]
impl crate :: Resettable for Qne1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE2 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 2\n\nYou can [`read`](crate::Reg::read) this register and get [`qne2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne2`]
module"]
# [doc (alias = "QNE2")]
pub type Qne2 = crate :: Reg < qne2 :: Qne2Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 2"]
pub mod qne2 { # [doc = "Register `QNE2` reader"]
pub type R = crate :: R < Qne2Spec > ; # [doc = "Register `QNE2` writer"]
pub type W = crate :: W < Qne2Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES41` reader - 31:8\\]
RESERVE FIELD"]
pub type Res41R = crate :: FieldReader < u32 > ; # [doc = "Field `RES41` writer - 31:8\\]
RESERVE FIELD"]
pub type Res41W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res41 (& self) -> Res41R { Res41R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne2Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne2Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res41 (& mut self) -> Res41W < Qne2Spec > { Res41W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 2\n\nYou can [`read`](crate::Reg::read) this register and get [`qne2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne2Spec ; impl crate :: RegisterSpec for Qne2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne2::R`](R) reader structure"]
impl crate :: Readable for Qne2Spec { } # [doc = "`write(|w| ..)` method takes [`qne2::W`](W) writer structure"]
impl crate :: Writable for Qne2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE2 to value 0"]
impl crate :: Resettable for Qne2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE3 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 3\n\nYou can [`read`](crate::Reg::read) this register and get [`qne3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne3`]
module"]
# [doc (alias = "QNE3")]
pub type Qne3 = crate :: Reg < qne3 :: Qne3Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 3"]
pub mod qne3 { # [doc = "Register `QNE3` reader"]
pub type R = crate :: R < Qne3Spec > ; # [doc = "Register `QNE3` writer"]
pub type W = crate :: W < Qne3Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES42` reader - 31:8\\]
RESERVE FIELD"]
pub type Res42R = crate :: FieldReader < u32 > ; # [doc = "Field `RES42` writer - 31:8\\]
RESERVE FIELD"]
pub type Res42W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res42 (& self) -> Res42R { Res42R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne3Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne3Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res42 (& mut self) -> Res42W < Qne3Spec > { Res42W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 3\n\nYou can [`read`](crate::Reg::read) this register and get [`qne3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne3Spec ; impl crate :: RegisterSpec for Qne3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne3::R`](R) reader structure"]
impl crate :: Readable for Qne3Spec { } # [doc = "`write(|w| ..)` method takes [`qne3::W`](W) writer structure"]
impl crate :: Writable for Qne3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE3 to value 0"]
impl crate :: Resettable for Qne3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE4 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 4\n\nYou can [`read`](crate::Reg::read) this register and get [`qne4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne4`]
module"]
# [doc (alias = "QNE4")]
pub type Qne4 = crate :: Reg < qne4 :: Qne4Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 4"]
pub mod qne4 { # [doc = "Register `QNE4` reader"]
pub type R = crate :: R < Qne4Spec > ; # [doc = "Register `QNE4` writer"]
pub type W = crate :: W < Qne4Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES43` reader - 31:8\\]
RESERVE FIELD"]
pub type Res43R = crate :: FieldReader < u32 > ; # [doc = "Field `RES43` writer - 31:8\\]
RESERVE FIELD"]
pub type Res43W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res43 (& self) -> Res43R { Res43R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne4Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne4Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res43 (& mut self) -> Res43W < Qne4Spec > { Res43W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 4\n\nYou can [`read`](crate::Reg::read) this register and get [`qne4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne4Spec ; impl crate :: RegisterSpec for Qne4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne4::R`](R) reader structure"]
impl crate :: Readable for Qne4Spec { } # [doc = "`write(|w| ..)` method takes [`qne4::W`](W) writer structure"]
impl crate :: Writable for Qne4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE4 to value 0"]
impl crate :: Resettable for Qne4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE5 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 5\n\nYou can [`read`](crate::Reg::read) this register and get [`qne5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne5`]
module"]
# [doc (alias = "QNE5")]
pub type Qne5 = crate :: Reg < qne5 :: Qne5Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 5"]
pub mod qne5 { # [doc = "Register `QNE5` reader"]
pub type R = crate :: R < Qne5Spec > ; # [doc = "Register `QNE5` writer"]
pub type W = crate :: W < Qne5Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES44` reader - 31:8\\]
RESERVE FIELD"]
pub type Res44R = crate :: FieldReader < u32 > ; # [doc = "Field `RES44` writer - 31:8\\]
RESERVE FIELD"]
pub type Res44W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res44 (& self) -> Res44R { Res44R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne5Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne5Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res44 (& mut self) -> Res44W < Qne5Spec > { Res44W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 5\n\nYou can [`read`](crate::Reg::read) this register and get [`qne5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne5Spec ; impl crate :: RegisterSpec for Qne5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne5::R`](R) reader structure"]
impl crate :: Readable for Qne5Spec { } # [doc = "`write(|w| ..)` method takes [`qne5::W`](W) writer structure"]
impl crate :: Writable for Qne5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE5 to value 0"]
impl crate :: Resettable for Qne5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE6 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 6\n\nYou can [`read`](crate::Reg::read) this register and get [`qne6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne6`]
module"]
# [doc (alias = "QNE6")]
pub type Qne6 = crate :: Reg < qne6 :: Qne6Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 6"]
pub mod qne6 { # [doc = "Register `QNE6` reader"]
pub type R = crate :: R < Qne6Spec > ; # [doc = "Register `QNE6` writer"]
pub type W = crate :: W < Qne6Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES45` reader - 31:8\\]
RESERVE FIELD"]
pub type Res45R = crate :: FieldReader < u32 > ; # [doc = "Field `RES45` writer - 31:8\\]
RESERVE FIELD"]
pub type Res45W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res45 (& self) -> Res45R { Res45R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne6Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne6Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res45 (& mut self) -> Res45W < Qne6Spec > { Res45W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 6\n\nYou can [`read`](crate::Reg::read) this register and get [`qne6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne6Spec ; impl crate :: RegisterSpec for Qne6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne6::R`](R) reader structure"]
impl crate :: Readable for Qne6Spec { } # [doc = "`write(|w| ..)` method takes [`qne6::W`](W) writer structure"]
impl crate :: Writable for Qne6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE6 to value 0"]
impl crate :: Resettable for Qne6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE7 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 7\n\nYou can [`read`](crate::Reg::read) this register and get [`qne7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne7`]
module"]
# [doc (alias = "QNE7")]
pub type Qne7 = crate :: Reg < qne7 :: Qne7Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 7"]
pub mod qne7 { # [doc = "Register `QNE7` reader"]
pub type R = crate :: R < Qne7Spec > ; # [doc = "Register `QNE7` writer"]
pub type W = crate :: W < Qne7Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES46` reader - 31:8\\]
RESERVE FIELD"]
pub type Res46R = crate :: FieldReader < u32 > ; # [doc = "Field `RES46` writer - 31:8\\]
RESERVE FIELD"]
pub type Res46W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res46 (& self) -> Res46R { Res46R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne7Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne7Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res46 (& mut self) -> Res46W < Qne7Spec > { Res46W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 7\n\nYou can [`read`](crate::Reg::read) this register and get [`qne7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne7Spec ; impl crate :: RegisterSpec for Qne7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne7::R`](R) reader structure"]
impl crate :: Readable for Qne7Spec { } # [doc = "`write(|w| ..)` method takes [`qne7::W`](W) writer structure"]
impl crate :: Writable for Qne7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE7 to value 0"]
impl crate :: Resettable for Qne7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE8 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 8\n\nYou can [`read`](crate::Reg::read) this register and get [`qne8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne8`]
module"]
# [doc (alias = "QNE8")]
pub type Qne8 = crate :: Reg < qne8 :: Qne8Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 8"]
pub mod qne8 { # [doc = "Register `QNE8` reader"]
pub type R = crate :: R < Qne8Spec > ; # [doc = "Register `QNE8` writer"]
pub type W = crate :: W < Qne8Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES47` reader - 31:8\\]
RESERVE FIELD"]
pub type Res47R = crate :: FieldReader < u32 > ; # [doc = "Field `RES47` writer - 31:8\\]
RESERVE FIELD"]
pub type Res47W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res47 (& self) -> Res47R { Res47R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne8Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne8Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res47 (& mut self) -> Res47W < Qne8Spec > { Res47W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 8\n\nYou can [`read`](crate::Reg::read) this register and get [`qne8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne8Spec ; impl crate :: RegisterSpec for Qne8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne8::R`](R) reader structure"]
impl crate :: Readable for Qne8Spec { } # [doc = "`write(|w| ..)` method takes [`qne8::W`](W) writer structure"]
impl crate :: Writable for Qne8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE8 to value 0"]
impl crate :: Resettable for Qne8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE9 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 9\n\nYou can [`read`](crate::Reg::read) this register and get [`qne9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne9`]
module"]
# [doc (alias = "QNE9")]
pub type Qne9 = crate :: Reg < qne9 :: Qne9Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 9"]
pub mod qne9 { # [doc = "Register `QNE9` reader"]
pub type R = crate :: R < Qne9Spec > ; # [doc = "Register `QNE9` writer"]
pub type W = crate :: W < Qne9Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES48` reader - 31:8\\]
RESERVE FIELD"]
pub type Res48R = crate :: FieldReader < u32 > ; # [doc = "Field `RES48` writer - 31:8\\]
RESERVE FIELD"]
pub type Res48W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res48 (& self) -> Res48R { Res48R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne9Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne9Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res48 (& mut self) -> Res48W < Qne9Spec > { Res48W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 9\n\nYou can [`read`](crate::Reg::read) this register and get [`qne9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne9Spec ; impl crate :: RegisterSpec for Qne9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne9::R`](R) reader structure"]
impl crate :: Readable for Qne9Spec { } # [doc = "`write(|w| ..)` method takes [`qne9::W`](W) writer structure"]
impl crate :: Writable for Qne9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE9 to value 0"]
impl crate :: Resettable for Qne9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE10 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne10`]
module"]
# [doc (alias = "QNE10")]
pub type Qne10 = crate :: Reg < qne10 :: Qne10Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 0"]
pub mod qne10 { # [doc = "Register `QNE10` reader"]
pub type R = crate :: R < Qne10Spec > ; # [doc = "Register `QNE10` writer"]
pub type W = crate :: W < Qne10Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES49` reader - 31:8\\]
RESERVE FIELD"]
pub type Res49R = crate :: FieldReader < u32 > ; # [doc = "Field `RES49` writer - 31:8\\]
RESERVE FIELD"]
pub type Res49W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res49 (& self) -> Res49R { Res49R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne10Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne10Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res49 (& mut self) -> Res49W < Qne10Spec > { Res49W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne10Spec ; impl crate :: RegisterSpec for Qne10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne10::R`](R) reader structure"]
impl crate :: Readable for Qne10Spec { } # [doc = "`write(|w| ..)` method takes [`qne10::W`](W) writer structure"]
impl crate :: Writable for Qne10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE10 to value 0"]
impl crate :: Resettable for Qne10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE11 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 11\n\nYou can [`read`](crate::Reg::read) this register and get [`qne11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne11`]
module"]
# [doc (alias = "QNE11")]
pub type Qne11 = crate :: Reg < qne11 :: Qne11Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 11"]
pub mod qne11 { # [doc = "Register `QNE11` reader"]
pub type R = crate :: R < Qne11Spec > ; # [doc = "Register `QNE11` writer"]
pub type W = crate :: W < Qne11Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES50` reader - 31:8\\]
RESERVE FIELD"]
pub type Res50R = crate :: FieldReader < u32 > ; # [doc = "Field `RES50` writer - 31:8\\]
RESERVE FIELD"]
pub type Res50W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res50 (& self) -> Res50R { Res50R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne11Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne11Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res50 (& mut self) -> Res50W < Qne11Spec > { Res50W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 11\n\nYou can [`read`](crate::Reg::read) this register and get [`qne11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne11Spec ; impl crate :: RegisterSpec for Qne11Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne11::R`](R) reader structure"]
impl crate :: Readable for Qne11Spec { } # [doc = "`write(|w| ..)` method takes [`qne11::W`](W) writer structure"]
impl crate :: Writable for Qne11Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE11 to value 0"]
impl crate :: Resettable for Qne11Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE12 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 12\n\nYou can [`read`](crate::Reg::read) this register and get [`qne12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne12`]
module"]
# [doc (alias = "QNE12")]
pub type Qne12 = crate :: Reg < qne12 :: Qne12Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 12"]
pub mod qne12 { # [doc = "Register `QNE12` reader"]
pub type R = crate :: R < Qne12Spec > ; # [doc = "Register `QNE12` writer"]
pub type W = crate :: W < Qne12Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES51` reader - 31:8\\]
RESERVE FIELD"]
pub type Res51R = crate :: FieldReader < u32 > ; # [doc = "Field `RES51` writer - 31:8\\]
RESERVE FIELD"]
pub type Res51W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res51 (& self) -> Res51R { Res51R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne12Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne12Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res51 (& mut self) -> Res51W < Qne12Spec > { Res51W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 12\n\nYou can [`read`](crate::Reg::read) this register and get [`qne12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne12Spec ; impl crate :: RegisterSpec for Qne12Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne12::R`](R) reader structure"]
impl crate :: Readable for Qne12Spec { } # [doc = "`write(|w| ..)` method takes [`qne12::W`](W) writer structure"]
impl crate :: Writable for Qne12Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE12 to value 0"]
impl crate :: Resettable for Qne12Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE13 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 13\n\nYou can [`read`](crate::Reg::read) this register and get [`qne13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne13`]
module"]
# [doc (alias = "QNE13")]
pub type Qne13 = crate :: Reg < qne13 :: Qne13Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 13"]
pub mod qne13 { # [doc = "Register `QNE13` reader"]
pub type R = crate :: R < Qne13Spec > ; # [doc = "Register `QNE13` writer"]
pub type W = crate :: W < Qne13Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES52` reader - 31:8\\]
RESERVE FIELD"]
pub type Res52R = crate :: FieldReader < u32 > ; # [doc = "Field `RES52` writer - 31:8\\]
RESERVE FIELD"]
pub type Res52W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res52 (& self) -> Res52R { Res52R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne13Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne13Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res52 (& mut self) -> Res52W < Qne13Spec > { Res52W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 13\n\nYou can [`read`](crate::Reg::read) this register and get [`qne13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne13Spec ; impl crate :: RegisterSpec for Qne13Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne13::R`](R) reader structure"]
impl crate :: Readable for Qne13Spec { } # [doc = "`write(|w| ..)` method takes [`qne13::W`](W) writer structure"]
impl crate :: Writable for Qne13Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE13 to value 0"]
impl crate :: Resettable for Qne13Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE14 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 14\n\nYou can [`read`](crate::Reg::read) this register and get [`qne14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne14`]
module"]
# [doc (alias = "QNE14")]
pub type Qne14 = crate :: Reg < qne14 :: Qne14Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 14"]
pub mod qne14 { # [doc = "Register `QNE14` reader"]
pub type R = crate :: R < Qne14Spec > ; # [doc = "Register `QNE14` writer"]
pub type W = crate :: W < Qne14Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES53` reader - 31:8\\]
RESERVE FIELD"]
pub type Res53R = crate :: FieldReader < u32 > ; # [doc = "Field `RES53` writer - 31:8\\]
RESERVE FIELD"]
pub type Res53W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res53 (& self) -> Res53R { Res53R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne14Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne14Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res53 (& mut self) -> Res53W < Qne14Spec > { Res53W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 14\n\nYou can [`read`](crate::Reg::read) this register and get [`qne14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne14Spec ; impl crate :: RegisterSpec for Qne14Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne14::R`](R) reader structure"]
impl crate :: Readable for Qne14Spec { } # [doc = "`write(|w| ..)` method takes [`qne14::W`](W) writer structure"]
impl crate :: Writable for Qne14Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE14 to value 0"]
impl crate :: Resettable for Qne14Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE15 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 15\n\nYou can [`read`](crate::Reg::read) this register and get [`qne15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne15`]
module"]
# [doc (alias = "QNE15")]
pub type Qne15 = crate :: Reg < qne15 :: Qne15Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 15"]
pub mod qne15 { # [doc = "Register `QNE15` reader"]
pub type R = crate :: R < Qne15Spec > ; # [doc = "Register `QNE15` writer"]
pub type W = crate :: W < Qne15Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES54` reader - 31:8\\]
RESERVE FIELD"]
pub type Res54R = crate :: FieldReader < u32 > ; # [doc = "Field `RES54` writer - 31:8\\]
RESERVE FIELD"]
pub type Res54W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res54 (& self) -> Res54R { Res54R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne15Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne15Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res54 (& mut self) -> Res54W < Qne15Spec > { Res54W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 15\n\nYou can [`read`](crate::Reg::read) this register and get [`qne15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne15Spec ; impl crate :: RegisterSpec for Qne15Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne15::R`](R) reader structure"]
impl crate :: Readable for Qne15Spec { } # [doc = "`write(|w| ..)` method takes [`qne15::W`](W) writer structure"]
impl crate :: Writable for Qne15Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE15 to value 0"]
impl crate :: Resettable for Qne15Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSTATN (rw) register accessor: QSTATn Register Set\n\nYou can [`read`](crate::Reg::read) this register and get [`qstatn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qstatn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qstatn`]
module"]
# [doc (alias = "QSTATN")]
pub type Qstatn = crate :: Reg < qstatn :: QstatnSpec > ; # [doc = "QSTATn Register Set"]
pub mod qstatn { # [doc = "Register `QSTATN` reader"]
pub type R = crate :: R < QstatnSpec > ; # [doc = "Register `QSTATN` writer"]
pub type W = crate :: W < QstatnSpec > ; # [doc = "Field `STRTPTR` reader - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
pub type StrtptrR = crate :: FieldReader ; # [doc = "Field `STRTPTR` writer - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
pub type StrtptrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RES58` reader - 7:4\\]
RESERVE FIELD"]
pub type Res58R = crate :: FieldReader ; # [doc = "Field `RES58` writer - 7:4\\]
RESERVE FIELD"]
pub type Res58W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NUMVAL` reader - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type NumvalR = crate :: FieldReader ; # [doc = "Field `NUMVAL` writer - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type NumvalW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES57` reader - 15:13\\]
RESERVE FIELD"]
pub type Res57R = crate :: FieldReader ; # [doc = "Field `RES57` writer - 15:13\\]
RESERVE FIELD"]
pub type Res57W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `WM` reader - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type WmR = crate :: FieldReader ; # [doc = "Field `WM` writer - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type WmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES56` reader - 23:21\\]
RESERVE FIELD"]
pub type Res56R = crate :: FieldReader ; # [doc = "Field `RES56` writer - 23:21\\]
RESERVE FIELD"]
pub type Res56W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `THRXCD` reader - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
pub type ThrxcdR = crate :: BitReader ; # [doc = "Field `THRXCD` writer - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
pub type ThrxcdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES55` reader - 31:25\\]
RESERVE FIELD"]
pub type Res55R = crate :: FieldReader ; # [doc = "Field `RES55` writer - 31:25\\]
RESERVE FIELD"]
pub type Res55W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
# [inline (always)]
pub fn strtptr (& self) -> StrtptrR { StrtptrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res58 (& self) -> Res58R { Res58R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
pub fn numval (& self) -> NumvalR { NumvalR :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res57 (& self) -> Res57R { Res57R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
pub fn wm (& self) -> WmR { WmR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:23 - 23:21\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res56 (& self) -> Res56R { Res56R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
# [inline (always)]
pub fn thrxcd (& self) -> ThrxcdR { ThrxcdR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res55 (& self) -> Res55R { Res55R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
# [inline (always)]
# [must_use]
pub fn strtptr (& mut self) -> StrtptrW < QstatnSpec > { StrtptrW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res58 (& mut self) -> Res58W < QstatnSpec > { Res58W :: new (self , 4) } # [doc = "Bits 8:12 - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
# [must_use]
pub fn numval (& mut self) -> NumvalW < QstatnSpec > { NumvalW :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res57 (& mut self) -> Res57W < QstatnSpec > { Res57W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
# [must_use]
pub fn wm (& mut self) -> WmW < QstatnSpec > { WmW :: new (self , 16) } # [doc = "Bits 21:23 - 23:21\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res56 (& mut self) -> Res56W < QstatnSpec > { Res56W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
# [inline (always)]
# [must_use]
pub fn thrxcd (& mut self) -> ThrxcdW < QstatnSpec > { ThrxcdW :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res55 (& mut self) -> Res55W < QstatnSpec > { Res55W :: new (self , 25) } } # [doc = "QSTATn Register Set\n\nYou can [`read`](crate::Reg::read) this register and get [`qstatn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qstatn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QstatnSpec ; impl crate :: RegisterSpec for QstatnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qstatn::R`](R) reader structure"]
impl crate :: Readable for QstatnSpec { } # [doc = "`write(|w| ..)` method takes [`qstatn::W`](W) writer structure"]
impl crate :: Writable for QstatnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSTATN to value 0"]
impl crate :: Resettable for QstatnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QWMTHRA (rw) register accessor: Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors.\n\nYou can [`read`](crate::Reg::read) this register and get [`qwmthra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qwmthra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qwmthra`]
module"]
# [doc (alias = "QWMTHRA")]
pub type Qwmthra = crate :: Reg < qwmthra :: QwmthraSpec > ; # [doc = "Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors."]
pub mod qwmthra { # [doc = "Register `QWMTHRA` reader"]
pub type R = crate :: R < QwmthraSpec > ; # [doc = "Register `QWMTHRA` writer"]
pub type W = crate :: W < QwmthraSpec > ; # [doc = "Field `Q0` reader - 4:0\\]
Queue Threshold for Q0 value"]
pub type Q0R = crate :: FieldReader ; # [doc = "Field `Q0` writer - 4:0\\]
Queue Threshold for Q0 value"]
pub type Q0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES60` reader - 7:5\\]
RESERVE FIELD"]
pub type Res60R = crate :: FieldReader ; # [doc = "Field `RES60` writer - 7:5\\]
RESERVE FIELD"]
pub type Res60W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `Q1` reader - 12:8\\]
Queue Threshold for Q1 value"]
pub type Q1R = crate :: FieldReader ; # [doc = "Field `Q1` writer - 12:8\\]
Queue Threshold for Q1 value"]
pub type Q1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES59` reader - 31:13\\]
RESERVE FIELD"]
pub type Res59R = crate :: FieldReader < u32 > ; # [doc = "Field `RES59` writer - 31:13\\]
RESERVE FIELD"]
pub type Res59W < 'a , REG > = crate :: FieldWriter < 'a , REG , 19 , u32 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Queue Threshold for Q0 value"]
# [inline (always)]
pub fn q0 (& self) -> Q0R { Q0R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res60 (& self) -> Res60R { Res60R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Queue Threshold for Q1 value"]
# [inline (always)]
pub fn q1 (& self) -> Q1R { Q1R :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:31 - 31:13\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res59 (& self) -> Res59R { Res59R :: new ((self . bits >> 13) & 0x0007_ffff) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Queue Threshold for Q0 value"]
# [inline (always)]
# [must_use]
pub fn q0 (& mut self) -> Q0W < QwmthraSpec > { Q0W :: new (self , 0) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res60 (& mut self) -> Res60W < QwmthraSpec > { Res60W :: new (self , 5) } # [doc = "Bits 8:12 - 12:8\\]
Queue Threshold for Q1 value"]
# [inline (always)]
# [must_use]
pub fn q1 (& mut self) -> Q1W < QwmthraSpec > { Q1W :: new (self , 8) } # [doc = "Bits 13:31 - 31:13\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res59 (& mut self) -> Res59W < QwmthraSpec > { Res59W :: new (self , 13) } } # [doc = "Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors.\n\nYou can [`read`](crate::Reg::read) this register and get [`qwmthra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qwmthra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QwmthraSpec ; impl crate :: RegisterSpec for QwmthraSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qwmthra::R`](R) reader structure"]
impl crate :: Readable for QwmthraSpec { } # [doc = "`write(|w| ..)` method takes [`qwmthra::W`](W) writer structure"]
impl crate :: Writable for QwmthraSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QWMTHRA to value 0"]
impl crate :: Resettable for QwmthraSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCSTAT (rw) register accessor: CC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccstat`]
module"]
# [doc (alias = "CCSTAT")]
pub type Ccstat = crate :: Reg < ccstat :: CcstatSpec > ; # [doc = "CC Status Register"]
pub mod ccstat { # [doc = "Register `CCSTAT` reader"]
pub type R = crate :: R < CcstatSpec > ; # [doc = "Register `CCSTAT` writer"]
pub type W = crate :: W < CcstatSpec > ; # [doc = "Field `EVTACTV` reader - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type EvtactvR = crate :: BitReader ; # [doc = "Field `EVTACTV` writer - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type EvtactvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QEVTACTV` reader - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type QevtactvR = crate :: BitReader ; # [doc = "Field `QEVTACTV` writer - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type QevtactvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACTV` reader - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
pub type TractvR = crate :: BitReader ; # [doc = "Field `TRACTV` writer - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
pub type TractvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES64` reader - 3:3\\]
RESERVE FIELD"]
pub type Res64R = crate :: BitReader ; # [doc = "Field `RES64` writer - 3:3\\]
RESERVE FIELD"]
pub type Res64W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ACTV` reader - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
pub type ActvR = crate :: BitReader ; # [doc = "Field `ACTV` writer - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
pub type ActvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES63` reader - 7:5\\]
RESERVE FIELD"]
pub type Res63R = crate :: FieldReader ; # [doc = "Field `RES63` writer - 7:5\\]
RESERVE FIELD"]
pub type Res63W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMPACTV` reader - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
pub type CompactvR = crate :: FieldReader ; # [doc = "Field `COMPACTV` writer - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
pub type CompactvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RES62` reader - 15:14\\]
RESERVE FIELD"]
pub type Res62R = crate :: FieldReader ; # [doc = "Field `RES62` writer - 15:14\\]
RESERVE FIELD"]
pub type Res62W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `QUEACTV0` reader - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
pub type Queactv0R = crate :: BitReader ; # [doc = "Field `QUEACTV0` writer - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
pub type Queactv0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV1` reader - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
pub type Queactv1R = crate :: BitReader ; # [doc = "Field `QUEACTV1` writer - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
pub type Queactv1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV2` reader - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
pub type Queactv2R = crate :: BitReader ; # [doc = "Field `QUEACTV2` writer - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
pub type Queactv2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV3` reader - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
pub type Queactv3R = crate :: BitReader ; # [doc = "Field `QUEACTV3` writer - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
pub type Queactv3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV4` reader - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
pub type Queactv4R = crate :: BitReader ; # [doc = "Field `QUEACTV4` writer - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
pub type Queactv4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV5` reader - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
pub type Queactv5R = crate :: BitReader ; # [doc = "Field `QUEACTV5` writer - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
pub type Queactv5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV6` reader - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
pub type Queactv6R = crate :: BitReader ; # [doc = "Field `QUEACTV6` writer - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
pub type Queactv6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV7` reader - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
pub type Queactv7R = crate :: BitReader ; # [doc = "Field `QUEACTV7` writer - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
pub type Queactv7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES61` reader - 31:24\\]
RESERVE FIELD"]
pub type Res61R = crate :: FieldReader ; # [doc = "Field `RES61` writer - 31:24\\]
RESERVE FIELD"]
pub type Res61W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bit 0 - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
pub fn evtactv (& self) -> EvtactvR { EvtactvR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
pub fn qevtactv (& self) -> QevtactvR { QevtactvR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
# [inline (always)]
pub fn tractv (& self) -> TractvR { TractvR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res64 (& self) -> Res64R { Res64R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
# [inline (always)]
pub fn actv (& self) -> ActvR { ActvR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res63 (& self) -> Res63R { Res63R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:13 - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
# [inline (always)]
pub fn compactv (& self) -> CompactvR { CompactvR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 14:15 - 15:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res62 (& self) -> Res62R { Res62R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
# [inline (always)]
pub fn queactv0 (& self) -> Queactv0R { Queactv0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
# [inline (always)]
pub fn queactv1 (& self) -> Queactv1R { Queactv1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
# [inline (always)]
pub fn queactv2 (& self) -> Queactv2R { Queactv2R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
# [inline (always)]
pub fn queactv3 (& self) -> Queactv3R { Queactv3R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
# [inline (always)]
pub fn queactv4 (& self) -> Queactv4R { Queactv4R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
# [inline (always)]
pub fn queactv5 (& self) -> Queactv5R { Queactv5R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
# [inline (always)]
pub fn queactv6 (& self) -> Queactv6R { Queactv6R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
# [inline (always)]
pub fn queactv7 (& self) -> Queactv7R { Queactv7R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:31 - 31:24\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res61 (& self) -> Res61R { Res61R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
# [must_use]
pub fn evtactv (& mut self) -> EvtactvW < CcstatSpec > { EvtactvW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
# [must_use]
pub fn qevtactv (& mut self) -> QevtactvW < CcstatSpec > { QevtactvW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
# [inline (always)]
# [must_use]
pub fn tractv (& mut self) -> TractvW < CcstatSpec > { TractvW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res64 (& mut self) -> Res64W < CcstatSpec > { Res64W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
# [inline (always)]
# [must_use]
pub fn actv (& mut self) -> ActvW < CcstatSpec > { ActvW :: new (self , 4) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res63 (& mut self) -> Res63W < CcstatSpec > { Res63W :: new (self , 5) } # [doc = "Bits 8:13 - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
# [inline (always)]
# [must_use]
pub fn compactv (& mut self) -> CompactvW < CcstatSpec > { CompactvW :: new (self , 8) } # [doc = "Bits 14:15 - 15:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res62 (& mut self) -> Res62W < CcstatSpec > { Res62W :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
# [inline (always)]
# [must_use]
pub fn queactv0 (& mut self) -> Queactv0W < CcstatSpec > { Queactv0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
# [inline (always)]
# [must_use]
pub fn queactv1 (& mut self) -> Queactv1W < CcstatSpec > { Queactv1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
# [inline (always)]
# [must_use]
pub fn queactv2 (& mut self) -> Queactv2W < CcstatSpec > { Queactv2W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
# [inline (always)]
# [must_use]
pub fn queactv3 (& mut self) -> Queactv3W < CcstatSpec > { Queactv3W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
# [inline (always)]
# [must_use]
pub fn queactv4 (& mut self) -> Queactv4W < CcstatSpec > { Queactv4W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
# [inline (always)]
# [must_use]
pub fn queactv5 (& mut self) -> Queactv5W < CcstatSpec > { Queactv5W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
# [inline (always)]
# [must_use]
pub fn queactv6 (& mut self) -> Queactv6W < CcstatSpec > { Queactv6W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
# [inline (always)]
# [must_use]
pub fn queactv7 (& mut self) -> Queactv7W < CcstatSpec > { Queactv7W :: new (self , 23) } # [doc = "Bits 24:31 - 31:24\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res61 (& mut self) -> Res61W < CcstatSpec > { Res61W :: new (self , 24) } } # [doc = "CC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcstatSpec ; impl crate :: RegisterSpec for CcstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccstat::R`](R) reader structure"]
impl crate :: Readable for CcstatSpec { } # [doc = "`write(|w| ..)` method takes [`ccstat::W`](W) writer structure"]
impl crate :: Writable for CcstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCSTAT to value 0"]
impl crate :: Resettable for CcstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AETCTL (rw) register accessor: Advanced Event Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`aetctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aetctl`]
module"]
# [doc (alias = "AETCTL")]
pub type Aetctl = crate :: Reg < aetctl :: AetctlSpec > ; # [doc = "Advanced Event Trigger Control"]
pub mod aetctl { # [doc = "Register `AETCTL` reader"]
pub type R = crate :: R < AetctlSpec > ; # [doc = "Register `AETCTL` writer"]
pub type W = crate :: W < AetctlSpec > ; # [doc = "Field `STRTEVT` reader - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
pub type StrtevtR = crate :: FieldReader ; # [doc = "Field `STRTEVT` writer - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
pub type StrtevtW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TYPE` reader - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
pub type TypeR = crate :: BitReader ; # [doc = "Field `TYPE` writer - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
pub type TypeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES66` reader - 7:7\\]
RESERVE FIELD"]
pub type Res66R = crate :: BitReader ; # [doc = "Field `RES66` writer - 7:7\\]
RESERVE FIELD"]
pub type Res66W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENDINT` reader - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
pub type EndintR = crate :: FieldReader ; # [doc = "Field `ENDINT` writer - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
pub type EndintW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RES65` reader - 30:14\\]
RESERVE FIELD"]
pub type Res65R = crate :: FieldReader < u32 > ; # [doc = "Field `RES65` writer - 30:14\\]
RESERVE FIELD"]
pub type Res65W < 'a , REG > = crate :: FieldWriter < 'a , REG , 17 , u32 > ; # [doc = "Field `EN` reader - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
# [inline (always)]
pub fn strtevt (& self) -> StrtevtR { StrtevtR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
# [inline (always)]
pub fn type_ (& self) -> TypeR { TypeR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res66 (& self) -> Res66R { Res66R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:13 - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
# [inline (always)]
pub fn endint (& self) -> EndintR { EndintR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 14:30 - 30:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res65 (& self) -> Res65R { Res65R :: new ((self . bits >> 14) & 0x0001_ffff) } # [doc = "Bit 31 - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
# [inline (always)]
# [must_use]
pub fn strtevt (& mut self) -> StrtevtW < AetctlSpec > { StrtevtW :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
# [inline (always)]
# [must_use]
pub fn type_ (& mut self) -> TypeW < AetctlSpec > { TypeW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res66 (& mut self) -> Res66W < AetctlSpec > { Res66W :: new (self , 7) } # [doc = "Bits 8:13 - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
# [inline (always)]
# [must_use]
pub fn endint (& mut self) -> EndintW < AetctlSpec > { EndintW :: new (self , 8) } # [doc = "Bits 14:30 - 30:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res65 (& mut self) -> Res65W < AetctlSpec > { Res65W :: new (self , 14) } # [doc = "Bit 31 - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < AetctlSpec > { EnW :: new (self , 31) } } # [doc = "Advanced Event Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`aetctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AetctlSpec ; impl crate :: RegisterSpec for AetctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aetctl::R`](R) reader structure"]
impl crate :: Readable for AetctlSpec { } # [doc = "`write(|w| ..)` method takes [`aetctl::W`](W) writer structure"]
impl crate :: Writable for AetctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AETCTL to value 0"]
impl crate :: Resettable for AetctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AETSTAT (rw) register accessor: Advanced Event Trigger Stat\n\nYou can [`read`](crate::Reg::read) this register and get [`aetstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aetstat`]
module"]
# [doc (alias = "AETSTAT")]
pub type Aetstat = crate :: Reg < aetstat :: AetstatSpec > ; # [doc = "Advanced Event Trigger Stat"]
pub mod aetstat { # [doc = "Register `AETSTAT` reader"]
pub type R = crate :: R < AetstatSpec > ; # [doc = "Register `AETSTAT` writer"]
pub type W = crate :: W < AetstatSpec > ; # [doc = "Field `STAT` reader - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
pub type StatR = crate :: BitReader ; # [doc = "Field `STAT` writer - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
pub type StatW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES67` reader - 31:1\\]
RESERVE FIELD"]
pub type Res67R = crate :: FieldReader < u32 > ; # [doc = "Field `RES67` writer - 31:1\\]
RESERVE FIELD"]
pub type Res67W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
# [inline (always)]
pub fn stat (& self) -> StatR { StatR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res67 (& self) -> Res67R { Res67R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
# [inline (always)]
# [must_use]
pub fn stat (& mut self) -> StatW < AetstatSpec > { StatW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res67 (& mut self) -> Res67W < AetstatSpec > { Res67W :: new (self , 1) } } # [doc = "Advanced Event Trigger Stat\n\nYou can [`read`](crate::Reg::read) this register and get [`aetstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AetstatSpec ; impl crate :: RegisterSpec for AetstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aetstat::R`](R) reader structure"]
impl crate :: Readable for AetstatSpec { } # [doc = "`write(|w| ..)` method takes [`aetstat::W`](W) writer structure"]
impl crate :: Writable for AetstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AETSTAT to value 0"]
impl crate :: Resettable for AetstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AETCMD (rw) register accessor: AET Command\n\nYou can [`read`](crate::Reg::read) this register and get [`aetcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aetcmd`]
module"]
# [doc (alias = "AETCMD")]
pub type Aetcmd = crate :: Reg < aetcmd :: AetcmdSpec > ; # [doc = "AET Command"]
pub mod aetcmd { # [doc = "Register `AETCMD` reader"]
pub type R = crate :: R < AetcmdSpec > ; # [doc = "Register `AETCMD` writer"]
pub type W = crate :: W < AetcmdSpec > ; # [doc = "Field `CLR` reader - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
pub type ClrR = crate :: BitReader ; # [doc = "Field `CLR` writer - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
pub type ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES68` reader - 31:1\\]
RESERVE FIELD"]
pub type Res68R = crate :: FieldReader < u32 > ; # [doc = "Field `RES68` writer - 31:1\\]
RESERVE FIELD"]
pub type Res68W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub fn clr (& self) -> ClrR { ClrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res68 (& self) -> Res68R { Res68R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
# [must_use]
pub fn clr (& mut self) -> ClrW < AetcmdSpec > { ClrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res68 (& mut self) -> Res68W < AetcmdSpec > { Res68W :: new (self , 1) } } # [doc = "AET Command\n\nYou can [`read`](crate::Reg::read) this register and get [`aetcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AetcmdSpec ; impl crate :: RegisterSpec for AetcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aetcmd::R`](R) reader structure"]
impl crate :: Readable for AetcmdSpec { } # [doc = "`write(|w| ..)` method takes [`aetcmd::W`](W) writer structure"]
impl crate :: Writable for AetcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AETCMD to value 0"]
impl crate :: Resettable for AetcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ER (rw) register accessor: Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@er`]
module"]
# [doc (alias = "ER")]
pub type Er = crate :: Reg < er :: ErSpec > ; # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
pub mod er { # [doc = "Register `ER` reader"]
pub type R = crate :: R < ErSpec > ; # [doc = "Register `ER` writer"]
pub type W = crate :: W < ErSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < ErSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < ErSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < ErSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < ErSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < ErSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < ErSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < ErSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < ErSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < ErSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < ErSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < ErSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < ErSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < ErSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < ErSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < ErSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < ErSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < ErSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < ErSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < ErSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < ErSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < ErSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < ErSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < ErSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < ErSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < ErSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < ErSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < ErSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < ErSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < ErSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < ErSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < ErSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < ErSpec > { E31W :: new (self , 31) } } # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErSpec ; impl crate :: RegisterSpec for ErSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`er::R`](R) reader structure"]
impl crate :: Readable for ErSpec { } # [doc = "`write(|w| ..)` method takes [`er::W`](W) writer structure"]
impl crate :: Writable for ErSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ER to value 0"]
impl crate :: Resettable for ErSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERH (rw) register accessor: Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erh`]
module"]
# [doc (alias = "ERH")]
pub type Erh = crate :: Reg < erh :: ErhSpec > ; # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
pub mod erh { # [doc = "Register `ERH` reader"]
pub type R = crate :: R < ErhSpec > ; # [doc = "Register `ERH` writer"]
pub type W = crate :: W < ErhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < ErhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < ErhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < ErhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < ErhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < ErhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < ErhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < ErhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < ErhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < ErhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < ErhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < ErhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < ErhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < ErhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < ErhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < ErhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < ErhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < ErhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < ErhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < ErhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < ErhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < ErhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < ErhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < ErhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < ErhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < ErhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < ErhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < ErhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < ErhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < ErhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < ErhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < ErhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < ErhSpec > { E63W :: new (self , 31) } } # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErhSpec ; impl crate :: RegisterSpec for ErhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erh::R`](R) reader structure"]
impl crate :: Readable for ErhSpec { } # [doc = "`write(|w| ..)` method takes [`erh::W`](W) writer structure"]
impl crate :: Writable for ErhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERH to value 0"]
impl crate :: Resettable for ErhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECR (rw) register accessor: Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`]
module"]
# [doc (alias = "ECR")]
pub type Ecr = crate :: Reg < ecr :: EcrSpec > ; # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecr { # [doc = "Register `ECR` reader"]
pub type R = crate :: R < EcrSpec > ; # [doc = "Register `ECR` writer"]
pub type W = crate :: W < EcrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EcrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EcrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EcrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EcrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EcrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EcrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EcrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EcrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EcrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EcrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EcrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EcrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EcrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EcrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EcrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EcrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EcrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EcrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EcrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EcrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EcrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EcrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EcrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EcrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EcrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EcrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EcrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EcrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EcrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EcrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EcrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EcrSpec > { E31W :: new (self , 31) } } # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrSpec ; impl crate :: RegisterSpec for EcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecr::R`](R) reader structure"]
impl crate :: Readable for EcrSpec { } # [doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"]
impl crate :: Writable for EcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECR to value 0"]
impl crate :: Resettable for EcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECRH (rw) register accessor: Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecrh`]
module"]
# [doc (alias = "ECRH")]
pub type Ecrh = crate :: Reg < ecrh :: EcrhSpec > ; # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecrh { # [doc = "Register `ECRH` reader"]
pub type R = crate :: R < EcrhSpec > ; # [doc = "Register `ECRH` writer"]
pub type W = crate :: W < EcrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EcrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EcrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EcrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EcrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EcrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EcrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EcrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EcrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EcrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EcrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EcrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EcrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EcrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EcrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EcrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EcrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EcrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EcrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EcrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EcrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EcrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EcrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EcrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EcrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EcrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EcrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EcrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EcrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EcrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EcrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EcrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EcrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrhSpec ; impl crate :: RegisterSpec for EcrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecrh::R`](R) reader structure"]
impl crate :: Readable for EcrhSpec { } # [doc = "`write(|w| ..)` method takes [`ecrh::W`](W) writer structure"]
impl crate :: Writable for EcrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECRH to value 0"]
impl crate :: Resettable for EcrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESR (rw) register accessor: Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr`]
module"]
# [doc (alias = "ESR")]
pub type Esr = crate :: Reg < esr :: EsrSpec > ; # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
pub mod esr { # [doc = "Register `ESR` reader"]
pub type R = crate :: R < EsrSpec > ; # [doc = "Register `ESR` writer"]
pub type W = crate :: W < EsrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EsrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EsrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EsrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EsrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EsrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EsrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EsrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EsrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EsrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EsrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EsrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EsrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EsrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EsrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EsrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EsrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EsrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EsrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EsrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EsrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EsrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EsrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EsrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EsrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EsrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EsrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EsrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EsrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EsrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EsrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EsrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EsrSpec > { E31W :: new (self , 31) } } # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrSpec ; impl crate :: RegisterSpec for EsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esr::R`](R) reader structure"]
impl crate :: Readable for EsrSpec { } # [doc = "`write(|w| ..)` method takes [`esr::W`](W) writer structure"]
impl crate :: Writable for EsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESR to value 0"]
impl crate :: Resettable for EsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESRH (rw) register accessor: Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esrh`]
module"]
# [doc (alias = "ESRH")]
pub type Esrh = crate :: Reg < esrh :: EsrhSpec > ; # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
pub mod esrh { # [doc = "Register `ESRH` reader"]
pub type R = crate :: R < EsrhSpec > ; # [doc = "Register `ESRH` writer"]
pub type W = crate :: W < EsrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EsrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EsrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EsrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EsrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EsrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EsrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EsrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EsrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EsrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EsrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EsrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EsrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EsrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EsrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EsrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EsrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EsrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EsrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EsrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EsrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EsrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EsrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EsrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EsrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EsrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EsrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EsrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EsrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EsrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EsrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EsrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EsrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrhSpec ; impl crate :: RegisterSpec for EsrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esrh::R`](R) reader structure"]
impl crate :: Readable for EsrhSpec { } # [doc = "`write(|w| ..)` method takes [`esrh::W`](W) writer structure"]
impl crate :: Writable for EsrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESRH to value 0"]
impl crate :: Resettable for EsrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CER (rw) register accessor: Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cer`]
module"]
# [doc (alias = "CER")]
pub type Cer = crate :: Reg < cer :: CerSpec > ; # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
pub mod cer { # [doc = "Register `CER` reader"]
pub type R = crate :: R < CerSpec > ; # [doc = "Register `CER` writer"]
pub type W = crate :: W < CerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < CerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < CerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < CerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < CerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < CerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < CerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < CerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < CerSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < CerSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < CerSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < CerSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < CerSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < CerSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < CerSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < CerSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < CerSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < CerSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < CerSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < CerSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < CerSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < CerSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < CerSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < CerSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < CerSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < CerSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < CerSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < CerSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < CerSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < CerSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < CerSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < CerSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < CerSpec > { E31W :: new (self , 31) } } # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerSpec ; impl crate :: RegisterSpec for CerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cer::R`](R) reader structure"]
impl crate :: Readable for CerSpec { } # [doc = "`write(|w| ..)` method takes [`cer::W`](W) writer structure"]
impl crate :: Writable for CerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CER to value 0"]
impl crate :: Resettable for CerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CERH (rw) register accessor: Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cerh`]
module"]
# [doc (alias = "CERH")]
pub type Cerh = crate :: Reg < cerh :: CerhSpec > ; # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
pub mod cerh { # [doc = "Register `CERH` reader"]
pub type R = crate :: R < CerhSpec > ; # [doc = "Register `CERH` writer"]
pub type W = crate :: W < CerhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < CerhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < CerhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < CerhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < CerhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < CerhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < CerhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < CerhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < CerhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < CerhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < CerhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < CerhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < CerhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < CerhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < CerhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < CerhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < CerhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < CerhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < CerhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < CerhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < CerhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < CerhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < CerhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < CerhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < CerhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < CerhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < CerhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < CerhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < CerhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < CerhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < CerhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < CerhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < CerhSpec > { E63W :: new (self , 31) } } # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerhSpec ; impl crate :: RegisterSpec for CerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cerh::R`](R) reader structure"]
impl crate :: Readable for CerhSpec { } # [doc = "`write(|w| ..)` method takes [`cerh::W`](W) writer structure"]
impl crate :: Writable for CerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CERH to value 0"]
impl crate :: Resettable for CerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EER (rw) register accessor: Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eer`]
module"]
# [doc (alias = "EER")]
pub type Eer = crate :: Reg < eer :: EerSpec > ; # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eer { # [doc = "Register `EER` reader"]
pub type R = crate :: R < EerSpec > ; # [doc = "Register `EER` writer"]
pub type W = crate :: W < EerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EerSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EerSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EerSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EerSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EerSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EerSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EerSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EerSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EerSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EerSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EerSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EerSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EerSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EerSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EerSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EerSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EerSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EerSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EerSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EerSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EerSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EerSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EerSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EerSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EerSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerSpec ; impl crate :: RegisterSpec for EerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eer::R`](R) reader structure"]
impl crate :: Readable for EerSpec { } # [doc = "`write(|w| ..)` method takes [`eer::W`](W) writer structure"]
impl crate :: Writable for EerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EER to value 0"]
impl crate :: Resettable for EerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EERH (rw) register accessor: Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eerh`]
module"]
# [doc (alias = "EERH")]
pub type Eerh = crate :: Reg < eerh :: EerhSpec > ; # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eerh { # [doc = "Register `EERH` reader"]
pub type R = crate :: R < EerhSpec > ; # [doc = "Register `EERH` writer"]
pub type W = crate :: W < EerhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EerhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EerhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EerhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EerhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EerhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EerhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EerhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EerhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EerhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EerhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EerhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EerhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EerhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EerhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EerhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EerhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EerhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EerhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EerhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EerhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EerhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EerhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EerhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EerhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EerhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EerhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EerhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EerhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EerhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EerhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EerhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EerhSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerhSpec ; impl crate :: RegisterSpec for EerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eerh::R`](R) reader structure"]
impl crate :: Readable for EerhSpec { } # [doc = "`write(|w| ..)` method takes [`eerh::W`](W) writer structure"]
impl crate :: Writable for EerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EERH to value 0"]
impl crate :: Resettable for EerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECR (rw) register accessor: Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecr`]
module"]
# [doc (alias = "EECR")]
pub type Eecr = crate :: Reg < eecr :: EecrSpec > ; # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecr { # [doc = "Register `EECR` reader"]
pub type R = crate :: R < EecrSpec > ; # [doc = "Register `EECR` writer"]
pub type W = crate :: W < EecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EecrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EecrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EecrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EecrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EecrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EecrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EecrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EecrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EecrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EecrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EecrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EecrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EecrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EecrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EecrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EecrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EecrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EecrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EecrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EecrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EecrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EecrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EecrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EecrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EecrSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrSpec ; impl crate :: RegisterSpec for EecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecr::R`](R) reader structure"]
impl crate :: Readable for EecrSpec { } # [doc = "`write(|w| ..)` method takes [`eecr::W`](W) writer structure"]
impl crate :: Writable for EecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECR to value 0"]
impl crate :: Resettable for EecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECRH (rw) register accessor: Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecrh`]
module"]
# [doc (alias = "EECRH")]
pub type Eecrh = crate :: Reg < eecrh :: EecrhSpec > ; # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecrh { # [doc = "Register `EECRH` reader"]
pub type R = crate :: R < EecrhSpec > ; # [doc = "Register `EECRH` writer"]
pub type W = crate :: W < EecrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EecrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EecrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EecrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EecrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EecrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EecrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EecrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EecrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EecrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EecrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EecrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EecrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EecrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EecrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EecrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EecrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EecrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EecrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EecrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EecrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EecrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EecrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EecrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EecrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EecrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EecrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EecrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EecrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EecrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EecrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EecrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EecrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrhSpec ; impl crate :: RegisterSpec for EecrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecrh::R`](R) reader structure"]
impl crate :: Readable for EecrhSpec { } # [doc = "`write(|w| ..)` method takes [`eecrh::W`](W) writer structure"]
impl crate :: Writable for EecrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECRH to value 0"]
impl crate :: Resettable for EecrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESR (rw) register accessor: Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesr`]
module"]
# [doc (alias = "EESR")]
pub type Eesr = crate :: Reg < eesr :: EesrSpec > ; # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesr { # [doc = "Register `EESR` reader"]
pub type R = crate :: R < EesrSpec > ; # [doc = "Register `EESR` writer"]
pub type W = crate :: W < EesrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EesrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EesrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EesrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EesrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EesrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EesrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EesrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EesrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EesrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EesrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EesrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EesrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EesrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EesrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EesrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EesrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EesrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EesrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EesrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EesrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EesrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EesrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EesrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EesrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EesrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EesrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EesrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EesrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EesrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EesrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EesrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EesrSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrSpec ; impl crate :: RegisterSpec for EesrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesr::R`](R) reader structure"]
impl crate :: Readable for EesrSpec { } # [doc = "`write(|w| ..)` method takes [`eesr::W`](W) writer structure"]
impl crate :: Writable for EesrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESR to value 0"]
impl crate :: Resettable for EesrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESRH (rw) register accessor: Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesrh`]
module"]
# [doc (alias = "EESRH")]
pub type Eesrh = crate :: Reg < eesrh :: EesrhSpec > ; # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesrh { # [doc = "Register `EESRH` reader"]
pub type R = crate :: R < EesrhSpec > ; # [doc = "Register `EESRH` writer"]
pub type W = crate :: W < EesrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EesrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EesrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EesrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EesrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EesrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EesrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EesrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EesrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EesrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EesrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EesrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EesrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EesrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EesrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EesrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EesrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EesrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EesrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EesrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EesrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EesrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EesrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EesrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EesrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EesrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EesrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EesrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EesrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EesrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EesrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EesrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EesrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrhSpec ; impl crate :: RegisterSpec for EesrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesrh::R`](R) reader structure"]
impl crate :: Readable for EesrhSpec { } # [doc = "`write(|w| ..)` method takes [`eesrh::W`](W) writer structure"]
impl crate :: Writable for EesrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESRH to value 0"]
impl crate :: Resettable for EesrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SER (rw) register accessor: Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ser`]
module"]
# [doc (alias = "SER")]
pub type Ser = crate :: Reg < ser :: SerSpec > ; # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod ser { # [doc = "Register `SER` reader"]
pub type R = crate :: R < SerSpec > ; # [doc = "Register `SER` writer"]
pub type W = crate :: W < SerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SerSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SerSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SerSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SerSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SerSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SerSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SerSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SerSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SerSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SerSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SerSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SerSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SerSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SerSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SerSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SerSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SerSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SerSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SerSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SerSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SerSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SerSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SerSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SerSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SerSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerSpec ; impl crate :: RegisterSpec for SerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ser::R`](R) reader structure"]
impl crate :: Readable for SerSpec { } # [doc = "`write(|w| ..)` method takes [`ser::W`](W) writer structure"]
impl crate :: Writable for SerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SER to value 0"]
impl crate :: Resettable for SerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SERH (rw) register accessor: Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@serh`]
module"]
# [doc (alias = "SERH")]
pub type Serh = crate :: Reg < serh :: SerhSpec > ; # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod serh { # [doc = "Register `SERH` reader"]
pub type R = crate :: R < SerhSpec > ; # [doc = "Register `SERH` writer"]
pub type W = crate :: W < SerhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SerhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SerhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SerhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SerhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SerhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SerhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SerhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SerhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SerhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SerhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SerhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SerhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SerhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SerhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SerhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SerhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SerhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SerhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SerhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SerhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SerhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SerhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SerhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SerhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SerhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SerhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SerhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SerhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SerhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SerhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SerhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SerhSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerhSpec ; impl crate :: RegisterSpec for SerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`serh::R`](R) reader structure"]
impl crate :: Readable for SerhSpec { } # [doc = "`write(|w| ..)` method takes [`serh::W`](W) writer structure"]
impl crate :: Writable for SerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SERH to value 0"]
impl crate :: Resettable for SerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECR (rw) register accessor: Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secr`]
module"]
# [doc (alias = "SECR")]
pub type Secr = crate :: Reg < secr :: SecrSpec > ; # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
pub mod secr { # [doc = "Register `SECR` reader"]
pub type R = crate :: R < SecrSpec > ; # [doc = "Register `SECR` writer"]
pub type W = crate :: W < SecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SecrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SecrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SecrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SecrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SecrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SecrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SecrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SecrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SecrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SecrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SecrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SecrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SecrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SecrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SecrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SecrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SecrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SecrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SecrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SecrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SecrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SecrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SecrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SecrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SecrSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrSpec ; impl crate :: RegisterSpec for SecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secr::R`](R) reader structure"]
impl crate :: Readable for SecrSpec { } # [doc = "`write(|w| ..)` method takes [`secr::W`](W) writer structure"]
impl crate :: Writable for SecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECR to value 0"]
impl crate :: Resettable for SecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECRH (rw) register accessor: Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secrh`]
module"]
# [doc (alias = "SECRH")]
pub type Secrh = crate :: Reg < secrh :: SecrhSpec > ; # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
pub mod secrh { # [doc = "Register `SECRH` reader"]
pub type R = crate :: R < SecrhSpec > ; # [doc = "Register `SECRH` writer"]
pub type W = crate :: W < SecrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SecrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SecrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SecrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SecrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SecrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SecrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SecrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SecrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SecrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SecrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SecrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SecrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SecrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SecrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SecrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SecrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SecrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SecrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SecrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SecrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SecrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SecrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SecrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SecrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SecrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SecrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SecrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SecrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SecrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SecrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SecrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SecrhSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrhSpec ; impl crate :: RegisterSpec for SecrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secrh::R`](R) reader structure"]
impl crate :: Readable for SecrhSpec { } # [doc = "`write(|w| ..)` method takes [`secrh::W`](W) writer structure"]
impl crate :: Writable for SecrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECRH to value 0"]
impl crate :: Resettable for SecrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IER (rw) register accessor: Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
# [doc (alias = "IER")]
pub type Ier = crate :: Reg < ier :: IerSpec > ; # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
pub mod ier { # [doc = "Register `IER` reader"]
pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"]
pub type W = crate :: W < IerSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IerSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IerSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IerSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IerSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IerSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IerSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IerSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IerSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IerSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IerSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IerSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IerSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IerSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IerSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IerSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IerSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IerSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IerSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IerSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IerSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IerSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IerSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IerSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IerSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IerSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IerSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IerSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IerSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IerSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IerSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IerSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IerSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IER to value 0"]
impl crate :: Resettable for IerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IERH (rw) register accessor: Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ierh`]
module"]
# [doc (alias = "IERH")]
pub type Ierh = crate :: Reg < ierh :: IerhSpec > ; # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
pub mod ierh { # [doc = "Register `IERH` reader"]
pub type R = crate :: R < IerhSpec > ; # [doc = "Register `IERH` writer"]
pub type W = crate :: W < IerhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IerhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IerhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IerhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IerhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IerhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IerhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IerhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IerhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IerhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IerhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IerhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IerhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IerhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IerhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IerhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IerhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IerhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IerhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IerhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IerhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IerhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IerhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IerhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IerhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IerhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IerhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IerhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IerhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IerhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IerhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IerhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IerhSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerhSpec ; impl crate :: RegisterSpec for IerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ierh::R`](R) reader structure"]
impl crate :: Readable for IerhSpec { } # [doc = "`write(|w| ..)` method takes [`ierh::W`](W) writer structure"]
impl crate :: Writable for IerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IERH to value 0"]
impl crate :: Resettable for IerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECR (rw) register accessor: Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecr`]
module"]
# [doc (alias = "IECR")]
pub type Iecr = crate :: Reg < iecr :: IecrSpec > ; # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecr { # [doc = "Register `IECR` reader"]
pub type R = crate :: R < IecrSpec > ; # [doc = "Register `IECR` writer"]
pub type W = crate :: W < IecrSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IecrSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IecrSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IecrSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IecrSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IecrSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IecrSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IecrSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IecrSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IecrSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IecrSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IecrSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IecrSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IecrSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IecrSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IecrSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IecrSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IecrSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IecrSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IecrSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IecrSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IecrSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IecrSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IecrSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IecrSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IecrSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IecrSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IecrSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IecrSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IecrSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IecrSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IecrSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IecrSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrSpec ; impl crate :: RegisterSpec for IecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecr::R`](R) reader structure"]
impl crate :: Readable for IecrSpec { } # [doc = "`write(|w| ..)` method takes [`iecr::W`](W) writer structure"]
impl crate :: Writable for IecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECR to value 0"]
impl crate :: Resettable for IecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECRH (rw) register accessor: Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecrh`]
module"]
# [doc (alias = "IECRH")]
pub type Iecrh = crate :: Reg < iecrh :: IecrhSpec > ; # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecrh { # [doc = "Register `IECRH` reader"]
pub type R = crate :: R < IecrhSpec > ; # [doc = "Register `IECRH` writer"]
pub type W = crate :: W < IecrhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IecrhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IecrhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IecrhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IecrhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IecrhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IecrhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IecrhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IecrhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IecrhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IecrhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IecrhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IecrhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IecrhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IecrhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IecrhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IecrhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IecrhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IecrhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IecrhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IecrhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IecrhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IecrhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IecrhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IecrhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IecrhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IecrhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IecrhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IecrhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IecrhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IecrhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IecrhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IecrhSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrhSpec ; impl crate :: RegisterSpec for IecrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecrh::R`](R) reader structure"]
impl crate :: Readable for IecrhSpec { } # [doc = "`write(|w| ..)` method takes [`iecrh::W`](W) writer structure"]
impl crate :: Writable for IecrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECRH to value 0"]
impl crate :: Resettable for IecrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESR (rw) register accessor: Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesr`]
module"]
# [doc (alias = "IESR")]
pub type Iesr = crate :: Reg < iesr :: IesrSpec > ; # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesr { # [doc = "Register `IESR` reader"]
pub type R = crate :: R < IesrSpec > ; # [doc = "Register `IESR` writer"]
pub type W = crate :: W < IesrSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IesrSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IesrSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IesrSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IesrSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IesrSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IesrSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IesrSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IesrSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IesrSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IesrSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IesrSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IesrSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IesrSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IesrSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IesrSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IesrSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IesrSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IesrSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IesrSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IesrSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IesrSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IesrSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IesrSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IesrSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IesrSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IesrSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IesrSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IesrSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IesrSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IesrSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IesrSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IesrSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrSpec ; impl crate :: RegisterSpec for IesrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesr::R`](R) reader structure"]
impl crate :: Readable for IesrSpec { } # [doc = "`write(|w| ..)` method takes [`iesr::W`](W) writer structure"]
impl crate :: Writable for IesrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESR to value 0"]
impl crate :: Resettable for IesrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESRH (rw) register accessor: Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesrh`]
module"]
# [doc (alias = "IESRH")]
pub type Iesrh = crate :: Reg < iesrh :: IesrhSpec > ; # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesrh { # [doc = "Register `IESRH` reader"]
pub type R = crate :: R < IesrhSpec > ; # [doc = "Register `IESRH` writer"]
pub type W = crate :: W < IesrhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IesrhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IesrhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IesrhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IesrhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IesrhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IesrhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IesrhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IesrhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IesrhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IesrhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IesrhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IesrhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IesrhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IesrhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IesrhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IesrhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IesrhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IesrhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IesrhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IesrhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IesrhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IesrhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IesrhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IesrhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IesrhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IesrhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IesrhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IesrhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IesrhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IesrhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IesrhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IesrhSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrhSpec ; impl crate :: RegisterSpec for IesrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesrh::R`](R) reader structure"]
impl crate :: Readable for IesrhSpec { } # [doc = "`write(|w| ..)` method takes [`iesrh::W`](W) writer structure"]
impl crate :: Writable for IesrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESRH to value 0"]
impl crate :: Resettable for IesrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPR (rw) register accessor: Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipr`]
module"]
# [doc (alias = "IPR")]
pub type Ipr = crate :: Reg < ipr :: IprSpec > ; # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
pub mod ipr { # [doc = "Register `IPR` reader"]
pub type R = crate :: R < IprSpec > ; # [doc = "Register `IPR` writer"]
pub type W = crate :: W < IprSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IprSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IprSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IprSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IprSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IprSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IprSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IprSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IprSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IprSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IprSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IprSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IprSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IprSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IprSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IprSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IprSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IprSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IprSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IprSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IprSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IprSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IprSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IprSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IprSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IprSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IprSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IprSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IprSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IprSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IprSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IprSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IprSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprSpec ; impl crate :: RegisterSpec for IprSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipr::R`](R) reader structure"]
impl crate :: Readable for IprSpec { } # [doc = "`write(|w| ..)` method takes [`ipr::W`](W) writer structure"]
impl crate :: Writable for IprSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPR to value 0"]
impl crate :: Resettable for IprSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPRH (rw) register accessor: Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iprh`]
module"]
# [doc (alias = "IPRH")]
pub type Iprh = crate :: Reg < iprh :: IprhSpec > ; # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
pub mod iprh { # [doc = "Register `IPRH` reader"]
pub type R = crate :: R < IprhSpec > ; # [doc = "Register `IPRH` writer"]
pub type W = crate :: W < IprhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IprhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IprhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IprhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IprhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IprhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IprhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IprhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IprhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IprhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IprhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IprhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IprhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IprhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IprhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IprhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IprhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IprhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IprhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IprhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IprhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IprhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IprhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IprhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IprhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IprhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IprhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IprhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IprhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IprhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IprhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IprhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IprhSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprhSpec ; impl crate :: RegisterSpec for IprhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iprh::R`](R) reader structure"]
impl crate :: Readable for IprhSpec { } # [doc = "`write(|w| ..)` method takes [`iprh::W`](W) writer structure"]
impl crate :: Writable for IprhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPRH to value 0"]
impl crate :: Resettable for IprhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICR (rw) register accessor: Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
# [doc (alias = "ICR")]
pub type Icr = crate :: Reg < icr :: IcrSpec > ; # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icr { # [doc = "Register `ICR` reader"]
pub type R = crate :: R < IcrSpec > ; # [doc = "Register `ICR` writer"]
pub type W = crate :: W < IcrSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IcrSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IcrSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IcrSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IcrSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IcrSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IcrSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IcrSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IcrSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IcrSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IcrSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IcrSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IcrSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IcrSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IcrSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IcrSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IcrSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IcrSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IcrSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IcrSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IcrSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IcrSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IcrSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IcrSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IcrSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IcrSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IcrSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IcrSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IcrSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IcrSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IcrSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IcrSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IcrSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate :: Readable for IcrSpec { } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICR to value 0"]
impl crate :: Resettable for IcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICRH (rw) register accessor: Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icrh`]
module"]
# [doc (alias = "ICRH")]
pub type Icrh = crate :: Reg < icrh :: IcrhSpec > ; # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icrh { # [doc = "Register `ICRH` reader"]
pub type R = crate :: R < IcrhSpec > ; # [doc = "Register `ICRH` writer"]
pub type W = crate :: W < IcrhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IcrhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IcrhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IcrhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IcrhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IcrhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IcrhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IcrhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IcrhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IcrhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IcrhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IcrhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IcrhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IcrhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IcrhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IcrhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IcrhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IcrhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IcrhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IcrhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IcrhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IcrhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IcrhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IcrhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IcrhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IcrhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IcrhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IcrhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IcrhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IcrhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IcrhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IcrhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IcrhSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrhSpec ; impl crate :: RegisterSpec for IcrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icrh::R`](R) reader structure"]
impl crate :: Readable for IcrhSpec { } # [doc = "`write(|w| ..)` method takes [`icrh::W`](W) writer structure"]
impl crate :: Writable for IcrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICRH to value 0"]
impl crate :: Resettable for IcrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IEVAL (rw) register accessor: Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ieval`]
module"]
# [doc (alias = "IEVAL")]
pub type Ieval = crate :: Reg < ieval :: IevalSpec > ; # [doc = "Interrupt Eval Register"]
pub mod ieval { # [doc = "Register `IEVAL` reader"]
pub type R = crate :: R < IevalSpec > ; # [doc = "Register `IEVAL` writer"]
pub type W = crate :: W < IevalSpec > ; # [doc = "Field `EVAL` reader - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalR = crate :: BitReader ; # [doc = "Field `EVAL` writer - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET` reader - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetR = crate :: BitReader ; # [doc = "Field `SET` writer - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES69` reader - 31:2\\]
RESERVE FIELD"]
pub type Res69R = crate :: FieldReader < u32 > ; # [doc = "Field `RES69` writer - 31:2\\]
RESERVE FIELD"]
pub type Res69W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
pub fn eval (& self) -> EvalR { EvalR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res69 (& self) -> Res69R { Res69R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
# [must_use]
pub fn eval (& mut self) -> EvalW < IevalSpec > { EvalW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < IevalSpec > { SetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res69 (& mut self) -> Res69W < IevalSpec > { Res69W :: new (self , 2) } } # [doc = "Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IevalSpec ; impl crate :: RegisterSpec for IevalSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ieval::R`](R) reader structure"]
impl crate :: Readable for IevalSpec { } # [doc = "`write(|w| ..)` method takes [`ieval::W`](W) writer structure"]
impl crate :: Writable for IevalSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IEVAL to value 0"]
impl crate :: Resettable for IevalSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QER (rw) register accessor: QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qer`]
module"]
# [doc (alias = "QER")]
pub type Qer = crate :: Reg < qer :: QerSpec > ; # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
pub mod qer { # [doc = "Register `QER` reader"]
pub type R = crate :: R < QerSpec > ; # [doc = "Register `QER` writer"]
pub type W = crate :: W < QerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES70` reader - 31:8\\]
RESERVE FIELD"]
pub type Res70R = crate :: FieldReader < u32 > ; # [doc = "Field `RES70` writer - 31:8\\]
RESERVE FIELD"]
pub type Res70W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res70 (& self) -> Res70R { Res70R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QerSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res70 (& mut self) -> Res70W < QerSpec > { Res70W :: new (self , 8) } } # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QerSpec ; impl crate :: RegisterSpec for QerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qer::R`](R) reader structure"]
impl crate :: Readable for QerSpec { } # [doc = "`write(|w| ..)` method takes [`qer::W`](W) writer structure"]
impl crate :: Writable for QerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QER to value 0"]
impl crate :: Resettable for QerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEER (rw) register accessor: QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeer`]
module"]
# [doc (alias = "QEER")]
pub type Qeer = crate :: Reg < qeer :: QeerSpec > ; # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
pub mod qeer { # [doc = "Register `QEER` reader"]
pub type R = crate :: R < QeerSpec > ; # [doc = "Register `QEER` writer"]
pub type W = crate :: W < QeerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES71` reader - 31:8\\]
RESERVE FIELD"]
pub type Res71R = crate :: FieldReader < u32 > ; # [doc = "Field `RES71` writer - 31:8\\]
RESERVE FIELD"]
pub type Res71W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res71 (& self) -> Res71R { Res71R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeerSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res71 (& mut self) -> Res71W < QeerSpec > { Res71W :: new (self , 8) } } # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeerSpec ; impl crate :: RegisterSpec for QeerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeer::R`](R) reader structure"]
impl crate :: Readable for QeerSpec { } # [doc = "`write(|w| ..)` method takes [`qeer::W`](W) writer structure"]
impl crate :: Writable for QeerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEER to value 0"]
impl crate :: Resettable for QeerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEECR (rw) register accessor: QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeecr`]
module"]
# [doc (alias = "QEECR")]
pub type Qeecr = crate :: Reg < qeecr :: QeecrSpec > ; # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod qeecr { # [doc = "Register `QEECR` reader"]
pub type R = crate :: R < QeecrSpec > ; # [doc = "Register `QEECR` writer"]
pub type W = crate :: W < QeecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES72` reader - 31:8\\]
RESERVE FIELD"]
pub type Res72R = crate :: FieldReader < u32 > ; # [doc = "Field `RES72` writer - 31:8\\]
RESERVE FIELD"]
pub type Res72W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res72 (& self) -> Res72R { Res72R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeecrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res72 (& mut self) -> Res72W < QeecrSpec > { Res72W :: new (self , 8) } } # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeecrSpec ; impl crate :: RegisterSpec for QeecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeecr::R`](R) reader structure"]
impl crate :: Readable for QeecrSpec { } # [doc = "`write(|w| ..)` method takes [`qeecr::W`](W) writer structure"]
impl crate :: Writable for QeecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEECR to value 0"]
impl crate :: Resettable for QeecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEESR (rw) register accessor: QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeesr`]
module"]
# [doc (alias = "QEESR")]
pub type Qeesr = crate :: Reg < qeesr :: QeesrSpec > ; # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
pub mod qeesr { # [doc = "Register `QEESR` reader"]
pub type R = crate :: R < QeesrSpec > ; # [doc = "Register `QEESR` writer"]
pub type W = crate :: W < QeesrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES73` reader - 31:8\\]
RESERVE FIELD"]
pub type Res73R = crate :: FieldReader < u32 > ; # [doc = "Field `RES73` writer - 31:8\\]
RESERVE FIELD"]
pub type Res73W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res73 (& self) -> Res73R { Res73R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeesrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeesrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeesrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeesrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeesrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeesrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeesrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeesrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res73 (& mut self) -> Res73W < QeesrSpec > { Res73W :: new (self , 8) } } # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeesrSpec ; impl crate :: RegisterSpec for QeesrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeesr::R`](R) reader structure"]
impl crate :: Readable for QeesrSpec { } # [doc = "`write(|w| ..)` method takes [`qeesr::W`](W) writer structure"]
impl crate :: Writable for QeesrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEESR to value 0"]
impl crate :: Resettable for QeesrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSER (rw) register accessor: QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qser`]
module"]
# [doc (alias = "QSER")]
pub type Qser = crate :: Reg < qser :: QserSpec > ; # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod qser { # [doc = "Register `QSER` reader"]
pub type R = crate :: R < QserSpec > ; # [doc = "Register `QSER` writer"]
pub type W = crate :: W < QserSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES74` reader - 31:8\\]
RESERVE FIELD"]
pub type Res74R = crate :: FieldReader < u32 > ; # [doc = "Field `RES74` writer - 31:8\\]
RESERVE FIELD"]
pub type Res74W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res74 (& self) -> Res74R { Res74R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QserSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QserSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QserSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QserSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QserSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QserSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QserSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QserSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res74 (& mut self) -> Res74W < QserSpec > { Res74W :: new (self , 8) } } # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QserSpec ; impl crate :: RegisterSpec for QserSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qser::R`](R) reader structure"]
impl crate :: Readable for QserSpec { } # [doc = "`write(|w| ..)` method takes [`qser::W`](W) writer structure"]
impl crate :: Writable for QserSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSER to value 0"]
impl crate :: Resettable for QserSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSECR (rw) register accessor: QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsecr`]
module"]
# [doc (alias = "QSECR")]
pub type Qsecr = crate :: Reg < qsecr :: QsecrSpec > ; # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
pub mod qsecr { # [doc = "Register `QSECR` reader"]
pub type R = crate :: R < QsecrSpec > ; # [doc = "Register `QSECR` writer"]
pub type W = crate :: W < QsecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES75` reader - 31:8\\]
RESERVE FIELD"]
pub type Res75R = crate :: FieldReader < u32 > ; # [doc = "Field `RES75` writer - 31:8\\]
RESERVE FIELD"]
pub type Res75W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res75 (& self) -> Res75R { Res75R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QsecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QsecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QsecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QsecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QsecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QsecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QsecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QsecrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res75 (& mut self) -> Res75W < QsecrSpec > { Res75W :: new (self , 8) } } # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QsecrSpec ; impl crate :: RegisterSpec for QsecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsecr::R`](R) reader structure"]
impl crate :: Readable for QsecrSpec { } # [doc = "`write(|w| ..)` method takes [`qsecr::W`](W) writer structure"]
impl crate :: Writable for QsecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSECR to value 0"]
impl crate :: Resettable for QsecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ER_RN (rw) register accessor: Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@er_rn`]
module"]
# [doc (alias = "ER_RN")]
pub type ErRn = crate :: Reg < er_rn :: ErRnSpec > ; # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
pub mod er_rn { # [doc = "Register `ER_RN` reader"]
pub type R = crate :: R < ErRnSpec > ; # [doc = "Register `ER_RN` writer"]
pub type W = crate :: W < ErRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < ErRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < ErRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < ErRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < ErRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < ErRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < ErRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < ErRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < ErRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < ErRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < ErRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < ErRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < ErRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < ErRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < ErRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < ErRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < ErRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < ErRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < ErRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < ErRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < ErRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < ErRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < ErRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < ErRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < ErRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < ErRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < ErRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < ErRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < ErRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < ErRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < ErRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < ErRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < ErRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErRnSpec ; impl crate :: RegisterSpec for ErRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`er_rn::R`](R) reader structure"]
impl crate :: Readable for ErRnSpec { } # [doc = "`write(|w| ..)` method takes [`er_rn::W`](W) writer structure"]
impl crate :: Writable for ErRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ER_RN to value 0"]
impl crate :: Resettable for ErRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERH_RN (rw) register accessor: Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erh_rn`]
module"]
# [doc (alias = "ERH_RN")]
pub type ErhRn = crate :: Reg < erh_rn :: ErhRnSpec > ; # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
pub mod erh_rn { # [doc = "Register `ERH_RN` reader"]
pub type R = crate :: R < ErhRnSpec > ; # [doc = "Register `ERH_RN` writer"]
pub type W = crate :: W < ErhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < ErhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < ErhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < ErhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < ErhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < ErhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < ErhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < ErhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < ErhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < ErhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < ErhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < ErhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < ErhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < ErhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < ErhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < ErhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < ErhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < ErhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < ErhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < ErhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < ErhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < ErhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < ErhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < ErhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < ErhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < ErhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < ErhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < ErhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < ErhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < ErhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < ErhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < ErhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < ErhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErhRnSpec ; impl crate :: RegisterSpec for ErhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erh_rn::R`](R) reader structure"]
impl crate :: Readable for ErhRnSpec { } # [doc = "`write(|w| ..)` method takes [`erh_rn::W`](W) writer structure"]
impl crate :: Writable for ErhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERH_RN to value 0"]
impl crate :: Resettable for ErhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECR_RN (rw) register accessor: Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr_rn`]
module"]
# [doc (alias = "ECR_RN")]
pub type EcrRn = crate :: Reg < ecr_rn :: EcrRnSpec > ; # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecr_rn { # [doc = "Register `ECR_RN` reader"]
pub type R = crate :: R < EcrRnSpec > ; # [doc = "Register `ECR_RN` writer"]
pub type W = crate :: W < EcrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EcrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EcrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EcrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EcrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EcrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EcrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EcrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EcrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EcrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EcrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EcrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EcrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EcrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EcrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EcrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EcrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EcrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EcrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EcrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EcrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EcrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EcrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EcrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EcrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EcrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EcrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EcrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EcrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EcrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EcrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EcrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EcrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrRnSpec ; impl crate :: RegisterSpec for EcrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecr_rn::R`](R) reader structure"]
impl crate :: Readable for EcrRnSpec { } # [doc = "`write(|w| ..)` method takes [`ecr_rn::W`](W) writer structure"]
impl crate :: Writable for EcrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECR_RN to value 0"]
impl crate :: Resettable for EcrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECRH_RN (rw) register accessor: Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecrh_rn`]
module"]
# [doc (alias = "ECRH_RN")]
pub type EcrhRn = crate :: Reg < ecrh_rn :: EcrhRnSpec > ; # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecrh_rn { # [doc = "Register `ECRH_RN` reader"]
pub type R = crate :: R < EcrhRnSpec > ; # [doc = "Register `ECRH_RN` writer"]
pub type W = crate :: W < EcrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EcrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EcrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EcrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EcrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EcrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EcrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EcrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EcrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EcrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EcrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EcrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EcrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EcrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EcrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EcrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EcrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EcrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EcrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EcrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EcrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EcrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EcrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EcrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EcrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EcrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EcrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EcrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EcrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EcrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EcrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EcrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EcrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrhRnSpec ; impl crate :: RegisterSpec for EcrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecrh_rn::R`](R) reader structure"]
impl crate :: Readable for EcrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`ecrh_rn::W`](W) writer structure"]
impl crate :: Writable for EcrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECRH_RN to value 0"]
impl crate :: Resettable for EcrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESR_RN (rw) register accessor: Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr_rn`]
module"]
# [doc (alias = "ESR_RN")]
pub type EsrRn = crate :: Reg < esr_rn :: EsrRnSpec > ; # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
pub mod esr_rn { # [doc = "Register `ESR_RN` reader"]
pub type R = crate :: R < EsrRnSpec > ; # [doc = "Register `ESR_RN` writer"]
pub type W = crate :: W < EsrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EsrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EsrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EsrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EsrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EsrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EsrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EsrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EsrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EsrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EsrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EsrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EsrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EsrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EsrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EsrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EsrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EsrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EsrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EsrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EsrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EsrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EsrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EsrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EsrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EsrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EsrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EsrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EsrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EsrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EsrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EsrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EsrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrRnSpec ; impl crate :: RegisterSpec for EsrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esr_rn::R`](R) reader structure"]
impl crate :: Readable for EsrRnSpec { } # [doc = "`write(|w| ..)` method takes [`esr_rn::W`](W) writer structure"]
impl crate :: Writable for EsrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESR_RN to value 0"]
impl crate :: Resettable for EsrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESRH_RN (rw) register accessor: Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esrh_rn`]
module"]
# [doc (alias = "ESRH_RN")]
pub type EsrhRn = crate :: Reg < esrh_rn :: EsrhRnSpec > ; # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
pub mod esrh_rn { # [doc = "Register `ESRH_RN` reader"]
pub type R = crate :: R < EsrhRnSpec > ; # [doc = "Register `ESRH_RN` writer"]
pub type W = crate :: W < EsrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EsrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EsrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EsrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EsrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EsrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EsrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EsrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EsrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EsrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EsrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EsrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EsrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EsrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EsrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EsrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EsrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EsrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EsrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EsrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EsrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EsrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EsrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EsrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EsrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EsrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EsrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EsrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EsrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EsrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EsrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EsrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EsrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrhRnSpec ; impl crate :: RegisterSpec for EsrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esrh_rn::R`](R) reader structure"]
impl crate :: Readable for EsrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`esrh_rn::W`](W) writer structure"]
impl crate :: Writable for EsrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESRH_RN to value 0"]
impl crate :: Resettable for EsrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CER_RN (rw) register accessor: Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cer_rn`]
module"]
# [doc (alias = "CER_RN")]
pub type CerRn = crate :: Reg < cer_rn :: CerRnSpec > ; # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
pub mod cer_rn { # [doc = "Register `CER_RN` reader"]
pub type R = crate :: R < CerRnSpec > ; # [doc = "Register `CER_RN` writer"]
pub type W = crate :: W < CerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < CerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < CerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < CerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < CerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < CerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < CerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < CerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < CerRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < CerRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < CerRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < CerRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < CerRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < CerRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < CerRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < CerRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < CerRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < CerRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < CerRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < CerRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < CerRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < CerRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < CerRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < CerRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < CerRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < CerRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < CerRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < CerRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < CerRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < CerRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < CerRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < CerRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < CerRnSpec > { E31W :: new (self , 31) } } # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerRnSpec ; impl crate :: RegisterSpec for CerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cer_rn::R`](R) reader structure"]
impl crate :: Readable for CerRnSpec { } # [doc = "`write(|w| ..)` method takes [`cer_rn::W`](W) writer structure"]
impl crate :: Writable for CerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CER_RN to value 0"]
impl crate :: Resettable for CerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CERH_RN (rw) register accessor: Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cerh_rn`]
module"]
# [doc (alias = "CERH_RN")]
pub type CerhRn = crate :: Reg < cerh_rn :: CerhRnSpec > ; # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
pub mod cerh_rn { # [doc = "Register `CERH_RN` reader"]
pub type R = crate :: R < CerhRnSpec > ; # [doc = "Register `CERH_RN` writer"]
pub type W = crate :: W < CerhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < CerhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < CerhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < CerhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < CerhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < CerhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < CerhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < CerhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < CerhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < CerhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < CerhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < CerhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < CerhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < CerhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < CerhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < CerhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < CerhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < CerhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < CerhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < CerhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < CerhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < CerhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < CerhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < CerhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < CerhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < CerhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < CerhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < CerhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < CerhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < CerhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < CerhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < CerhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < CerhRnSpec > { E63W :: new (self , 31) } } # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerhRnSpec ; impl crate :: RegisterSpec for CerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cerh_rn::R`](R) reader structure"]
impl crate :: Readable for CerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`cerh_rn::W`](W) writer structure"]
impl crate :: Writable for CerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CERH_RN to value 0"]
impl crate :: Resettable for CerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EER_RN (rw) register accessor: Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eer_rn`]
module"]
# [doc (alias = "EER_RN")]
pub type EerRn = crate :: Reg < eer_rn :: EerRnSpec > ; # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eer_rn { # [doc = "Register `EER_RN` reader"]
pub type R = crate :: R < EerRnSpec > ; # [doc = "Register `EER_RN` writer"]
pub type W = crate :: W < EerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EerRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EerRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EerRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EerRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EerRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EerRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EerRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EerRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EerRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EerRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EerRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EerRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EerRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EerRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EerRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EerRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EerRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EerRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EerRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EerRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EerRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EerRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EerRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EerRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EerRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerRnSpec ; impl crate :: RegisterSpec for EerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eer_rn::R`](R) reader structure"]
impl crate :: Readable for EerRnSpec { } # [doc = "`write(|w| ..)` method takes [`eer_rn::W`](W) writer structure"]
impl crate :: Writable for EerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EER_RN to value 0"]
impl crate :: Resettable for EerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EERH_RN (rw) register accessor: Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eerh_rn`]
module"]
# [doc (alias = "EERH_RN")]
pub type EerhRn = crate :: Reg < eerh_rn :: EerhRnSpec > ; # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eerh_rn { # [doc = "Register `EERH_RN` reader"]
pub type R = crate :: R < EerhRnSpec > ; # [doc = "Register `EERH_RN` writer"]
pub type W = crate :: W < EerhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EerhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EerhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EerhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EerhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EerhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EerhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EerhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EerhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EerhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EerhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EerhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EerhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EerhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EerhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EerhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EerhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EerhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EerhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EerhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EerhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EerhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EerhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EerhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EerhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EerhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EerhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EerhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EerhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EerhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EerhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EerhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EerhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerhRnSpec ; impl crate :: RegisterSpec for EerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eerh_rn::R`](R) reader structure"]
impl crate :: Readable for EerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`eerh_rn::W`](W) writer structure"]
impl crate :: Writable for EerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EERH_RN to value 0"]
impl crate :: Resettable for EerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECR_RN (rw) register accessor: Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecr_rn`]
module"]
# [doc (alias = "EECR_RN")]
pub type EecrRn = crate :: Reg < eecr_rn :: EecrRnSpec > ; # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecr_rn { # [doc = "Register `EECR_RN` reader"]
pub type R = crate :: R < EecrRnSpec > ; # [doc = "Register `EECR_RN` writer"]
pub type W = crate :: W < EecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EecrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EecrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EecrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EecrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EecrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EecrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EecrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EecrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EecrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EecrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EecrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EecrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EecrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EecrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EecrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EecrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EecrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EecrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EecrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EecrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EecrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EecrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EecrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EecrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrRnSpec ; impl crate :: RegisterSpec for EecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecr_rn::R`](R) reader structure"]
impl crate :: Readable for EecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`eecr_rn::W`](W) writer structure"]
impl crate :: Writable for EecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECR_RN to value 0"]
impl crate :: Resettable for EecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECRH_RN (rw) register accessor: Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecrh_rn`]
module"]
# [doc (alias = "EECRH_RN")]
pub type EecrhRn = crate :: Reg < eecrh_rn :: EecrhRnSpec > ; # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecrh_rn { # [doc = "Register `EECRH_RN` reader"]
pub type R = crate :: R < EecrhRnSpec > ; # [doc = "Register `EECRH_RN` writer"]
pub type W = crate :: W < EecrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EecrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EecrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EecrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EecrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EecrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EecrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EecrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EecrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EecrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EecrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EecrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EecrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EecrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EecrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EecrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EecrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EecrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EecrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EecrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EecrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EecrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EecrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EecrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EecrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EecrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EecrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EecrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EecrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EecrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EecrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EecrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EecrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrhRnSpec ; impl crate :: RegisterSpec for EecrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecrh_rn::R`](R) reader structure"]
impl crate :: Readable for EecrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`eecrh_rn::W`](W) writer structure"]
impl crate :: Writable for EecrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECRH_RN to value 0"]
impl crate :: Resettable for EecrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESR_RN (rw) register accessor: Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesr_rn`]
module"]
# [doc (alias = "EESR_RN")]
pub type EesrRn = crate :: Reg < eesr_rn :: EesrRnSpec > ; # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesr_rn { # [doc = "Register `EESR_RN` reader"]
pub type R = crate :: R < EesrRnSpec > ; # [doc = "Register `EESR_RN` writer"]
pub type W = crate :: W < EesrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EesrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EesrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EesrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EesrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EesrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EesrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EesrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EesrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EesrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EesrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EesrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EesrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EesrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EesrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EesrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EesrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EesrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EesrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EesrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EesrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EesrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EesrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EesrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EesrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EesrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EesrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EesrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EesrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EesrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EesrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EesrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EesrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrRnSpec ; impl crate :: RegisterSpec for EesrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesr_rn::R`](R) reader structure"]
impl crate :: Readable for EesrRnSpec { } # [doc = "`write(|w| ..)` method takes [`eesr_rn::W`](W) writer structure"]
impl crate :: Writable for EesrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESR_RN to value 0"]
impl crate :: Resettable for EesrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESRH_RN (rw) register accessor: Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesrh_rn`]
module"]
# [doc (alias = "EESRH_RN")]
pub type EesrhRn = crate :: Reg < eesrh_rn :: EesrhRnSpec > ; # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesrh_rn { # [doc = "Register `EESRH_RN` reader"]
pub type R = crate :: R < EesrhRnSpec > ; # [doc = "Register `EESRH_RN` writer"]
pub type W = crate :: W < EesrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EesrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EesrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EesrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EesrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EesrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EesrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EesrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EesrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EesrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EesrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EesrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EesrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EesrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EesrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EesrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EesrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EesrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EesrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EesrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EesrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EesrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EesrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EesrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EesrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EesrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EesrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EesrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EesrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EesrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EesrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EesrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EesrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrhRnSpec ; impl crate :: RegisterSpec for EesrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesrh_rn::R`](R) reader structure"]
impl crate :: Readable for EesrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`eesrh_rn::W`](W) writer structure"]
impl crate :: Writable for EesrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESRH_RN to value 0"]
impl crate :: Resettable for EesrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SER_RN (rw) register accessor: Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ser_rn`]
module"]
# [doc (alias = "SER_RN")]
pub type SerRn = crate :: Reg < ser_rn :: SerRnSpec > ; # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod ser_rn { # [doc = "Register `SER_RN` reader"]
pub type R = crate :: R < SerRnSpec > ; # [doc = "Register `SER_RN` writer"]
pub type W = crate :: W < SerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SerRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SerRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SerRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SerRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SerRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SerRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SerRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SerRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SerRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SerRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SerRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SerRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SerRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SerRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SerRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SerRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SerRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SerRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SerRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SerRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SerRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SerRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SerRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SerRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SerRnSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerRnSpec ; impl crate :: RegisterSpec for SerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ser_rn::R`](R) reader structure"]
impl crate :: Readable for SerRnSpec { } # [doc = "`write(|w| ..)` method takes [`ser_rn::W`](W) writer structure"]
impl crate :: Writable for SerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SER_RN to value 0"]
impl crate :: Resettable for SerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SERH_RN (rw) register accessor: Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@serh_rn`]
module"]
# [doc (alias = "SERH_RN")]
pub type SerhRn = crate :: Reg < serh_rn :: SerhRnSpec > ; # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod serh_rn { # [doc = "Register `SERH_RN` reader"]
pub type R = crate :: R < SerhRnSpec > ; # [doc = "Register `SERH_RN` writer"]
pub type W = crate :: W < SerhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SerhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SerhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SerhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SerhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SerhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SerhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SerhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SerhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SerhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SerhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SerhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SerhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SerhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SerhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SerhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SerhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SerhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SerhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SerhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SerhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SerhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SerhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SerhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SerhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SerhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SerhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SerhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SerhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SerhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SerhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SerhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SerhRnSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerhRnSpec ; impl crate :: RegisterSpec for SerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`serh_rn::R`](R) reader structure"]
impl crate :: Readable for SerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`serh_rn::W`](W) writer structure"]
impl crate :: Writable for SerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SERH_RN to value 0"]
impl crate :: Resettable for SerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECR_RN (rw) register accessor: Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secr_rn`]
module"]
# [doc (alias = "SECR_RN")]
pub type SecrRn = crate :: Reg < secr_rn :: SecrRnSpec > ; # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
pub mod secr_rn { # [doc = "Register `SECR_RN` reader"]
pub type R = crate :: R < SecrRnSpec > ; # [doc = "Register `SECR_RN` writer"]
pub type W = crate :: W < SecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SecrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SecrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SecrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SecrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SecrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SecrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SecrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SecrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SecrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SecrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SecrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SecrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SecrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SecrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SecrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SecrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SecrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SecrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SecrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SecrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SecrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SecrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SecrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SecrRnSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrRnSpec ; impl crate :: RegisterSpec for SecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secr_rn::R`](R) reader structure"]
impl crate :: Readable for SecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`secr_rn::W`](W) writer structure"]
impl crate :: Writable for SecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECR_RN to value 0"]
impl crate :: Resettable for SecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECRH_RN (rw) register accessor: Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secrh_rn`]
module"]
# [doc (alias = "SECRH_RN")]
pub type SecrhRn = crate :: Reg < secrh_rn :: SecrhRnSpec > ; # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
pub mod secrh_rn { # [doc = "Register `SECRH_RN` reader"]
pub type R = crate :: R < SecrhRnSpec > ; # [doc = "Register `SECRH_RN` writer"]
pub type W = crate :: W < SecrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SecrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SecrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SecrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SecrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SecrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SecrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SecrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SecrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SecrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SecrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SecrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SecrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SecrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SecrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SecrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SecrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SecrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SecrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SecrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SecrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SecrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SecrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SecrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SecrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SecrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SecrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SecrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SecrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SecrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SecrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SecrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SecrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrhRnSpec ; impl crate :: RegisterSpec for SecrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secrh_rn::R`](R) reader structure"]
impl crate :: Readable for SecrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`secrh_rn::W`](W) writer structure"]
impl crate :: Writable for SecrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECRH_RN to value 0"]
impl crate :: Resettable for SecrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IER_RN (rw) register accessor: Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier_rn`]
module"]
# [doc (alias = "IER_RN")]
pub type IerRn = crate :: Reg < ier_rn :: IerRnSpec > ; # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
pub mod ier_rn { # [doc = "Register `IER_RN` reader"]
pub type R = crate :: R < IerRnSpec > ; # [doc = "Register `IER_RN` writer"]
pub type W = crate :: W < IerRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IerRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IerRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IerRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IerRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IerRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IerRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IerRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IerRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IerRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IerRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IerRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IerRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IerRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IerRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IerRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IerRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IerRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IerRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IerRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IerRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IerRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IerRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IerRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IerRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IerRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IerRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IerRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IerRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IerRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IerRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IerRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IerRnSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerRnSpec ; impl crate :: RegisterSpec for IerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier_rn::R`](R) reader structure"]
impl crate :: Readable for IerRnSpec { } # [doc = "`write(|w| ..)` method takes [`ier_rn::W`](W) writer structure"]
impl crate :: Writable for IerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IER_RN to value 0"]
impl crate :: Resettable for IerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IERH_RN (rw) register accessor: Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ierh_rn`]
module"]
# [doc (alias = "IERH_RN")]
pub type IerhRn = crate :: Reg < ierh_rn :: IerhRnSpec > ; # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
pub mod ierh_rn { # [doc = "Register `IERH_RN` reader"]
pub type R = crate :: R < IerhRnSpec > ; # [doc = "Register `IERH_RN` writer"]
pub type W = crate :: W < IerhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IerhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IerhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IerhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IerhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IerhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IerhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IerhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IerhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IerhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IerhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IerhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IerhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IerhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IerhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IerhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IerhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IerhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IerhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IerhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IerhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IerhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IerhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IerhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IerhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IerhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IerhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IerhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IerhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IerhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IerhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IerhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IerhRnSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerhRnSpec ; impl crate :: RegisterSpec for IerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ierh_rn::R`](R) reader structure"]
impl crate :: Readable for IerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`ierh_rn::W`](W) writer structure"]
impl crate :: Writable for IerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IERH_RN to value 0"]
impl crate :: Resettable for IerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECR_RN (rw) register accessor: Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecr_rn`]
module"]
# [doc (alias = "IECR_RN")]
pub type IecrRn = crate :: Reg < iecr_rn :: IecrRnSpec > ; # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecr_rn { # [doc = "Register `IECR_RN` reader"]
pub type R = crate :: R < IecrRnSpec > ; # [doc = "Register `IECR_RN` writer"]
pub type W = crate :: W < IecrRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IecrRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IecrRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IecrRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IecrRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IecrRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IecrRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IecrRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IecrRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IecrRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IecrRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IecrRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IecrRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IecrRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IecrRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IecrRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IecrRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IecrRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IecrRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IecrRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IecrRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IecrRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IecrRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IecrRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IecrRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IecrRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IecrRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IecrRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IecrRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IecrRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IecrRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IecrRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IecrRnSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrRnSpec ; impl crate :: RegisterSpec for IecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecr_rn::R`](R) reader structure"]
impl crate :: Readable for IecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`iecr_rn::W`](W) writer structure"]
impl crate :: Writable for IecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECR_RN to value 0"]
impl crate :: Resettable for IecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECRH_RN (rw) register accessor: Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecrh_rn`]
module"]
# [doc (alias = "IECRH_RN")]
pub type IecrhRn = crate :: Reg < iecrh_rn :: IecrhRnSpec > ; # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecrh_rn { # [doc = "Register `IECRH_RN` reader"]
pub type R = crate :: R < IecrhRnSpec > ; # [doc = "Register `IECRH_RN` writer"]
pub type W = crate :: W < IecrhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IecrhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IecrhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IecrhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IecrhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IecrhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IecrhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IecrhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IecrhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IecrhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IecrhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IecrhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IecrhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IecrhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IecrhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IecrhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IecrhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IecrhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IecrhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IecrhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IecrhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IecrhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IecrhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IecrhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IecrhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IecrhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IecrhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IecrhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IecrhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IecrhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IecrhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IecrhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IecrhRnSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrhRnSpec ; impl crate :: RegisterSpec for IecrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecrh_rn::R`](R) reader structure"]
impl crate :: Readable for IecrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`iecrh_rn::W`](W) writer structure"]
impl crate :: Writable for IecrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECRH_RN to value 0"]
impl crate :: Resettable for IecrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESR_RN (rw) register accessor: Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesr_rn`]
module"]
# [doc (alias = "IESR_RN")]
pub type IesrRn = crate :: Reg < iesr_rn :: IesrRnSpec > ; # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesr_rn { # [doc = "Register `IESR_RN` reader"]
pub type R = crate :: R < IesrRnSpec > ; # [doc = "Register `IESR_RN` writer"]
pub type W = crate :: W < IesrRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IesrRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IesrRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IesrRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IesrRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IesrRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IesrRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IesrRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IesrRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IesrRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IesrRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IesrRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IesrRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IesrRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IesrRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IesrRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IesrRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IesrRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IesrRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IesrRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IesrRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IesrRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IesrRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IesrRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IesrRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IesrRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IesrRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IesrRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IesrRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IesrRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IesrRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IesrRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IesrRnSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrRnSpec ; impl crate :: RegisterSpec for IesrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesr_rn::R`](R) reader structure"]
impl crate :: Readable for IesrRnSpec { } # [doc = "`write(|w| ..)` method takes [`iesr_rn::W`](W) writer structure"]
impl crate :: Writable for IesrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESR_RN to value 0"]
impl crate :: Resettable for IesrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESRH_RN (rw) register accessor: Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesrh_rn`]
module"]
# [doc (alias = "IESRH_RN")]
pub type IesrhRn = crate :: Reg < iesrh_rn :: IesrhRnSpec > ; # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesrh_rn { # [doc = "Register `IESRH_RN` reader"]
pub type R = crate :: R < IesrhRnSpec > ; # [doc = "Register `IESRH_RN` writer"]
pub type W = crate :: W < IesrhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IesrhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IesrhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IesrhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IesrhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IesrhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IesrhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IesrhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IesrhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IesrhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IesrhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IesrhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IesrhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IesrhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IesrhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IesrhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IesrhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IesrhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IesrhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IesrhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IesrhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IesrhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IesrhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IesrhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IesrhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IesrhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IesrhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IesrhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IesrhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IesrhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IesrhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IesrhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IesrhRnSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrhRnSpec ; impl crate :: RegisterSpec for IesrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesrh_rn::R`](R) reader structure"]
impl crate :: Readable for IesrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`iesrh_rn::W`](W) writer structure"]
impl crate :: Writable for IesrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESRH_RN to value 0"]
impl crate :: Resettable for IesrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPR_RN (rw) register accessor: Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipr_rn`]
module"]
# [doc (alias = "IPR_RN")]
pub type IprRn = crate :: Reg < ipr_rn :: IprRnSpec > ; # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
pub mod ipr_rn { # [doc = "Register `IPR_RN` reader"]
pub type R = crate :: R < IprRnSpec > ; # [doc = "Register `IPR_RN` writer"]
pub type W = crate :: W < IprRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IprRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IprRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IprRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IprRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IprRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IprRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IprRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IprRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IprRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IprRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IprRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IprRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IprRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IprRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IprRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IprRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IprRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IprRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IprRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IprRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IprRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IprRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IprRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IprRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IprRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IprRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IprRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IprRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IprRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IprRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IprRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IprRnSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprRnSpec ; impl crate :: RegisterSpec for IprRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipr_rn::R`](R) reader structure"]
impl crate :: Readable for IprRnSpec { } # [doc = "`write(|w| ..)` method takes [`ipr_rn::W`](W) writer structure"]
impl crate :: Writable for IprRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPR_RN to value 0"]
impl crate :: Resettable for IprRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPRH_RN (rw) register accessor: Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iprh_rn`]
module"]
# [doc (alias = "IPRH_RN")]
pub type IprhRn = crate :: Reg < iprh_rn :: IprhRnSpec > ; # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
pub mod iprh_rn { # [doc = "Register `IPRH_RN` reader"]
pub type R = crate :: R < IprhRnSpec > ; # [doc = "Register `IPRH_RN` writer"]
pub type W = crate :: W < IprhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IprhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IprhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IprhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IprhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IprhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IprhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IprhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IprhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IprhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IprhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IprhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IprhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IprhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IprhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IprhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IprhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IprhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IprhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IprhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IprhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IprhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IprhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IprhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IprhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IprhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IprhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IprhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IprhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IprhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IprhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IprhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IprhRnSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprhRnSpec ; impl crate :: RegisterSpec for IprhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iprh_rn::R`](R) reader structure"]
impl crate :: Readable for IprhRnSpec { } # [doc = "`write(|w| ..)` method takes [`iprh_rn::W`](W) writer structure"]
impl crate :: Writable for IprhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPRH_RN to value 0"]
impl crate :: Resettable for IprhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICR_RN (rw) register accessor: Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr_rn`]
module"]
# [doc (alias = "ICR_RN")]
pub type IcrRn = crate :: Reg < icr_rn :: IcrRnSpec > ; # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icr_rn { # [doc = "Register `ICR_RN` reader"]
pub type R = crate :: R < IcrRnSpec > ; # [doc = "Register `ICR_RN` writer"]
pub type W = crate :: W < IcrRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IcrRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IcrRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IcrRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IcrRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IcrRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IcrRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IcrRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IcrRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IcrRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IcrRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IcrRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IcrRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IcrRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IcrRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IcrRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IcrRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IcrRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IcrRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IcrRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IcrRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IcrRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IcrRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IcrRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IcrRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IcrRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IcrRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IcrRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IcrRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IcrRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IcrRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IcrRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IcrRnSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrRnSpec ; impl crate :: RegisterSpec for IcrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icr_rn::R`](R) reader structure"]
impl crate :: Readable for IcrRnSpec { } # [doc = "`write(|w| ..)` method takes [`icr_rn::W`](W) writer structure"]
impl crate :: Writable for IcrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICR_RN to value 0"]
impl crate :: Resettable for IcrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICRH_RN (rw) register accessor: Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icrh_rn`]
module"]
# [doc (alias = "ICRH_RN")]
pub type IcrhRn = crate :: Reg < icrh_rn :: IcrhRnSpec > ; # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icrh_rn { # [doc = "Register `ICRH_RN` reader"]
pub type R = crate :: R < IcrhRnSpec > ; # [doc = "Register `ICRH_RN` writer"]
pub type W = crate :: W < IcrhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IcrhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IcrhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IcrhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IcrhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IcrhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IcrhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IcrhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IcrhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IcrhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IcrhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IcrhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IcrhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IcrhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IcrhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IcrhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IcrhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IcrhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IcrhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IcrhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IcrhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IcrhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IcrhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IcrhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IcrhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IcrhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IcrhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IcrhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IcrhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IcrhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IcrhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IcrhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IcrhRnSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrhRnSpec ; impl crate :: RegisterSpec for IcrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icrh_rn::R`](R) reader structure"]
impl crate :: Readable for IcrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`icrh_rn::W`](W) writer structure"]
impl crate :: Writable for IcrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICRH_RN to value 0"]
impl crate :: Resettable for IcrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IEVAL_RN (rw) register accessor: Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ieval_rn`]
module"]
# [doc (alias = "IEVAL_RN")]
pub type IevalRn = crate :: Reg < ieval_rn :: IevalRnSpec > ; # [doc = "Interrupt Eval Register"]
pub mod ieval_rn { # [doc = "Register `IEVAL_RN` reader"]
pub type R = crate :: R < IevalRnSpec > ; # [doc = "Register `IEVAL_RN` writer"]
pub type W = crate :: W < IevalRnSpec > ; # [doc = "Field `EVAL` reader - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalR = crate :: BitReader ; # [doc = "Field `EVAL` writer - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET` reader - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetR = crate :: BitReader ; # [doc = "Field `SET` writer - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES76` reader - 31:2\\]
RESERVE FIELD"]
pub type Res76R = crate :: FieldReader < u32 > ; # [doc = "Field `RES76` writer - 31:2\\]
RESERVE FIELD"]
pub type Res76W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
pub fn eval (& self) -> EvalR { EvalR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res76 (& self) -> Res76R { Res76R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
# [must_use]
pub fn eval (& mut self) -> EvalW < IevalRnSpec > { EvalW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < IevalRnSpec > { SetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res76 (& mut self) -> Res76W < IevalRnSpec > { Res76W :: new (self , 2) } } # [doc = "Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IevalRnSpec ; impl crate :: RegisterSpec for IevalRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ieval_rn::R`](R) reader structure"]
impl crate :: Readable for IevalRnSpec { } # [doc = "`write(|w| ..)` method takes [`ieval_rn::W`](W) writer structure"]
impl crate :: Writable for IevalRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IEVAL_RN to value 0"]
impl crate :: Resettable for IevalRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QER_RN (rw) register accessor: QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qer_rn`]
module"]
# [doc (alias = "QER_RN")]
pub type QerRn = crate :: Reg < qer_rn :: QerRnSpec > ; # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
pub mod qer_rn { # [doc = "Register `QER_RN` reader"]
pub type R = crate :: R < QerRnSpec > ; # [doc = "Register `QER_RN` writer"]
pub type W = crate :: W < QerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES77` reader - 31:8\\]
RESERVE FIELD"]
pub type Res77R = crate :: FieldReader < u32 > ; # [doc = "Field `RES77` writer - 31:8\\]
RESERVE FIELD"]
pub type Res77W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res77 (& self) -> Res77R { Res77R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QerRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res77 (& mut self) -> Res77W < QerRnSpec > { Res77W :: new (self , 8) } } # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QerRnSpec ; impl crate :: RegisterSpec for QerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qer_rn::R`](R) reader structure"]
impl crate :: Readable for QerRnSpec { } # [doc = "`write(|w| ..)` method takes [`qer_rn::W`](W) writer structure"]
impl crate :: Writable for QerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QER_RN to value 0"]
impl crate :: Resettable for QerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEER_RN (rw) register accessor: QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeer_rn`]
module"]
# [doc (alias = "QEER_RN")]
pub type QeerRn = crate :: Reg < qeer_rn :: QeerRnSpec > ; # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
pub mod qeer_rn { # [doc = "Register `QEER_RN` reader"]
pub type R = crate :: R < QeerRnSpec > ; # [doc = "Register `QEER_RN` writer"]
pub type W = crate :: W < QeerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES78` reader - 31:8\\]
RESERVE FIELD"]
pub type Res78R = crate :: FieldReader < u32 > ; # [doc = "Field `RES78` writer - 31:8\\]
RESERVE FIELD"]
pub type Res78W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res78 (& self) -> Res78R { Res78R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeerRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res78 (& mut self) -> Res78W < QeerRnSpec > { Res78W :: new (self , 8) } } # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeerRnSpec ; impl crate :: RegisterSpec for QeerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeer_rn::R`](R) reader structure"]
impl crate :: Readable for QeerRnSpec { } # [doc = "`write(|w| ..)` method takes [`qeer_rn::W`](W) writer structure"]
impl crate :: Writable for QeerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEER_RN to value 0"]
impl crate :: Resettable for QeerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEECR_RN (rw) register accessor: QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeecr_rn`]
module"]
# [doc (alias = "QEECR_RN")]
pub type QeecrRn = crate :: Reg < qeecr_rn :: QeecrRnSpec > ; # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod qeecr_rn { # [doc = "Register `QEECR_RN` reader"]
pub type R = crate :: R < QeecrRnSpec > ; # [doc = "Register `QEECR_RN` writer"]
pub type W = crate :: W < QeecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES79` reader - 31:8\\]
RESERVE FIELD"]
pub type Res79R = crate :: FieldReader < u32 > ; # [doc = "Field `RES79` writer - 31:8\\]
RESERVE FIELD"]
pub type Res79W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res79 (& self) -> Res79R { Res79R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res79 (& mut self) -> Res79W < QeecrRnSpec > { Res79W :: new (self , 8) } } # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeecrRnSpec ; impl crate :: RegisterSpec for QeecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeecr_rn::R`](R) reader structure"]
impl crate :: Readable for QeecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`qeecr_rn::W`](W) writer structure"]
impl crate :: Writable for QeecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEECR_RN to value 0"]
impl crate :: Resettable for QeecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEESR_RN (rw) register accessor: QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeesr_rn`]
module"]
# [doc (alias = "QEESR_RN")]
pub type QeesrRn = crate :: Reg < qeesr_rn :: QeesrRnSpec > ; # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
pub mod qeesr_rn { # [doc = "Register `QEESR_RN` reader"]
pub type R = crate :: R < QeesrRnSpec > ; # [doc = "Register `QEESR_RN` writer"]
pub type W = crate :: W < QeesrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES80` reader - 31:8\\]
RESERVE FIELD"]
pub type Res80R = crate :: FieldReader < u32 > ; # [doc = "Field `RES80` writer - 31:8\\]
RESERVE FIELD"]
pub type Res80W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res80 (& self) -> Res80R { Res80R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeesrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeesrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeesrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeesrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeesrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeesrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeesrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeesrRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res80 (& mut self) -> Res80W < QeesrRnSpec > { Res80W :: new (self , 8) } } # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeesrRnSpec ; impl crate :: RegisterSpec for QeesrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeesr_rn::R`](R) reader structure"]
impl crate :: Readable for QeesrRnSpec { } # [doc = "`write(|w| ..)` method takes [`qeesr_rn::W`](W) writer structure"]
impl crate :: Writable for QeesrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEESR_RN to value 0"]
impl crate :: Resettable for QeesrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSER_RN (rw) register accessor: QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qser_rn`]
module"]
# [doc (alias = "QSER_RN")]
pub type QserRn = crate :: Reg < qser_rn :: QserRnSpec > ; # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod qser_rn { # [doc = "Register `QSER_RN` reader"]
pub type R = crate :: R < QserRnSpec > ; # [doc = "Register `QSER_RN` writer"]
pub type W = crate :: W < QserRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES81` reader - 31:8\\]
RESERVE FIELD"]
pub type Res81R = crate :: FieldReader < u32 > ; # [doc = "Field `RES81` writer - 31:8\\]
RESERVE FIELD"]
pub type Res81W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res81 (& self) -> Res81R { Res81R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QserRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QserRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QserRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QserRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QserRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QserRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QserRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QserRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res81 (& mut self) -> Res81W < QserRnSpec > { Res81W :: new (self , 8) } } # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QserRnSpec ; impl crate :: RegisterSpec for QserRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qser_rn::R`](R) reader structure"]
impl crate :: Readable for QserRnSpec { } # [doc = "`write(|w| ..)` method takes [`qser_rn::W`](W) writer structure"]
impl crate :: Writable for QserRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSER_RN to value 0"]
impl crate :: Resettable for QserRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSECR_RN (rw) register accessor: QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsecr_rn`]
module"]
# [doc (alias = "QSECR_RN")]
pub type QsecrRn = crate :: Reg < qsecr_rn :: QsecrRnSpec > ; # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
pub mod qsecr_rn { # [doc = "Register `QSECR_RN` reader"]
pub type R = crate :: R < QsecrRnSpec > ; # [doc = "Register `QSECR_RN` writer"]
pub type W = crate :: W < QsecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES82` reader - 31:8\\]
RESERVE FIELD"]
pub type Res82R = crate :: FieldReader < u32 > ; # [doc = "Field `RES82` writer - 31:8\\]
RESERVE FIELD"]
pub type Res82W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res82 (& self) -> Res82R { Res82R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QsecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QsecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QsecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QsecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QsecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QsecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QsecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QsecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res82 (& mut self) -> Res82W < QsecrRnSpec > { Res82W :: new (self , 8) } } # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QsecrRnSpec ; impl crate :: RegisterSpec for QsecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsecr_rn::R`](R) reader structure"]
impl crate :: Readable for QsecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`qsecr_rn::W`](W) writer structure"]
impl crate :: Writable for QsecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSECR_RN to value 0"]
impl crate :: Resettable for QsecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "OPT (rw) register accessor: Options Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`opt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@opt`]
module"]
# [doc (alias = "OPT")]
pub type Opt = crate :: Reg < opt :: OptSpec > ; # [doc = "Options Parameter"]
pub mod opt { # [doc = "Register `OPT` reader"]
pub type R = crate :: R < OptSpec > ; # [doc = "Register `OPT` writer"]
pub type W = crate :: W < OptSpec > ; # [doc = "Field `SAM` reader - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SamR = crate :: BitReader ; # [doc = "Field `SAM` writer - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DAM` reader - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DamR = crate :: BitReader ; # [doc = "Field `DAM` writer - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SYNCDIM` reader - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
pub type SyncdimR = crate :: BitReader ; # [doc = "Field `SYNCDIM` writer - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
pub type SyncdimW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STATIC` reader - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
pub type StaticR = crate :: BitReader ; # [doc = "Field `STATIC` writer - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
pub type StaticW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES85` reader - 7:4\\]
RESERVE FIELD"]
pub type Res85R = crate :: FieldReader ; # [doc = "Field `RES85` writer - 7:4\\]
RESERVE FIELD"]
pub type Res85W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `FWID` reader - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
pub type FwidR = crate :: FieldReader ; # [doc = "Field `FWID` writer - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
pub type FwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TCCMODE` reader - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
pub type TccmodeR = crate :: BitReader ; # [doc = "Field `TCCMODE` writer - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
pub type TccmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCC` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
pub type TccR = crate :: FieldReader ; # [doc = "Field `TCC` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
pub type TccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RES84` reader - 18:18\\]
RESERVE FIELD"]
pub type Res84R = crate :: BitReader ; # [doc = "Field `RES84` writer - 18:18\\]
RESERVE FIELD"]
pub type Res84W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WIMODE` reader - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
pub type WimodeR = crate :: BitReader ; # [doc = "Field `WIMODE` writer - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
pub type WimodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCINTEN` reader - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type TcintenR = crate :: BitReader ; # [doc = "Field `TCINTEN` writer - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type TcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ITCINTEN` reader - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type ItcintenR = crate :: BitReader ; # [doc = "Field `ITCINTEN` writer - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type ItcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCCHEN` reader - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
pub type TcchenR = crate :: BitReader ; # [doc = "Field `TCCHEN` writer - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
pub type TcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ITCCHEN` reader - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
pub type ItcchenR = crate :: BitReader ; # [doc = "Field `ITCCHEN` writer - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
pub type ItcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PRIVID` reader - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
pub type PrividR = crate :: FieldReader ; # [doc = "Field `PRIVID` writer - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
pub type PrividW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RES83` reader - 30:28\\]
RESERVE FIELD"]
pub type Res83R = crate :: FieldReader ; # [doc = "Field `RES83` writer - 30:28\\]
RESERVE FIELD"]
pub type Res83W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PRIV` reader - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
pub type PrivR = crate :: BitReader ; # [doc = "Field `PRIV` writer - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
pub type PrivW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn sam (& self) -> SamR { SamR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn dam (& self) -> DamR { DamR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
# [inline (always)]
pub fn syncdim (& self) -> SyncdimR { SyncdimR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
# [inline (always)]
pub fn static_ (& self) -> StaticR { StaticR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res85 (& self) -> Res85R { Res85R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
# [inline (always)]
pub fn fwid (& self) -> FwidR { FwidR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
# [inline (always)]
pub fn tccmode (& self) -> TccmodeR { TccmodeR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
# [inline (always)]
pub fn tcc (& self) -> TccR { TccR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 18 - 18:18\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res84 (& self) -> Res84R { Res84R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
# [inline (always)]
pub fn wimode (& self) -> WimodeR { WimodeR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
pub fn tcinten (& self) -> TcintenR { TcintenR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
pub fn itcinten (& self) -> ItcintenR { ItcintenR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn tcchen (& self) -> TcchenR { TcchenR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
# [inline (always)]
pub fn itcchen (& self) -> ItcchenR { ItcchenR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:27 - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
# [inline (always)]
pub fn privid (& self) -> PrividR { PrividR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:30 - 30:28\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res83 (& self) -> Res83R { Res83R :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
# [inline (always)]
pub fn priv_ (& self) -> PrivR { PrivR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn sam (& mut self) -> SamW < OptSpec > { SamW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn dam (& mut self) -> DamW < OptSpec > { DamW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
# [inline (always)]
# [must_use]
pub fn syncdim (& mut self) -> SyncdimW < OptSpec > { SyncdimW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
# [inline (always)]
# [must_use]
pub fn static_ (& mut self) -> StaticW < OptSpec > { StaticW :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res85 (& mut self) -> Res85W < OptSpec > { Res85W :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
# [inline (always)]
# [must_use]
pub fn fwid (& mut self) -> FwidW < OptSpec > { FwidW :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
# [inline (always)]
# [must_use]
pub fn tccmode (& mut self) -> TccmodeW < OptSpec > { TccmodeW :: new (self , 11) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
# [inline (always)]
# [must_use]
pub fn tcc (& mut self) -> TccW < OptSpec > { TccW :: new (self , 12) } # [doc = "Bit 18 - 18:18\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res84 (& mut self) -> Res84W < OptSpec > { Res84W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
# [inline (always)]
# [must_use]
pub fn wimode (& mut self) -> WimodeW < OptSpec > { WimodeW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
# [must_use]
pub fn tcinten (& mut self) -> TcintenW < OptSpec > { TcintenW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
# [must_use]
pub fn itcinten (& mut self) -> ItcintenW < OptSpec > { ItcintenW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn tcchen (& mut self) -> TcchenW < OptSpec > { TcchenW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn itcchen (& mut self) -> ItcchenW < OptSpec > { ItcchenW :: new (self , 23) } # [doc = "Bits 24:27 - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
# [inline (always)]
# [must_use]
pub fn privid (& mut self) -> PrividW < OptSpec > { PrividW :: new (self , 24) } # [doc = "Bits 28:30 - 30:28\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res83 (& mut self) -> Res83W < OptSpec > { Res83W :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
# [inline (always)]
# [must_use]
pub fn priv_ (& mut self) -> PrivW < OptSpec > { PrivW :: new (self , 31) } } # [doc = "Options Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`opt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OptSpec ; impl crate :: RegisterSpec for OptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`opt::R`](R) reader structure"]
impl crate :: Readable for OptSpec { } # [doc = "`write(|w| ..)` method takes [`opt::W`](W) writer structure"]
impl crate :: Writable for OptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OPT to value 0"]
impl crate :: Resettable for OptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SRC (rw) register accessor: Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@src`]
module"]
# [doc (alias = "SRC")]
pub type Src = crate :: Reg < src :: SrcSpec > ; # [doc = "Source Address"]
pub mod src { # [doc = "Register `SRC` reader"]
pub type R = crate :: R < SrcSpec > ; # [doc = "Register `SRC` writer"]
pub type W = crate :: W < SrcSpec > ; # [doc = "Field `SRC` reader - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type SrcR = crate :: FieldReader < u32 > ; # [doc = "Field `SRC` writer - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type SrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
pub fn src (& self) -> SrcR { SrcR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
# [must_use]
pub fn src (& mut self) -> SrcW < SrcSpec > { SrcW :: new (self , 0) } } # [doc = "Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrcSpec ; impl crate :: RegisterSpec for SrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`src::R`](R) reader structure"]
impl crate :: Readable for SrcSpec { } # [doc = "`write(|w| ..)` method takes [`src::W`](W) writer structure"]
impl crate :: Writable for SrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SRC to value 0"]
impl crate :: Resettable for SrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ABCNT (rw) register accessor: A and B byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`abcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abcnt`]
module"]
# [doc (alias = "ABCNT")]
pub type Abcnt = crate :: Reg < abcnt :: AbcntSpec > ; # [doc = "A and B byte count"]
pub mod abcnt { # [doc = "Register `ABCNT` reader"]
pub type R = crate :: R < AbcntSpec > ; # [doc = "Register `ABCNT` writer"]
pub type W = crate :: W < AbcntSpec > ; # [doc = "Field `ACNT` reader - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
pub type AcntR = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT` writer - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
pub type AcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BCNT` reader - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
pub type BcntR = crate :: FieldReader < u16 > ; # [doc = "Field `BCNT` writer - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
pub type BcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
# [inline (always)]
pub fn acnt (& self) -> AcntR { AcntR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
# [inline (always)]
pub fn bcnt (& self) -> BcntR { BcntR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
# [inline (always)]
# [must_use]
pub fn acnt (& mut self) -> AcntW < AbcntSpec > { AcntW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
# [inline (always)]
# [must_use]
pub fn bcnt (& mut self) -> BcntW < AbcntSpec > { BcntW :: new (self , 16) } } # [doc = "A and B byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`abcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AbcntSpec ; impl crate :: RegisterSpec for AbcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`abcnt::R`](R) reader structure"]
impl crate :: Readable for AbcntSpec { } # [doc = "`write(|w| ..)` method takes [`abcnt::W`](W) writer structure"]
impl crate :: Writable for AbcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ABCNT to value 0"]
impl crate :: Resettable for AbcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DST (rw) register accessor: Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dst`]
module"]
# [doc (alias = "DST")]
pub type Dst = crate :: Reg < dst :: DstSpec > ; # [doc = "Destination Address"]
pub mod dst { # [doc = "Register `DST` reader"]
pub type R = crate :: R < DstSpec > ; # [doc = "Register `DST` writer"]
pub type W = crate :: W < DstSpec > ; # [doc = "Field `DST` reader - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type DstR = crate :: FieldReader < u32 > ; # [doc = "Field `DST` writer - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type DstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
pub fn dst (& self) -> DstR { DstR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
# [must_use]
pub fn dst (& mut self) -> DstW < DstSpec > { DstW :: new (self , 0) } } # [doc = "Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DstSpec ; impl crate :: RegisterSpec for DstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dst::R`](R) reader structure"]
impl crate :: Readable for DstSpec { } # [doc = "`write(|w| ..)` method takes [`dst::W`](W) writer structure"]
impl crate :: Writable for DstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DST to value 0"]
impl crate :: Resettable for DstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BIDX (rw) register accessor: Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`bidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bidx`]
module"]
# [doc (alias = "BIDX")]
pub type Bidx = crate :: Reg < bidx :: BidxSpec > ; # [doc = "Register description is not available"]
pub mod bidx { # [doc = "Register `BIDX` reader"]
pub type R = crate :: R < BidxSpec > ; # [doc = "Register `BIDX` writer"]
pub type W = crate :: W < BidxSpec > ; # [doc = "Field `SBIDX` reader - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
pub type SbidxR = crate :: FieldReader < u16 > ; # [doc = "Field `SBIDX` writer - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
pub type SbidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DBIDX` reader - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
pub type DbidxR = crate :: FieldReader < u16 > ; # [doc = "Field `DBIDX` writer - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
pub type DbidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
# [inline (always)]
pub fn sbidx (& self) -> SbidxR { SbidxR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
# [inline (always)]
pub fn dbidx (& self) -> DbidxR { DbidxR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
# [inline (always)]
# [must_use]
pub fn sbidx (& mut self) -> SbidxW < BidxSpec > { SbidxW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
# [inline (always)]
# [must_use]
pub fn dbidx (& mut self) -> DbidxW < BidxSpec > { DbidxW :: new (self , 16) } } # [doc = "Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`bidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BidxSpec ; impl crate :: RegisterSpec for BidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bidx::R`](R) reader structure"]
impl crate :: Readable for BidxSpec { } # [doc = "`write(|w| ..)` method takes [`bidx::W`](W) writer structure"]
impl crate :: Writable for BidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BIDX to value 0"]
impl crate :: Resettable for BidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LNK (rw) register accessor: Link and Reload parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`lnk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lnk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lnk`]
module"]
# [doc (alias = "LNK")]
pub type Lnk = crate :: Reg < lnk :: LnkSpec > ; # [doc = "Link and Reload parameters"]
pub mod lnk { # [doc = "Register `LNK` reader"]
pub type R = crate :: R < LnkSpec > ; # [doc = "Register `LNK` writer"]
pub type W = crate :: W < LnkSpec > ; # [doc = "Field `LINK` reader - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
pub type LinkR = crate :: FieldReader < u16 > ; # [doc = "Field `LINK` writer - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
pub type LinkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BCNTRLD` reader - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
pub type BcntrldR = crate :: FieldReader < u16 > ; # [doc = "Field `BCNTRLD` writer - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
pub type BcntrldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
# [inline (always)]
pub fn link (& self) -> LinkR { LinkR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
# [inline (always)]
pub fn bcntrld (& self) -> BcntrldR { BcntrldR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
# [inline (always)]
# [must_use]
pub fn link (& mut self) -> LinkW < LnkSpec > { LinkW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
# [inline (always)]
# [must_use]
pub fn bcntrld (& mut self) -> BcntrldW < LnkSpec > { BcntrldW :: new (self , 16) } } # [doc = "Link and Reload parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`lnk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lnk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LnkSpec ; impl crate :: RegisterSpec for LnkSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`lnk::R`](R) reader structure"]
impl crate :: Readable for LnkSpec { } # [doc = "`write(|w| ..)` method takes [`lnk::W`](W) writer structure"]
impl crate :: Writable for LnkSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LNK to value 0"]
impl crate :: Resettable for LnkSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CIDX (rw) register accessor: Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`cidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cidx`]
module"]
# [doc (alias = "CIDX")]
pub type Cidx = crate :: Reg < cidx :: CidxSpec > ; # [doc = "Register description is not available"]
pub mod cidx { # [doc = "Register `CIDX` reader"]
pub type R = crate :: R < CidxSpec > ; # [doc = "Register `CIDX` writer"]
pub type W = crate :: W < CidxSpec > ; # [doc = "Field `SCIDX` reader - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
pub type ScidxR = crate :: FieldReader < u16 > ; # [doc = "Field `SCIDX` writer - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
pub type ScidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DCIDX` reader - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
pub type DcidxR = crate :: FieldReader < u16 > ; # [doc = "Field `DCIDX` writer - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
pub type DcidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
# [inline (always)]
pub fn scidx (& self) -> ScidxR { ScidxR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
# [inline (always)]
pub fn dcidx (& self) -> DcidxR { DcidxR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
# [inline (always)]
# [must_use]
pub fn scidx (& mut self) -> ScidxW < CidxSpec > { ScidxW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
# [inline (always)]
# [must_use]
pub fn dcidx (& mut self) -> DcidxW < CidxSpec > { DcidxW :: new (self , 16) } } # [doc = "Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`cidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CidxSpec ; impl crate :: RegisterSpec for CidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cidx::R`](R) reader structure"]
impl crate :: Readable for CidxSpec { } # [doc = "`write(|w| ..)` method takes [`cidx::W`](W) writer structure"]
impl crate :: Writable for CidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CIDX to value 0"]
impl crate :: Resettable for CidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCNT (rw) register accessor: C byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`ccnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccnt`]
module"]
# [doc (alias = "CCNT")]
pub type Ccnt = crate :: Reg < ccnt :: CcntSpec > ; # [doc = "C byte count"]
pub mod ccnt { # [doc = "Register `CCNT` reader"]
pub type R = crate :: R < CcntSpec > ; # [doc = "Register `CCNT` writer"]
pub type W = crate :: W < CcntSpec > ; # [doc = "Field `CCNT` reader - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
pub type CcntR = crate :: FieldReader < u16 > ; # [doc = "Field `CCNT` writer - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
pub type CcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `RES86` reader - 31:16\\]
RESERVE FIELD"]
pub type Res86R = crate :: FieldReader < u16 > ; # [doc = "Field `RES86` writer - 31:16\\]
RESERVE FIELD"]
pub type Res86W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
# [inline (always)]
pub fn ccnt (& self) -> CcntR { CcntR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res86 (& self) -> Res86R { Res86R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
# [inline (always)]
# [must_use]
pub fn ccnt (& mut self) -> CcntW < CcntSpec > { CcntW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res86 (& mut self) -> Res86W < CcntSpec > { Res86W :: new (self , 16) } } # [doc = "C byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`ccnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcntSpec ; impl crate :: RegisterSpec for CcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccnt::R`](R) reader structure"]
impl crate :: Readable for CcntSpec { } # [doc = "`write(|w| ..)` method takes [`ccnt::W`](W) writer structure"]
impl crate :: Writable for CcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCNT to value 0"]
impl crate :: Resettable for CcntSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "TPCC"]
pub struct TpccA { _marker : PhantomData < * const () > } unsafe impl Send for TpccA { } impl TpccA { # [doc = r"Pointer to the register block"]
pub const PTR : * const tpcc_a :: RegisterBlock = 0x5600_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tpcc_a :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TpccA { type Target = tpcc_a :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TpccA { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TpccA") . finish () } } # [doc = "TPCC"]
pub mod tpcc_a { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , cccfg : Cccfg , _reserved2 : [u8 ; 0x01f8]
, qchmapn : Qchmapn , _reserved3 : [u8 ; 0x3c]
, dmaqnumn : Dmaqnumn , _reserved4 : [u8 ; 0x1c]
, qdmaqnum : Qdmaqnum , _reserved5 : [u8 ; 0x1c]
, quetcmap : Quetcmap , quepri : Quepri , _reserved7 : [u8 ; 0x78]
, emr : Emr , emrh : Emrh , emcr : Emcr , emcrh : Emcrh , qemr : Qemr , qemcr : Qemcr , ccerr : Ccerr , ccerrclr : Ccerrclr , eeval : Eeval , _reserved16 : [u8 ; 0x1c]
, draem : Draem , draehm : Draehm , _reserved18 : [u8 ; 0x38]
, qraen : Qraen , _reserved19 : [u8 ; 0x7c]
, qne0 : Qne0 , qne1 : Qne1 , qne2 : Qne2 , qne3 : Qne3 , qne4 : Qne4 , qne5 : Qne5 , qne6 : Qne6 , qne7 : Qne7 , qne8 : Qne8 , qne9 : Qne9 , qne10 : Qne10 , qne11 : Qne11 , qne12 : Qne12 , qne13 : Qne13 , qne14 : Qne14 , qne15 : Qne15 , _reserved35 : [u8 ; 0x01c0]
, qstatn : Qstatn , _reserved36 : [u8 ; 0x1c]
, qwmthra : Qwmthra , _reserved37 : [u8 ; 0x1c]
, ccstat : Ccstat , _reserved38 : [u8 ; 0xbc]
, aetctl : Aetctl , aetstat : Aetstat , aetcmd : Aetcmd , _reserved41 : [u8 ; 0x08f4]
, er : Er , erh : Erh , ecr : Ecr , ecrh : Ecrh , esr : Esr , esrh : Esrh , cer : Cer , cerh : Cerh , eer : Eer , eerh : Eerh , eecr : Eecr , eecrh : Eecrh , eesr : Eesr , eesrh : Eesrh , ser : Ser , serh : Serh , secr : Secr , secrh : Secrh , _reserved59 : [u8 ; 0x08]
, ier : Ier , ierh : Ierh , iecr : Iecr , iecrh : Iecrh , iesr : Iesr , iesrh : Iesrh , ipr : Ipr , iprh : Iprh , icr : Icr , icrh : Icrh , ieval : Ieval , _reserved70 : [u8 ; 0x04]
, qer : Qer , qeer : Qeer , qeecr : Qeecr , qeesr : Qeesr , qser : Qser , qsecr : Qsecr , _reserved76 : [u8 ; 0x0f68]
, er_rn : ErRn , erh_rn : ErhRn , ecr_rn : EcrRn , ecrh_rn : EcrhRn , esr_rn : EsrRn , esrh_rn : EsrhRn , cer_rn : CerRn , cerh_rn : CerhRn , eer_rn : EerRn , eerh_rn : EerhRn , eecr_rn : EecrRn , eecrh_rn : EecrhRn , eesr_rn : EesrRn , eesrh_rn : EesrhRn , ser_rn : SerRn , serh_rn : SerhRn , secr_rn : SecrRn , secrh_rn : SecrhRn , _reserved94 : [u8 ; 0x08]
, ier_rn : IerRn , ierh_rn : IerhRn , iecr_rn : IecrRn , iecrh_rn : IecrhRn , iesr_rn : IesrRn , iesrh_rn : IesrhRn , ipr_rn : IprRn , iprh_rn : IprhRn , icr_rn : IcrRn , icrh_rn : IcrhRn , ieval_rn : IevalRn , _reserved105 : [u8 ; 0x04]
, qer_rn : QerRn , qeer_rn : QeerRn , qeecr_rn : QeecrRn , qeesr_rn : QeesrRn , qser_rn : QserRn , qsecr_rn : QsecrRn , _reserved111 : [u8 ; 0x1f68]
, opt : Opt , src : Src , abcnt : Abcnt , dst : Dst , bidx : Bidx , lnk : Lnk , cidx : Cidx , ccnt : Ccnt , } impl RegisterBlock { # [doc = "0x00 - Peripheral ID Register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - CC Configuration Register"]
# [inline (always)]
pub const fn cccfg (& self) -> & Cccfg { & self . cccfg } # [doc = "0x200 - QDMA Channel N Mapping Register"]
# [inline (always)]
pub const fn qchmapn (& self) -> & Qchmapn { & self . qchmapn } # [doc = "0x240 - DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."]
# [inline (always)]
pub const fn dmaqnumn (& self) -> & Dmaqnumn { & self . dmaqnumn } # [doc = "0x260 - QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."]
# [inline (always)]
pub const fn qdmaqnum (& self) -> & Qdmaqnum { & self . qdmaqnum } # [doc = "0x280 - Queue to TC Mapping"]
# [inline (always)]
pub const fn quetcmap (& self) -> & Quetcmap { & self . quetcmap } # [doc = "0x284 - Queue Priority"]
# [inline (always)]
pub const fn quepri (& self) -> & Quepri { & self . quepri } # [doc = "0x300 - Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub const fn emr (& self) -> & Emr { & self . emr } # [doc = "0x304 - Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub const fn emrh (& self) -> & Emrh { & self . emrh } # [doc = "0x308 - Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
# [inline (always)]
pub const fn emcr (& self) -> & Emcr { & self . emcr } # [doc = "0x30c - Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
# [inline (always)]
pub const fn emcrh (& self) -> & Emcrh { & self . emcrh } # [doc = "0x310 - QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub const fn qemr (& self) -> & Qemr { & self . qemr } # [doc = "0x314 - QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
# [inline (always)]
pub const fn qemcr (& self) -> & Qemcr { & self . qemcr } # [doc = "0x318 - CC Error Register"]
# [inline (always)]
pub const fn ccerr (& self) -> & Ccerr { & self . ccerr } # [doc = "0x31c - CC Error Clear Register"]
# [inline (always)]
pub const fn ccerrclr (& self) -> & Ccerrclr { & self . ccerrclr } # [doc = "0x320 - Error Eval Register"]
# [inline (always)]
pub const fn eeval (& self) -> & Eeval { & self . eeval } # [doc = "0x340 - DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
# [inline (always)]
pub const fn draem (& self) -> & Draem { & self . draem } # [doc = "0x344 - DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
# [inline (always)]
pub const fn draehm (& self) -> & Draehm { & self . draehm } # [doc = "0x380 - QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt."]
# [inline (always)]
pub const fn qraen (& self) -> & Qraen { & self . qraen } # [doc = "0x400 - Event Queue Entry Diagram for Queue n - Entry 0"]
# [inline (always)]
pub const fn qne0 (& self) -> & Qne0 { & self . qne0 } # [doc = "0x404 - Event Queue Entry Diagram for Queue n - Entry 1"]
# [inline (always)]
pub const fn qne1 (& self) -> & Qne1 { & self . qne1 } # [doc = "0x408 - Event Queue Entry Diagram for Queue n - Entry 2"]
# [inline (always)]
pub const fn qne2 (& self) -> & Qne2 { & self . qne2 } # [doc = "0x40c - Event Queue Entry Diagram for Queue n - Entry 3"]
# [inline (always)]
pub const fn qne3 (& self) -> & Qne3 { & self . qne3 } # [doc = "0x410 - Event Queue Entry Diagram for Queue n - Entry 4"]
# [inline (always)]
pub const fn qne4 (& self) -> & Qne4 { & self . qne4 } # [doc = "0x414 - Event Queue Entry Diagram for Queue n - Entry 5"]
# [inline (always)]
pub const fn qne5 (& self) -> & Qne5 { & self . qne5 } # [doc = "0x418 - Event Queue Entry Diagram for Queue n - Entry 6"]
# [inline (always)]
pub const fn qne6 (& self) -> & Qne6 { & self . qne6 } # [doc = "0x41c - Event Queue Entry Diagram for Queue n - Entry 7"]
# [inline (always)]
pub const fn qne7 (& self) -> & Qne7 { & self . qne7 } # [doc = "0x420 - Event Queue Entry Diagram for Queue n - Entry 8"]
# [inline (always)]
pub const fn qne8 (& self) -> & Qne8 { & self . qne8 } # [doc = "0x424 - Event Queue Entry Diagram for Queue n - Entry 9"]
# [inline (always)]
pub const fn qne9 (& self) -> & Qne9 { & self . qne9 } # [doc = "0x428 - Event Queue Entry Diagram for Queue n - Entry 0"]
# [inline (always)]
pub const fn qne10 (& self) -> & Qne10 { & self . qne10 } # [doc = "0x42c - Event Queue Entry Diagram for Queue n - Entry 11"]
# [inline (always)]
pub const fn qne11 (& self) -> & Qne11 { & self . qne11 } # [doc = "0x430 - Event Queue Entry Diagram for Queue n - Entry 12"]
# [inline (always)]
pub const fn qne12 (& self) -> & Qne12 { & self . qne12 } # [doc = "0x434 - Event Queue Entry Diagram for Queue n - Entry 13"]
# [inline (always)]
pub const fn qne13 (& self) -> & Qne13 { & self . qne13 } # [doc = "0x438 - Event Queue Entry Diagram for Queue n - Entry 14"]
# [inline (always)]
pub const fn qne14 (& self) -> & Qne14 { & self . qne14 } # [doc = "0x43c - Event Queue Entry Diagram for Queue n - Entry 15"]
# [inline (always)]
pub const fn qne15 (& self) -> & Qne15 { & self . qne15 } # [doc = "0x600 - QSTATn Register Set"]
# [inline (always)]
pub const fn qstatn (& self) -> & Qstatn { & self . qstatn } # [doc = "0x620 - Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors."]
# [inline (always)]
pub const fn qwmthra (& self) -> & Qwmthra { & self . qwmthra } # [doc = "0x640 - CC Status Register"]
# [inline (always)]
pub const fn ccstat (& self) -> & Ccstat { & self . ccstat } # [doc = "0x700 - Advanced Event Trigger Control"]
# [inline (always)]
pub const fn aetctl (& self) -> & Aetctl { & self . aetctl } # [doc = "0x704 - Advanced Event Trigger Stat"]
# [inline (always)]
pub const fn aetstat (& self) -> & Aetstat { & self . aetstat } # [doc = "0x708 - AET Command"]
# [inline (always)]
pub const fn aetcmd (& self) -> & Aetcmd { & self . aetcmd } # [doc = "0x1000 - Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
# [inline (always)]
pub const fn er (& self) -> & Er { & self . er } # [doc = "0x1004 - Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
# [inline (always)]
pub const fn erh (& self) -> & Erh { & self . erh } # [doc = "0x1008 - Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecr (& self) -> & Ecr { & self . ecr } # [doc = "0x100c - Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecrh (& self) -> & Ecrh { & self . ecrh } # [doc = "0x1010 - Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esr (& self) -> & Esr { & self . esr } # [doc = "0x1014 - Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esrh (& self) -> & Esrh { & self . esrh } # [doc = "0x1018 - Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cer (& self) -> & Cer { & self . cer } # [doc = "0x101c - Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cerh (& self) -> & Cerh { & self . cerh } # [doc = "0x1020 - Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eer (& self) -> & Eer { & self . eer } # [doc = "0x1024 - Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eerh (& self) -> & Eerh { & self . eerh } # [doc = "0x1028 - Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecr (& self) -> & Eecr { & self . eecr } # [doc = "0x102c - Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecrh (& self) -> & Eecrh { & self . eecrh } # [doc = "0x1030 - Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesr (& self) -> & Eesr { & self . eesr } # [doc = "0x1034 - Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesrh (& self) -> & Eesrh { & self . eesrh } # [doc = "0x1038 - Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn ser (& self) -> & Ser { & self . ser } # [doc = "0x103c - Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn serh (& self) -> & Serh { & self . serh } # [doc = "0x1040 - Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secr (& self) -> & Secr { & self . secr } # [doc = "0x1044 - Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secrh (& self) -> & Secrh { & self . secrh } # [doc = "0x1050 - Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ier (& self) -> & Ier { & self . ier } # [doc = "0x1054 - Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ierh (& self) -> & Ierh { & self . ierh } # [doc = "0x1058 - Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecr (& self) -> & Iecr { & self . iecr } # [doc = "0x105c - Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecrh (& self) -> & Iecrh { & self . iecrh } # [doc = "0x1060 - Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesr (& self) -> & Iesr { & self . iesr } # [doc = "0x1064 - Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesrh (& self) -> & Iesrh { & self . iesrh } # [doc = "0x1068 - Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
# [inline (always)]
pub const fn ipr (& self) -> & Ipr { & self . ipr } # [doc = "0x106c - Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
# [inline (always)]
pub const fn iprh (& self) -> & Iprh { & self . iprh } # [doc = "0x1070 - Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icr (& self) -> & Icr { & self . icr } # [doc = "0x1074 - Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icrh (& self) -> & Icrh { & self . icrh } # [doc = "0x1078 - Interrupt Eval Register"]
# [inline (always)]
pub const fn ieval (& self) -> & Ieval { & self . ieval } # [doc = "0x1080 - QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
# [inline (always)]
pub const fn qer (& self) -> & Qer { & self . qer } # [doc = "0x1084 - QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
# [inline (always)]
pub const fn qeer (& self) -> & Qeer { & self . qeer } # [doc = "0x1088 - QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeecr (& self) -> & Qeecr { & self . qeecr } # [doc = "0x108c - QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeesr (& self) -> & Qeesr { & self . qeesr } # [doc = "0x1090 - QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn qser (& self) -> & Qser { & self . qser } # [doc = "0x1094 - QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qsecr (& self) -> & Qsecr { & self . qsecr } # [doc = "0x2000 - Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
# [inline (always)]
pub const fn er_rn (& self) -> & ErRn { & self . er_rn } # [doc = "0x2004 - Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
# [inline (always)]
pub const fn erh_rn (& self) -> & ErhRn { & self . erh_rn } # [doc = "0x2008 - Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecr_rn (& self) -> & EcrRn { & self . ecr_rn } # [doc = "0x200c - Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn ecrh_rn (& self) -> & EcrhRn { & self . ecrh_rn } # [doc = "0x2010 - Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esr_rn (& self) -> & EsrRn { & self . esr_rn } # [doc = "0x2014 - Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn esrh_rn (& self) -> & EsrhRn { & self . esrh_rn } # [doc = "0x2018 - Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cer_rn (& self) -> & CerRn { & self . cer_rn } # [doc = "0x201c - Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
# [inline (always)]
pub const fn cerh_rn (& self) -> & CerhRn { & self . cerh_rn } # [doc = "0x2020 - Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eer_rn (& self) -> & EerRn { & self . eer_rn } # [doc = "0x2024 - Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
# [inline (always)]
pub const fn eerh_rn (& self) -> & EerhRn { & self . eerh_rn } # [doc = "0x2028 - Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecr_rn (& self) -> & EecrRn { & self . eecr_rn } # [doc = "0x202c - Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eecrh_rn (& self) -> & EecrhRn { & self . eecrh_rn } # [doc = "0x2030 - Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesr_rn (& self) -> & EesrRn { & self . eesr_rn } # [doc = "0x2034 - Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn eesrh_rn (& self) -> & EesrhRn { & self . eesrh_rn } # [doc = "0x2038 - Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn ser_rn (& self) -> & SerRn { & self . ser_rn } # [doc = "0x203c - Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn serh_rn (& self) -> & SerhRn { & self . serh_rn } # [doc = "0x2040 - Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secr_rn (& self) -> & SecrRn { & self . secr_rn } # [doc = "0x2044 - Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
# [inline (always)]
pub const fn secrh_rn (& self) -> & SecrhRn { & self . secrh_rn } # [doc = "0x2050 - Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ier_rn (& self) -> & IerRn { & self . ier_rn } # [doc = "0x2054 - Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
# [inline (always)]
pub const fn ierh_rn (& self) -> & IerhRn { & self . ierh_rn } # [doc = "0x2058 - Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecr_rn (& self) -> & IecrRn { & self . iecr_rn } # [doc = "0x205c - Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iecrh_rn (& self) -> & IecrhRn { & self . iecrh_rn } # [doc = "0x2060 - Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesr_rn (& self) -> & IesrRn { & self . iesr_rn } # [doc = "0x2064 - Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn iesrh_rn (& self) -> & IesrhRn { & self . iesrh_rn } # [doc = "0x2068 - Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
# [inline (always)]
pub const fn ipr_rn (& self) -> & IprRn { & self . ipr_rn } # [doc = "0x206c - Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
# [inline (always)]
pub const fn iprh_rn (& self) -> & IprhRn { & self . iprh_rn } # [doc = "0x2070 - Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icr_rn (& self) -> & IcrRn { & self . icr_rn } # [doc = "0x2074 - Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
# [inline (always)]
pub const fn icrh_rn (& self) -> & IcrhRn { & self . icrh_rn } # [doc = "0x2078 - Interrupt Eval Register"]
# [inline (always)]
pub const fn ieval_rn (& self) -> & IevalRn { & self . ieval_rn } # [doc = "0x2080 - QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
# [inline (always)]
pub const fn qer_rn (& self) -> & QerRn { & self . qer_rn } # [doc = "0x2084 - QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
# [inline (always)]
pub const fn qeer_rn (& self) -> & QeerRn { & self . qeer_rn } # [doc = "0x2088 - QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeecr_rn (& self) -> & QeecrRn { & self . qeecr_rn } # [doc = "0x208c - QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qeesr_rn (& self) -> & QeesrRn { & self . qeesr_rn } # [doc = "0x2090 - QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
# [inline (always)]
pub const fn qser_rn (& self) -> & QserRn { & self . qser_rn } # [doc = "0x2094 - QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
# [inline (always)]
pub const fn qsecr_rn (& self) -> & QsecrRn { & self . qsecr_rn } # [doc = "0x4000 - Options Parameter"]
# [inline (always)]
pub const fn opt (& self) -> & Opt { & self . opt } # [doc = "0x4004 - Source Address"]
# [inline (always)]
pub const fn src (& self) -> & Src { & self . src } # [doc = "0x4008 - A and B byte count"]
# [inline (always)]
pub const fn abcnt (& self) -> & Abcnt { & self . abcnt } # [doc = "0x400c - Destination Address"]
# [inline (always)]
pub const fn dst (& self) -> & Dst { & self . dst } # [doc = "0x4010 - Register description is not available"]
# [inline (always)]
pub const fn bidx (& self) -> & Bidx { & self . bidx } # [doc = "0x4014 - Link and Reload parameters"]
# [inline (always)]
pub const fn lnk (& self) -> & Lnk { & self . lnk } # [doc = "0x4018 - Register description is not available"]
# [inline (always)]
pub const fn cidx (& self) -> & Cidx { & self . cidx } # [doc = "0x401c - C byte count"]
# [inline (always)]
pub const fn ccnt (& self) -> & Ccnt { & self . ccnt } } # [doc = "PID (rw) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "Peripheral ID Register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR` reader - 5:0\\]
Minor Revision"]
pub type MinorR = crate :: FieldReader ; # [doc = "Field `MINOR` writer - 5:0\\]
Minor Revision"]
pub type MinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR` reader - 10:8\\]
Major Revision"]
pub type MajorR = crate :: FieldReader ; # [doc = "Field `MAJOR` writer - 10:8\\]
Major Revision"]
pub type MajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL` reader - 15:11\\]
RTL Version"]
pub type RtlR = crate :: FieldReader ; # [doc = "Field `RTL` writer - 15:11\\]
RTL Version"]
pub type RtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNC` reader - 27:16\\]
Function indicates a software compatible module family."]
pub type FuncR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNC` writer - 27:16\\]
Function indicates a software compatible module family."]
pub type FuncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `RES1` reader - 29:28\\]
RESERVE FIELD"]
pub type Res1R = crate :: FieldReader ; # [doc = "Field `RES1` writer - 29:28\\]
RESERVE FIELD"]
pub type Res1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
pub fn minor (& self) -> MinorR { MinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
pub fn major (& self) -> MajorR { MajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
pub fn rtl (& self) -> RtlR { RtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
pub fn func (& self) -> FuncR { FuncR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res1 (& self) -> Res1R { Res1R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision"]
# [inline (always)]
# [must_use]
pub fn minor (& mut self) -> MinorW < PidSpec > { MinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom revision field: Not used on this version of EDMA."]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < PidSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision"]
# [inline (always)]
# [must_use]
pub fn major (& mut self) -> MajorW < PidSpec > { MajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version"]
# [inline (always)]
# [must_use]
pub fn rtl (& mut self) -> RtlW < PidSpec > { RtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family."]
# [inline (always)]
# [must_use]
pub fn func (& mut self) -> FuncW < PidSpec > { FuncW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res1 (& mut self) -> Res1W < PidSpec > { Res1W :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1."]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < PidSpec > { SchemeW :: new (self , 30) } } # [doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCCFG (rw) register accessor: CC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cccfg`]
module"]
# [doc (alias = "CCCFG")]
pub type Cccfg = crate :: Reg < cccfg :: CccfgSpec > ; # [doc = "CC Configuration Register"]
pub mod cccfg { # [doc = "Register `CCCFG` reader"]
pub type R = crate :: R < CccfgSpec > ; # [doc = "Register `CCCFG` writer"]
pub type W = crate :: W < CccfgSpec > ; # [doc = "Field `NUMDMACH` reader - 2:0\\]
Number of DMA Channels"]
pub type NumdmachR = crate :: FieldReader ; # [doc = "Field `NUMDMACH` writer - 2:0\\]
Number of DMA Channels"]
pub type NumdmachW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES8` reader - 3:3\\]
RESERVE FIELD"]
pub type Res8R = crate :: BitReader ; # [doc = "Field `RES8` writer - 3:3\\]
RESERVE FIELD"]
pub type Res8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMQDMACH` reader - 6:4\\]
Number of QDMA Channels"]
pub type NumqdmachR = crate :: FieldReader ; # [doc = "Field `NUMQDMACH` writer - 6:4\\]
Number of QDMA Channels"]
pub type NumqdmachW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES7` reader - 7:7\\]
RESERVE FIELD"]
pub type Res7R = crate :: BitReader ; # [doc = "Field `RES7` writer - 7:7\\]
RESERVE FIELD"]
pub type Res7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMINTCH` reader - 10:8\\]
Number of Interrupt Channels"]
pub type NumintchR = crate :: FieldReader ; # [doc = "Field `NUMINTCH` writer - 10:8\\]
Number of Interrupt Channels"]
pub type NumintchW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES6` reader - 11:11\\]
RESERVE FIELD"]
pub type Res6R = crate :: BitReader ; # [doc = "Field `RES6` writer - 11:11\\]
RESERVE FIELD"]
pub type Res6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMPAENTRY` reader - 14:12\\]
Number of PaRAM entries"]
pub type NumpaentryR = crate :: FieldReader ; # [doc = "Field `NUMPAENTRY` writer - 14:12\\]
Number of PaRAM entries"]
pub type NumpaentryW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES5` reader - 15:15\\]
RESERVE FIELD"]
pub type Res5R = crate :: BitReader ; # [doc = "Field `RES5` writer - 15:15\\]
RESERVE FIELD"]
pub type Res5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMTC` reader - 18:16\\]
Number of Queues/Number of TCs"]
pub type NumtcR = crate :: FieldReader ; # [doc = "Field `NUMTC` writer - 18:16\\]
Number of Queues/Number of TCs"]
pub type NumtcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES4` reader - 19:19\\]
RESERVE FIELD"]
pub type Res4R = crate :: BitReader ; # [doc = "Field `RES4` writer - 19:19\\]
RESERVE FIELD"]
pub type Res4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NUMREGN` reader - 21:20\\]
Number of MP and Shadow regions"]
pub type NumregnR = crate :: FieldReader ; # [doc = "Field `NUMREGN` writer - 21:20\\]
Number of MP and Shadow regions"]
pub type NumregnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES3` reader - 23:22\\]
RESERVE FIELD"]
pub type Res3R = crate :: FieldReader ; # [doc = "Field `RES3` writer - 23:22\\]
RESERVE FIELD"]
pub type Res3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CHMAPEXIST` reader - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
pub type ChmapexistR = crate :: BitReader ; # [doc = "Field `CHMAPEXIST` writer - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
pub type ChmapexistW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MPEXIST` reader - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
pub type MpexistR = crate :: BitReader ; # [doc = "Field `MPEXIST` writer - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
pub type MpexistW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES2` reader - 31:26\\]
RESERVE FIELD"]
pub type Res2R = crate :: FieldReader ; # [doc = "Field `RES2` writer - 31:26\\]
RESERVE FIELD"]
pub type Res2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Number of DMA Channels"]
# [inline (always)]
pub fn numdmach (& self) -> NumdmachR { NumdmachR :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res8 (& self) -> Res8R { Res8R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Number of QDMA Channels"]
# [inline (always)]
pub fn numqdmach (& self) -> NumqdmachR { NumqdmachR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res7 (& self) -> Res7R { Res7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
Number of Interrupt Channels"]
# [inline (always)]
pub fn numintch (& self) -> NumintchR { NumintchR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res6 (& self) -> Res6R { Res6R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - 14:12\\]
Number of PaRAM entries"]
# [inline (always)]
pub fn numpaentry (& self) -> NumpaentryR { NumpaentryR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res5 (& self) -> Res5R { Res5R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
Number of Queues/Number of TCs"]
# [inline (always)]
pub fn numtc (& self) -> NumtcR { NumtcR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res4 (& self) -> Res4R { Res4R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:21 - 21:20\\]
Number of MP and Shadow regions"]
# [inline (always)]
pub fn numregn (& self) -> NumregnR { NumregnR :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - 23:22\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res3 (& self) -> Res3R { Res3R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bit 24 - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
# [inline (always)]
pub fn chmapexist (& self) -> ChmapexistR { ChmapexistR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
# [inline (always)]
pub fn mpexist (& self) -> MpexistR { MpexistR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res2 (& self) -> Res2R { Res2R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Number of DMA Channels"]
# [inline (always)]
# [must_use]
pub fn numdmach (& mut self) -> NumdmachW < CccfgSpec > { NumdmachW :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res8 (& mut self) -> Res8W < CccfgSpec > { Res8W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Number of QDMA Channels"]
# [inline (always)]
# [must_use]
pub fn numqdmach (& mut self) -> NumqdmachW < CccfgSpec > { NumqdmachW :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res7 (& mut self) -> Res7W < CccfgSpec > { Res7W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
Number of Interrupt Channels"]
# [inline (always)]
# [must_use]
pub fn numintch (& mut self) -> NumintchW < CccfgSpec > { NumintchW :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res6 (& mut self) -> Res6W < CccfgSpec > { Res6W :: new (self , 11) } # [doc = "Bits 12:14 - 14:12\\]
Number of PaRAM entries"]
# [inline (always)]
# [must_use]
pub fn numpaentry (& mut self) -> NumpaentryW < CccfgSpec > { NumpaentryW :: new (self , 12) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res5 (& mut self) -> Res5W < CccfgSpec > { Res5W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
Number of Queues/Number of TCs"]
# [inline (always)]
# [must_use]
pub fn numtc (& mut self) -> NumtcW < CccfgSpec > { NumtcW :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res4 (& mut self) -> Res4W < CccfgSpec > { Res4W :: new (self , 19) } # [doc = "Bits 20:21 - 21:20\\]
Number of MP and Shadow regions"]
# [inline (always)]
# [must_use]
pub fn numregn (& mut self) -> NumregnW < CccfgSpec > { NumregnW :: new (self , 20) } # [doc = "Bits 22:23 - 23:22\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res3 (& mut self) -> Res3W < CccfgSpec > { Res3W :: new (self , 22) } # [doc = "Bit 24 - 24:24\\]
Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included."]
# [inline (always)]
# [must_use]
pub fn chmapexist (& mut self) -> ChmapexistW < CccfgSpec > { ChmapexistW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included."]
# [inline (always)]
# [must_use]
pub fn mpexist (& mut self) -> MpexistW < CccfgSpec > { MpexistW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res2 (& mut self) -> Res2W < CccfgSpec > { Res2W :: new (self , 26) } } # [doc = "CC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CccfgSpec ; impl crate :: RegisterSpec for CccfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cccfg::R`](R) reader structure"]
impl crate :: Readable for CccfgSpec { } # [doc = "`write(|w| ..)` method takes [`cccfg::W`](W) writer structure"]
impl crate :: Writable for CccfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCCFG to value 0"]
impl crate :: Resettable for CccfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QCHMAPN (rw) register accessor: QDMA Channel N Mapping Register\n\nYou can [`read`](crate::Reg::read) this register and get [`qchmapn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qchmapn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qchmapn`]
module"]
# [doc (alias = "QCHMAPN")]
pub type Qchmapn = crate :: Reg < qchmapn :: QchmapnSpec > ; # [doc = "QDMA Channel N Mapping Register"]
pub mod qchmapn { # [doc = "Register `QCHMAPN` reader"]
pub type R = crate :: R < QchmapnSpec > ; # [doc = "Register `QCHMAPN` writer"]
pub type W = crate :: W < QchmapnSpec > ; # [doc = "Field `TRWORD` reader - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
pub type TrwordR = crate :: FieldReader ; # [doc = "Field `TRWORD` writer - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
pub type TrwordW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PAENTRY` reader - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
pub type PaentryR = crate :: FieldReader < u16 > ; # [doc = "Field `PAENTRY` writer - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
pub type PaentryW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `RES10` reader - 31:14\\]
RESERVE FIELD"]
pub type Res10R = crate :: FieldReader < u32 > ; # [doc = "Field `RES10` writer - 31:14\\]
RESERVE FIELD"]
pub type Res10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bits 2:4 - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
# [inline (always)]
pub fn trword (& self) -> TrwordR { TrwordR :: new (((self . bits >> 2) & 7) as u8) } # [doc = "Bits 5:13 - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
# [inline (always)]
pub fn paentry (& self) -> PaentryR { PaentryR :: new (((self . bits >> 5) & 0x01ff) as u16) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res10 (& self) -> Res10R { Res10R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bits 2:4 - 4:2\\]
TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized."]
# [inline (always)]
# [must_use]
pub fn trword (& mut self) -> TrwordW < QchmapnSpec > { TrwordW :: new (self , 2) } # [doc = "Bits 5:13 - 13:5\\]
PaRAM Entry number for QDMA Channel N."]
# [inline (always)]
# [must_use]
pub fn paentry (& mut self) -> PaentryW < QchmapnSpec > { PaentryW :: new (self , 5) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res10 (& mut self) -> Res10W < QchmapnSpec > { Res10W :: new (self , 14) } } # [doc = "QDMA Channel N Mapping Register\n\nYou can [`read`](crate::Reg::read) this register and get [`qchmapn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qchmapn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QchmapnSpec ; impl crate :: RegisterSpec for QchmapnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qchmapn::R`](R) reader structure"]
impl crate :: Readable for QchmapnSpec { } # [doc = "`write(|w| ..)` method takes [`qchmapn::W`](W) writer structure"]
impl crate :: Writable for QchmapnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QCHMAPN to value 0"]
impl crate :: Resettable for QchmapnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMAQNUMN (rw) register accessor: DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaqnumn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaqnumn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaqnumn`]
module"]
# [doc (alias = "DMAQNUMN")]
pub type Dmaqnumn = crate :: Reg < dmaqnumn :: DmaqnumnSpec > ; # [doc = "DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."]
pub mod dmaqnumn { # [doc = "Register `DMAQNUMN` reader"]
pub type R = crate :: R < DmaqnumnSpec > ; # [doc = "Register `DMAQNUMN` writer"]
pub type W = crate :: W < DmaqnumnSpec > ; # [doc = "Field `E0` reader - 2:0\\]
DMA Queue Number for event #0"]
pub type E0R = crate :: FieldReader ; # [doc = "Field `E0` writer - 2:0\\]
DMA Queue Number for event #0"]
pub type E0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES18` reader - 3:3\\]
RESERVE FIELD"]
pub type Res18R = crate :: BitReader ; # [doc = "Field `RES18` writer - 3:3\\]
RESERVE FIELD"]
pub type Res18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 6:4\\]
DMA Queue Number for event #1"]
pub type E1R = crate :: FieldReader ; # [doc = "Field `E1` writer - 6:4\\]
DMA Queue Number for event #1"]
pub type E1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES17` reader - 7:7\\]
RESERVE FIELD"]
pub type Res17R = crate :: BitReader ; # [doc = "Field `RES17` writer - 7:7\\]
RESERVE FIELD"]
pub type Res17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 10:8\\]
DMA Queue Number for event #2"]
pub type E2R = crate :: FieldReader ; # [doc = "Field `E2` writer - 10:8\\]
DMA Queue Number for event #2"]
pub type E2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES16` reader - 11:11\\]
RESERVE FIELD"]
pub type Res16R = crate :: BitReader ; # [doc = "Field `RES16` writer - 11:11\\]
RESERVE FIELD"]
pub type Res16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 14:12\\]
DMA Queue Number for event #3"]
pub type E3R = crate :: FieldReader ; # [doc = "Field `E3` writer - 14:12\\]
DMA Queue Number for event #3"]
pub type E3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES15` reader - 15:15\\]
RESERVE FIELD"]
pub type Res15R = crate :: BitReader ; # [doc = "Field `RES15` writer - 15:15\\]
RESERVE FIELD"]
pub type Res15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 18:16\\]
DMA Queue Number for event #4"]
pub type E4R = crate :: FieldReader ; # [doc = "Field `E4` writer - 18:16\\]
DMA Queue Number for event #4"]
pub type E4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES14` reader - 19:19\\]
RESERVE FIELD"]
pub type Res14R = crate :: BitReader ; # [doc = "Field `RES14` writer - 19:19\\]
RESERVE FIELD"]
pub type Res14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 22:20\\]
DMA Queue Number for event #5"]
pub type E5R = crate :: FieldReader ; # [doc = "Field `E5` writer - 22:20\\]
DMA Queue Number for event #5"]
pub type E5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES13` reader - 23:23\\]
RESERVE FIELD"]
pub type Res13R = crate :: BitReader ; # [doc = "Field `RES13` writer - 23:23\\]
RESERVE FIELD"]
pub type Res13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 26:24\\]
DMA Queue Number for event #6"]
pub type E6R = crate :: FieldReader ; # [doc = "Field `E6` writer - 26:24\\]
DMA Queue Number for event #6"]
pub type E6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES12` reader - 27:27\\]
RESERVE FIELD"]
pub type Res12R = crate :: BitReader ; # [doc = "Field `RES12` writer - 27:27\\]
RESERVE FIELD"]
pub type Res12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 30:28\\]
DMA Queue Number for event #7"]
pub type E7R = crate :: FieldReader ; # [doc = "Field `E7` writer - 30:28\\]
DMA Queue Number for event #7"]
pub type E7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES11` reader - 31:31\\]
RESERVE FIELD"]
pub type Res11R = crate :: BitReader ; # [doc = "Field `RES11` writer - 31:31\\]
RESERVE FIELD"]
pub type Res11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
DMA Queue Number for event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res18 (& self) -> Res18R { Res18R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
DMA Queue Number for event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res17 (& self) -> Res17R { Res17R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
DMA Queue Number for event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res16 (& self) -> Res16R { Res16R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - 14:12\\]
DMA Queue Number for event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res15 (& self) -> Res15R { Res15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
DMA Queue Number for event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res14 (& self) -> Res14R { Res14R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:22 - 22:20\\]
DMA Queue Number for event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 20) & 7) as u8) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res13 (& self) -> Res13R { Res13R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - 26:24\\]
DMA Queue Number for event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res12 (& self) -> Res12R { Res12R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bits 28:30 - 30:28\\]
DMA Queue Number for event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res11 (& self) -> Res11R { Res11R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
DMA Queue Number for event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < DmaqnumnSpec > { E0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res18 (& mut self) -> Res18W < DmaqnumnSpec > { Res18W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
DMA Queue Number for event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < DmaqnumnSpec > { E1W :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res17 (& mut self) -> Res17W < DmaqnumnSpec > { Res17W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
DMA Queue Number for event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < DmaqnumnSpec > { E2W :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res16 (& mut self) -> Res16W < DmaqnumnSpec > { Res16W :: new (self , 11) } # [doc = "Bits 12:14 - 14:12\\]
DMA Queue Number for event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < DmaqnumnSpec > { E3W :: new (self , 12) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res15 (& mut self) -> Res15W < DmaqnumnSpec > { Res15W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
DMA Queue Number for event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < DmaqnumnSpec > { E4W :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res14 (& mut self) -> Res14W < DmaqnumnSpec > { Res14W :: new (self , 19) } # [doc = "Bits 20:22 - 22:20\\]
DMA Queue Number for event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < DmaqnumnSpec > { E5W :: new (self , 20) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res13 (& mut self) -> Res13W < DmaqnumnSpec > { Res13W :: new (self , 23) } # [doc = "Bits 24:26 - 26:24\\]
DMA Queue Number for event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < DmaqnumnSpec > { E6W :: new (self , 24) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res12 (& mut self) -> Res12W < DmaqnumnSpec > { Res12W :: new (self , 27) } # [doc = "Bits 28:30 - 30:28\\]
DMA Queue Number for event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < DmaqnumnSpec > { E7W :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res11 (& mut self) -> Res11W < DmaqnumnSpec > { Res11W :: new (self , 31) } } # [doc = "DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaqnumn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaqnumn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmaqnumnSpec ; impl crate :: RegisterSpec for DmaqnumnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dmaqnumn::R`](R) reader structure"]
impl crate :: Readable for DmaqnumnSpec { } # [doc = "`write(|w| ..)` method takes [`dmaqnumn::W`](W) writer structure"]
impl crate :: Writable for DmaqnumnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMAQNUMN to value 0"]
impl crate :: Resettable for DmaqnumnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QDMAQNUM (rw) register accessor: QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`qdmaqnum::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdmaqnum::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdmaqnum`]
module"]
# [doc (alias = "QDMAQNUM")]
pub type Qdmaqnum = crate :: Reg < qdmaqnum :: QdmaqnumSpec > ; # [doc = "QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."]
pub mod qdmaqnum { # [doc = "Register `QDMAQNUM` reader"]
pub type R = crate :: R < QdmaqnumSpec > ; # [doc = "Register `QDMAQNUM` writer"]
pub type W = crate :: W < QdmaqnumSpec > ; # [doc = "Field `E0` reader - 2:0\\]
QDMA Queue Number for event #0"]
pub type E0R = crate :: FieldReader ; # [doc = "Field `E0` writer - 2:0\\]
QDMA Queue Number for event #0"]
pub type E0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES26` reader - 3:3\\]
RESERVE FIELD"]
pub type Res26R = crate :: BitReader ; # [doc = "Field `RES26` writer - 3:3\\]
RESERVE FIELD"]
pub type Res26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 6:4\\]
QDMA Queue Number for event #1"]
pub type E1R = crate :: FieldReader ; # [doc = "Field `E1` writer - 6:4\\]
QDMA Queue Number for event #1"]
pub type E1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES25` reader - 7:7\\]
RESERVE FIELD"]
pub type Res25R = crate :: BitReader ; # [doc = "Field `RES25` writer - 7:7\\]
RESERVE FIELD"]
pub type Res25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 10:8\\]
QDMA Queue Number for event #2"]
pub type E2R = crate :: FieldReader ; # [doc = "Field `E2` writer - 10:8\\]
QDMA Queue Number for event #2"]
pub type E2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES24` reader - 11:11\\]
RESERVE FIELD"]
pub type Res24R = crate :: BitReader ; # [doc = "Field `RES24` writer - 11:11\\]
RESERVE FIELD"]
pub type Res24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 14:12\\]
QDMA Queue Number for event #3"]
pub type E3R = crate :: FieldReader ; # [doc = "Field `E3` writer - 14:12\\]
QDMA Queue Number for event #3"]
pub type E3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES23` reader - 15:15\\]
RESERVE FIELD"]
pub type Res23R = crate :: BitReader ; # [doc = "Field `RES23` writer - 15:15\\]
RESERVE FIELD"]
pub type Res23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 18:16\\]
QDMA Queue Number for event #4"]
pub type E4R = crate :: FieldReader ; # [doc = "Field `E4` writer - 18:16\\]
QDMA Queue Number for event #4"]
pub type E4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES22` reader - 19:19\\]
RESERVE FIELD"]
pub type Res22R = crate :: BitReader ; # [doc = "Field `RES22` writer - 19:19\\]
RESERVE FIELD"]
pub type Res22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 22:20\\]
QDMA Queue Number for event #5"]
pub type E5R = crate :: FieldReader ; # [doc = "Field `E5` writer - 22:20\\]
QDMA Queue Number for event #5"]
pub type E5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES21` reader - 23:23\\]
RESERVE FIELD"]
pub type Res21R = crate :: BitReader ; # [doc = "Field `RES21` writer - 23:23\\]
RESERVE FIELD"]
pub type Res21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 26:24\\]
QDMA Queue Number for event #6"]
pub type E6R = crate :: FieldReader ; # [doc = "Field `E6` writer - 26:24\\]
QDMA Queue Number for event #6"]
pub type E6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES20` reader - 27:27\\]
RESERVE FIELD"]
pub type Res20R = crate :: BitReader ; # [doc = "Field `RES20` writer - 27:27\\]
RESERVE FIELD"]
pub type Res20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 30:28\\]
QDMA Queue Number for event #7"]
pub type E7R = crate :: FieldReader ; # [doc = "Field `E7` writer - 30:28\\]
QDMA Queue Number for event #7"]
pub type E7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES19` reader - 31:31\\]
RESERVE FIELD"]
pub type Res19R = crate :: BitReader ; # [doc = "Field `RES19` writer - 31:31\\]
RESERVE FIELD"]
pub type Res19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
QDMA Queue Number for event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res26 (& self) -> Res26R { Res26R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
QDMA Queue Number for event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res25 (& self) -> Res25R { Res25R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - 10:8\\]
QDMA Queue Number for event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res24 (& self) -> Res24R { Res24R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - 14:12\\]
QDMA Queue Number for event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res23 (& self) -> Res23R { Res23R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
QDMA Queue Number for event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res22 (& self) -> Res22R { Res22R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:22 - 22:20\\]
QDMA Queue Number for event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 20) & 7) as u8) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res21 (& self) -> Res21R { Res21R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:26 - 26:24\\]
QDMA Queue Number for event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res20 (& self) -> Res20R { Res20R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bits 28:30 - 30:28\\]
QDMA Queue Number for event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res19 (& self) -> Res19R { Res19R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
QDMA Queue Number for event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QdmaqnumSpec > { E0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res26 (& mut self) -> Res26W < QdmaqnumSpec > { Res26W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
QDMA Queue Number for event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QdmaqnumSpec > { E1W :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res25 (& mut self) -> Res25W < QdmaqnumSpec > { Res25W :: new (self , 7) } # [doc = "Bits 8:10 - 10:8\\]
QDMA Queue Number for event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QdmaqnumSpec > { E2W :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res24 (& mut self) -> Res24W < QdmaqnumSpec > { Res24W :: new (self , 11) } # [doc = "Bits 12:14 - 14:12\\]
QDMA Queue Number for event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QdmaqnumSpec > { E3W :: new (self , 12) } # [doc = "Bit 15 - 15:15\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res23 (& mut self) -> Res23W < QdmaqnumSpec > { Res23W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
QDMA Queue Number for event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QdmaqnumSpec > { E4W :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res22 (& mut self) -> Res22W < QdmaqnumSpec > { Res22W :: new (self , 19) } # [doc = "Bits 20:22 - 22:20\\]
QDMA Queue Number for event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QdmaqnumSpec > { E5W :: new (self , 20) } # [doc = "Bit 23 - 23:23\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res21 (& mut self) -> Res21W < QdmaqnumSpec > { Res21W :: new (self , 23) } # [doc = "Bits 24:26 - 26:24\\]
QDMA Queue Number for event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QdmaqnumSpec > { E6W :: new (self , 24) } # [doc = "Bit 27 - 27:27\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res20 (& mut self) -> Res20W < QdmaqnumSpec > { Res20W :: new (self , 27) } # [doc = "Bits 28:30 - 30:28\\]
QDMA Queue Number for event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QdmaqnumSpec > { E7W :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res19 (& mut self) -> Res19W < QdmaqnumSpec > { Res19W :: new (self , 31) } } # [doc = "QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`qdmaqnum::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdmaqnum::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QdmaqnumSpec ; impl crate :: RegisterSpec for QdmaqnumSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qdmaqnum::R`](R) reader structure"]
impl crate :: Readable for QdmaqnumSpec { } # [doc = "`write(|w| ..)` method takes [`qdmaqnum::W`](W) writer structure"]
impl crate :: Writable for QdmaqnumSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QDMAQNUM to value 0"]
impl crate :: Resettable for QdmaqnumSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QUETCMAP (rw) register accessor: Queue to TC Mapping\n\nYou can [`read`](crate::Reg::read) this register and get [`quetcmap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quetcmap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@quetcmap`]
module"]
# [doc (alias = "QUETCMAP")]
pub type Quetcmap = crate :: Reg < quetcmap :: QuetcmapSpec > ; # [doc = "Queue to TC Mapping"]
pub mod quetcmap { # [doc = "Register `QUETCMAP` reader"]
pub type R = crate :: R < QuetcmapSpec > ; # [doc = "Register `QUETCMAP` writer"]
pub type W = crate :: W < QuetcmapSpec > ; # [doc = "Field `TCNUMQ0` reader - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq0R = crate :: FieldReader ; # [doc = "Field `TCNUMQ0` writer - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES28` reader - 3:3\\]
RESERVE FIELD"]
pub type Res28R = crate :: BitReader ; # [doc = "Field `RES28` writer - 3:3\\]
RESERVE FIELD"]
pub type Res28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCNUMQ1` reader - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq1R = crate :: FieldReader ; # [doc = "Field `TCNUMQ1` writer - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
pub type Tcnumq1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES27` reader - 31:7\\]
RESERVE FIELD"]
pub type Res27R = crate :: FieldReader < u32 > ; # [doc = "Field `RES27` writer - 31:7\\]
RESERVE FIELD"]
pub type Res27W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
pub fn tcnumq0 (& self) -> Tcnumq0R { Tcnumq0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res28 (& self) -> Res28R { Res28R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
pub fn tcnumq1 (& self) -> Tcnumq1R { Tcnumq1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res27 (& self) -> Res27R { Res27R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
# [must_use]
pub fn tcnumq0 (& mut self) -> Tcnumq0W < QuetcmapSpec > { Tcnumq0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res28 (& mut self) -> Res28W < QuetcmapSpec > { Res28W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to."]
# [inline (always)]
# [must_use]
pub fn tcnumq1 (& mut self) -> Tcnumq1W < QuetcmapSpec > { Tcnumq1W :: new (self , 4) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res27 (& mut self) -> Res27W < QuetcmapSpec > { Res27W :: new (self , 7) } } # [doc = "Queue to TC Mapping\n\nYou can [`read`](crate::Reg::read) this register and get [`quetcmap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quetcmap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QuetcmapSpec ; impl crate :: RegisterSpec for QuetcmapSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`quetcmap::R`](R) reader structure"]
impl crate :: Readable for QuetcmapSpec { } # [doc = "`write(|w| ..)` method takes [`quetcmap::W`](W) writer structure"]
impl crate :: Writable for QuetcmapSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QUETCMAP to value 0"]
impl crate :: Resettable for QuetcmapSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QUEPRI (rw) register accessor: Queue Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`quepri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quepri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@quepri`]
module"]
# [doc (alias = "QUEPRI")]
pub type Quepri = crate :: Reg < quepri :: QuepriSpec > ; # [doc = "Queue Priority"]
pub mod quepri { # [doc = "Register `QUEPRI` reader"]
pub type R = crate :: R < QuepriSpec > ; # [doc = "Register `QUEPRI` writer"]
pub type W = crate :: W < QuepriSpec > ; # [doc = "Field `PRIQ0` reader - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq0R = crate :: FieldReader ; # [doc = "Field `PRIQ0` writer - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES30` reader - 3:3\\]
RESERVE FIELD"]
pub type Res30R = crate :: BitReader ; # [doc = "Field `RES30` writer - 3:3\\]
RESERVE FIELD"]
pub type Res30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PRIQ1` reader - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq1R = crate :: FieldReader ; # [doc = "Field `PRIQ1` writer - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
pub type Priq1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RES29` reader - 31:7\\]
RESERVE FIELD"]
pub type Res29R = crate :: FieldReader < u32 > ; # [doc = "Field `RES29` writer - 31:7\\]
RESERVE FIELD"]
pub type Res29W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
pub fn priq0 (& self) -> Priq0R { Priq0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res30 (& self) -> Res30R { Res30R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
pub fn priq1 (& self) -> Priq1R { Priq1R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res29 (& self) -> Res29R { Res29R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
# [must_use]
pub fn priq0 (& mut self) -> Priq0W < QuepriSpec > { Priq0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res30 (& mut self) -> Res30W < QuepriSpec > { Res30W :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands."]
# [inline (always)]
# [must_use]
pub fn priq1 (& mut self) -> Priq1W < QuepriSpec > { Priq1W :: new (self , 4) } # [doc = "Bits 7:31 - 31:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res29 (& mut self) -> Res29W < QuepriSpec > { Res29W :: new (self , 7) } } # [doc = "Queue Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`quepri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quepri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QuepriSpec ; impl crate :: RegisterSpec for QuepriSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`quepri::R`](R) reader structure"]
impl crate :: Readable for QuepriSpec { } # [doc = "`write(|w| ..)` method takes [`quepri::W`](W) writer structure"]
impl crate :: Writable for QuepriSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QUEPRI to value 0"]
impl crate :: Resettable for QuepriSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMR (rw) register accessor: Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
module"]
# [doc (alias = "EMR")]
pub type Emr = crate :: Reg < emr :: EmrSpec > ; # [doc = "Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
pub mod emr { # [doc = "Register `EMR` reader"]
pub type R = crate :: R < EmrSpec > ; # [doc = "Register `EMR` writer"]
pub type W = crate :: W < EmrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event Missed #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event Missed #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event Missed #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event Missed #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event Missed #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event Missed #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event Missed #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event Missed #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event Missed #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event Missed #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event Missed #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event Missed #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event Missed #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event Missed #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event Missed #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event Missed #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event Missed #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event Missed #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event Missed #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event Missed #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event Missed #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event Missed #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event Missed #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event Missed #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event Missed #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event Missed #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event Missed #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event Missed #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event Missed #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event Missed #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event Missed #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event Missed #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event Missed #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event Missed #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event Missed #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event Missed #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event Missed #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event Missed #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event Missed #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event Missed #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event Missed #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event Missed #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event Missed #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event Missed #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event Missed #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event Missed #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event Missed #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event Missed #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EmrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EmrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EmrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EmrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EmrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EmrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EmrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EmrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EmrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EmrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EmrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EmrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EmrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EmrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EmrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EmrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EmrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EmrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EmrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EmrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EmrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EmrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EmrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EmrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EmrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EmrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EmrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EmrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EmrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EmrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EmrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EmrSpec > { E31W :: new (self , 31) } } # [doc = "Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmrSpec ; impl crate :: RegisterSpec for EmrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emr::R`](R) reader structure"]
impl crate :: Readable for EmrSpec { } # [doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"]
impl crate :: Writable for EmrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMR to value 0"]
impl crate :: Resettable for EmrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMRH (rw) register accessor: Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emrh`]
module"]
# [doc (alias = "EMRH")]
pub type Emrh = crate :: Reg < emrh :: EmrhSpec > ; # [doc = "Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
pub mod emrh { # [doc = "Register `EMRH` reader"]
pub type R = crate :: R < EmrhSpec > ; # [doc = "Register `EMRH` writer"]
pub type W = crate :: W < EmrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event Missed #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event Missed #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event Missed #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event Missed #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event Missed #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event Missed #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event Missed #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event Missed #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event Missed #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event Missed #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event Missed #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event Missed #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event Missed #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event Missed #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event Missed #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event Missed #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event Missed #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event Missed #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event Missed #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event Missed #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event Missed #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event Missed #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event Missed #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event Missed #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event Missed #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event Missed #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event Missed #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event Missed #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event Missed #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event Missed #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event Missed #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event Missed #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event Missed #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event Missed #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event Missed #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event Missed #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event Missed #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event Missed #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event Missed #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event Missed #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event Missed #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event Missed #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event Missed #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event Missed #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event Missed #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event Missed #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event Missed #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event Missed #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event Missed #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event Missed #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event Missed #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event Missed #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event Missed #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event Missed #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event Missed #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event Missed #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event Missed #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event Missed #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event Missed #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event Missed #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event Missed #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event Missed #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event Missed #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event Missed #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EmrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EmrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EmrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EmrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EmrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EmrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EmrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EmrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EmrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EmrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EmrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EmrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EmrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EmrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EmrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EmrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EmrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EmrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EmrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EmrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EmrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EmrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EmrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EmrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EmrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EmrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EmrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EmrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EmrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EmrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EmrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EmrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`emrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmrhSpec ; impl crate :: RegisterSpec for EmrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emrh::R`](R) reader structure"]
impl crate :: Readable for EmrhSpec { } # [doc = "`write(|w| ..)` method takes [`emrh::W`](W) writer structure"]
impl crate :: Writable for EmrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMRH to value 0"]
impl crate :: Resettable for EmrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMCR (rw) register accessor: Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emcr`]
module"]
# [doc (alias = "EMCR")]
pub type Emcr = crate :: Reg < emcr :: EmcrSpec > ; # [doc = "Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
pub mod emcr { # [doc = "Register `EMCR` reader"]
pub type R = crate :: R < EmcrSpec > ; # [doc = "Register `EMCR` writer"]
pub type W = crate :: W < EmcrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed Clear #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed Clear #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed Clear #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed Clear #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed Clear #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed Clear #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed Clear #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed Clear #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed Clear #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed Clear #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed Clear #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed Clear #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed Clear #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed Clear #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed Clear #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed Clear #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event Missed Clear #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event Missed Clear #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event Missed Clear #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event Missed Clear #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event Missed Clear #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event Missed Clear #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event Missed Clear #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event Missed Clear #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event Missed Clear #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event Missed Clear #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event Missed Clear #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event Missed Clear #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event Missed Clear #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event Missed Clear #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event Missed Clear #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event Missed Clear #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event Missed Clear #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event Missed Clear #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event Missed Clear #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event Missed Clear #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event Missed Clear #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event Missed Clear #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event Missed Clear #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event Missed Clear #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event Missed Clear #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event Missed Clear #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event Missed Clear #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event Missed Clear #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event Missed Clear #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event Missed Clear #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event Missed Clear #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event Missed Clear #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event Missed Clear #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event Missed Clear #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event Missed Clear #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event Missed Clear #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event Missed Clear #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event Missed Clear #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event Missed Clear #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event Missed Clear #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event Missed Clear #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event Missed Clear #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event Missed Clear #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event Missed Clear #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event Missed Clear #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event Missed Clear #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event Missed Clear #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event Missed Clear #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EmcrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EmcrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EmcrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EmcrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EmcrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EmcrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EmcrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EmcrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EmcrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EmcrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EmcrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EmcrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EmcrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EmcrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EmcrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EmcrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EmcrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EmcrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EmcrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EmcrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EmcrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EmcrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EmcrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EmcrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EmcrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EmcrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EmcrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EmcrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EmcrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EmcrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EmcrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EmcrSpec > { E31W :: new (self , 31) } } # [doc = "Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmcrSpec ; impl crate :: RegisterSpec for EmcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emcr::R`](R) reader structure"]
impl crate :: Readable for EmcrSpec { } # [doc = "`write(|w| ..)` method takes [`emcr::W`](W) writer structure"]
impl crate :: Writable for EmcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMCR to value 0"]
impl crate :: Resettable for EmcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EMCRH (rw) register accessor: Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emcrh`]
module"]
# [doc (alias = "EMCRH")]
pub type Emcrh = crate :: Reg < emcrh :: EmcrhSpec > ; # [doc = "Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
pub mod emcrh { # [doc = "Register `EMCRH` reader"]
pub type R = crate :: R < EmcrhSpec > ; # [doc = "Register `EMCRH` writer"]
pub type W = crate :: W < EmcrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event Missed Clear #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event Missed Clear #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event Missed Clear #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event Missed Clear #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event Missed Clear #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event Missed Clear #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event Missed Clear #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event Missed Clear #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event Missed Clear #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event Missed Clear #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event Missed Clear #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event Missed Clear #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event Missed Clear #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event Missed Clear #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event Missed Clear #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event Missed Clear #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event Missed Clear #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event Missed Clear #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event Missed Clear #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event Missed Clear #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event Missed Clear #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event Missed Clear #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event Missed Clear #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event Missed Clear #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event Missed Clear #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event Missed Clear #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event Missed Clear #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event Missed Clear #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event Missed Clear #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event Missed Clear #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event Missed Clear #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event Missed Clear #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event Missed Clear #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event Missed Clear #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event Missed Clear #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event Missed Clear #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event Missed Clear #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event Missed Clear #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event Missed Clear #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event Missed Clear #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event Missed Clear #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event Missed Clear #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event Missed Clear #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event Missed Clear #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event Missed Clear #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event Missed Clear #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event Missed Clear #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event Missed Clear #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event Missed Clear #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event Missed Clear #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event Missed Clear #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event Missed Clear #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event Missed Clear #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event Missed Clear #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event Missed Clear #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event Missed Clear #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event Missed Clear #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event Missed Clear #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event Missed Clear #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event Missed Clear #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event Missed Clear #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event Missed Clear #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event Missed Clear #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event Missed Clear #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EmcrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EmcrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EmcrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EmcrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EmcrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EmcrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EmcrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EmcrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event Missed Clear #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EmcrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event Missed Clear #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EmcrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event Missed Clear #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EmcrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event Missed Clear #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EmcrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event Missed Clear #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EmcrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event Missed Clear #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EmcrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event Missed Clear #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EmcrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event Missed Clear #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EmcrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event Missed Clear #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EmcrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event Missed Clear #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EmcrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event Missed Clear #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EmcrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event Missed Clear #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EmcrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event Missed Clear #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EmcrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event Missed Clear #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EmcrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event Missed Clear #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EmcrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event Missed Clear #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EmcrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event Missed Clear #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EmcrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event Missed Clear #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EmcrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event Missed Clear #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EmcrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event Missed Clear #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EmcrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event Missed Clear #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EmcrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event Missed Clear #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EmcrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event Missed Clear #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EmcrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event Missed Clear #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EmcrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`emcrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emcrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmcrhSpec ; impl crate :: RegisterSpec for EmcrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`emcrh::R`](R) reader structure"]
impl crate :: Readable for EmcrhSpec { } # [doc = "`write(|w| ..)` method takes [`emcrh::W`](W) writer structure"]
impl crate :: Writable for EmcrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EMCRH to value 0"]
impl crate :: Resettable for EmcrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEMR (rw) register accessor: QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qemr`]
module"]
# [doc (alias = "QEMR")]
pub type Qemr = crate :: Reg < qemr :: QemrSpec > ; # [doc = "QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt."]
pub mod qemr { # [doc = "Register `QEMR` reader"]
pub type R = crate :: R < QemrSpec > ; # [doc = "Register `QEMR` writer"]
pub type W = crate :: W < QemrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES31` reader - 31:8\\]
RESERVE FIELD"]
pub type Res31R = crate :: FieldReader < u32 > ; # [doc = "Field `RES31` writer - 31:8\\]
RESERVE FIELD"]
pub type Res31W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res31 (& self) -> Res31R { Res31R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QemrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QemrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QemrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QemrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QemrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QemrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QemrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QemrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res31 (& mut self) -> Res31W < QemrSpec > { Res31W :: new (self , 8) } } # [doc = "QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QemrSpec ; impl crate :: RegisterSpec for QemrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qemr::R`](R) reader structure"]
impl crate :: Readable for QemrSpec { } # [doc = "`write(|w| ..)` method takes [`qemr::W`](W) writer structure"]
impl crate :: Writable for QemrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEMR to value 0"]
impl crate :: Resettable for QemrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEMCR (rw) register accessor: QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qemcr`]
module"]
# [doc (alias = "QEMCR")]
pub type Qemcr = crate :: Reg < qemcr :: QemcrSpec > ; # [doc = "QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."]
pub mod qemcr { # [doc = "Register `QEMCR` reader"]
pub type R = crate :: R < QemcrSpec > ; # [doc = "Register `QEMCR` writer"]
pub type W = crate :: W < QemcrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event Missed Clear #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event Missed Clear #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event Missed Clear #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event Missed Clear #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event Missed Clear #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event Missed Clear #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event Missed Clear #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event Missed Clear #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event Missed Clear #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event Missed Clear #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event Missed Clear #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event Missed Clear #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event Missed Clear #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event Missed Clear #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event Missed Clear #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event Missed Clear #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES32` reader - 31:8\\]
RESERVE FIELD"]
pub type Res32R = crate :: FieldReader < u32 > ; # [doc = "Field `RES32` writer - 31:8\\]
RESERVE FIELD"]
pub type Res32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res32 (& self) -> Res32R { Res32R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event Missed Clear #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QemcrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event Missed Clear #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QemcrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event Missed Clear #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QemcrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event Missed Clear #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QemcrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event Missed Clear #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QemcrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event Missed Clear #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QemcrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event Missed Clear #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QemcrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event Missed Clear #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QemcrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res32 (& mut self) -> Res32W < QemcrSpec > { Res32W :: new (self , 8) } } # [doc = "QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`qemcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qemcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QemcrSpec ; impl crate :: RegisterSpec for QemcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qemcr::R`](R) reader structure"]
impl crate :: Readable for QemcrSpec { } # [doc = "`write(|w| ..)` method takes [`qemcr::W`](W) writer structure"]
impl crate :: Writable for QemcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEMCR to value 0"]
impl crate :: Resettable for QemcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCERR (rw) register accessor: CC Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccerr`]
module"]
# [doc (alias = "CCERR")]
pub type Ccerr = crate :: Reg < ccerr :: CcerrSpec > ; # [doc = "CC Error Register"]
pub mod ccerr { # [doc = "Register `CCERR` reader"]
pub type R = crate :: R < CcerrSpec > ; # [doc = "Register `CCERR` writer"]
pub type W = crate :: W < CcerrSpec > ; # [doc = "Field `QTHRXCD0` reader - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd0R = crate :: BitReader ; # [doc = "Field `QTHRXCD0` writer - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD1` reader - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd1R = crate :: BitReader ; # [doc = "Field `QTHRXCD1` writer - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD2` reader - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd2R = crate :: BitReader ; # [doc = "Field `QTHRXCD2` writer - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD3` reader - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd3R = crate :: BitReader ; # [doc = "Field `QTHRXCD3` writer - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD4` reader - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd4R = crate :: BitReader ; # [doc = "Field `QTHRXCD4` writer - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD5` reader - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd5R = crate :: BitReader ; # [doc = "Field `QTHRXCD5` writer - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD6` reader - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd6R = crate :: BitReader ; # [doc = "Field `QTHRXCD6` writer - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD7` reader - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd7R = crate :: BitReader ; # [doc = "Field `QTHRXCD7` writer - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
pub type Qthrxcd7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES34` reader - 15:8\\]
RESERVE FIELD"]
pub type Res34R = crate :: FieldReader ; # [doc = "Field `RES34` writer - 15:8\\]
RESERVE FIELD"]
pub type Res34W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TCERR` reader - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
pub type TcerrR = crate :: BitReader ; # [doc = "Field `TCERR` writer - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
pub type TcerrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES33` reader - 31:17\\]
RESERVE FIELD"]
pub type Res33R = crate :: FieldReader < u16 > ; # [doc = "Field `RES33` writer - 31:17\\]
RESERVE FIELD"]
pub type Res33W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd0 (& self) -> Qthrxcd0R { Qthrxcd0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd1 (& self) -> Qthrxcd1R { Qthrxcd1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd2 (& self) -> Qthrxcd2R { Qthrxcd2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd3 (& self) -> Qthrxcd3R { Qthrxcd3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd4 (& self) -> Qthrxcd4R { Qthrxcd4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd5 (& self) -> Qthrxcd5R { Qthrxcd5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd6 (& self) -> Qthrxcd6R { Qthrxcd6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
pub fn qthrxcd7 (& self) -> Qthrxcd7R { Qthrxcd7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res34 (& self) -> Res34R { Res34R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
pub fn tcerr (& self) -> TcerrR { TcerrR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res33 (& self) -> Res33R { Res33R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd0 (& mut self) -> Qthrxcd0W < CcerrSpec > { Qthrxcd0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd1 (& mut self) -> Qthrxcd1W < CcerrSpec > { Qthrxcd1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd2 (& mut self) -> Qthrxcd2W < CcerrSpec > { Qthrxcd2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd3 (& mut self) -> Qthrxcd3W < CcerrSpec > { Qthrxcd3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd4 (& mut self) -> Qthrxcd4W < CcerrSpec > { Qthrxcd4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd5 (& mut self) -> Qthrxcd5W < CcerrSpec > { Qthrxcd5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd6 (& mut self) -> Qthrxcd6W < CcerrSpec > { Qthrxcd6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn qthrxcd7 (& mut self) -> Qthrxcd7W < CcerrSpec > { Qthrxcd7W :: new (self , 7) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res34 (& mut self) -> Res34W < CcerrSpec > { Res34W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt."]
# [inline (always)]
# [must_use]
pub fn tcerr (& mut self) -> TcerrW < CcerrSpec > { TcerrW :: new (self , 16) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res33 (& mut self) -> Res33W < CcerrSpec > { Res33W :: new (self , 17) } } # [doc = "CC Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcerrSpec ; impl crate :: RegisterSpec for CcerrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccerr::R`](R) reader structure"]
impl crate :: Readable for CcerrSpec { } # [doc = "`write(|w| ..)` method takes [`ccerr::W`](W) writer structure"]
impl crate :: Writable for CcerrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCERR to value 0"]
impl crate :: Resettable for CcerrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCERRCLR (rw) register accessor: CC Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerrclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerrclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccerrclr`]
module"]
# [doc (alias = "CCERRCLR")]
pub type Ccerrclr = crate :: Reg < ccerrclr :: CcerrclrSpec > ; # [doc = "CC Error Clear Register"]
pub mod ccerrclr { # [doc = "Register `CCERRCLR` reader"]
pub type R = crate :: R < CcerrclrSpec > ; # [doc = "Register `CCERRCLR` writer"]
pub type W = crate :: W < CcerrclrSpec > ; # [doc = "Field `QTHRXCD0` reader - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
pub type Qthrxcd0R = crate :: BitReader ; # [doc = "Field `QTHRXCD0` writer - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
pub type Qthrxcd0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD1` reader - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
pub type Qthrxcd1R = crate :: BitReader ; # [doc = "Field `QTHRXCD1` writer - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
pub type Qthrxcd1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD2` reader - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
pub type Qthrxcd2R = crate :: BitReader ; # [doc = "Field `QTHRXCD2` writer - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
pub type Qthrxcd2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD3` reader - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
pub type Qthrxcd3R = crate :: BitReader ; # [doc = "Field `QTHRXCD3` writer - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
pub type Qthrxcd3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD4` reader - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
pub type Qthrxcd4R = crate :: BitReader ; # [doc = "Field `QTHRXCD4` writer - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
pub type Qthrxcd4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD5` reader - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
pub type Qthrxcd5R = crate :: BitReader ; # [doc = "Field `QTHRXCD5` writer - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
pub type Qthrxcd5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD6` reader - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
pub type Qthrxcd6R = crate :: BitReader ; # [doc = "Field `QTHRXCD6` writer - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
pub type Qthrxcd6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QTHRXCD7` reader - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
pub type Qthrxcd7R = crate :: BitReader ; # [doc = "Field `QTHRXCD7` writer - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
pub type Qthrxcd7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES36` reader - 15:8\\]
RESERVE FIELD"]
pub type Res36R = crate :: FieldReader ; # [doc = "Field `RES36` writer - 15:8\\]
RESERVE FIELD"]
pub type Res36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `TCERR` reader - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
pub type TcerrR = crate :: BitReader ; # [doc = "Field `TCERR` writer - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
pub type TcerrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES35` reader - 31:17\\]
RESERVE FIELD"]
pub type Res35R = crate :: FieldReader < u16 > ; # [doc = "Field `RES35` writer - 31:17\\]
RESERVE FIELD"]
pub type Res35W < 'a , REG > = crate :: FieldWriter < 'a , REG , 15 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd0 (& self) -> Qthrxcd0R { Qthrxcd0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd1 (& self) -> Qthrxcd1R { Qthrxcd1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd2 (& self) -> Qthrxcd2R { Qthrxcd2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd3 (& self) -> Qthrxcd3R { Qthrxcd3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd4 (& self) -> Qthrxcd4R { Qthrxcd4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd5 (& self) -> Qthrxcd5R { Qthrxcd5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd6 (& self) -> Qthrxcd6R { Qthrxcd6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
# [inline (always)]
pub fn qthrxcd7 (& self) -> Qthrxcd7R { Qthrxcd7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res36 (& self) -> Res36R { Res36R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
# [inline (always)]
pub fn tcerr (& self) -> TcerrR { TcerrR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res35 (& self) -> Res35R { Res35R :: new (((self . bits >> 17) & 0x7fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd0 (& mut self) -> Qthrxcd0W < CcerrclrSpec > { Qthrxcd0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd1 (& mut self) -> Qthrxcd1W < CcerrclrSpec > { Qthrxcd1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd2 (& mut self) -> Qthrxcd2W < CcerrclrSpec > { Qthrxcd2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd3 (& mut self) -> Qthrxcd3W < CcerrclrSpec > { Qthrxcd3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd4 (& mut self) -> Qthrxcd4W < CcerrclrSpec > { Qthrxcd4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd5 (& mut self) -> Qthrxcd5W < CcerrclrSpec > { Qthrxcd5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd6 (& mut self) -> Qthrxcd6W < CcerrclrSpec > { Qthrxcd6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn qthrxcd7 (& mut self) -> Qthrxcd7W < CcerrclrSpec > { Qthrxcd7W :: new (self , 7) } # [doc = "Bits 8:15 - 15:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res36 (& mut self) -> Res36W < CcerrclrSpec > { Res36W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect."]
# [inline (always)]
# [must_use]
pub fn tcerr (& mut self) -> TcerrW < CcerrclrSpec > { TcerrW :: new (self , 16) } # [doc = "Bits 17:31 - 31:17\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res35 (& mut self) -> Res35W < CcerrclrSpec > { Res35W :: new (self , 17) } } # [doc = "CC Error Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccerrclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccerrclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcerrclrSpec ; impl crate :: RegisterSpec for CcerrclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccerrclr::R`](R) reader structure"]
impl crate :: Readable for CcerrclrSpec { } # [doc = "`write(|w| ..)` method takes [`ccerrclr::W`](W) writer structure"]
impl crate :: Writable for CcerrclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCERRCLR to value 0"]
impl crate :: Resettable for CcerrclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EEVAL (rw) register accessor: Error Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eeval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eeval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eeval`]
module"]
# [doc (alias = "EEVAL")]
pub type Eeval = crate :: Reg < eeval :: EevalSpec > ; # [doc = "Error Eval Register"]
pub mod eeval { # [doc = "Register `EEVAL` reader"]
pub type R = crate :: R < EevalSpec > ; # [doc = "Register `EEVAL` writer"]
pub type W = crate :: W < EevalSpec > ; # [doc = "Field `EVAL` reader - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
pub type EvalR = crate :: BitReader ; # [doc = "Field `EVAL` writer - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
pub type EvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET` reader - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
pub type SetR = crate :: BitReader ; # [doc = "Field `SET` writer - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES37` reader - 31:2\\]
RESERVE FIELD"]
pub type Res37R = crate :: FieldReader < u32 > ; # [doc = "Field `RES37` writer - 31:2\\]
RESERVE FIELD"]
pub type Res37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
# [inline (always)]
pub fn eval (& self) -> EvalR { EvalR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res37 (& self) -> Res37R { Res37R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn eval (& mut self) -> EvalW < EevalSpec > { EvalW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < EevalSpec > { SetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res37 (& mut self) -> Res37W < EevalSpec > { Res37W :: new (self , 2) } } # [doc = "Error Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eeval::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eeval::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EevalSpec ; impl crate :: RegisterSpec for EevalSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eeval::R`](R) reader structure"]
impl crate :: Readable for EevalSpec { } # [doc = "`write(|w| ..)` method takes [`eeval::W`](W) writer structure"]
impl crate :: Writable for EevalSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EEVAL to value 0"]
impl crate :: Resettable for EevalSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DRAEM (rw) register accessor: DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@draem`]
module"]
# [doc (alias = "DRAEM")]
pub type Draem = crate :: Reg < draem :: DraemSpec > ; # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
pub mod draem { # [doc = "Register `DRAEM` reader"]
pub type R = crate :: R < DraemSpec > ; # [doc = "Register `DRAEM` writer"]
pub type W = crate :: W < DraemSpec > ; # [doc = "Field `E0` reader - 0:0\\]
DMA Region Access enable for Region M bit #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
DMA Region Access enable for Region M bit #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
DMA Region Access enable for Region M bit #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
DMA Region Access enable for Region M bit #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
DMA Region Access enable for Region M bit #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
DMA Region Access enable for Region M bit #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
DMA Region Access enable for Region M bit #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
DMA Region Access enable for Region M bit #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
DMA Region Access enable for Region M bit #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
DMA Region Access enable for Region M bit #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
DMA Region Access enable for Region M bit #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
DMA Region Access enable for Region M bit #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
DMA Region Access enable for Region M bit #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
DMA Region Access enable for Region M bit #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
DMA Region Access enable for Region M bit #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
DMA Region Access enable for Region M bit #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
DMA Region Access enable for Region M bit #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
DMA Region Access enable for Region M bit #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
DMA Region Access enable for Region M bit #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
DMA Region Access enable for Region M bit #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
DMA Region Access enable for Region M bit #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
DMA Region Access enable for Region M bit #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
DMA Region Access enable for Region M bit #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
DMA Region Access enable for Region M bit #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
DMA Region Access enable for Region M bit #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
DMA Region Access enable for Region M bit #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
DMA Region Access enable for Region M bit #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
DMA Region Access enable for Region M bit #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
DMA Region Access enable for Region M bit #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
DMA Region Access enable for Region M bit #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
DMA Region Access enable for Region M bit #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
DMA Region Access enable for Region M bit #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
DMA Region Access enable for Region M bit #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
DMA Region Access enable for Region M bit #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
DMA Region Access enable for Region M bit #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
DMA Region Access enable for Region M bit #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
DMA Region Access enable for Region M bit #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
DMA Region Access enable for Region M bit #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
DMA Region Access enable for Region M bit #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
DMA Region Access enable for Region M bit #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
DMA Region Access enable for Region M bit #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
DMA Region Access enable for Region M bit #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
DMA Region Access enable for Region M bit #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
DMA Region Access enable for Region M bit #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
DMA Region Access enable for Region M bit #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
DMA Region Access enable for Region M bit #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
DMA Region Access enable for Region M bit #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
DMA Region Access enable for Region M bit #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
DMA Region Access enable for Region M bit #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
DMA Region Access enable for Region M bit #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
DMA Region Access enable for Region M bit #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
DMA Region Access enable for Region M bit #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
DMA Region Access enable for Region M bit #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
DMA Region Access enable for Region M bit #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
DMA Region Access enable for Region M bit #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
DMA Region Access enable for Region M bit #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
DMA Region Access enable for Region M bit #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
DMA Region Access enable for Region M bit #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
DMA Region Access enable for Region M bit #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
DMA Region Access enable for Region M bit #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
DMA Region Access enable for Region M bit #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
DMA Region Access enable for Region M bit #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
DMA Region Access enable for Region M bit #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
DMA Region Access enable for Region M bit #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < DraemSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < DraemSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < DraemSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < DraemSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < DraemSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < DraemSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < DraemSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < DraemSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < DraemSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < DraemSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < DraemSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < DraemSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < DraemSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < DraemSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < DraemSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < DraemSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < DraemSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < DraemSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < DraemSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < DraemSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < DraemSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < DraemSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < DraemSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < DraemSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < DraemSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < DraemSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < DraemSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < DraemSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < DraemSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < DraemSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < DraemSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < DraemSpec > { E31W :: new (self , 31) } } # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DraemSpec ; impl crate :: RegisterSpec for DraemSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`draem::R`](R) reader structure"]
impl crate :: Readable for DraemSpec { } # [doc = "`write(|w| ..)` method takes [`draem::W`](W) writer structure"]
impl crate :: Writable for DraemSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DRAEM to value 0"]
impl crate :: Resettable for DraemSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DRAEHM (rw) register accessor: DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draehm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draehm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@draehm`]
module"]
# [doc (alias = "DRAEHM")]
pub type Draehm = crate :: Reg < draehm :: DraehmSpec > ; # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt."]
pub mod draehm { # [doc = "Register `DRAEHM` reader"]
pub type R = crate :: R < DraehmSpec > ; # [doc = "Register `DRAEHM` writer"]
pub type W = crate :: W < DraehmSpec > ; # [doc = "Field `E32` reader - 0:0\\]
DMA Region Access enable for Region M bit #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
DMA Region Access enable for Region M bit #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
DMA Region Access enable for Region M bit #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
DMA Region Access enable for Region M bit #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
DMA Region Access enable for Region M bit #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
DMA Region Access enable for Region M bit #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
DMA Region Access enable for Region M bit #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
DMA Region Access enable for Region M bit #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
DMA Region Access enable for Region M bit #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
DMA Region Access enable for Region M bit #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
DMA Region Access enable for Region M bit #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
DMA Region Access enable for Region M bit #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
DMA Region Access enable for Region M bit #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
DMA Region Access enable for Region M bit #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
DMA Region Access enable for Region M bit #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
DMA Region Access enable for Region M bit #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
DMA Region Access enable for Region M bit #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
DMA Region Access enable for Region M bit #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
DMA Region Access enable for Region M bit #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
DMA Region Access enable for Region M bit #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
DMA Region Access enable for Region M bit #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
DMA Region Access enable for Region M bit #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
DMA Region Access enable for Region M bit #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
DMA Region Access enable for Region M bit #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
DMA Region Access enable for Region M bit #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
DMA Region Access enable for Region M bit #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
DMA Region Access enable for Region M bit #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
DMA Region Access enable for Region M bit #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
DMA Region Access enable for Region M bit #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
DMA Region Access enable for Region M bit #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
DMA Region Access enable for Region M bit #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
DMA Region Access enable for Region M bit #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
DMA Region Access enable for Region M bit #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
DMA Region Access enable for Region M bit #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
DMA Region Access enable for Region M bit #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
DMA Region Access enable for Region M bit #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
DMA Region Access enable for Region M bit #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
DMA Region Access enable for Region M bit #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
DMA Region Access enable for Region M bit #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
DMA Region Access enable for Region M bit #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
DMA Region Access enable for Region M bit #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
DMA Region Access enable for Region M bit #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
DMA Region Access enable for Region M bit #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
DMA Region Access enable for Region M bit #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
DMA Region Access enable for Region M bit #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
DMA Region Access enable for Region M bit #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
DMA Region Access enable for Region M bit #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
DMA Region Access enable for Region M bit #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
DMA Region Access enable for Region M bit #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
DMA Region Access enable for Region M bit #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
DMA Region Access enable for Region M bit #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
DMA Region Access enable for Region M bit #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
DMA Region Access enable for Region M bit #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
DMA Region Access enable for Region M bit #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
DMA Region Access enable for Region M bit #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
DMA Region Access enable for Region M bit #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
DMA Region Access enable for Region M bit #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
DMA Region Access enable for Region M bit #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
DMA Region Access enable for Region M bit #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
DMA Region Access enable for Region M bit #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
DMA Region Access enable for Region M bit #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
DMA Region Access enable for Region M bit #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
DMA Region Access enable for Region M bit #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
DMA Region Access enable for Region M bit #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
DMA Region Access enable for Region M bit #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < DraehmSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DMA Region Access enable for Region M bit #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < DraehmSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
DMA Region Access enable for Region M bit #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < DraehmSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
DMA Region Access enable for Region M bit #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < DraehmSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
DMA Region Access enable for Region M bit #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < DraehmSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
DMA Region Access enable for Region M bit #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < DraehmSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
DMA Region Access enable for Region M bit #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < DraehmSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
DMA Region Access enable for Region M bit #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < DraehmSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
DMA Region Access enable for Region M bit #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < DraehmSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
DMA Region Access enable for Region M bit #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < DraehmSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
DMA Region Access enable for Region M bit #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < DraehmSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
DMA Region Access enable for Region M bit #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < DraehmSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
DMA Region Access enable for Region M bit #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < DraehmSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
DMA Region Access enable for Region M bit #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < DraehmSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
DMA Region Access enable for Region M bit #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < DraehmSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Region Access enable for Region M bit #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < DraehmSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
DMA Region Access enable for Region M bit #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < DraehmSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
DMA Region Access enable for Region M bit #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < DraehmSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
DMA Region Access enable for Region M bit #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < DraehmSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
DMA Region Access enable for Region M bit #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < DraehmSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
DMA Region Access enable for Region M bit #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < DraehmSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
DMA Region Access enable for Region M bit #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < DraehmSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
DMA Region Access enable for Region M bit #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < DraehmSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
DMA Region Access enable for Region M bit #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < DraehmSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
DMA Region Access enable for Region M bit #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < DraehmSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
DMA Region Access enable for Region M bit #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < DraehmSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
DMA Region Access enable for Region M bit #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < DraehmSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
DMA Region Access enable for Region M bit #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < DraehmSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
DMA Region Access enable for Region M bit #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < DraehmSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
DMA Region Access enable for Region M bit #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < DraehmSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
DMA Region Access enable for Region M bit #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < DraehmSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
DMA Region Access enable for Region M bit #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < DraehmSpec > { E63W :: new (self , 31) } } # [doc = "DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`draehm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`draehm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DraehmSpec ; impl crate :: RegisterSpec for DraehmSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`draehm::R`](R) reader structure"]
impl crate :: Readable for DraehmSpec { } # [doc = "`write(|w| ..)` method takes [`draehm::W`](W) writer structure"]
impl crate :: Writable for DraehmSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DRAEHM to value 0"]
impl crate :: Resettable for DraehmSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QRAEN (rw) register accessor: QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qraen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qraen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qraen`]
module"]
# [doc (alias = "QRAEN")]
pub type Qraen = crate :: Reg < qraen :: QraenSpec > ; # [doc = "QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt."]
pub mod qraen { # [doc = "Register `QRAEN` reader"]
pub type R = crate :: R < QraenSpec > ; # [doc = "Register `QRAEN` writer"]
pub type W = crate :: W < QraenSpec > ; # [doc = "Field `E0` reader - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES38` reader - 31:8\\]
RESERVE FIELD"]
pub type Res38R = crate :: FieldReader < u32 > ; # [doc = "Field `RES38` writer - 31:8\\]
RESERVE FIELD"]
pub type Res38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res38 (& self) -> Res38R { Res38R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
QDMA Region Access enable for Region M bit #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QraenSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Region Access enable for Region M bit #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QraenSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
QDMA Region Access enable for Region M bit #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QraenSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
QDMA Region Access enable for Region M bit #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QraenSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
QDMA Region Access enable for Region M bit #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QraenSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
QDMA Region Access enable for Region M bit #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QraenSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
QDMA Region Access enable for Region M bit #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QraenSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
QDMA Region Access enable for Region M bit #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QraenSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res38 (& mut self) -> Res38W < QraenSpec > { Res38W :: new (self , 8) } } # [doc = "QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`qraen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qraen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QraenSpec ; impl crate :: RegisterSpec for QraenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qraen::R`](R) reader structure"]
impl crate :: Readable for QraenSpec { } # [doc = "`write(|w| ..)` method takes [`qraen::W`](W) writer structure"]
impl crate :: Writable for QraenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QRAEN to value 0"]
impl crate :: Resettable for QraenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE0 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne0`]
module"]
# [doc (alias = "QNE0")]
pub type Qne0 = crate :: Reg < qne0 :: Qne0Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 0"]
pub mod qne0 { # [doc = "Register `QNE0` reader"]
pub type R = crate :: R < Qne0Spec > ; # [doc = "Register `QNE0` writer"]
pub type W = crate :: W < Qne0Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES39` reader - 31:8\\]
RESERVE FIELD"]
pub type Res39R = crate :: FieldReader < u32 > ; # [doc = "Field `RES39` writer - 31:8\\]
RESERVE FIELD"]
pub type Res39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res39 (& self) -> Res39R { Res39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne0Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne0Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res39 (& mut self) -> Res39W < Qne0Spec > { Res39W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne0Spec ; impl crate :: RegisterSpec for Qne0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne0::R`](R) reader structure"]
impl crate :: Readable for Qne0Spec { } # [doc = "`write(|w| ..)` method takes [`qne0::W`](W) writer structure"]
impl crate :: Writable for Qne0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE0 to value 0"]
impl crate :: Resettable for Qne0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE1 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 1\n\nYou can [`read`](crate::Reg::read) this register and get [`qne1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne1`]
module"]
# [doc (alias = "QNE1")]
pub type Qne1 = crate :: Reg < qne1 :: Qne1Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 1"]
pub mod qne1 { # [doc = "Register `QNE1` reader"]
pub type R = crate :: R < Qne1Spec > ; # [doc = "Register `QNE1` writer"]
pub type W = crate :: W < Qne1Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES40` reader - 31:8\\]
RESERVE FIELD"]
pub type Res40R = crate :: FieldReader < u32 > ; # [doc = "Field `RES40` writer - 31:8\\]
RESERVE FIELD"]
pub type Res40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res40 (& self) -> Res40R { Res40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne1Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne1Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res40 (& mut self) -> Res40W < Qne1Spec > { Res40W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 1\n\nYou can [`read`](crate::Reg::read) this register and get [`qne1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne1Spec ; impl crate :: RegisterSpec for Qne1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne1::R`](R) reader structure"]
impl crate :: Readable for Qne1Spec { } # [doc = "`write(|w| ..)` method takes [`qne1::W`](W) writer structure"]
impl crate :: Writable for Qne1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE1 to value 0"]
impl crate :: Resettable for Qne1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE2 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 2\n\nYou can [`read`](crate::Reg::read) this register and get [`qne2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne2`]
module"]
# [doc (alias = "QNE2")]
pub type Qne2 = crate :: Reg < qne2 :: Qne2Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 2"]
pub mod qne2 { # [doc = "Register `QNE2` reader"]
pub type R = crate :: R < Qne2Spec > ; # [doc = "Register `QNE2` writer"]
pub type W = crate :: W < Qne2Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES41` reader - 31:8\\]
RESERVE FIELD"]
pub type Res41R = crate :: FieldReader < u32 > ; # [doc = "Field `RES41` writer - 31:8\\]
RESERVE FIELD"]
pub type Res41W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res41 (& self) -> Res41R { Res41R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne2Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne2Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res41 (& mut self) -> Res41W < Qne2Spec > { Res41W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 2\n\nYou can [`read`](crate::Reg::read) this register and get [`qne2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne2Spec ; impl crate :: RegisterSpec for Qne2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne2::R`](R) reader structure"]
impl crate :: Readable for Qne2Spec { } # [doc = "`write(|w| ..)` method takes [`qne2::W`](W) writer structure"]
impl crate :: Writable for Qne2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE2 to value 0"]
impl crate :: Resettable for Qne2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE3 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 3\n\nYou can [`read`](crate::Reg::read) this register and get [`qne3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne3`]
module"]
# [doc (alias = "QNE3")]
pub type Qne3 = crate :: Reg < qne3 :: Qne3Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 3"]
pub mod qne3 { # [doc = "Register `QNE3` reader"]
pub type R = crate :: R < Qne3Spec > ; # [doc = "Register `QNE3` writer"]
pub type W = crate :: W < Qne3Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES42` reader - 31:8\\]
RESERVE FIELD"]
pub type Res42R = crate :: FieldReader < u32 > ; # [doc = "Field `RES42` writer - 31:8\\]
RESERVE FIELD"]
pub type Res42W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res42 (& self) -> Res42R { Res42R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne3Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne3Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res42 (& mut self) -> Res42W < Qne3Spec > { Res42W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 3\n\nYou can [`read`](crate::Reg::read) this register and get [`qne3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne3Spec ; impl crate :: RegisterSpec for Qne3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne3::R`](R) reader structure"]
impl crate :: Readable for Qne3Spec { } # [doc = "`write(|w| ..)` method takes [`qne3::W`](W) writer structure"]
impl crate :: Writable for Qne3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE3 to value 0"]
impl crate :: Resettable for Qne3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE4 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 4\n\nYou can [`read`](crate::Reg::read) this register and get [`qne4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne4`]
module"]
# [doc (alias = "QNE4")]
pub type Qne4 = crate :: Reg < qne4 :: Qne4Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 4"]
pub mod qne4 { # [doc = "Register `QNE4` reader"]
pub type R = crate :: R < Qne4Spec > ; # [doc = "Register `QNE4` writer"]
pub type W = crate :: W < Qne4Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES43` reader - 31:8\\]
RESERVE FIELD"]
pub type Res43R = crate :: FieldReader < u32 > ; # [doc = "Field `RES43` writer - 31:8\\]
RESERVE FIELD"]
pub type Res43W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res43 (& self) -> Res43R { Res43R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne4Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne4Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res43 (& mut self) -> Res43W < Qne4Spec > { Res43W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 4\n\nYou can [`read`](crate::Reg::read) this register and get [`qne4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne4Spec ; impl crate :: RegisterSpec for Qne4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne4::R`](R) reader structure"]
impl crate :: Readable for Qne4Spec { } # [doc = "`write(|w| ..)` method takes [`qne4::W`](W) writer structure"]
impl crate :: Writable for Qne4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE4 to value 0"]
impl crate :: Resettable for Qne4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE5 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 5\n\nYou can [`read`](crate::Reg::read) this register and get [`qne5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne5`]
module"]
# [doc (alias = "QNE5")]
pub type Qne5 = crate :: Reg < qne5 :: Qne5Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 5"]
pub mod qne5 { # [doc = "Register `QNE5` reader"]
pub type R = crate :: R < Qne5Spec > ; # [doc = "Register `QNE5` writer"]
pub type W = crate :: W < Qne5Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES44` reader - 31:8\\]
RESERVE FIELD"]
pub type Res44R = crate :: FieldReader < u32 > ; # [doc = "Field `RES44` writer - 31:8\\]
RESERVE FIELD"]
pub type Res44W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res44 (& self) -> Res44R { Res44R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne5Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne5Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res44 (& mut self) -> Res44W < Qne5Spec > { Res44W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 5\n\nYou can [`read`](crate::Reg::read) this register and get [`qne5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne5Spec ; impl crate :: RegisterSpec for Qne5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne5::R`](R) reader structure"]
impl crate :: Readable for Qne5Spec { } # [doc = "`write(|w| ..)` method takes [`qne5::W`](W) writer structure"]
impl crate :: Writable for Qne5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE5 to value 0"]
impl crate :: Resettable for Qne5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE6 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 6\n\nYou can [`read`](crate::Reg::read) this register and get [`qne6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne6`]
module"]
# [doc (alias = "QNE6")]
pub type Qne6 = crate :: Reg < qne6 :: Qne6Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 6"]
pub mod qne6 { # [doc = "Register `QNE6` reader"]
pub type R = crate :: R < Qne6Spec > ; # [doc = "Register `QNE6` writer"]
pub type W = crate :: W < Qne6Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES45` reader - 31:8\\]
RESERVE FIELD"]
pub type Res45R = crate :: FieldReader < u32 > ; # [doc = "Field `RES45` writer - 31:8\\]
RESERVE FIELD"]
pub type Res45W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res45 (& self) -> Res45R { Res45R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne6Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne6Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res45 (& mut self) -> Res45W < Qne6Spec > { Res45W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 6\n\nYou can [`read`](crate::Reg::read) this register and get [`qne6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne6Spec ; impl crate :: RegisterSpec for Qne6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne6::R`](R) reader structure"]
impl crate :: Readable for Qne6Spec { } # [doc = "`write(|w| ..)` method takes [`qne6::W`](W) writer structure"]
impl crate :: Writable for Qne6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE6 to value 0"]
impl crate :: Resettable for Qne6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE7 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 7\n\nYou can [`read`](crate::Reg::read) this register and get [`qne7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne7`]
module"]
# [doc (alias = "QNE7")]
pub type Qne7 = crate :: Reg < qne7 :: Qne7Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 7"]
pub mod qne7 { # [doc = "Register `QNE7` reader"]
pub type R = crate :: R < Qne7Spec > ; # [doc = "Register `QNE7` writer"]
pub type W = crate :: W < Qne7Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES46` reader - 31:8\\]
RESERVE FIELD"]
pub type Res46R = crate :: FieldReader < u32 > ; # [doc = "Field `RES46` writer - 31:8\\]
RESERVE FIELD"]
pub type Res46W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res46 (& self) -> Res46R { Res46R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne7Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne7Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res46 (& mut self) -> Res46W < Qne7Spec > { Res46W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 7\n\nYou can [`read`](crate::Reg::read) this register and get [`qne7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne7Spec ; impl crate :: RegisterSpec for Qne7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne7::R`](R) reader structure"]
impl crate :: Readable for Qne7Spec { } # [doc = "`write(|w| ..)` method takes [`qne7::W`](W) writer structure"]
impl crate :: Writable for Qne7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE7 to value 0"]
impl crate :: Resettable for Qne7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE8 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 8\n\nYou can [`read`](crate::Reg::read) this register and get [`qne8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne8`]
module"]
# [doc (alias = "QNE8")]
pub type Qne8 = crate :: Reg < qne8 :: Qne8Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 8"]
pub mod qne8 { # [doc = "Register `QNE8` reader"]
pub type R = crate :: R < Qne8Spec > ; # [doc = "Register `QNE8` writer"]
pub type W = crate :: W < Qne8Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES47` reader - 31:8\\]
RESERVE FIELD"]
pub type Res47R = crate :: FieldReader < u32 > ; # [doc = "Field `RES47` writer - 31:8\\]
RESERVE FIELD"]
pub type Res47W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res47 (& self) -> Res47R { Res47R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne8Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne8Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res47 (& mut self) -> Res47W < Qne8Spec > { Res47W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 8\n\nYou can [`read`](crate::Reg::read) this register and get [`qne8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne8Spec ; impl crate :: RegisterSpec for Qne8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne8::R`](R) reader structure"]
impl crate :: Readable for Qne8Spec { } # [doc = "`write(|w| ..)` method takes [`qne8::W`](W) writer structure"]
impl crate :: Writable for Qne8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE8 to value 0"]
impl crate :: Resettable for Qne8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE9 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 9\n\nYou can [`read`](crate::Reg::read) this register and get [`qne9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne9`]
module"]
# [doc (alias = "QNE9")]
pub type Qne9 = crate :: Reg < qne9 :: Qne9Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 9"]
pub mod qne9 { # [doc = "Register `QNE9` reader"]
pub type R = crate :: R < Qne9Spec > ; # [doc = "Register `QNE9` writer"]
pub type W = crate :: W < Qne9Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES48` reader - 31:8\\]
RESERVE FIELD"]
pub type Res48R = crate :: FieldReader < u32 > ; # [doc = "Field `RES48` writer - 31:8\\]
RESERVE FIELD"]
pub type Res48W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res48 (& self) -> Res48R { Res48R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne9Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne9Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res48 (& mut self) -> Res48W < Qne9Spec > { Res48W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 9\n\nYou can [`read`](crate::Reg::read) this register and get [`qne9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne9Spec ; impl crate :: RegisterSpec for Qne9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne9::R`](R) reader structure"]
impl crate :: Readable for Qne9Spec { } # [doc = "`write(|w| ..)` method takes [`qne9::W`](W) writer structure"]
impl crate :: Writable for Qne9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE9 to value 0"]
impl crate :: Resettable for Qne9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE10 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne10`]
module"]
# [doc (alias = "QNE10")]
pub type Qne10 = crate :: Reg < qne10 :: Qne10Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 0"]
pub mod qne10 { # [doc = "Register `QNE10` reader"]
pub type R = crate :: R < Qne10Spec > ; # [doc = "Register `QNE10` writer"]
pub type W = crate :: W < Qne10Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES49` reader - 31:8\\]
RESERVE FIELD"]
pub type Res49R = crate :: FieldReader < u32 > ; # [doc = "Field `RES49` writer - 31:8\\]
RESERVE FIELD"]
pub type Res49W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res49 (& self) -> Res49R { Res49R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne10Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne10Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res49 (& mut self) -> Res49W < Qne10Spec > { Res49W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 0\n\nYou can [`read`](crate::Reg::read) this register and get [`qne10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne10Spec ; impl crate :: RegisterSpec for Qne10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne10::R`](R) reader structure"]
impl crate :: Readable for Qne10Spec { } # [doc = "`write(|w| ..)` method takes [`qne10::W`](W) writer structure"]
impl crate :: Writable for Qne10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE10 to value 0"]
impl crate :: Resettable for Qne10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE11 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 11\n\nYou can [`read`](crate::Reg::read) this register and get [`qne11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne11`]
module"]
# [doc (alias = "QNE11")]
pub type Qne11 = crate :: Reg < qne11 :: Qne11Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 11"]
pub mod qne11 { # [doc = "Register `QNE11` reader"]
pub type R = crate :: R < Qne11Spec > ; # [doc = "Register `QNE11` writer"]
pub type W = crate :: W < Qne11Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES50` reader - 31:8\\]
RESERVE FIELD"]
pub type Res50R = crate :: FieldReader < u32 > ; # [doc = "Field `RES50` writer - 31:8\\]
RESERVE FIELD"]
pub type Res50W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res50 (& self) -> Res50R { Res50R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne11Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne11Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res50 (& mut self) -> Res50W < Qne11Spec > { Res50W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 11\n\nYou can [`read`](crate::Reg::read) this register and get [`qne11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne11Spec ; impl crate :: RegisterSpec for Qne11Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne11::R`](R) reader structure"]
impl crate :: Readable for Qne11Spec { } # [doc = "`write(|w| ..)` method takes [`qne11::W`](W) writer structure"]
impl crate :: Writable for Qne11Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE11 to value 0"]
impl crate :: Resettable for Qne11Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE12 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 12\n\nYou can [`read`](crate::Reg::read) this register and get [`qne12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne12`]
module"]
# [doc (alias = "QNE12")]
pub type Qne12 = crate :: Reg < qne12 :: Qne12Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 12"]
pub mod qne12 { # [doc = "Register `QNE12` reader"]
pub type R = crate :: R < Qne12Spec > ; # [doc = "Register `QNE12` writer"]
pub type W = crate :: W < Qne12Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES51` reader - 31:8\\]
RESERVE FIELD"]
pub type Res51R = crate :: FieldReader < u32 > ; # [doc = "Field `RES51` writer - 31:8\\]
RESERVE FIELD"]
pub type Res51W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res51 (& self) -> Res51R { Res51R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne12Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne12Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res51 (& mut self) -> Res51W < Qne12Spec > { Res51W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 12\n\nYou can [`read`](crate::Reg::read) this register and get [`qne12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne12Spec ; impl crate :: RegisterSpec for Qne12Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne12::R`](R) reader structure"]
impl crate :: Readable for Qne12Spec { } # [doc = "`write(|w| ..)` method takes [`qne12::W`](W) writer structure"]
impl crate :: Writable for Qne12Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE12 to value 0"]
impl crate :: Resettable for Qne12Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE13 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 13\n\nYou can [`read`](crate::Reg::read) this register and get [`qne13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne13`]
module"]
# [doc (alias = "QNE13")]
pub type Qne13 = crate :: Reg < qne13 :: Qne13Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 13"]
pub mod qne13 { # [doc = "Register `QNE13` reader"]
pub type R = crate :: R < Qne13Spec > ; # [doc = "Register `QNE13` writer"]
pub type W = crate :: W < Qne13Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES52` reader - 31:8\\]
RESERVE FIELD"]
pub type Res52R = crate :: FieldReader < u32 > ; # [doc = "Field `RES52` writer - 31:8\\]
RESERVE FIELD"]
pub type Res52W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res52 (& self) -> Res52R { Res52R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne13Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne13Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res52 (& mut self) -> Res52W < Qne13Spec > { Res52W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 13\n\nYou can [`read`](crate::Reg::read) this register and get [`qne13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne13Spec ; impl crate :: RegisterSpec for Qne13Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne13::R`](R) reader structure"]
impl crate :: Readable for Qne13Spec { } # [doc = "`write(|w| ..)` method takes [`qne13::W`](W) writer structure"]
impl crate :: Writable for Qne13Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE13 to value 0"]
impl crate :: Resettable for Qne13Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE14 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 14\n\nYou can [`read`](crate::Reg::read) this register and get [`qne14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne14`]
module"]
# [doc (alias = "QNE14")]
pub type Qne14 = crate :: Reg < qne14 :: Qne14Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 14"]
pub mod qne14 { # [doc = "Register `QNE14` reader"]
pub type R = crate :: R < Qne14Spec > ; # [doc = "Register `QNE14` writer"]
pub type W = crate :: W < Qne14Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES53` reader - 31:8\\]
RESERVE FIELD"]
pub type Res53R = crate :: FieldReader < u32 > ; # [doc = "Field `RES53` writer - 31:8\\]
RESERVE FIELD"]
pub type Res53W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res53 (& self) -> Res53R { Res53R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne14Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne14Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res53 (& mut self) -> Res53W < Qne14Spec > { Res53W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 14\n\nYou can [`read`](crate::Reg::read) this register and get [`qne14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne14Spec ; impl crate :: RegisterSpec for Qne14Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne14::R`](R) reader structure"]
impl crate :: Readable for Qne14Spec { } # [doc = "`write(|w| ..)` method takes [`qne14::W`](W) writer structure"]
impl crate :: Writable for Qne14Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE14 to value 0"]
impl crate :: Resettable for Qne14Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QNE15 (rw) register accessor: Event Queue Entry Diagram for Queue n - Entry 15\n\nYou can [`read`](crate::Reg::read) this register and get [`qne15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qne15`]
module"]
# [doc (alias = "QNE15")]
pub type Qne15 = crate :: Reg < qne15 :: Qne15Spec > ; # [doc = "Event Queue Entry Diagram for Queue n - Entry 15"]
pub mod qne15 { # [doc = "Register `QNE15` reader"]
pub type R = crate :: R < Qne15Spec > ; # [doc = "Register `QNE15` writer"]
pub type W = crate :: W < Qne15Spec > ; # [doc = "Field `ENUM` reader - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumR = crate :: FieldReader ; # [doc = "Field `ENUM` writer - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
pub type EnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ETYPE` reader - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeR = crate :: FieldReader ; # [doc = "Field `ETYPE` writer - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
pub type EtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES54` reader - 31:8\\]
RESERVE FIELD"]
pub type Res54R = crate :: FieldReader < u32 > ; # [doc = "Field `RES54` writer - 31:8\\]
RESERVE FIELD"]
pub type Res54W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
pub fn enum_ (& self) -> EnumR { EnumR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
pub fn etype (& self) -> EtypeR { EtypeR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res54 (& self) -> Res54R { Res54R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7)."]
# [inline (always)]
# [must_use]
pub fn enum_ (& mut self) -> EnumW < Qne15Spec > { EnumW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Event Type: Specifies the specific Event Type for the given entry in the Event Queue."]
# [inline (always)]
# [must_use]
pub fn etype (& mut self) -> EtypeW < Qne15Spec > { EtypeW :: new (self , 6) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res54 (& mut self) -> Res54W < Qne15Spec > { Res54W :: new (self , 8) } } # [doc = "Event Queue Entry Diagram for Queue n - Entry 15\n\nYou can [`read`](crate::Reg::read) this register and get [`qne15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qne15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Qne15Spec ; impl crate :: RegisterSpec for Qne15Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`qne15::R`](R) reader structure"]
impl crate :: Readable for Qne15Spec { } # [doc = "`write(|w| ..)` method takes [`qne15::W`](W) writer structure"]
impl crate :: Writable for Qne15Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QNE15 to value 0"]
impl crate :: Resettable for Qne15Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSTATN (rw) register accessor: QSTATn Register Set\n\nYou can [`read`](crate::Reg::read) this register and get [`qstatn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qstatn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qstatn`]
module"]
# [doc (alias = "QSTATN")]
pub type Qstatn = crate :: Reg < qstatn :: QstatnSpec > ; # [doc = "QSTATn Register Set"]
pub mod qstatn { # [doc = "Register `QSTATN` reader"]
pub type R = crate :: R < QstatnSpec > ; # [doc = "Register `QSTATN` writer"]
pub type W = crate :: W < QstatnSpec > ; # [doc = "Field `STRTPTR` reader - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
pub type StrtptrR = crate :: FieldReader ; # [doc = "Field `STRTPTR` writer - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
pub type StrtptrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RES58` reader - 7:4\\]
RESERVE FIELD"]
pub type Res58R = crate :: FieldReader ; # [doc = "Field `RES58` writer - 7:4\\]
RESERVE FIELD"]
pub type Res58W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NUMVAL` reader - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type NumvalR = crate :: FieldReader ; # [doc = "Field `NUMVAL` writer - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type NumvalW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES57` reader - 15:13\\]
RESERVE FIELD"]
pub type Res57R = crate :: FieldReader ; # [doc = "Field `RES57` writer - 15:13\\]
RESERVE FIELD"]
pub type Res57W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `WM` reader - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type WmR = crate :: FieldReader ; # [doc = "Field `WM` writer - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
pub type WmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES56` reader - 23:21\\]
RESERVE FIELD"]
pub type Res56R = crate :: FieldReader ; # [doc = "Field `RES56` writer - 23:21\\]
RESERVE FIELD"]
pub type Res56W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `THRXCD` reader - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
pub type ThrxcdR = crate :: BitReader ; # [doc = "Field `THRXCD` writer - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
pub type ThrxcdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES55` reader - 31:25\\]
RESERVE FIELD"]
pub type Res55R = crate :: FieldReader ; # [doc = "Field `RES55` writer - 31:25\\]
RESERVE FIELD"]
pub type Res55W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
# [inline (always)]
pub fn strtptr (& self) -> StrtptrR { StrtptrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res58 (& self) -> Res58R { Res58R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
pub fn numval (& self) -> NumvalR { NumvalR :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:15 - 15:13\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res57 (& self) -> Res57R { Res57R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:20 - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
pub fn wm (& self) -> WmR { WmR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:23 - 23:21\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res56 (& self) -> Res56R { Res56R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
# [inline (always)]
pub fn thrxcd (& self) -> ThrxcdR { ThrxcdR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res55 (& self) -> Res55R { Res55R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"]
# [inline (always)]
# [must_use]
pub fn strtptr (& mut self) -> StrtptrW < QstatnSpec > { StrtptrW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res58 (& mut self) -> Res58W < QstatnSpec > { Res58W :: new (self , 4) } # [doc = "Bits 8:12 - 12:8\\]
Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
# [must_use]
pub fn numval (& mut self) -> NumvalW < QstatnSpec > { NumvalW :: new (self , 8) } # [doc = "Bits 13:15 - 15:13\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res57 (& mut self) -> Res57W < QstatnSpec > { Res57W :: new (self , 13) } # [doc = "Bits 16:20 - 20:16\\]
Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full)"]
# [inline (always)]
# [must_use]
pub fn wm (& mut self) -> WmW < QstatnSpec > { WmW :: new (self , 16) } # [doc = "Bits 21:23 - 23:21\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res56 (& mut self) -> Res56W < QstatnSpec > { Res56W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit."]
# [inline (always)]
# [must_use]
pub fn thrxcd (& mut self) -> ThrxcdW < QstatnSpec > { ThrxcdW :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res55 (& mut self) -> Res55W < QstatnSpec > { Res55W :: new (self , 25) } } # [doc = "QSTATn Register Set\n\nYou can [`read`](crate::Reg::read) this register and get [`qstatn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qstatn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QstatnSpec ; impl crate :: RegisterSpec for QstatnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qstatn::R`](R) reader structure"]
impl crate :: Readable for QstatnSpec { } # [doc = "`write(|w| ..)` method takes [`qstatn::W`](W) writer structure"]
impl crate :: Writable for QstatnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSTATN to value 0"]
impl crate :: Resettable for QstatnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QWMTHRA (rw) register accessor: Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors.\n\nYou can [`read`](crate::Reg::read) this register and get [`qwmthra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qwmthra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qwmthra`]
module"]
# [doc (alias = "QWMTHRA")]
pub type Qwmthra = crate :: Reg < qwmthra :: QwmthraSpec > ; # [doc = "Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors."]
pub mod qwmthra { # [doc = "Register `QWMTHRA` reader"]
pub type R = crate :: R < QwmthraSpec > ; # [doc = "Register `QWMTHRA` writer"]
pub type W = crate :: W < QwmthraSpec > ; # [doc = "Field `Q0` reader - 4:0\\]
Queue Threshold for Q0 value"]
pub type Q0R = crate :: FieldReader ; # [doc = "Field `Q0` writer - 4:0\\]
Queue Threshold for Q0 value"]
pub type Q0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES60` reader - 7:5\\]
RESERVE FIELD"]
pub type Res60R = crate :: FieldReader ; # [doc = "Field `RES60` writer - 7:5\\]
RESERVE FIELD"]
pub type Res60W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `Q1` reader - 12:8\\]
Queue Threshold for Q1 value"]
pub type Q1R = crate :: FieldReader ; # [doc = "Field `Q1` writer - 12:8\\]
Queue Threshold for Q1 value"]
pub type Q1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RES59` reader - 31:13\\]
RESERVE FIELD"]
pub type Res59R = crate :: FieldReader < u32 > ; # [doc = "Field `RES59` writer - 31:13\\]
RESERVE FIELD"]
pub type Res59W < 'a , REG > = crate :: FieldWriter < 'a , REG , 19 , u32 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
Queue Threshold for Q0 value"]
# [inline (always)]
pub fn q0 (& self) -> Q0R { Q0R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res60 (& self) -> Res60R { Res60R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:12 - 12:8\\]
Queue Threshold for Q1 value"]
# [inline (always)]
pub fn q1 (& self) -> Q1R { Q1R :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 13:31 - 31:13\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res59 (& self) -> Res59R { Res59R :: new ((self . bits >> 13) & 0x0007_ffff) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
Queue Threshold for Q0 value"]
# [inline (always)]
# [must_use]
pub fn q0 (& mut self) -> Q0W < QwmthraSpec > { Q0W :: new (self , 0) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res60 (& mut self) -> Res60W < QwmthraSpec > { Res60W :: new (self , 5) } # [doc = "Bits 8:12 - 12:8\\]
Queue Threshold for Q1 value"]
# [inline (always)]
# [must_use]
pub fn q1 (& mut self) -> Q1W < QwmthraSpec > { Q1W :: new (self , 8) } # [doc = "Bits 13:31 - 31:13\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res59 (& mut self) -> Res59W < QwmthraSpec > { Res59W :: new (self , 13) } } # [doc = "Queue Threshold A for Q\\[3:0\\]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors.\n\nYou can [`read`](crate::Reg::read) this register and get [`qwmthra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qwmthra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QwmthraSpec ; impl crate :: RegisterSpec for QwmthraSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qwmthra::R`](R) reader structure"]
impl crate :: Readable for QwmthraSpec { } # [doc = "`write(|w| ..)` method takes [`qwmthra::W`](W) writer structure"]
impl crate :: Writable for QwmthraSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QWMTHRA to value 0"]
impl crate :: Resettable for QwmthraSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCSTAT (rw) register accessor: CC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccstat`]
module"]
# [doc (alias = "CCSTAT")]
pub type Ccstat = crate :: Reg < ccstat :: CcstatSpec > ; # [doc = "CC Status Register"]
pub mod ccstat { # [doc = "Register `CCSTAT` reader"]
pub type R = crate :: R < CcstatSpec > ; # [doc = "Register `CCSTAT` writer"]
pub type W = crate :: W < CcstatSpec > ; # [doc = "Field `EVTACTV` reader - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type EvtactvR = crate :: BitReader ; # [doc = "Field `EVTACTV` writer - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type EvtactvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QEVTACTV` reader - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type QevtactvR = crate :: BitReader ; # [doc = "Field `QEVTACTV` writer - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
pub type QevtactvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACTV` reader - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
pub type TractvR = crate :: BitReader ; # [doc = "Field `TRACTV` writer - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
pub type TractvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES64` reader - 3:3\\]
RESERVE FIELD"]
pub type Res64R = crate :: BitReader ; # [doc = "Field `RES64` writer - 3:3\\]
RESERVE FIELD"]
pub type Res64W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ACTV` reader - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
pub type ActvR = crate :: BitReader ; # [doc = "Field `ACTV` writer - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
pub type ActvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES63` reader - 7:5\\]
RESERVE FIELD"]
pub type Res63R = crate :: FieldReader ; # [doc = "Field `RES63` writer - 7:5\\]
RESERVE FIELD"]
pub type Res63W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMPACTV` reader - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
pub type CompactvR = crate :: FieldReader ; # [doc = "Field `COMPACTV` writer - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
pub type CompactvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RES62` reader - 15:14\\]
RESERVE FIELD"]
pub type Res62R = crate :: FieldReader ; # [doc = "Field `RES62` writer - 15:14\\]
RESERVE FIELD"]
pub type Res62W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `QUEACTV0` reader - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
pub type Queactv0R = crate :: BitReader ; # [doc = "Field `QUEACTV0` writer - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
pub type Queactv0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV1` reader - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
pub type Queactv1R = crate :: BitReader ; # [doc = "Field `QUEACTV1` writer - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
pub type Queactv1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV2` reader - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
pub type Queactv2R = crate :: BitReader ; # [doc = "Field `QUEACTV2` writer - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
pub type Queactv2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV3` reader - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
pub type Queactv3R = crate :: BitReader ; # [doc = "Field `QUEACTV3` writer - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
pub type Queactv3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV4` reader - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
pub type Queactv4R = crate :: BitReader ; # [doc = "Field `QUEACTV4` writer - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
pub type Queactv4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV5` reader - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
pub type Queactv5R = crate :: BitReader ; # [doc = "Field `QUEACTV5` writer - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
pub type Queactv5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV6` reader - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
pub type Queactv6R = crate :: BitReader ; # [doc = "Field `QUEACTV6` writer - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
pub type Queactv6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `QUEACTV7` reader - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
pub type Queactv7R = crate :: BitReader ; # [doc = "Field `QUEACTV7` writer - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
pub type Queactv7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES61` reader - 31:24\\]
RESERVE FIELD"]
pub type Res61R = crate :: FieldReader ; # [doc = "Field `RES61` writer - 31:24\\]
RESERVE FIELD"]
pub type Res61W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bit 0 - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
pub fn evtactv (& self) -> EvtactvR { EvtactvR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
pub fn qevtactv (& self) -> QevtactvR { QevtactvR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
# [inline (always)]
pub fn tractv (& self) -> TractvR { TractvR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res64 (& self) -> Res64R { Res64R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
# [inline (always)]
pub fn actv (& self) -> ActvR { ActvR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res63 (& self) -> Res63R { Res63R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:13 - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
# [inline (always)]
pub fn compactv (& self) -> CompactvR { CompactvR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 14:15 - 15:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res62 (& self) -> Res62R { Res62R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
# [inline (always)]
pub fn queactv0 (& self) -> Queactv0R { Queactv0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
# [inline (always)]
pub fn queactv1 (& self) -> Queactv1R { Queactv1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
# [inline (always)]
pub fn queactv2 (& self) -> Queactv2R { Queactv2R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
# [inline (always)]
pub fn queactv3 (& self) -> Queactv3R { Queactv3R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
# [inline (always)]
pub fn queactv4 (& self) -> Queactv4R { Queactv4R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
# [inline (always)]
pub fn queactv5 (& self) -> Queactv5R { Queactv5R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
# [inline (always)]
pub fn queactv6 (& self) -> Queactv6R { Queactv6R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
# [inline (always)]
pub fn queactv7 (& self) -> Queactv7R { Queactv7R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:31 - 31:24\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res61 (& self) -> Res61R { Res61R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
# [must_use]
pub fn evtactv (& mut self) -> EvtactvW < CcstatSpec > { EvtactvW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER &amp; EER ESR CER) is active within the CC."]
# [inline (always)]
# [must_use]
pub fn qevtactv (& mut self) -> QevtactvW < CcstatSpec > { QevtactvW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active."]
# [inline (always)]
# [must_use]
pub fn tractv (& mut self) -> TractvW < CcstatSpec > { TractvW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res64 (& mut self) -> Res64W < CcstatSpec > { Res64W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy."]
# [inline (always)]
# [must_use]
pub fn actv (& mut self) -> ActvW < CcstatSpec > { ActvW :: new (self , 4) } # [doc = "Bits 5:7 - 7:5\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res63 (& mut self) -> Res63W < CcstatSpec > { Res63W :: new (self , 5) } # [doc = "Bits 8:13 - 13:8\\]
Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63."]
# [inline (always)]
# [must_use]
pub fn compactv (& mut self) -> CompactvW < CcstatSpec > { CompactvW :: new (self , 8) } # [doc = "Bits 14:15 - 15:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res62 (& mut self) -> Res62W < CcstatSpec > { Res62W :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0."]
# [inline (always)]
# [must_use]
pub fn queactv0 (& mut self) -> Queactv0W < CcstatSpec > { Queactv0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1."]
# [inline (always)]
# [must_use]
pub fn queactv1 (& mut self) -> Queactv1W < CcstatSpec > { Queactv1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2."]
# [inline (always)]
# [must_use]
pub fn queactv2 (& mut self) -> Queactv2W < CcstatSpec > { Queactv2W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3."]
# [inline (always)]
# [must_use]
pub fn queactv3 (& mut self) -> Queactv3W < CcstatSpec > { Queactv3W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4."]
# [inline (always)]
# [must_use]
pub fn queactv4 (& mut self) -> Queactv4W < CcstatSpec > { Queactv4W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5."]
# [inline (always)]
# [must_use]
pub fn queactv5 (& mut self) -> Queactv5W < CcstatSpec > { Queactv5W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6."]
# [inline (always)]
# [must_use]
pub fn queactv6 (& mut self) -> Queactv6W < CcstatSpec > { Queactv6W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7."]
# [inline (always)]
# [must_use]
pub fn queactv7 (& mut self) -> Queactv7W < CcstatSpec > { Queactv7W :: new (self , 23) } # [doc = "Bits 24:31 - 31:24\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res61 (& mut self) -> Res61W < CcstatSpec > { Res61W :: new (self , 24) } } # [doc = "CC Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcstatSpec ; impl crate :: RegisterSpec for CcstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccstat::R`](R) reader structure"]
impl crate :: Readable for CcstatSpec { } # [doc = "`write(|w| ..)` method takes [`ccstat::W`](W) writer structure"]
impl crate :: Writable for CcstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCSTAT to value 0"]
impl crate :: Resettable for CcstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AETCTL (rw) register accessor: Advanced Event Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`aetctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aetctl`]
module"]
# [doc (alias = "AETCTL")]
pub type Aetctl = crate :: Reg < aetctl :: AetctlSpec > ; # [doc = "Advanced Event Trigger Control"]
pub mod aetctl { # [doc = "Register `AETCTL` reader"]
pub type R = crate :: R < AetctlSpec > ; # [doc = "Register `AETCTL` writer"]
pub type W = crate :: W < AetctlSpec > ; # [doc = "Field `STRTEVT` reader - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
pub type StrtevtR = crate :: FieldReader ; # [doc = "Field `STRTEVT` writer - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
pub type StrtevtW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `TYPE` reader - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
pub type TypeR = crate :: BitReader ; # [doc = "Field `TYPE` writer - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
pub type TypeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES66` reader - 7:7\\]
RESERVE FIELD"]
pub type Res66R = crate :: BitReader ; # [doc = "Field `RES66` writer - 7:7\\]
RESERVE FIELD"]
pub type Res66W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENDINT` reader - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
pub type EndintR = crate :: FieldReader ; # [doc = "Field `ENDINT` writer - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
pub type EndintW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RES65` reader - 30:14\\]
RESERVE FIELD"]
pub type Res65R = crate :: FieldReader < u32 > ; # [doc = "Field `RES65` writer - 30:14\\]
RESERVE FIELD"]
pub type Res65W < 'a , REG > = crate :: FieldWriter < 'a , REG , 17 , u32 > ; # [doc = "Field `EN` reader - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
# [inline (always)]
pub fn strtevt (& self) -> StrtevtR { StrtevtR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
# [inline (always)]
pub fn type_ (& self) -> TypeR { TypeR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res66 (& self) -> Res66R { Res66R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:13 - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
# [inline (always)]
pub fn endint (& self) -> EndintR { EndintR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 14:30 - 30:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res65 (& self) -> Res65R { Res65R :: new ((self . bits >> 14) & 0x0001_ffff) } # [doc = "Bit 31 - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"]
# [inline (always)]
# [must_use]
pub fn strtevt (& mut self) -> StrtevtW < AetctlSpec > { StrtevtW :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events"]
# [inline (always)]
# [must_use]
pub fn type_ (& mut self) -> TypeW < AetctlSpec > { TypeW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res66 (& mut self) -> Res66W < AetctlSpec > { Res66W :: new (self , 7) } # [doc = "Bits 8:13 - 13:8\\]
AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"]
# [inline (always)]
# [must_use]
pub fn endint (& mut self) -> EndintW < AetctlSpec > { EndintW :: new (self , 8) } # [doc = "Bits 14:30 - 30:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res65 (& mut self) -> Res65W < AetctlSpec > { Res65W :: new (self , 14) } # [doc = "Bit 31 - 31:31\\]
AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled."]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < AetctlSpec > { EnW :: new (self , 31) } } # [doc = "Advanced Event Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`aetctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AetctlSpec ; impl crate :: RegisterSpec for AetctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aetctl::R`](R) reader structure"]
impl crate :: Readable for AetctlSpec { } # [doc = "`write(|w| ..)` method takes [`aetctl::W`](W) writer structure"]
impl crate :: Writable for AetctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AETCTL to value 0"]
impl crate :: Resettable for AetctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AETSTAT (rw) register accessor: Advanced Event Trigger Stat\n\nYou can [`read`](crate::Reg::read) this register and get [`aetstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aetstat`]
module"]
# [doc (alias = "AETSTAT")]
pub type Aetstat = crate :: Reg < aetstat :: AetstatSpec > ; # [doc = "Advanced Event Trigger Stat"]
pub mod aetstat { # [doc = "Register `AETSTAT` reader"]
pub type R = crate :: R < AetstatSpec > ; # [doc = "Register `AETSTAT` writer"]
pub type W = crate :: W < AetstatSpec > ; # [doc = "Field `STAT` reader - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
pub type StatR = crate :: BitReader ; # [doc = "Field `STAT` writer - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
pub type StatW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES67` reader - 31:1\\]
RESERVE FIELD"]
pub type Res67R = crate :: FieldReader < u32 > ; # [doc = "Field `RES67` writer - 31:1\\]
RESERVE FIELD"]
pub type Res67W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
# [inline (always)]
pub fn stat (& self) -> StatR { StatR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res67 (& self) -> Res67R { Res67R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high."]
# [inline (always)]
# [must_use]
pub fn stat (& mut self) -> StatW < AetstatSpec > { StatW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res67 (& mut self) -> Res67W < AetstatSpec > { Res67W :: new (self , 1) } } # [doc = "Advanced Event Trigger Stat\n\nYou can [`read`](crate::Reg::read) this register and get [`aetstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AetstatSpec ; impl crate :: RegisterSpec for AetstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aetstat::R`](R) reader structure"]
impl crate :: Readable for AetstatSpec { } # [doc = "`write(|w| ..)` method takes [`aetstat::W`](W) writer structure"]
impl crate :: Writable for AetstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AETSTAT to value 0"]
impl crate :: Resettable for AetstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AETCMD (rw) register accessor: AET Command\n\nYou can [`read`](crate::Reg::read) this register and get [`aetcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aetcmd`]
module"]
# [doc (alias = "AETCMD")]
pub type Aetcmd = crate :: Reg < aetcmd :: AetcmdSpec > ; # [doc = "AET Command"]
pub mod aetcmd { # [doc = "Register `AETCMD` reader"]
pub type R = crate :: R < AetcmdSpec > ; # [doc = "Register `AETCMD` writer"]
pub type W = crate :: W < AetcmdSpec > ; # [doc = "Field `CLR` reader - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
pub type ClrR = crate :: BitReader ; # [doc = "Field `CLR` writer - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
pub type ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES68` reader - 31:1\\]
RESERVE FIELD"]
pub type Res68R = crate :: FieldReader < u32 > ; # [doc = "Field `RES68` writer - 31:1\\]
RESERVE FIELD"]
pub type Res68W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
pub fn clr (& self) -> ClrR { ClrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res68 (& self) -> Res68R { Res68R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.."]
# [inline (always)]
# [must_use]
pub fn clr (& mut self) -> ClrW < AetcmdSpec > { ClrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res68 (& mut self) -> Res68W < AetcmdSpec > { Res68W :: new (self , 1) } } # [doc = "AET Command\n\nYou can [`read`](crate::Reg::read) this register and get [`aetcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aetcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AetcmdSpec ; impl crate :: RegisterSpec for AetcmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aetcmd::R`](R) reader structure"]
impl crate :: Readable for AetcmdSpec { } # [doc = "`write(|w| ..)` method takes [`aetcmd::W`](W) writer structure"]
impl crate :: Writable for AetcmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AETCMD to value 0"]
impl crate :: Resettable for AetcmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ER (rw) register accessor: Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@er`]
module"]
# [doc (alias = "ER")]
pub type Er = crate :: Reg < er :: ErSpec > ; # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
pub mod er { # [doc = "Register `ER` reader"]
pub type R = crate :: R < ErSpec > ; # [doc = "Register `ER` writer"]
pub type W = crate :: W < ErSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < ErSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < ErSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < ErSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < ErSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < ErSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < ErSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < ErSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < ErSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < ErSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < ErSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < ErSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < ErSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < ErSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < ErSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < ErSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < ErSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < ErSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < ErSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < ErSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < ErSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < ErSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < ErSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < ErSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < ErSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < ErSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < ErSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < ErSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < ErSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < ErSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < ErSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < ErSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < ErSpec > { E31W :: new (self , 31) } } # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErSpec ; impl crate :: RegisterSpec for ErSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`er::R`](R) reader structure"]
impl crate :: Readable for ErSpec { } # [doc = "`write(|w| ..)` method takes [`er::W`](W) writer structure"]
impl crate :: Writable for ErSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ER to value 0"]
impl crate :: Resettable for ErSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERH (rw) register accessor: Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erh`]
module"]
# [doc (alias = "ERH")]
pub type Erh = crate :: Reg < erh :: ErhSpec > ; # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
pub mod erh { # [doc = "Register `ERH` reader"]
pub type R = crate :: R < ErhSpec > ; # [doc = "Register `ERH` writer"]
pub type W = crate :: W < ErhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < ErhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < ErhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < ErhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < ErhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < ErhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < ErhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < ErhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < ErhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < ErhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < ErhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < ErhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < ErhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < ErhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < ErhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < ErhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < ErhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < ErhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < ErhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < ErhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < ErhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < ErhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < ErhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < ErhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < ErhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < ErhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < ErhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < ErhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < ErhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < ErhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < ErhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < ErhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < ErhSpec > { E63W :: new (self , 31) } } # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErhSpec ; impl crate :: RegisterSpec for ErhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erh::R`](R) reader structure"]
impl crate :: Readable for ErhSpec { } # [doc = "`write(|w| ..)` method takes [`erh::W`](W) writer structure"]
impl crate :: Writable for ErhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERH to value 0"]
impl crate :: Resettable for ErhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECR (rw) register accessor: Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`]
module"]
# [doc (alias = "ECR")]
pub type Ecr = crate :: Reg < ecr :: EcrSpec > ; # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecr { # [doc = "Register `ECR` reader"]
pub type R = crate :: R < EcrSpec > ; # [doc = "Register `ECR` writer"]
pub type W = crate :: W < EcrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EcrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EcrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EcrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EcrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EcrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EcrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EcrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EcrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EcrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EcrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EcrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EcrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EcrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EcrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EcrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EcrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EcrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EcrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EcrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EcrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EcrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EcrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EcrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EcrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EcrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EcrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EcrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EcrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EcrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EcrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EcrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EcrSpec > { E31W :: new (self , 31) } } # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrSpec ; impl crate :: RegisterSpec for EcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecr::R`](R) reader structure"]
impl crate :: Readable for EcrSpec { } # [doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"]
impl crate :: Writable for EcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECR to value 0"]
impl crate :: Resettable for EcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECRH (rw) register accessor: Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecrh`]
module"]
# [doc (alias = "ECRH")]
pub type Ecrh = crate :: Reg < ecrh :: EcrhSpec > ; # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecrh { # [doc = "Register `ECRH` reader"]
pub type R = crate :: R < EcrhSpec > ; # [doc = "Register `ECRH` writer"]
pub type W = crate :: W < EcrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EcrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EcrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EcrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EcrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EcrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EcrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EcrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EcrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EcrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EcrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EcrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EcrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EcrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EcrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EcrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EcrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EcrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EcrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EcrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EcrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EcrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EcrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EcrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EcrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EcrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EcrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EcrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EcrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EcrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EcrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EcrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EcrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrhSpec ; impl crate :: RegisterSpec for EcrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecrh::R`](R) reader structure"]
impl crate :: Readable for EcrhSpec { } # [doc = "`write(|w| ..)` method takes [`ecrh::W`](W) writer structure"]
impl crate :: Writable for EcrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECRH to value 0"]
impl crate :: Resettable for EcrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESR (rw) register accessor: Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr`]
module"]
# [doc (alias = "ESR")]
pub type Esr = crate :: Reg < esr :: EsrSpec > ; # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
pub mod esr { # [doc = "Register `ESR` reader"]
pub type R = crate :: R < EsrSpec > ; # [doc = "Register `ESR` writer"]
pub type W = crate :: W < EsrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EsrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EsrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EsrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EsrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EsrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EsrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EsrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EsrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EsrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EsrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EsrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EsrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EsrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EsrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EsrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EsrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EsrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EsrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EsrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EsrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EsrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EsrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EsrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EsrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EsrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EsrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EsrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EsrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EsrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EsrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EsrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EsrSpec > { E31W :: new (self , 31) } } # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrSpec ; impl crate :: RegisterSpec for EsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esr::R`](R) reader structure"]
impl crate :: Readable for EsrSpec { } # [doc = "`write(|w| ..)` method takes [`esr::W`](W) writer structure"]
impl crate :: Writable for EsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESR to value 0"]
impl crate :: Resettable for EsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESRH (rw) register accessor: Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esrh`]
module"]
# [doc (alias = "ESRH")]
pub type Esrh = crate :: Reg < esrh :: EsrhSpec > ; # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
pub mod esrh { # [doc = "Register `ESRH` reader"]
pub type R = crate :: R < EsrhSpec > ; # [doc = "Register `ESRH` writer"]
pub type W = crate :: W < EsrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EsrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EsrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EsrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EsrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EsrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EsrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EsrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EsrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EsrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EsrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EsrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EsrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EsrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EsrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EsrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EsrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EsrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EsrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EsrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EsrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EsrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EsrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EsrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EsrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EsrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EsrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EsrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EsrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EsrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EsrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EsrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EsrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrhSpec ; impl crate :: RegisterSpec for EsrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esrh::R`](R) reader structure"]
impl crate :: Readable for EsrhSpec { } # [doc = "`write(|w| ..)` method takes [`esrh::W`](W) writer structure"]
impl crate :: Writable for EsrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESRH to value 0"]
impl crate :: Resettable for EsrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CER (rw) register accessor: Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cer`]
module"]
# [doc (alias = "CER")]
pub type Cer = crate :: Reg < cer :: CerSpec > ; # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
pub mod cer { # [doc = "Register `CER` reader"]
pub type R = crate :: R < CerSpec > ; # [doc = "Register `CER` writer"]
pub type W = crate :: W < CerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < CerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < CerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < CerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < CerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < CerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < CerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < CerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < CerSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < CerSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < CerSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < CerSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < CerSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < CerSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < CerSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < CerSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < CerSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < CerSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < CerSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < CerSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < CerSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < CerSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < CerSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < CerSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < CerSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < CerSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < CerSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < CerSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < CerSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < CerSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < CerSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < CerSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < CerSpec > { E31W :: new (self , 31) } } # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerSpec ; impl crate :: RegisterSpec for CerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cer::R`](R) reader structure"]
impl crate :: Readable for CerSpec { } # [doc = "`write(|w| ..)` method takes [`cer::W`](W) writer structure"]
impl crate :: Writable for CerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CER to value 0"]
impl crate :: Resettable for CerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CERH (rw) register accessor: Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cerh`]
module"]
# [doc (alias = "CERH")]
pub type Cerh = crate :: Reg < cerh :: CerhSpec > ; # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
pub mod cerh { # [doc = "Register `CERH` reader"]
pub type R = crate :: R < CerhSpec > ; # [doc = "Register `CERH` writer"]
pub type W = crate :: W < CerhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < CerhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < CerhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < CerhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < CerhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < CerhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < CerhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < CerhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < CerhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < CerhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < CerhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < CerhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < CerhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < CerhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < CerhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < CerhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < CerhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < CerhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < CerhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < CerhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < CerhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < CerhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < CerhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < CerhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < CerhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < CerhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < CerhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < CerhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < CerhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < CerhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < CerhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < CerhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < CerhSpec > { E63W :: new (self , 31) } } # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerhSpec ; impl crate :: RegisterSpec for CerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cerh::R`](R) reader structure"]
impl crate :: Readable for CerhSpec { } # [doc = "`write(|w| ..)` method takes [`cerh::W`](W) writer structure"]
impl crate :: Writable for CerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CERH to value 0"]
impl crate :: Resettable for CerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EER (rw) register accessor: Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eer`]
module"]
# [doc (alias = "EER")]
pub type Eer = crate :: Reg < eer :: EerSpec > ; # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eer { # [doc = "Register `EER` reader"]
pub type R = crate :: R < EerSpec > ; # [doc = "Register `EER` writer"]
pub type W = crate :: W < EerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EerSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EerSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EerSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EerSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EerSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EerSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EerSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EerSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EerSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EerSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EerSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EerSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EerSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EerSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EerSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EerSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EerSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EerSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EerSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EerSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EerSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EerSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EerSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EerSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EerSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerSpec ; impl crate :: RegisterSpec for EerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eer::R`](R) reader structure"]
impl crate :: Readable for EerSpec { } # [doc = "`write(|w| ..)` method takes [`eer::W`](W) writer structure"]
impl crate :: Writable for EerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EER to value 0"]
impl crate :: Resettable for EerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EERH (rw) register accessor: Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eerh`]
module"]
# [doc (alias = "EERH")]
pub type Eerh = crate :: Reg < eerh :: EerhSpec > ; # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eerh { # [doc = "Register `EERH` reader"]
pub type R = crate :: R < EerhSpec > ; # [doc = "Register `EERH` writer"]
pub type W = crate :: W < EerhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EerhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EerhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EerhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EerhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EerhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EerhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EerhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EerhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EerhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EerhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EerhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EerhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EerhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EerhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EerhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EerhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EerhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EerhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EerhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EerhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EerhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EerhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EerhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EerhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EerhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EerhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EerhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EerhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EerhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EerhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EerhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EerhSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerhSpec ; impl crate :: RegisterSpec for EerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eerh::R`](R) reader structure"]
impl crate :: Readable for EerhSpec { } # [doc = "`write(|w| ..)` method takes [`eerh::W`](W) writer structure"]
impl crate :: Writable for EerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EERH to value 0"]
impl crate :: Resettable for EerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECR (rw) register accessor: Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecr`]
module"]
# [doc (alias = "EECR")]
pub type Eecr = crate :: Reg < eecr :: EecrSpec > ; # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecr { # [doc = "Register `EECR` reader"]
pub type R = crate :: R < EecrSpec > ; # [doc = "Register `EECR` writer"]
pub type W = crate :: W < EecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EecrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EecrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EecrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EecrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EecrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EecrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EecrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EecrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EecrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EecrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EecrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EecrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EecrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EecrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EecrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EecrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EecrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EecrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EecrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EecrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EecrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EecrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EecrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EecrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EecrSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrSpec ; impl crate :: RegisterSpec for EecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecr::R`](R) reader structure"]
impl crate :: Readable for EecrSpec { } # [doc = "`write(|w| ..)` method takes [`eecr::W`](W) writer structure"]
impl crate :: Writable for EecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECR to value 0"]
impl crate :: Resettable for EecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECRH (rw) register accessor: Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecrh`]
module"]
# [doc (alias = "EECRH")]
pub type Eecrh = crate :: Reg < eecrh :: EecrhSpec > ; # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecrh { # [doc = "Register `EECRH` reader"]
pub type R = crate :: R < EecrhSpec > ; # [doc = "Register `EECRH` writer"]
pub type W = crate :: W < EecrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EecrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EecrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EecrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EecrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EecrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EecrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EecrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EecrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EecrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EecrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EecrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EecrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EecrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EecrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EecrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EecrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EecrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EecrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EecrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EecrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EecrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EecrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EecrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EecrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EecrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EecrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EecrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EecrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EecrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EecrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EecrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EecrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrhSpec ; impl crate :: RegisterSpec for EecrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecrh::R`](R) reader structure"]
impl crate :: Readable for EecrhSpec { } # [doc = "`write(|w| ..)` method takes [`eecrh::W`](W) writer structure"]
impl crate :: Writable for EecrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECRH to value 0"]
impl crate :: Resettable for EecrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESR (rw) register accessor: Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesr`]
module"]
# [doc (alias = "EESR")]
pub type Eesr = crate :: Reg < eesr :: EesrSpec > ; # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesr { # [doc = "Register `EESR` reader"]
pub type R = crate :: R < EesrSpec > ; # [doc = "Register `EESR` writer"]
pub type W = crate :: W < EesrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EesrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EesrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EesrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EesrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EesrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EesrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EesrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EesrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EesrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EesrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EesrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EesrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EesrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EesrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EesrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EesrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EesrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EesrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EesrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EesrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EesrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EesrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EesrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EesrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EesrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EesrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EesrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EesrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EesrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EesrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EesrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EesrSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrSpec ; impl crate :: RegisterSpec for EesrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesr::R`](R) reader structure"]
impl crate :: Readable for EesrSpec { } # [doc = "`write(|w| ..)` method takes [`eesr::W`](W) writer structure"]
impl crate :: Writable for EesrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESR to value 0"]
impl crate :: Resettable for EesrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESRH (rw) register accessor: Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesrh`]
module"]
# [doc (alias = "EESRH")]
pub type Eesrh = crate :: Reg < eesrh :: EesrhSpec > ; # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesrh { # [doc = "Register `EESRH` reader"]
pub type R = crate :: R < EesrhSpec > ; # [doc = "Register `EESRH` writer"]
pub type W = crate :: W < EesrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EesrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EesrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EesrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EesrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EesrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EesrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EesrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EesrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EesrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EesrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EesrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EesrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EesrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EesrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EesrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EesrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EesrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EesrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EesrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EesrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EesrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EesrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EesrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EesrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EesrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EesrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EesrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EesrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EesrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EesrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EesrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EesrhSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrhSpec ; impl crate :: RegisterSpec for EesrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesrh::R`](R) reader structure"]
impl crate :: Readable for EesrhSpec { } # [doc = "`write(|w| ..)` method takes [`eesrh::W`](W) writer structure"]
impl crate :: Writable for EesrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESRH to value 0"]
impl crate :: Resettable for EesrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SER (rw) register accessor: Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ser`]
module"]
# [doc (alias = "SER")]
pub type Ser = crate :: Reg < ser :: SerSpec > ; # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod ser { # [doc = "Register `SER` reader"]
pub type R = crate :: R < SerSpec > ; # [doc = "Register `SER` writer"]
pub type W = crate :: W < SerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SerSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SerSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SerSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SerSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SerSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SerSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SerSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SerSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SerSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SerSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SerSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SerSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SerSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SerSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SerSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SerSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SerSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SerSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SerSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SerSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SerSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SerSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SerSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SerSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SerSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerSpec ; impl crate :: RegisterSpec for SerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ser::R`](R) reader structure"]
impl crate :: Readable for SerSpec { } # [doc = "`write(|w| ..)` method takes [`ser::W`](W) writer structure"]
impl crate :: Writable for SerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SER to value 0"]
impl crate :: Resettable for SerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SERH (rw) register accessor: Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@serh`]
module"]
# [doc (alias = "SERH")]
pub type Serh = crate :: Reg < serh :: SerhSpec > ; # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod serh { # [doc = "Register `SERH` reader"]
pub type R = crate :: R < SerhSpec > ; # [doc = "Register `SERH` writer"]
pub type W = crate :: W < SerhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SerhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SerhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SerhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SerhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SerhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SerhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SerhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SerhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SerhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SerhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SerhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SerhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SerhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SerhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SerhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SerhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SerhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SerhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SerhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SerhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SerhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SerhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SerhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SerhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SerhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SerhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SerhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SerhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SerhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SerhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SerhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SerhSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerhSpec ; impl crate :: RegisterSpec for SerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`serh::R`](R) reader structure"]
impl crate :: Readable for SerhSpec { } # [doc = "`write(|w| ..)` method takes [`serh::W`](W) writer structure"]
impl crate :: Writable for SerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SERH to value 0"]
impl crate :: Resettable for SerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECR (rw) register accessor: Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secr`]
module"]
# [doc (alias = "SECR")]
pub type Secr = crate :: Reg < secr :: SecrSpec > ; # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
pub mod secr { # [doc = "Register `SECR` reader"]
pub type R = crate :: R < SecrSpec > ; # [doc = "Register `SECR` writer"]
pub type W = crate :: W < SecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SecrSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SecrSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SecrSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SecrSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SecrSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SecrSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SecrSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SecrSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SecrSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SecrSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SecrSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SecrSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SecrSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SecrSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SecrSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SecrSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SecrSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SecrSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SecrSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SecrSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SecrSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SecrSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SecrSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SecrSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SecrSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrSpec ; impl crate :: RegisterSpec for SecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secr::R`](R) reader structure"]
impl crate :: Readable for SecrSpec { } # [doc = "`write(|w| ..)` method takes [`secr::W`](W) writer structure"]
impl crate :: Writable for SecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECR to value 0"]
impl crate :: Resettable for SecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECRH (rw) register accessor: Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secrh`]
module"]
# [doc (alias = "SECRH")]
pub type Secrh = crate :: Reg < secrh :: SecrhSpec > ; # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
pub mod secrh { # [doc = "Register `SECRH` reader"]
pub type R = crate :: R < SecrhSpec > ; # [doc = "Register `SECRH` writer"]
pub type W = crate :: W < SecrhSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SecrhSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SecrhSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SecrhSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SecrhSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SecrhSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SecrhSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SecrhSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SecrhSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SecrhSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SecrhSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SecrhSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SecrhSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SecrhSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SecrhSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SecrhSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SecrhSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SecrhSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SecrhSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SecrhSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SecrhSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SecrhSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SecrhSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SecrhSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SecrhSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SecrhSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SecrhSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SecrhSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SecrhSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SecrhSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SecrhSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SecrhSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SecrhSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrhSpec ; impl crate :: RegisterSpec for SecrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secrh::R`](R) reader structure"]
impl crate :: Readable for SecrhSpec { } # [doc = "`write(|w| ..)` method takes [`secrh::W`](W) writer structure"]
impl crate :: Writable for SecrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECRH to value 0"]
impl crate :: Resettable for SecrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IER (rw) register accessor: Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
# [doc (alias = "IER")]
pub type Ier = crate :: Reg < ier :: IerSpec > ; # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
pub mod ier { # [doc = "Register `IER` reader"]
pub type R = crate :: R < IerSpec > ; # [doc = "Register `IER` writer"]
pub type W = crate :: W < IerSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IerSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IerSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IerSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IerSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IerSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IerSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IerSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IerSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IerSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IerSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IerSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IerSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IerSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IerSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IerSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IerSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IerSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IerSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IerSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IerSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IerSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IerSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IerSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IerSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IerSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IerSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IerSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IerSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IerSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IerSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IerSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IerSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec ; impl crate :: RegisterSpec for IerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate :: Readable for IerSpec { } # [doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate :: Writable for IerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IER to value 0"]
impl crate :: Resettable for IerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IERH (rw) register accessor: Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ierh`]
module"]
# [doc (alias = "IERH")]
pub type Ierh = crate :: Reg < ierh :: IerhSpec > ; # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
pub mod ierh { # [doc = "Register `IERH` reader"]
pub type R = crate :: R < IerhSpec > ; # [doc = "Register `IERH` writer"]
pub type W = crate :: W < IerhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IerhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IerhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IerhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IerhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IerhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IerhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IerhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IerhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IerhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IerhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IerhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IerhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IerhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IerhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IerhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IerhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IerhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IerhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IerhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IerhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IerhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IerhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IerhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IerhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IerhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IerhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IerhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IerhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IerhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IerhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IerhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IerhSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerhSpec ; impl crate :: RegisterSpec for IerhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ierh::R`](R) reader structure"]
impl crate :: Readable for IerhSpec { } # [doc = "`write(|w| ..)` method takes [`ierh::W`](W) writer structure"]
impl crate :: Writable for IerhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IERH to value 0"]
impl crate :: Resettable for IerhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECR (rw) register accessor: Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecr`]
module"]
# [doc (alias = "IECR")]
pub type Iecr = crate :: Reg < iecr :: IecrSpec > ; # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecr { # [doc = "Register `IECR` reader"]
pub type R = crate :: R < IecrSpec > ; # [doc = "Register `IECR` writer"]
pub type W = crate :: W < IecrSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IecrSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IecrSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IecrSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IecrSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IecrSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IecrSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IecrSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IecrSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IecrSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IecrSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IecrSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IecrSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IecrSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IecrSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IecrSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IecrSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IecrSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IecrSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IecrSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IecrSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IecrSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IecrSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IecrSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IecrSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IecrSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IecrSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IecrSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IecrSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IecrSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IecrSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IecrSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IecrSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrSpec ; impl crate :: RegisterSpec for IecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecr::R`](R) reader structure"]
impl crate :: Readable for IecrSpec { } # [doc = "`write(|w| ..)` method takes [`iecr::W`](W) writer structure"]
impl crate :: Writable for IecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECR to value 0"]
impl crate :: Resettable for IecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECRH (rw) register accessor: Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecrh`]
module"]
# [doc (alias = "IECRH")]
pub type Iecrh = crate :: Reg < iecrh :: IecrhSpec > ; # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecrh { # [doc = "Register `IECRH` reader"]
pub type R = crate :: R < IecrhSpec > ; # [doc = "Register `IECRH` writer"]
pub type W = crate :: W < IecrhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IecrhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IecrhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IecrhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IecrhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IecrhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IecrhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IecrhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IecrhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IecrhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IecrhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IecrhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IecrhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IecrhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IecrhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IecrhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IecrhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IecrhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IecrhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IecrhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IecrhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IecrhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IecrhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IecrhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IecrhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IecrhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IecrhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IecrhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IecrhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IecrhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IecrhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IecrhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IecrhSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrhSpec ; impl crate :: RegisterSpec for IecrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecrh::R`](R) reader structure"]
impl crate :: Readable for IecrhSpec { } # [doc = "`write(|w| ..)` method takes [`iecrh::W`](W) writer structure"]
impl crate :: Writable for IecrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECRH to value 0"]
impl crate :: Resettable for IecrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESR (rw) register accessor: Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesr`]
module"]
# [doc (alias = "IESR")]
pub type Iesr = crate :: Reg < iesr :: IesrSpec > ; # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesr { # [doc = "Register `IESR` reader"]
pub type R = crate :: R < IesrSpec > ; # [doc = "Register `IESR` writer"]
pub type W = crate :: W < IesrSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IesrSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IesrSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IesrSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IesrSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IesrSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IesrSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IesrSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IesrSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IesrSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IesrSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IesrSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IesrSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IesrSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IesrSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IesrSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IesrSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IesrSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IesrSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IesrSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IesrSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IesrSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IesrSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IesrSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IesrSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IesrSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IesrSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IesrSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IesrSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IesrSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IesrSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IesrSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IesrSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrSpec ; impl crate :: RegisterSpec for IesrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesr::R`](R) reader structure"]
impl crate :: Readable for IesrSpec { } # [doc = "`write(|w| ..)` method takes [`iesr::W`](W) writer structure"]
impl crate :: Writable for IesrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESR to value 0"]
impl crate :: Resettable for IesrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESRH (rw) register accessor: Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesrh`]
module"]
# [doc (alias = "IESRH")]
pub type Iesrh = crate :: Reg < iesrh :: IesrhSpec > ; # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesrh { # [doc = "Register `IESRH` reader"]
pub type R = crate :: R < IesrhSpec > ; # [doc = "Register `IESRH` writer"]
pub type W = crate :: W < IesrhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IesrhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IesrhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IesrhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IesrhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IesrhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IesrhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IesrhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IesrhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IesrhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IesrhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IesrhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IesrhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IesrhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IesrhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IesrhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IesrhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IesrhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IesrhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IesrhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IesrhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IesrhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IesrhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IesrhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IesrhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IesrhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IesrhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IesrhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IesrhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IesrhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IesrhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IesrhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IesrhSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrhSpec ; impl crate :: RegisterSpec for IesrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesrh::R`](R) reader structure"]
impl crate :: Readable for IesrhSpec { } # [doc = "`write(|w| ..)` method takes [`iesrh::W`](W) writer structure"]
impl crate :: Writable for IesrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESRH to value 0"]
impl crate :: Resettable for IesrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPR (rw) register accessor: Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipr`]
module"]
# [doc (alias = "IPR")]
pub type Ipr = crate :: Reg < ipr :: IprSpec > ; # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
pub mod ipr { # [doc = "Register `IPR` reader"]
pub type R = crate :: R < IprSpec > ; # [doc = "Register `IPR` writer"]
pub type W = crate :: W < IprSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IprSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IprSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IprSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IprSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IprSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IprSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IprSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IprSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IprSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IprSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IprSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IprSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IprSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IprSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IprSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IprSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IprSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IprSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IprSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IprSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IprSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IprSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IprSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IprSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IprSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IprSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IprSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IprSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IprSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IprSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IprSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IprSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprSpec ; impl crate :: RegisterSpec for IprSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipr::R`](R) reader structure"]
impl crate :: Readable for IprSpec { } # [doc = "`write(|w| ..)` method takes [`ipr::W`](W) writer structure"]
impl crate :: Writable for IprSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPR to value 0"]
impl crate :: Resettable for IprSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPRH (rw) register accessor: Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iprh`]
module"]
# [doc (alias = "IPRH")]
pub type Iprh = crate :: Reg < iprh :: IprhSpec > ; # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
pub mod iprh { # [doc = "Register `IPRH` reader"]
pub type R = crate :: R < IprhSpec > ; # [doc = "Register `IPRH` writer"]
pub type W = crate :: W < IprhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IprhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IprhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IprhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IprhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IprhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IprhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IprhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IprhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IprhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IprhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IprhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IprhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IprhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IprhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IprhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IprhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IprhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IprhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IprhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IprhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IprhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IprhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IprhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IprhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IprhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IprhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IprhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IprhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IprhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IprhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IprhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IprhSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprhSpec ; impl crate :: RegisterSpec for IprhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iprh::R`](R) reader structure"]
impl crate :: Readable for IprhSpec { } # [doc = "`write(|w| ..)` method takes [`iprh::W`](W) writer structure"]
impl crate :: Writable for IprhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPRH to value 0"]
impl crate :: Resettable for IprhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICR (rw) register accessor: Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
# [doc (alias = "ICR")]
pub type Icr = crate :: Reg < icr :: IcrSpec > ; # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icr { # [doc = "Register `ICR` reader"]
pub type R = crate :: R < IcrSpec > ; # [doc = "Register `ICR` writer"]
pub type W = crate :: W < IcrSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IcrSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IcrSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IcrSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IcrSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IcrSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IcrSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IcrSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IcrSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IcrSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IcrSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IcrSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IcrSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IcrSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IcrSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IcrSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IcrSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IcrSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IcrSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IcrSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IcrSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IcrSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IcrSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IcrSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IcrSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IcrSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IcrSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IcrSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IcrSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IcrSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IcrSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IcrSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IcrSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec ; impl crate :: RegisterSpec for IcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate :: Readable for IcrSpec { } # [doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate :: Writable for IcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICR to value 0"]
impl crate :: Resettable for IcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICRH (rw) register accessor: Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icrh`]
module"]
# [doc (alias = "ICRH")]
pub type Icrh = crate :: Reg < icrh :: IcrhSpec > ; # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icrh { # [doc = "Register `ICRH` reader"]
pub type R = crate :: R < IcrhSpec > ; # [doc = "Register `ICRH` writer"]
pub type W = crate :: W < IcrhSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IcrhSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IcrhSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IcrhSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IcrhSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IcrhSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IcrhSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IcrhSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IcrhSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IcrhSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IcrhSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IcrhSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IcrhSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IcrhSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IcrhSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IcrhSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IcrhSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IcrhSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IcrhSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IcrhSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IcrhSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IcrhSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IcrhSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IcrhSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IcrhSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IcrhSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IcrhSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IcrhSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IcrhSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IcrhSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IcrhSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IcrhSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IcrhSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrhSpec ; impl crate :: RegisterSpec for IcrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icrh::R`](R) reader structure"]
impl crate :: Readable for IcrhSpec { } # [doc = "`write(|w| ..)` method takes [`icrh::W`](W) writer structure"]
impl crate :: Writable for IcrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICRH to value 0"]
impl crate :: Resettable for IcrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IEVAL (rw) register accessor: Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ieval`]
module"]
# [doc (alias = "IEVAL")]
pub type Ieval = crate :: Reg < ieval :: IevalSpec > ; # [doc = "Interrupt Eval Register"]
pub mod ieval { # [doc = "Register `IEVAL` reader"]
pub type R = crate :: R < IevalSpec > ; # [doc = "Register `IEVAL` writer"]
pub type W = crate :: W < IevalSpec > ; # [doc = "Field `EVAL` reader - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalR = crate :: BitReader ; # [doc = "Field `EVAL` writer - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET` reader - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetR = crate :: BitReader ; # [doc = "Field `SET` writer - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES69` reader - 31:2\\]
RESERVE FIELD"]
pub type Res69R = crate :: FieldReader < u32 > ; # [doc = "Field `RES69` writer - 31:2\\]
RESERVE FIELD"]
pub type Res69W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
pub fn eval (& self) -> EvalR { EvalR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res69 (& self) -> Res69R { Res69R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
# [must_use]
pub fn eval (& mut self) -> EvalW < IevalSpec > { EvalW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < IevalSpec > { SetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res69 (& mut self) -> Res69W < IevalSpec > { Res69W :: new (self , 2) } } # [doc = "Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IevalSpec ; impl crate :: RegisterSpec for IevalSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ieval::R`](R) reader structure"]
impl crate :: Readable for IevalSpec { } # [doc = "`write(|w| ..)` method takes [`ieval::W`](W) writer structure"]
impl crate :: Writable for IevalSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IEVAL to value 0"]
impl crate :: Resettable for IevalSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QER (rw) register accessor: QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qer`]
module"]
# [doc (alias = "QER")]
pub type Qer = crate :: Reg < qer :: QerSpec > ; # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
pub mod qer { # [doc = "Register `QER` reader"]
pub type R = crate :: R < QerSpec > ; # [doc = "Register `QER` writer"]
pub type W = crate :: W < QerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES70` reader - 31:8\\]
RESERVE FIELD"]
pub type Res70R = crate :: FieldReader < u32 > ; # [doc = "Field `RES70` writer - 31:8\\]
RESERVE FIELD"]
pub type Res70W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res70 (& self) -> Res70R { Res70R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QerSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res70 (& mut self) -> Res70W < QerSpec > { Res70W :: new (self , 8) } } # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QerSpec ; impl crate :: RegisterSpec for QerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qer::R`](R) reader structure"]
impl crate :: Readable for QerSpec { } # [doc = "`write(|w| ..)` method takes [`qer::W`](W) writer structure"]
impl crate :: Writable for QerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QER to value 0"]
impl crate :: Resettable for QerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEER (rw) register accessor: QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeer`]
module"]
# [doc (alias = "QEER")]
pub type Qeer = crate :: Reg < qeer :: QeerSpec > ; # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
pub mod qeer { # [doc = "Register `QEER` reader"]
pub type R = crate :: R < QeerSpec > ; # [doc = "Register `QEER` writer"]
pub type W = crate :: W < QeerSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES71` reader - 31:8\\]
RESERVE FIELD"]
pub type Res71R = crate :: FieldReader < u32 > ; # [doc = "Field `RES71` writer - 31:8\\]
RESERVE FIELD"]
pub type Res71W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res71 (& self) -> Res71R { Res71R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeerSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeerSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeerSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeerSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeerSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeerSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeerSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeerSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res71 (& mut self) -> Res71W < QeerSpec > { Res71W :: new (self , 8) } } # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeerSpec ; impl crate :: RegisterSpec for QeerSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeer::R`](R) reader structure"]
impl crate :: Readable for QeerSpec { } # [doc = "`write(|w| ..)` method takes [`qeer::W`](W) writer structure"]
impl crate :: Writable for QeerSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEER to value 0"]
impl crate :: Resettable for QeerSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEECR (rw) register accessor: QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeecr`]
module"]
# [doc (alias = "QEECR")]
pub type Qeecr = crate :: Reg < qeecr :: QeecrSpec > ; # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod qeecr { # [doc = "Register `QEECR` reader"]
pub type R = crate :: R < QeecrSpec > ; # [doc = "Register `QEECR` writer"]
pub type W = crate :: W < QeecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES72` reader - 31:8\\]
RESERVE FIELD"]
pub type Res72R = crate :: FieldReader < u32 > ; # [doc = "Field `RES72` writer - 31:8\\]
RESERVE FIELD"]
pub type Res72W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res72 (& self) -> Res72R { Res72R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeecrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res72 (& mut self) -> Res72W < QeecrSpec > { Res72W :: new (self , 8) } } # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeecrSpec ; impl crate :: RegisterSpec for QeecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeecr::R`](R) reader structure"]
impl crate :: Readable for QeecrSpec { } # [doc = "`write(|w| ..)` method takes [`qeecr::W`](W) writer structure"]
impl crate :: Writable for QeecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEECR to value 0"]
impl crate :: Resettable for QeecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEESR (rw) register accessor: QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeesr`]
module"]
# [doc (alias = "QEESR")]
pub type Qeesr = crate :: Reg < qeesr :: QeesrSpec > ; # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
pub mod qeesr { # [doc = "Register `QEESR` reader"]
pub type R = crate :: R < QeesrSpec > ; # [doc = "Register `QEESR` writer"]
pub type W = crate :: W < QeesrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES73` reader - 31:8\\]
RESERVE FIELD"]
pub type Res73R = crate :: FieldReader < u32 > ; # [doc = "Field `RES73` writer - 31:8\\]
RESERVE FIELD"]
pub type Res73W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res73 (& self) -> Res73R { Res73R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeesrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeesrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeesrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeesrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeesrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeesrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeesrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeesrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res73 (& mut self) -> Res73W < QeesrSpec > { Res73W :: new (self , 8) } } # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeesrSpec ; impl crate :: RegisterSpec for QeesrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeesr::R`](R) reader structure"]
impl crate :: Readable for QeesrSpec { } # [doc = "`write(|w| ..)` method takes [`qeesr::W`](W) writer structure"]
impl crate :: Writable for QeesrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEESR to value 0"]
impl crate :: Resettable for QeesrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSER (rw) register accessor: QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qser`]
module"]
# [doc (alias = "QSER")]
pub type Qser = crate :: Reg < qser :: QserSpec > ; # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod qser { # [doc = "Register `QSER` reader"]
pub type R = crate :: R < QserSpec > ; # [doc = "Register `QSER` writer"]
pub type W = crate :: W < QserSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES74` reader - 31:8\\]
RESERVE FIELD"]
pub type Res74R = crate :: FieldReader < u32 > ; # [doc = "Field `RES74` writer - 31:8\\]
RESERVE FIELD"]
pub type Res74W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res74 (& self) -> Res74R { Res74R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QserSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QserSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QserSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QserSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QserSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QserSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QserSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QserSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res74 (& mut self) -> Res74W < QserSpec > { Res74W :: new (self , 8) } } # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QserSpec ; impl crate :: RegisterSpec for QserSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qser::R`](R) reader structure"]
impl crate :: Readable for QserSpec { } # [doc = "`write(|w| ..)` method takes [`qser::W`](W) writer structure"]
impl crate :: Writable for QserSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSER to value 0"]
impl crate :: Resettable for QserSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSECR (rw) register accessor: QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsecr`]
module"]
# [doc (alias = "QSECR")]
pub type Qsecr = crate :: Reg < qsecr :: QsecrSpec > ; # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
pub mod qsecr { # [doc = "Register `QSECR` reader"]
pub type R = crate :: R < QsecrSpec > ; # [doc = "Register `QSECR` writer"]
pub type W = crate :: W < QsecrSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES75` reader - 31:8\\]
RESERVE FIELD"]
pub type Res75R = crate :: FieldReader < u32 > ; # [doc = "Field `RES75` writer - 31:8\\]
RESERVE FIELD"]
pub type Res75W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res75 (& self) -> Res75R { Res75R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QsecrSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QsecrSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QsecrSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QsecrSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QsecrSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QsecrSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QsecrSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QsecrSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res75 (& mut self) -> Res75W < QsecrSpec > { Res75W :: new (self , 8) } } # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QsecrSpec ; impl crate :: RegisterSpec for QsecrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsecr::R`](R) reader structure"]
impl crate :: Readable for QsecrSpec { } # [doc = "`write(|w| ..)` method takes [`qsecr::W`](W) writer structure"]
impl crate :: Writable for QsecrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSECR to value 0"]
impl crate :: Resettable for QsecrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ER_RN (rw) register accessor: Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@er_rn`]
module"]
# [doc (alias = "ER_RN")]
pub type ErRn = crate :: Reg < er_rn :: ErRnSpec > ; # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register."]
pub mod er_rn { # [doc = "Register `ER_RN` reader"]
pub type R = crate :: R < ErRnSpec > ; # [doc = "Register `ER_RN` writer"]
pub type W = crate :: W < ErRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < ErRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < ErRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < ErRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < ErRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < ErRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < ErRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < ErRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < ErRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < ErRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < ErRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < ErRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < ErRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < ErRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < ErRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < ErRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < ErRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < ErRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < ErRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < ErRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < ErRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < ErRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < ErRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < ErRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < ErRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < ErRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < ErRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < ErRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < ErRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < ErRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < ErRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < ErRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < ErRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`er_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`er_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErRnSpec ; impl crate :: RegisterSpec for ErRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`er_rn::R`](R) reader structure"]
impl crate :: Readable for ErRnSpec { } # [doc = "`write(|w| ..)` method takes [`er_rn::W`](W) writer structure"]
impl crate :: Writable for ErRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ER_RN to value 0"]
impl crate :: Resettable for ErRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERH_RN (rw) register accessor: Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erh_rn`]
module"]
# [doc (alias = "ERH_RN")]
pub type ErhRn = crate :: Reg < erh_rn :: ErhRnSpec > ; # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register."]
pub mod erh_rn { # [doc = "Register `ERH_RN` reader"]
pub type R = crate :: R < ErhRnSpec > ; # [doc = "Register `ERH_RN` writer"]
pub type W = crate :: W < ErhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < ErhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < ErhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < ErhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < ErhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < ErhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < ErhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < ErhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < ErhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < ErhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < ErhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < ErhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < ErhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < ErhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < ErhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < ErhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < ErhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < ErhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < ErhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < ErhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < ErhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < ErhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < ErhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < ErhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < ErhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < ErhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < ErhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < ErhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < ErhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < ErhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < ErhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < ErhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < ErhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.\n\nYou can [`read`](crate::Reg::read) this register and get [`erh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErhRnSpec ; impl crate :: RegisterSpec for ErhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`erh_rn::R`](R) reader structure"]
impl crate :: Readable for ErhRnSpec { } # [doc = "`write(|w| ..)` method takes [`erh_rn::W`](W) writer structure"]
impl crate :: Writable for ErhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERH_RN to value 0"]
impl crate :: Resettable for ErhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECR_RN (rw) register accessor: Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr_rn`]
module"]
# [doc (alias = "ECR_RN")]
pub type EcrRn = crate :: Reg < ecr_rn :: EcrRnSpec > ; # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecr_rn { # [doc = "Register `ECR_RN` reader"]
pub type R = crate :: R < EcrRnSpec > ; # [doc = "Register `ECR_RN` writer"]
pub type W = crate :: W < EcrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EcrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EcrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EcrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EcrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EcrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EcrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EcrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EcrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EcrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EcrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EcrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EcrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EcrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EcrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EcrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EcrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EcrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EcrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EcrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EcrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EcrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EcrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EcrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EcrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EcrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EcrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EcrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EcrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EcrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EcrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EcrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EcrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrRnSpec ; impl crate :: RegisterSpec for EcrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecr_rn::R`](R) reader structure"]
impl crate :: Readable for EcrRnSpec { } # [doc = "`write(|w| ..)` method takes [`ecr_rn::W`](W) writer structure"]
impl crate :: Writable for EcrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECR_RN to value 0"]
impl crate :: Resettable for EcrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECRH_RN (rw) register accessor: Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecrh_rn`]
module"]
# [doc (alias = "ECRH_RN")]
pub type EcrhRn = crate :: Reg < ecrh_rn :: EcrhRnSpec > ; # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."]
pub mod ecrh_rn { # [doc = "Register `ECRH_RN` reader"]
pub type R = crate :: R < EcrhRnSpec > ; # [doc = "Register `ECRH_RN` writer"]
pub type W = crate :: W < EcrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EcrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EcrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EcrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EcrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EcrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EcrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EcrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EcrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EcrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EcrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EcrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EcrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EcrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EcrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EcrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EcrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EcrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EcrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EcrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EcrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EcrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EcrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EcrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EcrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EcrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EcrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EcrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EcrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EcrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EcrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EcrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EcrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`ecrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EcrhRnSpec ; impl crate :: RegisterSpec for EcrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecrh_rn::R`](R) reader structure"]
impl crate :: Readable for EcrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`ecrh_rn::W`](W) writer structure"]
impl crate :: Writable for EcrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECRH_RN to value 0"]
impl crate :: Resettable for EcrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESR_RN (rw) register accessor: Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr_rn`]
module"]
# [doc (alias = "ESR_RN")]
pub type EsrRn = crate :: Reg < esr_rn :: EsrRnSpec > ; # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."]
pub mod esr_rn { # [doc = "Register `ESR_RN` reader"]
pub type R = crate :: R < EsrRnSpec > ; # [doc = "Register `ESR_RN` writer"]
pub type W = crate :: W < EsrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EsrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EsrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EsrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EsrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EsrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EsrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EsrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EsrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EsrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EsrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EsrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EsrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EsrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EsrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EsrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EsrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EsrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EsrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EsrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EsrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EsrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EsrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EsrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EsrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EsrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EsrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EsrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EsrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EsrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EsrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EsrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EsrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrRnSpec ; impl crate :: RegisterSpec for EsrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esr_rn::R`](R) reader structure"]
impl crate :: Readable for EsrRnSpec { } # [doc = "`write(|w| ..)` method takes [`esr_rn::W`](W) writer structure"]
impl crate :: Writable for EsrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESR_RN to value 0"]
impl crate :: Resettable for EsrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESRH_RN (rw) register accessor: Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esrh_rn`]
module"]
# [doc (alias = "ESRH_RN")]
pub type EsrhRn = crate :: Reg < esrh_rn :: EsrhRnSpec > ; # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."]
pub mod esrh_rn { # [doc = "Register `ESRH_RN` reader"]
pub type R = crate :: R < EsrhRnSpec > ; # [doc = "Register `ESRH_RN` writer"]
pub type W = crate :: W < EsrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EsrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EsrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EsrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EsrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EsrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EsrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EsrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EsrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EsrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EsrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EsrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EsrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EsrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EsrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EsrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EsrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EsrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EsrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EsrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EsrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EsrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EsrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EsrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EsrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EsrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EsrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EsrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EsrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EsrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EsrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EsrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EsrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`esrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsrhRnSpec ; impl crate :: RegisterSpec for EsrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esrh_rn::R`](R) reader structure"]
impl crate :: Readable for EsrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`esrh_rn::W`](W) writer structure"]
impl crate :: Writable for EsrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESRH_RN to value 0"]
impl crate :: Resettable for EsrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CER_RN (rw) register accessor: Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cer_rn`]
module"]
# [doc (alias = "CER_RN")]
pub type CerRn = crate :: Reg < cer_rn :: CerRnSpec > ; # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software."]
pub mod cer_rn { # [doc = "Register `CER_RN` reader"]
pub type R = crate :: R < CerRnSpec > ; # [doc = "Register `CER_RN` writer"]
pub type W = crate :: W < CerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < CerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < CerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < CerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < CerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < CerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < CerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < CerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < CerRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < CerRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < CerRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < CerRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < CerRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < CerRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < CerRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < CerRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < CerRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < CerRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < CerRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < CerRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < CerRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < CerRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < CerRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < CerRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < CerRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < CerRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < CerRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < CerRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < CerRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < CerRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < CerRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < CerRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < CerRnSpec > { E31W :: new (self , 31) } } # [doc = "Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerRnSpec ; impl crate :: RegisterSpec for CerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cer_rn::R`](R) reader structure"]
impl crate :: Readable for CerRnSpec { } # [doc = "`write(|w| ..)` method takes [`cer_rn::W`](W) writer structure"]
impl crate :: Writable for CerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CER_RN to value 0"]
impl crate :: Resettable for CerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CERH_RN (rw) register accessor: Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cerh_rn`]
module"]
# [doc (alias = "CERH_RN")]
pub type CerhRn = crate :: Reg < cerh_rn :: CerhRnSpec > ; # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software."]
pub mod cerh_rn { # [doc = "Register `CERH_RN` reader"]
pub type R = crate :: R < CerhRnSpec > ; # [doc = "Register `CERH_RN` writer"]
pub type W = crate :: W < CerhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < CerhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < CerhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < CerhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < CerhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < CerhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < CerhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < CerhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < CerhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < CerhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < CerhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < CerhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < CerhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < CerhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < CerhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < CerhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < CerhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < CerhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < CerhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < CerhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < CerhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < CerhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < CerhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < CerhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < CerhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < CerhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < CerhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < CerhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < CerhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < CerhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < CerhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < CerhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < CerhRnSpec > { E63W :: new (self , 31) } } # [doc = "Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software.\n\nYou can [`read`](crate::Reg::read) this register and get [`cerh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cerh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CerhRnSpec ; impl crate :: RegisterSpec for CerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cerh_rn::R`](R) reader structure"]
impl crate :: Readable for CerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`cerh_rn::W`](W) writer structure"]
impl crate :: Writable for CerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CERH_RN to value 0"]
impl crate :: Resettable for CerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EER_RN (rw) register accessor: Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eer_rn`]
module"]
# [doc (alias = "EER_RN")]
pub type EerRn = crate :: Reg < eer_rn :: EerRnSpec > ; # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eer_rn { # [doc = "Register `EER_RN` reader"]
pub type R = crate :: R < EerRnSpec > ; # [doc = "Register `EER_RN` writer"]
pub type W = crate :: W < EerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EerRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EerRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EerRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EerRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EerRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EerRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EerRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EerRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EerRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EerRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EerRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EerRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EerRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EerRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EerRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EerRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EerRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EerRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EerRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EerRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EerRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EerRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EerRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EerRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EerRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerRnSpec ; impl crate :: RegisterSpec for EerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eer_rn::R`](R) reader structure"]
impl crate :: Readable for EerRnSpec { } # [doc = "`write(|w| ..)` method takes [`eer_rn::W`](W) writer structure"]
impl crate :: Writable for EerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EER_RN to value 0"]
impl crate :: Resettable for EerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EERH_RN (rw) register accessor: Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eerh_rn`]
module"]
# [doc (alias = "EERH_RN")]
pub type EerhRn = crate :: Reg < eerh_rn :: EerhRnSpec > ; # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers."]
pub mod eerh_rn { # [doc = "Register `EERH_RN` reader"]
pub type R = crate :: R < EerhRnSpec > ; # [doc = "Register `EERH_RN` writer"]
pub type W = crate :: W < EerhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EerhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EerhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EerhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EerhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EerhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EerhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EerhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EerhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EerhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EerhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EerhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EerhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EerhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EerhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EerhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EerhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EerhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EerhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EerhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EerhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EerhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EerhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EerhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EerhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EerhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EerhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EerhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EerhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EerhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EerhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EerhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EerhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`eerh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eerh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EerhRnSpec ; impl crate :: RegisterSpec for EerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eerh_rn::R`](R) reader structure"]
impl crate :: Readable for EerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`eerh_rn::W`](W) writer structure"]
impl crate :: Writable for EerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EERH_RN to value 0"]
impl crate :: Resettable for EerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECR_RN (rw) register accessor: Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecr_rn`]
module"]
# [doc (alias = "EECR_RN")]
pub type EecrRn = crate :: Reg < eecr_rn :: EecrRnSpec > ; # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecr_rn { # [doc = "Register `EECR_RN` reader"]
pub type R = crate :: R < EecrRnSpec > ; # [doc = "Register `EECR_RN` writer"]
pub type W = crate :: W < EecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EecrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EecrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EecrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EecrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EecrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EecrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EecrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EecrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EecrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EecrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EecrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EecrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EecrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EecrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EecrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EecrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EecrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EecrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EecrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EecrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EecrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EecrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EecrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EecrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrRnSpec ; impl crate :: RegisterSpec for EecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecr_rn::R`](R) reader structure"]
impl crate :: Readable for EecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`eecr_rn::W`](W) writer structure"]
impl crate :: Writable for EecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECR_RN to value 0"]
impl crate :: Resettable for EecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EECRH_RN (rw) register accessor: Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eecrh_rn`]
module"]
# [doc (alias = "EECRH_RN")]
pub type EecrhRn = crate :: Reg < eecrh_rn :: EecrhRnSpec > ; # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod eecrh_rn { # [doc = "Register `EECRH_RN` reader"]
pub type R = crate :: R < EecrhRnSpec > ; # [doc = "Register `EECRH_RN` writer"]
pub type W = crate :: W < EecrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EecrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EecrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EecrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EecrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EecrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EecrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EecrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EecrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EecrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EecrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EecrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EecrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EecrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EecrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EecrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EecrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EecrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EecrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EecrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EecrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EecrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EecrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EecrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EecrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EecrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EecrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EecrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EecrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EecrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EecrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EecrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EecrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eecrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eecrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EecrhRnSpec ; impl crate :: RegisterSpec for EecrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eecrh_rn::R`](R) reader structure"]
impl crate :: Readable for EecrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`eecrh_rn::W`](W) writer structure"]
impl crate :: Writable for EecrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EECRH_RN to value 0"]
impl crate :: Resettable for EecrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESR_RN (rw) register accessor: Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesr_rn`]
module"]
# [doc (alias = "EESR_RN")]
pub type EesrRn = crate :: Reg < eesr_rn :: EesrRnSpec > ; # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesr_rn { # [doc = "Register `EESR_RN` reader"]
pub type R = crate :: R < EesrRnSpec > ; # [doc = "Register `EESR_RN` writer"]
pub type W = crate :: W < EesrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < EesrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < EesrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < EesrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < EesrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < EesrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < EesrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < EesrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < EesrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < EesrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < EesrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < EesrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < EesrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < EesrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < EesrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < EesrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < EesrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < EesrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < EesrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < EesrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < EesrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < EesrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < EesrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < EesrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < EesrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < EesrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < EesrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < EesrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < EesrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < EesrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < EesrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < EesrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < EesrRnSpec > { E31W :: new (self , 31) } } # [doc = "Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrRnSpec ; impl crate :: RegisterSpec for EesrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesr_rn::R`](R) reader structure"]
impl crate :: Readable for EesrRnSpec { } # [doc = "`write(|w| ..)` method takes [`eesr_rn::W`](W) writer structure"]
impl crate :: Writable for EesrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESR_RN to value 0"]
impl crate :: Resettable for EesrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "EESRH_RN (rw) register accessor: Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eesrh_rn`]
module"]
# [doc (alias = "EESRH_RN")]
pub type EesrhRn = crate :: Reg < eesrh_rn :: EesrhRnSpec > ; # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."]
pub mod eesrh_rn { # [doc = "Register `EESRH_RN` reader"]
pub type R = crate :: R < EesrhRnSpec > ; # [doc = "Register `EESRH_RN` writer"]
pub type W = crate :: W < EesrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < EesrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < EesrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < EesrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < EesrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < EesrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < EesrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < EesrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < EesrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < EesrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < EesrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < EesrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < EesrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < EesrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < EesrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < EesrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < EesrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < EesrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < EesrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < EesrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < EesrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < EesrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < EesrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < EesrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < EesrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < EesrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < EesrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < EesrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < EesrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < EesrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < EesrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < EesrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < EesrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`eesrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eesrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EesrhRnSpec ; impl crate :: RegisterSpec for EesrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eesrh_rn::R`](R) reader structure"]
impl crate :: Readable for EesrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`eesrh_rn::W`](W) writer structure"]
impl crate :: Writable for EesrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EESRH_RN to value 0"]
impl crate :: Resettable for EesrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SER_RN (rw) register accessor: Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ser_rn`]
module"]
# [doc (alias = "SER_RN")]
pub type SerRn = crate :: Reg < ser_rn :: SerRnSpec > ; # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod ser_rn { # [doc = "Register `SER_RN` reader"]
pub type R = crate :: R < SerRnSpec > ; # [doc = "Register `SER_RN` writer"]
pub type W = crate :: W < SerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SerRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SerRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SerRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SerRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SerRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SerRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SerRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SerRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SerRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SerRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SerRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SerRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SerRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SerRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SerRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SerRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SerRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SerRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SerRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SerRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SerRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SerRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SerRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SerRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SerRnSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`ser_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerRnSpec ; impl crate :: RegisterSpec for SerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ser_rn::R`](R) reader structure"]
impl crate :: Readable for SerRnSpec { } # [doc = "`write(|w| ..)` method takes [`ser_rn::W`](W) writer structure"]
impl crate :: Writable for SerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SER_RN to value 0"]
impl crate :: Resettable for SerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SERH_RN (rw) register accessor: Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@serh_rn`]
module"]
# [doc (alias = "SERH_RN")]
pub type SerhRn = crate :: Reg < serh_rn :: SerhRnSpec > ; # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod serh_rn { # [doc = "Register `SERH_RN` reader"]
pub type R = crate :: R < SerhRnSpec > ; # [doc = "Register `SERH_RN` writer"]
pub type W = crate :: W < SerhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SerhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SerhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SerhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SerhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SerhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SerhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SerhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SerhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SerhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SerhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SerhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SerhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SerhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SerhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SerhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SerhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SerhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SerhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SerhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SerhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SerhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SerhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SerhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SerhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SerhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SerhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SerhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SerhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SerhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SerhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SerhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SerhRnSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`serh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SerhRnSpec ; impl crate :: RegisterSpec for SerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`serh_rn::R`](R) reader structure"]
impl crate :: Readable for SerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`serh_rn::W`](W) writer structure"]
impl crate :: Writable for SerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SERH_RN to value 0"]
impl crate :: Resettable for SerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECR_RN (rw) register accessor: Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secr_rn`]
module"]
# [doc (alias = "SECR_RN")]
pub type SecrRn = crate :: Reg < secr_rn :: SecrRnSpec > ; # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."]
pub mod secr_rn { # [doc = "Register `SECR_RN` reader"]
pub type R = crate :: R < SecrRnSpec > ; # [doc = "Register `SECR_RN` writer"]
pub type W = crate :: W < SecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E8` reader - 8:8\\]
Event #8"]
pub type E8R = crate :: BitReader ; # [doc = "Field `E8` writer - 8:8\\]
Event #8"]
pub type E8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E9` reader - 9:9\\]
Event #9"]
pub type E9R = crate :: BitReader ; # [doc = "Field `E9` writer - 9:9\\]
Event #9"]
pub type E9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E10` reader - 10:10\\]
Event #10"]
pub type E10R = crate :: BitReader ; # [doc = "Field `E10` writer - 10:10\\]
Event #10"]
pub type E10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E11` reader - 11:11\\]
Event #11"]
pub type E11R = crate :: BitReader ; # [doc = "Field `E11` writer - 11:11\\]
Event #11"]
pub type E11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E12` reader - 12:12\\]
Event #12"]
pub type E12R = crate :: BitReader ; # [doc = "Field `E12` writer - 12:12\\]
Event #12"]
pub type E12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E13` reader - 13:13\\]
Event #13"]
pub type E13R = crate :: BitReader ; # [doc = "Field `E13` writer - 13:13\\]
Event #13"]
pub type E13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E14` reader - 14:14\\]
Event #14"]
pub type E14R = crate :: BitReader ; # [doc = "Field `E14` writer - 14:14\\]
Event #14"]
pub type E14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E15` reader - 15:15\\]
Event #15"]
pub type E15R = crate :: BitReader ; # [doc = "Field `E15` writer - 15:15\\]
Event #15"]
pub type E15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E16` reader - 16:16\\]
Event #16"]
pub type E16R = crate :: BitReader ; # [doc = "Field `E16` writer - 16:16\\]
Event #16"]
pub type E16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E17` reader - 17:17\\]
Event #17"]
pub type E17R = crate :: BitReader ; # [doc = "Field `E17` writer - 17:17\\]
Event #17"]
pub type E17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E18` reader - 18:18\\]
Event #18"]
pub type E18R = crate :: BitReader ; # [doc = "Field `E18` writer - 18:18\\]
Event #18"]
pub type E18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E19` reader - 19:19\\]
Event #19"]
pub type E19R = crate :: BitReader ; # [doc = "Field `E19` writer - 19:19\\]
Event #19"]
pub type E19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E20` reader - 20:20\\]
Event #20"]
pub type E20R = crate :: BitReader ; # [doc = "Field `E20` writer - 20:20\\]
Event #20"]
pub type E20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E21` reader - 21:21\\]
Event #21"]
pub type E21R = crate :: BitReader ; # [doc = "Field `E21` writer - 21:21\\]
Event #21"]
pub type E21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E22` reader - 22:22\\]
Event #22"]
pub type E22R = crate :: BitReader ; # [doc = "Field `E22` writer - 22:22\\]
Event #22"]
pub type E22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E23` reader - 23:23\\]
Event #23"]
pub type E23R = crate :: BitReader ; # [doc = "Field `E23` writer - 23:23\\]
Event #23"]
pub type E23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E24` reader - 24:24\\]
Event #24"]
pub type E24R = crate :: BitReader ; # [doc = "Field `E24` writer - 24:24\\]
Event #24"]
pub type E24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E25` reader - 25:25\\]
Event #25"]
pub type E25R = crate :: BitReader ; # [doc = "Field `E25` writer - 25:25\\]
Event #25"]
pub type E25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E26` reader - 26:26\\]
Event #26"]
pub type E26R = crate :: BitReader ; # [doc = "Field `E26` writer - 26:26\\]
Event #26"]
pub type E26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E27` reader - 27:27\\]
Event #27"]
pub type E27R = crate :: BitReader ; # [doc = "Field `E27` writer - 27:27\\]
Event #27"]
pub type E27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E28` reader - 28:28\\]
Event #28"]
pub type E28R = crate :: BitReader ; # [doc = "Field `E28` writer - 28:28\\]
Event #28"]
pub type E28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E29` reader - 29:29\\]
Event #29"]
pub type E29R = crate :: BitReader ; # [doc = "Field `E29` writer - 29:29\\]
Event #29"]
pub type E29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E30` reader - 30:30\\]
Event #30"]
pub type E30R = crate :: BitReader ; # [doc = "Field `E30` writer - 30:30\\]
Event #30"]
pub type E30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E31` reader - 31:31\\]
Event #31"]
pub type E31R = crate :: BitReader ; # [doc = "Field `E31` writer - 31:31\\]
Event #31"]
pub type E31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
pub fn e8 (& self) -> E8R { E8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
pub fn e9 (& self) -> E9R { E9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
pub fn e10 (& self) -> E10R { E10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
pub fn e11 (& self) -> E11R { E11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
pub fn e12 (& self) -> E12R { E12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
pub fn e13 (& self) -> E13R { E13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
pub fn e14 (& self) -> E14R { E14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
pub fn e15 (& self) -> E15R { E15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
pub fn e16 (& self) -> E16R { E16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
pub fn e17 (& self) -> E17R { E17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
pub fn e18 (& self) -> E18R { E18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
pub fn e19 (& self) -> E19R { E19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
pub fn e20 (& self) -> E20R { E20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
pub fn e21 (& self) -> E21R { E21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
pub fn e22 (& self) -> E22R { E22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
pub fn e23 (& self) -> E23R { E23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
pub fn e24 (& self) -> E24R { E24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
pub fn e25 (& self) -> E25R { E25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
pub fn e26 (& self) -> E26R { E26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
pub fn e27 (& self) -> E27R { E27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
pub fn e28 (& self) -> E28R { E28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
pub fn e29 (& self) -> E29R { E29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
pub fn e30 (& self) -> E30R { E30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
pub fn e31 (& self) -> E31R { E31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < SecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < SecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < SecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < SecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < SecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < SecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < SecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < SecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #8"]
# [inline (always)]
# [must_use]
pub fn e8 (& mut self) -> E8W < SecrRnSpec > { E8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #9"]
# [inline (always)]
# [must_use]
pub fn e9 (& mut self) -> E9W < SecrRnSpec > { E9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #10"]
# [inline (always)]
# [must_use]
pub fn e10 (& mut self) -> E10W < SecrRnSpec > { E10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #11"]
# [inline (always)]
# [must_use]
pub fn e11 (& mut self) -> E11W < SecrRnSpec > { E11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #12"]
# [inline (always)]
# [must_use]
pub fn e12 (& mut self) -> E12W < SecrRnSpec > { E12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #13"]
# [inline (always)]
# [must_use]
pub fn e13 (& mut self) -> E13W < SecrRnSpec > { E13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #14"]
# [inline (always)]
# [must_use]
pub fn e14 (& mut self) -> E14W < SecrRnSpec > { E14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #15"]
# [inline (always)]
# [must_use]
pub fn e15 (& mut self) -> E15W < SecrRnSpec > { E15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #16"]
# [inline (always)]
# [must_use]
pub fn e16 (& mut self) -> E16W < SecrRnSpec > { E16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #17"]
# [inline (always)]
# [must_use]
pub fn e17 (& mut self) -> E17W < SecrRnSpec > { E17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #18"]
# [inline (always)]
# [must_use]
pub fn e18 (& mut self) -> E18W < SecrRnSpec > { E18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #19"]
# [inline (always)]
# [must_use]
pub fn e19 (& mut self) -> E19W < SecrRnSpec > { E19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #20"]
# [inline (always)]
# [must_use]
pub fn e20 (& mut self) -> E20W < SecrRnSpec > { E20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #21"]
# [inline (always)]
# [must_use]
pub fn e21 (& mut self) -> E21W < SecrRnSpec > { E21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #22"]
# [inline (always)]
# [must_use]
pub fn e22 (& mut self) -> E22W < SecrRnSpec > { E22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #23"]
# [inline (always)]
# [must_use]
pub fn e23 (& mut self) -> E23W < SecrRnSpec > { E23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #24"]
# [inline (always)]
# [must_use]
pub fn e24 (& mut self) -> E24W < SecrRnSpec > { E24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #25"]
# [inline (always)]
# [must_use]
pub fn e25 (& mut self) -> E25W < SecrRnSpec > { E25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #26"]
# [inline (always)]
# [must_use]
pub fn e26 (& mut self) -> E26W < SecrRnSpec > { E26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #27"]
# [inline (always)]
# [must_use]
pub fn e27 (& mut self) -> E27W < SecrRnSpec > { E27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #28"]
# [inline (always)]
# [must_use]
pub fn e28 (& mut self) -> E28W < SecrRnSpec > { E28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #29"]
# [inline (always)]
# [must_use]
pub fn e29 (& mut self) -> E29W < SecrRnSpec > { E29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #30"]
# [inline (always)]
# [must_use]
pub fn e30 (& mut self) -> E30W < SecrRnSpec > { E30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #31"]
# [inline (always)]
# [must_use]
pub fn e31 (& mut self) -> E31W < SecrRnSpec > { E31W :: new (self , 31) } } # [doc = "Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrRnSpec ; impl crate :: RegisterSpec for SecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secr_rn::R`](R) reader structure"]
impl crate :: Readable for SecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`secr_rn::W`](W) writer structure"]
impl crate :: Writable for SecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECR_RN to value 0"]
impl crate :: Resettable for SecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECRH_RN (rw) register accessor: Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secrh_rn`]
module"]
# [doc (alias = "SECRH_RN")]
pub type SecrhRn = crate :: Reg < secrh_rn :: SecrhRnSpec > ; # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."]
pub mod secrh_rn { # [doc = "Register `SECRH_RN` reader"]
pub type R = crate :: R < SecrhRnSpec > ; # [doc = "Register `SECRH_RN` writer"]
pub type W = crate :: W < SecrhRnSpec > ; # [doc = "Field `E32` reader - 0:0\\]
Event #32"]
pub type E32R = crate :: BitReader ; # [doc = "Field `E32` writer - 0:0\\]
Event #32"]
pub type E32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E33` reader - 1:1\\]
Event #33"]
pub type E33R = crate :: BitReader ; # [doc = "Field `E33` writer - 1:1\\]
Event #33"]
pub type E33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E34` reader - 2:2\\]
Event #34"]
pub type E34R = crate :: BitReader ; # [doc = "Field `E34` writer - 2:2\\]
Event #34"]
pub type E34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E35` reader - 3:3\\]
Event #35"]
pub type E35R = crate :: BitReader ; # [doc = "Field `E35` writer - 3:3\\]
Event #35"]
pub type E35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E36` reader - 4:4\\]
Event #36"]
pub type E36R = crate :: BitReader ; # [doc = "Field `E36` writer - 4:4\\]
Event #36"]
pub type E36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E37` reader - 5:5\\]
Event #37"]
pub type E37R = crate :: BitReader ; # [doc = "Field `E37` writer - 5:5\\]
Event #37"]
pub type E37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E38` reader - 6:6\\]
Event #38"]
pub type E38R = crate :: BitReader ; # [doc = "Field `E38` writer - 6:6\\]
Event #38"]
pub type E38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E39` reader - 7:7\\]
Event #39"]
pub type E39R = crate :: BitReader ; # [doc = "Field `E39` writer - 7:7\\]
Event #39"]
pub type E39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E40` reader - 8:8\\]
Event #40"]
pub type E40R = crate :: BitReader ; # [doc = "Field `E40` writer - 8:8\\]
Event #40"]
pub type E40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E41` reader - 9:9\\]
Event #41"]
pub type E41R = crate :: BitReader ; # [doc = "Field `E41` writer - 9:9\\]
Event #41"]
pub type E41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E42` reader - 10:10\\]
Event #42"]
pub type E42R = crate :: BitReader ; # [doc = "Field `E42` writer - 10:10\\]
Event #42"]
pub type E42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E43` reader - 11:11\\]
Event #43"]
pub type E43R = crate :: BitReader ; # [doc = "Field `E43` writer - 11:11\\]
Event #43"]
pub type E43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E44` reader - 12:12\\]
Event #44"]
pub type E44R = crate :: BitReader ; # [doc = "Field `E44` writer - 12:12\\]
Event #44"]
pub type E44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E45` reader - 13:13\\]
Event #45"]
pub type E45R = crate :: BitReader ; # [doc = "Field `E45` writer - 13:13\\]
Event #45"]
pub type E45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E46` reader - 14:14\\]
Event #46"]
pub type E46R = crate :: BitReader ; # [doc = "Field `E46` writer - 14:14\\]
Event #46"]
pub type E46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E47` reader - 15:15\\]
Event #47"]
pub type E47R = crate :: BitReader ; # [doc = "Field `E47` writer - 15:15\\]
Event #47"]
pub type E47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E48` reader - 16:16\\]
Event #48"]
pub type E48R = crate :: BitReader ; # [doc = "Field `E48` writer - 16:16\\]
Event #48"]
pub type E48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E49` reader - 17:17\\]
Event #49"]
pub type E49R = crate :: BitReader ; # [doc = "Field `E49` writer - 17:17\\]
Event #49"]
pub type E49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E50` reader - 18:18\\]
Event #50"]
pub type E50R = crate :: BitReader ; # [doc = "Field `E50` writer - 18:18\\]
Event #50"]
pub type E50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E51` reader - 19:19\\]
Event #51"]
pub type E51R = crate :: BitReader ; # [doc = "Field `E51` writer - 19:19\\]
Event #51"]
pub type E51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E52` reader - 20:20\\]
Event #52"]
pub type E52R = crate :: BitReader ; # [doc = "Field `E52` writer - 20:20\\]
Event #52"]
pub type E52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E53` reader - 21:21\\]
Event #53"]
pub type E53R = crate :: BitReader ; # [doc = "Field `E53` writer - 21:21\\]
Event #53"]
pub type E53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E54` reader - 22:22\\]
Event #54"]
pub type E54R = crate :: BitReader ; # [doc = "Field `E54` writer - 22:22\\]
Event #54"]
pub type E54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E55` reader - 23:23\\]
Event #55"]
pub type E55R = crate :: BitReader ; # [doc = "Field `E55` writer - 23:23\\]
Event #55"]
pub type E55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E56` reader - 24:24\\]
Event #56"]
pub type E56R = crate :: BitReader ; # [doc = "Field `E56` writer - 24:24\\]
Event #56"]
pub type E56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E57` reader - 25:25\\]
Event #57"]
pub type E57R = crate :: BitReader ; # [doc = "Field `E57` writer - 25:25\\]
Event #57"]
pub type E57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E58` reader - 26:26\\]
Event #58"]
pub type E58R = crate :: BitReader ; # [doc = "Field `E58` writer - 26:26\\]
Event #58"]
pub type E58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E59` reader - 27:27\\]
Event #59"]
pub type E59R = crate :: BitReader ; # [doc = "Field `E59` writer - 27:27\\]
Event #59"]
pub type E59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E60` reader - 28:28\\]
Event #60"]
pub type E60R = crate :: BitReader ; # [doc = "Field `E60` writer - 28:28\\]
Event #60"]
pub type E60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E61` reader - 29:29\\]
Event #61"]
pub type E61R = crate :: BitReader ; # [doc = "Field `E61` writer - 29:29\\]
Event #61"]
pub type E61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E62` reader - 30:30\\]
Event #62"]
pub type E62R = crate :: BitReader ; # [doc = "Field `E62` writer - 30:30\\]
Event #62"]
pub type E62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E63` reader - 31:31\\]
Event #63"]
pub type E63R = crate :: BitReader ; # [doc = "Field `E63` writer - 31:31\\]
Event #63"]
pub type E63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
pub fn e32 (& self) -> E32R { E32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
pub fn e33 (& self) -> E33R { E33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
pub fn e34 (& self) -> E34R { E34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
pub fn e35 (& self) -> E35R { E35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
pub fn e36 (& self) -> E36R { E36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
pub fn e37 (& self) -> E37R { E37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
pub fn e38 (& self) -> E38R { E38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
pub fn e39 (& self) -> E39R { E39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
pub fn e40 (& self) -> E40R { E40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
pub fn e41 (& self) -> E41R { E41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
pub fn e42 (& self) -> E42R { E42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
pub fn e43 (& self) -> E43R { E43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
pub fn e44 (& self) -> E44R { E44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
pub fn e45 (& self) -> E45R { E45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
pub fn e46 (& self) -> E46R { E46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
pub fn e47 (& self) -> E47R { E47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
pub fn e48 (& self) -> E48R { E48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
pub fn e49 (& self) -> E49R { E49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
pub fn e50 (& self) -> E50R { E50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
pub fn e51 (& self) -> E51R { E51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
pub fn e52 (& self) -> E52R { E52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
pub fn e53 (& self) -> E53R { E53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
pub fn e54 (& self) -> E54R { E54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
pub fn e55 (& self) -> E55R { E55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
pub fn e56 (& self) -> E56R { E56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
pub fn e57 (& self) -> E57R { E57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
pub fn e58 (& self) -> E58R { E58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
pub fn e59 (& self) -> E59R { E59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
pub fn e60 (& self) -> E60R { E60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
pub fn e61 (& self) -> E61R { E61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
pub fn e62 (& self) -> E62R { E62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
pub fn e63 (& self) -> E63R { E63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #32"]
# [inline (always)]
# [must_use]
pub fn e32 (& mut self) -> E32W < SecrhRnSpec > { E32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #33"]
# [inline (always)]
# [must_use]
pub fn e33 (& mut self) -> E33W < SecrhRnSpec > { E33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #34"]
# [inline (always)]
# [must_use]
pub fn e34 (& mut self) -> E34W < SecrhRnSpec > { E34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #35"]
# [inline (always)]
# [must_use]
pub fn e35 (& mut self) -> E35W < SecrhRnSpec > { E35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #36"]
# [inline (always)]
# [must_use]
pub fn e36 (& mut self) -> E36W < SecrhRnSpec > { E36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #37"]
# [inline (always)]
# [must_use]
pub fn e37 (& mut self) -> E37W < SecrhRnSpec > { E37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #38"]
# [inline (always)]
# [must_use]
pub fn e38 (& mut self) -> E38W < SecrhRnSpec > { E38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #39"]
# [inline (always)]
# [must_use]
pub fn e39 (& mut self) -> E39W < SecrhRnSpec > { E39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Event #40"]
# [inline (always)]
# [must_use]
pub fn e40 (& mut self) -> E40W < SecrhRnSpec > { E40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Event #41"]
# [inline (always)]
# [must_use]
pub fn e41 (& mut self) -> E41W < SecrhRnSpec > { E41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Event #42"]
# [inline (always)]
# [must_use]
pub fn e42 (& mut self) -> E42W < SecrhRnSpec > { E42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Event #43"]
# [inline (always)]
# [must_use]
pub fn e43 (& mut self) -> E43W < SecrhRnSpec > { E43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Event #44"]
# [inline (always)]
# [must_use]
pub fn e44 (& mut self) -> E44W < SecrhRnSpec > { E44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Event #45"]
# [inline (always)]
# [must_use]
pub fn e45 (& mut self) -> E45W < SecrhRnSpec > { E45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Event #46"]
# [inline (always)]
# [must_use]
pub fn e46 (& mut self) -> E46W < SecrhRnSpec > { E46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Event #47"]
# [inline (always)]
# [must_use]
pub fn e47 (& mut self) -> E47W < SecrhRnSpec > { E47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Event #48"]
# [inline (always)]
# [must_use]
pub fn e48 (& mut self) -> E48W < SecrhRnSpec > { E48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Event #49"]
# [inline (always)]
# [must_use]
pub fn e49 (& mut self) -> E49W < SecrhRnSpec > { E49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Event #50"]
# [inline (always)]
# [must_use]
pub fn e50 (& mut self) -> E50W < SecrhRnSpec > { E50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Event #51"]
# [inline (always)]
# [must_use]
pub fn e51 (& mut self) -> E51W < SecrhRnSpec > { E51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Event #52"]
# [inline (always)]
# [must_use]
pub fn e52 (& mut self) -> E52W < SecrhRnSpec > { E52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Event #53"]
# [inline (always)]
# [must_use]
pub fn e53 (& mut self) -> E53W < SecrhRnSpec > { E53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Event #54"]
# [inline (always)]
# [must_use]
pub fn e54 (& mut self) -> E54W < SecrhRnSpec > { E54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Event #55"]
# [inline (always)]
# [must_use]
pub fn e55 (& mut self) -> E55W < SecrhRnSpec > { E55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Event #56"]
# [inline (always)]
# [must_use]
pub fn e56 (& mut self) -> E56W < SecrhRnSpec > { E56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Event #57"]
# [inline (always)]
# [must_use]
pub fn e57 (& mut self) -> E57W < SecrhRnSpec > { E57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Event #58"]
# [inline (always)]
# [must_use]
pub fn e58 (& mut self) -> E58W < SecrhRnSpec > { E58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Event #59"]
# [inline (always)]
# [must_use]
pub fn e59 (& mut self) -> E59W < SecrhRnSpec > { E59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Event #60"]
# [inline (always)]
# [must_use]
pub fn e60 (& mut self) -> E60W < SecrhRnSpec > { E60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Event #61"]
# [inline (always)]
# [must_use]
pub fn e61 (& mut self) -> E61W < SecrhRnSpec > { E61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Event #62"]
# [inline (always)]
# [must_use]
pub fn e62 (& mut self) -> E62W < SecrhRnSpec > { E62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Event #63"]
# [inline (always)]
# [must_use]
pub fn e63 (& mut self) -> E63W < SecrhRnSpec > { E63W :: new (self , 31) } } # [doc = "Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect.\n\nYou can [`read`](crate::Reg::read) this register and get [`secrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecrhRnSpec ; impl crate :: RegisterSpec for SecrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secrh_rn::R`](R) reader structure"]
impl crate :: Readable for SecrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`secrh_rn::W`](W) writer structure"]
impl crate :: Writable for SecrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECRH_RN to value 0"]
impl crate :: Resettable for SecrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IER_RN (rw) register accessor: Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier_rn`]
module"]
# [doc (alias = "IER_RN")]
pub type IerRn = crate :: Reg < ier_rn :: IerRnSpec > ; # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."]
pub mod ier_rn { # [doc = "Register `IER_RN` reader"]
pub type R = crate :: R < IerRnSpec > ; # [doc = "Register `IER_RN` writer"]
pub type W = crate :: W < IerRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IerRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IerRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IerRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IerRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IerRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IerRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IerRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IerRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IerRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IerRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IerRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IerRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IerRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IerRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IerRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IerRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IerRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IerRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IerRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IerRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IerRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IerRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IerRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IerRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IerRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IerRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IerRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IerRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IerRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IerRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IerRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IerRnSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ier_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerRnSpec ; impl crate :: RegisterSpec for IerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ier_rn::R`](R) reader structure"]
impl crate :: Readable for IerRnSpec { } # [doc = "`write(|w| ..)` method takes [`ier_rn::W`](W) writer structure"]
impl crate :: Writable for IerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IER_RN to value 0"]
impl crate :: Resettable for IerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IERH_RN (rw) register accessor: Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ierh_rn`]
module"]
# [doc (alias = "IERH_RN")]
pub type IerhRn = crate :: Reg < ierh_rn :: IerhRnSpec > ; # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts."]
pub mod ierh_rn { # [doc = "Register `IERH_RN` reader"]
pub type R = crate :: R < IerhRnSpec > ; # [doc = "Register `IERH_RN` writer"]
pub type W = crate :: W < IerhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IerhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IerhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IerhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IerhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IerhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IerhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IerhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IerhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IerhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IerhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IerhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IerhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IerhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IerhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IerhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IerhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IerhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IerhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IerhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IerhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IerhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IerhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IerhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IerhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IerhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IerhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IerhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IerhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IerhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IerhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IerhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IerhRnSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`ierh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ierh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerhRnSpec ; impl crate :: RegisterSpec for IerhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ierh_rn::R`](R) reader structure"]
impl crate :: Readable for IerhRnSpec { } # [doc = "`write(|w| ..)` method takes [`ierh_rn::W`](W) writer structure"]
impl crate :: Writable for IerhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IERH_RN to value 0"]
impl crate :: Resettable for IerhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECR_RN (rw) register accessor: Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecr_rn`]
module"]
# [doc (alias = "IECR_RN")]
pub type IecrRn = crate :: Reg < iecr_rn :: IecrRnSpec > ; # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecr_rn { # [doc = "Register `IECR_RN` reader"]
pub type R = crate :: R < IecrRnSpec > ; # [doc = "Register `IECR_RN` writer"]
pub type W = crate :: W < IecrRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IecrRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IecrRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IecrRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IecrRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IecrRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IecrRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IecrRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IecrRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IecrRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IecrRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IecrRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IecrRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IecrRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IecrRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IecrRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IecrRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IecrRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IecrRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IecrRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IecrRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IecrRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IecrRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IecrRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IecrRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IecrRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IecrRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IecrRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IecrRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IecrRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IecrRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IecrRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IecrRnSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrRnSpec ; impl crate :: RegisterSpec for IecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecr_rn::R`](R) reader structure"]
impl crate :: Readable for IecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`iecr_rn::W`](W) writer structure"]
impl crate :: Writable for IecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECR_RN to value 0"]
impl crate :: Resettable for IecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IECRH_RN (rw) register accessor: Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecrh_rn`]
module"]
# [doc (alias = "IECRH_RN")]
pub type IecrhRn = crate :: Reg < iecrh_rn :: IecrhRnSpec > ; # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."]
pub mod iecrh_rn { # [doc = "Register `IECRH_RN` reader"]
pub type R = crate :: R < IecrhRnSpec > ; # [doc = "Register `IECRH_RN` writer"]
pub type W = crate :: W < IecrhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IecrhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IecrhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IecrhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IecrhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IecrhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IecrhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IecrhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IecrhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IecrhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IecrhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IecrhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IecrhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IecrhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IecrhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IecrhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IecrhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IecrhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IecrhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IecrhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IecrhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IecrhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IecrhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IecrhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IecrhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IecrhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IecrhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IecrhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IecrhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IecrhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IecrhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IecrhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IecrhRnSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iecrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iecrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IecrhRnSpec ; impl crate :: RegisterSpec for IecrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iecrh_rn::R`](R) reader structure"]
impl crate :: Readable for IecrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`iecrh_rn::W`](W) writer structure"]
impl crate :: Writable for IecrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IECRH_RN to value 0"]
impl crate :: Resettable for IecrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESR_RN (rw) register accessor: Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesr_rn`]
module"]
# [doc (alias = "IESR_RN")]
pub type IesrRn = crate :: Reg < iesr_rn :: IesrRnSpec > ; # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesr_rn { # [doc = "Register `IESR_RN` reader"]
pub type R = crate :: R < IesrRnSpec > ; # [doc = "Register `IESR_RN` writer"]
pub type W = crate :: W < IesrRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IesrRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IesrRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IesrRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IesrRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IesrRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IesrRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IesrRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IesrRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IesrRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IesrRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IesrRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IesrRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IesrRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IesrRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IesrRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IesrRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IesrRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IesrRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IesrRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IesrRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IesrRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IesrRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IesrRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IesrRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IesrRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IesrRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IesrRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IesrRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IesrRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IesrRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IesrRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IesrRnSpec > { I31W :: new (self , 31) } } # [doc = "Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrRnSpec ; impl crate :: RegisterSpec for IesrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesr_rn::R`](R) reader structure"]
impl crate :: Readable for IesrRnSpec { } # [doc = "`write(|w| ..)` method takes [`iesr_rn::W`](W) writer structure"]
impl crate :: Writable for IesrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESR_RN to value 0"]
impl crate :: Resettable for IesrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IESRH_RN (rw) register accessor: Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesrh_rn`]
module"]
# [doc (alias = "IESRH_RN")]
pub type IesrhRn = crate :: Reg < iesrh_rn :: IesrhRnSpec > ; # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."]
pub mod iesrh_rn { # [doc = "Register `IESRH_RN` reader"]
pub type R = crate :: R < IesrhRnSpec > ; # [doc = "Register `IESRH_RN` writer"]
pub type W = crate :: W < IesrhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IesrhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IesrhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IesrhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IesrhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IesrhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IesrhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IesrhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IesrhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IesrhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IesrhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IesrhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IesrhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IesrhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IesrhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IesrhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IesrhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IesrhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IesrhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IesrhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IesrhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IesrhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IesrhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IesrhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IesrhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IesrhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IesrhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IesrhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IesrhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IesrhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IesrhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IesrhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IesrhRnSpec > { I63W :: new (self , 31) } } # [doc = "Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`iesrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iesrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IesrhRnSpec ; impl crate :: RegisterSpec for IesrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iesrh_rn::R`](R) reader structure"]
impl crate :: Readable for IesrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`iesrh_rn::W`](W) writer structure"]
impl crate :: Writable for IesrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IESRH_RN to value 0"]
impl crate :: Resettable for IesrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPR_RN (rw) register accessor: Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipr_rn`]
module"]
# [doc (alias = "IPR_RN")]
pub type IprRn = crate :: Reg < ipr_rn :: IprRnSpec > ; # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."]
pub mod ipr_rn { # [doc = "Register `IPR_RN` reader"]
pub type R = crate :: R < IprRnSpec > ; # [doc = "Register `IPR_RN` writer"]
pub type W = crate :: W < IprRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IprRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IprRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IprRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IprRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IprRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IprRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IprRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IprRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IprRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IprRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IprRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IprRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IprRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IprRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IprRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IprRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IprRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IprRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IprRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IprRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IprRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IprRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IprRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IprRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IprRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IprRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IprRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IprRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IprRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IprRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IprRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IprRnSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`ipr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprRnSpec ; impl crate :: RegisterSpec for IprRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipr_rn::R`](R) reader structure"]
impl crate :: Readable for IprRnSpec { } # [doc = "`write(|w| ..)` method takes [`ipr_rn::W`](W) writer structure"]
impl crate :: Writable for IprRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPR_RN to value 0"]
impl crate :: Resettable for IprRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPRH_RN (rw) register accessor: Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iprh_rn`]
module"]
# [doc (alias = "IPRH_RN")]
pub type IprhRn = crate :: Reg < iprh_rn :: IprhRnSpec > ; # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."]
pub mod iprh_rn { # [doc = "Register `IPRH_RN` reader"]
pub type R = crate :: R < IprhRnSpec > ; # [doc = "Register `IPRH_RN` writer"]
pub type W = crate :: W < IprhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IprhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IprhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IprhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IprhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IprhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IprhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IprhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IprhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IprhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IprhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IprhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IprhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IprhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IprhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IprhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IprhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IprhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IprhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IprhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IprhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IprhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IprhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IprhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IprhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IprhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IprhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IprhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IprhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IprhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IprhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IprhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IprhRnSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit.\n\nYou can [`read`](crate::Reg::read) this register and get [`iprh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iprh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IprhRnSpec ; impl crate :: RegisterSpec for IprhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iprh_rn::R`](R) reader structure"]
impl crate :: Readable for IprhRnSpec { } # [doc = "`write(|w| ..)` method takes [`iprh_rn::W`](W) writer structure"]
impl crate :: Writable for IprhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPRH_RN to value 0"]
impl crate :: Resettable for IprhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICR_RN (rw) register accessor: Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr_rn`]
module"]
# [doc (alias = "ICR_RN")]
pub type IcrRn = crate :: Reg < icr_rn :: IcrRnSpec > ; # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icr_rn { # [doc = "Register `ICR_RN` reader"]
pub type R = crate :: R < IcrRnSpec > ; # [doc = "Register `ICR_RN` writer"]
pub type W = crate :: W < IcrRnSpec > ; # [doc = "Field `I0` reader - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0R = crate :: BitReader ; # [doc = "Field `I0` writer - 0:0\\]
Interrupt associated with TCC #0"]
pub type I0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I1` reader - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1R = crate :: BitReader ; # [doc = "Field `I1` writer - 1:1\\]
Interrupt associated with TCC #1"]
pub type I1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2` reader - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2R = crate :: BitReader ; # [doc = "Field `I2` writer - 2:2\\]
Interrupt associated with TCC #2"]
pub type I2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I3` reader - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3R = crate :: BitReader ; # [doc = "Field `I3` writer - 3:3\\]
Interrupt associated with TCC #3"]
pub type I3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I4` reader - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4R = crate :: BitReader ; # [doc = "Field `I4` writer - 4:4\\]
Interrupt associated with TCC #4"]
pub type I4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I5` reader - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5R = crate :: BitReader ; # [doc = "Field `I5` writer - 5:5\\]
Interrupt associated with TCC #5"]
pub type I5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I6` reader - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6R = crate :: BitReader ; # [doc = "Field `I6` writer - 6:6\\]
Interrupt associated with TCC #6"]
pub type I6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I7` reader - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7R = crate :: BitReader ; # [doc = "Field `I7` writer - 7:7\\]
Interrupt associated with TCC #7"]
pub type I7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I8` reader - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8R = crate :: BitReader ; # [doc = "Field `I8` writer - 8:8\\]
Interrupt associated with TCC #8"]
pub type I8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I9` reader - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9R = crate :: BitReader ; # [doc = "Field `I9` writer - 9:9\\]
Interrupt associated with TCC #9"]
pub type I9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I10` reader - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10R = crate :: BitReader ; # [doc = "Field `I10` writer - 10:10\\]
Interrupt associated with TCC #10"]
pub type I10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I11` reader - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11R = crate :: BitReader ; # [doc = "Field `I11` writer - 11:11\\]
Interrupt associated with TCC #11"]
pub type I11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I12` reader - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12R = crate :: BitReader ; # [doc = "Field `I12` writer - 12:12\\]
Interrupt associated with TCC #12"]
pub type I12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I13` reader - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13R = crate :: BitReader ; # [doc = "Field `I13` writer - 13:13\\]
Interrupt associated with TCC #13"]
pub type I13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I14` reader - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14R = crate :: BitReader ; # [doc = "Field `I14` writer - 14:14\\]
Interrupt associated with TCC #14"]
pub type I14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I15` reader - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15R = crate :: BitReader ; # [doc = "Field `I15` writer - 15:15\\]
Interrupt associated with TCC #15"]
pub type I15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I16` reader - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16R = crate :: BitReader ; # [doc = "Field `I16` writer - 16:16\\]
Interrupt associated with TCC #16"]
pub type I16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I17` reader - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17R = crate :: BitReader ; # [doc = "Field `I17` writer - 17:17\\]
Interrupt associated with TCC #17"]
pub type I17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I18` reader - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18R = crate :: BitReader ; # [doc = "Field `I18` writer - 18:18\\]
Interrupt associated with TCC #18"]
pub type I18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I19` reader - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19R = crate :: BitReader ; # [doc = "Field `I19` writer - 19:19\\]
Interrupt associated with TCC #19"]
pub type I19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I20` reader - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20R = crate :: BitReader ; # [doc = "Field `I20` writer - 20:20\\]
Interrupt associated with TCC #20"]
pub type I20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I21` reader - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21R = crate :: BitReader ; # [doc = "Field `I21` writer - 21:21\\]
Interrupt associated with TCC #21"]
pub type I21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I22` reader - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22R = crate :: BitReader ; # [doc = "Field `I22` writer - 22:22\\]
Interrupt associated with TCC #22"]
pub type I22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I23` reader - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23R = crate :: BitReader ; # [doc = "Field `I23` writer - 23:23\\]
Interrupt associated with TCC #23"]
pub type I23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I24` reader - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24R = crate :: BitReader ; # [doc = "Field `I24` writer - 24:24\\]
Interrupt associated with TCC #24"]
pub type I24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I25` reader - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25R = crate :: BitReader ; # [doc = "Field `I25` writer - 25:25\\]
Interrupt associated with TCC #25"]
pub type I25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I26` reader - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26R = crate :: BitReader ; # [doc = "Field `I26` writer - 26:26\\]
Interrupt associated with TCC #26"]
pub type I26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I27` reader - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27R = crate :: BitReader ; # [doc = "Field `I27` writer - 27:27\\]
Interrupt associated with TCC #27"]
pub type I27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I28` reader - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28R = crate :: BitReader ; # [doc = "Field `I28` writer - 28:28\\]
Interrupt associated with TCC #28"]
pub type I28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I29` reader - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29R = crate :: BitReader ; # [doc = "Field `I29` writer - 29:29\\]
Interrupt associated with TCC #29"]
pub type I29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I30` reader - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30R = crate :: BitReader ; # [doc = "Field `I30` writer - 30:30\\]
Interrupt associated with TCC #30"]
pub type I30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I31` reader - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31R = crate :: BitReader ; # [doc = "Field `I31` writer - 31:31\\]
Interrupt associated with TCC #31"]
pub type I31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
pub fn i0 (& self) -> I0R { I0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
pub fn i1 (& self) -> I1R { I1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
pub fn i2 (& self) -> I2R { I2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
pub fn i3 (& self) -> I3R { I3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
pub fn i4 (& self) -> I4R { I4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
pub fn i5 (& self) -> I5R { I5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
pub fn i6 (& self) -> I6R { I6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
pub fn i7 (& self) -> I7R { I7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
pub fn i8 (& self) -> I8R { I8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
pub fn i9 (& self) -> I9R { I9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
pub fn i10 (& self) -> I10R { I10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
pub fn i11 (& self) -> I11R { I11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
pub fn i12 (& self) -> I12R { I12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
pub fn i13 (& self) -> I13R { I13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
pub fn i14 (& self) -> I14R { I14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
pub fn i15 (& self) -> I15R { I15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
pub fn i16 (& self) -> I16R { I16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
pub fn i17 (& self) -> I17R { I17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
pub fn i18 (& self) -> I18R { I18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
pub fn i19 (& self) -> I19R { I19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
pub fn i20 (& self) -> I20R { I20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
pub fn i21 (& self) -> I21R { I21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
pub fn i22 (& self) -> I22R { I22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
pub fn i23 (& self) -> I23R { I23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
pub fn i24 (& self) -> I24R { I24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
pub fn i25 (& self) -> I25R { I25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
pub fn i26 (& self) -> I26R { I26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
pub fn i27 (& self) -> I27R { I27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
pub fn i28 (& self) -> I28R { I28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
pub fn i29 (& self) -> I29R { I29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
pub fn i30 (& self) -> I30R { I30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
pub fn i31 (& self) -> I31R { I31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #0"]
# [inline (always)]
# [must_use]
pub fn i0 (& mut self) -> I0W < IcrRnSpec > { I0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #1"]
# [inline (always)]
# [must_use]
pub fn i1 (& mut self) -> I1W < IcrRnSpec > { I1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #2"]
# [inline (always)]
# [must_use]
pub fn i2 (& mut self) -> I2W < IcrRnSpec > { I2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #3"]
# [inline (always)]
# [must_use]
pub fn i3 (& mut self) -> I3W < IcrRnSpec > { I3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #4"]
# [inline (always)]
# [must_use]
pub fn i4 (& mut self) -> I4W < IcrRnSpec > { I4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #5"]
# [inline (always)]
# [must_use]
pub fn i5 (& mut self) -> I5W < IcrRnSpec > { I5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #6"]
# [inline (always)]
# [must_use]
pub fn i6 (& mut self) -> I6W < IcrRnSpec > { I6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #7"]
# [inline (always)]
# [must_use]
pub fn i7 (& mut self) -> I7W < IcrRnSpec > { I7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #8"]
# [inline (always)]
# [must_use]
pub fn i8 (& mut self) -> I8W < IcrRnSpec > { I8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #9"]
# [inline (always)]
# [must_use]
pub fn i9 (& mut self) -> I9W < IcrRnSpec > { I9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #10"]
# [inline (always)]
# [must_use]
pub fn i10 (& mut self) -> I10W < IcrRnSpec > { I10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #11"]
# [inline (always)]
# [must_use]
pub fn i11 (& mut self) -> I11W < IcrRnSpec > { I11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #12"]
# [inline (always)]
# [must_use]
pub fn i12 (& mut self) -> I12W < IcrRnSpec > { I12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #13"]
# [inline (always)]
# [must_use]
pub fn i13 (& mut self) -> I13W < IcrRnSpec > { I13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #14"]
# [inline (always)]
# [must_use]
pub fn i14 (& mut self) -> I14W < IcrRnSpec > { I14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #15"]
# [inline (always)]
# [must_use]
pub fn i15 (& mut self) -> I15W < IcrRnSpec > { I15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #16"]
# [inline (always)]
# [must_use]
pub fn i16 (& mut self) -> I16W < IcrRnSpec > { I16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #17"]
# [inline (always)]
# [must_use]
pub fn i17 (& mut self) -> I17W < IcrRnSpec > { I17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #18"]
# [inline (always)]
# [must_use]
pub fn i18 (& mut self) -> I18W < IcrRnSpec > { I18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #19"]
# [inline (always)]
# [must_use]
pub fn i19 (& mut self) -> I19W < IcrRnSpec > { I19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #20"]
# [inline (always)]
# [must_use]
pub fn i20 (& mut self) -> I20W < IcrRnSpec > { I20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #21"]
# [inline (always)]
# [must_use]
pub fn i21 (& mut self) -> I21W < IcrRnSpec > { I21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #22"]
# [inline (always)]
# [must_use]
pub fn i22 (& mut self) -> I22W < IcrRnSpec > { I22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #23"]
# [inline (always)]
# [must_use]
pub fn i23 (& mut self) -> I23W < IcrRnSpec > { I23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #24"]
# [inline (always)]
# [must_use]
pub fn i24 (& mut self) -> I24W < IcrRnSpec > { I24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #25"]
# [inline (always)]
# [must_use]
pub fn i25 (& mut self) -> I25W < IcrRnSpec > { I25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #26"]
# [inline (always)]
# [must_use]
pub fn i26 (& mut self) -> I26W < IcrRnSpec > { I26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #27"]
# [inline (always)]
# [must_use]
pub fn i27 (& mut self) -> I27W < IcrRnSpec > { I27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #28"]
# [inline (always)]
# [must_use]
pub fn i28 (& mut self) -> I28W < IcrRnSpec > { I28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #29"]
# [inline (always)]
# [must_use]
pub fn i29 (& mut self) -> I29W < IcrRnSpec > { I29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #30"]
# [inline (always)]
# [must_use]
pub fn i30 (& mut self) -> I30W < IcrRnSpec > { I30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #31"]
# [inline (always)]
# [must_use]
pub fn i31 (& mut self) -> I31W < IcrRnSpec > { I31W :: new (self , 31) } } # [doc = "Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrRnSpec ; impl crate :: RegisterSpec for IcrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icr_rn::R`](R) reader structure"]
impl crate :: Readable for IcrRnSpec { } # [doc = "`write(|w| ..)` method takes [`icr_rn::W`](W) writer structure"]
impl crate :: Writable for IcrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICR_RN to value 0"]
impl crate :: Resettable for IcrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICRH_RN (rw) register accessor: Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icrh_rn`]
module"]
# [doc (alias = "ICRH_RN")]
pub type IcrhRn = crate :: Reg < icrh_rn :: IcrhRnSpec > ; # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."]
pub mod icrh_rn { # [doc = "Register `ICRH_RN` reader"]
pub type R = crate :: R < IcrhRnSpec > ; # [doc = "Register `ICRH_RN` writer"]
pub type W = crate :: W < IcrhRnSpec > ; # [doc = "Field `I32` reader - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32R = crate :: BitReader ; # [doc = "Field `I32` writer - 0:0\\]
Interrupt associated with TCC #32"]
pub type I32W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I33` reader - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33R = crate :: BitReader ; # [doc = "Field `I33` writer - 1:1\\]
Interrupt associated with TCC #33"]
pub type I33W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I34` reader - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34R = crate :: BitReader ; # [doc = "Field `I34` writer - 2:2\\]
Interrupt associated with TCC #34"]
pub type I34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I35` reader - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35R = crate :: BitReader ; # [doc = "Field `I35` writer - 3:3\\]
Interrupt associated with TCC #35"]
pub type I35W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I36` reader - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36R = crate :: BitReader ; # [doc = "Field `I36` writer - 4:4\\]
Interrupt associated with TCC #36"]
pub type I36W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I37` reader - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37R = crate :: BitReader ; # [doc = "Field `I37` writer - 5:5\\]
Interrupt associated with TCC #37"]
pub type I37W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I38` reader - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38R = crate :: BitReader ; # [doc = "Field `I38` writer - 6:6\\]
Interrupt associated with TCC #38"]
pub type I38W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I39` reader - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39R = crate :: BitReader ; # [doc = "Field `I39` writer - 7:7\\]
Interrupt associated with TCC #39"]
pub type I39W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I40` reader - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40R = crate :: BitReader ; # [doc = "Field `I40` writer - 8:8\\]
Interrupt associated with TCC #40"]
pub type I40W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I41` reader - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41R = crate :: BitReader ; # [doc = "Field `I41` writer - 9:9\\]
Interrupt associated with TCC #41"]
pub type I41W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I42` reader - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42R = crate :: BitReader ; # [doc = "Field `I42` writer - 10:10\\]
Interrupt associated with TCC #42"]
pub type I42W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I43` reader - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43R = crate :: BitReader ; # [doc = "Field `I43` writer - 11:11\\]
Interrupt associated with TCC #43"]
pub type I43W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I44` reader - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44R = crate :: BitReader ; # [doc = "Field `I44` writer - 12:12\\]
Interrupt associated with TCC #44"]
pub type I44W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I45` reader - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45R = crate :: BitReader ; # [doc = "Field `I45` writer - 13:13\\]
Interrupt associated with TCC #45"]
pub type I45W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I46` reader - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46R = crate :: BitReader ; # [doc = "Field `I46` writer - 14:14\\]
Interrupt associated with TCC #46"]
pub type I46W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I47` reader - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47R = crate :: BitReader ; # [doc = "Field `I47` writer - 15:15\\]
Interrupt associated with TCC #47"]
pub type I47W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I48` reader - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48R = crate :: BitReader ; # [doc = "Field `I48` writer - 16:16\\]
Interrupt associated with TCC #48"]
pub type I48W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I49` reader - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49R = crate :: BitReader ; # [doc = "Field `I49` writer - 17:17\\]
Interrupt associated with TCC #49"]
pub type I49W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I50` reader - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50R = crate :: BitReader ; # [doc = "Field `I50` writer - 18:18\\]
Interrupt associated with TCC #50"]
pub type I50W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I51` reader - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51R = crate :: BitReader ; # [doc = "Field `I51` writer - 19:19\\]
Interrupt associated with TCC #51"]
pub type I51W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I52` reader - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52R = crate :: BitReader ; # [doc = "Field `I52` writer - 20:20\\]
Interrupt associated with TCC #52"]
pub type I52W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I53` reader - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53R = crate :: BitReader ; # [doc = "Field `I53` writer - 21:21\\]
Interrupt associated with TCC #53"]
pub type I53W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I54` reader - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54R = crate :: BitReader ; # [doc = "Field `I54` writer - 22:22\\]
Interrupt associated with TCC #54"]
pub type I54W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I55` reader - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55R = crate :: BitReader ; # [doc = "Field `I55` writer - 23:23\\]
Interrupt associated with TCC #55"]
pub type I55W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I56` reader - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56R = crate :: BitReader ; # [doc = "Field `I56` writer - 24:24\\]
Interrupt associated with TCC #56"]
pub type I56W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I57` reader - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57R = crate :: BitReader ; # [doc = "Field `I57` writer - 25:25\\]
Interrupt associated with TCC #57"]
pub type I57W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I58` reader - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58R = crate :: BitReader ; # [doc = "Field `I58` writer - 26:26\\]
Interrupt associated with TCC #58"]
pub type I58W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I59` reader - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59R = crate :: BitReader ; # [doc = "Field `I59` writer - 27:27\\]
Interrupt associated with TCC #59"]
pub type I59W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I60` reader - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60R = crate :: BitReader ; # [doc = "Field `I60` writer - 28:28\\]
Interrupt associated with TCC #60"]
pub type I60W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I61` reader - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61R = crate :: BitReader ; # [doc = "Field `I61` writer - 29:29\\]
Interrupt associated with TCC #61"]
pub type I61W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I62` reader - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62R = crate :: BitReader ; # [doc = "Field `I62` writer - 30:30\\]
Interrupt associated with TCC #62"]
pub type I62W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I63` reader - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63R = crate :: BitReader ; # [doc = "Field `I63` writer - 31:31\\]
Interrupt associated with TCC #63"]
pub type I63W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
pub fn i32 (& self) -> I32R { I32R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
pub fn i33 (& self) -> I33R { I33R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
pub fn i34 (& self) -> I34R { I34R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
pub fn i35 (& self) -> I35R { I35R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
pub fn i36 (& self) -> I36R { I36R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
pub fn i37 (& self) -> I37R { I37R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
pub fn i38 (& self) -> I38R { I38R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
pub fn i39 (& self) -> I39R { I39R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
pub fn i40 (& self) -> I40R { I40R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
pub fn i41 (& self) -> I41R { I41R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
pub fn i42 (& self) -> I42R { I42R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
pub fn i43 (& self) -> I43R { I43R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
pub fn i44 (& self) -> I44R { I44R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
pub fn i45 (& self) -> I45R { I45R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
pub fn i46 (& self) -> I46R { I46R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
pub fn i47 (& self) -> I47R { I47R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
pub fn i48 (& self) -> I48R { I48R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
pub fn i49 (& self) -> I49R { I49R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
pub fn i50 (& self) -> I50R { I50R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
pub fn i51 (& self) -> I51R { I51R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
pub fn i52 (& self) -> I52R { I52R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
pub fn i53 (& self) -> I53R { I53R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
pub fn i54 (& self) -> I54R { I54R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
pub fn i55 (& self) -> I55R { I55R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
pub fn i56 (& self) -> I56R { I56R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
pub fn i57 (& self) -> I57R { I57R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
pub fn i58 (& self) -> I58R { I58R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
pub fn i59 (& self) -> I59R { I59R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
pub fn i60 (& self) -> I60R { I60R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
pub fn i61 (& self) -> I61R { I61R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
pub fn i62 (& self) -> I62R { I62R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
pub fn i63 (& self) -> I63R { I63R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt associated with TCC #32"]
# [inline (always)]
# [must_use]
pub fn i32 (& mut self) -> I32W < IcrhRnSpec > { I32W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt associated with TCC #33"]
# [inline (always)]
# [must_use]
pub fn i33 (& mut self) -> I33W < IcrhRnSpec > { I33W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt associated with TCC #34"]
# [inline (always)]
# [must_use]
pub fn i34 (& mut self) -> I34W < IcrhRnSpec > { I34W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt associated with TCC #35"]
# [inline (always)]
# [must_use]
pub fn i35 (& mut self) -> I35W < IcrhRnSpec > { I35W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt associated with TCC #36"]
# [inline (always)]
# [must_use]
pub fn i36 (& mut self) -> I36W < IcrhRnSpec > { I36W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt associated with TCC #37"]
# [inline (always)]
# [must_use]
pub fn i37 (& mut self) -> I37W < IcrhRnSpec > { I37W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt associated with TCC #38"]
# [inline (always)]
# [must_use]
pub fn i38 (& mut self) -> I38W < IcrhRnSpec > { I38W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt associated with TCC #39"]
# [inline (always)]
# [must_use]
pub fn i39 (& mut self) -> I39W < IcrhRnSpec > { I39W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt associated with TCC #40"]
# [inline (always)]
# [must_use]
pub fn i40 (& mut self) -> I40W < IcrhRnSpec > { I40W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt associated with TCC #41"]
# [inline (always)]
# [must_use]
pub fn i41 (& mut self) -> I41W < IcrhRnSpec > { I41W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt associated with TCC #42"]
# [inline (always)]
# [must_use]
pub fn i42 (& mut self) -> I42W < IcrhRnSpec > { I42W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt associated with TCC #43"]
# [inline (always)]
# [must_use]
pub fn i43 (& mut self) -> I43W < IcrhRnSpec > { I43W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt associated with TCC #44"]
# [inline (always)]
# [must_use]
pub fn i44 (& mut self) -> I44W < IcrhRnSpec > { I44W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt associated with TCC #45"]
# [inline (always)]
# [must_use]
pub fn i45 (& mut self) -> I45W < IcrhRnSpec > { I45W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Interrupt associated with TCC #46"]
# [inline (always)]
# [must_use]
pub fn i46 (& mut self) -> I46W < IcrhRnSpec > { I46W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Interrupt associated with TCC #47"]
# [inline (always)]
# [must_use]
pub fn i47 (& mut self) -> I47W < IcrhRnSpec > { I47W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Interrupt associated with TCC #48"]
# [inline (always)]
# [must_use]
pub fn i48 (& mut self) -> I48W < IcrhRnSpec > { I48W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Interrupt associated with TCC #49"]
# [inline (always)]
# [must_use]
pub fn i49 (& mut self) -> I49W < IcrhRnSpec > { I49W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Interrupt associated with TCC #50"]
# [inline (always)]
# [must_use]
pub fn i50 (& mut self) -> I50W < IcrhRnSpec > { I50W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Interrupt associated with TCC #51"]
# [inline (always)]
# [must_use]
pub fn i51 (& mut self) -> I51W < IcrhRnSpec > { I51W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Interrupt associated with TCC #52"]
# [inline (always)]
# [must_use]
pub fn i52 (& mut self) -> I52W < IcrhRnSpec > { I52W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Interrupt associated with TCC #53"]
# [inline (always)]
# [must_use]
pub fn i53 (& mut self) -> I53W < IcrhRnSpec > { I53W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Interrupt associated with TCC #54"]
# [inline (always)]
# [must_use]
pub fn i54 (& mut self) -> I54W < IcrhRnSpec > { I54W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Interrupt associated with TCC #55"]
# [inline (always)]
# [must_use]
pub fn i55 (& mut self) -> I55W < IcrhRnSpec > { I55W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Interrupt associated with TCC #56"]
# [inline (always)]
# [must_use]
pub fn i56 (& mut self) -> I56W < IcrhRnSpec > { I56W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Interrupt associated with TCC #57"]
# [inline (always)]
# [must_use]
pub fn i57 (& mut self) -> I57W < IcrhRnSpec > { I57W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Interrupt associated with TCC #58"]
# [inline (always)]
# [must_use]
pub fn i58 (& mut self) -> I58W < IcrhRnSpec > { I58W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Interrupt associated with TCC #59"]
# [inline (always)]
# [must_use]
pub fn i59 (& mut self) -> I59W < IcrhRnSpec > { I59W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Interrupt associated with TCC #60"]
# [inline (always)]
# [must_use]
pub fn i60 (& mut self) -> I60W < IcrhRnSpec > { I60W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Interrupt associated with TCC #61"]
# [inline (always)]
# [must_use]
pub fn i61 (& mut self) -> I61W < IcrhRnSpec > { I61W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Interrupt associated with TCC #62"]
# [inline (always)]
# [must_use]
pub fn i62 (& mut self) -> I62W < IcrhRnSpec > { I62W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Interrupt associated with TCC #63"]
# [inline (always)]
# [must_use]
pub fn i63 (& mut self) -> I63W < IcrhRnSpec > { I63W :: new (self , 31) } } # [doc = "Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC.\n\nYou can [`read`](crate::Reg::read) this register and get [`icrh_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icrh_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrhRnSpec ; impl crate :: RegisterSpec for IcrhRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icrh_rn::R`](R) reader structure"]
impl crate :: Readable for IcrhRnSpec { } # [doc = "`write(|w| ..)` method takes [`icrh_rn::W`](W) writer structure"]
impl crate :: Writable for IcrhRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICRH_RN to value 0"]
impl crate :: Resettable for IcrhRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IEVAL_RN (rw) register accessor: Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ieval_rn`]
module"]
# [doc (alias = "IEVAL_RN")]
pub type IevalRn = crate :: Reg < ieval_rn :: IevalRnSpec > ; # [doc = "Interrupt Eval Register"]
pub mod ieval_rn { # [doc = "Register `IEVAL_RN` reader"]
pub type R = crate :: R < IevalRnSpec > ; # [doc = "Register `IEVAL_RN` writer"]
pub type W = crate :: W < IevalRnSpec > ; # [doc = "Field `EVAL` reader - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalR = crate :: BitReader ; # [doc = "Field `EVAL` writer - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
pub type EvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET` reader - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetR = crate :: BitReader ; # [doc = "Field `SET` writer - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES76` reader - 31:2\\]
RESERVE FIELD"]
pub type Res76R = crate :: FieldReader < u32 > ; # [doc = "Field `RES76` writer - 31:2\\]
RESERVE FIELD"]
pub type Res76W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
pub fn eval (& self) -> EvalR { EvalR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res76 (& self) -> Res76R { Res76R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.."]
# [inline (always)]
# [must_use]
pub fn eval (& mut self) -> EvalW < IevalRnSpec > { EvalW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < IevalRnSpec > { SetW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res76 (& mut self) -> Res76W < IevalRnSpec > { Res76W :: new (self , 2) } } # [doc = "Interrupt Eval Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ieval_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ieval_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IevalRnSpec ; impl crate :: RegisterSpec for IevalRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ieval_rn::R`](R) reader structure"]
impl crate :: Readable for IevalRnSpec { } # [doc = "`write(|w| ..)` method takes [`ieval_rn::W`](W) writer structure"]
impl crate :: Writable for IevalRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IEVAL_RN to value 0"]
impl crate :: Resettable for IevalRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QER_RN (rw) register accessor: QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qer_rn`]
module"]
# [doc (alias = "QER_RN")]
pub type QerRn = crate :: Reg < qer_rn :: QerRnSpec > ; # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set."]
pub mod qer_rn { # [doc = "Register `QER_RN` reader"]
pub type R = crate :: R < QerRnSpec > ; # [doc = "Register `QER_RN` writer"]
pub type W = crate :: W < QerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES77` reader - 31:8\\]
RESERVE FIELD"]
pub type Res77R = crate :: FieldReader < u32 > ; # [doc = "Field `RES77` writer - 31:8\\]
RESERVE FIELD"]
pub type Res77W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res77 (& self) -> Res77R { Res77R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QerRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res77 (& mut self) -> Res77W < QerRnSpec > { Res77W :: new (self , 8) } } # [doc = "QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.\n\nYou can [`read`](crate::Reg::read) this register and get [`qer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QerRnSpec ; impl crate :: RegisterSpec for QerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qer_rn::R`](R) reader structure"]
impl crate :: Readable for QerRnSpec { } # [doc = "`write(|w| ..)` method takes [`qer_rn::W`](W) writer structure"]
impl crate :: Writable for QerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QER_RN to value 0"]
impl crate :: Resettable for QerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEER_RN (rw) register accessor: QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeer_rn`]
module"]
# [doc (alias = "QEER_RN")]
pub type QeerRn = crate :: Reg < qeer_rn :: QeerRnSpec > ; # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En."]
pub mod qeer_rn { # [doc = "Register `QEER_RN` reader"]
pub type R = crate :: R < QeerRnSpec > ; # [doc = "Register `QEER_RN` writer"]
pub type W = crate :: W < QeerRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES78` reader - 31:8\\]
RESERVE FIELD"]
pub type Res78R = crate :: FieldReader < u32 > ; # [doc = "Field `RES78` writer - 31:8\\]
RESERVE FIELD"]
pub type Res78W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res78 (& self) -> Res78R { Res78R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeerRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeerRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeerRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeerRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeerRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeerRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeerRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeerRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res78 (& mut self) -> Res78W < QeerRnSpec > { Res78W :: new (self , 8) } } # [doc = "QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En.\n\nYou can [`read`](crate::Reg::read) this register and get [`qeer_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeer_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeerRnSpec ; impl crate :: RegisterSpec for QeerRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeer_rn::R`](R) reader structure"]
impl crate :: Readable for QeerRnSpec { } # [doc = "`write(|w| ..)` method takes [`qeer_rn::W`](W) writer structure"]
impl crate :: Writable for QeerRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEER_RN to value 0"]
impl crate :: Resettable for QeerRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEECR_RN (rw) register accessor: QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeecr_rn`]
module"]
# [doc (alias = "QEECR_RN")]
pub type QeecrRn = crate :: Reg < qeecr_rn :: QeecrRnSpec > ; # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."]
pub mod qeecr_rn { # [doc = "Register `QEECR_RN` reader"]
pub type R = crate :: R < QeecrRnSpec > ; # [doc = "Register `QEECR_RN` writer"]
pub type W = crate :: W < QeecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES79` reader - 31:8\\]
RESERVE FIELD"]
pub type Res79R = crate :: FieldReader < u32 > ; # [doc = "Field `RES79` writer - 31:8\\]
RESERVE FIELD"]
pub type Res79W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res79 (& self) -> Res79R { Res79R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res79 (& mut self) -> Res79W < QeecrRnSpec > { Res79W :: new (self , 8) } } # [doc = "QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeecrRnSpec ; impl crate :: RegisterSpec for QeecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeecr_rn::R`](R) reader structure"]
impl crate :: Readable for QeecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`qeecr_rn::W`](W) writer structure"]
impl crate :: Writable for QeecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEECR_RN to value 0"]
impl crate :: Resettable for QeecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QEESR_RN (rw) register accessor: QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qeesr_rn`]
module"]
# [doc (alias = "QEESR_RN")]
pub type QeesrRn = crate :: Reg < qeesr_rn :: QeesrRnSpec > ; # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."]
pub mod qeesr_rn { # [doc = "Register `QEESR_RN` reader"]
pub type R = crate :: R < QeesrRnSpec > ; # [doc = "Register `QEESR_RN` writer"]
pub type W = crate :: W < QeesrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES80` reader - 31:8\\]
RESERVE FIELD"]
pub type Res80R = crate :: FieldReader < u32 > ; # [doc = "Field `RES80` writer - 31:8\\]
RESERVE FIELD"]
pub type Res80W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res80 (& self) -> Res80R { Res80R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QeesrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QeesrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QeesrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QeesrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QeesrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QeesrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QeesrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QeesrRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res80 (& mut self) -> Res80W < QeesrRnSpec > { Res80W :: new (self , 8) } } # [doc = "QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qeesr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qeesr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QeesrRnSpec ; impl crate :: RegisterSpec for QeesrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qeesr_rn::R`](R) reader structure"]
impl crate :: Readable for QeesrRnSpec { } # [doc = "`write(|w| ..)` method takes [`qeesr_rn::W`](W) writer structure"]
impl crate :: Writable for QeesrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QEESR_RN to value 0"]
impl crate :: Resettable for QeesrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSER_RN (rw) register accessor: QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qser_rn`]
module"]
# [doc (alias = "QSER_RN")]
pub type QserRn = crate :: Reg < qser_rn :: QserRnSpec > ; # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events."]
pub mod qser_rn { # [doc = "Register `QSER_RN` reader"]
pub type R = crate :: R < QserRnSpec > ; # [doc = "Register `QSER_RN` writer"]
pub type W = crate :: W < QserRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES81` reader - 31:8\\]
RESERVE FIELD"]
pub type Res81R = crate :: FieldReader < u32 > ; # [doc = "Field `RES81` writer - 31:8\\]
RESERVE FIELD"]
pub type Res81W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res81 (& self) -> Res81R { Res81R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QserRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QserRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QserRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QserRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QserRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QserRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QserRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QserRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res81 (& mut self) -> Res81W < QserRnSpec > { Res81W :: new (self , 8) } } # [doc = "QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.\n\nYou can [`read`](crate::Reg::read) this register and get [`qser_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qser_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QserRnSpec ; impl crate :: RegisterSpec for QserRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qser_rn::R`](R) reader structure"]
impl crate :: Readable for QserRnSpec { } # [doc = "`write(|w| ..)` method takes [`qser_rn::W`](W) writer structure"]
impl crate :: Writable for QserRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSER_RN to value 0"]
impl crate :: Resettable for QserRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSECR_RN (rw) register accessor: QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr_rn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr_rn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qsecr_rn`]
module"]
# [doc (alias = "QSECR_RN")]
pub type QsecrRn = crate :: Reg < qsecr_rn :: QsecrRnSpec > ; # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.."]
pub mod qsecr_rn { # [doc = "Register `QSECR_RN` reader"]
pub type R = crate :: R < QsecrRnSpec > ; # [doc = "Register `QSECR_RN` writer"]
pub type W = crate :: W < QsecrRnSpec > ; # [doc = "Field `E0` reader - 0:0\\]
Event #0"]
pub type E0R = crate :: BitReader ; # [doc = "Field `E0` writer - 0:0\\]
Event #0"]
pub type E0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E1` reader - 1:1\\]
Event #1"]
pub type E1R = crate :: BitReader ; # [doc = "Field `E1` writer - 1:1\\]
Event #1"]
pub type E1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E2` reader - 2:2\\]
Event #2"]
pub type E2R = crate :: BitReader ; # [doc = "Field `E2` writer - 2:2\\]
Event #2"]
pub type E2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E3` reader - 3:3\\]
Event #3"]
pub type E3R = crate :: BitReader ; # [doc = "Field `E3` writer - 3:3\\]
Event #3"]
pub type E3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E4` reader - 4:4\\]
Event #4"]
pub type E4R = crate :: BitReader ; # [doc = "Field `E4` writer - 4:4\\]
Event #4"]
pub type E4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E5` reader - 5:5\\]
Event #5"]
pub type E5R = crate :: BitReader ; # [doc = "Field `E5` writer - 5:5\\]
Event #5"]
pub type E5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E6` reader - 6:6\\]
Event #6"]
pub type E6R = crate :: BitReader ; # [doc = "Field `E6` writer - 6:6\\]
Event #6"]
pub type E6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `E7` reader - 7:7\\]
Event #7"]
pub type E7R = crate :: BitReader ; # [doc = "Field `E7` writer - 7:7\\]
Event #7"]
pub type E7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES82` reader - 31:8\\]
RESERVE FIELD"]
pub type Res82R = crate :: FieldReader < u32 > ; # [doc = "Field `RES82` writer - 31:8\\]
RESERVE FIELD"]
pub type Res82W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
pub fn e0 (& self) -> E0R { E0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
pub fn e1 (& self) -> E1R { E1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
pub fn e2 (& self) -> E2R { E2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
pub fn e3 (& self) -> E3R { E3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
pub fn e4 (& self) -> E4R { E4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
pub fn e5 (& self) -> E5R { E5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
pub fn e6 (& self) -> E6R { E6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
pub fn e7 (& self) -> E7R { E7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res82 (& self) -> Res82R { Res82R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Event #0"]
# [inline (always)]
# [must_use]
pub fn e0 (& mut self) -> E0W < QsecrRnSpec > { E0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Event #1"]
# [inline (always)]
# [must_use]
pub fn e1 (& mut self) -> E1W < QsecrRnSpec > { E1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Event #2"]
# [inline (always)]
# [must_use]
pub fn e2 (& mut self) -> E2W < QsecrRnSpec > { E2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Event #3"]
# [inline (always)]
# [must_use]
pub fn e3 (& mut self) -> E3W < QsecrRnSpec > { E3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Event #4"]
# [inline (always)]
# [must_use]
pub fn e4 (& mut self) -> E4W < QsecrRnSpec > { E4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Event #5"]
# [inline (always)]
# [must_use]
pub fn e5 (& mut self) -> E5W < QsecrRnSpec > { E5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Event #6"]
# [inline (always)]
# [must_use]
pub fn e6 (& mut self) -> E6W < QsecrRnSpec > { E6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Event #7"]
# [inline (always)]
# [must_use]
pub fn e7 (& mut self) -> E7W < QsecrRnSpec > { E7W :: new (self , 7) } # [doc = "Bits 8:31 - 31:8\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res82 (& mut self) -> Res82W < QsecrRnSpec > { Res82W :: new (self , 8) } } # [doc = "QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect..\n\nYou can [`read`](crate::Reg::read) this register and get [`qsecr_rn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qsecr_rn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QsecrRnSpec ; impl crate :: RegisterSpec for QsecrRnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qsecr_rn::R`](R) reader structure"]
impl crate :: Readable for QsecrRnSpec { } # [doc = "`write(|w| ..)` method takes [`qsecr_rn::W`](W) writer structure"]
impl crate :: Writable for QsecrRnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSECR_RN to value 0"]
impl crate :: Resettable for QsecrRnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "OPT (rw) register accessor: Options Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`opt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@opt`]
module"]
# [doc (alias = "OPT")]
pub type Opt = crate :: Reg < opt :: OptSpec > ; # [doc = "Options Parameter"]
pub mod opt { # [doc = "Register `OPT` reader"]
pub type R = crate :: R < OptSpec > ; # [doc = "Register `OPT` writer"]
pub type W = crate :: W < OptSpec > ; # [doc = "Field `SAM` reader - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SamR = crate :: BitReader ; # [doc = "Field `SAM` writer - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
pub type SamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DAM` reader - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DamR = crate :: BitReader ; # [doc = "Field `DAM` writer - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
pub type DamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SYNCDIM` reader - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
pub type SyncdimR = crate :: BitReader ; # [doc = "Field `SYNCDIM` writer - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
pub type SyncdimW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STATIC` reader - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
pub type StaticR = crate :: BitReader ; # [doc = "Field `STATIC` writer - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
pub type StaticW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES85` reader - 7:4\\]
RESERVE FIELD"]
pub type Res85R = crate :: FieldReader ; # [doc = "Field `RES85` writer - 7:4\\]
RESERVE FIELD"]
pub type Res85W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `FWID` reader - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
pub type FwidR = crate :: FieldReader ; # [doc = "Field `FWID` writer - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
pub type FwidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TCCMODE` reader - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
pub type TccmodeR = crate :: BitReader ; # [doc = "Field `TCCMODE` writer - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
pub type TccmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCC` reader - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
pub type TccR = crate :: FieldReader ; # [doc = "Field `TCC` writer - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
pub type TccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RES84` reader - 18:18\\]
RESERVE FIELD"]
pub type Res84R = crate :: BitReader ; # [doc = "Field `RES84` writer - 18:18\\]
RESERVE FIELD"]
pub type Res84W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WIMODE` reader - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
pub type WimodeR = crate :: BitReader ; # [doc = "Field `WIMODE` writer - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
pub type WimodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCINTEN` reader - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type TcintenR = crate :: BitReader ; # [doc = "Field `TCINTEN` writer - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type TcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ITCINTEN` reader - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type ItcintenR = crate :: BitReader ; # [doc = "Field `ITCINTEN` writer - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
pub type ItcintenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCCHEN` reader - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
pub type TcchenR = crate :: BitReader ; # [doc = "Field `TCCHEN` writer - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
pub type TcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ITCCHEN` reader - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
pub type ItcchenR = crate :: BitReader ; # [doc = "Field `ITCCHEN` writer - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
pub type ItcchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PRIVID` reader - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
pub type PrividR = crate :: FieldReader ; # [doc = "Field `PRIVID` writer - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
pub type PrividW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RES83` reader - 30:28\\]
RESERVE FIELD"]
pub type Res83R = crate :: FieldReader ; # [doc = "Field `RES83` writer - 30:28\\]
RESERVE FIELD"]
pub type Res83W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PRIV` reader - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
pub type PrivR = crate :: BitReader ; # [doc = "Field `PRIV` writer - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
pub type PrivW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn sam (& self) -> SamR { SamR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
pub fn dam (& self) -> DamR { DamR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
# [inline (always)]
pub fn syncdim (& self) -> SyncdimR { SyncdimR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
# [inline (always)]
pub fn static_ (& self) -> StaticR { StaticR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res85 (& self) -> Res85R { Res85R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
# [inline (always)]
pub fn fwid (& self) -> FwidR { FwidR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 11 - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
# [inline (always)]
pub fn tccmode (& self) -> TccmodeR { TccmodeR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
# [inline (always)]
pub fn tcc (& self) -> TccR { TccR :: new (((self . bits >> 12) & 0x3f) as u8) } # [doc = "Bit 18 - 18:18\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res84 (& self) -> Res84R { Res84R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
# [inline (always)]
pub fn wimode (& self) -> WimodeR { WimodeR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
pub fn tcinten (& self) -> TcintenR { TcintenR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
pub fn itcinten (& self) -> ItcintenR { ItcintenR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
# [inline (always)]
pub fn tcchen (& self) -> TcchenR { TcchenR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
# [inline (always)]
pub fn itcchen (& self) -> ItcchenR { ItcchenR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bits 24:27 - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
# [inline (always)]
pub fn privid (& self) -> PrividR { PrividR :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:30 - 30:28\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res83 (& self) -> Res83R { Res83R :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
# [inline (always)]
pub fn priv_ (& self) -> PrivR { PrivR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn sam (& mut self) -> SamW < OptSpec > { SamW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width."]
# [inline (always)]
# [must_use]
pub fn dam (& mut self) -> DamW < OptSpec > { DamW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements"]
# [inline (always)]
# [must_use]
pub fn syncdim (& mut self) -> SyncdimW < OptSpec > { SyncdimW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed."]
# [inline (always)]
# [must_use]
pub fn static_ (& mut self) -> StaticW < OptSpec > { StaticW :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res85 (& mut self) -> Res85W < OptSpec > { Res85W :: new (self , 4) } # [doc = "Bits 8:10 - 10:8\\]
FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC."]
# [inline (always)]
# [must_use]
pub fn fwid (& mut self) -> FwidW < OptSpec > { FwidW :: new (self , 8) } # [doc = "Bit 11 - 11:11\\]
Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally ."]
# [inline (always)]
# [must_use]
pub fn tccmode (& mut self) -> TccmodeW < OptSpec > { TccmodeW :: new (self , 11) } # [doc = "Bits 12:17 - 17:12\\]
Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER\\[TCC\\]) for chaining or in IER (bit IER\\[TCC\\]) for interrupts."]
# [inline (always)]
# [must_use]
pub fn tcc (& mut self) -> TccW < OptSpec > { TccW :: new (self , 12) } # [doc = "Bit 18 - 18:18\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res84 (& mut self) -> Res84W < OptSpec > { Res84W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission)"]
# [inline (always)]
# [must_use]
pub fn wimode (& mut self) -> WimodeW < OptSpec > { WimodeW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
# [must_use]
pub fn tcinten (& mut self) -> TcintenW < OptSpec > { TcintenW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER\\[TCC\\]
bit must be set to 1 to generate interrupt)"]
# [inline (always)]
# [must_use]
pub fn itcinten (& mut self) -> ItcintenW < OptSpec > { ItcintenW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn tcchen (& mut self) -> TcchenW < OptSpec > { TcchenW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled."]
# [inline (always)]
# [must_use]
pub fn itcchen (& mut self) -> ItcchenW < OptSpec > { ItcchenW :: new (self , 23) } # [doc = "Bits 24:27 - 27:24\\]
Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus."]
# [inline (always)]
# [must_use]
pub fn privid (& mut self) -> PrividW < OptSpec > { PrividW :: new (self , 24) } # [doc = "Bits 28:30 - 30:28\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res83 (& mut self) -> Res83W < OptSpec > { Res83W :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege"]
# [inline (always)]
# [must_use]
pub fn priv_ (& mut self) -> PrivW < OptSpec > { PrivW :: new (self , 31) } } # [doc = "Options Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`opt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OptSpec ; impl crate :: RegisterSpec for OptSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`opt::R`](R) reader structure"]
impl crate :: Readable for OptSpec { } # [doc = "`write(|w| ..)` method takes [`opt::W`](W) writer structure"]
impl crate :: Writable for OptSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OPT to value 0"]
impl crate :: Resettable for OptSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SRC (rw) register accessor: Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@src`]
module"]
# [doc (alias = "SRC")]
pub type Src = crate :: Reg < src :: SrcSpec > ; # [doc = "Source Address"]
pub mod src { # [doc = "Register `SRC` reader"]
pub type R = crate :: R < SrcSpec > ; # [doc = "Register `SRC` writer"]
pub type W = crate :: W < SrcSpec > ; # [doc = "Field `SRC` reader - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type SrcR = crate :: FieldReader < u32 > ; # [doc = "Field `SRC` writer - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type SrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
pub fn src (& self) -> SrcR { SrcR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
# [must_use]
pub fn src (& mut self) -> SrcW < SrcSpec > { SrcW :: new (self , 0) } } # [doc = "Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrcSpec ; impl crate :: RegisterSpec for SrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`src::R`](R) reader structure"]
impl crate :: Readable for SrcSpec { } # [doc = "`write(|w| ..)` method takes [`src::W`](W) writer structure"]
impl crate :: Writable for SrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SRC to value 0"]
impl crate :: Resettable for SrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ABCNT (rw) register accessor: A and B byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`abcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abcnt`]
module"]
# [doc (alias = "ABCNT")]
pub type Abcnt = crate :: Reg < abcnt :: AbcntSpec > ; # [doc = "A and B byte count"]
pub mod abcnt { # [doc = "Register `ABCNT` reader"]
pub type R = crate :: R < AbcntSpec > ; # [doc = "Register `ABCNT` writer"]
pub type W = crate :: W < AbcntSpec > ; # [doc = "Field `ACNT` reader - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
pub type AcntR = crate :: FieldReader < u16 > ; # [doc = "Field `ACNT` writer - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
pub type AcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BCNT` reader - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
pub type BcntR = crate :: FieldReader < u16 > ; # [doc = "Field `BCNT` writer - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
pub type BcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
# [inline (always)]
pub fn acnt (& self) -> AcntR { AcntR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
# [inline (always)]
pub fn bcnt (& self) -> BcntR { BcntR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT."]
# [inline (always)]
# [must_use]
pub fn acnt (& mut self) -> AcntW < AbcntSpec > { AcntW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ..."]
# [inline (always)]
# [must_use]
pub fn bcnt (& mut self) -> BcntW < AbcntSpec > { BcntW :: new (self , 16) } } # [doc = "A and B byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`abcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AbcntSpec ; impl crate :: RegisterSpec for AbcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`abcnt::R`](R) reader structure"]
impl crate :: Readable for AbcntSpec { } # [doc = "`write(|w| ..)` method takes [`abcnt::W`](W) writer structure"]
impl crate :: Writable for AbcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ABCNT to value 0"]
impl crate :: Resettable for AbcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DST (rw) register accessor: Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dst`]
module"]
# [doc (alias = "DST")]
pub type Dst = crate :: Reg < dst :: DstSpec > ; # [doc = "Destination Address"]
pub mod dst { # [doc = "Register `DST` reader"]
pub type R = crate :: R < DstSpec > ; # [doc = "Register `DST` writer"]
pub type W = crate :: W < DstSpec > ; # [doc = "Field `DST` reader - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type DstR = crate :: FieldReader < u32 > ; # [doc = "Field `DST` writer - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
pub type DstW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
pub fn dst (& self) -> DstR { DstR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true."]
# [inline (always)]
# [must_use]
pub fn dst (& mut self) -> DstW < DstSpec > { DstW :: new (self , 0) } } # [doc = "Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DstSpec ; impl crate :: RegisterSpec for DstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dst::R`](R) reader structure"]
impl crate :: Readable for DstSpec { } # [doc = "`write(|w| ..)` method takes [`dst::W`](W) writer structure"]
impl crate :: Writable for DstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DST to value 0"]
impl crate :: Resettable for DstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BIDX (rw) register accessor: Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`bidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bidx`]
module"]
# [doc (alias = "BIDX")]
pub type Bidx = crate :: Reg < bidx :: BidxSpec > ; # [doc = "Register description is not available"]
pub mod bidx { # [doc = "Register `BIDX` reader"]
pub type R = crate :: R < BidxSpec > ; # [doc = "Register `BIDX` writer"]
pub type W = crate :: W < BidxSpec > ; # [doc = "Field `SBIDX` reader - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
pub type SbidxR = crate :: FieldReader < u16 > ; # [doc = "Field `SBIDX` writer - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
pub type SbidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DBIDX` reader - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
pub type DbidxR = crate :: FieldReader < u16 > ; # [doc = "Field `DBIDX` writer - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
pub type DbidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
# [inline (always)]
pub fn sbidx (& self) -> SbidxR { SbidxR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
# [inline (always)]
pub fn dbidx (& self) -> DbidxR { DbidxR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers."]
# [inline (always)]
# [must_use]
pub fn sbidx (& mut self) -> SbidxW < BidxSpec > { SbidxW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers."]
# [inline (always)]
# [must_use]
pub fn dbidx (& mut self) -> DbidxW < BidxSpec > { DbidxW :: new (self , 16) } } # [doc = "Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`bidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BidxSpec ; impl crate :: RegisterSpec for BidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`bidx::R`](R) reader structure"]
impl crate :: Readable for BidxSpec { } # [doc = "`write(|w| ..)` method takes [`bidx::W`](W) writer structure"]
impl crate :: Writable for BidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BIDX to value 0"]
impl crate :: Resettable for BidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LNK (rw) register accessor: Link and Reload parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`lnk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lnk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lnk`]
module"]
# [doc (alias = "LNK")]
pub type Lnk = crate :: Reg < lnk :: LnkSpec > ; # [doc = "Link and Reload parameters"]
pub mod lnk { # [doc = "Register `LNK` reader"]
pub type R = crate :: R < LnkSpec > ; # [doc = "Register `LNK` writer"]
pub type W = crate :: W < LnkSpec > ; # [doc = "Field `LINK` reader - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
pub type LinkR = crate :: FieldReader < u16 > ; # [doc = "Field `LINK` writer - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
pub type LinkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `BCNTRLD` reader - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
pub type BcntrldR = crate :: FieldReader < u16 > ; # [doc = "Field `BCNTRLD` writer - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
pub type BcntrldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
# [inline (always)]
pub fn link (& self) -> LinkR { LinkR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
# [inline (always)]
pub fn bcntrld (& self) -> BcntrldR { BcntrldR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field."]
# [inline (always)]
# [must_use]
pub fn link (& mut self) -> LinkW < LnkSpec > { LinkW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field."]
# [inline (always)]
# [must_use]
pub fn bcntrld (& mut self) -> BcntrldW < LnkSpec > { BcntrldW :: new (self , 16) } } # [doc = "Link and Reload parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`lnk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lnk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LnkSpec ; impl crate :: RegisterSpec for LnkSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`lnk::R`](R) reader structure"]
impl crate :: Readable for LnkSpec { } # [doc = "`write(|w| ..)` method takes [`lnk::W`](W) writer structure"]
impl crate :: Writable for LnkSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LNK to value 0"]
impl crate :: Resettable for LnkSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CIDX (rw) register accessor: Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`cidx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cidx`]
module"]
# [doc (alias = "CIDX")]
pub type Cidx = crate :: Reg < cidx :: CidxSpec > ; # [doc = "Register description is not available"]
pub mod cidx { # [doc = "Register `CIDX` reader"]
pub type R = crate :: R < CidxSpec > ; # [doc = "Register `CIDX` writer"]
pub type W = crate :: W < CidxSpec > ; # [doc = "Field `SCIDX` reader - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
pub type ScidxR = crate :: FieldReader < u16 > ; # [doc = "Field `SCIDX` writer - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
pub type ScidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DCIDX` reader - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
pub type DcidxR = crate :: FieldReader < u16 > ; # [doc = "Field `DCIDX` writer - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
pub type DcidxW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
# [inline (always)]
pub fn scidx (& self) -> ScidxR { ScidxR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
# [inline (always)]
pub fn dcidx (& self) -> DcidxR { DcidxR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame."]
# [inline (always)]
# [must_use]
pub fn scidx (& mut self) -> ScidxW < CidxSpec > { ScidxW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame."]
# [inline (always)]
# [must_use]
pub fn dcidx (& mut self) -> DcidxW < CidxSpec > { DcidxW :: new (self , 16) } } # [doc = "Register description is not available\n\nYou can [`read`](crate::Reg::read) this register and get [`cidx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CidxSpec ; impl crate :: RegisterSpec for CidxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cidx::R`](R) reader structure"]
impl crate :: Readable for CidxSpec { } # [doc = "`write(|w| ..)` method takes [`cidx::W`](W) writer structure"]
impl crate :: Writable for CidxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CIDX to value 0"]
impl crate :: Resettable for CidxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCNT (rw) register accessor: C byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`ccnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccnt`]
module"]
# [doc (alias = "CCNT")]
pub type Ccnt = crate :: Reg < ccnt :: CcntSpec > ; # [doc = "C byte count"]
pub mod ccnt { # [doc = "Register `CCNT` reader"]
pub type R = crate :: R < CcntSpec > ; # [doc = "Register `CCNT` writer"]
pub type W = crate :: W < CcntSpec > ; # [doc = "Field `CCNT` reader - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
pub type CcntR = crate :: FieldReader < u16 > ; # [doc = "Field `CCNT` writer - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
pub type CcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `RES86` reader - 31:16\\]
RESERVE FIELD"]
pub type Res86R = crate :: FieldReader < u16 > ; # [doc = "Field `RES86` writer - 31:16\\]
RESERVE FIELD"]
pub type Res86W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
# [inline (always)]
pub fn ccnt (& self) -> CcntR { CcntR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res86 (& self) -> Res86R { Res86R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation."]
# [inline (always)]
# [must_use]
pub fn ccnt (& mut self) -> CcntW < CcntSpec > { CcntW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res86 (& mut self) -> Res86W < CcntSpec > { Res86W :: new (self , 16) } } # [doc = "C byte count\n\nYou can [`read`](crate::Reg::read) this register and get [`ccnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcntSpec ; impl crate :: RegisterSpec for CcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ccnt::R`](R) reader structure"]
impl crate :: Readable for CcntSpec { } # [doc = "`write(|w| ..)` method takes [`ccnt::W`](W) writer structure"]
impl crate :: Writable for CcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCNT to value 0"]
impl crate :: Resettable for CcntSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_RCM"]
pub struct AppRcm { _marker : PhantomData < * const () > } unsafe impl Send for AppRcm { } impl AppRcm { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_rcm :: RegisterBlock = 0x5604_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_rcm :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppRcm { type Target = app_rcm :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppRcm { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppRcm") . finish () } } # [doc = "APP_RCM"]
pub mod app_rcm { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , app_cpu_clkctl : AppCpuClkctl , app_cpu_clkstat : AppCpuClkstat , app_can_clkctl : AppCanClkctl , app_can_clkstat : AppCanClkstat , app_spi_clkctl : AppSpiClkctl , app_spi_clkstat : AppSpiClkstat , app_spi_busif_clkctl : AppSpiBusifClkctl , app_spi_busif_clkstat : AppSpiBusifClkstat , app_qspi_clkctl : AppQspiClkctl , app_qspi_clkstat : AppQspiClkstat , topss_clkctl : TopssClkctl , topss_clkstat : TopssClkstat , app_rti_clkctl : AppRtiClkctl , app_rti_clkstat : AppRtiClkstat , app_wd_clkctl : AppWdClkctl , app_wd_clkstat : AppWdClkstat , app_uart_0_clkctl : AppUart0Clkctl , app_uart_0_clkstat : AppUart0Clkstat , app_uart_1_clkctl : AppUart1Clkctl , app_uart_1_clkstat : AppUart1Clkstat , app_i2c_clkctl : AppI2cClkctl , app_i2c_clkstat : AppI2cClkstat , app_lin_clkctl : AppLinClkctl , app_lin_clkstat : AppLinClkstat , reserved0 : Reserved0 , reserved1 : Reserved1 , reserved2 : Reserved2 , reserved3 : Reserved3 , ipcfgclkgate0 : Ipcfgclkgate0 , ipcfgclkgate1 : Ipcfgclkgate1 , ipcfgclkgate2 : Ipcfgclkgate2 , blockreset0 : Blockreset0 , blockreset1 : Blockreset1 , blockreset2 : Blockreset2 , platform_signature : PlatformSignature , powermode : Powermode , rst_wficheck : RstWficheck , rst_assertdly : RstAssertdly , rst2assertdly : Rst2assertdly , rst_fsm_trig : RstFsmTrig , rst_cause : RstCause , rst_cause_clr : RstCauseClr , xtalclk_clk_gate : XtalclkClkGate , xtalclkx2_clk_gate : Xtalclkx2ClkGate , aplldiv2_clk_gate : Aplldiv2ClkGate , dft_appss_lstc_clk_gate : DftAppssLstcClkGate , dft_appss_lstc_vbusp_clk_gate : DftAppssLstcVbuspClkGate , app_rom_clock_gate : AppRomClockGate , app_ram1_clock_gate : AppRam1ClockGate , app_ram2_clock_gate : AppRam2ClockGate , app_ram3_clock_gate : AppRam3ClockGate , cfg_xbara_dynamic_cg : CfgXbaraDynamicCg , cfg_tptc1_dynamic_cg : CfgTptc1DynamicCg , cfg_tptc2_dynamic_cg : CfgTptc2DynamicCg , cfg_xbara_set_dynamic_cg : CfgXbaraSetDynamicCg , cfg_tptc1_set_dynamic_cg : CfgTptc1SetDynamicCg , cfg_tptc2_set_dynamic_cg : CfgTptc2SetDynamicCg , cm4_force_hclk_gate : Cm4ForceHclkGate , lin_sci_div : LinSciDiv , app_lstc_en : AppLstcEn , _reserved61 : [u8 ; 0x0f14]
, lock0_kick0 : Lock0Kick0 , lock0_kick1 : Lock0Kick1 , intr_raw_status : IntrRawStatus , intr_enabled_status_clear : IntrEnabledStatusClear , intr_enable : IntrEnable , intr_enable_clear : IntrEnableClear , eoi : Eoi , fault_address : FaultAddress , fault_type_status : FaultTypeStatus , fault_attr_status : FaultAttrStatus , fault_clear : FaultClear , } impl RegisterBlock { # [doc = "0x00 - PID register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - APP_CPU_CLKCTL"]
# [inline (always)]
pub const fn app_cpu_clkctl (& self) -> & AppCpuClkctl { & self . app_cpu_clkctl } # [doc = "0x08 - APP_CPU_CLKSTAT"]
# [inline (always)]
pub const fn app_cpu_clkstat (& self) -> & AppCpuClkstat { & self . app_cpu_clkstat } # [doc = "0x0c - APP_CAN_CLKCTL"]
# [inline (always)]
pub const fn app_can_clkctl (& self) -> & AppCanClkctl { & self . app_can_clkctl } # [doc = "0x10 - APP_CAN_CLKSTAT"]
# [inline (always)]
pub const fn app_can_clkstat (& self) -> & AppCanClkstat { & self . app_can_clkstat } # [doc = "0x14 - APP_SPI_CLKCTL"]
# [inline (always)]
pub const fn app_spi_clkctl (& self) -> & AppSpiClkctl { & self . app_spi_clkctl } # [doc = "0x18 - APP_SPI_CLKSTAT"]
# [inline (always)]
pub const fn app_spi_clkstat (& self) -> & AppSpiClkstat { & self . app_spi_clkstat } # [doc = "0x1c - APP_SPI_BUSIF_CLKCTL"]
# [inline (always)]
pub const fn app_spi_busif_clkctl (& self) -> & AppSpiBusifClkctl { & self . app_spi_busif_clkctl } # [doc = "0x20 - APP_SPI_BUSIF_CLKSTAT"]
# [inline (always)]
pub const fn app_spi_busif_clkstat (& self) -> & AppSpiBusifClkstat { & self . app_spi_busif_clkstat } # [doc = "0x24 - APP_QSPI_CLKCTL"]
# [inline (always)]
pub const fn app_qspi_clkctl (& self) -> & AppQspiClkctl { & self . app_qspi_clkctl } # [doc = "0x28 - APP_QSPI_CLKSTAT"]
# [inline (always)]
pub const fn app_qspi_clkstat (& self) -> & AppQspiClkstat { & self . app_qspi_clkstat } # [doc = "0x2c - TOPSS_CLKCTL"]
# [inline (always)]
pub const fn topss_clkctl (& self) -> & TopssClkctl { & self . topss_clkctl } # [doc = "0x30 - TOPSS_CLKSTAT"]
# [inline (always)]
pub const fn topss_clkstat (& self) -> & TopssClkstat { & self . topss_clkstat } # [doc = "0x34 - APP_RTI_CLKCTL"]
# [inline (always)]
pub const fn app_rti_clkctl (& self) -> & AppRtiClkctl { & self . app_rti_clkctl } # [doc = "0x38 - APP_RTI_CLKSTAT"]
# [inline (always)]
pub const fn app_rti_clkstat (& self) -> & AppRtiClkstat { & self . app_rti_clkstat } # [doc = "0x3c - APP_WD_CLKCTL"]
# [inline (always)]
pub const fn app_wd_clkctl (& self) -> & AppWdClkctl { & self . app_wd_clkctl } # [doc = "0x40 - APP_WD_CLKSTAT"]
# [inline (always)]
pub const fn app_wd_clkstat (& self) -> & AppWdClkstat { & self . app_wd_clkstat } # [doc = "0x44 - APP_UART_0_CLKCTL"]
# [inline (always)]
pub const fn app_uart_0_clkctl (& self) -> & AppUart0Clkctl { & self . app_uart_0_clkctl } # [doc = "0x48 - APP_UART_0_CLKSTAT"]
# [inline (always)]
pub const fn app_uart_0_clkstat (& self) -> & AppUart0Clkstat { & self . app_uart_0_clkstat } # [doc = "0x4c - APP_UART_1_CLKCTL"]
# [inline (always)]
pub const fn app_uart_1_clkctl (& self) -> & AppUart1Clkctl { & self . app_uart_1_clkctl } # [doc = "0x50 - APP_UART_1_CLKSTAT"]
# [inline (always)]
pub const fn app_uart_1_clkstat (& self) -> & AppUart1Clkstat { & self . app_uart_1_clkstat } # [doc = "0x54 - APP_I2C_CLKCTL"]
# [inline (always)]
pub const fn app_i2c_clkctl (& self) -> & AppI2cClkctl { & self . app_i2c_clkctl } # [doc = "0x58 - APP_I2C_CLKSTAT"]
# [inline (always)]
pub const fn app_i2c_clkstat (& self) -> & AppI2cClkstat { & self . app_i2c_clkstat } # [doc = "0x5c - APP_LIN_CLKCTL"]
# [inline (always)]
pub const fn app_lin_clkctl (& self) -> & AppLinClkctl { & self . app_lin_clkctl } # [doc = "0x60 - APP_LIN_CLKSTAT"]
# [inline (always)]
pub const fn app_lin_clkstat (& self) -> & AppLinClkstat { & self . app_lin_clkstat } # [doc = "0x64 - RESERVED0"]
# [inline (always)]
pub const fn reserved0 (& self) -> & Reserved0 { & self . reserved0 } # [doc = "0x68 - RESERVED1"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0x6c - RESERVED2"]
# [inline (always)]
pub const fn reserved2 (& self) -> & Reserved2 { & self . reserved2 } # [doc = "0x70 - RESERVED3"]
# [inline (always)]
pub const fn reserved3 (& self) -> & Reserved3 { & self . reserved3 } # [doc = "0x74 - IPCFGCLKGATE0"]
# [inline (always)]
pub const fn ipcfgclkgate0 (& self) -> & Ipcfgclkgate0 { & self . ipcfgclkgate0 } # [doc = "0x78 - IPCFGCLKGATE1"]
# [inline (always)]
pub const fn ipcfgclkgate1 (& self) -> & Ipcfgclkgate1 { & self . ipcfgclkgate1 } # [doc = "0x7c - IPCFGCLKGATE2"]
# [inline (always)]
pub const fn ipcfgclkgate2 (& self) -> & Ipcfgclkgate2 { & self . ipcfgclkgate2 } # [doc = "0x80 - BLOCKRESET0"]
# [inline (always)]
pub const fn blockreset0 (& self) -> & Blockreset0 { & self . blockreset0 } # [doc = "0x84 - BLOCKRESET1"]
# [inline (always)]
pub const fn blockreset1 (& self) -> & Blockreset1 { & self . blockreset1 } # [doc = "0x88 - BLOCKRESET2"]
# [inline (always)]
pub const fn blockreset2 (& self) -> & Blockreset2 { & self . blockreset2 } # [doc = "0x8c - PLATFORM_SIGNATURE"]
# [inline (always)]
pub const fn platform_signature (& self) -> & PlatformSignature { & self . platform_signature } # [doc = "0x90 - POWERMODE"]
# [inline (always)]
pub const fn powermode (& self) -> & Powermode { & self . powermode } # [doc = "0x94 - RST_WFICHECK"]
# [inline (always)]
pub const fn rst_wficheck (& self) -> & RstWficheck { & self . rst_wficheck } # [doc = "0x98 - RST_ASSERTDLY"]
# [inline (always)]
pub const fn rst_assertdly (& self) -> & RstAssertdly { & self . rst_assertdly } # [doc = "0x9c - RST2ASSERTDLY"]
# [inline (always)]
pub const fn rst2assertdly (& self) -> & Rst2assertdly { & self . rst2assertdly } # [doc = "0xa0 - RST_FSM_TRIG"]
# [inline (always)]
pub const fn rst_fsm_trig (& self) -> & RstFsmTrig { & self . rst_fsm_trig } # [doc = "0xa4 - RST_CAUSE"]
# [inline (always)]
pub const fn rst_cause (& self) -> & RstCause { & self . rst_cause } # [doc = "0xa8 - RST_CAUSE_CLR"]
# [inline (always)]
pub const fn rst_cause_clr (& self) -> & RstCauseClr { & self . rst_cause_clr } # [doc = "0xac - XTALCLK_CLK_GATE"]
# [inline (always)]
pub const fn xtalclk_clk_gate (& self) -> & XtalclkClkGate { & self . xtalclk_clk_gate } # [doc = "0xb0 - XTALCLKX2_CLK_GATE"]
# [inline (always)]
pub const fn xtalclkx2_clk_gate (& self) -> & Xtalclkx2ClkGate { & self . xtalclkx2_clk_gate } # [doc = "0xb4 - APLLDIV2_CLK_GATE"]
# [inline (always)]
pub const fn aplldiv2_clk_gate (& self) -> & Aplldiv2ClkGate { & self . aplldiv2_clk_gate } # [doc = "0xb8 - DFT_APPSS_LSTC_CLK_GATE"]
# [inline (always)]
pub const fn dft_appss_lstc_clk_gate (& self) -> & DftAppssLstcClkGate { & self . dft_appss_lstc_clk_gate } # [doc = "0xbc - DFT_APPSS_LSTC_VBUSP_CLK_GATE"]
# [inline (always)]
pub const fn dft_appss_lstc_vbusp_clk_gate (& self) -> & DftAppssLstcVbuspClkGate { & self . dft_appss_lstc_vbusp_clk_gate } # [doc = "0xc0 - APP_ROM_CLOCK_GATE"]
# [inline (always)]
pub const fn app_rom_clock_gate (& self) -> & AppRomClockGate { & self . app_rom_clock_gate } # [doc = "0xc4 - APP_RAM1_CLOCK_GATE"]
# [inline (always)]
pub const fn app_ram1_clock_gate (& self) -> & AppRam1ClockGate { & self . app_ram1_clock_gate } # [doc = "0xc8 - APP_RAM2_CLOCK_GATE"]
# [inline (always)]
pub const fn app_ram2_clock_gate (& self) -> & AppRam2ClockGate { & self . app_ram2_clock_gate } # [doc = "0xcc - APP_RAM3_CLOCK_GATE"]
# [inline (always)]
pub const fn app_ram3_clock_gate (& self) -> & AppRam3ClockGate { & self . app_ram3_clock_gate } # [doc = "0xd0 - CFG_XBARA_DYNAMIC_CG"]
# [inline (always)]
pub const fn cfg_xbara_dynamic_cg (& self) -> & CfgXbaraDynamicCg { & self . cfg_xbara_dynamic_cg } # [doc = "0xd4 - CFG_TPTC1_DYNAMIC_CG"]
# [inline (always)]
pub const fn cfg_tptc1_dynamic_cg (& self) -> & CfgTptc1DynamicCg { & self . cfg_tptc1_dynamic_cg } # [doc = "0xd8 - CFG_TPTC2_DYNAMIC_CG"]
# [inline (always)]
pub const fn cfg_tptc2_dynamic_cg (& self) -> & CfgTptc2DynamicCg { & self . cfg_tptc2_dynamic_cg } # [doc = "0xdc - CFG_XBARA_SET_DYNAMIC_CG"]
# [inline (always)]
pub const fn cfg_xbara_set_dynamic_cg (& self) -> & CfgXbaraSetDynamicCg { & self . cfg_xbara_set_dynamic_cg } # [doc = "0xe0 - CFG_TPTC1_SET_DYNAMIC_CG"]
# [inline (always)]
pub const fn cfg_tptc1_set_dynamic_cg (& self) -> & CfgTptc1SetDynamicCg { & self . cfg_tptc1_set_dynamic_cg } # [doc = "0xe4 - CFG_TPTC2_SET_DYNAMIC_CG"]
# [inline (always)]
pub const fn cfg_tptc2_set_dynamic_cg (& self) -> & CfgTptc2SetDynamicCg { & self . cfg_tptc2_set_dynamic_cg } # [doc = "0xe8 - CM4_FORCE_HCLK_GATE"]
# [inline (always)]
pub const fn cm4_force_hclk_gate (& self) -> & Cm4ForceHclkGate { & self . cm4_force_hclk_gate } # [doc = "0xec - LIN_SCI_DIV"]
# [inline (always)]
pub const fn lin_sci_div (& self) -> & LinSciDiv { & self . lin_sci_div } # [doc = "0xf0 - APP_LSTC_EN"]
# [inline (always)]
pub const fn app_lstc_en (& self) -> & AppLstcEn { & self . app_lstc_en } # [doc = "0x1008 - - KICK0 component"]
# [inline (always)]
pub const fn lock0_kick0 (& self) -> & Lock0Kick0 { & self . lock0_kick0 } # [doc = "0x100c - - KICK1 component"]
# [inline (always)]
pub const fn lock0_kick1 (& self) -> & Lock0Kick1 { & self . lock0_kick1 } # [doc = "0x1010 - Interrupt Raw Status/Set Register"]
# [inline (always)]
pub const fn intr_raw_status (& self) -> & IntrRawStatus { & self . intr_raw_status } # [doc = "0x1014 - Interrupt Enabled Status/Clear register"]
# [inline (always)]
pub const fn intr_enabled_status_clear (& self) -> & IntrEnabledStatusClear { & self . intr_enabled_status_clear } # [doc = "0x1018 - Interrupt Enable register"]
# [inline (always)]
pub const fn intr_enable (& self) -> & IntrEnable { & self . intr_enable } # [doc = "0x101c - Interrupt Enable Clear register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x1020 - EOI register"]
# [inline (always)]
pub const fn eoi (& self) -> & Eoi { & self . eoi } # [doc = "0x1024 - Fault Address register"]
# [inline (always)]
pub const fn fault_address (& self) -> & FaultAddress { & self . fault_address } # [doc = "0x1028 - Fault Type Status register"]
# [inline (always)]
pub const fn fault_type_status (& self) -> & FaultTypeStatus { & self . fault_type_status } # [doc = "0x102c - Fault Attribute Status register"]
# [inline (always)]
pub const fn fault_attr_status (& self) -> & FaultAttrStatus { & self . fault_attr_status } # [doc = "0x1030 - Fault Clear register"]
# [inline (always)]
pub const fn fault_clear (& self) -> & FaultClear { & self . fault_clear } } # [doc = "PID (rw) register accessor: PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `PID_W6_O0` reader - "]
pub type PidW6O0R = crate :: FieldReader ; # [doc = "Field `PID_W6_O0` writer - "]
pub type PidW6O0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PID_W2_O6` reader - "]
pub type PidW2O6R = crate :: FieldReader ; # [doc = "Field `PID_W2_O6` writer - "]
pub type PidW2O6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PID_W3_O8` reader - "]
pub type PidW3O8R = crate :: FieldReader ; # [doc = "Field `PID_W3_O8` writer - "]
pub type PidW3O8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PID_W5_O11` reader - "]
pub type PidW5O11R = crate :: FieldReader ; # [doc = "Field `PID_W5_O11` writer - "]
pub type PidW5O11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PID_W16_O16` reader - "]
pub type PidW16O16R = crate :: FieldReader < u16 > ; # [doc = "Field `PID_W16_O16` writer - "]
pub type PidW16O16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5"]
# [inline (always)]
pub fn pid_w6_o0 (& self) -> PidW6O0R { PidW6O0R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7"]
# [inline (always)]
pub fn pid_w2_o6 (& self) -> PidW2O6R { PidW2O6R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10"]
# [inline (always)]
pub fn pid_w3_o8 (& self) -> PidW3O8R { PidW3O8R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15"]
# [inline (always)]
pub fn pid_w5_o11 (& self) -> PidW5O11R { PidW5O11R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn pid_w16_o16 (& self) -> PidW16O16R { PidW16O16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5"]
# [inline (always)]
# [must_use]
pub fn pid_w6_o0 (& mut self) -> PidW6O0W < PidSpec > { PidW6O0W :: new (self , 0) } # [doc = "Bits 6:7"]
# [inline (always)]
# [must_use]
pub fn pid_w2_o6 (& mut self) -> PidW2O6W < PidSpec > { PidW2O6W :: new (self , 6) } # [doc = "Bits 8:10"]
# [inline (always)]
# [must_use]
pub fn pid_w3_o8 (& mut self) -> PidW3O8W < PidSpec > { PidW3O8W :: new (self , 8) } # [doc = "Bits 11:15"]
# [inline (always)]
# [must_use]
pub fn pid_w5_o11 (& mut self) -> PidW5O11W < PidSpec > { PidW5O11W :: new (self , 11) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn pid_w16_o16 (& mut self) -> PidW16O16W < PidSpec > { PidW16O16W :: new (self , 16) } } # [doc = "PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CPU_CLKCTL (rw) register accessor: APP_CPU_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cpu_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cpu_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cpu_clkctl`]
module"]
# [doc (alias = "APP_CPU_CLKCTL")]
pub type AppCpuClkctl = crate :: Reg < app_cpu_clkctl :: AppCpuClkctlSpec > ; # [doc = "APP_CPU_CLKCTL"]
pub mod app_cpu_clkctl { # [doc = "Register `APP_CPU_CLKCTL` reader"]
pub type R = crate :: R < AppCpuClkctlSpec > ; # [doc = "Register `APP_CPU_CLKCTL` writer"]
pub type W = crate :: W < AppCpuClkctlSpec > ; # [doc = "Field `srcsel` reader - 15:4\\]
Select the source clock: 0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
Select the source clock: 0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 4:15 - 15:4\\]
Select the source clock: 0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 4:15 - 15:4\\]
Select the source clock: 0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < AppCpuClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppCpuClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_CPU_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cpu_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cpu_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCpuClkctlSpec ; impl crate :: RegisterSpec for AppCpuClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cpu_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppCpuClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_cpu_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppCpuClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CPU_CLKCTL to value 0"]
impl crate :: Resettable for AppCpuClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CPU_CLKSTAT (rw) register accessor: APP_CPU_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cpu_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cpu_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cpu_clkstat`]
module"]
# [doc (alias = "APP_CPU_CLKSTAT")]
pub type AppCpuClkstat = crate :: Reg < app_cpu_clkstat :: AppCpuClkstatSpec > ; # [doc = "APP_CPU_CLKSTAT"]
pub mod app_cpu_clkstat { # [doc = "Register `APP_CPU_CLKSTAT` reader"]
pub type R = crate :: R < AppCpuClkstatSpec > ; # [doc = "Register `APP_CPU_CLKSTAT` writer"]
pub type W = crate :: W < AppCpuClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppCpuClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < AppCpuClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "APP_CPU_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cpu_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cpu_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCpuClkstatSpec ; impl crate :: RegisterSpec for AppCpuClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cpu_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppCpuClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_cpu_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppCpuClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CPU_CLKSTAT to value 0"]
impl crate :: Resettable for AppCpuClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CAN_CLKCTL (rw) register accessor: APP_CAN_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_can_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_can_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_can_clkctl`]
module"]
# [doc (alias = "APP_CAN_CLKCTL")]
pub type AppCanClkctl = crate :: Reg < app_can_clkctl :: AppCanClkctlSpec > ; # [doc = "APP_CAN_CLKCTL"]
pub mod app_can_clkctl { # [doc = "Register `APP_CAN_CLKCTL` reader"]
pub type R = crate :: R < AppCanClkctlSpec > ; # [doc = "Register `APP_CAN_CLKCTL` writer"]
pub type W = crate :: W < AppCanClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `srcsel` reader - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLKFor other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLKFor other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLKFor other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppCanClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLKFor other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < AppCanClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppCanClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_CAN_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_can_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_can_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCanClkctlSpec ; impl crate :: RegisterSpec for AppCanClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_can_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppCanClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_can_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppCanClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CAN_CLKCTL to value 0"]
impl crate :: Resettable for AppCanClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CAN_CLKSTAT (rw) register accessor: APP_CAN_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_can_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_can_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_can_clkstat`]
module"]
# [doc (alias = "APP_CAN_CLKSTAT")]
pub type AppCanClkstat = crate :: Reg < app_can_clkstat :: AppCanClkstatSpec > ; # [doc = "APP_CAN_CLKSTAT"]
pub mod app_can_clkstat { # [doc = "Register `APP_CAN_CLKSTAT` reader"]
pub type R = crate :: R < AppCanClkstatSpec > ; # [doc = "Register `APP_CAN_CLKSTAT` writer"]
pub type W = crate :: W < AppCanClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppCanClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < AppCanClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "APP_CAN_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_can_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_can_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCanClkstatSpec ; impl crate :: RegisterSpec for AppCanClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_can_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppCanClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_can_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppCanClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CAN_CLKSTAT to value 0"]
impl crate :: Resettable for AppCanClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_SPI_CLKCTL (rw) register accessor: APP_SPI_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_spi_clkctl`]
module"]
# [doc (alias = "APP_SPI_CLKCTL")]
pub type AppSpiClkctl = crate :: Reg < app_spi_clkctl :: AppSpiClkctlSpec > ; # [doc = "APP_SPI_CLKCTL"]
pub mod app_spi_clkctl { # [doc = "Register `APP_SPI_CLKCTL` reader"]
pub type R = crate :: R < AppSpiClkctlSpec > ; # [doc = "Register `APP_SPI_CLKCTL` writer"]
pub type W = crate :: W < AppSpiClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `srcsel` reader - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppSpiClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < AppSpiClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppSpiClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_SPI_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppSpiClkctlSpec ; impl crate :: RegisterSpec for AppSpiClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_spi_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppSpiClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_spi_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppSpiClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_SPI_CLKCTL to value 0"]
impl crate :: Resettable for AppSpiClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_SPI_CLKSTAT (rw) register accessor: APP_SPI_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_spi_clkstat`]
module"]
# [doc (alias = "APP_SPI_CLKSTAT")]
pub type AppSpiClkstat = crate :: Reg < app_spi_clkstat :: AppSpiClkstatSpec > ; # [doc = "APP_SPI_CLKSTAT"]
pub mod app_spi_clkstat { # [doc = "Register `APP_SPI_CLKSTAT` reader"]
pub type R = crate :: R < AppSpiClkstatSpec > ; # [doc = "Register `APP_SPI_CLKSTAT` writer"]
pub type W = crate :: W < AppSpiClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppSpiClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < AppSpiClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "APP_SPI_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppSpiClkstatSpec ; impl crate :: RegisterSpec for AppSpiClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_spi_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppSpiClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_spi_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppSpiClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_SPI_CLKSTAT to value 0"]
impl crate :: Resettable for AppSpiClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_SPI_BUSIF_CLKCTL (rw) register accessor: APP_SPI_BUSIF_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_busif_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_busif_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_spi_busif_clkctl`]
module"]
# [doc (alias = "APP_SPI_BUSIF_CLKCTL")]
pub type AppSpiBusifClkctl = crate :: Reg < app_spi_busif_clkctl :: AppSpiBusifClkctlSpec > ; # [doc = "APP_SPI_BUSIF_CLKCTL"]
pub mod app_spi_busif_clkctl { # [doc = "Register `APP_SPI_BUSIF_CLKCTL` reader"]
pub type R = crate :: R < AppSpiBusifClkctlSpec > ; # [doc = "Register `APP_SPI_BUSIF_CLKCTL` writer"]
pub type W = crate :: W < AppSpiBusifClkctlSpec > ; # [doc = "Field `divr` reader - 11:0\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 11:0\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppSpiBusifClkctlSpec > { DivrW :: new (self , 0) } } # [doc = "APP_SPI_BUSIF_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_busif_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_busif_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppSpiBusifClkctlSpec ; impl crate :: RegisterSpec for AppSpiBusifClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_spi_busif_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppSpiBusifClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_spi_busif_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppSpiBusifClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_SPI_BUSIF_CLKCTL to value 0"]
impl crate :: Resettable for AppSpiBusifClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_SPI_BUSIF_CLKSTAT (rw) register accessor: APP_SPI_BUSIF_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_busif_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_busif_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_spi_busif_clkstat`]
module"]
# [doc (alias = "APP_SPI_BUSIF_CLKSTAT")]
pub type AppSpiBusifClkstat = crate :: Reg < app_spi_busif_clkstat :: AppSpiBusifClkstatSpec > ; # [doc = "APP_SPI_BUSIF_CLKSTAT"]
pub mod app_spi_busif_clkstat { # [doc = "Register `APP_SPI_BUSIF_CLKSTAT` reader"]
pub type R = crate :: R < AppSpiBusifClkstatSpec > ; # [doc = "Register `APP_SPI_BUSIF_CLKSTAT` writer"]
pub type W = crate :: W < AppSpiBusifClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppSpiBusifClkstatSpec > { CurrdivrW :: new (self , 0) } } # [doc = "APP_SPI_BUSIF_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_spi_busif_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_spi_busif_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppSpiBusifClkstatSpec ; impl crate :: RegisterSpec for AppSpiBusifClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_spi_busif_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppSpiBusifClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_spi_busif_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppSpiBusifClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_SPI_BUSIF_CLKSTAT to value 0"]
impl crate :: Resettable for AppSpiBusifClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_QSPI_CLKCTL (rw) register accessor: APP_QSPI_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_qspi_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_qspi_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_qspi_clkctl`]
module"]
# [doc (alias = "APP_QSPI_CLKCTL")]
pub type AppQspiClkctl = crate :: Reg < app_qspi_clkctl :: AppQspiClkctlSpec > ; # [doc = "APP_QSPI_CLKCTL"]
pub mod app_qspi_clkctl { # [doc = "Register `APP_QSPI_CLKCTL` reader"]
pub type R = crate :: R < AppQspiClkctlSpec > ; # [doc = "Register `APP_QSPI_CLKCTL` writer"]
pub type W = crate :: W < AppQspiClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `srcsel` reader - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppQspiClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < AppQspiClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppQspiClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_QSPI_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_qspi_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_qspi_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppQspiClkctlSpec ; impl crate :: RegisterSpec for AppQspiClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_qspi_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppQspiClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_qspi_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppQspiClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_QSPI_CLKCTL to value 0"]
impl crate :: Resettable for AppQspiClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_QSPI_CLKSTAT (rw) register accessor: APP_QSPI_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_qspi_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_qspi_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_qspi_clkstat`]
module"]
# [doc (alias = "APP_QSPI_CLKSTAT")]
pub type AppQspiClkstat = crate :: Reg < app_qspi_clkstat :: AppQspiClkstatSpec > ; # [doc = "APP_QSPI_CLKSTAT"]
pub mod app_qspi_clkstat { # [doc = "Register `APP_QSPI_CLKSTAT` reader"]
pub type R = crate :: R < AppQspiClkstatSpec > ; # [doc = "Register `APP_QSPI_CLKSTAT` writer"]
pub type W = crate :: W < AppQspiClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppQspiClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < AppQspiClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "APP_QSPI_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_qspi_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_qspi_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppQspiClkstatSpec ; impl crate :: RegisterSpec for AppQspiClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_qspi_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppQspiClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_qspi_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppQspiClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_QSPI_CLKSTAT to value 0"]
impl crate :: Resettable for AppQspiClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TOPSS_CLKCTL (rw) register accessor: TOPSS_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`topss_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`topss_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@topss_clkctl`]
module"]
# [doc (alias = "TOPSS_CLKCTL")]
pub type TopssClkctl = crate :: Reg < topss_clkctl :: TopssClkctlSpec > ; # [doc = "TOPSS_CLKCTL"]
pub mod topss_clkctl { # [doc = "Register `TOPSS_CLKCTL` reader"]
pub type R = crate :: R < TopssClkctlSpec > ; # [doc = "Register `TOPSS_CLKCTL` writer"]
pub type W = crate :: W < TopssClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `srcsel` reader - 15:4\\]
0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL 0x3 : FAST_CLK 0x4 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL 0x3 : FAST_CLK 0x4 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL 0x3 : FAST_CLK 0x4 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < TopssClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL 0x3 : FAST_CLK 0x4 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < TopssClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < TopssClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "TOPSS_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`topss_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`topss_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TopssClkctlSpec ; impl crate :: RegisterSpec for TopssClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`topss_clkctl::R`](R) reader structure"]
impl crate :: Readable for TopssClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`topss_clkctl::W`](W) writer structure"]
impl crate :: Writable for TopssClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TOPSS_CLKCTL to value 0"]
impl crate :: Resettable for TopssClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TOPSS_CLKSTAT (rw) register accessor: TOPSS_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`topss_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`topss_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@topss_clkstat`]
module"]
# [doc (alias = "TOPSS_CLKSTAT")]
pub type TopssClkstat = crate :: Reg < topss_clkstat :: TopssClkstatSpec > ; # [doc = "TOPSS_CLKSTAT"]
pub mod topss_clkstat { # [doc = "Register `TOPSS_CLKSTAT` reader"]
pub type R = crate :: R < TopssClkstatSpec > ; # [doc = "Register `TOPSS_CLKSTAT` writer"]
pub type W = crate :: W < TopssClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < TopssClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < TopssClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "TOPSS_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`topss_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`topss_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TopssClkstatSpec ; impl crate :: RegisterSpec for TopssClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`topss_clkstat::R`](R) reader structure"]
impl crate :: Readable for TopssClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`topss_clkstat::W`](W) writer structure"]
impl crate :: Writable for TopssClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TOPSS_CLKSTAT to value 0"]
impl crate :: Resettable for TopssClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_RTI_CLKCTL (rw) register accessor: APP_RTI_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_rti_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_rti_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_rti_clkctl`]
module"]
# [doc (alias = "APP_RTI_CLKCTL")]
pub type AppRtiClkctl = crate :: Reg < app_rti_clkctl :: AppRtiClkctlSpec > ; # [doc = "APP_RTI_CLKCTL"]
pub mod app_rti_clkctl { # [doc = "Register `APP_RTI_CLKCTL` reader"]
pub type R = crate :: R < AppRtiClkctlSpec > ; # [doc = "Register `APP_RTI_CLKCTL` writer"]
pub type W = crate :: W < AppRtiClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `srcsel` reader - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK (Ungated OSC_CLK for RTI in Sleep mode) 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK (Ungated OSC_CLK for RTI in Sleep mode) 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK (Ungated OSC_CLK for RTI in Sleep mode) 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppRtiClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK (Ungated OSC_CLK for RTI in Sleep mode) 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < AppRtiClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppRtiClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_RTI_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_rti_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_rti_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppRtiClkctlSpec ; impl crate :: RegisterSpec for AppRtiClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_rti_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppRtiClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_rti_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppRtiClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_RTI_CLKCTL to value 0"]
impl crate :: Resettable for AppRtiClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_RTI_CLKSTAT (rw) register accessor: APP_RTI_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_rti_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_rti_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_rti_clkstat`]
module"]
# [doc (alias = "APP_RTI_CLKSTAT")]
pub type AppRtiClkstat = crate :: Reg < app_rti_clkstat :: AppRtiClkstatSpec > ; # [doc = "APP_RTI_CLKSTAT"]
pub mod app_rti_clkstat { # [doc = "Register `APP_RTI_CLKSTAT` reader"]
pub type R = crate :: R < AppRtiClkstatSpec > ; # [doc = "Register `APP_RTI_CLKSTAT` writer"]
pub type W = crate :: W < AppRtiClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppRtiClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < AppRtiClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "APP_RTI_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_rti_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_rti_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppRtiClkstatSpec ; impl crate :: RegisterSpec for AppRtiClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_rti_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppRtiClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_rti_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppRtiClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_RTI_CLKSTAT to value 0"]
impl crate :: Resettable for AppRtiClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_WD_CLKCTL (rw) register accessor: APP_WD_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_wd_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_wd_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_wd_clkctl`]
module"]
# [doc (alias = "APP_WD_CLKCTL")]
pub type AppWdClkctl = crate :: Reg < app_wd_clkctl :: AppWdClkctlSpec > ; # [doc = "APP_WD_CLKCTL"]
pub mod app_wd_clkctl { # [doc = "Register `APP_WD_CLKCTL` reader"]
pub type R = crate :: R < AppWdClkctlSpec > ; # [doc = "Register `APP_WD_CLKCTL` writer"]
pub type W = crate :: W < AppWdClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `srcsel` reader - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselR = crate :: FieldReader < u16 > ; # [doc = "Field `srcsel` writer - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppWdClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < AppWdClkctlSpec > { SrcselW :: new (self , 4) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppWdClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_WD_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_wd_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_wd_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppWdClkctlSpec ; impl crate :: RegisterSpec for AppWdClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_wd_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppWdClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_wd_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppWdClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_WD_CLKCTL to value 0"]
impl crate :: Resettable for AppWdClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_WD_CLKSTAT (rw) register accessor: APP_WD_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_wd_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_wd_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_wd_clkstat`]
module"]
# [doc (alias = "APP_WD_CLKSTAT")]
pub type AppWdClkstat = crate :: Reg < app_wd_clkstat :: AppWdClkstatSpec > ; # [doc = "APP_WD_CLKSTAT"]
pub mod app_wd_clkstat { # [doc = "Register `APP_WD_CLKSTAT` reader"]
pub type R = crate :: R < AppWdClkstatSpec > ; # [doc = "Register `APP_WD_CLKSTAT` writer"]
pub type W = crate :: W < AppWdClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppWdClkstatSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < AppWdClkstatSpec > { CurrclkW :: new (self , 4) } } # [doc = "APP_WD_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_wd_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_wd_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppWdClkstatSpec ; impl crate :: RegisterSpec for AppWdClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_wd_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppWdClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_wd_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppWdClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_WD_CLKSTAT to value 0"]
impl crate :: Resettable for AppWdClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_UART_0_CLKCTL (rw) register accessor: APP_UART_0_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_0_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_0_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_uart_0_clkctl`]
module"]
# [doc (alias = "APP_UART_0_CLKCTL")]
pub type AppUart0Clkctl = crate :: Reg < app_uart_0_clkctl :: AppUart0ClkctlSpec > ; # [doc = "APP_UART_0_CLKCTL"]
pub mod app_uart_0_clkctl { # [doc = "Register `APP_UART_0_CLKCTL` reader"]
pub type R = crate :: R < AppUart0ClkctlSpec > ; # [doc = "Register `APP_UART_0_CLKCTL` writer"]
pub type W = crate :: W < AppUart0ClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppUart0ClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppUart0ClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_UART_0_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_0_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_0_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppUart0ClkctlSpec ; impl crate :: RegisterSpec for AppUart0ClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_uart_0_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppUart0ClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_uart_0_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppUart0ClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_UART_0_CLKCTL to value 0"]
impl crate :: Resettable for AppUart0ClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_UART_0_CLKSTAT (rw) register accessor: APP_UART_0_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_0_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_0_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_uart_0_clkstat`]
module"]
# [doc (alias = "APP_UART_0_CLKSTAT")]
pub type AppUart0Clkstat = crate :: Reg < app_uart_0_clkstat :: AppUart0ClkstatSpec > ; # [doc = "APP_UART_0_CLKSTAT"]
pub mod app_uart_0_clkstat { # [doc = "Register `APP_UART_0_CLKSTAT` reader"]
pub type R = crate :: R < AppUart0ClkstatSpec > ; # [doc = "Register `APP_UART_0_CLKSTAT` writer"]
pub type W = crate :: W < AppUart0ClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppUart0ClkstatSpec > { CurrdivrW :: new (self , 0) } } # [doc = "APP_UART_0_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_0_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_0_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppUart0ClkstatSpec ; impl crate :: RegisterSpec for AppUart0ClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_uart_0_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppUart0ClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_uart_0_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppUart0ClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_UART_0_CLKSTAT to value 0"]
impl crate :: Resettable for AppUart0ClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_UART_1_CLKCTL (rw) register accessor: APP_UART_1_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_1_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_1_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_uart_1_clkctl`]
module"]
# [doc (alias = "APP_UART_1_CLKCTL")]
pub type AppUart1Clkctl = crate :: Reg < app_uart_1_clkctl :: AppUart1ClkctlSpec > ; # [doc = "APP_UART_1_CLKCTL"]
pub mod app_uart_1_clkctl { # [doc = "Register `APP_UART_1_CLKCTL` reader"]
pub type R = crate :: R < AppUart1ClkctlSpec > ; # [doc = "Register `APP_UART_1_CLKCTL` writer"]
pub type W = crate :: W < AppUart1ClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppUart1ClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppUart1ClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_UART_1_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_1_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_1_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppUart1ClkctlSpec ; impl crate :: RegisterSpec for AppUart1ClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_uart_1_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppUart1ClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_uart_1_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppUart1ClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_UART_1_CLKCTL to value 0"]
impl crate :: Resettable for AppUart1ClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_UART_1_CLKSTAT (rw) register accessor: APP_UART_1_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_1_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_1_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_uart_1_clkstat`]
module"]
# [doc (alias = "APP_UART_1_CLKSTAT")]
pub type AppUart1Clkstat = crate :: Reg < app_uart_1_clkstat :: AppUart1ClkstatSpec > ; # [doc = "APP_UART_1_CLKSTAT"]
pub mod app_uart_1_clkstat { # [doc = "Register `APP_UART_1_CLKSTAT` reader"]
pub type R = crate :: R < AppUart1ClkstatSpec > ; # [doc = "Register `APP_UART_1_CLKSTAT` writer"]
pub type W = crate :: W < AppUart1ClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppUart1ClkstatSpec > { CurrdivrW :: new (self , 0) } } # [doc = "APP_UART_1_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_uart_1_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_uart_1_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppUart1ClkstatSpec ; impl crate :: RegisterSpec for AppUart1ClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_uart_1_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppUart1ClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_uart_1_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppUart1ClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_UART_1_CLKSTAT to value 0"]
impl crate :: Resettable for AppUart1ClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_I2C_CLKCTL (rw) register accessor: APP_I2C_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_i2c_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_i2c_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_i2c_clkctl`]
module"]
# [doc (alias = "APP_I2C_CLKCTL")]
pub type AppI2cClkctl = crate :: Reg < app_i2c_clkctl :: AppI2cClkctlSpec > ; # [doc = "APP_I2C_CLKCTL"]
pub mod app_i2c_clkctl { # [doc = "Register `APP_I2C_CLKCTL` reader"]
pub type R = crate :: R < AppI2cClkctlSpec > ; # [doc = "Register `APP_I2C_CLKCTL` writer"]
pub type W = crate :: W < AppI2cClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppI2cClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppI2cClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_I2C_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_i2c_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_i2c_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppI2cClkctlSpec ; impl crate :: RegisterSpec for AppI2cClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_i2c_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppI2cClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_i2c_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppI2cClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_I2C_CLKCTL to value 0"]
impl crate :: Resettable for AppI2cClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_I2C_CLKSTAT (rw) register accessor: APP_I2C_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_i2c_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_i2c_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_i2c_clkstat`]
module"]
# [doc (alias = "APP_I2C_CLKSTAT")]
pub type AppI2cClkstat = crate :: Reg < app_i2c_clkstat :: AppI2cClkstatSpec > ; # [doc = "APP_I2C_CLKSTAT"]
pub mod app_i2c_clkstat { # [doc = "Register `APP_I2C_CLKSTAT` reader"]
pub type R = crate :: R < AppI2cClkstatSpec > ; # [doc = "Register `APP_I2C_CLKSTAT` writer"]
pub type W = crate :: W < AppI2cClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppI2cClkstatSpec > { CurrdivrW :: new (self , 0) } } # [doc = "APP_I2C_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_i2c_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_i2c_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppI2cClkstatSpec ; impl crate :: RegisterSpec for AppI2cClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_i2c_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppI2cClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_i2c_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppI2cClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_I2C_CLKSTAT to value 0"]
impl crate :: Resettable for AppI2cClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_LIN_CLKCTL (rw) register accessor: APP_LIN_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_lin_clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_lin_clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_lin_clkctl`]
module"]
# [doc (alias = "APP_LIN_CLKCTL")]
pub type AppLinClkctl = crate :: Reg < app_lin_clkctl :: AppLinClkctlSpec > ; # [doc = "APP_LIN_CLKCTL"]
pub mod app_lin_clkctl { # [doc = "Register `APP_LIN_CLKCTL` reader"]
pub type R = crate :: R < AppLinClkctlSpec > ; # [doc = "Register `APP_LIN_CLKCTL` writer"]
pub type W = crate :: W < AppLinClkctlSpec > ; # [doc = "Field `gate` reader - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < AppLinClkctlSpec > { GateW :: new (self , 0) } # [doc = "Bits 16:27 - 27:16\\]
Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < AppLinClkctlSpec > { DivrW :: new (self , 16) } } # [doc = "APP_LIN_CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_lin_clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_lin_clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppLinClkctlSpec ; impl crate :: RegisterSpec for AppLinClkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_lin_clkctl::R`](R) reader structure"]
impl crate :: Readable for AppLinClkctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_lin_clkctl::W`](W) writer structure"]
impl crate :: Writable for AppLinClkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_LIN_CLKCTL to value 0"]
impl crate :: Resettable for AppLinClkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_LIN_CLKSTAT (rw) register accessor: APP_LIN_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_lin_clkstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_lin_clkstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_lin_clkstat`]
module"]
# [doc (alias = "APP_LIN_CLKSTAT")]
pub type AppLinClkstat = crate :: Reg < app_lin_clkstat :: AppLinClkstatSpec > ; # [doc = "APP_LIN_CLKSTAT"]
pub mod app_lin_clkstat { # [doc = "Register `APP_LIN_CLKSTAT` reader"]
pub type R = crate :: R < AppLinClkstatSpec > ; # [doc = "Register `APP_LIN_CLKSTAT` writer"]
pub type W = crate :: W < AppLinClkstatSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < AppLinClkstatSpec > { CurrdivrW :: new (self , 0) } } # [doc = "APP_LIN_CLKSTAT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_lin_clkstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_lin_clkstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppLinClkstatSpec ; impl crate :: RegisterSpec for AppLinClkstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_lin_clkstat::R`](R) reader structure"]
impl crate :: Readable for AppLinClkstatSpec { } # [doc = "`write(|w| ..)` method takes [`app_lin_clkstat::W`](W) writer structure"]
impl crate :: Writable for AppLinClkstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_LIN_CLKSTAT to value 0"]
impl crate :: Resettable for AppLinClkstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED0 (rw) register accessor: RESERVED0\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved0`]
module"]
# [doc (alias = "RESERVED0")]
pub type Reserved0 = crate :: Reg < reserved0 :: Reserved0Spec > ; # [doc = "RESERVED0"]
pub mod reserved0 { # [doc = "Register `RESERVED0` reader"]
pub type R = crate :: R < Reserved0Spec > ; # [doc = "Register `RESERVED0` writer"]
pub type W = crate :: W < Reserved0Spec > ; # [doc = "Field `rwres` reader - 7:0\\]
Bit 2:0 - Software reset for hwass cba3to2 and m64top32 bridge instances in appss. (reset value - 0) Bit 5:3 - Software reset for fecss p2p async bridge instance in appss. (reset value - 0) 0x0 : Release the reset 0x7 : Assert the reset Bit 31:6 - Reserved"]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - 7:0\\]
Bit 2:0 - Software reset for hwass cba3to2 and m64top32 bridge instances in appss. (reset value - 0) Bit 5:3 - Software reset for fecss p2p async bridge instance in appss. (reset value - 0) 0x0 : Release the reset 0x7 : Assert the reset Bit 31:6 - Reserved"]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - 15:8\\]
Reserved"]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - 15:8\\]
Reserved"]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - 31:24\\]
Reserved"]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - 31:24\\]
Reserved"]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Bit 2:0 - Software reset for hwass cba3to2 and m64top32 bridge instances in appss. (reset value - 0) Bit 5:3 - Software reset for fecss p2p async bridge instance in appss. (reset value - 0) 0x0 : Release the reset 0x7 : Assert the reset Bit 31:6 - Reserved"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Bit 2:0 - Software reset for hwass cba3to2 and m64top32 bridge instances in appss. (reset value - 0) Bit 5:3 - Software reset for fecss p2p async bridge instance in appss. (reset value - 0) 0x0 : Release the reset 0x7 : Assert the reset Bit 31:6 - Reserved"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved0Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved0Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved0Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED0\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved0Spec ; impl crate :: RegisterSpec for Reserved0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved0::R`](R) reader structure"]
impl crate :: Readable for Reserved0Spec { } # [doc = "`write(|w| ..)` method takes [`reserved0::W`](W) writer structure"]
impl crate :: Writable for Reserved0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED0 to value 0"]
impl crate :: Resettable for Reserved0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED1 (rw) register accessor: RESERVED1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
# [doc (alias = "RESERVED1")]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "RESERVED1"]
pub mod reserved1 { # [doc = "Register `RESERVED1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `RESERVED1` writer"]
pub type W = crate :: W < Reserved1Spec > ; # [doc = "Field `rwres` reader - 7:0\\]
Reserved"]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - 7:0\\]
Reserved"]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - 15:8\\]
Reserved"]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - 15:8\\]
Reserved"]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - 31:24\\]
Reserved"]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - 31:24\\]
Reserved"]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved1Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved1Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved1Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED2 (rw) register accessor: RESERVED2\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved2`]
module"]
# [doc (alias = "RESERVED2")]
pub type Reserved2 = crate :: Reg < reserved2 :: Reserved2Spec > ; # [doc = "RESERVED2"]
pub mod reserved2 { # [doc = "Register `RESERVED2` reader"]
pub type R = crate :: R < Reserved2Spec > ; # [doc = "Register `RESERVED2` writer"]
pub type W = crate :: W < Reserved2Spec > ; # [doc = "Field `rwres` reader - 7:0\\]
Reserved"]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - 7:0\\]
Reserved"]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - 15:8\\]
Reserved"]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - 15:8\\]
Reserved"]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - 31:24\\]
Reserved"]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - 31:24\\]
Reserved"]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved2Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved2Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved2Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED2\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved2Spec ; impl crate :: RegisterSpec for Reserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved2::R`](R) reader structure"]
impl crate :: Readable for Reserved2Spec { } # [doc = "`write(|w| ..)` method takes [`reserved2::W`](W) writer structure"]
impl crate :: Writable for Reserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED2 to value 0"]
impl crate :: Resettable for Reserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED3 (rw) register accessor: RESERVED3\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved3`]
module"]
# [doc (alias = "RESERVED3")]
pub type Reserved3 = crate :: Reg < reserved3 :: Reserved3Spec > ; # [doc = "RESERVED3"]
pub mod reserved3 { # [doc = "Register `RESERVED3` reader"]
pub type R = crate :: R < Reserved3Spec > ; # [doc = "Register `RESERVED3` writer"]
pub type W = crate :: W < Reserved3Spec > ; # [doc = "Field `rwres` reader - 7:0\\]
Reserved"]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - 7:0\\]
Reserved"]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - 15:8\\]
Reserved"]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - 15:8\\]
Reserved"]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - 31:24\\]
Reserved"]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - 31:24\\]
Reserved"]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved3Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved3Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved3Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED3\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved3Spec ; impl crate :: RegisterSpec for Reserved3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved3::R`](R) reader structure"]
impl crate :: Readable for Reserved3Spec { } # [doc = "`write(|w| ..)` method takes [`reserved3::W`](W) writer structure"]
impl crate :: Writable for Reserved3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED3 to value 0"]
impl crate :: Resettable for Reserved3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPCFGCLKGATE0 (rw) register accessor: IPCFGCLKGATE0\n\nYou can [`read`](crate::Reg::read) this register and get [`ipcfgclkgate0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipcfgclkgate0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipcfgclkgate0`]
module"]
# [doc (alias = "IPCFGCLKGATE0")]
pub type Ipcfgclkgate0 = crate :: Reg < ipcfgclkgate0 :: Ipcfgclkgate0Spec > ; # [doc = "IPCFGCLKGATE0"]
pub mod ipcfgclkgate0 { # [doc = "Register `IPCFGCLKGATE0` reader"]
pub type R = crate :: R < Ipcfgclkgate0Spec > ; # [doc = "Register `IPCFGCLKGATE0` writer"]
pub type W = crate :: W < Ipcfgclkgate0Spec > ; # [doc = "Field `xbara` reader - 2:0\\]
Reserved Setting this bit does not cause any affect to any logic"]
pub type XbaraR = crate :: FieldReader ; # [doc = "Field `xbara` writer - 2:0\\]
Reserved Setting this bit does not cause any affect to any logic"]
pub type XbaraW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_qspi` reader - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppQspiR = crate :: FieldReader ; # [doc = "Field `app_qspi` writer - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppQspiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc_a0` reader - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type TptcA0R = crate :: FieldReader ; # [doc = "Field `tptc_a0` writer - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type TptcA0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc_a1` reader - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type TptcA1R = crate :: FieldReader ; # [doc = "Field `tptc_a1` writer - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type TptcA1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tpcc_a` reader - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type TpccAR = crate :: FieldReader ; # [doc = "Field `tpcc_a` writer - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type TpccAW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_esm` reader - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppEsmR = crate :: FieldReader ; # [doc = "Field `app_esm` writer - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppEsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_rti` reader - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppRtiR = crate :: FieldReader ; # [doc = "Field `app_rti` writer - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppRtiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_wd` reader - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppWdR = crate :: FieldReader ; # [doc = "Field `app_wd` writer - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppWdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_dcc` reader - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppDccR = crate :: FieldReader ; # [doc = "Field `app_dcc` writer - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppDccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_i2c` reader - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppI2cR = crate :: FieldReader ; # [doc = "Field `app_i2c` writer - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppI2cW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Reserved Setting this bit does not cause any affect to any logic"]
# [inline (always)]
pub fn xbara (& self) -> XbaraR { XbaraR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_qspi (& self) -> AppQspiR { AppQspiR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn tpcc_a (& self) -> TpccAR { TpccAR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_esm (& self) -> AppEsmR { AppEsmR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_rti (& self) -> AppRtiR { AppRtiR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_wd (& self) -> AppWdR { AppWdR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_dcc (& self) -> AppDccR { AppDccR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_i2c (& self) -> AppI2cR { AppI2cR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Reserved Setting this bit does not cause any affect to any logic"]
# [inline (always)]
# [must_use]
pub fn xbara (& mut self) -> XbaraW < Ipcfgclkgate0Spec > { XbaraW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_qspi (& mut self) -> AppQspiW < Ipcfgclkgate0Spec > { AppQspiW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < Ipcfgclkgate0Spec > { TptcA0W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < Ipcfgclkgate0Spec > { TptcA1W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn tpcc_a (& mut self) -> TpccAW < Ipcfgclkgate0Spec > { TpccAW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_esm (& mut self) -> AppEsmW < Ipcfgclkgate0Spec > { AppEsmW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_rti (& mut self) -> AppRtiW < Ipcfgclkgate0Spec > { AppRtiW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_wd (& mut self) -> AppWdW < Ipcfgclkgate0Spec > { AppWdW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_dcc (& mut self) -> AppDccW < Ipcfgclkgate0Spec > { AppDccW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_i2c (& mut self) -> AppI2cW < Ipcfgclkgate0Spec > { AppI2cW :: new (self , 27) } } # [doc = "IPCFGCLKGATE0\n\nYou can [`read`](crate::Reg::read) this register and get [`ipcfgclkgate0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipcfgclkgate0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ipcfgclkgate0Spec ; impl crate :: RegisterSpec for Ipcfgclkgate0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipcfgclkgate0::R`](R) reader structure"]
impl crate :: Readable for Ipcfgclkgate0Spec { } # [doc = "`write(|w| ..)` method takes [`ipcfgclkgate0::W`](W) writer structure"]
impl crate :: Writable for Ipcfgclkgate0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPCFGCLKGATE0 to value 0"]
impl crate :: Resettable for Ipcfgclkgate0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPCFGCLKGATE1 (rw) register accessor: IPCFGCLKGATE1\n\nYou can [`read`](crate::Reg::read) this register and get [`ipcfgclkgate1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipcfgclkgate1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipcfgclkgate1`]
module"]
# [doc (alias = "IPCFGCLKGATE1")]
pub type Ipcfgclkgate1 = crate :: Reg < ipcfgclkgate1 :: Ipcfgclkgate1Spec > ; # [doc = "IPCFGCLKGATE1"]
pub mod ipcfgclkgate1 { # [doc = "Register `IPCFGCLKGATE1` reader"]
pub type R = crate :: R < Ipcfgclkgate1Spec > ; # [doc = "Register `IPCFGCLKGATE1` writer"]
pub type W = crate :: W < Ipcfgclkgate1Spec > ; # [doc = "Field `app_uart_0` reader - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppUart0R = crate :: FieldReader ; # [doc = "Field `app_uart_0` writer - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppUart0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_uart_1` reader - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppUart1R = crate :: FieldReader ; # [doc = "Field `app_uart_1` writer - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppUart1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_spi_0` reader - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppSpi0R = crate :: FieldReader ; # [doc = "Field `app_spi_0` writer - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppSpi0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_spi_1` reader - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppSpi1R = crate :: FieldReader ; # [doc = "Field `app_spi_1` writer - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppSpi1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_can` reader - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppCanR = crate :: FieldReader ; # [doc = "Field `app_can` writer - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppCanW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_lin` reader - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppLinR = crate :: FieldReader ; # [doc = "Field `app_lin` writer - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppLinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pwm` reader - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppPwmR = crate :: FieldReader ; # [doc = "Field `app_pwm` writer - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppPwmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_crc` reader - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppCrcR = crate :: FieldReader ; # [doc = "Field `app_crc` writer - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppCrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_ctrl` reader - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppCtrlR = crate :: FieldReader ; # [doc = "Field `app_ctrl` writer - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type AppCtrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res` reader - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type ResR = crate :: FieldReader ; # [doc = "Field `res` writer - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type ResW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_uart_0 (& self) -> AppUart0R { AppUart0R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_uart_1 (& self) -> AppUart1R { AppUart1R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_spi_0 (& self) -> AppSpi0R { AppSpi0R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_spi_1 (& self) -> AppSpi1R { AppSpi1R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_can (& self) -> AppCanR { AppCanR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_lin (& self) -> AppLinR { AppLinR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_pwm (& self) -> AppPwmR { AppPwmR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_crc (& self) -> AppCrcR { AppCrcR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn app_ctrl (& self) -> AppCtrlR { AppCtrlR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn res (& self) -> ResR { ResR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_uart_0 (& mut self) -> AppUart0W < Ipcfgclkgate1Spec > { AppUart0W :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_uart_1 (& mut self) -> AppUart1W < Ipcfgclkgate1Spec > { AppUart1W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_spi_0 (& mut self) -> AppSpi0W < Ipcfgclkgate1Spec > { AppSpi0W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_spi_1 (& mut self) -> AppSpi1W < Ipcfgclkgate1Spec > { AppSpi1W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_can (& mut self) -> AppCanW < Ipcfgclkgate1Spec > { AppCanW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_lin (& mut self) -> AppLinW < Ipcfgclkgate1Spec > { AppLinW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_pwm (& mut self) -> AppPwmW < Ipcfgclkgate1Spec > { AppPwmW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_crc (& mut self) -> AppCrcW < Ipcfgclkgate1Spec > { AppCrcW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn app_ctrl (& mut self) -> AppCtrlW < Ipcfgclkgate1Spec > { AppCtrlW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res (& mut self) -> ResW < Ipcfgclkgate1Spec > { ResW :: new (self , 27) } } # [doc = "IPCFGCLKGATE1\n\nYou can [`read`](crate::Reg::read) this register and get [`ipcfgclkgate1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipcfgclkgate1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ipcfgclkgate1Spec ; impl crate :: RegisterSpec for Ipcfgclkgate1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipcfgclkgate1::R`](R) reader structure"]
impl crate :: Readable for Ipcfgclkgate1Spec { } # [doc = "`write(|w| ..)` method takes [`ipcfgclkgate1::W`](W) writer structure"]
impl crate :: Writable for Ipcfgclkgate1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPCFGCLKGATE1 to value 0"]
impl crate :: Resettable for Ipcfgclkgate1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPCFGCLKGATE2 (rw) register accessor: IPCFGCLKGATE2\n\nYou can [`read`](crate::Reg::read) this register and get [`ipcfgclkgate2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipcfgclkgate2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipcfgclkgate2`]
module"]
# [doc (alias = "IPCFGCLKGATE2")]
pub type Ipcfgclkgate2 = crate :: Reg < ipcfgclkgate2 :: Ipcfgclkgate2Spec > ; # [doc = "IPCFGCLKGATE2"]
pub mod ipcfgclkgate2 { # [doc = "Register `IPCFGCLKGATE2` reader"]
pub type R = crate :: R < Ipcfgclkgate2Spec > ; # [doc = "Register `IPCFGCLKGATE2` writer"]
pub type W = crate :: W < Ipcfgclkgate2Spec > ; # [doc = "Field `gio` reader - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GioR = crate :: FieldReader ; # [doc = "Field `gio` writer - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type GioW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `rs232` reader - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type Rs232R = crate :: FieldReader ; # [doc = "Field `rs232` writer - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type Rs232W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `hwass` reader - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type HwassR = crate :: FieldReader ; # [doc = "Field `hwass` writer - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type HwassW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pcr5` reader - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type Pcr5R = crate :: FieldReader ; # [doc = "Field `pcr5` writer - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type Pcr5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pcr6` reader - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type Pcr6R = crate :: FieldReader ; # [doc = "Field `pcr6` writer - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
pub type Pcr6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn gio (& self) -> GioR { GioR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn rs232 (& self) -> Rs232R { Rs232R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn hwass (& self) -> HwassR { HwassR :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn pcr5 (& self) -> Pcr5R { Pcr5R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
pub fn pcr6 (& self) -> Pcr6R { Pcr6R :: new (((self . bits >> 12) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gio (& mut self) -> GioW < Ipcfgclkgate2Spec > { GioW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn rs232 (& mut self) -> Rs232W < Ipcfgclkgate2Spec > { Rs232W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn hwass (& mut self) -> HwassW < Ipcfgclkgate2Spec > { HwassW :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pcr5 (& mut self) -> Pcr5W < Ipcfgclkgate2Spec > { Pcr5W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock 0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pcr6 (& mut self) -> Pcr6W < Ipcfgclkgate2Spec > { Pcr6W :: new (self , 12) } } # [doc = "IPCFGCLKGATE2\n\nYou can [`read`](crate::Reg::read) this register and get [`ipcfgclkgate2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ipcfgclkgate2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ipcfgclkgate2Spec ; impl crate :: RegisterSpec for Ipcfgclkgate2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ipcfgclkgate2::R`](R) reader structure"]
impl crate :: Readable for Ipcfgclkgate2Spec { } # [doc = "`write(|w| ..)` method takes [`ipcfgclkgate2::W`](W) writer structure"]
impl crate :: Writable for Ipcfgclkgate2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPCFGCLKGATE2 to value 0"]
impl crate :: Resettable for Ipcfgclkgate2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BLOCKRESET0 (rw) register accessor: BLOCKRESET0\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blockreset0`]
module"]
# [doc (alias = "BLOCKRESET0")]
pub type Blockreset0 = crate :: Reg < blockreset0 :: Blockreset0Spec > ; # [doc = "BLOCKRESET0"]
pub mod blockreset0 { # [doc = "Register `BLOCKRESET0` reader"]
pub type R = crate :: R < Blockreset0Spec > ; # [doc = "Register `BLOCKRESET0` writer"]
pub type W = crate :: W < Blockreset0Spec > ; # [doc = "Field `hwass` reader - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type HwassR = crate :: FieldReader ; # [doc = "Field `hwass` writer - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type HwassW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_qspi` reader - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppQspiR = crate :: FieldReader ; # [doc = "Field `app_qspi` writer - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppQspiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc_a0` reader - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TptcA0R = crate :: FieldReader ; # [doc = "Field `tptc_a0` writer - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TptcA0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc_a1` reader - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TptcA1R = crate :: FieldReader ; # [doc = "Field `tptc_a1` writer - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TptcA1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tpcc_a` reader - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TpccAR = crate :: FieldReader ; # [doc = "Field `tpcc_a` writer - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TpccAW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_esm` reader - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppEsmR = crate :: FieldReader ; # [doc = "Field `app_esm` writer - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppEsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_rti` reader - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppRtiR = crate :: FieldReader ; # [doc = "Field `app_rti` writer - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppRtiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_wd` reader - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppWdR = crate :: FieldReader ; # [doc = "Field `app_wd` writer - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppWdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_dcc` reader - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppDccR = crate :: FieldReader ; # [doc = "Field `app_dcc` writer - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppDccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_i2c` reader - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppI2cR = crate :: FieldReader ; # [doc = "Field `app_i2c` writer - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppI2cW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn hwass (& self) -> HwassR { HwassR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_qspi (& self) -> AppQspiR { AppQspiR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn tpcc_a (& self) -> TpccAR { TpccAR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_esm (& self) -> AppEsmR { AppEsmR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_rti (& self) -> AppRtiR { AppRtiR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_wd (& self) -> AppWdR { AppWdR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_dcc (& self) -> AppDccR { AppDccR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_i2c (& self) -> AppI2cR { AppI2cR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn hwass (& mut self) -> HwassW < Blockreset0Spec > { HwassW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_qspi (& mut self) -> AppQspiW < Blockreset0Spec > { AppQspiW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < Blockreset0Spec > { TptcA0W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < Blockreset0Spec > { TptcA1W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn tpcc_a (& mut self) -> TpccAW < Blockreset0Spec > { TpccAW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_esm (& mut self) -> AppEsmW < Blockreset0Spec > { AppEsmW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_rti (& mut self) -> AppRtiW < Blockreset0Spec > { AppRtiW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_wd (& mut self) -> AppWdW < Blockreset0Spec > { AppWdW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_dcc (& mut self) -> AppDccW < Blockreset0Spec > { AppDccW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_i2c (& mut self) -> AppI2cW < Blockreset0Spec > { AppI2cW :: new (self , 27) } } # [doc = "BLOCKRESET0\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Blockreset0Spec ; impl crate :: RegisterSpec for Blockreset0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`blockreset0::R`](R) reader structure"]
impl crate :: Readable for Blockreset0Spec { } # [doc = "`write(|w| ..)` method takes [`blockreset0::W`](W) writer structure"]
impl crate :: Writable for Blockreset0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BLOCKRESET0 to value 0"]
impl crate :: Resettable for Blockreset0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BLOCKRESET1 (rw) register accessor: BLOCKRESET1\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blockreset1`]
module"]
# [doc (alias = "BLOCKRESET1")]
pub type Blockreset1 = crate :: Reg < blockreset1 :: Blockreset1Spec > ; # [doc = "BLOCKRESET1"]
pub mod blockreset1 { # [doc = "Register `BLOCKRESET1` reader"]
pub type R = crate :: R < Blockreset1Spec > ; # [doc = "Register `BLOCKRESET1` writer"]
pub type W = crate :: W < Blockreset1Spec > ; # [doc = "Field `app_uart_0` reader - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppUart0R = crate :: FieldReader ; # [doc = "Field `app_uart_0` writer - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppUart0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_uart_1` reader - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppUart1R = crate :: FieldReader ; # [doc = "Field `app_uart_1` writer - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppUart1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_spi_0` reader - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppSpi0R = crate :: FieldReader ; # [doc = "Field `app_spi_0` writer - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppSpi0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_spi_1` reader - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppSpi1R = crate :: FieldReader ; # [doc = "Field `app_spi_1` writer - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppSpi1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_can` reader - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppCanR = crate :: FieldReader ; # [doc = "Field `app_can` writer - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppCanW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_lin` reader - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppLinR = crate :: FieldReader ; # [doc = "Field `app_lin` writer - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppLinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pwm` reader - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppPwmR = crate :: FieldReader ; # [doc = "Field `app_pwm` writer - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppPwmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_crc` reader - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppCrcR = crate :: FieldReader ; # [doc = "Field `app_crc` writer - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppCrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_ctrl` reader - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppCtrlR = crate :: FieldReader ; # [doc = "Field `app_ctrl` writer - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type AppCtrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `topss` reader - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TopssR = crate :: FieldReader ; # [doc = "Field `topss` writer - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type TopssW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_uart_0 (& self) -> AppUart0R { AppUart0R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_uart_1 (& self) -> AppUart1R { AppUart1R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_spi_0 (& self) -> AppSpi0R { AppSpi0R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_spi_1 (& self) -> AppSpi1R { AppSpi1R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_can (& self) -> AppCanR { AppCanR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_lin (& self) -> AppLinR { AppLinR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_pwm (& self) -> AppPwmR { AppPwmR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_crc (& self) -> AppCrcR { AppCrcR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn app_ctrl (& self) -> AppCtrlR { AppCtrlR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn topss (& self) -> TopssR { TopssR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_uart_0 (& mut self) -> AppUart0W < Blockreset1Spec > { AppUart0W :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_uart_1 (& mut self) -> AppUart1W < Blockreset1Spec > { AppUart1W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_spi_0 (& mut self) -> AppSpi0W < Blockreset1Spec > { AppSpi0W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_spi_1 (& mut self) -> AppSpi1W < Blockreset1Spec > { AppSpi1W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_can (& mut self) -> AppCanW < Blockreset1Spec > { AppCanW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_lin (& mut self) -> AppLinW < Blockreset1Spec > { AppLinW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_pwm (& mut self) -> AppPwmW < Blockreset1Spec > { AppPwmW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_crc (& mut self) -> AppCrcW < Blockreset1Spec > { AppCrcW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn app_ctrl (& mut self) -> AppCtrlW < Blockreset1Spec > { AppCtrlW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn topss (& mut self) -> TopssW < Blockreset1Spec > { TopssW :: new (self , 27) } } # [doc = "BLOCKRESET1\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Blockreset1Spec ; impl crate :: RegisterSpec for Blockreset1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`blockreset1::R`](R) reader structure"]
impl crate :: Readable for Blockreset1Spec { } # [doc = "`write(|w| ..)` method takes [`blockreset1::W`](W) writer structure"]
impl crate :: Writable for Blockreset1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BLOCKRESET1 to value 0"]
impl crate :: Resettable for Blockreset1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BLOCKRESET2 (rw) register accessor: BLOCKRESET2\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blockreset2`]
module"]
# [doc (alias = "BLOCKRESET2")]
pub type Blockreset2 = crate :: Reg < blockreset2 :: Blockreset2Spec > ; # [doc = "BLOCKRESET2"]
pub mod blockreset2 { # [doc = "Register `BLOCKRESET2` reader"]
pub type R = crate :: R < Blockreset2Spec > ; # [doc = "Register `BLOCKRESET2` writer"]
pub type W = crate :: W < Blockreset2Spec > ; # [doc = "Field `rs232` reader - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type Rs232R = crate :: FieldReader ; # [doc = "Field `rs232` writer - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type Rs232W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `frc` reader - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type FrcR = crate :: FieldReader ; # [doc = "Field `frc` writer - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
pub type FrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn rs232 (& self) -> Rs232R { Rs232R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
pub fn frc (& self) -> FrcR { FrcR :: new (((self . bits >> 6) & 7) as u8) } } impl W { # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn rs232 (& mut self) -> Rs232W < Blockreset2Spec > { Rs232W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset 0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn frc (& mut self) -> FrcW < Blockreset2Spec > { FrcW :: new (self , 6) } } # [doc = "BLOCKRESET2\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Blockreset2Spec ; impl crate :: RegisterSpec for Blockreset2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`blockreset2::R`](R) reader structure"]
impl crate :: Readable for Blockreset2Spec { } # [doc = "`write(|w| ..)` method takes [`blockreset2::W`](W) writer structure"]
impl crate :: Writable for Blockreset2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BLOCKRESET2 to value 0"]
impl crate :: Resettable for Blockreset2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLATFORM_SIGNATURE (rw) register accessor: PLATFORM_SIGNATURE\n\nYou can [`read`](crate::Reg::read) this register and get [`platform_signature::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`platform_signature::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@platform_signature`]
module"]
# [doc (alias = "PLATFORM_SIGNATURE")]
pub type PlatformSignature = crate :: Reg < platform_signature :: PlatformSignatureSpec > ; # [doc = "PLATFORM_SIGNATURE"]
pub mod platform_signature { # [doc = "Register `PLATFORM_SIGNATURE` reader"]
pub type R = crate :: R < PlatformSignatureSpec > ; # [doc = "Register `PLATFORM_SIGNATURE` writer"]
pub type W = crate :: W < PlatformSignatureSpec > ; # [doc = "Field `signature` reader - 31:0\\]
Platform signature to identify the platform"]
pub type SignatureR = crate :: FieldReader < u32 > ; # [doc = "Field `signature` writer - 31:0\\]
Platform signature to identify the platform"]
pub type SignatureW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Platform signature to identify the platform"]
# [inline (always)]
pub fn signature (& self) -> SignatureR { SignatureR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Platform signature to identify the platform"]
# [inline (always)]
# [must_use]
pub fn signature (& mut self) -> SignatureW < PlatformSignatureSpec > { SignatureW :: new (self , 0) } } # [doc = "PLATFORM_SIGNATURE\n\nYou can [`read`](crate::Reg::read) this register and get [`platform_signature::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`platform_signature::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlatformSignatureSpec ; impl crate :: RegisterSpec for PlatformSignatureSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`platform_signature::R`](R) reader structure"]
impl crate :: Readable for PlatformSignatureSpec { } # [doc = "`write(|w| ..)` method takes [`platform_signature::W`](W) writer structure"]
impl crate :: Writable for PlatformSignatureSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLATFORM_SIGNATURE to value 0"]
impl crate :: Resettable for PlatformSignatureSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "POWERMODE (rw) register accessor: POWERMODE\n\nYou can [`read`](crate::Reg::read) this register and get [`powermode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`powermode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@powermode`]
module"]
# [doc (alias = "POWERMODE")]
pub type Powermode = crate :: Reg < powermode :: PowermodeSpec > ; # [doc = "POWERMODE"]
pub mod powermode { # [doc = "Register `POWERMODE` reader"]
pub type R = crate :: R < PowermodeSpec > ; # [doc = "Register `POWERMODE` writer"]
pub type W = crate :: W < PowermodeSpec > ; # [doc = "Field `SLEEP` reader - 0:0\\]
0x0 : CM4 CORE SLEEP 0x1 : DEVICE SLEEP"]
pub type SleepR = crate :: BitReader ; # [doc = "Field `SLEEP` writer - 0:0\\]
0x0 : CM4 CORE SLEEP 0x1 : DEVICE SLEEP"]
pub type SleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DEEPSLEEP` reader - 1:1\\]
0x0 : CM4 CORE DEEP SLEEP 0x1 : DEVICE DEEP SLEEP"]
pub type DeepsleepR = crate :: BitReader ; # [doc = "Field `DEEPSLEEP` writer - 1:1\\]
0x0 : CM4 CORE DEEP SLEEP 0x1 : DEVICE DEEP SLEEP"]
pub type DeepsleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM3_SLEEP_STATUS` reader - 2:2\\]
CM3 Core Sleep Status"]
pub type Cm3SleepStatusR = crate :: BitReader ; # [doc = "Field `CM3_SLEEP_STATUS` writer - 2:2\\]
CM3 Core Sleep Status"]
pub type Cm3SleepStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CM3_DEEPSLEEP_STATUS` reader - 3:3\\]
CM3 Core Deep Sleep Status"]
pub type Cm3DeepsleepStatusR = crate :: BitReader ; # [doc = "Field `CM3_DEEPSLEEP_STATUS` writer - 3:3\\]
CM3 Core Deep Sleep Status"]
pub type Cm3DeepsleepStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
0x0 : CM4 CORE SLEEP 0x1 : DEVICE SLEEP"]
# [inline (always)]
pub fn sleep (& self) -> SleepR { SleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
0x0 : CM4 CORE DEEP SLEEP 0x1 : DEVICE DEEP SLEEP"]
# [inline (always)]
pub fn deepsleep (& self) -> DeepsleepR { DeepsleepR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
CM3 Core Sleep Status"]
# [inline (always)]
pub fn cm3_sleep_status (& self) -> Cm3SleepStatusR { Cm3SleepStatusR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
CM3 Core Deep Sleep Status"]
# [inline (always)]
pub fn cm3_deepsleep_status (& self) -> Cm3DeepsleepStatusR { Cm3DeepsleepStatusR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
0x0 : CM4 CORE SLEEP 0x1 : DEVICE SLEEP"]
# [inline (always)]
# [must_use]
pub fn sleep (& mut self) -> SleepW < PowermodeSpec > { SleepW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
0x0 : CM4 CORE DEEP SLEEP 0x1 : DEVICE DEEP SLEEP"]
# [inline (always)]
# [must_use]
pub fn deepsleep (& mut self) -> DeepsleepW < PowermodeSpec > { DeepsleepW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
CM3 Core Sleep Status"]
# [inline (always)]
# [must_use]
pub fn cm3_sleep_status (& mut self) -> Cm3SleepStatusW < PowermodeSpec > { Cm3SleepStatusW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
CM3 Core Deep Sleep Status"]
# [inline (always)]
# [must_use]
pub fn cm3_deepsleep_status (& mut self) -> Cm3DeepsleepStatusW < PowermodeSpec > { Cm3DeepsleepStatusW :: new (self , 3) } } # [doc = "POWERMODE\n\nYou can [`read`](crate::Reg::read) this register and get [`powermode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`powermode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PowermodeSpec ; impl crate :: RegisterSpec for PowermodeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`powermode::R`](R) reader structure"]
impl crate :: Readable for PowermodeSpec { } # [doc = "`write(|w| ..)` method takes [`powermode::W`](W) writer structure"]
impl crate :: Writable for PowermodeSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets POWERMODE to value 0"]
impl crate :: Resettable for PowermodeSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RST_WFICHECK (rw) register accessor: RST_WFICHECK\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_wficheck::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_wficheck::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_wficheck`]
module"]
# [doc (alias = "RST_WFICHECK")]
pub type RstWficheck = crate :: Reg < rst_wficheck :: RstWficheckSpec > ; # [doc = "RST_WFICHECK"]
pub mod rst_wficheck { # [doc = "Register `RST_WFICHECK` reader"]
pub type R = crate :: R < RstWficheckSpec > ; # [doc = "Register `RST_WFICHECK` writer"]
pub type W = crate :: W < RstWficheckSpec > ; # [doc = "Field `cpu` reader - 2:0\\]
Writing '000' will disable check for WFI before local reset assertion of app cpu"]
pub type CpuR = crate :: FieldReader ; # [doc = "Field `cpu` writer - 2:0\\]
Writing '000' will disable check for WFI before local reset assertion of app cpu"]
pub type CpuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing '000' will disable check for WFI before local reset assertion of app cpu"]
# [inline (always)]
pub fn cpu (& self) -> CpuR { CpuR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing '000' will disable check for WFI before local reset assertion of app cpu"]
# [inline (always)]
# [must_use]
pub fn cpu (& mut self) -> CpuW < RstWficheckSpec > { CpuW :: new (self , 0) } } # [doc = "RST_WFICHECK\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_wficheck::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_wficheck::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstWficheckSpec ; impl crate :: RegisterSpec for RstWficheckSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rst_wficheck::R`](R) reader structure"]
impl crate :: Readable for RstWficheckSpec { } # [doc = "`write(|w| ..)` method takes [`rst_wficheck::W`](W) writer structure"]
impl crate :: Writable for RstWficheckSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RST_WFICHECK to value 0"]
impl crate :: Resettable for RstWficheckSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RST_ASSERTDLY (rw) register accessor: RST_ASSERTDLY\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_assertdly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_assertdly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_assertdly`]
module"]
# [doc (alias = "RST_ASSERTDLY")]
pub type RstAssertdly = crate :: Reg < rst_assertdly :: RstAssertdlySpec > ; # [doc = "RST_ASSERTDLY"]
pub mod rst_assertdly { # [doc = "Register `RST_ASSERTDLY` reader"]
pub type R = crate :: R < RstAssertdlySpec > ; # [doc = "Register `RST_ASSERTDLY` writer"]
pub type W = crate :: W < RstAssertdlySpec > ; # [doc = "Field `common` reader - 7:0\\]
Value decides number of cycles reset should be asserted for cpu"]
pub type CommonR = crate :: FieldReader ; # [doc = "Field `common` writer - 7:0\\]
Value decides number of cycles reset should be asserted for cpu"]
pub type CommonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Value decides number of cycles reset should be asserted for cpu"]
# [inline (always)]
pub fn common (& self) -> CommonR { CommonR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Value decides number of cycles reset should be asserted for cpu"]
# [inline (always)]
# [must_use]
pub fn common (& mut self) -> CommonW < RstAssertdlySpec > { CommonW :: new (self , 0) } } # [doc = "RST_ASSERTDLY\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_assertdly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_assertdly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstAssertdlySpec ; impl crate :: RegisterSpec for RstAssertdlySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rst_assertdly::R`](R) reader structure"]
impl crate :: Readable for RstAssertdlySpec { } # [doc = "`write(|w| ..)` method takes [`rst_assertdly::W`](W) writer structure"]
impl crate :: Writable for RstAssertdlySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RST_ASSERTDLY to value 0"]
impl crate :: Resettable for RstAssertdlySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RST2ASSERTDLY (rw) register accessor: RST2ASSERTDLY\n\nYou can [`read`](crate::Reg::read) this register and get [`rst2assertdly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst2assertdly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst2assertdly`]
module"]
# [doc (alias = "RST2ASSERTDLY")]
pub type Rst2assertdly = crate :: Reg < rst2assertdly :: Rst2assertdlySpec > ; # [doc = "RST2ASSERTDLY"]
pub mod rst2assertdly { # [doc = "Register `RST2ASSERTDLY` reader"]
pub type R = crate :: R < Rst2assertdlySpec > ; # [doc = "Register `RST2ASSERTDLY` writer"]
pub type W = crate :: W < Rst2assertdlySpec > ; # [doc = "Field `cpu` reader - 15:8\\]
Value decides number of cycles to be held before asserting reset for app cpu"]
pub type CpuR = crate :: FieldReader ; # [doc = "Field `cpu` writer - 15:8\\]
Value decides number of cycles to be held before asserting reset for app cpu"]
pub type CpuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 8:15 - 15:8\\]
Value decides number of cycles to be held before asserting reset for app cpu"]
# [inline (always)]
pub fn cpu (& self) -> CpuR { CpuR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { # [doc = "Bits 8:15 - 15:8\\]
Value decides number of cycles to be held before asserting reset for app cpu"]
# [inline (always)]
# [must_use]
pub fn cpu (& mut self) -> CpuW < Rst2assertdlySpec > { CpuW :: new (self , 8) } } # [doc = "RST2ASSERTDLY\n\nYou can [`read`](crate::Reg::read) this register and get [`rst2assertdly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst2assertdly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rst2assertdlySpec ; impl crate :: RegisterSpec for Rst2assertdlySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rst2assertdly::R`](R) reader structure"]
impl crate :: Readable for Rst2assertdlySpec { } # [doc = "`write(|w| ..)` method takes [`rst2assertdly::W`](W) writer structure"]
impl crate :: Writable for Rst2assertdlySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RST2ASSERTDLY to value 0"]
impl crate :: Resettable for Rst2assertdlySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RST_FSM_TRIG (rw) register accessor: RST_FSM_TRIG\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_fsm_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_fsm_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_fsm_trig`]
module"]
# [doc (alias = "RST_FSM_TRIG")]
pub type RstFsmTrig = crate :: Reg < rst_fsm_trig :: RstFsmTrigSpec > ; # [doc = "RST_FSM_TRIG"]
pub mod rst_fsm_trig { # [doc = "Register `RST_FSM_TRIG` reader"]
pub type R = crate :: R < RstFsmTrigSpec > ; # [doc = "Register `RST_FSM_TRIG` writer"]
pub type W = crate :: W < RstFsmTrigSpec > ; # [doc = "Field `cpu` reader - 2:0\\]
FSM Reset Trigger"]
pub type CpuR = crate :: FieldReader ; # [doc = "Field `cpu` writer - 2:0\\]
FSM Reset Trigger"]
pub type CpuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
FSM Reset Trigger"]
# [inline (always)]
pub fn cpu (& self) -> CpuR { CpuR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
FSM Reset Trigger"]
# [inline (always)]
# [must_use]
pub fn cpu (& mut self) -> CpuW < RstFsmTrigSpec > { CpuW :: new (self , 0) } } # [doc = "RST_FSM_TRIG\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_fsm_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_fsm_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstFsmTrigSpec ; impl crate :: RegisterSpec for RstFsmTrigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rst_fsm_trig::R`](R) reader structure"]
impl crate :: Readable for RstFsmTrigSpec { } # [doc = "`write(|w| ..)` method takes [`rst_fsm_trig::W`](W) writer structure"]
impl crate :: Writable for RstFsmTrigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RST_FSM_TRIG to value 0"]
impl crate :: Resettable for RstFsmTrigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RST_CAUSE (rw) register accessor: RST_CAUSE\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_cause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_cause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_cause`]
module"]
# [doc (alias = "RST_CAUSE")]
pub type RstCause = crate :: Reg < rst_cause :: RstCauseSpec > ; # [doc = "RST_CAUSE"]
pub mod rst_cause { # [doc = "Register `RST_CAUSE` reader"]
pub type R = crate :: R < RstCauseSpec > ; # [doc = "Register `RST_CAUSE` writer"]
pub type W = crate :: W < RstCauseSpec > ; # [doc = "Field `common` reader - 7:0\\]
Reset cause register for APP CPU 0x00 - All cleared 0x01 - Power On Reset (PoR) 0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset) 0x04 - STC RESET 0x08 - Reserved 0x10 - CPU Only Reset triggered by writing to LPRADAR:APP_RCM:RST_FSM_TRIG&lt;RST_FSM_TRIG_CPU> (self triggered CPU reset during MEMSWAP/ECLIPSE mode to wait for WFI to assert the reset to CPU) 0x20 - Core Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or LPRADAR:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE 0x40 - Reserved"]
pub type CommonR = crate :: FieldReader ; # [doc = "Field `common` writer - 7:0\\]
Reset cause register for APP CPU 0x00 - All cleared 0x01 - Power On Reset (PoR) 0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset) 0x04 - STC RESET 0x08 - Reserved 0x10 - CPU Only Reset triggered by writing to LPRADAR:APP_RCM:RST_FSM_TRIG&lt;RST_FSM_TRIG_CPU> (self triggered CPU reset during MEMSWAP/ECLIPSE mode to wait for WFI to assert the reset to CPU) 0x20 - Core Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or LPRADAR:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE 0x40 - Reserved"]
pub type CommonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Reset cause register for APP CPU 0x00 - All cleared 0x01 - Power On Reset (PoR) 0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset) 0x04 - STC RESET 0x08 - Reserved 0x10 - CPU Only Reset triggered by writing to LPRADAR:APP_RCM:RST_FSM_TRIG&lt;RST_FSM_TRIG_CPU> (self triggered CPU reset during MEMSWAP/ECLIPSE mode to wait for WFI to assert the reset to CPU) 0x20 - Core Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or LPRADAR:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE 0x40 - Reserved"]
# [inline (always)]
pub fn common (& self) -> CommonR { CommonR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Reset cause register for APP CPU 0x00 - All cleared 0x01 - Power On Reset (PoR) 0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset) 0x04 - STC RESET 0x08 - Reserved 0x10 - CPU Only Reset triggered by writing to LPRADAR:APP_RCM:RST_FSM_TRIG&lt;RST_FSM_TRIG_CPU> (self triggered CPU reset during MEMSWAP/ECLIPSE mode to wait for WFI to assert the reset to CPU) 0x20 - Core Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or LPRADAR:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE 0x40 - Reserved"]
# [inline (always)]
# [must_use]
pub fn common (& mut self) -> CommonW < RstCauseSpec > { CommonW :: new (self , 0) } } # [doc = "RST_CAUSE\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_cause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_cause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstCauseSpec ; impl crate :: RegisterSpec for RstCauseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rst_cause::R`](R) reader structure"]
impl crate :: Readable for RstCauseSpec { } # [doc = "`write(|w| ..)` method takes [`rst_cause::W`](W) writer structure"]
impl crate :: Writable for RstCauseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RST_CAUSE to value 0"]
impl crate :: Resettable for RstCauseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RST_CAUSE_CLR (rw) register accessor: RST_CAUSE_CLR\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_cause_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_cause_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_cause_clr`]
module"]
# [doc (alias = "RST_CAUSE_CLR")]
pub type RstCauseClr = crate :: Reg < rst_cause_clr :: RstCauseClrSpec > ; # [doc = "RST_CAUSE_CLR"]
pub mod rst_cause_clr { # [doc = "Register `RST_CAUSE_CLR` reader"]
pub type R = crate :: R < RstCauseClrSpec > ; # [doc = "Register `RST_CAUSE_CLR` writer"]
pub type W = crate :: W < RstCauseClrSpec > ; # [doc = "Field `cpu` reader - 2:0\\]
Writing '111' will clear the RST_CAUSE register"]
pub type CpuR = crate :: FieldReader ; # [doc = "Field `cpu` writer - 2:0\\]
Writing '111' will clear the RST_CAUSE register"]
pub type CpuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing '111' will clear the RST_CAUSE register"]
# [inline (always)]
pub fn cpu (& self) -> CpuR { CpuR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing '111' will clear the RST_CAUSE register"]
# [inline (always)]
# [must_use]
pub fn cpu (& mut self) -> CpuW < RstCauseClrSpec > { CpuW :: new (self , 0) } } # [doc = "RST_CAUSE_CLR\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_cause_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_cause_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstCauseClrSpec ; impl crate :: RegisterSpec for RstCauseClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rst_cause_clr::R`](R) reader structure"]
impl crate :: Readable for RstCauseClrSpec { } # [doc = "`write(|w| ..)` method takes [`rst_cause_clr::W`](W) writer structure"]
impl crate :: Writable for RstCauseClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RST_CAUSE_CLR to value 0"]
impl crate :: Resettable for RstCauseClrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XTALCLK_CLK_GATE (rw) register accessor: XTALCLK_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`xtalclk_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtalclk_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xtalclk_clk_gate`]
module"]
# [doc (alias = "XTALCLK_CLK_GATE")]
pub type XtalclkClkGate = crate :: Reg < xtalclk_clk_gate :: XtalclkClkGateSpec > ; # [doc = "XTALCLK_CLK_GATE"]
pub mod xtalclk_clk_gate { # [doc = "Register `XTALCLK_CLK_GATE` reader"]
pub type R = crate :: R < XtalclkClkGateSpec > ; # [doc = "Register `XTALCLK_CLK_GATE` writer"]
pub type W = crate :: W < XtalclkClkGateSpec > ; # [doc = "Field `XTALCLK_CLK_GATE` reader - 2:0\\]
RESERVED"]
pub type XtalclkClkGateR = crate :: FieldReader ; # [doc = "Field `XTALCLK_CLK_GATE` writer - 2:0\\]
RESERVED"]
pub type XtalclkClkGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
RESERVED"]
# [inline (always)]
pub fn xtalclk_clk_gate (& self) -> XtalclkClkGateR { XtalclkClkGateR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn xtalclk_clk_gate (& mut self) -> XtalclkClkGateW < XtalclkClkGateSpec > { XtalclkClkGateW :: new (self , 0) } } # [doc = "XTALCLK_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`xtalclk_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtalclk_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XtalclkClkGateSpec ; impl crate :: RegisterSpec for XtalclkClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xtalclk_clk_gate::R`](R) reader structure"]
impl crate :: Readable for XtalclkClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`xtalclk_clk_gate::W`](W) writer structure"]
impl crate :: Writable for XtalclkClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XTALCLK_CLK_GATE to value 0"]
impl crate :: Resettable for XtalclkClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XTALCLKX2_CLK_GATE (rw) register accessor: XTALCLKX2_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`xtalclkx2_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtalclkx2_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xtalclkx2_clk_gate`]
module"]
# [doc (alias = "XTALCLKX2_CLK_GATE")]
pub type Xtalclkx2ClkGate = crate :: Reg < xtalclkx2_clk_gate :: Xtalclkx2ClkGateSpec > ; # [doc = "XTALCLKX2_CLK_GATE"]
pub mod xtalclkx2_clk_gate { # [doc = "Register `XTALCLKX2_CLK_GATE` reader"]
pub type R = crate :: R < Xtalclkx2ClkGateSpec > ; # [doc = "Register `XTALCLKX2_CLK_GATE` writer"]
pub type W = crate :: W < Xtalclkx2ClkGateSpec > ; # [doc = "Field `XTALCLKX2_CLK_GATE` reader - 2:0\\]
Writing 3'b111 will gate the XTALX2 clock.Writing 3'b000 will ungate the clock."]
pub type Xtalclkx2ClkGateR = crate :: FieldReader ; # [doc = "Field `XTALCLKX2_CLK_GATE` writer - 2:0\\]
Writing 3'b111 will gate the XTALX2 clock.Writing 3'b000 will ungate the clock."]
pub type Xtalclkx2ClkGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the XTALX2 clock.Writing 3'b000 will ungate the clock."]
# [inline (always)]
pub fn xtalclkx2_clk_gate (& self) -> Xtalclkx2ClkGateR { Xtalclkx2ClkGateR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the XTALX2 clock.Writing 3'b000 will ungate the clock."]
# [inline (always)]
# [must_use]
pub fn xtalclkx2_clk_gate (& mut self) -> Xtalclkx2ClkGateW < Xtalclkx2ClkGateSpec > { Xtalclkx2ClkGateW :: new (self , 0) } } # [doc = "XTALCLKX2_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`xtalclkx2_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtalclkx2_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Xtalclkx2ClkGateSpec ; impl crate :: RegisterSpec for Xtalclkx2ClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xtalclkx2_clk_gate::R`](R) reader structure"]
impl crate :: Readable for Xtalclkx2ClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`xtalclkx2_clk_gate::W`](W) writer structure"]
impl crate :: Writable for Xtalclkx2ClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XTALCLKX2_CLK_GATE to value 0"]
impl crate :: Resettable for Xtalclkx2ClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APLLDIV2_CLK_GATE (rw) register accessor: APLLDIV2_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`aplldiv2_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aplldiv2_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aplldiv2_clk_gate`]
module"]
# [doc (alias = "APLLDIV2_CLK_GATE")]
pub type Aplldiv2ClkGate = crate :: Reg < aplldiv2_clk_gate :: Aplldiv2ClkGateSpec > ; # [doc = "APLLDIV2_CLK_GATE"]
pub mod aplldiv2_clk_gate { # [doc = "Register `APLLDIV2_CLK_GATE` reader"]
pub type R = crate :: R < Aplldiv2ClkGateSpec > ; # [doc = "Register `APLLDIV2_CLK_GATE` writer"]
pub type W = crate :: W < Aplldiv2ClkGateSpec > ; # [doc = "Field `APLLDIV2_CLK_GATE` reader - 2:0\\]
Writing 3'b111 will gate the APLL/2clock to EDCC.Writing 3'b000 will ungate the clock."]
pub type Aplldiv2ClkGateR = crate :: FieldReader ; # [doc = "Field `APLLDIV2_CLK_GATE` writer - 2:0\\]
Writing 3'b111 will gate the APLL/2clock to EDCC.Writing 3'b000 will ungate the clock."]
pub type Aplldiv2ClkGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the APLL/2clock to EDCC.Writing 3'b000 will ungate the clock."]
# [inline (always)]
pub fn aplldiv2_clk_gate (& self) -> Aplldiv2ClkGateR { Aplldiv2ClkGateR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the APLL/2clock to EDCC.Writing 3'b000 will ungate the clock."]
# [inline (always)]
# [must_use]
pub fn aplldiv2_clk_gate (& mut self) -> Aplldiv2ClkGateW < Aplldiv2ClkGateSpec > { Aplldiv2ClkGateW :: new (self , 0) } } # [doc = "APLLDIV2_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`aplldiv2_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aplldiv2_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Aplldiv2ClkGateSpec ; impl crate :: RegisterSpec for Aplldiv2ClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aplldiv2_clk_gate::R`](R) reader structure"]
impl crate :: Readable for Aplldiv2ClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`aplldiv2_clk_gate::W`](W) writer structure"]
impl crate :: Writable for Aplldiv2ClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APLLDIV2_CLK_GATE to value 0"]
impl crate :: Resettable for Aplldiv2ClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFT_APPSS_LSTC_CLK_GATE (rw) register accessor: DFT_APPSS_LSTC_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_appss_lstc_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_appss_lstc_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_appss_lstc_clk_gate`]
module"]
# [doc (alias = "DFT_APPSS_LSTC_CLK_GATE")]
pub type DftAppssLstcClkGate = crate :: Reg < dft_appss_lstc_clk_gate :: DftAppssLstcClkGateSpec > ; # [doc = "DFT_APPSS_LSTC_CLK_GATE"]
pub mod dft_appss_lstc_clk_gate { # [doc = "Register `DFT_APPSS_LSTC_CLK_GATE` reader"]
pub type R = crate :: R < DftAppssLstcClkGateSpec > ; # [doc = "Register `DFT_APPSS_LSTC_CLK_GATE` writer"]
pub type W = crate :: W < DftAppssLstcClkGateSpec > ; # [doc = "Field `DFT_APPSS_LSTC_CLK_GATE` reader - 2:0\\]
Writing 3'b111 will gate the clock to LSTC.Writing 3'b000 will ungate the clock."]
pub type DftAppssLstcClkGateR = crate :: FieldReader ; # [doc = "Field `DFT_APPSS_LSTC_CLK_GATE` writer - 2:0\\]
Writing 3'b111 will gate the clock to LSTC.Writing 3'b000 will ungate the clock."]
pub type DftAppssLstcClkGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the clock to LSTC.Writing 3'b000 will ungate the clock."]
# [inline (always)]
pub fn dft_appss_lstc_clk_gate (& self) -> DftAppssLstcClkGateR { DftAppssLstcClkGateR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the clock to LSTC.Writing 3'b000 will ungate the clock."]
# [inline (always)]
# [must_use]
pub fn dft_appss_lstc_clk_gate (& mut self) -> DftAppssLstcClkGateW < DftAppssLstcClkGateSpec > { DftAppssLstcClkGateW :: new (self , 0) } } # [doc = "DFT_APPSS_LSTC_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_appss_lstc_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_appss_lstc_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftAppssLstcClkGateSpec ; impl crate :: RegisterSpec for DftAppssLstcClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_appss_lstc_clk_gate::R`](R) reader structure"]
impl crate :: Readable for DftAppssLstcClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`dft_appss_lstc_clk_gate::W`](W) writer structure"]
impl crate :: Writable for DftAppssLstcClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFT_APPSS_LSTC_CLK_GATE to value 0"]
impl crate :: Resettable for DftAppssLstcClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DFT_APPSS_LSTC_VBUSP_CLK_GATE (rw) register accessor: DFT_APPSS_LSTC_VBUSP_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_appss_lstc_vbusp_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_appss_lstc_vbusp_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_appss_lstc_vbusp_clk_gate`]
module"]
# [doc (alias = "DFT_APPSS_LSTC_VBUSP_CLK_GATE")]
pub type DftAppssLstcVbuspClkGate = crate :: Reg < dft_appss_lstc_vbusp_clk_gate :: DftAppssLstcVbuspClkGateSpec > ; # [doc = "DFT_APPSS_LSTC_VBUSP_CLK_GATE"]
pub mod dft_appss_lstc_vbusp_clk_gate { # [doc = "Register `DFT_APPSS_LSTC_VBUSP_CLK_GATE` reader"]
pub type R = crate :: R < DftAppssLstcVbuspClkGateSpec > ; # [doc = "Register `DFT_APPSS_LSTC_VBUSP_CLK_GATE` writer"]
pub type W = crate :: W < DftAppssLstcVbuspClkGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 : Gate clock to LSTC VBUSP 3'b111 : Ungate Clock to LSTC VBUSP"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 : Gate clock to LSTC VBUSP 3'b111 : Ungate Clock to LSTC VBUSP"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Gate clock to LSTC VBUSP 3'b111 : Ungate Clock to LSTC VBUSP"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Gate clock to LSTC VBUSP 3'b111 : Ungate Clock to LSTC VBUSP"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < DftAppssLstcVbuspClkGateSpec > { EnableW :: new (self , 0) } } # [doc = "DFT_APPSS_LSTC_VBUSP_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_appss_lstc_vbusp_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_appss_lstc_vbusp_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftAppssLstcVbuspClkGateSpec ; impl crate :: RegisterSpec for DftAppssLstcVbuspClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_appss_lstc_vbusp_clk_gate::R`](R) reader structure"]
impl crate :: Readable for DftAppssLstcVbuspClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`dft_appss_lstc_vbusp_clk_gate::W`](W) writer structure"]
impl crate :: Writable for DftAppssLstcVbuspClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DFT_APPSS_LSTC_VBUSP_CLK_GATE to value 0"]
impl crate :: Resettable for DftAppssLstcVbuspClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_ROM_CLOCK_GATE (rw) register accessor: APP_ROM_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_rom_clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_rom_clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_rom_clock_gate`]
module"]
# [doc (alias = "APP_ROM_CLOCK_GATE")]
pub type AppRomClockGate = crate :: Reg < app_rom_clock_gate :: AppRomClockGateSpec > ; # [doc = "APP_ROM_CLOCK_GATE"]
pub mod app_rom_clock_gate { # [doc = "Register `APP_ROM_CLOCK_GATE` reader"]
pub type R = crate :: R < AppRomClockGateSpec > ; # [doc = "Register `APP_ROM_CLOCK_GATE` writer"]
pub type W = crate :: W < AppRomClockGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 : Ungate clock to APP ROM 3'b111 : Gate Clock to APP ROM"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 : Ungate clock to APP ROM 3'b111 : Gate Clock to APP ROM"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP ROM 3'b111 : Gate Clock to APP ROM"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP ROM 3'b111 : Gate Clock to APP ROM"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppRomClockGateSpec > { EnableW :: new (self , 0) } } # [doc = "APP_ROM_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_rom_clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_rom_clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppRomClockGateSpec ; impl crate :: RegisterSpec for AppRomClockGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_rom_clock_gate::R`](R) reader structure"]
impl crate :: Readable for AppRomClockGateSpec { } # [doc = "`write(|w| ..)` method takes [`app_rom_clock_gate::W`](W) writer structure"]
impl crate :: Writable for AppRomClockGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_ROM_CLOCK_GATE to value 0"]
impl crate :: Resettable for AppRomClockGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_RAM1_CLOCK_GATE (rw) register accessor: APP_RAM1_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ram1_clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ram1_clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_ram1_clock_gate`]
module"]
# [doc (alias = "APP_RAM1_CLOCK_GATE")]
pub type AppRam1ClockGate = crate :: Reg < app_ram1_clock_gate :: AppRam1ClockGateSpec > ; # [doc = "APP_RAM1_CLOCK_GATE"]
pub mod app_ram1_clock_gate { # [doc = "Register `APP_RAM1_CLOCK_GATE` reader"]
pub type R = crate :: R < AppRam1ClockGateSpec > ; # [doc = "Register `APP_RAM1_CLOCK_GATE` writer"]
pub type W = crate :: W < AppRam1ClockGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 : Ungate clock to APP RAM1 3'b111 : Gate Clock to APP_RAM1"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 : Ungate clock to APP RAM1 3'b111 : Gate Clock to APP_RAM1"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP RAM1 3'b111 : Gate Clock to APP_RAM1"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP RAM1 3'b111 : Gate Clock to APP_RAM1"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppRam1ClockGateSpec > { EnableW :: new (self , 0) } } # [doc = "APP_RAM1_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ram1_clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ram1_clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppRam1ClockGateSpec ; impl crate :: RegisterSpec for AppRam1ClockGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_ram1_clock_gate::R`](R) reader structure"]
impl crate :: Readable for AppRam1ClockGateSpec { } # [doc = "`write(|w| ..)` method takes [`app_ram1_clock_gate::W`](W) writer structure"]
impl crate :: Writable for AppRam1ClockGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_RAM1_CLOCK_GATE to value 0"]
impl crate :: Resettable for AppRam1ClockGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_RAM2_CLOCK_GATE (rw) register accessor: APP_RAM2_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ram2_clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ram2_clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_ram2_clock_gate`]
module"]
# [doc (alias = "APP_RAM2_CLOCK_GATE")]
pub type AppRam2ClockGate = crate :: Reg < app_ram2_clock_gate :: AppRam2ClockGateSpec > ; # [doc = "APP_RAM2_CLOCK_GATE"]
pub mod app_ram2_clock_gate { # [doc = "Register `APP_RAM2_CLOCK_GATE` reader"]
pub type R = crate :: R < AppRam2ClockGateSpec > ; # [doc = "Register `APP_RAM2_CLOCK_GATE` writer"]
pub type W = crate :: W < AppRam2ClockGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 : Ungate clock to APP RAM2 3'b111 : Gate Clock to APP RAM2"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 : Ungate clock to APP RAM2 3'b111 : Gate Clock to APP RAM2"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP RAM2 3'b111 : Gate Clock to APP RAM2"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP RAM2 3'b111 : Gate Clock to APP RAM2"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppRam2ClockGateSpec > { EnableW :: new (self , 0) } } # [doc = "APP_RAM2_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ram2_clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ram2_clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppRam2ClockGateSpec ; impl crate :: RegisterSpec for AppRam2ClockGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_ram2_clock_gate::R`](R) reader structure"]
impl crate :: Readable for AppRam2ClockGateSpec { } # [doc = "`write(|w| ..)` method takes [`app_ram2_clock_gate::W`](W) writer structure"]
impl crate :: Writable for AppRam2ClockGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_RAM2_CLOCK_GATE to value 0"]
impl crate :: Resettable for AppRam2ClockGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_RAM3_CLOCK_GATE (rw) register accessor: APP_RAM3_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ram3_clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ram3_clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_ram3_clock_gate`]
module"]
# [doc (alias = "APP_RAM3_CLOCK_GATE")]
pub type AppRam3ClockGate = crate :: Reg < app_ram3_clock_gate :: AppRam3ClockGateSpec > ; # [doc = "APP_RAM3_CLOCK_GATE"]
pub mod app_ram3_clock_gate { # [doc = "Register `APP_RAM3_CLOCK_GATE` reader"]
pub type R = crate :: R < AppRam3ClockGateSpec > ; # [doc = "Register `APP_RAM3_CLOCK_GATE` writer"]
pub type W = crate :: W < AppRam3ClockGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 : Ungate clock to APP RAM3 3'b111 : Gate Clock to APP RAM3"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 : Ungate clock to APP RAM3 3'b111 : Gate Clock to APP RAM3"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP RAM3 3'b111 : Gate Clock to APP RAM3"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to APP RAM3 3'b111 : Gate Clock to APP RAM3"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppRam3ClockGateSpec > { EnableW :: new (self , 0) } } # [doc = "APP_RAM3_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ram3_clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ram3_clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppRam3ClockGateSpec ; impl crate :: RegisterSpec for AppRam3ClockGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_ram3_clock_gate::R`](R) reader structure"]
impl crate :: Readable for AppRam3ClockGateSpec { } # [doc = "`write(|w| ..)` method takes [`app_ram3_clock_gate::W`](W) writer structure"]
impl crate :: Writable for AppRam3ClockGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_RAM3_CLOCK_GATE to value 0"]
impl crate :: Resettable for AppRam3ClockGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_XBARA_DYNAMIC_CG (rw) register accessor: CFG_XBARA_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_xbara_dynamic_cg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_xbara_dynamic_cg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_xbara_dynamic_cg`]
module"]
# [doc (alias = "CFG_XBARA_DYNAMIC_CG")]
pub type CfgXbaraDynamicCg = crate :: Reg < cfg_xbara_dynamic_cg :: CfgXbaraDynamicCgSpec > ; # [doc = "CFG_XBARA_DYNAMIC_CG"]
pub mod cfg_xbara_dynamic_cg { # [doc = "Register `CFG_XBARA_DYNAMIC_CG` reader"]
pub type R = crate :: R < CfgXbaraDynamicCgSpec > ; # [doc = "Register `CFG_XBARA_DYNAMIC_CG` writer"]
pub type W = crate :: W < CfgXbaraDynamicCgSpec > ; # [doc = "Field `enable` reader - 2:0\\]
Enable APPSS crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. When the feature is enabed, the CM4 should monitor for any possible pending transactions from various masters like DMA/NWA and if no transaction is expected to be iniated by the masters, the CM4 executes WFI. On ssertion of WFI signal, the clock to crossbar is gated. The clock is automatically ungated under two conditions (i) when the WFI signal is deasserted by any interrupted (ii) when any of the APPSS TPCC triggers are asserted. Instead of WFI, cfg_xbara_set_dynamic_cg also can be used to start the clock gating. 0 - Dynamic clock gating feature is disabled. The clock to APPSS crossbar is not gated dynamically. The clock to APPSS crossbar is gated/ungated as per device ice level power states."]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
Enable APPSS crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. When the feature is enabed, the CM4 should monitor for any possible pending transactions from various masters like DMA/NWA and if no transaction is expected to be iniated by the masters, the CM4 executes WFI. On ssertion of WFI signal, the clock to crossbar is gated. The clock is automatically ungated under two conditions (i) when the WFI signal is deasserted by any interrupted (ii) when any of the APPSS TPCC triggers are asserted. Instead of WFI, cfg_xbara_set_dynamic_cg also can be used to start the clock gating. 0 - Dynamic clock gating feature is disabled. The clock to APPSS crossbar is not gated dynamically. The clock to APPSS crossbar is gated/ungated as per device ice level power states."]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Enable APPSS crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. When the feature is enabed, the CM4 should monitor for any possible pending transactions from various masters like DMA/NWA and if no transaction is expected to be iniated by the masters, the CM4 executes WFI. On ssertion of WFI signal, the clock to crossbar is gated. The clock is automatically ungated under two conditions (i) when the WFI signal is deasserted by any interrupted (ii) when any of the APPSS TPCC triggers are asserted. Instead of WFI, cfg_xbara_set_dynamic_cg also can be used to start the clock gating. 0 - Dynamic clock gating feature is disabled. The clock to APPSS crossbar is not gated dynamically. The clock to APPSS crossbar is gated/ungated as per device ice level power states."]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Enable APPSS crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. When the feature is enabed, the CM4 should monitor for any possible pending transactions from various masters like DMA/NWA and if no transaction is expected to be iniated by the masters, the CM4 executes WFI. On ssertion of WFI signal, the clock to crossbar is gated. The clock is automatically ungated under two conditions (i) when the WFI signal is deasserted by any interrupted (ii) when any of the APPSS TPCC triggers are asserted. Instead of WFI, cfg_xbara_set_dynamic_cg also can be used to start the clock gating. 0 - Dynamic clock gating feature is disabled. The clock to APPSS crossbar is not gated dynamically. The clock to APPSS crossbar is gated/ungated as per device ice level power states."]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < CfgXbaraDynamicCgSpec > { EnableW :: new (self , 0) } } # [doc = "CFG_XBARA_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_xbara_dynamic_cg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_xbara_dynamic_cg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgXbaraDynamicCgSpec ; impl crate :: RegisterSpec for CfgXbaraDynamicCgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_xbara_dynamic_cg::R`](R) reader structure"]
impl crate :: Readable for CfgXbaraDynamicCgSpec { } # [doc = "`write(|w| ..)` method takes [`cfg_xbara_dynamic_cg::W`](W) writer structure"]
impl crate :: Writable for CfgXbaraDynamicCgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_XBARA_DYNAMIC_CG to value 0"]
impl crate :: Resettable for CfgXbaraDynamicCgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_TPTC1_DYNAMIC_CG (rw) register accessor: CFG_TPTC1_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc1_dynamic_cg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc1_dynamic_cg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tptc1_dynamic_cg`]
module"]
# [doc (alias = "CFG_TPTC1_DYNAMIC_CG")]
pub type CfgTptc1DynamicCg = crate :: Reg < cfg_tptc1_dynamic_cg :: CfgTptc1DynamicCgSpec > ; # [doc = "CFG_TPTC1_DYNAMIC_CG"]
pub mod cfg_tptc1_dynamic_cg { # [doc = "Register `CFG_TPTC1_DYNAMIC_CG` reader"]
pub type R = crate :: R < CfgTptc1DynamicCgSpec > ; # [doc = "Register `CFG_TPTC1_DYNAMIC_CG` writer"]
pub type W = crate :: W < CfgTptc1DynamicCgSpec > ; # [doc = "Field `enable` reader - 2:0\\]
Enable APPSS TPTC1 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc1_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC1 crossbar is not gated dynamically. The clock to APPSS TPTC1 crossbar is gated/ungated as per device ice level power states."]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
Enable APPSS TPTC1 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc1_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC1 crossbar is not gated dynamically. The clock to APPSS TPTC1 crossbar is gated/ungated as per device ice level power states."]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Enable APPSS TPTC1 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc1_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC1 crossbar is not gated dynamically. The clock to APPSS TPTC1 crossbar is gated/ungated as per device ice level power states."]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Enable APPSS TPTC1 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc1_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC1 crossbar is not gated dynamically. The clock to APPSS TPTC1 crossbar is gated/ungated as per device ice level power states."]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < CfgTptc1DynamicCgSpec > { EnableW :: new (self , 0) } } # [doc = "CFG_TPTC1_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc1_dynamic_cg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc1_dynamic_cg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgTptc1DynamicCgSpec ; impl crate :: RegisterSpec for CfgTptc1DynamicCgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_tptc1_dynamic_cg::R`](R) reader structure"]
impl crate :: Readable for CfgTptc1DynamicCgSpec { } # [doc = "`write(|w| ..)` method takes [`cfg_tptc1_dynamic_cg::W`](W) writer structure"]
impl crate :: Writable for CfgTptc1DynamicCgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_TPTC1_DYNAMIC_CG to value 0"]
impl crate :: Resettable for CfgTptc1DynamicCgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_TPTC2_DYNAMIC_CG (rw) register accessor: CFG_TPTC2_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc2_dynamic_cg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc2_dynamic_cg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tptc2_dynamic_cg`]
module"]
# [doc (alias = "CFG_TPTC2_DYNAMIC_CG")]
pub type CfgTptc2DynamicCg = crate :: Reg < cfg_tptc2_dynamic_cg :: CfgTptc2DynamicCgSpec > ; # [doc = "CFG_TPTC2_DYNAMIC_CG"]
pub mod cfg_tptc2_dynamic_cg { # [doc = "Register `CFG_TPTC2_DYNAMIC_CG` reader"]
pub type R = crate :: R < CfgTptc2DynamicCgSpec > ; # [doc = "Register `CFG_TPTC2_DYNAMIC_CG` writer"]
pub type W = crate :: W < CfgTptc2DynamicCgSpec > ; # [doc = "Field `enable` reader - 2:0\\]
Enable APPSS TPTC2 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc2_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC2 crossbar is not gated dynamically. The clock to APPSS TPTC2 crossbar is gated/ungated as per device ice level power states"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
Enable APPSS TPTC2 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc2_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC2 crossbar is not gated dynamically. The clock to APPSS TPTC2 crossbar is gated/ungated as per device ice level power states"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Enable APPSS TPTC2 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc2_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC2 crossbar is not gated dynamically. The clock to APPSS TPTC2 crossbar is gated/ungated as per device ice level power states"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Enable APPSS TPTC2 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc2_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC2 crossbar is not gated dynamically. The clock to APPSS TPTC2 crossbar is gated/ungated as per device ice level power states"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < CfgTptc2DynamicCgSpec > { EnableW :: new (self , 0) } } # [doc = "CFG_TPTC2_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc2_dynamic_cg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc2_dynamic_cg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgTptc2DynamicCgSpec ; impl crate :: RegisterSpec for CfgTptc2DynamicCgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_tptc2_dynamic_cg::R`](R) reader structure"]
impl crate :: Readable for CfgTptc2DynamicCgSpec { } # [doc = "`write(|w| ..)` method takes [`cfg_tptc2_dynamic_cg::W`](W) writer structure"]
impl crate :: Writable for CfgTptc2DynamicCgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_TPTC2_DYNAMIC_CG to value 0"]
impl crate :: Resettable for CfgTptc2DynamicCgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_XBARA_SET_DYNAMIC_CG (rw) register accessor: CFG_XBARA_SET_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_xbara_set_dynamic_cg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_xbara_set_dynamic_cg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_xbara_set_dynamic_cg`]
module"]
# [doc (alias = "CFG_XBARA_SET_DYNAMIC_CG")]
pub type CfgXbaraSetDynamicCg = crate :: Reg < cfg_xbara_set_dynamic_cg :: CfgXbaraSetDynamicCgSpec > ; # [doc = "CFG_XBARA_SET_DYNAMIC_CG"]
pub mod cfg_xbara_set_dynamic_cg { # [doc = "Register `CFG_XBARA_SET_DYNAMIC_CG` reader"]
pub type R = crate :: R < CfgXbaraSetDynamicCgSpec > ; # [doc = "Register `CFG_XBARA_SET_DYNAMIC_CG` writer"]
pub type W = crate :: W < CfgXbaraSetDynamicCgSpec > ; # [doc = "Field `set` reader - 0:0\\]
Start APPSS crossbar dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
pub type SetR = crate :: BitReader ; # [doc = "Field `set` writer - 0:0\\]
Start APPSS crossbar dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Start APPSS crossbar dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Start APPSS crossbar dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < CfgXbaraSetDynamicCgSpec > { SetW :: new (self , 0) } } # [doc = "CFG_XBARA_SET_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_xbara_set_dynamic_cg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_xbara_set_dynamic_cg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgXbaraSetDynamicCgSpec ; impl crate :: RegisterSpec for CfgXbaraSetDynamicCgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_xbara_set_dynamic_cg::R`](R) reader structure"]
impl crate :: Readable for CfgXbaraSetDynamicCgSpec { } # [doc = "`write(|w| ..)` method takes [`cfg_xbara_set_dynamic_cg::W`](W) writer structure"]
impl crate :: Writable for CfgXbaraSetDynamicCgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_XBARA_SET_DYNAMIC_CG to value 0"]
impl crate :: Resettable for CfgXbaraSetDynamicCgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_TPTC1_SET_DYNAMIC_CG (rw) register accessor: CFG_TPTC1_SET_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc1_set_dynamic_cg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc1_set_dynamic_cg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tptc1_set_dynamic_cg`]
module"]
# [doc (alias = "CFG_TPTC1_SET_DYNAMIC_CG")]
pub type CfgTptc1SetDynamicCg = crate :: Reg < cfg_tptc1_set_dynamic_cg :: CfgTptc1SetDynamicCgSpec > ; # [doc = "CFG_TPTC1_SET_DYNAMIC_CG"]
pub mod cfg_tptc1_set_dynamic_cg { # [doc = "Register `CFG_TPTC1_SET_DYNAMIC_CG` reader"]
pub type R = crate :: R < CfgTptc1SetDynamicCgSpec > ; # [doc = "Register `CFG_TPTC1_SET_DYNAMIC_CG` writer"]
pub type W = crate :: W < CfgTptc1SetDynamicCgSpec > ; # [doc = "Field `set` reader - 0:0\\]
Start APPSS tptc1 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
pub type SetR = crate :: BitReader ; # [doc = "Field `set` writer - 0:0\\]
Start APPSS tptc1 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Start APPSS tptc1 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Start APPSS tptc1 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < CfgTptc1SetDynamicCgSpec > { SetW :: new (self , 0) } } # [doc = "CFG_TPTC1_SET_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc1_set_dynamic_cg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc1_set_dynamic_cg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgTptc1SetDynamicCgSpec ; impl crate :: RegisterSpec for CfgTptc1SetDynamicCgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_tptc1_set_dynamic_cg::R`](R) reader structure"]
impl crate :: Readable for CfgTptc1SetDynamicCgSpec { } # [doc = "`write(|w| ..)` method takes [`cfg_tptc1_set_dynamic_cg::W`](W) writer structure"]
impl crate :: Writable for CfgTptc1SetDynamicCgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_TPTC1_SET_DYNAMIC_CG to value 0"]
impl crate :: Resettable for CfgTptc1SetDynamicCgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_TPTC2_SET_DYNAMIC_CG (rw) register accessor: CFG_TPTC2_SET_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc2_set_dynamic_cg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc2_set_dynamic_cg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tptc2_set_dynamic_cg`]
module"]
# [doc (alias = "CFG_TPTC2_SET_DYNAMIC_CG")]
pub type CfgTptc2SetDynamicCg = crate :: Reg < cfg_tptc2_set_dynamic_cg :: CfgTptc2SetDynamicCgSpec > ; # [doc = "CFG_TPTC2_SET_DYNAMIC_CG"]
pub mod cfg_tptc2_set_dynamic_cg { # [doc = "Register `CFG_TPTC2_SET_DYNAMIC_CG` reader"]
pub type R = crate :: R < CfgTptc2SetDynamicCgSpec > ; # [doc = "Register `CFG_TPTC2_SET_DYNAMIC_CG` writer"]
pub type W = crate :: W < CfgTptc2SetDynamicCgSpec > ; # [doc = "Field `set` reader - 0:0\\]
Start APPSS tptc2 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
pub type SetR = crate :: BitReader ; # [doc = "Field `set` writer - 0:0\\]
Start APPSS tptc2 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
pub type SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Start APPSS tptc2 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Start APPSS tptc2 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock."]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < CfgTptc2SetDynamicCgSpec > { SetW :: new (self , 0) } } # [doc = "CFG_TPTC2_SET_DYNAMIC_CG\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tptc2_set_dynamic_cg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tptc2_set_dynamic_cg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgTptc2SetDynamicCgSpec ; impl crate :: RegisterSpec for CfgTptc2SetDynamicCgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_tptc2_set_dynamic_cg::R`](R) reader structure"]
impl crate :: Readable for CfgTptc2SetDynamicCgSpec { } # [doc = "`write(|w| ..)` method takes [`cfg_tptc2_set_dynamic_cg::W`](W) writer structure"]
impl crate :: Writable for CfgTptc2SetDynamicCgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_TPTC2_SET_DYNAMIC_CG to value 0"]
impl crate :: Resettable for CfgTptc2SetDynamicCgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CM4_FORCE_HCLK_GATE (rw) register accessor: CM4_FORCE_HCLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`cm4_force_hclk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cm4_force_hclk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm4_force_hclk_gate`]
module"]
# [doc (alias = "CM4_FORCE_HCLK_GATE")]
pub type Cm4ForceHclkGate = crate :: Reg < cm4_force_hclk_gate :: Cm4ForceHclkGateSpec > ; # [doc = "CM4_FORCE_HCLK_GATE"]
pub mod cm4_force_hclk_gate { # [doc = "Register `CM4_FORCE_HCLK_GATE` reader"]
pub type R = crate :: R < Cm4ForceHclkGateSpec > ; # [doc = "Register `CM4_FORCE_HCLK_GATE` writer"]
pub type W = crate :: W < Cm4ForceHclkGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 - CM4 HCLK is ungated 3'b111 - CM4 HCLK is gated"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 - CM4 HCLK is ungated 3'b111 - CM4 HCLK is gated"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 - CM4 HCLK is ungated 3'b111 - CM4 HCLK is gated"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 - CM4 HCLK is ungated 3'b111 - CM4 HCLK is gated"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < Cm4ForceHclkGateSpec > { EnableW :: new (self , 0) } } # [doc = "CM4_FORCE_HCLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`cm4_force_hclk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cm4_force_hclk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm4ForceHclkGateSpec ; impl crate :: RegisterSpec for Cm4ForceHclkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cm4_force_hclk_gate::R`](R) reader structure"]
impl crate :: Readable for Cm4ForceHclkGateSpec { } # [doc = "`write(|w| ..)` method takes [`cm4_force_hclk_gate::W`](W) writer structure"]
impl crate :: Writable for Cm4ForceHclkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CM4_FORCE_HCLK_GATE to value 0"]
impl crate :: Resettable for Cm4ForceHclkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LIN_SCI_DIV (rw) register accessor: LIN_SCI_DIV\n\nYou can [`read`](crate::Reg::read) this register and get [`lin_sci_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lin_sci_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lin_sci_div`]
module"]
# [doc (alias = "LIN_SCI_DIV")]
pub type LinSciDiv = crate :: Reg < lin_sci_div :: LinSciDivSpec > ; # [doc = "LIN_SCI_DIV"]
pub mod lin_sci_div { # [doc = "Register `LIN_SCI_DIV` reader"]
pub type R = crate :: R < LinSciDivSpec > ; # [doc = "Register `LIN_SCI_DIV` writer"]
pub type W = crate :: W < LinSciDivSpec > ; # [doc = "Field `val` reader - 7:0\\]
ICG Based Divider for LIN"]
pub type ValR = crate :: FieldReader ; # [doc = "Field `val` writer - 7:0\\]
ICG Based Divider for LIN"]
pub type ValW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
ICG Based Divider for LIN"]
# [inline (always)]
pub fn val (& self) -> ValR { ValR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
ICG Based Divider for LIN"]
# [inline (always)]
# [must_use]
pub fn val (& mut self) -> ValW < LinSciDivSpec > { ValW :: new (self , 0) } } # [doc = "LIN_SCI_DIV\n\nYou can [`read`](crate::Reg::read) this register and get [`lin_sci_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lin_sci_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LinSciDivSpec ; impl crate :: RegisterSpec for LinSciDivSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`lin_sci_div::R`](R) reader structure"]
impl crate :: Readable for LinSciDivSpec { } # [doc = "`write(|w| ..)` method takes [`lin_sci_div::W`](W) writer structure"]
impl crate :: Writable for LinSciDivSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LIN_SCI_DIV to value 0"]
impl crate :: Resettable for LinSciDivSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_LSTC_EN (rw) register accessor: APP_LSTC_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`app_lstc_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_lstc_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_lstc_en`]
module"]
# [doc (alias = "APP_LSTC_EN")]
pub type AppLstcEn = crate :: Reg < app_lstc_en :: AppLstcEnSpec > ; # [doc = "APP_LSTC_EN"]
pub mod app_lstc_en { # [doc = "Register `APP_LSTC_EN` reader"]
pub type R = crate :: R < AppLstcEnSpec > ; # [doc = "Register `APP_LSTC_EN` writer"]
pub type W = crate :: W < AppLstcEnSpec > ; # [doc = "Field `enable` reader - 0:0\\]
Enable vbusp_req and clk_en for app lstc"]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
Enable vbusp_req and clk_en for app lstc"]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Enable vbusp_req and clk_en for app lstc"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Enable vbusp_req and clk_en for app lstc"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppLstcEnSpec > { EnableW :: new (self , 0) } } # [doc = "APP_LSTC_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`app_lstc_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_lstc_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppLstcEnSpec ; impl crate :: RegisterSpec for AppLstcEnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_lstc_en::R`](R) reader structure"]
impl crate :: Readable for AppLstcEnSpec { } # [doc = "`write(|w| ..)` method takes [`app_lstc_en::W`](W) writer structure"]
impl crate :: Writable for AppLstcEnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_LSTC_EN to value 0"]
impl crate :: Resettable for AppLstcEnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK0 (rw) register accessor: - KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick0`]
module"]
# [doc (alias = "LOCK0_KICK0")]
pub type Lock0Kick0 = crate :: Reg < lock0_kick0 :: Lock0Kick0Spec > ; # [doc = "- KICK0 component"]
pub mod lock0_kick0 { # [doc = "Register `LOCK0_KICK0` reader"]
pub type R = crate :: R < Lock0Kick0Spec > ; # [doc = "Register `LOCK0_KICK0` writer"]
pub type W = crate :: W < Lock0Kick0Spec > ; # [doc = "Field `KICK0_COMPONENT` reader - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK0_COMPONENT` writer - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
pub fn kick0_component (& self) -> Kick0ComponentR { Kick0ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
# [must_use]
pub fn kick0_component (& mut self) -> Kick0ComponentW < Lock0Kick0Spec > { Kick0ComponentW :: new (self , 0) } } # [doc = "- KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick0Spec ; impl crate :: RegisterSpec for Lock0Kick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick0::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick0Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick0::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK0 to value 0"]
impl crate :: Resettable for Lock0Kick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK1 (rw) register accessor: - KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick1`]
module"]
# [doc (alias = "LOCK0_KICK1")]
pub type Lock0Kick1 = crate :: Reg < lock0_kick1 :: Lock0Kick1Spec > ; # [doc = "- KICK1 component"]
pub mod lock0_kick1 { # [doc = "Register `LOCK0_KICK1` reader"]
pub type R = crate :: R < Lock0Kick1Spec > ; # [doc = "Register `LOCK0_KICK1` writer"]
pub type W = crate :: W < Lock0Kick1Spec > ; # [doc = "Field `KICK1_COMPONENT` reader - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK1_COMPONENT` writer - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
pub fn kick1_component (& self) -> Kick1ComponentR { Kick1ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
# [must_use]
pub fn kick1_component (& mut self) -> Kick1ComponentW < Lock0Kick1Spec > { Kick1ComponentW :: new (self , 0) } } # [doc = "- KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick1Spec ; impl crate :: RegisterSpec for Lock0Kick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick1::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick1Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick1::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK1 to value 0"]
impl crate :: Resettable for Lock0Kick1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_raw_status (rw) register accessor: Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw_status`]
module"]
# [doc (alias = "intr_raw_status")]
pub type IntrRawStatus = crate :: Reg < intr_raw_status :: IntrRawStatusSpec > ; # [doc = "Interrupt Raw Status/Set Register"]
pub mod intr_raw_status { # [doc = "Register `intr_raw_status` reader"]
pub type R = crate :: R < IntrRawStatusSpec > ; # [doc = "Register `intr_raw_status` writer"]
pub type W = crate :: W < IntrRawStatusSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrRawStatusSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrRawStatusSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrRawStatusSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrRawStatusSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrRawStatusSpec ; impl crate :: RegisterSpec for IntrRawStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_raw_status::R`](R) reader structure"]
impl crate :: Readable for IntrRawStatusSpec { } # [doc = "`write(|w| ..)` method takes [`intr_raw_status::W`](W) writer structure"]
impl crate :: Writable for IntrRawStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_raw_status to value 0"]
impl crate :: Resettable for IntrRawStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enabled_status_clear (rw) register accessor: Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enabled_status_clear`]
module"]
# [doc (alias = "intr_enabled_status_clear")]
pub type IntrEnabledStatusClear = crate :: Reg < intr_enabled_status_clear :: IntrEnabledStatusClearSpec > ; # [doc = "Interrupt Enabled Status/Clear register"]
pub mod intr_enabled_status_clear { # [doc = "Register `intr_enabled_status_clear` reader"]
pub type R = crate :: R < IntrEnabledStatusClearSpec > ; # [doc = "Register `intr_enabled_status_clear` writer"]
pub type W = crate :: W < IntrEnabledStatusClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrEnabledStatusClearSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrEnabledStatusClearSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnabledStatusClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnabledStatusClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnabledStatusClearSpec ; impl crate :: RegisterSpec for IntrEnabledStatusClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enabled_status_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnabledStatusClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enabled_status_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnabledStatusClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enabled_status_clear to value 0"]
impl crate :: Resettable for IntrEnabledStatusClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable`]
module"]
# [doc (alias = "intr_enable")]
pub type IntrEnable = crate :: Reg < intr_enable :: IntrEnableSpec > ; # [doc = "Interrupt Enable register"]
pub mod intr_enable { # [doc = "Register `intr_enable` reader"]
pub type R = crate :: R < IntrEnableSpec > ; # [doc = "Register `intr_enable` writer"]
pub type W = crate :: W < IntrEnableSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSpec ; impl crate :: RegisterSpec for IntrEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable to value 0"]
impl crate :: Resettable for IntrEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable_clear (rw) register accessor: Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "intr_enable_clear")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "Interrupt Enable Clear register"]
pub mod intr_enable_clear { # [doc = "Register `intr_enable_clear` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `intr_enable_clear` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableClearSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableClearSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable_clear to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "eoi (rw) register accessor: EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi`]
module"]
# [doc (alias = "eoi")]
pub type Eoi = crate :: Reg < eoi :: EoiSpec > ; # [doc = "EOI register"]
pub mod eoi { # [doc = "Register `eoi` reader"]
pub type R = crate :: R < EoiSpec > ; # [doc = "Register `eoi` writer"]
pub type W = crate :: W < EoiSpec > ; # [doc = "Field `EOI_VECTOR_VALUE_` reader - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_R = crate :: FieldReader ; # [doc = "Field `EOI_VECTOR_VALUE_` writer - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
pub fn eoi_vector_value_ (& self) -> EoiVectorValue_R { EoiVectorValue_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
# [must_use]
pub fn eoi_vector_value_ (& mut self) -> EoiVectorValue_W < EoiSpec > { EoiVectorValue_W :: new (self , 0) } } # [doc = "EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EoiSpec ; impl crate :: RegisterSpec for EoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eoi::R`](R) reader structure"]
impl crate :: Readable for EoiSpec { } # [doc = "`write(|w| ..)` method takes [`eoi::W`](W) writer structure"]
impl crate :: Writable for EoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets eoi to value 0"]
impl crate :: Resettable for EoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_address (rw) register accessor: Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_address`]
module"]
# [doc (alias = "fault_address")]
pub type FaultAddress = crate :: Reg < fault_address :: FaultAddressSpec > ; # [doc = "Fault Address register"]
pub mod fault_address { # [doc = "Register `fault_address` reader"]
pub type R = crate :: R < FaultAddressSpec > ; # [doc = "Register `fault_address` writer"]
pub type W = crate :: W < FaultAddressSpec > ; # [doc = "Field `FAULT_ADDRESS_` reader - 31:0\\]
Fault Address."]
pub type FaultAddress_R = crate :: FieldReader < u32 > ; # [doc = "Field `FAULT_ADDRESS_` writer - 31:0\\]
Fault Address."]
pub type FaultAddress_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
pub fn fault_address_ (& self) -> FaultAddress_R { FaultAddress_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
# [must_use]
pub fn fault_address_ (& mut self) -> FaultAddress_W < FaultAddressSpec > { FaultAddress_W :: new (self , 0) } } # [doc = "Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAddressSpec ; impl crate :: RegisterSpec for FaultAddressSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_address::R`](R) reader structure"]
impl crate :: Readable for FaultAddressSpec { } # [doc = "`write(|w| ..)` method takes [`fault_address::W`](W) writer structure"]
impl crate :: Writable for FaultAddressSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_address to value 0"]
impl crate :: Resettable for FaultAddressSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_type_status (rw) register accessor: Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_type_status`]
module"]
# [doc (alias = "fault_type_status")]
pub type FaultTypeStatus = crate :: Reg < fault_type_status :: FaultTypeStatusSpec > ; # [doc = "Fault Type Status register"]
pub mod fault_type_status { # [doc = "Register `fault_type_status` reader"]
pub type R = crate :: R < FaultTypeStatusSpec > ; # [doc = "Register `fault_type_status` writer"]
pub type W = crate :: W < FaultTypeStatusSpec > ; # [doc = "Field `FAULT_TYPE_10_0000` reader - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000R = crate :: FieldReader ; # [doc = "Field `FAULT_TYPE_10_0000` writer - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NONSECURE_ACCESS_` reader - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_R = crate :: BitReader ; # [doc = "Field `NONSECURE_ACCESS_` writer - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
pub fn fault_type_10_0000 (& self) -> FaultType10_0000R { FaultType10_0000R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
pub fn nonsecure_access_ (& self) -> NonsecureAccess_R { NonsecureAccess_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
# [must_use]
pub fn fault_type_10_0000 (& mut self) -> FaultType10_0000W < FaultTypeStatusSpec > { FaultType10_0000W :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
# [must_use]
pub fn nonsecure_access_ (& mut self) -> NonsecureAccess_W < FaultTypeStatusSpec > { NonsecureAccess_W :: new (self , 6) } } # [doc = "Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultTypeStatusSpec ; impl crate :: RegisterSpec for FaultTypeStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_type_status::R`](R) reader structure"]
impl crate :: Readable for FaultTypeStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_type_status::W`](W) writer structure"]
impl crate :: Writable for FaultTypeStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_type_status to value 0"]
impl crate :: Resettable for FaultTypeStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_attr_status (rw) register accessor: Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_attr_status`]
module"]
# [doc (alias = "fault_attr_status")]
pub type FaultAttrStatus = crate :: Reg < fault_attr_status :: FaultAttrStatusSpec > ; # [doc = "Fault Attribute Status register"]
pub mod fault_attr_status { # [doc = "Register `fault_attr_status` reader"]
pub type R = crate :: R < FaultAttrStatusSpec > ; # [doc = "Register `fault_attr_status` writer"]
pub type W = crate :: W < FaultAttrStatusSpec > ; # [doc = "Field `PRIVILEGE_ID_` reader - 7:0\\]
Privilege ID."]
pub type PrivilegeId_R = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID_` writer - 7:0\\]
Privilege ID."]
pub type PrivilegeId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ROUTE_ID_` reader - 19:8\\]
Route ID."]
pub type RouteId_R = crate :: FieldReader < u16 > ; # [doc = "Field `ROUTE_ID_` writer - 19:8\\]
Route ID."]
pub type RouteId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `XID_` reader - 31:20\\]
XID."]
pub type Xid_R = crate :: FieldReader < u16 > ; # [doc = "Field `XID_` writer - 31:20\\]
XID."]
pub type Xid_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
pub fn privilege_id_ (& self) -> PrivilegeId_R { PrivilegeId_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
pub fn route_id_ (& self) -> RouteId_R { RouteId_R :: new (((self . bits >> 8) & 0x0fff) as u16) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
pub fn xid_ (& self) -> Xid_R { Xid_R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
# [must_use]
pub fn privilege_id_ (& mut self) -> PrivilegeId_W < FaultAttrStatusSpec > { PrivilegeId_W :: new (self , 0) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
# [must_use]
pub fn route_id_ (& mut self) -> RouteId_W < FaultAttrStatusSpec > { RouteId_W :: new (self , 8) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
# [must_use]
pub fn xid_ (& mut self) -> Xid_W < FaultAttrStatusSpec > { Xid_W :: new (self , 20) } } # [doc = "Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAttrStatusSpec ; impl crate :: RegisterSpec for FaultAttrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_attr_status::R`](R) reader structure"]
impl crate :: Readable for FaultAttrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_attr_status::W`](W) writer structure"]
impl crate :: Writable for FaultAttrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_attr_status to value 0"]
impl crate :: Resettable for FaultAttrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_clear (rw) register accessor: Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_clear`]
module"]
# [doc (alias = "fault_clear")]
pub type FaultClear = crate :: Reg < fault_clear :: FaultClearSpec > ; # [doc = "Fault Clear register"]
pub mod fault_clear { # [doc = "Register `fault_clear` reader"]
pub type R = crate :: R < FaultClearSpec > ; # [doc = "Register `fault_clear` writer"]
pub type W = crate :: W < FaultClearSpec > ; # [doc = "Field `FAULT_CLEAR__WRITING` reader - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingR = crate :: BitReader ; # [doc = "Field `FAULT_CLEAR__WRITING` writer - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
pub fn fault_clear__writing (& self) -> FaultClear_WritingR { FaultClear_WritingR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn fault_clear__writing (& mut self) -> FaultClear_WritingW < FaultClearSpec > { FaultClear_WritingW :: new (self , 0) } } # [doc = "Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultClearSpec ; impl crate :: RegisterSpec for FaultClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_clear::R`](R) reader structure"]
impl crate :: Readable for FaultClearSpec { } # [doc = "`write(|w| ..)` method takes [`fault_clear::W`](W) writer structure"]
impl crate :: Writable for FaultClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_clear to value 0"]
impl crate :: Resettable for FaultClearSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_CTRL"]
pub struct AppCtrl { _marker : PhantomData < * const () > } unsafe impl Send for AppCtrl { } impl AppCtrl { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_ctrl :: RegisterBlock = 0x5606_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_ctrl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppCtrl { type Target = app_ctrl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppCtrl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppCtrl") . finish () } } # [doc = "APP_CTRL"]
pub mod app_ctrl { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , hw_reg0 : HwReg0 , hw_reg1 : HwReg1 , previous_name : PreviousName , hw_reg3 : HwReg3 , hw_reg4 : HwReg4 , hw_reg5 : HwReg5 , hw_reg6 : HwReg6 , hw_reg7 : HwReg7 , appss_sw_int : AppssSwInt , appss_ipc_rfs : AppssIpcRfs , appss_capevnt_sel : AppssCapevntSel , appss_dma_req_sel : AppssDmaReqSel , appss_dma1_req_sel : AppssDma1ReqSel , appss_irq_req_sel : AppssIrqReqSel , appss_spi_trig_src : AppssSpiTrigSrc , appss_ram1a_mem_init : AppssRam1aMemInit , appss_ram1a_mem_init_done : AppssRam1aMemInitDone , appss_ram1a_mem_init_status : AppssRam1aMemInitStatus , appss_ram2a_mem_init : AppssRam2aMemInit , appss_ram2a_mem_init_done : AppssRam2aMemInitDone , appss_ram2a_mem_init_status : AppssRam2aMemInitStatus , appss_ram3a_mem_init : AppssRam3aMemInit , appss_ram3a_mem_init_done : AppssRam3aMemInitDone , appss_ram3a_mem_init_status : AppssRam3aMemInitStatus , hwass_shrd_ram0_mem_init : HwassShrdRam0MemInit , hwass_shrd_ram0_mem_init_done : HwassShrdRam0MemInitDone , hwass_shrd_ram0_mem_init_status : HwassShrdRam0MemInitStatus , hwass_shrd_ram1_mem_init : HwassShrdRam1MemInit , hwass_shrd_ram1_mem_init_done : HwassShrdRam1MemInitDone , hwass_shrd_ram1_mem_init_status : HwassShrdRam1MemInitStatus , appss_tpcc_meminit_start : AppssTpccMeminitStart , appss_tpcc_meminit_done : AppssTpccMeminitDone , appss_tpcc_meminit_status : AppssTpccMeminitStatus , appss_spia_cfg : AppssSpiaCfg , appss_spib_cfg : AppssSpibCfg , appss_epwm_cfg : AppssEpwmCfg , reserved : Reserved , appss_mcan_fe_and_lin_intr_sel : AppssMcanFeAndLinIntrSel , appss_mcana_int_clr : AppssMcanaIntClr , appss_mcana_int_mask : AppssMcanaIntMask , appss_mcana_int_stat : AppssMcanaIntStat , appss_cm4_global_config : AppssCm4GlobalConfig , reserved1 : Reserved1 , appss_cm4_rom_eclipse : AppssCm4RomEclipse , appss_cm4_status_reg : AppssCm4StatusReg , appss_ahb_ctrl : AppssAhbCtrl , esm_gating0 : EsmGating0 , esm_gating1 : EsmGating1 , esm_gating2 : EsmGating2 , esm_gating3 : EsmGating3 , esm_gating4 : EsmGating4 , esm_gating5 : EsmGating5 , esm_gating6 : EsmGating6 , esm_gating7 : EsmGating7 , appss_cm4_halt : AppssCm4Halt , appss_cm4_event : AppssCm4Event , spia_io_cfg : SpiaIoCfg , spib_io_cfg : SpibIoCfg , spi_host_irq : SpiHostIrq , tptc_dbs_config : TptcDbsConfig , tpcc_parity_ctrl : TpccParityCtrl , tpcc_parity_status : TpccParityStatus , appss_dbg_ack_ctl0 : AppssDbgAckCtl0 , debugss_csetb_flush : DebugssCsetbFlush , cpsw_control : CpswControl , appss_erragg_mask0 : AppssErraggMask0 , appss_erragg_status0 : AppssErraggStatus0 , _reserved68 : [u8 ; 0x80]
, appss_tpcc_a_erragg_mask : AppssTpccAErraggMask , appss_tpcc_a_erragg_status : AppssTpccAErraggStatus , appss_tpcc_a_erragg_status_raw : AppssTpccAErraggStatusRaw , _reserved71 : [u8 ; 0x78]
, appss_tpcc_a_intagg_mask : AppssTpccAIntaggMask , hw_spare_wph : HwSpareWph , appss_tpcc_a_intagg_status_raw : AppssTpccAIntaggStatusRaw , _reserved74 : [u8 ; 0x54]
, appss_tpcc_b_erragg_mask : AppssTpccBErraggMask , appss_tpcc_b_erragg_status : AppssTpccBErraggStatus , appss_tpcc_b_erragg_status_raw : AppssTpccBErraggStatusRaw , _reserved77 : [u8 ; 0x6c]
, appss_tpcc_b_intagg_mask : AppssTpccBIntaggMask , appss_tpcc_b_intagg_status : AppssTpccBIntaggStatus , appss_tpcc_b_intagg_status_raw : AppssTpccBIntaggStatusRaw , appss_mpu_erragg_mask : AppssMpuErraggMask , appss_mpu_erragg_status : AppssMpuErraggStatus , appss_mpu_erragg_status_raw : AppssMpuErraggStatusRaw , appss_qspi_config : AppssQspiConfig , appss_cti_trig_sel : AppssCtiTrigSel , appss_dbgss_cti_trig_sel : AppssDbgssCtiTrigSel , appss_boot_info_reg0 : AppssBootInfoReg0 , appss_boot_info_reg1 : AppssBootInfoReg1 , appss_boot_info_reg2 : AppssBootInfoReg2 , appss_boot_info_reg3 : AppssBootInfoReg3 , appss_boot_info_reg4 : AppssBootInfoReg4 , appss_boot_info_reg5 : AppssBootInfoReg5 , appss_boot_info_reg6 : AppssBootInfoReg6 , appss_boot_info_reg7 : AppssBootInfoReg7 , appss_tptc_eccaggr_clk_cntrl : AppssTptcEccaggrClkCntrl , appss_tptc_boundary_cfg : AppssTptcBoundaryCfg , appss_tptc_xid_reorder_cfg : AppssTptcXidReorderCfg , hw_sync_fe_ctrl : HwSyncFeCtrl , hw_spare_reg1 : HwSpareReg1 , hw_spare_reg2 : HwSpareReg2 , hw_spare_reg3 : HwSpareReg3 , nerror_mask : NerrorMask , hw_spare_rw0 : HwSpareRw0 , hw_spare_rw1 : HwSpareRw1 , hw_spare_rw2 : HwSpareRw2 , hw_spare_rw3 : HwSpareRw3 , hw_spare_rw4 : HwSpareRw4 , hw_spare_rw5 : HwSpareRw5 , hw_spare_ro0 : HwSpareRo0 , hw_spare_ro1 : HwSpareRo1 , hw_spare_ro2 : HwSpareRo2 , hw_spare_ro3 : HwSpareRo3 , hw_spare_rec : HwSpareRec , app_ctrl : AppCtrl , wic_ctrl : WicCtrl , wic_stat_clr : WicStatClr , wic_stat : WicStat , wicen : Wicen , forcefclkactive : Forcefclkactive , fecss_clk_gate : FecssClkGate , appss_shared_mem_clk_gate : AppssSharedMemClkGate , appss_mem_init_slice_sel : AppssMemInitSliceSel , appss_qspi_char_ext_clk_en : AppssQspiCharExtClkEn , appss_qspi_ext_clk_en : AppssQspiExtClkEn , spi1_smart_idle : Spi1SmartIdle , spi2_smart_idle : Spi2SmartIdle , can_smart_idle : CanSmartIdle , lin_smart_idle : LinSmartIdle , hwass_clk_gate : HwassClkGate , cfg_timeout_pcr3 : CfgTimeoutPcr3 , reserved0 : Reserved0 , appss_erragg_mask1 : AppssErraggMask1 , appss_erragg_status1 : AppssErraggStatus1 , forcehclkactive : Forcehclkactive , appss_ram1_owrite_err : AppssRam1OwriteErr , appss_ram1_owrite_err_addr : AppssRam1OwriteErrAddr , appss_ram2_owrite_err : AppssRam2OwriteErr , appss_ram2_owrite_err_addr : AppssRam2OwriteErrAddr , appss_ram3_owrite_err : AppssRam3OwriteErr , appss_ram3_owrite_err_addr : AppssRam3OwriteErrAddr , appss_shrd_ram_owrite_err : AppssShrdRamOwriteErr , appss_shrd_ram_owrite_err_addr : AppssShrdRamOwriteErrAddr , appss_owrite_err_aggr : AppssOwriteErrAggr , hw_spare_rw6 : HwSpareRw6 , hw_spare_rw7 : HwSpareRw7 , hw_spare_rw8 : HwSpareRw8 , hw_spare_rw9 : HwSpareRw9 , hw_spare_hwa_rw0 : HwSpareHwaRw0 , _reserved148 : [u8 ; 0x0c00]
, lock0_kick0 : Lock0Kick0 , lock0_kick1 : Lock0Kick1 , intr_raw_status : IntrRawStatus , intr_enabled_status_clear : IntrEnabledStatusClear , intr_enable : IntrEnable , intr_enable_clear : IntrEnableClear , eoi : Eoi , fault_address : FaultAddress , fault_type_status : FaultTypeStatus , fault_attr_status : FaultAttrStatus , fault_clear : FaultClear , } impl RegisterBlock { # [doc = "0x00 - PID register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - HW_REG0"]
# [inline (always)]
pub const fn hw_reg0 (& self) -> & HwReg0 { & self . hw_reg0 } # [doc = "0x08 - HW_REG1"]
# [inline (always)]
pub const fn hw_reg1 (& self) -> & HwReg1 { & self . hw_reg1 } # [doc = "0x0c - PREVIOUS_NAME"]
# [inline (always)]
pub const fn previous_name (& self) -> & PreviousName { & self . previous_name } # [doc = "0x10 - HW_REG3"]
# [inline (always)]
pub const fn hw_reg3 (& self) -> & HwReg3 { & self . hw_reg3 } # [doc = "0x14 - HW_REG4"]
# [inline (always)]
pub const fn hw_reg4 (& self) -> & HwReg4 { & self . hw_reg4 } # [doc = "0x18 - HW_REG5"]
# [inline (always)]
pub const fn hw_reg5 (& self) -> & HwReg5 { & self . hw_reg5 } # [doc = "0x1c - HW_REG6"]
# [inline (always)]
pub const fn hw_reg6 (& self) -> & HwReg6 { & self . hw_reg6 } # [doc = "0x20 - HW_REG7"]
# [inline (always)]
pub const fn hw_reg7 (& self) -> & HwReg7 { & self . hw_reg7 } # [doc = "0x24 - APPSS_SW_INT"]
# [inline (always)]
pub const fn appss_sw_int (& self) -> & AppssSwInt { & self . appss_sw_int } # [doc = "0x28 - APPSS_IPC_RFS"]
# [inline (always)]
pub const fn appss_ipc_rfs (& self) -> & AppssIpcRfs { & self . appss_ipc_rfs } # [doc = "0x2c - APPSS_CAPEVNT_SEL"]
# [inline (always)]
pub const fn appss_capevnt_sel (& self) -> & AppssCapevntSel { & self . appss_capevnt_sel } # [doc = "0x30 - APPSS_DMA_REQ_SEL"]
# [inline (always)]
pub const fn appss_dma_req_sel (& self) -> & AppssDmaReqSel { & self . appss_dma_req_sel } # [doc = "0x34 - APPSS_DMA1_REQ_SEL"]
# [inline (always)]
pub const fn appss_dma1_req_sel (& self) -> & AppssDma1ReqSel { & self . appss_dma1_req_sel } # [doc = "0x38 - APPSS_IRQ_REQ_SEL"]
# [inline (always)]
pub const fn appss_irq_req_sel (& self) -> & AppssIrqReqSel { & self . appss_irq_req_sel } # [doc = "0x3c - APPSS_SPI_TRIG_SRC"]
# [inline (always)]
pub const fn appss_spi_trig_src (& self) -> & AppssSpiTrigSrc { & self . appss_spi_trig_src } # [doc = "0x40 - APPSS_RAM1A_MEM_INIT"]
# [inline (always)]
pub const fn appss_ram1a_mem_init (& self) -> & AppssRam1aMemInit { & self . appss_ram1a_mem_init } # [doc = "0x44 - APPSS_RAM1A_MEM_INIT_DONE"]
# [inline (always)]
pub const fn appss_ram1a_mem_init_done (& self) -> & AppssRam1aMemInitDone { & self . appss_ram1a_mem_init_done } # [doc = "0x48 - APPSS_RAM1A_MEM_INIT_STATUS"]
# [inline (always)]
pub const fn appss_ram1a_mem_init_status (& self) -> & AppssRam1aMemInitStatus { & self . appss_ram1a_mem_init_status } # [doc = "0x4c - APPSS_RAM2A_MEM_INIT"]
# [inline (always)]
pub const fn appss_ram2a_mem_init (& self) -> & AppssRam2aMemInit { & self . appss_ram2a_mem_init } # [doc = "0x50 - APPSS_RAM2A_MEM_INIT_DONE"]
# [inline (always)]
pub const fn appss_ram2a_mem_init_done (& self) -> & AppssRam2aMemInitDone { & self . appss_ram2a_mem_init_done } # [doc = "0x54 - APPSS_RAM2A_MEM_INIT_STATUS"]
# [inline (always)]
pub const fn appss_ram2a_mem_init_status (& self) -> & AppssRam2aMemInitStatus { & self . appss_ram2a_mem_init_status } # [doc = "0x58 - APPSS_RAM3A_MEM_INIT"]
# [inline (always)]
pub const fn appss_ram3a_mem_init (& self) -> & AppssRam3aMemInit { & self . appss_ram3a_mem_init } # [doc = "0x5c - APPSS_RAM3A_MEM_INIT_DONE"]
# [inline (always)]
pub const fn appss_ram3a_mem_init_done (& self) -> & AppssRam3aMemInitDone { & self . appss_ram3a_mem_init_done } # [doc = "0x60 - APPSS_RAM3A_MEM_INIT_STATUS"]
# [inline (always)]
pub const fn appss_ram3a_mem_init_status (& self) -> & AppssRam3aMemInitStatus { & self . appss_ram3a_mem_init_status } # [doc = "0x64 - HWASS_SHRD_RAM0_MEM_INIT"]
# [inline (always)]
pub const fn hwass_shrd_ram0_mem_init (& self) -> & HwassShrdRam0MemInit { & self . hwass_shrd_ram0_mem_init } # [doc = "0x68 - HWASS_SHRD_RAM0_MEM_INIT_DONE"]
# [inline (always)]
pub const fn hwass_shrd_ram0_mem_init_done (& self) -> & HwassShrdRam0MemInitDone { & self . hwass_shrd_ram0_mem_init_done } # [doc = "0x6c - HWASS_SHRD_RAM0_MEM_INIT_STATUS"]
# [inline (always)]
pub const fn hwass_shrd_ram0_mem_init_status (& self) -> & HwassShrdRam0MemInitStatus { & self . hwass_shrd_ram0_mem_init_status } # [doc = "0x70 - HWASS_SHRD_RAM1_MEM_INIT"]
# [inline (always)]
pub const fn hwass_shrd_ram1_mem_init (& self) -> & HwassShrdRam1MemInit { & self . hwass_shrd_ram1_mem_init } # [doc = "0x74 - HWASS_SHRD_RAM1_MEM_INIT_DONE"]
# [inline (always)]
pub const fn hwass_shrd_ram1_mem_init_done (& self) -> & HwassShrdRam1MemInitDone { & self . hwass_shrd_ram1_mem_init_done } # [doc = "0x78 - HWASS_SHRD_RAM1_MEM_INIT_STATUS"]
# [inline (always)]
pub const fn hwass_shrd_ram1_mem_init_status (& self) -> & HwassShrdRam1MemInitStatus { & self . hwass_shrd_ram1_mem_init_status } # [doc = "0x7c - APPSS_TPCC_MEMINIT_START"]
# [inline (always)]
pub const fn appss_tpcc_meminit_start (& self) -> & AppssTpccMeminitStart { & self . appss_tpcc_meminit_start } # [doc = "0x80 - APPSS_TPCC_MEMINIT_DONE"]
# [inline (always)]
pub const fn appss_tpcc_meminit_done (& self) -> & AppssTpccMeminitDone { & self . appss_tpcc_meminit_done } # [doc = "0x84 - APPSS_TPCC_MEMINIT_STATUS"]
# [inline (always)]
pub const fn appss_tpcc_meminit_status (& self) -> & AppssTpccMeminitStatus { & self . appss_tpcc_meminit_status } # [doc = "0x88 - APPSS_SPIA_CFG"]
# [inline (always)]
pub const fn appss_spia_cfg (& self) -> & AppssSpiaCfg { & self . appss_spia_cfg } # [doc = "0x8c - APPSS_SPIB_CFG"]
# [inline (always)]
pub const fn appss_spib_cfg (& self) -> & AppssSpibCfg { & self . appss_spib_cfg } # [doc = "0x90 - APPSS_EPWM_CFG"]
# [inline (always)]
pub const fn appss_epwm_cfg (& self) -> & AppssEpwmCfg { & self . appss_epwm_cfg } # [doc = "0x94 - RESERVED"]
# [inline (always)]
pub const fn reserved (& self) -> & Reserved { & self . reserved } # [doc = "0x98 - APPSS_MCAN_FE_AND_LIN_INTR_SEL"]
# [inline (always)]
pub const fn appss_mcan_fe_and_lin_intr_sel (& self) -> & AppssMcanFeAndLinIntrSel { & self . appss_mcan_fe_and_lin_intr_sel } # [doc = "0x9c - APPSS_MCANA_INT_CLR"]
# [inline (always)]
pub const fn appss_mcana_int_clr (& self) -> & AppssMcanaIntClr { & self . appss_mcana_int_clr } # [doc = "0xa0 - APPSS_MCANA_INT_MASK"]
# [inline (always)]
pub const fn appss_mcana_int_mask (& self) -> & AppssMcanaIntMask { & self . appss_mcana_int_mask } # [doc = "0xa4 - APPSS_MCANA_INT_STAT"]
# [inline (always)]
pub const fn appss_mcana_int_stat (& self) -> & AppssMcanaIntStat { & self . appss_mcana_int_stat } # [doc = "0xa8 - APPSS_CM4_GLOBAL_CONFIG"]
# [inline (always)]
pub const fn appss_cm4_global_config (& self) -> & AppssCm4GlobalConfig { & self . appss_cm4_global_config } # [doc = "0xac - RESERVED1"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0xb0 - APPSS_CM4_ROM_ECLIPSE"]
# [inline (always)]
pub const fn appss_cm4_rom_eclipse (& self) -> & AppssCm4RomEclipse { & self . appss_cm4_rom_eclipse } # [doc = "0xb4 - APPSS_CM4_STATUS_REG"]
# [inline (always)]
pub const fn appss_cm4_status_reg (& self) -> & AppssCm4StatusReg { & self . appss_cm4_status_reg } # [doc = "0xb8 - APPSS_AHB_CTRL"]
# [inline (always)]
pub const fn appss_ahb_ctrl (& self) -> & AppssAhbCtrl { & self . appss_ahb_ctrl } # [doc = "0xbc - ESM_GATING0"]
# [inline (always)]
pub const fn esm_gating0 (& self) -> & EsmGating0 { & self . esm_gating0 } # [doc = "0xc0 - ESM_GATING1"]
# [inline (always)]
pub const fn esm_gating1 (& self) -> & EsmGating1 { & self . esm_gating1 } # [doc = "0xc4 - ESM_GATING2"]
# [inline (always)]
pub const fn esm_gating2 (& self) -> & EsmGating2 { & self . esm_gating2 } # [doc = "0xc8 - ESM_GATING3"]
# [inline (always)]
pub const fn esm_gating3 (& self) -> & EsmGating3 { & self . esm_gating3 } # [doc = "0xcc - ESM_GATING4"]
# [inline (always)]
pub const fn esm_gating4 (& self) -> & EsmGating4 { & self . esm_gating4 } # [doc = "0xd0 - ESM_GATING5"]
# [inline (always)]
pub const fn esm_gating5 (& self) -> & EsmGating5 { & self . esm_gating5 } # [doc = "0xd4 - ESM_GATING6"]
# [inline (always)]
pub const fn esm_gating6 (& self) -> & EsmGating6 { & self . esm_gating6 } # [doc = "0xd8 - ESM_GATING7"]
# [inline (always)]
pub const fn esm_gating7 (& self) -> & EsmGating7 { & self . esm_gating7 } # [doc = "0xdc - APPSS_CM4_HALT"]
# [inline (always)]
pub const fn appss_cm4_halt (& self) -> & AppssCm4Halt { & self . appss_cm4_halt } # [doc = "0xe0 - APPSS_CM4_EVENT"]
# [inline (always)]
pub const fn appss_cm4_event (& self) -> & AppssCm4Event { & self . appss_cm4_event } # [doc = "0xe4 - SPIA_IO_CFG"]
# [inline (always)]
pub const fn spia_io_cfg (& self) -> & SpiaIoCfg { & self . spia_io_cfg } # [doc = "0xe8 - SPIB_IO_CFG"]
# [inline (always)]
pub const fn spib_io_cfg (& self) -> & SpibIoCfg { & self . spib_io_cfg } # [doc = "0xec - SPI_HOST_IRQ"]
# [inline (always)]
pub const fn spi_host_irq (& self) -> & SpiHostIrq { & self . spi_host_irq } # [doc = "0xf0 - TPTC_DBS_CONFIG"]
# [inline (always)]
pub const fn tptc_dbs_config (& self) -> & TptcDbsConfig { & self . tptc_dbs_config } # [doc = "0xf4 - TPCC_PARITY_CTRL"]
# [inline (always)]
pub const fn tpcc_parity_ctrl (& self) -> & TpccParityCtrl { & self . tpcc_parity_ctrl } # [doc = "0xf8 - TPCC_PARITY_STATUS"]
# [inline (always)]
pub const fn tpcc_parity_status (& self) -> & TpccParityStatus { & self . tpcc_parity_status } # [doc = "0xfc - APPSS_DBG_ACK_CTL0"]
# [inline (always)]
pub const fn appss_dbg_ack_ctl0 (& self) -> & AppssDbgAckCtl0 { & self . appss_dbg_ack_ctl0 } # [doc = "0x100 - DEBUGSS_CSETB_FLUSH"]
# [inline (always)]
pub const fn debugss_csetb_flush (& self) -> & DebugssCsetbFlush { & self . debugss_csetb_flush } # [doc = "0x104 - CPSW_CONTROL"]
# [inline (always)]
pub const fn cpsw_control (& self) -> & CpswControl { & self . cpsw_control } # [doc = "0x108 - APPSS_ERRAGG_MASK0"]
# [inline (always)]
pub const fn appss_erragg_mask0 (& self) -> & AppssErraggMask0 { & self . appss_erragg_mask0 } # [doc = "0x10c - APPSS_ERRAGG_STATUS0"]
# [inline (always)]
pub const fn appss_erragg_status0 (& self) -> & AppssErraggStatus0 { & self . appss_erragg_status0 } # [doc = "0x190 - APPSS_TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub const fn appss_tpcc_a_erragg_mask (& self) -> & AppssTpccAErraggMask { & self . appss_tpcc_a_erragg_mask } # [doc = "0x194 - APPSS_TPCC_A_ERRAGG_STATUS"]
# [inline (always)]
pub const fn appss_tpcc_a_erragg_status (& self) -> & AppssTpccAErraggStatus { & self . appss_tpcc_a_erragg_status } # [doc = "0x198 - APPSS_TPCC_A_ERRAGG_STATUS_RAW"]
# [inline (always)]
pub const fn appss_tpcc_a_erragg_status_raw (& self) -> & AppssTpccAErraggStatusRaw { & self . appss_tpcc_a_erragg_status_raw } # [doc = "0x214 - APPSS_TPCC_A_INTAGG_MASK"]
# [inline (always)]
pub const fn appss_tpcc_a_intagg_mask (& self) -> & AppssTpccAIntaggMask { & self . appss_tpcc_a_intagg_mask } # [doc = "0x218 - HW_SPARE_WPH"]
# [inline (always)]
pub const fn hw_spare_wph (& self) -> & HwSpareWph { & self . hw_spare_wph } # [doc = "0x21c - APPSS_TPCC_A_INTAGG_STATUS_RAW"]
# [inline (always)]
pub const fn appss_tpcc_a_intagg_status_raw (& self) -> & AppssTpccAIntaggStatusRaw { & self . appss_tpcc_a_intagg_status_raw } # [doc = "0x274 - APPSS_TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub const fn appss_tpcc_b_erragg_mask (& self) -> & AppssTpccBErraggMask { & self . appss_tpcc_b_erragg_mask } # [doc = "0x278 - APPSS_TPCC_B_ERRAGG_STATUS"]
# [inline (always)]
pub const fn appss_tpcc_b_erragg_status (& self) -> & AppssTpccBErraggStatus { & self . appss_tpcc_b_erragg_status } # [doc = "0x27c - APPSS_TPCC_B_ERRAGG_STATUS_RAW"]
# [inline (always)]
pub const fn appss_tpcc_b_erragg_status_raw (& self) -> & AppssTpccBErraggStatusRaw { & self . appss_tpcc_b_erragg_status_raw } # [doc = "0x2ec - APPSS_TPCC_B_INTAGG_MASK"]
# [inline (always)]
pub const fn appss_tpcc_b_intagg_mask (& self) -> & AppssTpccBIntaggMask { & self . appss_tpcc_b_intagg_mask } # [doc = "0x2f0 - APPSS_TPCC_B_INTAGG_STATUS"]
# [inline (always)]
pub const fn appss_tpcc_b_intagg_status (& self) -> & AppssTpccBIntaggStatus { & self . appss_tpcc_b_intagg_status } # [doc = "0x2f4 - APPSS_TPCC_B_INTAGG_STATUS_RAW"]
# [inline (always)]
pub const fn appss_tpcc_b_intagg_status_raw (& self) -> & AppssTpccBIntaggStatusRaw { & self . appss_tpcc_b_intagg_status_raw } # [doc = "0x2f8 - APPSS_MPU_ERRAGG_MASK"]
# [inline (always)]
pub const fn appss_mpu_erragg_mask (& self) -> & AppssMpuErraggMask { & self . appss_mpu_erragg_mask } # [doc = "0x2fc - APPSS_MPU_ERRAGG_STATUS"]
# [inline (always)]
pub const fn appss_mpu_erragg_status (& self) -> & AppssMpuErraggStatus { & self . appss_mpu_erragg_status } # [doc = "0x300 - APPSS_MPU_ERRAGG_STATUS_RAW"]
# [inline (always)]
pub const fn appss_mpu_erragg_status_raw (& self) -> & AppssMpuErraggStatusRaw { & self . appss_mpu_erragg_status_raw } # [doc = "0x304 - APPSS_QSPI_CONFIG"]
# [inline (always)]
pub const fn appss_qspi_config (& self) -> & AppssQspiConfig { & self . appss_qspi_config } # [doc = "0x308 - APPSS_CTI_TRIG_SEL"]
# [inline (always)]
pub const fn appss_cti_trig_sel (& self) -> & AppssCtiTrigSel { & self . appss_cti_trig_sel } # [doc = "0x30c - APPSS_DBGSS_CTI_TRIG_SEL"]
# [inline (always)]
pub const fn appss_dbgss_cti_trig_sel (& self) -> & AppssDbgssCtiTrigSel { & self . appss_dbgss_cti_trig_sel } # [doc = "0x310 - APPSS_BOOT_INFO_REG0"]
# [inline (always)]
pub const fn appss_boot_info_reg0 (& self) -> & AppssBootInfoReg0 { & self . appss_boot_info_reg0 } # [doc = "0x314 - APPSS_BOOT_INFO_REG1"]
# [inline (always)]
pub const fn appss_boot_info_reg1 (& self) -> & AppssBootInfoReg1 { & self . appss_boot_info_reg1 } # [doc = "0x318 - APPSS_BOOT_INFO_REG2"]
# [inline (always)]
pub const fn appss_boot_info_reg2 (& self) -> & AppssBootInfoReg2 { & self . appss_boot_info_reg2 } # [doc = "0x31c - APPSS_BOOT_INFO_REG3"]
# [inline (always)]
pub const fn appss_boot_info_reg3 (& self) -> & AppssBootInfoReg3 { & self . appss_boot_info_reg3 } # [doc = "0x320 - APPSS_BOOT_INFO_REG4"]
# [inline (always)]
pub const fn appss_boot_info_reg4 (& self) -> & AppssBootInfoReg4 { & self . appss_boot_info_reg4 } # [doc = "0x324 - APPSS_BOOT_INFO_REG5"]
# [inline (always)]
pub const fn appss_boot_info_reg5 (& self) -> & AppssBootInfoReg5 { & self . appss_boot_info_reg5 } # [doc = "0x328 - APPSS_BOOT_INFO_REG6"]
# [inline (always)]
pub const fn appss_boot_info_reg6 (& self) -> & AppssBootInfoReg6 { & self . appss_boot_info_reg6 } # [doc = "0x32c - APPSS_BOOT_INFO_REG7"]
# [inline (always)]
pub const fn appss_boot_info_reg7 (& self) -> & AppssBootInfoReg7 { & self . appss_boot_info_reg7 } # [doc = "0x330 - APPSS_TPTC_ECCAGGR_CLK_CNTRL"]
# [inline (always)]
pub const fn appss_tptc_eccaggr_clk_cntrl (& self) -> & AppssTptcEccaggrClkCntrl { & self . appss_tptc_eccaggr_clk_cntrl } # [doc = "0x334 - APPSS_TPTC_BOUNDARY_CFG"]
# [inline (always)]
pub const fn appss_tptc_boundary_cfg (& self) -> & AppssTptcBoundaryCfg { & self . appss_tptc_boundary_cfg } # [doc = "0x338 - APPSS_TPTC_XID_REORDER_CFG"]
# [inline (always)]
pub const fn appss_tptc_xid_reorder_cfg (& self) -> & AppssTptcXidReorderCfg { & self . appss_tptc_xid_reorder_cfg } # [doc = "0x33c - HW_Sync_FE_CTRL"]
# [inline (always)]
pub const fn hw_sync_fe_ctrl (& self) -> & HwSyncFeCtrl { & self . hw_sync_fe_ctrl } # [doc = "0x340 - HW_SPARE_REG1"]
# [inline (always)]
pub const fn hw_spare_reg1 (& self) -> & HwSpareReg1 { & self . hw_spare_reg1 } # [doc = "0x344 - HW_SPARE_REG2"]
# [inline (always)]
pub const fn hw_spare_reg2 (& self) -> & HwSpareReg2 { & self . hw_spare_reg2 } # [doc = "0x348 - HW_SPARE_REG3"]
# [inline (always)]
pub const fn hw_spare_reg3 (& self) -> & HwSpareReg3 { & self . hw_spare_reg3 } # [doc = "0x34c - NERROR_MASK"]
# [inline (always)]
pub const fn nerror_mask (& self) -> & NerrorMask { & self . nerror_mask } # [doc = "0x350 - HW_SPARE_RW0"]
# [inline (always)]
pub const fn hw_spare_rw0 (& self) -> & HwSpareRw0 { & self . hw_spare_rw0 } # [doc = "0x354 - HW_SPARE_RW1"]
# [inline (always)]
pub const fn hw_spare_rw1 (& self) -> & HwSpareRw1 { & self . hw_spare_rw1 } # [doc = "0x358 - HW_SPARE_RW2"]
# [inline (always)]
pub const fn hw_spare_rw2 (& self) -> & HwSpareRw2 { & self . hw_spare_rw2 } # [doc = "0x35c - HW_SPARE_RW3"]
# [inline (always)]
pub const fn hw_spare_rw3 (& self) -> & HwSpareRw3 { & self . hw_spare_rw3 } # [doc = "0x360 - HW_SPARE_RW4"]
# [inline (always)]
pub const fn hw_spare_rw4 (& self) -> & HwSpareRw4 { & self . hw_spare_rw4 } # [doc = "0x364 - HW_SPARE_RW5"]
# [inline (always)]
pub const fn hw_spare_rw5 (& self) -> & HwSpareRw5 { & self . hw_spare_rw5 } # [doc = "0x368 - HW_SPARE_RO0"]
# [inline (always)]
pub const fn hw_spare_ro0 (& self) -> & HwSpareRo0 { & self . hw_spare_ro0 } # [doc = "0x36c - HW_SPARE_RO1"]
# [inline (always)]
pub const fn hw_spare_ro1 (& self) -> & HwSpareRo1 { & self . hw_spare_ro1 } # [doc = "0x370 - HW_SPARE_RO2"]
# [inline (always)]
pub const fn hw_spare_ro2 (& self) -> & HwSpareRo2 { & self . hw_spare_ro2 } # [doc = "0x374 - HW_SPARE_RO3"]
# [inline (always)]
pub const fn hw_spare_ro3 (& self) -> & HwSpareRo3 { & self . hw_spare_ro3 } # [doc = "0x378 - HW_SPARE_REC"]
# [inline (always)]
pub const fn hw_spare_rec (& self) -> & HwSpareRec { & self . hw_spare_rec } # [doc = "0x37c - APP_CTRL"]
# [inline (always)]
pub const fn app_ctrl (& self) -> & AppCtrl { & self . app_ctrl } # [doc = "0x380 - WIC_CTRL"]
# [inline (always)]
pub const fn wic_ctrl (& self) -> & WicCtrl { & self . wic_ctrl } # [doc = "0x384 - WIC_STAT_CLR"]
# [inline (always)]
pub const fn wic_stat_clr (& self) -> & WicStatClr { & self . wic_stat_clr } # [doc = "0x388 - WIC_STAT"]
# [inline (always)]
pub const fn wic_stat (& self) -> & WicStat { & self . wic_stat } # [doc = "0x38c - WICEN"]
# [inline (always)]
pub const fn wicen (& self) -> & Wicen { & self . wicen } # [doc = "0x390 - FORCEFCLKACTIVE"]
# [inline (always)]
pub const fn forcefclkactive (& self) -> & Forcefclkactive { & self . forcefclkactive } # [doc = "0x394 - FECSS_CLK_GATE"]
# [inline (always)]
pub const fn fecss_clk_gate (& self) -> & FecssClkGate { & self . fecss_clk_gate } # [doc = "0x398 - APPSS_SHARED_MEM_CLK_GATE"]
# [inline (always)]
pub const fn appss_shared_mem_clk_gate (& self) -> & AppssSharedMemClkGate { & self . appss_shared_mem_clk_gate } # [doc = "0x39c - APPSS_MEM_INIT_SLICE_SEL"]
# [inline (always)]
pub const fn appss_mem_init_slice_sel (& self) -> & AppssMemInitSliceSel { & self . appss_mem_init_slice_sel } # [doc = "0x3a0 - APPSS_QSPI_CHAR_EXT_CLK_EN"]
# [inline (always)]
pub const fn appss_qspi_char_ext_clk_en (& self) -> & AppssQspiCharExtClkEn { & self . appss_qspi_char_ext_clk_en } # [doc = "0x3a4 - APPSS_QSPI_EXT_CLK_EN"]
# [inline (always)]
pub const fn appss_qspi_ext_clk_en (& self) -> & AppssQspiExtClkEn { & self . appss_qspi_ext_clk_en } # [doc = "0x3a8 - SPI1_SMART_IDLE"]
# [inline (always)]
pub const fn spi1_smart_idle (& self) -> & Spi1SmartIdle { & self . spi1_smart_idle } # [doc = "0x3ac - SPI2_SMART_IDLE"]
# [inline (always)]
pub const fn spi2_smart_idle (& self) -> & Spi2SmartIdle { & self . spi2_smart_idle } # [doc = "0x3b0 - CAN_SMART_IDLE"]
# [inline (always)]
pub const fn can_smart_idle (& self) -> & CanSmartIdle { & self . can_smart_idle } # [doc = "0x3b4 - LIN_SMART_IDLE"]
# [inline (always)]
pub const fn lin_smart_idle (& self) -> & LinSmartIdle { & self . lin_smart_idle } # [doc = "0x3b8 - HWASS_CLK_GATE"]
# [inline (always)]
pub const fn hwass_clk_gate (& self) -> & HwassClkGate { & self . hwass_clk_gate } # [doc = "0x3bc - CFG_TIMEOUT_PCR3"]
# [inline (always)]
pub const fn cfg_timeout_pcr3 (& self) -> & CfgTimeoutPcr3 { & self . cfg_timeout_pcr3 } # [doc = "0x3c0 - RESERVED0"]
# [inline (always)]
pub const fn reserved0 (& self) -> & Reserved0 { & self . reserved0 } # [doc = "0x3c4 - APPSS_ERRAGG_MASK1"]
# [inline (always)]
pub const fn appss_erragg_mask1 (& self) -> & AppssErraggMask1 { & self . appss_erragg_mask1 } # [doc = "0x3c8 - APPSS_ERRAGG_STATUS1"]
# [inline (always)]
pub const fn appss_erragg_status1 (& self) -> & AppssErraggStatus1 { & self . appss_erragg_status1 } # [doc = "0x3cc - FORCEHCLKACTIVE"]
# [inline (always)]
pub const fn forcehclkactive (& self) -> & Forcehclkactive { & self . forcehclkactive } # [doc = "0x3d0 - APPSS_RAM1_OWRITE_ERR"]
# [inline (always)]
pub const fn appss_ram1_owrite_err (& self) -> & AppssRam1OwriteErr { & self . appss_ram1_owrite_err } # [doc = "0x3d4 - APPSS_RAM1_OWRITE_ERR_ADDR"]
# [inline (always)]
pub const fn appss_ram1_owrite_err_addr (& self) -> & AppssRam1OwriteErrAddr { & self . appss_ram1_owrite_err_addr } # [doc = "0x3d8 - APPSS_RAM2_OWRITE_ERR"]
# [inline (always)]
pub const fn appss_ram2_owrite_err (& self) -> & AppssRam2OwriteErr { & self . appss_ram2_owrite_err } # [doc = "0x3dc - APPSS_RAM2_OWRITE_ERR_ADDR"]
# [inline (always)]
pub const fn appss_ram2_owrite_err_addr (& self) -> & AppssRam2OwriteErrAddr { & self . appss_ram2_owrite_err_addr } # [doc = "0x3e0 - APPSS_RAM3_OWRITE_ERR"]
# [inline (always)]
pub const fn appss_ram3_owrite_err (& self) -> & AppssRam3OwriteErr { & self . appss_ram3_owrite_err } # [doc = "0x3e4 - APPSS_RAM3_OWRITE_ERR_ADDR"]
# [inline (always)]
pub const fn appss_ram3_owrite_err_addr (& self) -> & AppssRam3OwriteErrAddr { & self . appss_ram3_owrite_err_addr } # [doc = "0x3e8 - APPSS_SHRD_RAM_OWRITE_ERR"]
# [inline (always)]
pub const fn appss_shrd_ram_owrite_err (& self) -> & AppssShrdRamOwriteErr { & self . appss_shrd_ram_owrite_err } # [doc = "0x3ec - APPSS_SHRD_RAM_OWRITE_ERR_ADDR"]
# [inline (always)]
pub const fn appss_shrd_ram_owrite_err_addr (& self) -> & AppssShrdRamOwriteErrAddr { & self . appss_shrd_ram_owrite_err_addr } # [doc = "0x3f0 - APPSS_OWRITE_ERR_AGGR"]
# [inline (always)]
pub const fn appss_owrite_err_aggr (& self) -> & AppssOwriteErrAggr { & self . appss_owrite_err_aggr } # [doc = "0x3f4 - HW_SPARE_RW6"]
# [inline (always)]
pub const fn hw_spare_rw6 (& self) -> & HwSpareRw6 { & self . hw_spare_rw6 } # [doc = "0x3f8 - HW_SPARE_RW7"]
# [inline (always)]
pub const fn hw_spare_rw7 (& self) -> & HwSpareRw7 { & self . hw_spare_rw7 } # [doc = "0x3fc - HW_SPARE_RW8"]
# [inline (always)]
pub const fn hw_spare_rw8 (& self) -> & HwSpareRw8 { & self . hw_spare_rw8 } # [doc = "0x400 - HW_SPARE_RW9"]
# [inline (always)]
pub const fn hw_spare_rw9 (& self) -> & HwSpareRw9 { & self . hw_spare_rw9 } # [doc = "0x404 - HW_SPARE_HWA_RW0"]
# [inline (always)]
pub const fn hw_spare_hwa_rw0 (& self) -> & HwSpareHwaRw0 { & self . hw_spare_hwa_rw0 } # [doc = "0x1008 - - KICK0 component"]
# [inline (always)]
pub const fn lock0_kick0 (& self) -> & Lock0Kick0 { & self . lock0_kick0 } # [doc = "0x100c - - KICK1 component"]
# [inline (always)]
pub const fn lock0_kick1 (& self) -> & Lock0Kick1 { & self . lock0_kick1 } # [doc = "0x1010 - Interrupt Raw Status/Set Register"]
# [inline (always)]
pub const fn intr_raw_status (& self) -> & IntrRawStatus { & self . intr_raw_status } # [doc = "0x1014 - Interrupt Enabled Status/Clear register"]
# [inline (always)]
pub const fn intr_enabled_status_clear (& self) -> & IntrEnabledStatusClear { & self . intr_enabled_status_clear } # [doc = "0x1018 - Interrupt Enable register"]
# [inline (always)]
pub const fn intr_enable (& self) -> & IntrEnable { & self . intr_enable } # [doc = "0x101c - Interrupt Enable Clear register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x1020 - EOI register"]
# [inline (always)]
pub const fn eoi (& self) -> & Eoi { & self . eoi } # [doc = "0x1024 - Fault Address register"]
# [inline (always)]
pub const fn fault_address (& self) -> & FaultAddress { & self . fault_address } # [doc = "0x1028 - Fault Type Status register"]
# [inline (always)]
pub const fn fault_type_status (& self) -> & FaultTypeStatus { & self . fault_type_status } # [doc = "0x102c - Fault Attribute Status register"]
# [inline (always)]
pub const fn fault_attr_status (& self) -> & FaultAttrStatus { & self . fault_attr_status } # [doc = "0x1030 - Fault Clear register"]
# [inline (always)]
pub const fn fault_clear (& self) -> & FaultClear { & self . fault_clear } } # [doc = "PID (rw) register accessor: PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `PID_W6_O0` reader - "]
pub type PidW6O0R = crate :: FieldReader ; # [doc = "Field `PID_W6_O0` writer - "]
pub type PidW6O0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PID_W2_O6` reader - "]
pub type PidW2O6R = crate :: FieldReader ; # [doc = "Field `PID_W2_O6` writer - "]
pub type PidW2O6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PID_W3_O8` reader - "]
pub type PidW3O8R = crate :: FieldReader ; # [doc = "Field `PID_W3_O8` writer - "]
pub type PidW3O8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PID_W5_O11` reader - "]
pub type PidW5O11R = crate :: FieldReader ; # [doc = "Field `PID_W5_O11` writer - "]
pub type PidW5O11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PID_W16_O16` reader - "]
pub type PidW16O16R = crate :: FieldReader < u16 > ; # [doc = "Field `PID_W16_O16` writer - "]
pub type PidW16O16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5"]
# [inline (always)]
pub fn pid_w6_o0 (& self) -> PidW6O0R { PidW6O0R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7"]
# [inline (always)]
pub fn pid_w2_o6 (& self) -> PidW2O6R { PidW2O6R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10"]
# [inline (always)]
pub fn pid_w3_o8 (& self) -> PidW3O8R { PidW3O8R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15"]
# [inline (always)]
pub fn pid_w5_o11 (& self) -> PidW5O11R { PidW5O11R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn pid_w16_o16 (& self) -> PidW16O16R { PidW16O16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5"]
# [inline (always)]
# [must_use]
pub fn pid_w6_o0 (& mut self) -> PidW6O0W < PidSpec > { PidW6O0W :: new (self , 0) } # [doc = "Bits 6:7"]
# [inline (always)]
# [must_use]
pub fn pid_w2_o6 (& mut self) -> PidW2O6W < PidSpec > { PidW2O6W :: new (self , 6) } # [doc = "Bits 8:10"]
# [inline (always)]
# [must_use]
pub fn pid_w3_o8 (& mut self) -> PidW3O8W < PidSpec > { PidW3O8W :: new (self , 8) } # [doc = "Bits 11:15"]
# [inline (always)]
# [must_use]
pub fn pid_w5_o11 (& mut self) -> PidW5O11W < PidSpec > { PidW5O11W :: new (self , 11) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn pid_w16_o16 (& mut self) -> PidW16O16W < PidSpec > { PidW16O16W :: new (self , 16) } } # [doc = "PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG0 (rw) register accessor: HW_REG0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg0`]
module"]
# [doc (alias = "HW_REG0")]
pub type HwReg0 = crate :: Reg < hw_reg0 :: HwReg0Spec > ; # [doc = "HW_REG0"]
pub mod hw_reg0 { # [doc = "Register `HW_REG0` reader"]
pub type R = crate :: R < HwReg0Spec > ; # [doc = "Register `HW_REG0` writer"]
pub type W = crate :: W < HwReg0Spec > ; # [doc = "Field `hwreg0` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg0R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg0` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg0 (& self) -> Hwreg0R { Hwreg0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg0 (& mut self) -> Hwreg0W < HwReg0Spec > { Hwreg0W :: new (self , 0) } } # [doc = "HW_REG0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg0Spec ; impl crate :: RegisterSpec for HwReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg0::R`](R) reader structure"]
impl crate :: Readable for HwReg0Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg0::W`](W) writer structure"]
impl crate :: Writable for HwReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG0 to value 0"]
impl crate :: Resettable for HwReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG1 (rw) register accessor: HW_REG1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg1`]
module"]
# [doc (alias = "HW_REG1")]
pub type HwReg1 = crate :: Reg < hw_reg1 :: HwReg1Spec > ; # [doc = "HW_REG1"]
pub mod hw_reg1 { # [doc = "Register `HW_REG1` reader"]
pub type R = crate :: R < HwReg1Spec > ; # [doc = "Register `HW_REG1` writer"]
pub type W = crate :: W < HwReg1Spec > ; # [doc = "Field `hwreg1` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg1R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg1` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg1 (& self) -> Hwreg1R { Hwreg1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg1 (& mut self) -> Hwreg1W < HwReg1Spec > { Hwreg1W :: new (self , 0) } } # [doc = "HW_REG1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg1Spec ; impl crate :: RegisterSpec for HwReg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg1::R`](R) reader structure"]
impl crate :: Readable for HwReg1Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg1::W`](W) writer structure"]
impl crate :: Writable for HwReg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG1 to value 0"]
impl crate :: Resettable for HwReg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PREVIOUS_NAME (rw) register accessor: PREVIOUS_NAME\n\nYou can [`read`](crate::Reg::read) this register and get [`previous_name::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`previous_name::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@previous_name`]
module"]
# [doc (alias = "PREVIOUS_NAME")]
pub type PreviousName = crate :: Reg < previous_name :: PreviousNameSpec > ; # [doc = "PREVIOUS_NAME"]
pub mod previous_name { # [doc = "Register `PREVIOUS_NAME` reader"]
pub type R = crate :: R < PreviousNameSpec > ; # [doc = "Register `PREVIOUS_NAME` writer"]
pub type W = crate :: W < PreviousNameSpec > ; # [doc = "Field `hwreg2` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg2R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg2` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg2 (& self) -> Hwreg2R { Hwreg2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg2 (& mut self) -> Hwreg2W < PreviousNameSpec > { Hwreg2W :: new (self , 0) } } # [doc = "PREVIOUS_NAME\n\nYou can [`read`](crate::Reg::read) this register and get [`previous_name::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`previous_name::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PreviousNameSpec ; impl crate :: RegisterSpec for PreviousNameSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`previous_name::R`](R) reader structure"]
impl crate :: Readable for PreviousNameSpec { } # [doc = "`write(|w| ..)` method takes [`previous_name::W`](W) writer structure"]
impl crate :: Writable for PreviousNameSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PREVIOUS_NAME to value 0"]
impl crate :: Resettable for PreviousNameSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG3 (rw) register accessor: HW_REG3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg3`]
module"]
# [doc (alias = "HW_REG3")]
pub type HwReg3 = crate :: Reg < hw_reg3 :: HwReg3Spec > ; # [doc = "HW_REG3"]
pub mod hw_reg3 { # [doc = "Register `HW_REG3` reader"]
pub type R = crate :: R < HwReg3Spec > ; # [doc = "Register `HW_REG3` writer"]
pub type W = crate :: W < HwReg3Spec > ; # [doc = "Field `hwreg3` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg3R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg3` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg3 (& self) -> Hwreg3R { Hwreg3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg3 (& mut self) -> Hwreg3W < HwReg3Spec > { Hwreg3W :: new (self , 0) } } # [doc = "HW_REG3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg3Spec ; impl crate :: RegisterSpec for HwReg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg3::R`](R) reader structure"]
impl crate :: Readable for HwReg3Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg3::W`](W) writer structure"]
impl crate :: Writable for HwReg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG3 to value 0"]
impl crate :: Resettable for HwReg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG4 (rw) register accessor: HW_REG4\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg4`]
module"]
# [doc (alias = "HW_REG4")]
pub type HwReg4 = crate :: Reg < hw_reg4 :: HwReg4Spec > ; # [doc = "HW_REG4"]
pub mod hw_reg4 { # [doc = "Register `HW_REG4` reader"]
pub type R = crate :: R < HwReg4Spec > ; # [doc = "Register `HW_REG4` writer"]
pub type W = crate :: W < HwReg4Spec > ; # [doc = "Field `hwreg4` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg4R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg4` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg4 (& self) -> Hwreg4R { Hwreg4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg4 (& mut self) -> Hwreg4W < HwReg4Spec > { Hwreg4W :: new (self , 0) } } # [doc = "HW_REG4\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg4Spec ; impl crate :: RegisterSpec for HwReg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg4::R`](R) reader structure"]
impl crate :: Readable for HwReg4Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg4::W`](W) writer structure"]
impl crate :: Writable for HwReg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG4 to value 0"]
impl crate :: Resettable for HwReg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG5 (rw) register accessor: HW_REG5\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg5`]
module"]
# [doc (alias = "HW_REG5")]
pub type HwReg5 = crate :: Reg < hw_reg5 :: HwReg5Spec > ; # [doc = "HW_REG5"]
pub mod hw_reg5 { # [doc = "Register `HW_REG5` reader"]
pub type R = crate :: R < HwReg5Spec > ; # [doc = "Register `HW_REG5` writer"]
pub type W = crate :: W < HwReg5Spec > ; # [doc = "Field `hwreg5` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg5R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg5` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg5 (& self) -> Hwreg5R { Hwreg5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg5 (& mut self) -> Hwreg5W < HwReg5Spec > { Hwreg5W :: new (self , 0) } } # [doc = "HW_REG5\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg5Spec ; impl crate :: RegisterSpec for HwReg5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg5::R`](R) reader structure"]
impl crate :: Readable for HwReg5Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg5::W`](W) writer structure"]
impl crate :: Writable for HwReg5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG5 to value 0"]
impl crate :: Resettable for HwReg5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG6 (rw) register accessor: HW_REG6\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg6`]
module"]
# [doc (alias = "HW_REG6")]
pub type HwReg6 = crate :: Reg < hw_reg6 :: HwReg6Spec > ; # [doc = "HW_REG6"]
pub mod hw_reg6 { # [doc = "Register `HW_REG6` reader"]
pub type R = crate :: R < HwReg6Spec > ; # [doc = "Register `HW_REG6` writer"]
pub type W = crate :: W < HwReg6Spec > ; # [doc = "Field `hwreg6` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg6R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg6` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg6 (& self) -> Hwreg6R { Hwreg6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg6 (& mut self) -> Hwreg6W < HwReg6Spec > { Hwreg6W :: new (self , 0) } } # [doc = "HW_REG6\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg6Spec ; impl crate :: RegisterSpec for HwReg6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg6::R`](R) reader structure"]
impl crate :: Readable for HwReg6Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg6::W`](W) writer structure"]
impl crate :: Writable for HwReg6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG6 to value 0"]
impl crate :: Resettable for HwReg6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG7 (rw) register accessor: HW_REG7\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg7`]
module"]
# [doc (alias = "HW_REG7")]
pub type HwReg7 = crate :: Reg < hw_reg7 :: HwReg7Spec > ; # [doc = "HW_REG7"]
pub mod hw_reg7 { # [doc = "Register `HW_REG7` reader"]
pub type R = crate :: R < HwReg7Spec > ; # [doc = "Register `HW_REG7` writer"]
pub type W = crate :: W < HwReg7Spec > ; # [doc = "Field `hwreg7` reader - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg7R = crate :: FieldReader < u32 > ; # [doc = "Field `hwreg7` writer - 31:0\\]
HW reserved Regsiter"]
pub type Hwreg7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
pub fn hwreg7 (& self) -> Hwreg7R { Hwreg7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
HW reserved Regsiter"]
# [inline (always)]
# [must_use]
pub fn hwreg7 (& mut self) -> Hwreg7W < HwReg7Spec > { Hwreg7W :: new (self , 0) } } # [doc = "HW_REG7\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg7Spec ; impl crate :: RegisterSpec for HwReg7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg7::R`](R) reader structure"]
impl crate :: Readable for HwReg7Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg7::W`](W) writer structure"]
impl crate :: Writable for HwReg7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG7 to value 0"]
impl crate :: Resettable for HwReg7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SW_INT (rw) register accessor: APPSS_SW_INT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_sw_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_sw_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_sw_int`]
module"]
# [doc (alias = "APPSS_SW_INT")]
pub type AppssSwInt = crate :: Reg < appss_sw_int :: AppssSwIntSpec > ; # [doc = "APPSS_SW_INT"]
pub mod appss_sw_int { # [doc = "Register `APPSS_SW_INT` reader"]
pub type R = crate :: R < AppssSwIntSpec > ; # [doc = "Register `APPSS_SW_INT` writer"]
pub type W = crate :: W < AppssSwIntSpec > ; # [doc = "Field `pulse` reader - 3:0\\]
Write_pulse bit field: writing 1'b1 to each bit will trigger SW_INT&lt;0-3> respectively to CM4."]
pub type PulseR = crate :: FieldReader ; # [doc = "Field `pulse` writer - 3:0\\]
Write_pulse bit field: writing 1'b1 to each bit will trigger SW_INT&lt;0-3> respectively to CM4."]
pub type PulseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Write_pulse bit field: writing 1'b1 to each bit will trigger SW_INT&lt;0-3> respectively to CM4."]
# [inline (always)]
pub fn pulse (& self) -> PulseR { PulseR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Write_pulse bit field: writing 1'b1 to each bit will trigger SW_INT&lt;0-3> respectively to CM4."]
# [inline (always)]
# [must_use]
pub fn pulse (& mut self) -> PulseW < AppssSwIntSpec > { PulseW :: new (self , 0) } } # [doc = "APPSS_SW_INT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_sw_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_sw_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssSwIntSpec ; impl crate :: RegisterSpec for AppssSwIntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_sw_int::R`](R) reader structure"]
impl crate :: Readable for AppssSwIntSpec { } # [doc = "`write(|w| ..)` method takes [`appss_sw_int::W`](W) writer structure"]
impl crate :: Writable for AppssSwIntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SW_INT to value 0"]
impl crate :: Resettable for AppssSwIntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_IPC_RFS (rw) register accessor: APPSS_IPC_RFS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ipc_rfs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ipc_rfs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ipc_rfs`]
module"]
# [doc (alias = "APPSS_IPC_RFS")]
pub type AppssIpcRfs = crate :: Reg < appss_ipc_rfs :: AppssIpcRfsSpec > ; # [doc = "APPSS_IPC_RFS"]
pub mod appss_ipc_rfs { # [doc = "Register `APPSS_IPC_RFS` reader"]
pub type R = crate :: R < AppssIpcRfsSpec > ; # [doc = "Register `APPSS_IPC_RFS` writer"]
pub type W = crate :: W < AppssIpcRfsSpec > ; # [doc = "Field `host_intr` reader - 3:0\\]
Write_pulse bit field: Writing 1'b1 to each bit will trigger HOST_INTR &lt;0-3> respectively to CM3."]
pub type HostIntrR = crate :: FieldReader ; # [doc = "Field `host_intr` writer - 3:0\\]
Write_pulse bit field: Writing 1'b1 to each bit will trigger HOST_INTR &lt;0-3> respectively to CM3."]
pub type HostIntrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `command` reader - 31:4\\]
Used by software to communicate commands and response. It is 7-bits per interrupt."]
pub type CommandR = crate :: FieldReader < u32 > ; # [doc = "Field `command` writer - 31:4\\]
Used by software to communicate commands and response. It is 7-bits per interrupt."]
pub type CommandW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Write_pulse bit field: Writing 1'b1 to each bit will trigger HOST_INTR &lt;0-3> respectively to CM3."]
# [inline (always)]
pub fn host_intr (& self) -> HostIntrR { HostIntrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Used by software to communicate commands and response. It is 7-bits per interrupt."]
# [inline (always)]
pub fn command (& self) -> CommandR { CommandR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Write_pulse bit field: Writing 1'b1 to each bit will trigger HOST_INTR &lt;0-3> respectively to CM3."]
# [inline (always)]
# [must_use]
pub fn host_intr (& mut self) -> HostIntrW < AppssIpcRfsSpec > { HostIntrW :: new (self , 0) } # [doc = "Bits 4:31 - 31:4\\]
Used by software to communicate commands and response. It is 7-bits per interrupt."]
# [inline (always)]
# [must_use]
pub fn command (& mut self) -> CommandW < AppssIpcRfsSpec > { CommandW :: new (self , 4) } } # [doc = "APPSS_IPC_RFS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ipc_rfs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ipc_rfs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssIpcRfsSpec ; impl crate :: RegisterSpec for AppssIpcRfsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ipc_rfs::R`](R) reader structure"]
impl crate :: Readable for AppssIpcRfsSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ipc_rfs::W`](W) writer structure"]
impl crate :: Writable for AppssIpcRfsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_IPC_RFS to value 0"]
impl crate :: Resettable for AppssIpcRfsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CAPEVNT_SEL (rw) register accessor: APPSS_CAPEVNT_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_capevnt_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_capevnt_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_capevnt_sel`]
module"]
# [doc (alias = "APPSS_CAPEVNT_SEL")]
pub type AppssCapevntSel = crate :: Reg < appss_capevnt_sel :: AppssCapevntSelSpec > ; # [doc = "APPSS_CAPEVNT_SEL"]
pub mod appss_capevnt_sel { # [doc = "Register `APPSS_CAPEVNT_SEL` reader"]
pub type R = crate :: R < AppssCapevntSelSpec > ; # [doc = "Register `APPSS_CAPEVNT_SEL` writer"]
pub type W = crate :: W < AppssCapevntSelSpec > ; # [doc = "Field `src0` reader - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
pub type Src0R = crate :: FieldReader < u16 > ; # [doc = "Field `src0` writer - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
pub type Src0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `src1` reader - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
pub type Src1R = crate :: FieldReader < u16 > ; # [doc = "Field `src1` writer - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
pub type Src1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
# [inline (always)]
pub fn src0 (& self) -> Src0R { Src0R :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:23 - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
# [inline (always)]
pub fn src1 (& self) -> Src1R { Src1R :: new (((self . bits >> 12) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0"]
# [inline (always)]
# [must_use]
pub fn src0 (& mut self) -> Src0W < AppssCapevntSelSpec > { Src0W :: new (self , 0) } # [doc = "Bits 12:23 - 23:12\\]
5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1"]
# [inline (always)]
# [must_use]
pub fn src1 (& mut self) -> Src1W < AppssCapevntSelSpec > { Src1W :: new (self , 12) } } # [doc = "APPSS_CAPEVNT_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_capevnt_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_capevnt_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCapevntSelSpec ; impl crate :: RegisterSpec for AppssCapevntSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_capevnt_sel::R`](R) reader structure"]
impl crate :: Readable for AppssCapevntSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_capevnt_sel::W`](W) writer structure"]
impl crate :: Writable for AppssCapevntSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CAPEVNT_SEL to value 0"]
impl crate :: Resettable for AppssCapevntSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_DMA_REQ_SEL (rw) register accessor: APPSS_DMA_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dma_req_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dma_req_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_dma_req_sel`]
module"]
# [doc (alias = "APPSS_DMA_REQ_SEL")]
pub type AppssDmaReqSel = crate :: Reg < appss_dma_req_sel :: AppssDmaReqSelSpec > ; # [doc = "APPSS_DMA_REQ_SEL"]
pub mod appss_dma_req_sel { # [doc = "Register `APPSS_DMA_REQ_SEL` reader"]
pub type R = crate :: R < AppssDmaReqSelSpec > ; # [doc = "Register `APPSS_DMA_REQ_SEL` writer"]
pub type W = crate :: W < AppssDmaReqSelSpec > ; # [doc = "Field `select` reader - 31:0\\]
Reserved for R&amp;D. Do not touch"]
pub type SelectR = crate :: FieldReader < u32 > ; # [doc = "Field `select` writer - 31:0\\]
Reserved for R&amp;D. Do not touch"]
pub type SelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for R&amp;D. Do not touch"]
# [inline (always)]
pub fn select (& self) -> SelectR { SelectR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for R&amp;D. Do not touch"]
# [inline (always)]
# [must_use]
pub fn select (& mut self) -> SelectW < AppssDmaReqSelSpec > { SelectW :: new (self , 0) } } # [doc = "APPSS_DMA_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dma_req_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dma_req_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssDmaReqSelSpec ; impl crate :: RegisterSpec for AppssDmaReqSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_dma_req_sel::R`](R) reader structure"]
impl crate :: Readable for AppssDmaReqSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_dma_req_sel::W`](W) writer structure"]
impl crate :: Writable for AppssDmaReqSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_DMA_REQ_SEL to value 0"]
impl crate :: Resettable for AppssDmaReqSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_DMA1_REQ_SEL (rw) register accessor: APPSS_DMA1_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dma1_req_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dma1_req_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_dma1_req_sel`]
module"]
# [doc (alias = "APPSS_DMA1_REQ_SEL")]
pub type AppssDma1ReqSel = crate :: Reg < appss_dma1_req_sel :: AppssDma1ReqSelSpec > ; # [doc = "APPSS_DMA1_REQ_SEL"]
pub mod appss_dma1_req_sel { # [doc = "Register `APPSS_DMA1_REQ_SEL` reader"]
pub type R = crate :: R < AppssDma1ReqSelSpec > ; # [doc = "Register `APPSS_DMA1_REQ_SEL` writer"]
pub type W = crate :: W < AppssDma1ReqSelSpec > ; # [doc = "Field `select` reader - 31:0\\]
Reserved for R&amp;D. Do not touch"]
pub type SelectR = crate :: FieldReader < u32 > ; # [doc = "Field `select` writer - 31:0\\]
Reserved for R&amp;D. Do not touch"]
pub type SelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for R&amp;D. Do not touch"]
# [inline (always)]
pub fn select (& self) -> SelectR { SelectR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for R&amp;D. Do not touch"]
# [inline (always)]
# [must_use]
pub fn select (& mut self) -> SelectW < AppssDma1ReqSelSpec > { SelectW :: new (self , 0) } } # [doc = "APPSS_DMA1_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dma1_req_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dma1_req_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssDma1ReqSelSpec ; impl crate :: RegisterSpec for AppssDma1ReqSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_dma1_req_sel::R`](R) reader structure"]
impl crate :: Readable for AppssDma1ReqSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_dma1_req_sel::W`](W) writer structure"]
impl crate :: Writable for AppssDma1ReqSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_DMA1_REQ_SEL to value 0"]
impl crate :: Resettable for AppssDma1ReqSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_IRQ_REQ_SEL (rw) register accessor: APPSS_IRQ_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_irq_req_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_irq_req_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_irq_req_sel`]
module"]
# [doc (alias = "APPSS_IRQ_REQ_SEL")]
pub type AppssIrqReqSel = crate :: Reg < appss_irq_req_sel :: AppssIrqReqSelSpec > ; # [doc = "APPSS_IRQ_REQ_SEL"]
pub mod appss_irq_req_sel { # [doc = "Register `APPSS_IRQ_REQ_SEL` reader"]
pub type R = crate :: R < AppssIrqReqSelSpec > ; # [doc = "Register `APPSS_IRQ_REQ_SEL` writer"]
pub type W = crate :: W < AppssIrqReqSelSpec > ; # [doc = "Field `select` reader - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
pub type SelectR = crate :: FieldReader < u32 > ; # [doc = "Field `select` writer - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
pub type SelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
# [inline (always)]
pub fn select (& self) -> SelectR { SelectR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18"]
# [inline (always)]
# [must_use]
pub fn select (& mut self) -> SelectW < AppssIrqReqSelSpec > { SelectW :: new (self , 0) } } # [doc = "APPSS_IRQ_REQ_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_irq_req_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_irq_req_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssIrqReqSelSpec ; impl crate :: RegisterSpec for AppssIrqReqSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_irq_req_sel::R`](R) reader structure"]
impl crate :: Readable for AppssIrqReqSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_irq_req_sel::W`](W) writer structure"]
impl crate :: Writable for AppssIrqReqSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_IRQ_REQ_SEL to value 0"]
impl crate :: Resettable for AppssIrqReqSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SPI_TRIG_SRC (rw) register accessor: APPSS_SPI_TRIG_SRC\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_spi_trig_src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_spi_trig_src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_spi_trig_src`]
module"]
# [doc (alias = "APPSS_SPI_TRIG_SRC")]
pub type AppssSpiTrigSrc = crate :: Reg < appss_spi_trig_src :: AppssSpiTrigSrcSpec > ; # [doc = "APPSS_SPI_TRIG_SRC"]
pub mod appss_spi_trig_src { # [doc = "Register `APPSS_SPI_TRIG_SRC` reader"]
pub type R = crate :: R < AppssSpiTrigSrcSpec > ; # [doc = "Register `APPSS_SPI_TRIG_SRC` writer"]
pub type W = crate :: W < AppssSpiTrigSrcSpec > ; # [doc = "Field `trig_spia` reader - 1:0\\]
RESERVED"]
pub type TrigSpiaR = crate :: FieldReader ; # [doc = "Field `trig_spia` writer - 1:0\\]
RESERVED"]
pub type TrigSpiaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `trig_spib` reader - 26:16\\]
RESERVED"]
pub type TrigSpibR = crate :: FieldReader < u16 > ; # [doc = "Field `trig_spib` writer - 26:16\\]
RESERVED"]
pub type TrigSpibW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
RESERVED"]
# [inline (always)]
pub fn trig_spia (& self) -> TrigSpiaR { TrigSpiaR :: new ((self . bits & 3) as u8) } # [doc = "Bits 16:26 - 26:16\\]
RESERVED"]
# [inline (always)]
pub fn trig_spib (& self) -> TrigSpibR { TrigSpibR :: new (((self . bits >> 16) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn trig_spia (& mut self) -> TrigSpiaW < AppssSpiTrigSrcSpec > { TrigSpiaW :: new (self , 0) } # [doc = "Bits 16:26 - 26:16\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn trig_spib (& mut self) -> TrigSpibW < AppssSpiTrigSrcSpec > { TrigSpibW :: new (self , 16) } } # [doc = "APPSS_SPI_TRIG_SRC\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_spi_trig_src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_spi_trig_src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssSpiTrigSrcSpec ; impl crate :: RegisterSpec for AppssSpiTrigSrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_spi_trig_src::R`](R) reader structure"]
impl crate :: Readable for AppssSpiTrigSrcSpec { } # [doc = "`write(|w| ..)` method takes [`appss_spi_trig_src::W`](W) writer structure"]
impl crate :: Writable for AppssSpiTrigSrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SPI_TRIG_SRC to value 0"]
impl crate :: Resettable for AppssSpiTrigSrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM1A_MEM_INIT (rw) register accessor: APPSS_RAM1A_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1a_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1a_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram1a_mem_init`]
module"]
# [doc (alias = "APPSS_RAM1A_MEM_INIT")]
pub type AppssRam1aMemInit = crate :: Reg < appss_ram1a_mem_init :: AppssRam1aMemInitSpec > ; # [doc = "APPSS_RAM1A_MEM_INIT"]
pub mod appss_ram1a_mem_init { # [doc = "Register `APPSS_RAM1A_MEM_INIT` reader"]
pub type R = crate :: R < AppssRam1aMemInitSpec > ; # [doc = "Register `APPSS_RAM1A_MEM_INIT` writer"]
pub type W = crate :: W < AppssRam1aMemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM1 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM1 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM1 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM1 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < AppssRam1aMemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "APPSS_RAM1A_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1a_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1a_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam1aMemInitSpec ; impl crate :: RegisterSpec for AppssRam1aMemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram1a_mem_init::R`](R) reader structure"]
impl crate :: Readable for AppssRam1aMemInitSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram1a_mem_init::W`](W) writer structure"]
impl crate :: Writable for AppssRam1aMemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM1A_MEM_INIT to value 0"]
impl crate :: Resettable for AppssRam1aMemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM1A_MEM_INIT_DONE (rw) register accessor: APPSS_RAM1A_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1a_mem_init_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1a_mem_init_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram1a_mem_init_done`]
module"]
# [doc (alias = "APPSS_RAM1A_MEM_INIT_DONE")]
pub type AppssRam1aMemInitDone = crate :: Reg < appss_ram1a_mem_init_done :: AppssRam1aMemInitDoneSpec > ; # [doc = "APPSS_RAM1A_MEM_INIT_DONE"]
pub mod appss_ram1a_mem_init_done { # [doc = "Register `APPSS_RAM1A_MEM_INIT_DONE` reader"]
pub type R = crate :: R < AppssRam1aMemInitDoneSpec > ; # [doc = "Register `APPSS_RAM1A_MEM_INIT_DONE` writer"]
pub type W = crate :: W < AppssRam1aMemInitDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once initialization of APPSS_RAM1 partion0 banks is finished. Writing '1' would clear the bit."]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once initialization of APPSS_RAM1 partion0 banks is finished. Writing '1' would clear the bit."]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of APPSS_RAM1 partion0 banks is finished. Writing '1' would clear the bit."]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of APPSS_RAM1 partion0 banks is finished. Writing '1' would clear the bit."]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < AppssRam1aMemInitDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "APPSS_RAM1A_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1a_mem_init_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1a_mem_init_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam1aMemInitDoneSpec ; impl crate :: RegisterSpec for AppssRam1aMemInitDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram1a_mem_init_done::R`](R) reader structure"]
impl crate :: Readable for AppssRam1aMemInitDoneSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram1a_mem_init_done::W`](W) writer structure"]
impl crate :: Writable for AppssRam1aMemInitDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM1A_MEM_INIT_DONE to value 0"]
impl crate :: Resettable for AppssRam1aMemInitDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM1A_MEM_INIT_STATUS (rw) register accessor: APPSS_RAM1A_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1a_mem_init_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1a_mem_init_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram1a_mem_init_status`]
module"]
# [doc (alias = "APPSS_RAM1A_MEM_INIT_STATUS")]
pub type AppssRam1aMemInitStatus = crate :: Reg < appss_ram1a_mem_init_status :: AppssRam1aMemInitStatusSpec > ; # [doc = "APPSS_RAM1A_MEM_INIT_STATUS"]
pub mod appss_ram1a_mem_init_status { # [doc = "Register `APPSS_RAM1A_MEM_INIT_STATUS` reader"]
pub type R = crate :: R < AppssRam1aMemInitStatusSpec > ; # [doc = "Register `APPSS_RAM1A_MEM_INIT_STATUS` writer"]
pub type W = crate :: W < AppssRam1aMemInitStatusSpec > ; # [doc = "Field `mem_status` reader - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM1 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM1 partion0 bank"]
pub type MemStatusR = crate :: BitReader ; # [doc = "Field `mem_status` writer - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM1 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM1 partion0 bank"]
pub type MemStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM1 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM1 partion0 bank"]
# [inline (always)]
pub fn mem_status (& self) -> MemStatusR { MemStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM1 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM1 partion0 bank"]
# [inline (always)]
# [must_use]
pub fn mem_status (& mut self) -> MemStatusW < AppssRam1aMemInitStatusSpec > { MemStatusW :: new (self , 0) } } # [doc = "APPSS_RAM1A_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1a_mem_init_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1a_mem_init_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam1aMemInitStatusSpec ; impl crate :: RegisterSpec for AppssRam1aMemInitStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram1a_mem_init_status::R`](R) reader structure"]
impl crate :: Readable for AppssRam1aMemInitStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram1a_mem_init_status::W`](W) writer structure"]
impl crate :: Writable for AppssRam1aMemInitStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM1A_MEM_INIT_STATUS to value 0"]
impl crate :: Resettable for AppssRam1aMemInitStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM2A_MEM_INIT (rw) register accessor: APPSS_RAM2A_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2a_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2a_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram2a_mem_init`]
module"]
# [doc (alias = "APPSS_RAM2A_MEM_INIT")]
pub type AppssRam2aMemInit = crate :: Reg < appss_ram2a_mem_init :: AppssRam2aMemInitSpec > ; # [doc = "APPSS_RAM2A_MEM_INIT"]
pub mod appss_ram2a_mem_init { # [doc = "Register `APPSS_RAM2A_MEM_INIT` reader"]
pub type R = crate :: R < AppssRam2aMemInitSpec > ; # [doc = "Register `APPSS_RAM2A_MEM_INIT` writer"]
pub type W = crate :: W < AppssRam2aMemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM2 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM2 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM2 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM2 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < AppssRam2aMemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "APPSS_RAM2A_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2a_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2a_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam2aMemInitSpec ; impl crate :: RegisterSpec for AppssRam2aMemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram2a_mem_init::R`](R) reader structure"]
impl crate :: Readable for AppssRam2aMemInitSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram2a_mem_init::W`](W) writer structure"]
impl crate :: Writable for AppssRam2aMemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM2A_MEM_INIT to value 0"]
impl crate :: Resettable for AppssRam2aMemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM2A_MEM_INIT_DONE (rw) register accessor: APPSS_RAM2A_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2a_mem_init_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2a_mem_init_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram2a_mem_init_done`]
module"]
# [doc (alias = "APPSS_RAM2A_MEM_INIT_DONE")]
pub type AppssRam2aMemInitDone = crate :: Reg < appss_ram2a_mem_init_done :: AppssRam2aMemInitDoneSpec > ; # [doc = "APPSS_RAM2A_MEM_INIT_DONE"]
pub mod appss_ram2a_mem_init_done { # [doc = "Register `APPSS_RAM2A_MEM_INIT_DONE` reader"]
pub type R = crate :: R < AppssRam2aMemInitDoneSpec > ; # [doc = "Register `APPSS_RAM2A_MEM_INIT_DONE` writer"]
pub type W = crate :: W < AppssRam2aMemInitDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once initialization of APPSS_RAM2 partion0 banks is finished. Writing '1' would clear the bit."]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once initialization of APPSS_RAM2 partion0 banks is finished. Writing '1' would clear the bit."]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of APPSS_RAM2 partion0 banks is finished. Writing '1' would clear the bit."]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of APPSS_RAM2 partion0 banks is finished. Writing '1' would clear the bit."]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < AppssRam2aMemInitDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "APPSS_RAM2A_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2a_mem_init_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2a_mem_init_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam2aMemInitDoneSpec ; impl crate :: RegisterSpec for AppssRam2aMemInitDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram2a_mem_init_done::R`](R) reader structure"]
impl crate :: Readable for AppssRam2aMemInitDoneSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram2a_mem_init_done::W`](W) writer structure"]
impl crate :: Writable for AppssRam2aMemInitDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM2A_MEM_INIT_DONE to value 0"]
impl crate :: Resettable for AppssRam2aMemInitDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM2A_MEM_INIT_STATUS (rw) register accessor: APPSS_RAM2A_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2a_mem_init_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2a_mem_init_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram2a_mem_init_status`]
module"]
# [doc (alias = "APPSS_RAM2A_MEM_INIT_STATUS")]
pub type AppssRam2aMemInitStatus = crate :: Reg < appss_ram2a_mem_init_status :: AppssRam2aMemInitStatusSpec > ; # [doc = "APPSS_RAM2A_MEM_INIT_STATUS"]
pub mod appss_ram2a_mem_init_status { # [doc = "Register `APPSS_RAM2A_MEM_INIT_STATUS` reader"]
pub type R = crate :: R < AppssRam2aMemInitStatusSpec > ; # [doc = "Register `APPSS_RAM2A_MEM_INIT_STATUS` writer"]
pub type W = crate :: W < AppssRam2aMemInitStatusSpec > ; # [doc = "Field `mem_status` reader - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM2 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM2 partion0 bank"]
pub type MemStatusR = crate :: BitReader ; # [doc = "Field `mem_status` writer - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM2 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM2 partion0 bank"]
pub type MemStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM2 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM2 partion0 bank"]
# [inline (always)]
pub fn mem_status (& self) -> MemStatusR { MemStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM2 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM2 partion0 bank"]
# [inline (always)]
# [must_use]
pub fn mem_status (& mut self) -> MemStatusW < AppssRam2aMemInitStatusSpec > { MemStatusW :: new (self , 0) } } # [doc = "APPSS_RAM2A_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2a_mem_init_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2a_mem_init_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam2aMemInitStatusSpec ; impl crate :: RegisterSpec for AppssRam2aMemInitStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram2a_mem_init_status::R`](R) reader structure"]
impl crate :: Readable for AppssRam2aMemInitStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram2a_mem_init_status::W`](W) writer structure"]
impl crate :: Writable for AppssRam2aMemInitStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM2A_MEM_INIT_STATUS to value 0"]
impl crate :: Resettable for AppssRam2aMemInitStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM3A_MEM_INIT (rw) register accessor: APPSS_RAM3A_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3a_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3a_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram3a_mem_init`]
module"]
# [doc (alias = "APPSS_RAM3A_MEM_INIT")]
pub type AppssRam3aMemInit = crate :: Reg < appss_ram3a_mem_init :: AppssRam3aMemInitSpec > ; # [doc = "APPSS_RAM3A_MEM_INIT"]
pub mod appss_ram3a_mem_init { # [doc = "Register `APPSS_RAM3A_MEM_INIT` reader"]
pub type R = crate :: R < AppssRam3aMemInitSpec > ; # [doc = "Register `APPSS_RAM3A_MEM_INIT` writer"]
pub type W = crate :: W < AppssRam3aMemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM3 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM3 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM3 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM3 partion0 bank. Value in each row is initialized to 0x0C_0000_0000"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < AppssRam3aMemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "APPSS_RAM3A_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3a_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3a_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam3aMemInitSpec ; impl crate :: RegisterSpec for AppssRam3aMemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram3a_mem_init::R`](R) reader structure"]
impl crate :: Readable for AppssRam3aMemInitSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram3a_mem_init::W`](W) writer structure"]
impl crate :: Writable for AppssRam3aMemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM3A_MEM_INIT to value 0"]
impl crate :: Resettable for AppssRam3aMemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM3A_MEM_INIT_DONE (rw) register accessor: APPSS_RAM3A_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3a_mem_init_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3a_mem_init_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram3a_mem_init_done`]
module"]
# [doc (alias = "APPSS_RAM3A_MEM_INIT_DONE")]
pub type AppssRam3aMemInitDone = crate :: Reg < appss_ram3a_mem_init_done :: AppssRam3aMemInitDoneSpec > ; # [doc = "APPSS_RAM3A_MEM_INIT_DONE"]
pub mod appss_ram3a_mem_init_done { # [doc = "Register `APPSS_RAM3A_MEM_INIT_DONE` reader"]
pub type R = crate :: R < AppssRam3aMemInitDoneSpec > ; # [doc = "Register `APPSS_RAM3A_MEM_INIT_DONE` writer"]
pub type W = crate :: W < AppssRam3aMemInitDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once initialization of APPSS_RAM3 partion0 banks is finished. Writing '1' would clear the bit."]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once initialization of APPSS_RAM3 partion0 banks is finished. Writing '1' would clear the bit."]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of APPSS_RAM3 partion0 banks is finished. Writing '1' would clear the bit."]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of APPSS_RAM3 partion0 banks is finished. Writing '1' would clear the bit."]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < AppssRam3aMemInitDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "APPSS_RAM3A_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3a_mem_init_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3a_mem_init_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam3aMemInitDoneSpec ; impl crate :: RegisterSpec for AppssRam3aMemInitDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram3a_mem_init_done::R`](R) reader structure"]
impl crate :: Readable for AppssRam3aMemInitDoneSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram3a_mem_init_done::W`](W) writer structure"]
impl crate :: Writable for AppssRam3aMemInitDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM3A_MEM_INIT_DONE to value 0"]
impl crate :: Resettable for AppssRam3aMemInitDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM3A_MEM_INIT_STATUS (rw) register accessor: APPSS_RAM3A_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3a_mem_init_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3a_mem_init_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram3a_mem_init_status`]
module"]
# [doc (alias = "APPSS_RAM3A_MEM_INIT_STATUS")]
pub type AppssRam3aMemInitStatus = crate :: Reg < appss_ram3a_mem_init_status :: AppssRam3aMemInitStatusSpec > ; # [doc = "APPSS_RAM3A_MEM_INIT_STATUS"]
pub mod appss_ram3a_mem_init_status { # [doc = "Register `APPSS_RAM3A_MEM_INIT_STATUS` reader"]
pub type R = crate :: R < AppssRam3aMemInitStatusSpec > ; # [doc = "Register `APPSS_RAM3A_MEM_INIT_STATUS` writer"]
pub type W = crate :: W < AppssRam3aMemInitStatusSpec > ; # [doc = "Field `mem_status` reader - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM3 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM3 partion0 bank"]
pub type MemStatusR = crate :: BitReader ; # [doc = "Field `mem_status` writer - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM3 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM3 partion0 bank"]
pub type MemStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM3 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM3 partion0 bank"]
# [inline (always)]
pub fn mem_status (& self) -> MemStatusR { MemStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for APPSS_RAM3 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM3 partion0 bank"]
# [inline (always)]
# [must_use]
pub fn mem_status (& mut self) -> MemStatusW < AppssRam3aMemInitStatusSpec > { MemStatusW :: new (self , 0) } } # [doc = "APPSS_RAM3A_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3a_mem_init_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3a_mem_init_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam3aMemInitStatusSpec ; impl crate :: RegisterSpec for AppssRam3aMemInitStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram3a_mem_init_status::R`](R) reader structure"]
impl crate :: Readable for AppssRam3aMemInitStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram3a_mem_init_status::W`](W) writer structure"]
impl crate :: Writable for AppssRam3aMemInitStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM3A_MEM_INIT_STATUS to value 0"]
impl crate :: Resettable for AppssRam3aMemInitStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM0_MEM_INIT (rw) register accessor: HWASS_SHRD_RAM0_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram0_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram0_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram0_mem_init`]
module"]
# [doc (alias = "HWASS_SHRD_RAM0_MEM_INIT")]
pub type HwassShrdRam0MemInit = crate :: Reg < hwass_shrd_ram0_mem_init :: HwassShrdRam0MemInitSpec > ; # [doc = "HWASS_SHRD_RAM0_MEM_INIT"]
pub mod hwass_shrd_ram0_mem_init { # [doc = "Register `HWASS_SHRD_RAM0_MEM_INIT` reader"]
pub type R = crate :: R < HwassShrdRam0MemInitSpec > ; # [doc = "Register `HWASS_SHRD_RAM0_MEM_INIT` writer"]
pub type W = crate :: W < HwassShrdRam0MemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition0. Value in each row is initialized to 0x0"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition0. Value in each row is initialized to 0x0"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition0. Value in each row is initialized to 0x0"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition0. Value in each row is initialized to 0x0"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < HwassShrdRam0MemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM0_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram0_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram0_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRam0MemInitSpec ; impl crate :: RegisterSpec for HwassShrdRam0MemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram0_mem_init::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRam0MemInitSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram0_mem_init::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRam0MemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM0_MEM_INIT to value 0"]
impl crate :: Resettable for HwassShrdRam0MemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM0_MEM_INIT_DONE (rw) register accessor: HWASS_SHRD_RAM0_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram0_mem_init_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram0_mem_init_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram0_mem_init_done`]
module"]
# [doc (alias = "HWASS_SHRD_RAM0_MEM_INIT_DONE")]
pub type HwassShrdRam0MemInitDone = crate :: Reg < hwass_shrd_ram0_mem_init_done :: HwassShrdRam0MemInitDoneSpec > ; # [doc = "HWASS_SHRD_RAM0_MEM_INIT_DONE"]
pub mod hwass_shrd_ram0_mem_init_done { # [doc = "Register `HWASS_SHRD_RAM0_MEM_INIT_DONE` reader"]
pub type R = crate :: R < HwassShrdRam0MemInitDoneSpec > ; # [doc = "Register `HWASS_SHRD_RAM0_MEM_INIT_DONE` writer"]
pub type W = crate :: W < HwassShrdRam0MemInitDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition0 is finished. Writing '1' would clear the bit"]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition0 is finished. Writing '1' would clear the bit"]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition0 is finished. Writing '1' would clear the bit"]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition0 is finished. Writing '1' would clear the bit"]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < HwassShrdRam0MemInitDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM0_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram0_mem_init_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram0_mem_init_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRam0MemInitDoneSpec ; impl crate :: RegisterSpec for HwassShrdRam0MemInitDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram0_mem_init_done::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRam0MemInitDoneSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram0_mem_init_done::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRam0MemInitDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM0_MEM_INIT_DONE to value 0"]
impl crate :: Resettable for HwassShrdRam0MemInitDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM0_MEM_INIT_STATUS (rw) register accessor: HWASS_SHRD_RAM0_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram0_mem_init_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram0_mem_init_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram0_mem_init_status`]
module"]
# [doc (alias = "HWASS_SHRD_RAM0_MEM_INIT_STATUS")]
pub type HwassShrdRam0MemInitStatus = crate :: Reg < hwass_shrd_ram0_mem_init_status :: HwassShrdRam0MemInitStatusSpec > ; # [doc = "HWASS_SHRD_RAM0_MEM_INIT_STATUS"]
pub mod hwass_shrd_ram0_mem_init_status { # [doc = "Register `HWASS_SHRD_RAM0_MEM_INIT_STATUS` reader"]
pub type R = crate :: R < HwassShrdRam0MemInitStatusSpec > ; # [doc = "Register `HWASS_SHRD_RAM0_MEM_INIT_STATUS` writer"]
pub type W = crate :: W < HwassShrdRam0MemInitStatusSpec > ; # [doc = "Field `mem_status` reader - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition0 1'b1: Initialization is in progress for HWASS Shared RAM parition0"]
pub type MemStatusR = crate :: BitReader ; # [doc = "Field `mem_status` writer - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition0 1'b1: Initialization is in progress for HWASS Shared RAM parition0"]
pub type MemStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition0 1'b1: Initialization is in progress for HWASS Shared RAM parition0"]
# [inline (always)]
pub fn mem_status (& self) -> MemStatusR { MemStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition0 1'b1: Initialization is in progress for HWASS Shared RAM parition0"]
# [inline (always)]
# [must_use]
pub fn mem_status (& mut self) -> MemStatusW < HwassShrdRam0MemInitStatusSpec > { MemStatusW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM0_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram0_mem_init_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram0_mem_init_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRam0MemInitStatusSpec ; impl crate :: RegisterSpec for HwassShrdRam0MemInitStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram0_mem_init_status::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRam0MemInitStatusSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram0_mem_init_status::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRam0MemInitStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM0_MEM_INIT_STATUS to value 0"]
impl crate :: Resettable for HwassShrdRam0MemInitStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM1_MEM_INIT (rw) register accessor: HWASS_SHRD_RAM1_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram1_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram1_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram1_mem_init`]
module"]
# [doc (alias = "HWASS_SHRD_RAM1_MEM_INIT")]
pub type HwassShrdRam1MemInit = crate :: Reg < hwass_shrd_ram1_mem_init :: HwassShrdRam1MemInitSpec > ; # [doc = "HWASS_SHRD_RAM1_MEM_INIT"]
pub mod hwass_shrd_ram1_mem_init { # [doc = "Register `HWASS_SHRD_RAM1_MEM_INIT` reader"]
pub type R = crate :: R < HwassShrdRam1MemInitSpec > ; # [doc = "Register `HWASS_SHRD_RAM1_MEM_INIT` writer"]
pub type W = crate :: W < HwassShrdRam1MemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition1. Value in each row is initialized to 0x0"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition1. Value in each row is initialized to 0x0"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition1. Value in each row is initialized to 0x0"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition1. Value in each row is initialized to 0x0"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < HwassShrdRam1MemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM1_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram1_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram1_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRam1MemInitSpec ; impl crate :: RegisterSpec for HwassShrdRam1MemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram1_mem_init::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRam1MemInitSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram1_mem_init::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRam1MemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM1_MEM_INIT to value 0"]
impl crate :: Resettable for HwassShrdRam1MemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM1_MEM_INIT_DONE (rw) register accessor: HWASS_SHRD_RAM1_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram1_mem_init_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram1_mem_init_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram1_mem_init_done`]
module"]
# [doc (alias = "HWASS_SHRD_RAM1_MEM_INIT_DONE")]
pub type HwassShrdRam1MemInitDone = crate :: Reg < hwass_shrd_ram1_mem_init_done :: HwassShrdRam1MemInitDoneSpec > ; # [doc = "HWASS_SHRD_RAM1_MEM_INIT_DONE"]
pub mod hwass_shrd_ram1_mem_init_done { # [doc = "Register `HWASS_SHRD_RAM1_MEM_INIT_DONE` reader"]
pub type R = crate :: R < HwassShrdRam1MemInitDoneSpec > ; # [doc = "Register `HWASS_SHRD_RAM1_MEM_INIT_DONE` writer"]
pub type W = crate :: W < HwassShrdRam1MemInitDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition1 is finished. Writing '1' would clear the bit"]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition1 is finished. Writing '1' would clear the bit"]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition1 is finished. Writing '1' would clear the bit"]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once intialization of HWASS Shared RAM parition1 is finished. Writing '1' would clear the bit"]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < HwassShrdRam1MemInitDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM1_MEM_INIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram1_mem_init_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram1_mem_init_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRam1MemInitDoneSpec ; impl crate :: RegisterSpec for HwassShrdRam1MemInitDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram1_mem_init_done::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRam1MemInitDoneSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram1_mem_init_done::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRam1MemInitDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM1_MEM_INIT_DONE to value 0"]
impl crate :: Resettable for HwassShrdRam1MemInitDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM1_MEM_INIT_STATUS (rw) register accessor: HWASS_SHRD_RAM1_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram1_mem_init_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram1_mem_init_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram1_mem_init_status`]
module"]
# [doc (alias = "HWASS_SHRD_RAM1_MEM_INIT_STATUS")]
pub type HwassShrdRam1MemInitStatus = crate :: Reg < hwass_shrd_ram1_mem_init_status :: HwassShrdRam1MemInitStatusSpec > ; # [doc = "HWASS_SHRD_RAM1_MEM_INIT_STATUS"]
pub mod hwass_shrd_ram1_mem_init_status { # [doc = "Register `HWASS_SHRD_RAM1_MEM_INIT_STATUS` reader"]
pub type R = crate :: R < HwassShrdRam1MemInitStatusSpec > ; # [doc = "Register `HWASS_SHRD_RAM1_MEM_INIT_STATUS` writer"]
pub type W = crate :: W < HwassShrdRam1MemInitStatusSpec > ; # [doc = "Field `mem_status` reader - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition1 1'b1: Initialization is in progress for HWASS Shared RAM parition1"]
pub type MemStatusR = crate :: BitReader ; # [doc = "Field `mem_status` writer - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition1 1'b1: Initialization is in progress for HWASS Shared RAM parition1"]
pub type MemStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition1 1'b1: Initialization is in progress for HWASS Shared RAM parition1"]
# [inline (always)]
pub fn mem_status (& self) -> MemStatusR { MemStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for HWASS Shared RAM parition1 1'b1: Initialization is in progress for HWASS Shared RAM parition1"]
# [inline (always)]
# [must_use]
pub fn mem_status (& mut self) -> MemStatusW < HwassShrdRam1MemInitStatusSpec > { MemStatusW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM1_MEM_INIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram1_mem_init_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram1_mem_init_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRam1MemInitStatusSpec ; impl crate :: RegisterSpec for HwassShrdRam1MemInitStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram1_mem_init_status::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRam1MemInitStatusSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram1_mem_init_status::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRam1MemInitStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM1_MEM_INIT_STATUS to value 0"]
impl crate :: Resettable for HwassShrdRam1MemInitStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_MEMINIT_START (rw) register accessor: APPSS_TPCC_MEMINIT_START\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_meminit_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_meminit_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_meminit_start`]
module"]
# [doc (alias = "APPSS_TPCC_MEMINIT_START")]
pub type AppssTpccMeminitStart = crate :: Reg < appss_tpcc_meminit_start :: AppssTpccMeminitStartSpec > ; # [doc = "APPSS_TPCC_MEMINIT_START"]
pub mod appss_tpcc_meminit_start { # [doc = "Register `APPSS_TPCC_MEMINIT_START` reader"]
pub type R = crate :: R < AppssTpccMeminitStartSpec > ; # [doc = "Register `APPSS_TPCC_MEMINIT_START` writer"]
pub type W = crate :: W < AppssTpccMeminitStartSpec > ; # [doc = "Field `tpcc_a_meminit_start` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCA"]
pub type TpccAMeminitStartR = crate :: BitReader ; # [doc = "Field `tpcc_a_meminit_start` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCA"]
pub type TpccAMeminitStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_meminit_start` reader - 16:16\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCB"]
pub type TpccBMeminitStartR = crate :: BitReader ; # [doc = "Field `tpcc_b_meminit_start` writer - 16:16\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCB"]
pub type TpccBMeminitStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCA"]
# [inline (always)]
pub fn tpcc_a_meminit_start (& self) -> TpccAMeminitStartR { TpccAMeminitStartR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCB"]
# [inline (always)]
pub fn tpcc_b_meminit_start (& self) -> TpccBMeminitStartR { TpccBMeminitStartR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCA"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_meminit_start (& mut self) -> TpccAMeminitStartW < AppssTpccMeminitStartSpec > { TpccAMeminitStartW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
Write_pulse bit field: Writing 1'b1 will start initializing the TPCCB"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_meminit_start (& mut self) -> TpccBMeminitStartW < AppssTpccMeminitStartSpec > { TpccBMeminitStartW :: new (self , 16) } } # [doc = "APPSS_TPCC_MEMINIT_START\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_meminit_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_meminit_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccMeminitStartSpec ; impl crate :: RegisterSpec for AppssTpccMeminitStartSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_meminit_start::R`](R) reader structure"]
impl crate :: Readable for AppssTpccMeminitStartSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_meminit_start::W`](W) writer structure"]
impl crate :: Writable for AppssTpccMeminitStartSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_MEMINIT_START to value 0"]
impl crate :: Resettable for AppssTpccMeminitStartSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_MEMINIT_DONE (rw) register accessor: APPSS_TPCC_MEMINIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_meminit_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_meminit_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_meminit_done`]
module"]
# [doc (alias = "APPSS_TPCC_MEMINIT_DONE")]
pub type AppssTpccMeminitDone = crate :: Reg < appss_tpcc_meminit_done :: AppssTpccMeminitDoneSpec > ; # [doc = "APPSS_TPCC_MEMINIT_DONE"]
pub mod appss_tpcc_meminit_done { # [doc = "Register `APPSS_TPCC_MEMINIT_DONE` reader"]
pub type R = crate :: R < AppssTpccMeminitDoneSpec > ; # [doc = "Register `APPSS_TPCC_MEMINIT_DONE` writer"]
pub type W = crate :: W < AppssTpccMeminitDoneSpec > ; # [doc = "Field `tpcc_a_meminit_done` reader - 0:0\\]
This field will be high once intialization of TPCCA is finished. Writing '1' would clear the bit"]
pub type TpccAMeminitDoneR = crate :: BitReader ; # [doc = "Field `tpcc_a_meminit_done` writer - 0:0\\]
This field will be high once intialization of TPCCA is finished. Writing '1' would clear the bit"]
pub type TpccAMeminitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_meminit_done` reader - 16:16\\]
This field will be high once intialization of TPCCB is finished. Writing '1' would clear the bit"]
pub type TpccBMeminitDoneR = crate :: BitReader ; # [doc = "Field `tpcc_b_meminit_done` writer - 16:16\\]
This field will be high once intialization of TPCCB is finished. Writing '1' would clear the bit"]
pub type TpccBMeminitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once intialization of TPCCA is finished. Writing '1' would clear the bit"]
# [inline (always)]
pub fn tpcc_a_meminit_done (& self) -> TpccAMeminitDoneR { TpccAMeminitDoneR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
This field will be high once intialization of TPCCB is finished. Writing '1' would clear the bit"]
# [inline (always)]
pub fn tpcc_b_meminit_done (& self) -> TpccBMeminitDoneR { TpccBMeminitDoneR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once intialization of TPCCA is finished. Writing '1' would clear the bit"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_meminit_done (& mut self) -> TpccAMeminitDoneW < AppssTpccMeminitDoneSpec > { TpccAMeminitDoneW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
This field will be high once intialization of TPCCB is finished. Writing '1' would clear the bit"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_meminit_done (& mut self) -> TpccBMeminitDoneW < AppssTpccMeminitDoneSpec > { TpccBMeminitDoneW :: new (self , 16) } } # [doc = "APPSS_TPCC_MEMINIT_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_meminit_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_meminit_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccMeminitDoneSpec ; impl crate :: RegisterSpec for AppssTpccMeminitDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_meminit_done::R`](R) reader structure"]
impl crate :: Readable for AppssTpccMeminitDoneSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_meminit_done::W`](W) writer structure"]
impl crate :: Writable for AppssTpccMeminitDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_MEMINIT_DONE to value 0"]
impl crate :: Resettable for AppssTpccMeminitDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_MEMINIT_STATUS (rw) register accessor: APPSS_TPCC_MEMINIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_meminit_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_meminit_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_meminit_status`]
module"]
# [doc (alias = "APPSS_TPCC_MEMINIT_STATUS")]
pub type AppssTpccMeminitStatus = crate :: Reg < appss_tpcc_meminit_status :: AppssTpccMeminitStatusSpec > ; # [doc = "APPSS_TPCC_MEMINIT_STATUS"]
pub mod appss_tpcc_meminit_status { # [doc = "Register `APPSS_TPCC_MEMINIT_STATUS` reader"]
pub type R = crate :: R < AppssTpccMeminitStatusSpec > ; # [doc = "Register `APPSS_TPCC_MEMINIT_STATUS` writer"]
pub type W = crate :: W < AppssTpccMeminitStatusSpec > ; # [doc = "Field `tpcc_a_meminit_status` reader - 0:0\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
pub type TpccAMeminitStatusR = crate :: BitReader ; # [doc = "Field `tpcc_a_meminit_status` writer - 0:0\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
pub type TpccAMeminitStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_meminit_status` reader - 16:16\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
pub type TpccBMeminitStatusR = crate :: BitReader ; # [doc = "Field `tpcc_b_meminit_status` writer - 16:16\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
pub type TpccBMeminitStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
# [inline (always)]
pub fn tpcc_a_meminit_status (& self) -> TpccAMeminitStatusR { TpccAMeminitStatusR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
# [inline (always)]
pub fn tpcc_b_meminit_status (& self) -> TpccBMeminitStatusR { TpccBMeminitStatusR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_meminit_status (& mut self) -> TpccAMeminitStatusW < AppssTpccMeminitStatusSpec > { TpccAMeminitStatusW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_meminit_status (& mut self) -> TpccBMeminitStatusW < AppssTpccMeminitStatusSpec > { TpccBMeminitStatusW :: new (self , 16) } } # [doc = "APPSS_TPCC_MEMINIT_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_meminit_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_meminit_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccMeminitStatusSpec ; impl crate :: RegisterSpec for AppssTpccMeminitStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_meminit_status::R`](R) reader structure"]
impl crate :: Readable for AppssTpccMeminitStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_meminit_status::W`](W) writer structure"]
impl crate :: Writable for AppssTpccMeminitStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_MEMINIT_STATUS to value 0"]
impl crate :: Resettable for AppssTpccMeminitStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SPIA_CFG (rw) register accessor: APPSS_SPIA_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_spia_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_spia_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_spia_cfg`]
module"]
# [doc (alias = "APPSS_SPIA_CFG")]
pub type AppssSpiaCfg = crate :: Reg < appss_spia_cfg :: AppssSpiaCfgSpec > ; # [doc = "APPSS_SPIA_CFG"]
pub mod appss_spia_cfg { # [doc = "Register `APPSS_SPIA_CFG` reader"]
pub type R = crate :: R < AppssSpiaCfgSpec > ; # [doc = "Register `APPSS_SPIA_CFG` writer"]
pub type W = crate :: W < AppssSpiaCfgSpec > ; # [doc = "Field `spiasync2sen` reader - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
pub type Spiasync2senR = crate :: BitReader ; # [doc = "Field `spiasync2sen` writer - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
pub type Spiasync2senW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spia_cs_trigsrc_en` reader - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
pub type SpiaCsTrigsrcEnR = crate :: BitReader ; # [doc = "Field `spia_cs_trigsrc_en` writer - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
pub type SpiaCsTrigsrcEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spia_trig_gate_en` reader - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
pub type SpiaTrigGateEnR = crate :: BitReader ; # [doc = "Field `spia_trig_gate_en` writer - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
pub type SpiaTrigGateEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spia_int_trig_polarity` reader - 24:24\\]
SPIA trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
pub type SpiaIntTrigPolarityR = crate :: BitReader ; # [doc = "Field `spia_int_trig_polarity` writer - 24:24\\]
SPIA trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
pub type SpiaIntTrigPolarityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spia_iodft_en` reader - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
pub type SpiaIodftEnR = crate :: BitReader ; # [doc = "Field `spia_iodft_en` writer - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
pub type SpiaIodftEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
# [inline (always)]
pub fn spiasync2sen (& self) -> Spiasync2senR { Spiasync2senR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
# [inline (always)]
pub fn spia_cs_trigsrc_en (& self) -> SpiaCsTrigsrcEnR { SpiaCsTrigsrcEnR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
# [inline (always)]
pub fn spia_trig_gate_en (& self) -> SpiaTrigGateEnR { SpiaTrigGateEnR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
SPIA trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
# [inline (always)]
pub fn spia_int_trig_polarity (& self) -> SpiaIntTrigPolarityR { SpiaIntTrigPolarityR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
# [inline (always)]
pub fn spia_iodft_en (& self) -> SpiaIodftEnR { SpiaIodftEnR :: new (((self . bits >> 28) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
# [inline (always)]
# [must_use]
pub fn spiasync2sen (& mut self) -> Spiasync2senW < AppssSpiaCfgSpec > { Spiasync2senW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
# [inline (always)]
# [must_use]
pub fn spia_cs_trigsrc_en (& mut self) -> SpiaCsTrigsrcEnW < AppssSpiaCfgSpec > { SpiaCsTrigsrcEnW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
# [inline (always)]
# [must_use]
pub fn spia_trig_gate_en (& mut self) -> SpiaTrigGateEnW < AppssSpiaCfgSpec > { SpiaTrigGateEnW :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
SPIA trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
# [inline (always)]
# [must_use]
pub fn spia_int_trig_polarity (& mut self) -> SpiaIntTrigPolarityW < AppssSpiaCfgSpec > { SpiaIntTrigPolarityW :: new (self , 24) } # [doc = "Bit 28 - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
# [inline (always)]
# [must_use]
pub fn spia_iodft_en (& mut self) -> SpiaIodftEnW < AppssSpiaCfgSpec > { SpiaIodftEnW :: new (self , 28) } } # [doc = "APPSS_SPIA_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_spia_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_spia_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssSpiaCfgSpec ; impl crate :: RegisterSpec for AppssSpiaCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_spia_cfg::R`](R) reader structure"]
impl crate :: Readable for AppssSpiaCfgSpec { } # [doc = "`write(|w| ..)` method takes [`appss_spia_cfg::W`](W) writer structure"]
impl crate :: Writable for AppssSpiaCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SPIA_CFG to value 0"]
impl crate :: Resettable for AppssSpiaCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SPIB_CFG (rw) register accessor: APPSS_SPIB_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_spib_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_spib_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_spib_cfg`]
module"]
# [doc (alias = "APPSS_SPIB_CFG")]
pub type AppssSpibCfg = crate :: Reg < appss_spib_cfg :: AppssSpibCfgSpec > ; # [doc = "APPSS_SPIB_CFG"]
pub mod appss_spib_cfg { # [doc = "Register `APPSS_SPIB_CFG` reader"]
pub type R = crate :: R < AppssSpibCfgSpec > ; # [doc = "Register `APPSS_SPIB_CFG` writer"]
pub type W = crate :: W < AppssSpibCfgSpec > ; # [doc = "Field `spibsync2sen` reader - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
pub type Spibsync2senR = crate :: BitReader ; # [doc = "Field `spibsync2sen` writer - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
pub type Spibsync2senW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spib_cs_trigsrc_en` reader - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
pub type SpibCsTrigsrcEnR = crate :: BitReader ; # [doc = "Field `spib_cs_trigsrc_en` writer - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
pub type SpibCsTrigsrcEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spib_trig_gate_en` reader - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
pub type SpibTrigGateEnR = crate :: BitReader ; # [doc = "Field `spib_trig_gate_en` writer - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
pub type SpibTrigGateEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spib_int_trig_polarity` reader - 24:24\\]
SPIB trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
pub type SpibIntTrigPolarityR = crate :: BitReader ; # [doc = "Field `spib_int_trig_polarity` writer - 24:24\\]
SPIB trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
pub type SpibIntTrigPolarityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `spib_iodft_en` reader - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
pub type SpibIodftEnR = crate :: BitReader ; # [doc = "Field `spib_iodft_en` writer - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
pub type SpibIodftEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
# [inline (always)]
pub fn spibsync2sen (& self) -> Spibsync2senR { Spibsync2senR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
# [inline (always)]
pub fn spib_cs_trigsrc_en (& self) -> SpibCsTrigsrcEnR { SpibCsTrigsrcEnR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
# [inline (always)]
pub fn spib_trig_gate_en (& self) -> SpibTrigGateEnR { SpibTrigGateEnR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
SPIB trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
# [inline (always)]
pub fn spib_int_trig_polarity (& self) -> SpibIntTrigPolarityR { SpibIntTrigPolarityR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
# [inline (always)]
pub fn spib_iodft_en (& self) -> SpibIodftEnR { SpibIodftEnR :: new (((self . bits >> 28) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Donot touch the field. Used as Tie-off for IP-config."]
# [inline (always)]
# [must_use]
pub fn spibsync2sen (& mut self) -> Spibsync2senW < AppssSpibCfgSpec > { Spibsync2senW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source"]
# [inline (always)]
# [must_use]
pub fn spib_cs_trigsrc_en (& mut self) -> SpibCsTrigsrcEnW < AppssSpibCfgSpec > { SpibCsTrigsrcEnW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
When set the TRIGGER s are un-gated only when chip-select is active"]
# [inline (always)]
# [must_use]
pub fn spib_trig_gate_en (& mut self) -> SpibTrigGateEnW < AppssSpibCfgSpec > { SpibTrigGateEnW :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
SPIB trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1"]
# [inline (always)]
# [must_use]
pub fn spib_int_trig_polarity (& mut self) -> SpibIntTrigPolarityW < AppssSpibCfgSpec > { SpibIntTrigPolarityW :: new (self , 24) } # [doc = "Bit 28 - 28:28\\]
1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode"]
# [inline (always)]
# [must_use]
pub fn spib_iodft_en (& mut self) -> SpibIodftEnW < AppssSpibCfgSpec > { SpibIodftEnW :: new (self , 28) } } # [doc = "APPSS_SPIB_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_spib_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_spib_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssSpibCfgSpec ; impl crate :: RegisterSpec for AppssSpibCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_spib_cfg::R`](R) reader structure"]
impl crate :: Readable for AppssSpibCfgSpec { } # [doc = "`write(|w| ..)` method takes [`appss_spib_cfg::W`](W) writer structure"]
impl crate :: Writable for AppssSpibCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SPIB_CFG to value 0"]
impl crate :: Resettable for AppssSpibCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_EPWM_CFG (rw) register accessor: APPSS_EPWM_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_epwm_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_epwm_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_epwm_cfg`]
module"]
# [doc (alias = "APPSS_EPWM_CFG")]
pub type AppssEpwmCfg = crate :: Reg < appss_epwm_cfg :: AppssEpwmCfgSpec > ; # [doc = "APPSS_EPWM_CFG"]
pub mod appss_epwm_cfg { # [doc = "Register `APPSS_EPWM_CFG` reader"]
pub type R = crate :: R < AppssEpwmCfgSpec > ; # [doc = "Register `APPSS_EPWM_CFG` writer"]
pub type W = crate :: W < AppssEpwmCfgSpec > ; # [doc = "Field `epwm_config` reader - 31:0\\]
bit0: SW syncin for EPWM1 bit1: SW syncin for EPWM2 bit2: SW syncin for EPWM3 bit8:9 : select bits for EPWM1 '0' : external syncin '1' : reserved '2' : sw syncin '3' : reserved bit10:11 : select bits for EPWM2 '0' : external syncin '1' : chained from EPWM1 '2' : sw syncin '3' : reserved bit12:13 : select bits for EPWM3 '0' : external syncin '1' : chained from EPWM2 '2' : sw syncin '3' : reserved bit24:TBCLKEN for EPWM1 bit25:TBCLKEN for EPWM2 bit26:TBCLKEN for EPWM3"]
pub type EpwmConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `epwm_config` writer - 31:0\\]
bit0: SW syncin for EPWM1 bit1: SW syncin for EPWM2 bit2: SW syncin for EPWM3 bit8:9 : select bits for EPWM1 '0' : external syncin '1' : reserved '2' : sw syncin '3' : reserved bit10:11 : select bits for EPWM2 '0' : external syncin '1' : chained from EPWM1 '2' : sw syncin '3' : reserved bit12:13 : select bits for EPWM3 '0' : external syncin '1' : chained from EPWM2 '2' : sw syncin '3' : reserved bit24:TBCLKEN for EPWM1 bit25:TBCLKEN for EPWM2 bit26:TBCLKEN for EPWM3"]
pub type EpwmConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit0: SW syncin for EPWM1 bit1: SW syncin for EPWM2 bit2: SW syncin for EPWM3 bit8:9 : select bits for EPWM1 '0' : external syncin '1' : reserved '2' : sw syncin '3' : reserved bit10:11 : select bits for EPWM2 '0' : external syncin '1' : chained from EPWM1 '2' : sw syncin '3' : reserved bit12:13 : select bits for EPWM3 '0' : external syncin '1' : chained from EPWM2 '2' : sw syncin '3' : reserved bit24:TBCLKEN for EPWM1 bit25:TBCLKEN for EPWM2 bit26:TBCLKEN for EPWM3"]
# [inline (always)]
pub fn epwm_config (& self) -> EpwmConfigR { EpwmConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit0: SW syncin for EPWM1 bit1: SW syncin for EPWM2 bit2: SW syncin for EPWM3 bit8:9 : select bits for EPWM1 '0' : external syncin '1' : reserved '2' : sw syncin '3' : reserved bit10:11 : select bits for EPWM2 '0' : external syncin '1' : chained from EPWM1 '2' : sw syncin '3' : reserved bit12:13 : select bits for EPWM3 '0' : external syncin '1' : chained from EPWM2 '2' : sw syncin '3' : reserved bit24:TBCLKEN for EPWM1 bit25:TBCLKEN for EPWM2 bit26:TBCLKEN for EPWM3"]
# [inline (always)]
# [must_use]
pub fn epwm_config (& mut self) -> EpwmConfigW < AppssEpwmCfgSpec > { EpwmConfigW :: new (self , 0) } } # [doc = "APPSS_EPWM_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_epwm_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_epwm_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssEpwmCfgSpec ; impl crate :: RegisterSpec for AppssEpwmCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_epwm_cfg::R`](R) reader structure"]
impl crate :: Readable for AppssEpwmCfgSpec { } # [doc = "`write(|w| ..)` method takes [`appss_epwm_cfg::W`](W) writer structure"]
impl crate :: Writable for AppssEpwmCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_EPWM_CFG to value 0"]
impl crate :: Resettable for AppssEpwmCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED (rw) register accessor: RESERVED\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved`]
module"]
# [doc (alias = "RESERVED")]
pub type Reserved = crate :: Reg < reserved :: ReservedSpec > ; # [doc = "RESERVED"]
pub mod reserved { # [doc = "Register `RESERVED` reader"]
pub type R = crate :: R < ReservedSpec > ; # [doc = "Register `RESERVED` writer"]
pub type W = crate :: W < ReservedSpec > ; # [doc = "Field `gio_config` reader - 31:0\\]
bit0 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT0 to IRQ bit1 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT1to IRQ bit2: writing '1' will slect negedge for pulse generation of GIO_PAD_INT2 to IRQ bit3 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT3 to IRQ bit4 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT4 to IRQ bit5 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT5 to IRQ bit6 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT6 to IRQ bit7 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT7 to IRQ"]
pub type GioConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `gio_config` writer - 31:0\\]
bit0 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT0 to IRQ bit1 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT1to IRQ bit2: writing '1' will slect negedge for pulse generation of GIO_PAD_INT2 to IRQ bit3 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT3 to IRQ bit4 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT4 to IRQ bit5 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT5 to IRQ bit6 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT6 to IRQ bit7 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT7 to IRQ"]
pub type GioConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit0 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT0 to IRQ bit1 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT1to IRQ bit2: writing '1' will slect negedge for pulse generation of GIO_PAD_INT2 to IRQ bit3 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT3 to IRQ bit4 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT4 to IRQ bit5 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT5 to IRQ bit6 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT6 to IRQ bit7 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT7 to IRQ"]
# [inline (always)]
pub fn gio_config (& self) -> GioConfigR { GioConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit0 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT0 to IRQ bit1 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT1to IRQ bit2: writing '1' will slect negedge for pulse generation of GIO_PAD_INT2 to IRQ bit3 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT3 to IRQ bit4 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT4 to IRQ bit5 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT5 to IRQ bit6 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT6 to IRQ bit7 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT7 to IRQ"]
# [inline (always)]
# [must_use]
pub fn gio_config (& mut self) -> GioConfigW < ReservedSpec > { GioConfigW :: new (self , 0) } } # [doc = "RESERVED\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ReservedSpec ; impl crate :: RegisterSpec for ReservedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved::R`](R) reader structure"]
impl crate :: Readable for ReservedSpec { } # [doc = "`write(|w| ..)` method takes [`reserved::W`](W) writer structure"]
impl crate :: Writable for ReservedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED to value 0"]
impl crate :: Resettable for ReservedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MCAN_FE_AND_LIN_INTR_SEL (rw) register accessor: APPSS_MCAN_FE_AND_LIN_INTR_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcan_fe_and_lin_intr_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcan_fe_and_lin_intr_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mcan_fe_and_lin_intr_sel`]
module"]
# [doc (alias = "APPSS_MCAN_FE_AND_LIN_INTR_SEL")]
pub type AppssMcanFeAndLinIntrSel = crate :: Reg < appss_mcan_fe_and_lin_intr_sel :: AppssMcanFeAndLinIntrSelSpec > ; # [doc = "APPSS_MCAN_FE_AND_LIN_INTR_SEL"]
pub mod appss_mcan_fe_and_lin_intr_sel { # [doc = "Register `APPSS_MCAN_FE_AND_LIN_INTR_SEL` reader"]
pub type R = crate :: R < AppssMcanFeAndLinIntrSelSpec > ; # [doc = "Register `APPSS_MCAN_FE_AND_LIN_INTR_SEL` writer"]
pub type W = crate :: W < AppssMcanFeAndLinIntrSelSpec > ; # [doc = "Field `mcan_fe_sel` reader - 2:0\\]
Writing a value 'N' would select Nth filter interrupt combination with SYNC_IN(IO) for triggering timing engine Example: writing 3'd&lt;1-7> selects MCAN_FE_INT&lt;1-7> respectively"]
pub type McanFeSelR = crate :: FieldReader ; # [doc = "Field `mcan_fe_sel` writer - 2:0\\]
Writing a value 'N' would select Nth filter interrupt combination with SYNC_IN(IO) for triggering timing engine Example: writing 3'd&lt;1-7> selects MCAN_FE_INT&lt;1-7> respectively"]
pub type McanFeSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `lin_intr_sel` reader - 3:3\\]
Writing a value would select the LIN interrupt in combination with HW_SYNC_IN and CAN filter events for Frame timer 0 : 0th interrupt bit is selected 1 : 1st interrupt bit is selected"]
pub type LinIntrSelR = crate :: BitReader ; # [doc = "Field `lin_intr_sel` writer - 3:3\\]
Writing a value would select the LIN interrupt in combination with HW_SYNC_IN and CAN filter events for Frame timer 0 : 0th interrupt bit is selected 1 : 1st interrupt bit is selected"]
pub type LinIntrSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing a value 'N' would select Nth filter interrupt combination with SYNC_IN(IO) for triggering timing engine Example: writing 3'd&lt;1-7> selects MCAN_FE_INT&lt;1-7> respectively"]
# [inline (always)]
pub fn mcan_fe_sel (& self) -> McanFeSelR { McanFeSelR :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
Writing a value would select the LIN interrupt in combination with HW_SYNC_IN and CAN filter events for Frame timer 0 : 0th interrupt bit is selected 1 : 1st interrupt bit is selected"]
# [inline (always)]
pub fn lin_intr_sel (& self) -> LinIntrSelR { LinIntrSelR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing a value 'N' would select Nth filter interrupt combination with SYNC_IN(IO) for triggering timing engine Example: writing 3'd&lt;1-7> selects MCAN_FE_INT&lt;1-7> respectively"]
# [inline (always)]
# [must_use]
pub fn mcan_fe_sel (& mut self) -> McanFeSelW < AppssMcanFeAndLinIntrSelSpec > { McanFeSelW :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
Writing a value would select the LIN interrupt in combination with HW_SYNC_IN and CAN filter events for Frame timer 0 : 0th interrupt bit is selected 1 : 1st interrupt bit is selected"]
# [inline (always)]
# [must_use]
pub fn lin_intr_sel (& mut self) -> LinIntrSelW < AppssMcanFeAndLinIntrSelSpec > { LinIntrSelW :: new (self , 3) } } # [doc = "APPSS_MCAN_FE_AND_LIN_INTR_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcan_fe_and_lin_intr_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcan_fe_and_lin_intr_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMcanFeAndLinIntrSelSpec ; impl crate :: RegisterSpec for AppssMcanFeAndLinIntrSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mcan_fe_and_lin_intr_sel::R`](R) reader structure"]
impl crate :: Readable for AppssMcanFeAndLinIntrSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mcan_fe_and_lin_intr_sel::W`](W) writer structure"]
impl crate :: Writable for AppssMcanFeAndLinIntrSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MCAN_FE_AND_LIN_INTR_SEL to value 0"]
impl crate :: Resettable for AppssMcanFeAndLinIntrSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MCANA_INT_CLR (rw) register accessor: APPSS_MCANA_INT_CLR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcana_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcana_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mcana_int_clr`]
module"]
# [doc (alias = "APPSS_MCANA_INT_CLR")]
pub type AppssMcanaIntClr = crate :: Reg < appss_mcana_int_clr :: AppssMcanaIntClrSpec > ; # [doc = "APPSS_MCANA_INT_CLR"]
pub mod appss_mcana_int_clr { # [doc = "Register `APPSS_MCANA_INT_CLR` reader"]
pub type R = crate :: R < AppssMcanaIntClrSpec > ; # [doc = "Register `APPSS_MCANA_INT_CLR` writer"]
pub type W = crate :: W < AppssMcanaIntClrSpec > ; # [doc = "Field `mcan_int_clr` reader - 31:0\\]
Interrupt Clear for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> clears interrupt source &lt;0-31> respectively in MCANA"]
pub type McanIntClrR = crate :: FieldReader < u32 > ; # [doc = "Field `mcan_int_clr` writer - 31:0\\]
Interrupt Clear for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> clears interrupt source &lt;0-31> respectively in MCANA"]
pub type McanIntClrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Interrupt Clear for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> clears interrupt source &lt;0-31> respectively in MCANA"]
# [inline (always)]
pub fn mcan_int_clr (& self) -> McanIntClrR { McanIntClrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Interrupt Clear for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> clears interrupt source &lt;0-31> respectively in MCANA"]
# [inline (always)]
# [must_use]
pub fn mcan_int_clr (& mut self) -> McanIntClrW < AppssMcanaIntClrSpec > { McanIntClrW :: new (self , 0) } } # [doc = "APPSS_MCANA_INT_CLR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcana_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcana_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMcanaIntClrSpec ; impl crate :: RegisterSpec for AppssMcanaIntClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mcana_int_clr::R`](R) reader structure"]
impl crate :: Readable for AppssMcanaIntClrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mcana_int_clr::W`](W) writer structure"]
impl crate :: Writable for AppssMcanaIntClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MCANA_INT_CLR to value 0"]
impl crate :: Resettable for AppssMcanaIntClrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MCANA_INT_MASK (rw) register accessor: APPSS_MCANA_INT_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcana_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcana_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mcana_int_mask`]
module"]
# [doc (alias = "APPSS_MCANA_INT_MASK")]
pub type AppssMcanaIntMask = crate :: Reg < appss_mcana_int_mask :: AppssMcanaIntMaskSpec > ; # [doc = "APPSS_MCANA_INT_MASK"]
pub mod appss_mcana_int_mask { # [doc = "Register `APPSS_MCANA_INT_MASK` reader"]
pub type R = crate :: R < AppssMcanaIntMaskSpec > ; # [doc = "Register `APPSS_MCANA_INT_MASK` writer"]
pub type W = crate :: W < AppssMcanaIntMaskSpec > ; # [doc = "Field `mcan_int_mask` reader - 31:0\\]
Interrupt Mask for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> masks interrupt source &lt;0-31> respectively in MCANA"]
pub type McanIntMaskR = crate :: FieldReader < u32 > ; # [doc = "Field `mcan_int_mask` writer - 31:0\\]
Interrupt Mask for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> masks interrupt source &lt;0-31> respectively in MCANA"]
pub type McanIntMaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Interrupt Mask for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> masks interrupt source &lt;0-31> respectively in MCANA"]
# [inline (always)]
pub fn mcan_int_mask (& self) -> McanIntMaskR { McanIntMaskR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Interrupt Mask for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit&lt;0-31> masks interrupt source &lt;0-31> respectively in MCANA"]
# [inline (always)]
# [must_use]
pub fn mcan_int_mask (& mut self) -> McanIntMaskW < AppssMcanaIntMaskSpec > { McanIntMaskW :: new (self , 0) } } # [doc = "APPSS_MCANA_INT_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcana_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcana_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMcanaIntMaskSpec ; impl crate :: RegisterSpec for AppssMcanaIntMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mcana_int_mask::R`](R) reader structure"]
impl crate :: Readable for AppssMcanaIntMaskSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mcana_int_mask::W`](W) writer structure"]
impl crate :: Writable for AppssMcanaIntMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MCANA_INT_MASK to value 0"]
impl crate :: Resettable for AppssMcanaIntMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MCANA_INT_STAT (rw) register accessor: APPSS_MCANA_INT_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcana_int_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcana_int_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mcana_int_stat`]
module"]
# [doc (alias = "APPSS_MCANA_INT_STAT")]
pub type AppssMcanaIntStat = crate :: Reg < appss_mcana_int_stat :: AppssMcanaIntStatSpec > ; # [doc = "APPSS_MCANA_INT_STAT"]
pub mod appss_mcana_int_stat { # [doc = "Register `APPSS_MCANA_INT_STAT` reader"]
pub type R = crate :: R < AppssMcanaIntStatSpec > ; # [doc = "Register `APPSS_MCANA_INT_STAT` writer"]
pub type W = crate :: W < AppssMcanaIntStatSpec > ; # [doc = "Field `mcan_int_status` reader - 31:0\\]
Interrupt status for 32 MCANSS TX DMA interrupts. 1'b1 in bit&lt;0-31> gives pending status for interrupt &lt;0-31> respectively in MCANA"]
pub type McanIntStatusR = crate :: FieldReader < u32 > ; # [doc = "Field `mcan_int_status` writer - 31:0\\]
Interrupt status for 32 MCANSS TX DMA interrupts. 1'b1 in bit&lt;0-31> gives pending status for interrupt &lt;0-31> respectively in MCANA"]
pub type McanIntStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Interrupt status for 32 MCANSS TX DMA interrupts. 1'b1 in bit&lt;0-31> gives pending status for interrupt &lt;0-31> respectively in MCANA"]
# [inline (always)]
pub fn mcan_int_status (& self) -> McanIntStatusR { McanIntStatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Interrupt status for 32 MCANSS TX DMA interrupts. 1'b1 in bit&lt;0-31> gives pending status for interrupt &lt;0-31> respectively in MCANA"]
# [inline (always)]
# [must_use]
pub fn mcan_int_status (& mut self) -> McanIntStatusW < AppssMcanaIntStatSpec > { McanIntStatusW :: new (self , 0) } } # [doc = "APPSS_MCANA_INT_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mcana_int_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mcana_int_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMcanaIntStatSpec ; impl crate :: RegisterSpec for AppssMcanaIntStatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mcana_int_stat::R`](R) reader structure"]
impl crate :: Readable for AppssMcanaIntStatSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mcana_int_stat::W`](W) writer structure"]
impl crate :: Writable for AppssMcanaIntStatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MCANA_INT_STAT to value 0"]
impl crate :: Resettable for AppssMcanaIntStatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CM4_GLOBAL_CONFIG (rw) register accessor: APPSS_CM4_GLOBAL_CONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_global_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_global_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_cm4_global_config`]
module"]
# [doc (alias = "APPSS_CM4_GLOBAL_CONFIG")]
pub type AppssCm4GlobalConfig = crate :: Reg < appss_cm4_global_config :: AppssCm4GlobalConfigSpec > ; # [doc = "APPSS_CM4_GLOBAL_CONFIG"]
pub mod appss_cm4_global_config { # [doc = "Register `APPSS_CM4_GLOBAL_CONFIG` reader"]
pub type R = crate :: R < AppssCm4GlobalConfigSpec > ; # [doc = "Register `APPSS_CM4_GLOBAL_CONFIG` writer"]
pub type W = crate :: W < AppssCm4GlobalConfigSpec > ; # [doc = "Field `teinit` reader - 0:0\\]
Reserved"]
pub type TeinitR = crate :: BitReader ; # [doc = "Field `teinit` writer - 0:0\\]
Reserved"]
pub type TeinitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn teinit (& self) -> TeinitR { TeinitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn teinit (& mut self) -> TeinitW < AppssCm4GlobalConfigSpec > { TeinitW :: new (self , 0) } } # [doc = "APPSS_CM4_GLOBAL_CONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_global_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_global_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCm4GlobalConfigSpec ; impl crate :: RegisterSpec for AppssCm4GlobalConfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_cm4_global_config::R`](R) reader structure"]
impl crate :: Readable for AppssCm4GlobalConfigSpec { } # [doc = "`write(|w| ..)` method takes [`appss_cm4_global_config::W`](W) writer structure"]
impl crate :: Writable for AppssCm4GlobalConfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CM4_GLOBAL_CONFIG to value 0"]
impl crate :: Resettable for AppssCm4GlobalConfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED1 (rw) register accessor: RESERVED1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
# [doc (alias = "RESERVED1")]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "RESERVED1"]
pub mod reserved1 { # [doc = "Register `RESERVED1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `RESERVED1` writer"]
pub type W = crate :: W < Reserved1Spec > ; # [doc = "Field `res` reader - 31:0\\]
reserved"]
pub type ResR = crate :: FieldReader < u32 > ; # [doc = "Field `res` writer - 31:0\\]
reserved"]
pub type ResW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
reserved"]
# [inline (always)]
pub fn res (& self) -> ResR { ResR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
reserved"]
# [inline (always)]
# [must_use]
pub fn res (& mut self) -> ResW < Reserved1Spec > { ResW :: new (self , 0) } } # [doc = "RESERVED1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CM4_ROM_ECLIPSE (rw) register accessor: APPSS_CM4_ROM_ECLIPSE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_rom_eclipse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_rom_eclipse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_cm4_rom_eclipse`]
module"]
# [doc (alias = "APPSS_CM4_ROM_ECLIPSE")]
pub type AppssCm4RomEclipse = crate :: Reg < appss_cm4_rom_eclipse :: AppssCm4RomEclipseSpec > ; # [doc = "APPSS_CM4_ROM_ECLIPSE"]
pub mod appss_cm4_rom_eclipse { # [doc = "Register `APPSS_CM4_ROM_ECLIPSE` reader"]
pub type R = crate :: R < AppssCm4RomEclipseSpec > ; # [doc = "Register `APPSS_CM4_ROM_ECLIPSE` writer"]
pub type W = crate :: W < AppssCm4RomEclipseSpec > ; # [doc = "Field `memswap` reader - 2:0\\]
writing '111' ensures eclipsing of CPU_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after CPU sys reset assertion."]
pub type MemswapR = crate :: FieldReader ; # [doc = "Field `memswap` writer - 2:0\\]
writing '111' ensures eclipsing of CPU_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after CPU sys reset assertion."]
pub type MemswapW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `memswap_wait` reader - 10:8\\]
writing 3'b111 ensures ROM-Eclipsing happens only after CPU sys reset. Orelse it will be a immediate change."]
pub type MemswapWaitR = crate :: FieldReader ; # [doc = "Field `memswap_wait` writer - 10:8\\]
writing 3'b111 ensures ROM-Eclipsing happens only after CPU sys reset. Orelse it will be a immediate change."]
pub type MemswapWaitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
writing '111' ensures eclipsing of CPU_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after CPU sys reset assertion."]
# [inline (always)]
pub fn memswap (& self) -> MemswapR { MemswapR :: new ((self . bits & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
writing 3'b111 ensures ROM-Eclipsing happens only after CPU sys reset. Orelse it will be a immediate change."]
# [inline (always)]
pub fn memswap_wait (& self) -> MemswapWaitR { MemswapWaitR :: new (((self . bits >> 8) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
writing '111' ensures eclipsing of CPU_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after CPU sys reset assertion."]
# [inline (always)]
# [must_use]
pub fn memswap (& mut self) -> MemswapW < AppssCm4RomEclipseSpec > { MemswapW :: new (self , 0) } # [doc = "Bits 8:10 - 10:8\\]
writing 3'b111 ensures ROM-Eclipsing happens only after CPU sys reset. Orelse it will be a immediate change."]
# [inline (always)]
# [must_use]
pub fn memswap_wait (& mut self) -> MemswapWaitW < AppssCm4RomEclipseSpec > { MemswapWaitW :: new (self , 8) } } # [doc = "APPSS_CM4_ROM_ECLIPSE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_rom_eclipse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_rom_eclipse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCm4RomEclipseSpec ; impl crate :: RegisterSpec for AppssCm4RomEclipseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_cm4_rom_eclipse::R`](R) reader structure"]
impl crate :: Readable for AppssCm4RomEclipseSpec { } # [doc = "`write(|w| ..)` method takes [`appss_cm4_rom_eclipse::W`](W) writer structure"]
impl crate :: Writable for AppssCm4RomEclipseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CM4_ROM_ECLIPSE to value 0"]
impl crate :: Resettable for AppssCm4RomEclipseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CM4_STATUS_REG (rw) register accessor: APPSS_CM4_STATUS_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_status_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_status_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_cm4_status_reg`]
module"]
# [doc (alias = "APPSS_CM4_STATUS_REG")]
pub type AppssCm4StatusReg = crate :: Reg < appss_cm4_status_reg :: AppssCm4StatusRegSpec > ; # [doc = "APPSS_CM4_STATUS_REG"]
pub mod appss_cm4_status_reg { # [doc = "Register `APPSS_CM4_STATUS_REG` reader"]
pub type R = crate :: R < AppssCm4StatusRegSpec > ; # [doc = "Register `APPSS_CM4_STATUS_REG` writer"]
pub type W = crate :: W < AppssCm4StatusRegSpec > ; # [doc = "Field `memswap` reader - 0:0\\]
reading 1: confirms ROM is Eclipsed from with RAM for the CPU."]
pub type MemswapR = crate :: BitReader ; # [doc = "Field `memswap` writer - 0:0\\]
reading 1: confirms ROM is Eclipsed from with RAM for the CPU."]
pub type MemswapW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
reading 1: confirms ROM is Eclipsed from with RAM for the CPU."]
# [inline (always)]
pub fn memswap (& self) -> MemswapR { MemswapR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
reading 1: confirms ROM is Eclipsed from with RAM for the CPU."]
# [inline (always)]
# [must_use]
pub fn memswap (& mut self) -> MemswapW < AppssCm4StatusRegSpec > { MemswapW :: new (self , 0) } } # [doc = "APPSS_CM4_STATUS_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_status_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_status_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCm4StatusRegSpec ; impl crate :: RegisterSpec for AppssCm4StatusRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_cm4_status_reg::R`](R) reader structure"]
impl crate :: Readable for AppssCm4StatusRegSpec { } # [doc = "`write(|w| ..)` method takes [`appss_cm4_status_reg::W`](W) writer structure"]
impl crate :: Writable for AppssCm4StatusRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CM4_STATUS_REG to value 0"]
impl crate :: Resettable for AppssCm4StatusRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_AHB_CTRL (rw) register accessor: APPSS_AHB_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ahb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ahb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ahb_ctrl`]
module"]
# [doc (alias = "APPSS_AHB_CTRL")]
pub type AppssAhbCtrl = crate :: Reg < appss_ahb_ctrl :: AppssAhbCtrlSpec > ; # [doc = "APPSS_AHB_CTRL"]
pub mod appss_ahb_ctrl { # [doc = "Register `APPSS_AHB_CTRL` reader"]
pub type R = crate :: R < AppssAhbCtrlSpec > ; # [doc = "Register `APPSS_AHB_CTRL` writer"]
pub type W = crate :: W < AppssAhbCtrlSpec > ; # [doc = "Field `cpu0_ahb_init` reader - 0:0\\]
Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not."]
pub type Cpu0AhbInitR = crate :: BitReader ; # [doc = "Field `cpu0_ahb_init` writer - 0:0\\]
Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not."]
pub type Cpu0AhbInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not."]
# [inline (always)]
pub fn cpu0_ahb_init (& self) -> Cpu0AhbInitR { Cpu0AhbInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not."]
# [inline (always)]
# [must_use]
pub fn cpu0_ahb_init (& mut self) -> Cpu0AhbInitW < AppssAhbCtrlSpec > { Cpu0AhbInitW :: new (self , 0) } } # [doc = "APPSS_AHB_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ahb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ahb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssAhbCtrlSpec ; impl crate :: RegisterSpec for AppssAhbCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ahb_ctrl::R`](R) reader structure"]
impl crate :: Readable for AppssAhbCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ahb_ctrl::W`](W) writer structure"]
impl crate :: Writable for AppssAhbCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_AHB_CTRL to value 0"]
impl crate :: Resettable for AppssAhbCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING0 (rw) register accessor: ESM_GATING0\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating0`]
module"]
# [doc (alias = "ESM_GATING0")]
pub type EsmGating0 = crate :: Reg < esm_gating0 :: EsmGating0Spec > ; # [doc = "ESM_GATING0"]
pub mod esm_gating0 { # [doc = "Register `ESM_GATING0` reader"]
pub type R = crate :: R < EsmGating0Spec > ; # [doc = "Register `ESM_GATING0` writer"]
pub type W = crate :: W < EsmGating0Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_7"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_7"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_7"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_7"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating0Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING0\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating0Spec ; impl crate :: RegisterSpec for EsmGating0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating0::R`](R) reader structure"]
impl crate :: Readable for EsmGating0Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating0::W`](W) writer structure"]
impl crate :: Writable for EsmGating0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING0 to value 0"]
impl crate :: Resettable for EsmGating0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING1 (rw) register accessor: ESM_GATING1\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating1`]
module"]
# [doc (alias = "ESM_GATING1")]
pub type EsmGating1 = crate :: Reg < esm_gating1 :: EsmGating1Spec > ; # [doc = "ESM_GATING1"]
pub mod esm_gating1 { # [doc = "Register `ESM_GATING1` reader"]
pub type R = crate :: R < EsmGating1Spec > ; # [doc = "Register `ESM_GATING1` writer"]
pub type W = crate :: W < EsmGating1Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_15"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_15"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_15"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_15"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating1Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING1\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating1Spec ; impl crate :: RegisterSpec for EsmGating1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating1::R`](R) reader structure"]
impl crate :: Readable for EsmGating1Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating1::W`](W) writer structure"]
impl crate :: Writable for EsmGating1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING1 to value 0"]
impl crate :: Resettable for EsmGating1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING2 (rw) register accessor: ESM_GATING2\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating2`]
module"]
# [doc (alias = "ESM_GATING2")]
pub type EsmGating2 = crate :: Reg < esm_gating2 :: EsmGating2Spec > ; # [doc = "ESM_GATING2"]
pub mod esm_gating2 { # [doc = "Register `ESM_GATING2` reader"]
pub type R = crate :: R < EsmGating2Spec > ; # [doc = "Register `ESM_GATING2` writer"]
pub type W = crate :: W < EsmGating2Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_23"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_23"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_23"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_23"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating2Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING2\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating2Spec ; impl crate :: RegisterSpec for EsmGating2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating2::R`](R) reader structure"]
impl crate :: Readable for EsmGating2Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating2::W`](W) writer structure"]
impl crate :: Writable for EsmGating2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING2 to value 0"]
impl crate :: Resettable for EsmGating2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING3 (rw) register accessor: ESM_GATING3\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating3`]
module"]
# [doc (alias = "ESM_GATING3")]
pub type EsmGating3 = crate :: Reg < esm_gating3 :: EsmGating3Spec > ; # [doc = "ESM_GATING3"]
pub mod esm_gating3 { # [doc = "Register `ESM_GATING3` reader"]
pub type R = crate :: R < EsmGating3Spec > ; # [doc = "Register `ESM_GATING3` writer"]
pub type W = crate :: W < EsmGating3Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_31"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_31"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_31"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_31"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating3Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING3\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating3Spec ; impl crate :: RegisterSpec for EsmGating3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating3::R`](R) reader structure"]
impl crate :: Readable for EsmGating3Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating3::W`](W) writer structure"]
impl crate :: Writable for EsmGating3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING3 to value 0"]
impl crate :: Resettable for EsmGating3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING4 (rw) register accessor: ESM_GATING4\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating4`]
module"]
# [doc (alias = "ESM_GATING4")]
pub type EsmGating4 = crate :: Reg < esm_gating4 :: EsmGating4Spec > ; # [doc = "ESM_GATING4"]
pub mod esm_gating4 { # [doc = "Register `ESM_GATING4` reader"]
pub type R = crate :: R < EsmGating4Spec > ; # [doc = "Register `ESM_GATING4` writer"]
pub type W = crate :: W < EsmGating4Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_7"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_7"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_7"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_7"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating4Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING4\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating4Spec ; impl crate :: RegisterSpec for EsmGating4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating4::R`](R) reader structure"]
impl crate :: Readable for EsmGating4Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating4::W`](W) writer structure"]
impl crate :: Writable for EsmGating4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING4 to value 0"]
impl crate :: Resettable for EsmGating4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING5 (rw) register accessor: ESM_GATING5\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating5`]
module"]
# [doc (alias = "ESM_GATING5")]
pub type EsmGating5 = crate :: Reg < esm_gating5 :: EsmGating5Spec > ; # [doc = "ESM_GATING5"]
pub mod esm_gating5 { # [doc = "Register `ESM_GATING5` reader"]
pub type R = crate :: R < EsmGating5Spec > ; # [doc = "Register `ESM_GATING5` writer"]
pub type W = crate :: W < EsmGating5Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_15"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_15"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_15"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_15"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating5Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING5\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating5Spec ; impl crate :: RegisterSpec for EsmGating5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating5::R`](R) reader structure"]
impl crate :: Readable for EsmGating5Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating5::W`](W) writer structure"]
impl crate :: Writable for EsmGating5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING5 to value 0"]
impl crate :: Resettable for EsmGating5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING6 (rw) register accessor: ESM_GATING6\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating6`]
module"]
# [doc (alias = "ESM_GATING6")]
pub type EsmGating6 = crate :: Reg < esm_gating6 :: EsmGating6Spec > ; # [doc = "ESM_GATING6"]
pub mod esm_gating6 { # [doc = "Register `ESM_GATING6` reader"]
pub type R = crate :: R < EsmGating6Spec > ; # [doc = "Register `ESM_GATING6` writer"]
pub type W = crate :: W < EsmGating6Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_23"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_23"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_23"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_23"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating6Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING6\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating6Spec ; impl crate :: RegisterSpec for EsmGating6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating6::R`](R) reader structure"]
impl crate :: Readable for EsmGating6Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating6::W`](W) writer structure"]
impl crate :: Writable for EsmGating6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING6 to value 0"]
impl crate :: Resettable for EsmGating6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESM_GATING7 (rw) register accessor: ESM_GATING7\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esm_gating7`]
module"]
# [doc (alias = "ESM_GATING7")]
pub type EsmGating7 = crate :: Reg < esm_gating7 :: EsmGating7Spec > ; # [doc = "ESM_GATING7"]
pub mod esm_gating7 { # [doc = "Register `ESM_GATING7` reader"]
pub type R = crate :: R < EsmGating7Spec > ; # [doc = "Register `ESM_GATING7` writer"]
pub type W = crate :: W < EsmGating7Spec > ; # [doc = "Field `esm_gating` reader - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_31"]
pub type EsmGatingR = crate :: FieldReader < u32 > ; # [doc = "Field `esm_gating` writer - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_31"]
pub type EsmGatingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_31"]
# [inline (always)]
pub fn esm_gating (& self) -> EsmGatingR { EsmGatingR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_31"]
# [inline (always)]
# [must_use]
pub fn esm_gating (& mut self) -> EsmGatingW < EsmGating7Spec > { EsmGatingW :: new (self , 0) } } # [doc = "ESM_GATING7\n\nYou can [`read`](crate::Reg::read) this register and get [`esm_gating7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esm_gating7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmGating7Spec ; impl crate :: RegisterSpec for EsmGating7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esm_gating7::R`](R) reader structure"]
impl crate :: Readable for EsmGating7Spec { } # [doc = "`write(|w| ..)` method takes [`esm_gating7::W`](W) writer structure"]
impl crate :: Writable for EsmGating7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESM_GATING7 to value 0"]
impl crate :: Resettable for EsmGating7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CM4_HALT (rw) register accessor: APPSS_CM4_HALT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_halt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_halt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_cm4_halt`]
module"]
# [doc (alias = "APPSS_CM4_HALT")]
pub type AppssCm4Halt = crate :: Reg < appss_cm4_halt :: AppssCm4HaltSpec > ; # [doc = "APPSS_CM4_HALT"]
pub mod appss_cm4_halt { # [doc = "Register `APPSS_CM4_HALT` reader"]
pub type R = crate :: R < AppssCm4HaltSpec > ; # [doc = "Register `APPSS_CM4_HALT` writer"]
pub type W = crate :: W < AppssCm4HaltSpec > ; # [doc = "Field `halt` reader - 2:0\\]
RESERVED"]
pub type HaltR = crate :: FieldReader ; # [doc = "Field `halt` writer - 2:0\\]
RESERVED"]
pub type HaltW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
RESERVED"]
# [inline (always)]
pub fn halt (& self) -> HaltR { HaltR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn halt (& mut self) -> HaltW < AppssCm4HaltSpec > { HaltW :: new (self , 0) } } # [doc = "APPSS_CM4_HALT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_halt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_halt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCm4HaltSpec ; impl crate :: RegisterSpec for AppssCm4HaltSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_cm4_halt::R`](R) reader structure"]
impl crate :: Readable for AppssCm4HaltSpec { } # [doc = "`write(|w| ..)` method takes [`appss_cm4_halt::W`](W) writer structure"]
impl crate :: Writable for AppssCm4HaltSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CM4_HALT to value 0"]
impl crate :: Resettable for AppssCm4HaltSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CM4_EVENT (rw) register accessor: APPSS_CM4_EVENT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_event::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_event::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_cm4_event`]
module"]
# [doc (alias = "APPSS_CM4_EVENT")]
pub type AppssCm4Event = crate :: Reg < appss_cm4_event :: AppssCm4EventSpec > ; # [doc = "APPSS_CM4_EVENT"]
pub mod appss_cm4_event { # [doc = "Register `APPSS_CM4_EVENT` reader"]
pub type R = crate :: R < AppssCm4EventSpec > ; # [doc = "Register `APPSS_CM4_EVENT` writer"]
pub type W = crate :: W < AppssCm4EventSpec > ; # [doc = "Field `cpu0_event` reader - 2:0\\]
Reserved Register for R &amp; D"]
pub type Cpu0EventR = crate :: FieldReader ; # [doc = "Field `cpu0_event` writer - 2:0\\]
Reserved Register for R &amp; D"]
pub type Cpu0EventW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Reserved Register for R &amp; D"]
# [inline (always)]
pub fn cpu0_event (& self) -> Cpu0EventR { Cpu0EventR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Reserved Register for R &amp; D"]
# [inline (always)]
# [must_use]
pub fn cpu0_event (& mut self) -> Cpu0EventW < AppssCm4EventSpec > { Cpu0EventW :: new (self , 0) } } # [doc = "APPSS_CM4_EVENT\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cm4_event::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cm4_event::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCm4EventSpec ; impl crate :: RegisterSpec for AppssCm4EventSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_cm4_event::R`](R) reader structure"]
impl crate :: Readable for AppssCm4EventSpec { } # [doc = "`write(|w| ..)` method takes [`appss_cm4_event::W`](W) writer structure"]
impl crate :: Writable for AppssCm4EventSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CM4_EVENT to value 0"]
impl crate :: Resettable for AppssCm4EventSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPIA_IO_CFG (rw) register accessor: SPIA_IO_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`spia_io_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spia_io_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spia_io_cfg`]
module"]
# [doc (alias = "SPIA_IO_CFG")]
pub type SpiaIoCfg = crate :: Reg < spia_io_cfg :: SpiaIoCfgSpec > ; # [doc = "SPIA_IO_CFG"]
pub mod spia_io_cfg { # [doc = "Register `SPIA_IO_CFG` reader"]
pub type R = crate :: R < SpiaIoCfgSpec > ; # [doc = "Register `SPIA_IO_CFG` writer"]
pub type W = crate :: W < SpiaIoCfgSpec > ; # [doc = "Field `cs_deact` reader - 0:0\\]
RESERVED"]
pub type CsDeactR = crate :: BitReader ; # [doc = "Field `cs_deact` writer - 0:0\\]
RESERVED"]
pub type CsDeactW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cs_pol` reader - 8:8\\]
RESERVED"]
pub type CsPolR = crate :: BitReader ; # [doc = "Field `cs_pol` writer - 8:8\\]
RESERVED"]
pub type CsPolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `miso_oen_by_cs` reader - 16:16\\]
RESERVED"]
pub type MisoOenByCsR = crate :: BitReader ; # [doc = "Field `miso_oen_by_cs` writer - 16:16\\]
RESERVED"]
pub type MisoOenByCsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
pub fn cs_deact (& self) -> CsDeactR { CsDeactR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
pub fn cs_pol (& self) -> CsPolR { CsPolR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
RESERVED"]
# [inline (always)]
pub fn miso_oen_by_cs (& self) -> MisoOenByCsR { MisoOenByCsR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn cs_deact (& mut self) -> CsDeactW < SpiaIoCfgSpec > { CsDeactW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn cs_pol (& mut self) -> CsPolW < SpiaIoCfgSpec > { CsPolW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn miso_oen_by_cs (& mut self) -> MisoOenByCsW < SpiaIoCfgSpec > { MisoOenByCsW :: new (self , 16) } } # [doc = "SPIA_IO_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`spia_io_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spia_io_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiaIoCfgSpec ; impl crate :: RegisterSpec for SpiaIoCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spia_io_cfg::R`](R) reader structure"]
impl crate :: Readable for SpiaIoCfgSpec { } # [doc = "`write(|w| ..)` method takes [`spia_io_cfg::W`](W) writer structure"]
impl crate :: Writable for SpiaIoCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPIA_IO_CFG to value 0"]
impl crate :: Resettable for SpiaIoCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPIB_IO_CFG (rw) register accessor: SPIB_IO_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`spib_io_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spib_io_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spib_io_cfg`]
module"]
# [doc (alias = "SPIB_IO_CFG")]
pub type SpibIoCfg = crate :: Reg < spib_io_cfg :: SpibIoCfgSpec > ; # [doc = "SPIB_IO_CFG"]
pub mod spib_io_cfg { # [doc = "Register `SPIB_IO_CFG` reader"]
pub type R = crate :: R < SpibIoCfgSpec > ; # [doc = "Register `SPIB_IO_CFG` writer"]
pub type W = crate :: W < SpibIoCfgSpec > ; # [doc = "Field `cs_deact` reader - 0:0\\]
RESERVED"]
pub type CsDeactR = crate :: BitReader ; # [doc = "Field `cs_deact` writer - 0:0\\]
RESERVED"]
pub type CsDeactW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cs_pol` reader - 8:8\\]
RESERVED"]
pub type CsPolR = crate :: BitReader ; # [doc = "Field `cs_pol` writer - 8:8\\]
RESERVED"]
pub type CsPolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `miso_oen_by_cs` reader - 16:16\\]
RESERVED"]
pub type MisoOenByCsR = crate :: BitReader ; # [doc = "Field `miso_oen_by_cs` writer - 16:16\\]
RESERVED"]
pub type MisoOenByCsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
pub fn cs_deact (& self) -> CsDeactR { CsDeactR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
pub fn cs_pol (& self) -> CsPolR { CsPolR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
RESERVED"]
# [inline (always)]
pub fn miso_oen_by_cs (& self) -> MisoOenByCsR { MisoOenByCsR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn cs_deact (& mut self) -> CsDeactW < SpibIoCfgSpec > { CsDeactW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn cs_pol (& mut self) -> CsPolW < SpibIoCfgSpec > { CsPolW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn miso_oen_by_cs (& mut self) -> MisoOenByCsW < SpibIoCfgSpec > { MisoOenByCsW :: new (self , 16) } } # [doc = "SPIB_IO_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`spib_io_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spib_io_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpibIoCfgSpec ; impl crate :: RegisterSpec for SpibIoCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spib_io_cfg::R`](R) reader structure"]
impl crate :: Readable for SpibIoCfgSpec { } # [doc = "`write(|w| ..)` method takes [`spib_io_cfg::W`](W) writer structure"]
impl crate :: Writable for SpibIoCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPIB_IO_CFG to value 0"]
impl crate :: Resettable for SpibIoCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_HOST_IRQ (rw) register accessor: SPI_HOST_IRQ\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_host_irq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_host_irq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_host_irq`]
module"]
# [doc (alias = "SPI_HOST_IRQ")]
pub type SpiHostIrq = crate :: Reg < spi_host_irq :: SpiHostIrqSpec > ; # [doc = "SPI_HOST_IRQ"]
pub mod spi_host_irq { # [doc = "Register `SPI_HOST_IRQ` reader"]
pub type R = crate :: R < SpiHostIrqSpec > ; # [doc = "Register `SPI_HOST_IRQ` writer"]
pub type W = crate :: W < SpiHostIrqSpec > ; # [doc = "Field `host_irq` reader - 0:0\\]
RESERVED"]
pub type HostIrqR = crate :: BitReader ; # [doc = "Field `host_irq` writer - 0:0\\]
RESERVED"]
pub type HostIrqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
pub fn host_irq (& self) -> HostIrqR { HostIrqR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn host_irq (& mut self) -> HostIrqW < SpiHostIrqSpec > { HostIrqW :: new (self , 0) } } # [doc = "SPI_HOST_IRQ\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_host_irq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_host_irq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiHostIrqSpec ; impl crate :: RegisterSpec for SpiHostIrqSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_host_irq::R`](R) reader structure"]
impl crate :: Readable for SpiHostIrqSpec { } # [doc = "`write(|w| ..)` method takes [`spi_host_irq::W`](W) writer structure"]
impl crate :: Writable for SpiHostIrqSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_HOST_IRQ to value 0"]
impl crate :: Resettable for SpiHostIrqSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TPTC_DBS_CONFIG (rw) register accessor: TPTC_DBS_CONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`tptc_dbs_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tptc_dbs_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tptc_dbs_config`]
module"]
# [doc (alias = "TPTC_DBS_CONFIG")]
pub type TptcDbsConfig = crate :: Reg < tptc_dbs_config :: TptcDbsConfigSpec > ; # [doc = "TPTC_DBS_CONFIG"]
pub mod tptc_dbs_config { # [doc = "Register `TPTC_DBS_CONFIG` reader"]
pub type R = crate :: R < TptcDbsConfigSpec > ; # [doc = "Register `TPTC_DBS_CONFIG` writer"]
pub type W = crate :: W < TptcDbsConfigSpec > ; # [doc = "Field `tptc_a0` reader - 1:0\\]
Default burst size tieoff value for TPTC_A0"]
pub type TptcA0R = crate :: FieldReader ; # [doc = "Field `tptc_a0` writer - 1:0\\]
Default burst size tieoff value for TPTC_A0"]
pub type TptcA0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `tptc_a1` reader - 5:4\\]
Default burst size tieoff value for TPTC_A1"]
pub type TptcA1R = crate :: FieldReader ; # [doc = "Field `tptc_a1` writer - 5:4\\]
Default burst size tieoff value for TPTC_A1"]
pub type TptcA1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `tptc_b0` reader - 9:8\\]
Default burst size tieoff value for TPTC_B0"]
pub type TptcB0R = crate :: FieldReader ; # [doc = "Field `tptc_b0` writer - 9:8\\]
Default burst size tieoff value for TPTC_B0"]
pub type TptcB0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `tptc_b1` reader - 13:12\\]
Default burst size tieoff value for TPTC_B1"]
pub type TptcB1R = crate :: FieldReader ; # [doc = "Field `tptc_b1` writer - 13:12\\]
Default burst size tieoff value for TPTC_B1"]
pub type TptcB1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Default burst size tieoff value for TPTC_A0"]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new ((self . bits & 3) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Default burst size tieoff value for TPTC_A1"]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Default burst size tieoff value for TPTC_B0"]
# [inline (always)]
pub fn tptc_b0 (& self) -> TptcB0R { TptcB0R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Default burst size tieoff value for TPTC_B1"]
# [inline (always)]
pub fn tptc_b1 (& self) -> TptcB1R { TptcB1R :: new (((self . bits >> 12) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Default burst size tieoff value for TPTC_A0"]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < TptcDbsConfigSpec > { TptcA0W :: new (self , 0) } # [doc = "Bits 4:5 - 5:4\\]
Default burst size tieoff value for TPTC_A1"]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < TptcDbsConfigSpec > { TptcA1W :: new (self , 4) } # [doc = "Bits 8:9 - 9:8\\]
Default burst size tieoff value for TPTC_B0"]
# [inline (always)]
# [must_use]
pub fn tptc_b0 (& mut self) -> TptcB0W < TptcDbsConfigSpec > { TptcB0W :: new (self , 8) } # [doc = "Bits 12:13 - 13:12\\]
Default burst size tieoff value for TPTC_B1"]
# [inline (always)]
# [must_use]
pub fn tptc_b1 (& mut self) -> TptcB1W < TptcDbsConfigSpec > { TptcB1W :: new (self , 12) } } # [doc = "TPTC_DBS_CONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`tptc_dbs_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tptc_dbs_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TptcDbsConfigSpec ; impl crate :: RegisterSpec for TptcDbsConfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tptc_dbs_config::R`](R) reader structure"]
impl crate :: Readable for TptcDbsConfigSpec { } # [doc = "`write(|w| ..)` method takes [`tptc_dbs_config::W`](W) writer structure"]
impl crate :: Writable for TptcDbsConfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TPTC_DBS_CONFIG to value 0"]
impl crate :: Resettable for TptcDbsConfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TPCC_PARITY_CTRL (rw) register accessor: TPCC_PARITY_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`tpcc_parity_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpcc_parity_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpcc_parity_ctrl`]
module"]
# [doc (alias = "TPCC_PARITY_CTRL")]
pub type TpccParityCtrl = crate :: Reg < tpcc_parity_ctrl :: TpccParityCtrlSpec > ; # [doc = "TPCC_PARITY_CTRL"]
pub mod tpcc_parity_ctrl { # [doc = "Register `TPCC_PARITY_CTRL` reader"]
pub type R = crate :: R < TpccParityCtrlSpec > ; # [doc = "Register `TPCC_PARITY_CTRL` writer"]
pub type W = crate :: W < TpccParityCtrlSpec > ; # [doc = "Field `tpcc_a_parity_en` reader - 0:0\\]
writing 1'b1 enables parity for TPCC_A"]
pub type TpccAParityEnR = crate :: BitReader ; # [doc = "Field `tpcc_a_parity_en` writer - 0:0\\]
writing 1'b1 enables parity for TPCC_A"]
pub type TpccAParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_parity_testen` reader - 4:4\\]
parity test enable for tpcc a"]
pub type TpccAParityTestenR = crate :: BitReader ; # [doc = "Field `tpcc_a_parity_testen` writer - 4:4\\]
parity test enable for tpcc a"]
pub type TpccAParityTestenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_parity_en` reader - 8:8\\]
parity en for tpcc b"]
pub type TpccBParityEnR = crate :: BitReader ; # [doc = "Field `tpcc_b_parity_en` writer - 8:8\\]
parity en for tpcc b"]
pub type TpccBParityEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_parity_testen` reader - 12:12\\]
parity test enable for tpcc b"]
pub type TpccBParityTestenR = crate :: BitReader ; # [doc = "Field `tpcc_b_parity_testen` writer - 12:12\\]
parity test enable for tpcc b"]
pub type TpccBParityTestenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_parity_err_clr` reader - 16:16\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr"]
pub type TpccAParityErrClrR = crate :: BitReader ; # [doc = "Field `tpcc_a_parity_err_clr` writer - 16:16\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr"]
pub type TpccAParityErrClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_parity_err_clr` reader - 20:20\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_b_parity_addr"]
pub type TpccBParityErrClrR = crate :: BitReader ; # [doc = "Field `tpcc_b_parity_err_clr` writer - 20:20\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_b_parity_addr"]
pub type TpccBParityErrClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
writing 1'b1 enables parity for TPCC_A"]
# [inline (always)]
pub fn tpcc_a_parity_en (& self) -> TpccAParityEnR { TpccAParityEnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
parity test enable for tpcc a"]
# [inline (always)]
pub fn tpcc_a_parity_testen (& self) -> TpccAParityTestenR { TpccAParityTestenR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
parity en for tpcc b"]
# [inline (always)]
pub fn tpcc_b_parity_en (& self) -> TpccBParityEnR { TpccBParityEnR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
parity test enable for tpcc b"]
# [inline (always)]
pub fn tpcc_b_parity_testen (& self) -> TpccBParityTestenR { TpccBParityTestenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr"]
# [inline (always)]
pub fn tpcc_a_parity_err_clr (& self) -> TpccAParityErrClrR { TpccAParityErrClrR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_b_parity_addr"]
# [inline (always)]
pub fn tpcc_b_parity_err_clr (& self) -> TpccBParityErrClrR { TpccBParityErrClrR :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
writing 1'b1 enables parity for TPCC_A"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_parity_en (& mut self) -> TpccAParityEnW < TpccParityCtrlSpec > { TpccAParityEnW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
parity test enable for tpcc a"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_parity_testen (& mut self) -> TpccAParityTestenW < TpccParityCtrlSpec > { TpccAParityTestenW :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
parity en for tpcc b"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_parity_en (& mut self) -> TpccBParityEnW < TpccParityCtrlSpec > { TpccBParityEnW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
parity test enable for tpcc b"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_parity_testen (& mut self) -> TpccBParityTestenW < TpccParityCtrlSpec > { TpccBParityTestenW :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_parity_err_clr (& mut self) -> TpccAParityErrClrW < TpccParityCtrlSpec > { TpccAParityErrClrW :: new (self , 16) } # [doc = "Bit 20 - 20:20\\]
Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_b_parity_addr"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_parity_err_clr (& mut self) -> TpccBParityErrClrW < TpccParityCtrlSpec > { TpccBParityErrClrW :: new (self , 20) } } # [doc = "TPCC_PARITY_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`tpcc_parity_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpcc_parity_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TpccParityCtrlSpec ; impl crate :: RegisterSpec for TpccParityCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tpcc_parity_ctrl::R`](R) reader structure"]
impl crate :: Readable for TpccParityCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`tpcc_parity_ctrl::W`](W) writer structure"]
impl crate :: Writable for TpccParityCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TPCC_PARITY_CTRL to value 0"]
impl crate :: Resettable for TpccParityCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TPCC_PARITY_STATUS (rw) register accessor: TPCC_PARITY_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`tpcc_parity_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpcc_parity_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpcc_parity_status`]
module"]
# [doc (alias = "TPCC_PARITY_STATUS")]
pub type TpccParityStatus = crate :: Reg < tpcc_parity_status :: TpccParityStatusSpec > ; # [doc = "TPCC_PARITY_STATUS"]
pub mod tpcc_parity_status { # [doc = "Register `TPCC_PARITY_STATUS` reader"]
pub type R = crate :: R < TpccParityStatusSpec > ; # [doc = "Register `TPCC_PARITY_STATUS` writer"]
pub type W = crate :: W < TpccParityStatusSpec > ; # [doc = "Field `tpcc_a_parity_addr` reader - 7:0\\]
address where parity error happened for tpcca"]
pub type TpccAParityAddrR = crate :: FieldReader ; # [doc = "Field `tpcc_a_parity_addr` writer - 7:0\\]
address where parity error happened for tpcca"]
pub type TpccAParityAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `tpcc_b_parity_addr` reader - 23:16\\]
address where parity error happened for tpccb"]
pub type TpccBParityAddrR = crate :: FieldReader ; # [doc = "Field `tpcc_b_parity_addr` writer - 23:16\\]
address where parity error happened for tpccb"]
pub type TpccBParityAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
address where parity error happened for tpcca"]
# [inline (always)]
pub fn tpcc_a_parity_addr (& self) -> TpccAParityAddrR { TpccAParityAddrR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
address where parity error happened for tpccb"]
# [inline (always)]
pub fn tpcc_b_parity_addr (& self) -> TpccBParityAddrR { TpccBParityAddrR :: new (((self . bits >> 16) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
address where parity error happened for tpcca"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_parity_addr (& mut self) -> TpccAParityAddrW < TpccParityStatusSpec > { TpccAParityAddrW :: new (self , 0) } # [doc = "Bits 16:23 - 23:16\\]
address where parity error happened for tpccb"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_parity_addr (& mut self) -> TpccBParityAddrW < TpccParityStatusSpec > { TpccBParityAddrW :: new (self , 16) } } # [doc = "TPCC_PARITY_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`tpcc_parity_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpcc_parity_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TpccParityStatusSpec ; impl crate :: RegisterSpec for TpccParityStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tpcc_parity_status::R`](R) reader structure"]
impl crate :: Readable for TpccParityStatusSpec { } # [doc = "`write(|w| ..)` method takes [`tpcc_parity_status::W`](W) writer structure"]
impl crate :: Writable for TpccParityStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TPCC_PARITY_STATUS to value 0"]
impl crate :: Resettable for TpccParityStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_DBG_ACK_CTL0 (rw) register accessor: APPSS_DBG_ACK_CTL0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dbg_ack_ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dbg_ack_ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_dbg_ack_ctl0`]
module"]
# [doc (alias = "APPSS_DBG_ACK_CTL0")]
pub type AppssDbgAckCtl0 = crate :: Reg < appss_dbg_ack_ctl0 :: AppssDbgAckCtl0Spec > ; # [doc = "APPSS_DBG_ACK_CTL0"]
pub mod appss_dbg_ack_ctl0 { # [doc = "Register `APPSS_DBG_ACK_CTL0` reader"]
pub type R = crate :: R < AppssDbgAckCtl0Spec > ; # [doc = "Register `APPSS_DBG_ACK_CTL0` writer"]
pub type W = crate :: W < AppssDbgAckCtl0Spec > ; # [doc = "Field `can` reader - 0:0\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type CanR = crate :: BitReader ; # [doc = "Field `can` writer - 0:0\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type CanW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `rti` reader - 4:4\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type RtiR = crate :: BitReader ; # [doc = "Field `rti` writer - 4:4\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type RtiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wdt` reader - 8:8\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type WdtR = crate :: BitReader ; # [doc = "Field `wdt` writer - 8:8\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type WdtW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `mcrc` reader - 12:12\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type McrcR = crate :: BitReader ; # [doc = "Field `mcrc` writer - 12:12\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type McrcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `i2c` reader - 16:16\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type I2cR = crate :: BitReader ; # [doc = "Field `i2c` writer - 16:16\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type I2cW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `scia` reader - 20:20\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type SciaR = crate :: BitReader ; # [doc = "Field `scia` writer - 20:20\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type SciaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `scib` reader - 24:24\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type ScibR = crate :: BitReader ; # [doc = "Field `scib` writer - 24:24\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type ScibW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `lin` reader - 28:28\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type LinR = crate :: BitReader ; # [doc = "Field `lin` writer - 28:28\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
pub type LinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn can (& self) -> CanR { CanR :: new ((self . bits & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn rti (& self) -> RtiR { RtiR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn wdt (& self) -> WdtR { WdtR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn mcrc (& self) -> McrcR { McrcR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn i2c (& self) -> I2cR { I2cR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn scia (& self) -> SciaR { SciaR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn scib (& self) -> ScibR { ScibR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
pub fn lin (& self) -> LinR { LinR :: new (((self . bits >> 28) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn can (& mut self) -> CanW < AppssDbgAckCtl0Spec > { CanW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn rti (& mut self) -> RtiW < AppssDbgAckCtl0Spec > { RtiW :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn wdt (& mut self) -> WdtW < AppssDbgAckCtl0Spec > { WdtW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn mcrc (& mut self) -> McrcW < AppssDbgAckCtl0Spec > { McrcW :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn i2c (& mut self) -> I2cW < AppssDbgAckCtl0Spec > { I2cW :: new (self , 16) } # [doc = "Bit 20 - 20:20\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn scia (& mut self) -> SciaW < AppssDbgAckCtl0Spec > { SciaW :: new (self , 20) } # [doc = "Bit 24 - 24:24\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn scib (& mut self) -> ScibW < AppssDbgAckCtl0Spec > { ScibW :: new (self , 24) } # [doc = "Bit 28 - 28:28\\]
Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor"]
# [inline (always)]
# [must_use]
pub fn lin (& mut self) -> LinW < AppssDbgAckCtl0Spec > { LinW :: new (self , 28) } } # [doc = "APPSS_DBG_ACK_CTL0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dbg_ack_ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dbg_ack_ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssDbgAckCtl0Spec ; impl crate :: RegisterSpec for AppssDbgAckCtl0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_dbg_ack_ctl0::R`](R) reader structure"]
impl crate :: Readable for AppssDbgAckCtl0Spec { } # [doc = "`write(|w| ..)` method takes [`appss_dbg_ack_ctl0::W`](W) writer structure"]
impl crate :: Writable for AppssDbgAckCtl0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_DBG_ACK_CTL0 to value 0"]
impl crate :: Resettable for AppssDbgAckCtl0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUGSS_CSETB_FLUSH (rw) register accessor: DEBUGSS_CSETB_FLUSH\n\nYou can [`read`](crate::Reg::read) this register and get [`debugss_csetb_flush::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debugss_csetb_flush::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debugss_csetb_flush`]
module"]
# [doc (alias = "DEBUGSS_CSETB_FLUSH")]
pub type DebugssCsetbFlush = crate :: Reg < debugss_csetb_flush :: DebugssCsetbFlushSpec > ; # [doc = "DEBUGSS_CSETB_FLUSH"]
pub mod debugss_csetb_flush { # [doc = "Register `DEBUGSS_CSETB_FLUSH` reader"]
pub type R = crate :: R < DebugssCsetbFlushSpec > ; # [doc = "Register `DEBUGSS_CSETB_FLUSH` writer"]
pub type W = crate :: W < DebugssCsetbFlushSpec > ; # [doc = "Field `CSETB_FLUSHIN` reader - 0:0\\]
RESERVED"]
pub type CsetbFlushinR = crate :: BitReader ; # [doc = "Field `CSETB_FLUSHIN` writer - 0:0\\]
RESERVED"]
pub type CsetbFlushinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSETB_FLUSHINACK` reader - 8:8\\]
RESERVED"]
pub type CsetbFlushinackR = crate :: BitReader ; # [doc = "Field `CSETB_FLUSHINACK` writer - 8:8\\]
RESERVED"]
pub type CsetbFlushinackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSETB_ACQ_COMPLETE` reader - 9:9\\]
RESERVED"]
pub type CsetbAcqCompleteR = crate :: BitReader ; # [doc = "Field `CSETB_ACQ_COMPLETE` writer - 9:9\\]
RESERVED"]
pub type CsetbAcqCompleteW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSETB_FULL` reader - 10:10\\]
RESERVED"]
pub type CsetbFullR = crate :: BitReader ; # [doc = "Field `CSETB_FULL` writer - 10:10\\]
RESERVED"]
pub type CsetbFullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
pub fn csetb_flushin (& self) -> CsetbFlushinR { CsetbFlushinR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
pub fn csetb_flushinack (& self) -> CsetbFlushinackR { CsetbFlushinackR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
RESERVED"]
# [inline (always)]
pub fn csetb_acq_complete (& self) -> CsetbAcqCompleteR { CsetbAcqCompleteR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
RESERVED"]
# [inline (always)]
pub fn csetb_full (& self) -> CsetbFullR { CsetbFullR :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn csetb_flushin (& mut self) -> CsetbFlushinW < DebugssCsetbFlushSpec > { CsetbFlushinW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn csetb_flushinack (& mut self) -> CsetbFlushinackW < DebugssCsetbFlushSpec > { CsetbFlushinackW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn csetb_acq_complete (& mut self) -> CsetbAcqCompleteW < DebugssCsetbFlushSpec > { CsetbAcqCompleteW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn csetb_full (& mut self) -> CsetbFullW < DebugssCsetbFlushSpec > { CsetbFullW :: new (self , 10) } } # [doc = "DEBUGSS_CSETB_FLUSH\n\nYou can [`read`](crate::Reg::read) this register and get [`debugss_csetb_flush::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debugss_csetb_flush::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugssCsetbFlushSpec ; impl crate :: RegisterSpec for DebugssCsetbFlushSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`debugss_csetb_flush::R`](R) reader structure"]
impl crate :: Readable for DebugssCsetbFlushSpec { } # [doc = "`write(|w| ..)` method takes [`debugss_csetb_flush::W`](W) writer structure"]
impl crate :: Writable for DebugssCsetbFlushSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUGSS_CSETB_FLUSH to value 0"]
impl crate :: Resettable for DebugssCsetbFlushSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CPSW_CONTROL (rw) register accessor: CPSW_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`cpsw_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpsw_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpsw_control`]
module"]
# [doc (alias = "CPSW_CONTROL")]
pub type CpswControl = crate :: Reg < cpsw_control :: CpswControlSpec > ; # [doc = "CPSW_CONTROL"]
pub mod cpsw_control { # [doc = "Register `CPSW_CONTROL` reader"]
pub type R = crate :: R < CpswControlSpec > ; # [doc = "Register `CPSW_CONTROL` writer"]
pub type W = crate :: W < CpswControlSpec > ; # [doc = "Field `port1_mode_sel` reader - 0:0\\]
Reserved"]
pub type Port1ModeSelR = crate :: BitReader ; # [doc = "Field `port1_mode_sel` writer - 0:0\\]
Reserved"]
pub type Port1ModeSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `rmii_ref_clk_oe_n` reader - 8:8\\]
Reserved"]
pub type RmiiRefClkOeNR = crate :: BitReader ; # [doc = "Field `rmii_ref_clk_oe_n` writer - 8:8\\]
Reserved"]
pub type RmiiRefClkOeNW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `rgmii1_id_mode` reader - 16:16\\]
Reserved"]
pub type Rgmii1IdModeR = crate :: BitReader ; # [doc = "Field `rgmii1_id_mode` writer - 16:16\\]
Reserved"]
pub type Rgmii1IdModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn port1_mode_sel (& self) -> Port1ModeSelR { Port1ModeSelR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Reserved"]
# [inline (always)]
pub fn rmii_ref_clk_oe_n (& self) -> RmiiRefClkOeNR { RmiiRefClkOeNR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
pub fn rgmii1_id_mode (& self) -> Rgmii1IdModeR { Rgmii1IdModeR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn port1_mode_sel (& mut self) -> Port1ModeSelW < CpswControlSpec > { Port1ModeSelW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rmii_ref_clk_oe_n (& mut self) -> RmiiRefClkOeNW < CpswControlSpec > { RmiiRefClkOeNW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn rgmii1_id_mode (& mut self) -> Rgmii1IdModeW < CpswControlSpec > { Rgmii1IdModeW :: new (self , 16) } } # [doc = "CPSW_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`cpsw_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpsw_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CpswControlSpec ; impl crate :: RegisterSpec for CpswControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cpsw_control::R`](R) reader structure"]
impl crate :: Readable for CpswControlSpec { } # [doc = "`write(|w| ..)` method takes [`cpsw_control::W`](W) writer structure"]
impl crate :: Writable for CpswControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CPSW_CONTROL to value 0"]
impl crate :: Resettable for CpswControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_ERRAGG_MASK0 (rw) register accessor: APPSS_ERRAGG_MASK0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_mask0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_mask0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_erragg_mask0`]
module"]
# [doc (alias = "APPSS_ERRAGG_MASK0")]
pub type AppssErraggMask0 = crate :: Reg < appss_erragg_mask0 :: AppssErraggMask0Spec > ; # [doc = "APPSS_ERRAGG_MASK0"]
pub mod appss_erragg_mask0 { # [doc = "Register `APPSS_ERRAGG_MASK0` reader"]
pub type R = crate :: R < AppssErraggMask0Spec > ; # [doc = "Register `APPSS_ERRAGG_MASK0` writer"]
pub type W = crate :: W < AppssErraggMask0Spec > ; # [doc = "Field `app_rcm_rd` reader - 0:0\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppRcmRdR = crate :: BitReader ; # [doc = "Field `app_rcm_rd` writer - 0:0\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppRcmRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_rcm_wr` reader - 1:1\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppRcmWrR = crate :: BitReader ; # [doc = "Field `app_rcm_wr` writer - 1:1\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppRcmWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ctrl_rd` reader - 2:2\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppCtrlRdR = crate :: BitReader ; # [doc = "Field `app_ctrl_rd` writer - 2:2\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ctrl_wr` reader - 3:3\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppCtrlWrR = crate :: BitReader ; # [doc = "Field `app_ctrl_wr` writer - 3:3\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_idalloc_rd` reader - 4:4\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppIdallocRdR = crate :: BitReader ; # [doc = "Field `app_idalloc_rd` writer - 4:4\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppIdallocRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_idalloc_wr` reader - 5:5\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppIdallocWrR = crate :: BitReader ; # [doc = "Field `app_idalloc_wr` writer - 5:5\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppIdallocWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `adcbuff_ctrl_rd` reader - 6:6\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AdcbuffCtrlRdR = crate :: BitReader ; # [doc = "Field `adcbuff_ctrl_rd` writer - 6:6\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AdcbuffCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `adcbuff_ctrl_wr` reader - 7:7\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AdcbuffCtrlWrR = crate :: BitReader ; # [doc = "Field `adcbuff_ctrl_wr` writer - 7:7\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AdcbuffCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `plldig_ctrl_rd` reader - 8:8\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type PlldigCtrlRdR = crate :: BitReader ; # [doc = "Field `plldig_ctrl_rd` writer - 8:8\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type PlldigCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `plldig_ctrl_wr` reader - 9:9\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type PlldigCtrlWrR = crate :: BitReader ; # [doc = "Field `plldig_ctrl_wr` writer - 9:9\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type PlldigCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `topss_ctrl_rd` reader - 10:10\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopssCtrlRdR = crate :: BitReader ; # [doc = "Field `topss_ctrl_rd` writer - 10:10\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopssCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `topss_ctrl_wr` reader - 11:11\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopssCtrlWrR = crate :: BitReader ; # [doc = "Field `topss_ctrl_wr` writer - 11:11\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopssCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `apll_ctrl_rd` reader - 12:12\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type ApllCtrlRdR = crate :: BitReader ; # [doc = "Field `apll_ctrl_rd` writer - 12:12\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type ApllCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `apll_ctrl_wr` reader - 13:13\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type ApllCtrlWrR = crate :: BitReader ; # [doc = "Field `apll_ctrl_wr` writer - 13:13\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type ApllCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `frame_timer_rd` reader - 14:14\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FrameTimerRdR = crate :: BitReader ; # [doc = "Field `frame_timer_rd` writer - 14:14\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FrameTimerRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `frame_timer_wr` reader - 15:15\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FrameTimerWrR = crate :: BitReader ; # [doc = "Field `frame_timer_wr` writer - 15:15\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FrameTimerWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_prcm_rd` reader - 16:16\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopPrcmRdR = crate :: BitReader ; # [doc = "Field `top_prcm_rd` writer - 16:16\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopPrcmRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_prcm_wr` reader - 17:17\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopPrcmWrR = crate :: BitReader ; # [doc = "Field `top_prcm_wr` writer - 17:17\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopPrcmWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_efuse_ctrl_rd` reader - 18:18\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopEfuseCtrlRdR = crate :: BitReader ; # [doc = "Field `top_efuse_ctrl_rd` writer - 18:18\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopEfuseCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_efuse_ctrl_wr` reader - 19:19\\]
Mask Interrupt from TOP_EFUSE_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopEfuseCtrlWrR = crate :: BitReader ; # [doc = "Field `top_efuse_ctrl_wr` writer - 19:19\\]
Mask Interrupt from TOP_EFUSE_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TopEfuseCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_mpu` reader - 20:20\\]
Mask Interrupt from APP_MPU to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppMpuR = crate :: BitReader ; # [doc = "Field `app_mpu` writer - 20:20\\]
Mask Interrupt from APP_MPU to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ahb` reader - 21:21\\]
Mask Interrupt from APP_AHB to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppAhbR = crate :: BitReader ; # [doc = "Field `app_ahb` writer - 21:21\\]
Mask Interrupt from APP_AHB to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppAhbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_shared_mem` reader - 22:22\\]
Mask Interrupt from APP_SHARED_MEM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppSharedMemR = crate :: BitReader ; # [doc = "Field `app_shared_mem` writer - 22:22\\]
Mask Interrupt from APP_SHARED_MEM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppSharedMemW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_erroragg` reader - 23:23\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FecErroraggR = crate :: BitReader ; # [doc = "Field `fec_erroragg` writer - 23:23\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FecErroraggW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ahb_slv_wr` reader - 24:24\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppAhbSlvWrR = crate :: BitReader ; # [doc = "Field `app_ahb_slv_wr` writer - 24:24\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppAhbSlvWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ahb_slv_rd` reader - 25:25\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppAhbSlvRdR = crate :: BitReader ; # [doc = "Field `app_ahb_slv_rd` writer - 25:25\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppAhbSlvRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_rcm_rd (& self) -> AppRcmRdR { AppRcmRdR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_rcm_wr (& self) -> AppRcmWrR { AppRcmWrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_ctrl_rd (& self) -> AppCtrlRdR { AppCtrlRdR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_ctrl_wr (& self) -> AppCtrlWrR { AppCtrlWrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_idalloc_rd (& self) -> AppIdallocRdR { AppIdallocRdR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_idalloc_wr (& self) -> AppIdallocWrR { AppIdallocWrR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn adcbuff_ctrl_rd (& self) -> AdcbuffCtrlRdR { AdcbuffCtrlRdR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn adcbuff_ctrl_wr (& self) -> AdcbuffCtrlWrR { AdcbuffCtrlWrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn plldig_ctrl_rd (& self) -> PlldigCtrlRdR { PlldigCtrlRdR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn plldig_ctrl_wr (& self) -> PlldigCtrlWrR { PlldigCtrlWrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn topss_ctrl_rd (& self) -> TopssCtrlRdR { TopssCtrlRdR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn topss_ctrl_wr (& self) -> TopssCtrlWrR { TopssCtrlWrR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn apll_ctrl_rd (& self) -> ApllCtrlRdR { ApllCtrlRdR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn apll_ctrl_wr (& self) -> ApllCtrlWrR { ApllCtrlWrR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn frame_timer_rd (& self) -> FrameTimerRdR { FrameTimerRdR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn frame_timer_wr (& self) -> FrameTimerWrR { FrameTimerWrR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn top_prcm_rd (& self) -> TopPrcmRdR { TopPrcmRdR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn top_prcm_wr (& self) -> TopPrcmWrR { TopPrcmWrR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn top_efuse_ctrl_rd (& self) -> TopEfuseCtrlRdR { TopEfuseCtrlRdR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Mask Interrupt from TOP_EFUSE_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn top_efuse_ctrl_wr (& self) -> TopEfuseCtrlWrR { TopEfuseCtrlWrR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Mask Interrupt from APP_MPU to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_mpu (& self) -> AppMpuR { AppMpuR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Mask Interrupt from APP_AHB to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_ahb (& self) -> AppAhbR { AppAhbR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Mask Interrupt from APP_SHARED_MEM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_shared_mem (& self) -> AppSharedMemR { AppSharedMemR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn fec_erroragg (& self) -> FecErroraggR { FecErroraggR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_ahb_slv_wr (& self) -> AppAhbSlvWrR { AppAhbSlvWrR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn app_ahb_slv_rd (& self) -> AppAhbSlvRdR { AppAhbSlvRdR :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_rcm_rd (& mut self) -> AppRcmRdW < AppssErraggMask0Spec > { AppRcmRdW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_rcm_wr (& mut self) -> AppRcmWrW < AppssErraggMask0Spec > { AppRcmWrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_ctrl_rd (& mut self) -> AppCtrlRdW < AppssErraggMask0Spec > { AppCtrlRdW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_ctrl_wr (& mut self) -> AppCtrlWrW < AppssErraggMask0Spec > { AppCtrlWrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_idalloc_rd (& mut self) -> AppIdallocRdW < AppssErraggMask0Spec > { AppIdallocRdW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_idalloc_wr (& mut self) -> AppIdallocWrW < AppssErraggMask0Spec > { AppIdallocWrW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn adcbuff_ctrl_rd (& mut self) -> AdcbuffCtrlRdW < AppssErraggMask0Spec > { AdcbuffCtrlRdW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn adcbuff_ctrl_wr (& mut self) -> AdcbuffCtrlWrW < AppssErraggMask0Spec > { AdcbuffCtrlWrW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn plldig_ctrl_rd (& mut self) -> PlldigCtrlRdW < AppssErraggMask0Spec > { PlldigCtrlRdW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn plldig_ctrl_wr (& mut self) -> PlldigCtrlWrW < AppssErraggMask0Spec > { PlldigCtrlWrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn topss_ctrl_rd (& mut self) -> TopssCtrlRdW < AppssErraggMask0Spec > { TopssCtrlRdW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn topss_ctrl_wr (& mut self) -> TopssCtrlWrW < AppssErraggMask0Spec > { TopssCtrlWrW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn apll_ctrl_rd (& mut self) -> ApllCtrlRdW < AppssErraggMask0Spec > { ApllCtrlRdW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn apll_ctrl_wr (& mut self) -> ApllCtrlWrW < AppssErraggMask0Spec > { ApllCtrlWrW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn frame_timer_rd (& mut self) -> FrameTimerRdW < AppssErraggMask0Spec > { FrameTimerRdW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn frame_timer_wr (& mut self) -> FrameTimerWrW < AppssErraggMask0Spec > { FrameTimerWrW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn top_prcm_rd (& mut self) -> TopPrcmRdW < AppssErraggMask0Spec > { TopPrcmRdW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn top_prcm_wr (& mut self) -> TopPrcmWrW < AppssErraggMask0Spec > { TopPrcmWrW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn top_efuse_ctrl_rd (& mut self) -> TopEfuseCtrlRdW < AppssErraggMask0Spec > { TopEfuseCtrlRdW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Mask Interrupt from TOP_EFUSE_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn top_efuse_ctrl_wr (& mut self) -> TopEfuseCtrlWrW < AppssErraggMask0Spec > { TopEfuseCtrlWrW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Mask Interrupt from APP_MPU to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_mpu (& mut self) -> AppMpuW < AppssErraggMask0Spec > { AppMpuW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Mask Interrupt from APP_AHB to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_ahb (& mut self) -> AppAhbW < AppssErraggMask0Spec > { AppAhbW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Mask Interrupt from APP_SHARED_MEM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_shared_mem (& mut self) -> AppSharedMemW < AppssErraggMask0Spec > { AppSharedMemW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn fec_erroragg (& mut self) -> FecErroraggW < AppssErraggMask0Spec > { FecErroraggW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_ahb_slv_wr (& mut self) -> AppAhbSlvWrW < AppssErraggMask0Spec > { AppAhbSlvWrW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn app_ahb_slv_rd (& mut self) -> AppAhbSlvRdW < AppssErraggMask0Spec > { AppAhbSlvRdW :: new (self , 25) } } # [doc = "APPSS_ERRAGG_MASK0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_mask0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_mask0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssErraggMask0Spec ; impl crate :: RegisterSpec for AppssErraggMask0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_erragg_mask0::R`](R) reader structure"]
impl crate :: Readable for AppssErraggMask0Spec { } # [doc = "`write(|w| ..)` method takes [`appss_erragg_mask0::W`](W) writer structure"]
impl crate :: Writable for AppssErraggMask0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_ERRAGG_MASK0 to value 0"]
impl crate :: Resettable for AppssErraggMask0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_ERRAGG_STATUS0 (rw) register accessor: APPSS_ERRAGG_STATUS0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_status0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_status0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_erragg_status0`]
module"]
# [doc (alias = "APPSS_ERRAGG_STATUS0")]
pub type AppssErraggStatus0 = crate :: Reg < appss_erragg_status0 :: AppssErraggStatus0Spec > ; # [doc = "APPSS_ERRAGG_STATUS0"]
pub mod appss_erragg_status0 { # [doc = "Register `APPSS_ERRAGG_STATUS0` reader"]
pub type R = crate :: R < AppssErraggStatus0Spec > ; # [doc = "Register `APPSS_ERRAGG_STATUS0` writer"]
pub type W = crate :: W < AppssErraggStatus0Spec > ; # [doc = "Field `app_rcm_rd` reader - 0:0\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppRcmRdR = crate :: BitReader ; # [doc = "Field `app_rcm_rd` writer - 0:0\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppRcmRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_rcm_wr` reader - 1:1\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppRcmWrR = crate :: BitReader ; # [doc = "Field `app_rcm_wr` writer - 1:1\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppRcmWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ctrl_rd` reader - 2:2\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppCtrlRdR = crate :: BitReader ; # [doc = "Field `app_ctrl_rd` writer - 2:2\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ctrl_wr` reader - 3:3\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppCtrlWrR = crate :: BitReader ; # [doc = "Field `app_ctrl_wr` writer - 3:3\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_idalloc_rd` reader - 4:4\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppIdallocRdR = crate :: BitReader ; # [doc = "Field `app_idalloc_rd` writer - 4:4\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppIdallocRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_idalloc_wr` reader - 5:5\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppIdallocWrR = crate :: BitReader ; # [doc = "Field `app_idalloc_wr` writer - 5:5\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppIdallocWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `adcbuff_ctrl_rd` reader - 6:6\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AdcbuffCtrlRdR = crate :: BitReader ; # [doc = "Field `adcbuff_ctrl_rd` writer - 6:6\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AdcbuffCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `adcbuff_ctrl_wr` reader - 7:7\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AdcbuffCtrlWrR = crate :: BitReader ; # [doc = "Field `adcbuff_ctrl_wr` writer - 7:7\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AdcbuffCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `plldig_ctrl_rd` reader - 8:8\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type PlldigCtrlRdR = crate :: BitReader ; # [doc = "Field `plldig_ctrl_rd` writer - 8:8\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type PlldigCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `plldig_ctrl_wr` reader - 9:9\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type PlldigCtrlWrR = crate :: BitReader ; # [doc = "Field `plldig_ctrl_wr` writer - 9:9\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type PlldigCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `topss_ctrl_rd` reader - 10:10\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopssCtrlRdR = crate :: BitReader ; # [doc = "Field `topss_ctrl_rd` writer - 10:10\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopssCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `topss_ctrl_wr` reader - 11:11\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopssCtrlWrR = crate :: BitReader ; # [doc = "Field `topss_ctrl_wr` writer - 11:11\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopssCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `apll_ctrl_rd` reader - 12:12\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type ApllCtrlRdR = crate :: BitReader ; # [doc = "Field `apll_ctrl_rd` writer - 12:12\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type ApllCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `apll_ctrl_wr` reader - 13:13\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type ApllCtrlWrR = crate :: BitReader ; # [doc = "Field `apll_ctrl_wr` writer - 13:13\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type ApllCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `frame_timer_rd` reader - 14:14\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type FrameTimerRdR = crate :: BitReader ; # [doc = "Field `frame_timer_rd` writer - 14:14\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type FrameTimerRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `frame_timer_wr` reader - 15:15\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type FrameTimerWrR = crate :: BitReader ; # [doc = "Field `frame_timer_wr` writer - 15:15\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type FrameTimerWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_prcm_rd` reader - 16:16\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopPrcmRdR = crate :: BitReader ; # [doc = "Field `top_prcm_rd` writer - 16:16\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopPrcmRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_prcm_wr` reader - 17:17\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopPrcmWrR = crate :: BitReader ; # [doc = "Field `top_prcm_wr` writer - 17:17\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopPrcmWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_efuse_ctrl_rd` reader - 18:18\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopEfuseCtrlRdR = crate :: BitReader ; # [doc = "Field `top_efuse_ctrl_rd` writer - 18:18\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopEfuseCtrlRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `top_efuse_ctrl_wr` reader - 19:19\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopEfuseCtrlWrR = crate :: BitReader ; # [doc = "Field `top_efuse_ctrl_wr` writer - 19:19\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type TopEfuseCtrlWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_mpu_rd` reader - 20:20\\]
Status of Interrupt from APP_MPU Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppMpuRdR = crate :: BitReader ; # [doc = "Field `app_mpu_rd` writer - 20:20\\]
Status of Interrupt from APP_MPU Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppMpuRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ahb_wr` reader - 21:21\\]
Status of Interrupt from APP_AHB Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppAhbWrR = crate :: BitReader ; # [doc = "Field `app_ahb_wr` writer - 21:21\\]
Status of Interrupt from APP_AHB Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppAhbWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_shared_mem_err` reader - 22:22\\]
Status of Interrupt from APP_SHARED_MEM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppSharedMemErrR = crate :: BitReader ; # [doc = "Field `app_shared_mem_err` writer - 22:22\\]
Status of Interrupt from APP_SHARED_MEM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppSharedMemErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_erroragg` reader - 23:23\\]
Status of Interrupt from FEC_ERRORAGG Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type FecErroraggR = crate :: BitReader ; # [doc = "Field `fec_erroragg` writer - 23:23\\]
Status of Interrupt from FEC_ERRORAGG Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type FecErroraggW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ahb_slv_wr` reader - 24:24\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppAhbSlvWrR = crate :: BitReader ; # [doc = "Field `app_ahb_slv_wr` writer - 24:24\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppAhbSlvWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_ahb_slv_rd` reader - 25:25\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppAhbSlvRdR = crate :: BitReader ; # [doc = "Field `app_ahb_slv_rd` writer - 25:25\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
pub type AppAhbSlvRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_rcm_rd (& self) -> AppRcmRdR { AppRcmRdR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_rcm_wr (& self) -> AppRcmWrR { AppRcmWrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_ctrl_rd (& self) -> AppCtrlRdR { AppCtrlRdR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_ctrl_wr (& self) -> AppCtrlWrR { AppCtrlWrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_idalloc_rd (& self) -> AppIdallocRdR { AppIdallocRdR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_idalloc_wr (& self) -> AppIdallocWrR { AppIdallocWrR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn adcbuff_ctrl_rd (& self) -> AdcbuffCtrlRdR { AdcbuffCtrlRdR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn adcbuff_ctrl_wr (& self) -> AdcbuffCtrlWrR { AdcbuffCtrlWrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn plldig_ctrl_rd (& self) -> PlldigCtrlRdR { PlldigCtrlRdR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn plldig_ctrl_wr (& self) -> PlldigCtrlWrR { PlldigCtrlWrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn topss_ctrl_rd (& self) -> TopssCtrlRdR { TopssCtrlRdR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn topss_ctrl_wr (& self) -> TopssCtrlWrR { TopssCtrlWrR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn apll_ctrl_rd (& self) -> ApllCtrlRdR { ApllCtrlRdR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn apll_ctrl_wr (& self) -> ApllCtrlWrR { ApllCtrlWrR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn frame_timer_rd (& self) -> FrameTimerRdR { FrameTimerRdR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn frame_timer_wr (& self) -> FrameTimerWrR { FrameTimerWrR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn top_prcm_rd (& self) -> TopPrcmRdR { TopPrcmRdR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn top_prcm_wr (& self) -> TopPrcmWrR { TopPrcmWrR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn top_efuse_ctrl_rd (& self) -> TopEfuseCtrlRdR { TopEfuseCtrlRdR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn top_efuse_ctrl_wr (& self) -> TopEfuseCtrlWrR { TopEfuseCtrlWrR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Status of Interrupt from APP_MPU Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_mpu_rd (& self) -> AppMpuRdR { AppMpuRdR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Status of Interrupt from APP_AHB Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_ahb_wr (& self) -> AppAhbWrR { AppAhbWrR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Status of Interrupt from APP_SHARED_MEM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_shared_mem_err (& self) -> AppSharedMemErrR { AppSharedMemErrR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Status of Interrupt from FEC_ERRORAGG Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn fec_erroragg (& self) -> FecErroraggR { FecErroraggR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_ahb_slv_wr (& self) -> AppAhbSlvWrR { AppAhbSlvWrR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn app_ahb_slv_rd (& self) -> AppAhbSlvRdR { AppAhbSlvRdR :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_rcm_rd (& mut self) -> AppRcmRdW < AppssErraggStatus0Spec > { AppRcmRdW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_rcm_wr (& mut self) -> AppRcmWrW < AppssErraggStatus0Spec > { AppRcmWrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_ctrl_rd (& mut self) -> AppCtrlRdW < AppssErraggStatus0Spec > { AppCtrlRdW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_ctrl_wr (& mut self) -> AppCtrlWrW < AppssErraggStatus0Spec > { AppCtrlWrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_idalloc_rd (& mut self) -> AppIdallocRdW < AppssErraggStatus0Spec > { AppIdallocRdW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_idalloc_wr (& mut self) -> AppIdallocWrW < AppssErraggStatus0Spec > { AppIdallocWrW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn adcbuff_ctrl_rd (& mut self) -> AdcbuffCtrlRdW < AppssErraggStatus0Spec > { AdcbuffCtrlRdW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn adcbuff_ctrl_wr (& mut self) -> AdcbuffCtrlWrW < AppssErraggStatus0Spec > { AdcbuffCtrlWrW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn plldig_ctrl_rd (& mut self) -> PlldigCtrlRdW < AppssErraggStatus0Spec > { PlldigCtrlRdW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn plldig_ctrl_wr (& mut self) -> PlldigCtrlWrW < AppssErraggStatus0Spec > { PlldigCtrlWrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn topss_ctrl_rd (& mut self) -> TopssCtrlRdW < AppssErraggStatus0Spec > { TopssCtrlRdW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn topss_ctrl_wr (& mut self) -> TopssCtrlWrW < AppssErraggStatus0Spec > { TopssCtrlWrW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn apll_ctrl_rd (& mut self) -> ApllCtrlRdW < AppssErraggStatus0Spec > { ApllCtrlRdW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn apll_ctrl_wr (& mut self) -> ApllCtrlWrW < AppssErraggStatus0Spec > { ApllCtrlWrW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn frame_timer_rd (& mut self) -> FrameTimerRdW < AppssErraggStatus0Spec > { FrameTimerRdW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn frame_timer_wr (& mut self) -> FrameTimerWrW < AppssErraggStatus0Spec > { FrameTimerWrW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn top_prcm_rd (& mut self) -> TopPrcmRdW < AppssErraggStatus0Spec > { TopPrcmRdW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn top_prcm_wr (& mut self) -> TopPrcmWrW < AppssErraggStatus0Spec > { TopPrcmWrW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn top_efuse_ctrl_rd (& mut self) -> TopEfuseCtrlRdW < AppssErraggStatus0Spec > { TopEfuseCtrlRdW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn top_efuse_ctrl_wr (& mut self) -> TopEfuseCtrlWrW < AppssErraggStatus0Spec > { TopEfuseCtrlWrW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Status of Interrupt from APP_MPU Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_mpu_rd (& mut self) -> AppMpuRdW < AppssErraggStatus0Spec > { AppMpuRdW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Status of Interrupt from APP_AHB Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_ahb_wr (& mut self) -> AppAhbWrW < AppssErraggStatus0Spec > { AppAhbWrW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Status of Interrupt from APP_SHARED_MEM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_shared_mem_err (& mut self) -> AppSharedMemErrW < AppssErraggStatus0Spec > { AppSharedMemErrW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Status of Interrupt from FEC_ERRORAGG Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn fec_erroragg (& mut self) -> FecErroraggW < AppssErraggStatus0Spec > { FecErroraggW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_ahb_slv_wr (& mut self) -> AppAhbSlvWrW < AppssErraggStatus0Spec > { AppAhbSlvWrW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn app_ahb_slv_rd (& mut self) -> AppAhbSlvRdW < AppssErraggStatus0Spec > { AppAhbSlvRdW :: new (self , 25) } } # [doc = "APPSS_ERRAGG_STATUS0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_status0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_status0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssErraggStatus0Spec ; impl crate :: RegisterSpec for AppssErraggStatus0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_erragg_status0::R`](R) reader structure"]
impl crate :: Readable for AppssErraggStatus0Spec { } # [doc = "`write(|w| ..)` method takes [`appss_erragg_status0::W`](W) writer structure"]
impl crate :: Writable for AppssErraggStatus0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_ERRAGG_STATUS0 to value 0"]
impl crate :: Resettable for AppssErraggStatus0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_A_ERRAGG_MASK (rw) register accessor: APPSS_TPCC_A_ERRAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_erragg_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_erragg_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_a_erragg_mask`]
module"]
# [doc (alias = "APPSS_TPCC_A_ERRAGG_MASK")]
pub type AppssTpccAErraggMask = crate :: Reg < appss_tpcc_a_erragg_mask :: AppssTpccAErraggMaskSpec > ; # [doc = "APPSS_TPCC_A_ERRAGG_MASK"]
pub mod appss_tpcc_a_erragg_mask { # [doc = "Register `APPSS_TPCC_A_ERRAGG_MASK` reader"]
pub type R = crate :: R < AppssTpccAErraggMaskSpec > ; # [doc = "Register `APPSS_TPCC_A_ERRAGG_MASK` writer"]
pub type W = crate :: W < AppssTpccAErraggMaskSpec > ; # [doc = "Field `tpcc_a_errint` reader - 0:0\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAErrintR = crate :: BitReader ; # [doc = "Field `tpcc_a_errint` writer - 0:0\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAErrintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_mpint` reader - 1:1\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAMpintR = crate :: BitReader ; # [doc = "Field `tpcc_a_mpint` writer - 1:1\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAMpintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_err` reader - 2:2\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA0ErrR = crate :: BitReader ; # [doc = "Field `tptc_a0_err` writer - 2:2\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA0ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_err` reader - 3:3\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA1ErrR = crate :: BitReader ; # [doc = "Field `tptc_a1_err` writer - 3:3\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA1ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_par_err` reader - 4:4\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAParErrR = crate :: BitReader ; # [doc = "Field `tpcc_a_par_err` writer - 4:4\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAParErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_write_access_error` reader - 16:16\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAWriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_a_write_access_error` writer - 16:16\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAWriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_write_access_error` reader - 17:17\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA0WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a0_write_access_error` writer - 17:17\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA0WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_write_access_error` reader - 18:18\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA1WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a1_write_access_error` writer - 18:18\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA1WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_read_access_error` reader - 24:24\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_a_read_access_error` writer - 24:24\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccAReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_read_access_error` reader - 25:25\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA0ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a0_read_access_error` writer - 25:25\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA0ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_read_access_error` reader - 26:26\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA1ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a1_read_access_error` writer - 26:26\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcA1ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_a_errint (& self) -> TpccAErrintR { TpccAErrintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_a_mpint (& self) -> TpccAMpintR { TpccAMpintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_a0_err (& self) -> TptcA0ErrR { TptcA0ErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_a1_err (& self) -> TptcA1ErrR { TptcA1ErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_a_par_err (& self) -> TpccAParErrR { TpccAParErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_a_write_access_error (& self) -> TpccAWriteAccessErrorR { TpccAWriteAccessErrorR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_a0_write_access_error (& self) -> TptcA0WriteAccessErrorR { TptcA0WriteAccessErrorR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_a1_write_access_error (& self) -> TptcA1WriteAccessErrorR { TptcA1WriteAccessErrorR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_a_read_access_error (& self) -> TpccAReadAccessErrorR { TpccAReadAccessErrorR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_a0_read_access_error (& self) -> TptcA0ReadAccessErrorR { TptcA0ReadAccessErrorR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_a1_read_access_error (& self) -> TptcA1ReadAccessErrorR { TptcA1ReadAccessErrorR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_errint (& mut self) -> TpccAErrintW < AppssTpccAErraggMaskSpec > { TpccAErrintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_mpint (& mut self) -> TpccAMpintW < AppssTpccAErraggMaskSpec > { TpccAMpintW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_err (& mut self) -> TptcA0ErrW < AppssTpccAErraggMaskSpec > { TptcA0ErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_err (& mut self) -> TptcA1ErrW < AppssTpccAErraggMaskSpec > { TptcA1ErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_par_err (& mut self) -> TpccAParErrW < AppssTpccAErraggMaskSpec > { TpccAParErrW :: new (self , 4) } # [doc = "Bit 16 - 16:16\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_write_access_error (& mut self) -> TpccAWriteAccessErrorW < AppssTpccAErraggMaskSpec > { TpccAWriteAccessErrorW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_write_access_error (& mut self) -> TptcA0WriteAccessErrorW < AppssTpccAErraggMaskSpec > { TptcA0WriteAccessErrorW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_write_access_error (& mut self) -> TptcA1WriteAccessErrorW < AppssTpccAErraggMaskSpec > { TptcA1WriteAccessErrorW :: new (self , 18) } # [doc = "Bit 24 - 24:24\\]
Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_read_access_error (& mut self) -> TpccAReadAccessErrorW < AppssTpccAErraggMaskSpec > { TpccAReadAccessErrorW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_read_access_error (& mut self) -> TptcA0ReadAccessErrorW < AppssTpccAErraggMaskSpec > { TptcA0ReadAccessErrorW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_read_access_error (& mut self) -> TptcA1ReadAccessErrorW < AppssTpccAErraggMaskSpec > { TptcA1ReadAccessErrorW :: new (self , 26) } } # [doc = "APPSS_TPCC_A_ERRAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_erragg_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_erragg_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccAErraggMaskSpec ; impl crate :: RegisterSpec for AppssTpccAErraggMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_a_erragg_mask::R`](R) reader structure"]
impl crate :: Readable for AppssTpccAErraggMaskSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_a_erragg_mask::W`](W) writer structure"]
impl crate :: Writable for AppssTpccAErraggMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_A_ERRAGG_MASK to value 0"]
impl crate :: Resettable for AppssTpccAErraggMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_A_ERRAGG_STATUS (rw) register accessor: APPSS_TPCC_A_ERRAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_erragg_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_erragg_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_a_erragg_status`]
module"]
# [doc (alias = "APPSS_TPCC_A_ERRAGG_STATUS")]
pub type AppssTpccAErraggStatus = crate :: Reg < appss_tpcc_a_erragg_status :: AppssTpccAErraggStatusSpec > ; # [doc = "APPSS_TPCC_A_ERRAGG_STATUS"]
pub mod appss_tpcc_a_erragg_status { # [doc = "Register `APPSS_TPCC_A_ERRAGG_STATUS` reader"]
pub type R = crate :: R < AppssTpccAErraggStatusSpec > ; # [doc = "Register `APPSS_TPCC_A_ERRAGG_STATUS` writer"]
pub type W = crate :: W < AppssTpccAErraggStatusSpec > ; # [doc = "Field `tpcc_a_errint` reader - 0:0\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAErrintR = crate :: BitReader ; # [doc = "Field `tpcc_a_errint` writer - 0:0\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAErrintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_mpint` reader - 1:1\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAMpintR = crate :: BitReader ; # [doc = "Field `tpcc_a_mpint` writer - 1:1\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAMpintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_err` reader - 2:2\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA0ErrR = crate :: BitReader ; # [doc = "Field `tptc_a0_err` writer - 2:2\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA0ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_err` reader - 3:3\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA1ErrR = crate :: BitReader ; # [doc = "Field `tptc_a1_err` writer - 3:3\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA1ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_par_err` reader - 4:4\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAParErrR = crate :: BitReader ; # [doc = "Field `tpcc_a_par_err` writer - 4:4\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAParErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_write_access_error` reader - 16:16\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAWriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_a_write_access_error` writer - 16:16\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAWriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_write_access_error` reader - 17:17\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA0WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a0_write_access_error` writer - 17:17\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA0WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_write_access_error` reader - 18:18\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA1WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a1_write_access_error` writer - 18:18\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA1WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_read_access_error` reader - 24:24\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_a_read_access_error` writer - 24:24\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccAReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_read_access_error` reader - 25:25\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA0ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a0_read_access_error` writer - 25:25\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA0ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_read_access_error` reader - 26:26\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA1ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a1_read_access_error` writer - 26:26\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcA1ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_a_errint (& self) -> TpccAErrintR { TpccAErrintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_a_mpint (& self) -> TpccAMpintR { TpccAMpintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_a0_err (& self) -> TptcA0ErrR { TptcA0ErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_a1_err (& self) -> TptcA1ErrR { TptcA1ErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_a_par_err (& self) -> TpccAParErrR { TpccAParErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_a_write_access_error (& self) -> TpccAWriteAccessErrorR { TpccAWriteAccessErrorR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_a0_write_access_error (& self) -> TptcA0WriteAccessErrorR { TptcA0WriteAccessErrorR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_a1_write_access_error (& self) -> TptcA1WriteAccessErrorR { TptcA1WriteAccessErrorR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_a_read_access_error (& self) -> TpccAReadAccessErrorR { TpccAReadAccessErrorR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_a0_read_access_error (& self) -> TptcA0ReadAccessErrorR { TptcA0ReadAccessErrorR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_a1_read_access_error (& self) -> TptcA1ReadAccessErrorR { TptcA1ReadAccessErrorR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_errint (& mut self) -> TpccAErrintW < AppssTpccAErraggStatusSpec > { TpccAErrintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_mpint (& mut self) -> TpccAMpintW < AppssTpccAErraggStatusSpec > { TpccAMpintW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_a0_err (& mut self) -> TptcA0ErrW < AppssTpccAErraggStatusSpec > { TptcA0ErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_a1_err (& mut self) -> TptcA1ErrW < AppssTpccAErraggStatusSpec > { TptcA1ErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_par_err (& mut self) -> TpccAParErrW < AppssTpccAErraggStatusSpec > { TpccAParErrW :: new (self , 4) } # [doc = "Bit 16 - 16:16\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_write_access_error (& mut self) -> TpccAWriteAccessErrorW < AppssTpccAErraggStatusSpec > { TpccAWriteAccessErrorW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_a0_write_access_error (& mut self) -> TptcA0WriteAccessErrorW < AppssTpccAErraggStatusSpec > { TptcA0WriteAccessErrorW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_a1_write_access_error (& mut self) -> TptcA1WriteAccessErrorW < AppssTpccAErraggStatusSpec > { TptcA1WriteAccessErrorW :: new (self , 18) } # [doc = "Bit 24 - 24:24\\]
Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_read_access_error (& mut self) -> TpccAReadAccessErrorW < AppssTpccAErraggStatusSpec > { TpccAReadAccessErrorW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_a0_read_access_error (& mut self) -> TptcA0ReadAccessErrorW < AppssTpccAErraggStatusSpec > { TptcA0ReadAccessErrorW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_a1_read_access_error (& mut self) -> TptcA1ReadAccessErrorW < AppssTpccAErraggStatusSpec > { TptcA1ReadAccessErrorW :: new (self , 26) } } # [doc = "APPSS_TPCC_A_ERRAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_erragg_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_erragg_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccAErraggStatusSpec ; impl crate :: RegisterSpec for AppssTpccAErraggStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_a_erragg_status::R`](R) reader structure"]
impl crate :: Readable for AppssTpccAErraggStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_a_erragg_status::W`](W) writer structure"]
impl crate :: Writable for AppssTpccAErraggStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_A_ERRAGG_STATUS to value 0"]
impl crate :: Resettable for AppssTpccAErraggStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_A_ERRAGG_STATUS_RAW (rw) register accessor: APPSS_TPCC_A_ERRAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_erragg_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_erragg_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_a_erragg_status_raw`]
module"]
# [doc (alias = "APPSS_TPCC_A_ERRAGG_STATUS_RAW")]
pub type AppssTpccAErraggStatusRaw = crate :: Reg < appss_tpcc_a_erragg_status_raw :: AppssTpccAErraggStatusRawSpec > ; # [doc = "APPSS_TPCC_A_ERRAGG_STATUS_RAW"]
pub mod appss_tpcc_a_erragg_status_raw { # [doc = "Register `APPSS_TPCC_A_ERRAGG_STATUS_RAW` reader"]
pub type R = crate :: R < AppssTpccAErraggStatusRawSpec > ; # [doc = "Register `APPSS_TPCC_A_ERRAGG_STATUS_RAW` writer"]
pub type W = crate :: W < AppssTpccAErraggStatusRawSpec > ; # [doc = "Field `tpcc_a_errint` reader - 0:0\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAErrintR = crate :: BitReader ; # [doc = "Field `tpcc_a_errint` writer - 0:0\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAErrintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_mpint` reader - 1:1\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAMpintR = crate :: BitReader ; # [doc = "Field `tpcc_a_mpint` writer - 1:1\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAMpintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_err` reader - 2:2\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA0ErrR = crate :: BitReader ; # [doc = "Field `tptc_a0_err` writer - 2:2\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA0ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_err` reader - 3:3\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA1ErrR = crate :: BitReader ; # [doc = "Field `tptc_a1_err` writer - 3:3\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA1ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_par_err` reader - 4:4\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAParErrR = crate :: BitReader ; # [doc = "Field `tpcc_a_par_err` writer - 4:4\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAParErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_write_access_error` reader - 16:16\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAWriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_a_write_access_error` writer - 16:16\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAWriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_write_access_error` reader - 17:17\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA0WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a0_write_access_error` writer - 17:17\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA0WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_write_access_error` reader - 18:18\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA1WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a1_write_access_error` writer - 18:18\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA1WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_read_access_error` reader - 24:24\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_a_read_access_error` writer - 24:24\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TpccAReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0_read_access_error` reader - 25:25\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA0ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a0_read_access_error` writer - 25:25\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA0ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_read_access_error` reader - 26:26\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA1ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_a1_read_access_error` writer - 26:26\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
pub type TptcA1ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_errint (& self) -> TpccAErrintR { TpccAErrintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_mpint (& self) -> TpccAMpintR { TpccAMpintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_a0_err (& self) -> TptcA0ErrR { TptcA0ErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_a1_err (& self) -> TptcA1ErrR { TptcA1ErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_par_err (& self) -> TpccAParErrR { TpccAParErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_write_access_error (& self) -> TpccAWriteAccessErrorR { TpccAWriteAccessErrorR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_a0_write_access_error (& self) -> TptcA0WriteAccessErrorR { TptcA0WriteAccessErrorR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_a1_write_access_error (& self) -> TptcA1WriteAccessErrorR { TptcA1WriteAccessErrorR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_read_access_error (& self) -> TpccAReadAccessErrorR { TpccAReadAccessErrorR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_a0_read_access_error (& self) -> TptcA0ReadAccessErrorR { TptcA0ReadAccessErrorR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_a1_read_access_error (& self) -> TptcA1ReadAccessErrorR { TptcA1ReadAccessErrorR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_errint (& mut self) -> TpccAErrintW < AppssTpccAErraggStatusRawSpec > { TpccAErrintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_mpint (& mut self) -> TpccAMpintW < AppssTpccAErraggStatusRawSpec > { TpccAMpintW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_err (& mut self) -> TptcA0ErrW < AppssTpccAErraggStatusRawSpec > { TptcA0ErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_err (& mut self) -> TptcA1ErrW < AppssTpccAErraggStatusRawSpec > { TptcA1ErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_par_err (& mut self) -> TpccAParErrW < AppssTpccAErraggStatusRawSpec > { TpccAParErrW :: new (self , 4) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_write_access_error (& mut self) -> TpccAWriteAccessErrorW < AppssTpccAErraggStatusRawSpec > { TpccAWriteAccessErrorW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_write_access_error (& mut self) -> TptcA0WriteAccessErrorW < AppssTpccAErraggStatusRawSpec > { TptcA0WriteAccessErrorW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_write_access_error (& mut self) -> TptcA1WriteAccessErrorW < AppssTpccAErraggStatusRawSpec > { TptcA1WriteAccessErrorW :: new (self , 18) } # [doc = "Bit 24 - 24:24\\]
Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_read_access_error (& mut self) -> TpccAReadAccessErrorW < AppssTpccAErraggStatusRawSpec > { TpccAReadAccessErrorW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_read_access_error (& mut self) -> TptcA0ReadAccessErrorW < AppssTpccAErraggStatusRawSpec > { TptcA0ReadAccessErrorW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_read_access_error (& mut self) -> TptcA1ReadAccessErrorW < AppssTpccAErraggStatusRawSpec > { TptcA1ReadAccessErrorW :: new (self , 26) } } # [doc = "APPSS_TPCC_A_ERRAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_erragg_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_erragg_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccAErraggStatusRawSpec ; impl crate :: RegisterSpec for AppssTpccAErraggStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_a_erragg_status_raw::R`](R) reader structure"]
impl crate :: Readable for AppssTpccAErraggStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_a_erragg_status_raw::W`](W) writer structure"]
impl crate :: Writable for AppssTpccAErraggStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_A_ERRAGG_STATUS_RAW to value 0"]
impl crate :: Resettable for AppssTpccAErraggStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_A_INTAGG_MASK (rw) register accessor: APPSS_TPCC_A_INTAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_intagg_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_intagg_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_a_intagg_mask`]
module"]
# [doc (alias = "APPSS_TPCC_A_INTAGG_MASK")]
pub type AppssTpccAIntaggMask = crate :: Reg < appss_tpcc_a_intagg_mask :: AppssTpccAIntaggMaskSpec > ; # [doc = "APPSS_TPCC_A_INTAGG_MASK"]
pub mod appss_tpcc_a_intagg_mask { # [doc = "Register `APPSS_TPCC_A_INTAGG_MASK` reader"]
pub type R = crate :: R < AppssTpccAIntaggMaskSpec > ; # [doc = "Register `APPSS_TPCC_A_INTAGG_MASK` writer"]
pub type W = crate :: W < AppssTpccAIntaggMaskSpec > ; # [doc = "Field `tpcc_a_intg` reader - 0:0\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAIntgR = crate :: BitReader ; # [doc = "Field `tpcc_a_intg` writer - 0:0\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAIntgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int0` reader - 1:1\\]
Mask Interrupt from TPCC A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt0R = crate :: BitReader ; # [doc = "Field `tpcc_a_int0` writer - 1:1\\]
Mask Interrupt from TPCC A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int1` reader - 2:2\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt1R = crate :: BitReader ; # [doc = "Field `tpcc_a_int1` writer - 2:2\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int2` reader - 3:3\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt2R = crate :: BitReader ; # [doc = "Field `tpcc_a_int2` writer - 3:3\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int3` reader - 4:4\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt3R = crate :: BitReader ; # [doc = "Field `tpcc_a_int3` writer - 4:4\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int4` reader - 5:5\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt4R = crate :: BitReader ; # [doc = "Field `tpcc_a_int4` writer - 5:5\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int5` reader - 6:6\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt5R = crate :: BitReader ; # [doc = "Field `tpcc_a_int5` writer - 6:6\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int6` reader - 7:7\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt6R = crate :: BitReader ; # [doc = "Field `tpcc_a_int6` writer - 7:7\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int7` reader - 8:8\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt7R = crate :: BitReader ; # [doc = "Field `tpcc_a_int7` writer - 8:8\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccAInt7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0` reader - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcA0R = crate :: BitReader ; # [doc = "Field `tptc_a0` writer - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcA0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1` reader - 17:17\\]
Mask Interrupt from TPTC A1 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcA1R = crate :: BitReader ; # [doc = "Field `tptc_a1` writer - 17:17\\]
Mask Interrupt from TPTC A1 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcA1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_intg (& self) -> TpccAIntgR { TpccAIntgR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from TPCC A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int0 (& self) -> TpccAInt0R { TpccAInt0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int1 (& self) -> TpccAInt1R { TpccAInt1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int2 (& self) -> TpccAInt2R { TpccAInt2R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int3 (& self) -> TpccAInt3R { TpccAInt3R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int4 (& self) -> TpccAInt4R { TpccAInt4R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int5 (& self) -> TpccAInt5R { TpccAInt5R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int6 (& self) -> TpccAInt6R { TpccAInt6R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_a_int7 (& self) -> TpccAInt7R { TpccAInt7R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Mask Interrupt from TPTC A1 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_intg (& mut self) -> TpccAIntgW < AppssTpccAIntaggMaskSpec > { TpccAIntgW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from TPCC A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int0 (& mut self) -> TpccAInt0W < AppssTpccAIntaggMaskSpec > { TpccAInt0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int1 (& mut self) -> TpccAInt1W < AppssTpccAIntaggMaskSpec > { TpccAInt1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int2 (& mut self) -> TpccAInt2W < AppssTpccAIntaggMaskSpec > { TpccAInt2W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int3 (& mut self) -> TpccAInt3W < AppssTpccAIntaggMaskSpec > { TpccAInt3W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int4 (& mut self) -> TpccAInt4W < AppssTpccAIntaggMaskSpec > { TpccAInt4W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int5 (& mut self) -> TpccAInt5W < AppssTpccAIntaggMaskSpec > { TpccAInt5W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int6 (& mut self) -> TpccAInt6W < AppssTpccAIntaggMaskSpec > { TpccAInt6W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int7 (& mut self) -> TpccAInt7W < AppssTpccAIntaggMaskSpec > { TpccAInt7W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < AppssTpccAIntaggMaskSpec > { TptcA0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Mask Interrupt from TPTC A1 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < AppssTpccAIntaggMaskSpec > { TptcA1W :: new (self , 17) } } # [doc = "APPSS_TPCC_A_INTAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_intagg_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_intagg_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccAIntaggMaskSpec ; impl crate :: RegisterSpec for AppssTpccAIntaggMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_a_intagg_mask::R`](R) reader structure"]
impl crate :: Readable for AppssTpccAIntaggMaskSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_a_intagg_mask::W`](W) writer structure"]
impl crate :: Writable for AppssTpccAIntaggMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_A_INTAGG_MASK to value 0"]
impl crate :: Resettable for AppssTpccAIntaggMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_WPH (rw) register accessor: HW_SPARE_WPH\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_wph::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_wph::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_wph`]
module"]
# [doc (alias = "HW_SPARE_WPH")]
pub type HwSpareWph = crate :: Reg < hw_spare_wph :: HwSpareWphSpec > ; # [doc = "HW_SPARE_WPH"]
pub mod hw_spare_wph { # [doc = "Register `HW_SPARE_WPH` reader"]
pub type R = crate :: R < HwSpareWphSpec > ; # [doc = "Register `HW_SPARE_WPH` writer"]
pub type W = crate :: W < HwSpareWphSpec > ; # [doc = "Field `tpcc_a_intg` reader - 0:0\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAIntgR = crate :: BitReader ; # [doc = "Field `tpcc_a_intg` writer - 0:0\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAIntgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int0` reader - 1:1\\]
Status of Interrupt from TPCC A Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt0R = crate :: BitReader ; # [doc = "Field `tpcc_a_int0` writer - 1:1\\]
Status of Interrupt from TPCC A Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int1` reader - 2:2\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt1R = crate :: BitReader ; # [doc = "Field `tpcc_a_int1` writer - 2:2\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int2` reader - 3:3\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt2R = crate :: BitReader ; # [doc = "Field `tpcc_a_int2` writer - 3:3\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int3` reader - 4:4\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt3R = crate :: BitReader ; # [doc = "Field `tpcc_a_int3` writer - 4:4\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int4` reader - 5:5\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt4R = crate :: BitReader ; # [doc = "Field `tpcc_a_int4` writer - 5:5\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int5` reader - 6:6\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt5R = crate :: BitReader ; # [doc = "Field `tpcc_a_int5` writer - 6:6\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int6` reader - 7:7\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt6R = crate :: BitReader ; # [doc = "Field `tpcc_a_int6` writer - 7:7\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int7` reader - 8:8\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt7R = crate :: BitReader ; # [doc = "Field `tpcc_a_int7` writer - 8:8\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccAInt7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0` reader - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcA0R = crate :: BitReader ; # [doc = "Field `tptc_a0` writer - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcA0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1` reader - 17:17\\]
Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcA1R = crate :: BitReader ; # [doc = "Field `tptc_a1` writer - 17:17\\]
Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcA1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_intg (& self) -> TpccAIntgR { TpccAIntgR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from TPCC A Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int0 (& self) -> TpccAInt0R { TpccAInt0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int1 (& self) -> TpccAInt1R { TpccAInt1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int2 (& self) -> TpccAInt2R { TpccAInt2R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int3 (& self) -> TpccAInt3R { TpccAInt3R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int4 (& self) -> TpccAInt4R { TpccAInt4R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int5 (& self) -> TpccAInt5R { TpccAInt5R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int6 (& self) -> TpccAInt6R { TpccAInt6R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_a_int7 (& self) -> TpccAInt7R { TpccAInt7R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_intg (& mut self) -> TpccAIntgW < HwSpareWphSpec > { TpccAIntgW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from TPCC A Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int0 (& mut self) -> TpccAInt0W < HwSpareWphSpec > { TpccAInt0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int1 (& mut self) -> TpccAInt1W < HwSpareWphSpec > { TpccAInt1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int2 (& mut self) -> TpccAInt2W < HwSpareWphSpec > { TpccAInt2W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int3 (& mut self) -> TpccAInt3W < HwSpareWphSpec > { TpccAInt3W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int4 (& mut self) -> TpccAInt4W < HwSpareWphSpec > { TpccAInt4W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int5 (& mut self) -> TpccAInt5W < HwSpareWphSpec > { TpccAInt5W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int6 (& mut self) -> TpccAInt6W < HwSpareWphSpec > { TpccAInt6W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int7 (& mut self) -> TpccAInt7W < HwSpareWphSpec > { TpccAInt7W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < HwSpareWphSpec > { TptcA0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < HwSpareWphSpec > { TptcA1W :: new (self , 17) } } # [doc = "HW_SPARE_WPH\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_wph::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_wph::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareWphSpec ; impl crate :: RegisterSpec for HwSpareWphSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_wph::R`](R) reader structure"]
impl crate :: Readable for HwSpareWphSpec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_wph::W`](W) writer structure"]
impl crate :: Writable for HwSpareWphSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_WPH to value 0"]
impl crate :: Resettable for HwSpareWphSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_A_INTAGG_STATUS_RAW (rw) register accessor: APPSS_TPCC_A_INTAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_intagg_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_intagg_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_a_intagg_status_raw`]
module"]
# [doc (alias = "APPSS_TPCC_A_INTAGG_STATUS_RAW")]
pub type AppssTpccAIntaggStatusRaw = crate :: Reg < appss_tpcc_a_intagg_status_raw :: AppssTpccAIntaggStatusRawSpec > ; # [doc = "APPSS_TPCC_A_INTAGG_STATUS_RAW"]
pub mod appss_tpcc_a_intagg_status_raw { # [doc = "Register `APPSS_TPCC_A_INTAGG_STATUS_RAW` reader"]
pub type R = crate :: R < AppssTpccAIntaggStatusRawSpec > ; # [doc = "Register `APPSS_TPCC_A_INTAGG_STATUS_RAW` writer"]
pub type W = crate :: W < AppssTpccAIntaggStatusRawSpec > ; # [doc = "Field `tpcc_a_intg` reader - 0:0\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAIntgR = crate :: BitReader ; # [doc = "Field `tpcc_a_intg` writer - 0:0\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAIntgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int0` reader - 1:1\\]
Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TpccAInt0R = crate :: BitReader ; # [doc = "Field `tpcc_a_int0` writer - 1:1\\]
Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TpccAInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int1` reader - 2:2\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt1R = crate :: BitReader ; # [doc = "Field `tpcc_a_int1` writer - 2:2\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int2` reader - 3:3\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt2R = crate :: BitReader ; # [doc = "Field `tpcc_a_int2` writer - 3:3\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int3` reader - 4:4\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt3R = crate :: BitReader ; # [doc = "Field `tpcc_a_int3` writer - 4:4\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int4` reader - 5:5\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt4R = crate :: BitReader ; # [doc = "Field `tpcc_a_int4` writer - 5:5\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int5` reader - 6:6\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt5R = crate :: BitReader ; # [doc = "Field `tpcc_a_int5` writer - 6:6\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int6` reader - 7:7\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt6R = crate :: BitReader ; # [doc = "Field `tpcc_a_int6` writer - 7:7\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_a_int7` reader - 8:8\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt7R = crate :: BitReader ; # [doc = "Field `tpcc_a_int7` writer - 8:8\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccAInt7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a0` reader - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcA0R = crate :: BitReader ; # [doc = "Field `tptc_a0` writer - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcA0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1` reader - 17:17\\]
Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcA1R = crate :: BitReader ; # [doc = "Field `tptc_a1` writer - 17:17\\]
Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcA1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_intg (& self) -> TpccAIntgR { TpccAIntgR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int0 (& self) -> TpccAInt0R { TpccAInt0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int1 (& self) -> TpccAInt1R { TpccAInt1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int2 (& self) -> TpccAInt2R { TpccAInt2R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int3 (& self) -> TpccAInt3R { TpccAInt3R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int4 (& self) -> TpccAInt4R { TpccAInt4R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int5 (& self) -> TpccAInt5R { TpccAInt5R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int6 (& self) -> TpccAInt6R { TpccAInt6R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_a_int7 (& self) -> TpccAInt7R { TpccAInt7R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_intg (& mut self) -> TpccAIntgW < AppssTpccAIntaggStatusRawSpec > { TpccAIntgW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int0 (& mut self) -> TpccAInt0W < AppssTpccAIntaggStatusRawSpec > { TpccAInt0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int1 (& mut self) -> TpccAInt1W < AppssTpccAIntaggStatusRawSpec > { TpccAInt1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int2 (& mut self) -> TpccAInt2W < AppssTpccAIntaggStatusRawSpec > { TpccAInt2W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int3 (& mut self) -> TpccAInt3W < AppssTpccAIntaggStatusRawSpec > { TpccAInt3W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int4 (& mut self) -> TpccAInt4W < AppssTpccAIntaggStatusRawSpec > { TpccAInt4W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int5 (& mut self) -> TpccAInt5W < AppssTpccAIntaggStatusRawSpec > { TpccAInt5W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int6 (& mut self) -> TpccAInt6W < AppssTpccAIntaggStatusRawSpec > { TpccAInt6W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_a_int7 (& mut self) -> TpccAInt7W < AppssTpccAIntaggStatusRawSpec > { TpccAInt7W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < AppssTpccAIntaggStatusRawSpec > { TptcA0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < AppssTpccAIntaggStatusRawSpec > { TptcA1W :: new (self , 17) } } # [doc = "APPSS_TPCC_A_INTAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_a_intagg_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_a_intagg_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccAIntaggStatusRawSpec ; impl crate :: RegisterSpec for AppssTpccAIntaggStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_a_intagg_status_raw::R`](R) reader structure"]
impl crate :: Readable for AppssTpccAIntaggStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_a_intagg_status_raw::W`](W) writer structure"]
impl crate :: Writable for AppssTpccAIntaggStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_A_INTAGG_STATUS_RAW to value 0"]
impl crate :: Resettable for AppssTpccAIntaggStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_B_ERRAGG_MASK (rw) register accessor: APPSS_TPCC_B_ERRAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_erragg_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_erragg_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_b_erragg_mask`]
module"]
# [doc (alias = "APPSS_TPCC_B_ERRAGG_MASK")]
pub type AppssTpccBErraggMask = crate :: Reg < appss_tpcc_b_erragg_mask :: AppssTpccBErraggMaskSpec > ; # [doc = "APPSS_TPCC_B_ERRAGG_MASK"]
pub mod appss_tpcc_b_erragg_mask { # [doc = "Register `APPSS_TPCC_B_ERRAGG_MASK` reader"]
pub type R = crate :: R < AppssTpccBErraggMaskSpec > ; # [doc = "Register `APPSS_TPCC_B_ERRAGG_MASK` writer"]
pub type W = crate :: W < AppssTpccBErraggMaskSpec > ; # [doc = "Field `tpcc_b_errint` reader - 0:0\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBErrintR = crate :: BitReader ; # [doc = "Field `tpcc_b_errint` writer - 0:0\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBErrintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_mpint` reader - 1:1\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBMpintR = crate :: BitReader ; # [doc = "Field `tpcc_b_mpint` writer - 1:1\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBMpintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_err` reader - 2:2\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB0ErrR = crate :: BitReader ; # [doc = "Field `tptc_b0_err` writer - 2:2\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB0ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_err` reader - 3:3\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB1ErrR = crate :: BitReader ; # [doc = "Field `tptc_b1_err` writer - 3:3\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB1ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_par_err` reader - 4:4\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBParErrR = crate :: BitReader ; # [doc = "Field `tpcc_b_par_err` writer - 4:4\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBParErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_write_access_error` reader - 14:14\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB1WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b1_write_access_error` writer - 14:14\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB1WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_write_access_error` reader - 16:16\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBWriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_b_write_access_error` writer - 16:16\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBWriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_write_access_error` reader - 17:17\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB0WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b0_write_access_error` writer - 17:17\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB0WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_read_access_error` reader - 24:24\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_b_read_access_error` writer - 24:24\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TpccBReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_read_access_error` reader - 25:25\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB0ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b0_read_access_error` writer - 25:25\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB0ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_read_access_error` reader - 26:26\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB1ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b1_read_access_error` writer - 26:26\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
pub type TptcB1ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_b_errint (& self) -> TpccBErrintR { TpccBErrintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_b_mpint (& self) -> TpccBMpintR { TpccBMpintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_b0_err (& self) -> TptcB0ErrR { TptcB0ErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_b1_err (& self) -> TptcB1ErrR { TptcB1ErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_b_par_err (& self) -> TpccBParErrR { TpccBParErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_b1_write_access_error (& self) -> TptcB1WriteAccessErrorR { TptcB1WriteAccessErrorR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_b_write_access_error (& self) -> TpccBWriteAccessErrorR { TpccBWriteAccessErrorR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_b0_write_access_error (& self) -> TptcB0WriteAccessErrorR { TptcB0WriteAccessErrorR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tpcc_b_read_access_error (& self) -> TpccBReadAccessErrorR { TpccBReadAccessErrorR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_b0_read_access_error (& self) -> TptcB0ReadAccessErrorR { TptcB0ReadAccessErrorR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
pub fn tptc_b1_read_access_error (& self) -> TptcB1ReadAccessErrorR { TptcB1ReadAccessErrorR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_errint (& mut self) -> TpccBErrintW < AppssTpccBErraggMaskSpec > { TpccBErrintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_mpint (& mut self) -> TpccBMpintW < AppssTpccBErraggMaskSpec > { TpccBMpintW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_err (& mut self) -> TptcB0ErrW < AppssTpccBErraggMaskSpec > { TptcB0ErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_err (& mut self) -> TptcB1ErrW < AppssTpccBErraggMaskSpec > { TptcB1ErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_par_err (& mut self) -> TpccBParErrW < AppssTpccBErraggMaskSpec > { TpccBParErrW :: new (self , 4) } # [doc = "Bit 14 - 14:14\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_write_access_error (& mut self) -> TptcB1WriteAccessErrorW < AppssTpccBErraggMaskSpec > { TptcB1WriteAccessErrorW :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_write_access_error (& mut self) -> TpccBWriteAccessErrorW < AppssTpccBErraggMaskSpec > { TpccBWriteAccessErrorW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_write_access_error (& mut self) -> TptcB0WriteAccessErrorW < AppssTpccBErraggMaskSpec > { TptcB0WriteAccessErrorW :: new (self , 17) } # [doc = "Bit 24 - 24:24\\]
Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_read_access_error (& mut self) -> TpccBReadAccessErrorW < AppssTpccBErraggMaskSpec > { TpccBReadAccessErrorW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_read_access_error (& mut self) -> TptcB0ReadAccessErrorW < AppssTpccBErraggMaskSpec > { TptcB0ReadAccessErrorW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_read_access_error (& mut self) -> TptcB1ReadAccessErrorW < AppssTpccBErraggMaskSpec > { TptcB1ReadAccessErrorW :: new (self , 26) } } # [doc = "APPSS_TPCC_B_ERRAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_erragg_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_erragg_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccBErraggMaskSpec ; impl crate :: RegisterSpec for AppssTpccBErraggMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_b_erragg_mask::R`](R) reader structure"]
impl crate :: Readable for AppssTpccBErraggMaskSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_b_erragg_mask::W`](W) writer structure"]
impl crate :: Writable for AppssTpccBErraggMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_B_ERRAGG_MASK to value 0"]
impl crate :: Resettable for AppssTpccBErraggMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_B_ERRAGG_STATUS (rw) register accessor: APPSS_TPCC_B_ERRAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_erragg_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_erragg_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_b_erragg_status`]
module"]
# [doc (alias = "APPSS_TPCC_B_ERRAGG_STATUS")]
pub type AppssTpccBErraggStatus = crate :: Reg < appss_tpcc_b_erragg_status :: AppssTpccBErraggStatusSpec > ; # [doc = "APPSS_TPCC_B_ERRAGG_STATUS"]
pub mod appss_tpcc_b_erragg_status { # [doc = "Register `APPSS_TPCC_B_ERRAGG_STATUS` reader"]
pub type R = crate :: R < AppssTpccBErraggStatusSpec > ; # [doc = "Register `APPSS_TPCC_B_ERRAGG_STATUS` writer"]
pub type W = crate :: W < AppssTpccBErraggStatusSpec > ; # [doc = "Field `tpcc_b_errint` reader - 0:0\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBErrintR = crate :: BitReader ; # [doc = "Field `tpcc_b_errint` writer - 0:0\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBErrintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_mpint` reader - 1:1\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBMpintR = crate :: BitReader ; # [doc = "Field `tpcc_b_mpint` writer - 1:1\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBMpintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_err` reader - 2:2\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB0ErrR = crate :: BitReader ; # [doc = "Field `tptc_b0_err` writer - 2:2\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB0ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_err` reader - 3:3\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB1ErrR = crate :: BitReader ; # [doc = "Field `tptc_b1_err` writer - 3:3\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB1ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_par_err` reader - 4:4\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBParErrR = crate :: BitReader ; # [doc = "Field `tpcc_b_par_err` writer - 4:4\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBParErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_write_access_error` reader - 14:14\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB1WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b1_write_access_error` writer - 14:14\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB1WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_write_access_error` reader - 16:16\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBWriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_b_write_access_error` writer - 16:16\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBWriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_write_access_error` reader - 17:17\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB0WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b0_write_access_error` writer - 17:17\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB0WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_read_access_error` reader - 24:24\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_b_read_access_error` writer - 24:24\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TpccBReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_read_access_error` reader - 25:25\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB0ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b0_read_access_error` writer - 25:25\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB0ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_read_access_error` reader - 26:26\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB1ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b1_read_access_error` writer - 26:26\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
pub type TptcB1ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_b_errint (& self) -> TpccBErrintR { TpccBErrintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_b_mpint (& self) -> TpccBMpintR { TpccBMpintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_b0_err (& self) -> TptcB0ErrR { TptcB0ErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_b1_err (& self) -> TptcB1ErrR { TptcB1ErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_b_par_err (& self) -> TpccBParErrR { TpccBParErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_b1_write_access_error (& self) -> TptcB1WriteAccessErrorR { TptcB1WriteAccessErrorR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_b_write_access_error (& self) -> TpccBWriteAccessErrorR { TpccBWriteAccessErrorR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_b0_write_access_error (& self) -> TptcB0WriteAccessErrorR { TptcB0WriteAccessErrorR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tpcc_b_read_access_error (& self) -> TpccBReadAccessErrorR { TpccBReadAccessErrorR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_b0_read_access_error (& self) -> TptcB0ReadAccessErrorR { TptcB0ReadAccessErrorR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
pub fn tptc_b1_read_access_error (& self) -> TptcB1ReadAccessErrorR { TptcB1ReadAccessErrorR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_errint (& mut self) -> TpccBErrintW < AppssTpccBErraggStatusSpec > { TpccBErrintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_mpint (& mut self) -> TpccBMpintW < AppssTpccBErraggStatusSpec > { TpccBMpintW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_b0_err (& mut self) -> TptcB0ErrW < AppssTpccBErraggStatusSpec > { TptcB0ErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_b1_err (& mut self) -> TptcB1ErrW < AppssTpccBErraggStatusSpec > { TptcB1ErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_par_err (& mut self) -> TpccBParErrW < AppssTpccBErraggStatusSpec > { TpccBParErrW :: new (self , 4) } # [doc = "Bit 14 - 14:14\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_b1_write_access_error (& mut self) -> TptcB1WriteAccessErrorW < AppssTpccBErraggStatusSpec > { TptcB1WriteAccessErrorW :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_write_access_error (& mut self) -> TpccBWriteAccessErrorW < AppssTpccBErraggStatusSpec > { TpccBWriteAccessErrorW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_b0_write_access_error (& mut self) -> TptcB0WriteAccessErrorW < AppssTpccBErraggStatusSpec > { TptcB0WriteAccessErrorW :: new (self , 17) } # [doc = "Bit 24 - 24:24\\]
Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_read_access_error (& mut self) -> TpccBReadAccessErrorW < AppssTpccBErraggStatusSpec > { TpccBReadAccessErrorW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_b0_read_access_error (& mut self) -> TptcB0ReadAccessErrorW < AppssTpccBErraggStatusSpec > { TptcB0ReadAccessErrorW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error."]
# [inline (always)]
# [must_use]
pub fn tptc_b1_read_access_error (& mut self) -> TptcB1ReadAccessErrorW < AppssTpccBErraggStatusSpec > { TptcB1ReadAccessErrorW :: new (self , 26) } } # [doc = "APPSS_TPCC_B_ERRAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_erragg_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_erragg_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccBErraggStatusSpec ; impl crate :: RegisterSpec for AppssTpccBErraggStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_b_erragg_status::R`](R) reader structure"]
impl crate :: Readable for AppssTpccBErraggStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_b_erragg_status::W`](W) writer structure"]
impl crate :: Writable for AppssTpccBErraggStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_B_ERRAGG_STATUS to value 0"]
impl crate :: Resettable for AppssTpccBErraggStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_B_ERRAGG_STATUS_RAW (rw) register accessor: APPSS_TPCC_B_ERRAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_erragg_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_erragg_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_b_erragg_status_raw`]
module"]
# [doc (alias = "APPSS_TPCC_B_ERRAGG_STATUS_RAW")]
pub type AppssTpccBErraggStatusRaw = crate :: Reg < appss_tpcc_b_erragg_status_raw :: AppssTpccBErraggStatusRawSpec > ; # [doc = "APPSS_TPCC_B_ERRAGG_STATUS_RAW"]
pub mod appss_tpcc_b_erragg_status_raw { # [doc = "Register `APPSS_TPCC_B_ERRAGG_STATUS_RAW` reader"]
pub type R = crate :: R < AppssTpccBErraggStatusRawSpec > ; # [doc = "Register `APPSS_TPCC_B_ERRAGG_STATUS_RAW` writer"]
pub type W = crate :: W < AppssTpccBErraggStatusRawSpec > ; # [doc = "Field `tpcc_b_errint` reader - 0:0\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBErrintR = crate :: BitReader ; # [doc = "Field `tpcc_b_errint` writer - 0:0\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBErrintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_mpint` reader - 1:1\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBMpintR = crate :: BitReader ; # [doc = "Field `tpcc_b_mpint` writer - 1:1\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBMpintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_err` reader - 2:2\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB0ErrR = crate :: BitReader ; # [doc = "Field `tptc_b0_err` writer - 2:2\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB0ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_err` reader - 3:3\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB1ErrR = crate :: BitReader ; # [doc = "Field `tptc_b1_err` writer - 3:3\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB1ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_par_err` reader - 4:4\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBParErrR = crate :: BitReader ; # [doc = "Field `tpcc_b_par_err` writer - 4:4\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBParErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_write_access_error` reader - 14:14\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB1WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b1_write_access_error` writer - 14:14\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB1WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_write_access_error` reader - 16:16\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBWriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_b_write_access_error` writer - 16:16\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBWriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_write_access_error` reader - 17:17\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB0WriteAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b0_write_access_error` writer - 17:17\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB0WriteAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_read_access_error` reader - 24:24\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tpcc_b_read_access_error` writer - 24:24\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TpccBReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_read_access_error` reader - 25:25\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB0ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b0_read_access_error` writer - 25:25\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB0ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_read_access_error` reader - 26:26\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB1ReadAccessErrorR = crate :: BitReader ; # [doc = "Field `tptc_b1_read_access_error` writer - 26:26\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
pub type TptcB1ReadAccessErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_errint (& self) -> TpccBErrintR { TpccBErrintR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_mpint (& self) -> TpccBMpintR { TpccBMpintR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_b0_err (& self) -> TptcB0ErrR { TptcB0ErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_b1_err (& self) -> TptcB1ErrR { TptcB1ErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_par_err (& self) -> TpccBParErrR { TpccBParErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_b1_write_access_error (& self) -> TptcB1WriteAccessErrorR { TptcB1WriteAccessErrorR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_write_access_error (& self) -> TpccBWriteAccessErrorR { TpccBWriteAccessErrorR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_b0_write_access_error (& self) -> TptcB0WriteAccessErrorR { TptcB0WriteAccessErrorR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_read_access_error (& self) -> TpccBReadAccessErrorR { TpccBReadAccessErrorR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_b0_read_access_error (& self) -> TptcB0ReadAccessErrorR { TptcB0ReadAccessErrorR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
pub fn tptc_b1_read_access_error (& self) -> TptcB1ReadAccessErrorR { TptcB1ReadAccessErrorR :: new (((self . bits >> 26) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_errint (& mut self) -> TpccBErrintW < AppssTpccBErraggStatusRawSpec > { TpccBErrintW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_mpint (& mut self) -> TpccBMpintW < AppssTpccBErraggStatusRawSpec > { TpccBMpintW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_err (& mut self) -> TptcB0ErrW < AppssTpccBErraggStatusRawSpec > { TptcB0ErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_err (& mut self) -> TptcB1ErrW < AppssTpccBErraggStatusRawSpec > { TptcB1ErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_par_err (& mut self) -> TpccBParErrW < AppssTpccBErraggStatusRawSpec > { TpccBParErrW :: new (self , 4) } # [doc = "Bit 14 - 14:14\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_write_access_error (& mut self) -> TptcB1WriteAccessErrorW < AppssTpccBErraggStatusRawSpec > { TptcB1WriteAccessErrorW :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_write_access_error (& mut self) -> TpccBWriteAccessErrorW < AppssTpccBErraggStatusRawSpec > { TpccBWriteAccessErrorW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_write_access_error (& mut self) -> TptcB0WriteAccessErrorW < AppssTpccBErraggStatusRawSpec > { TptcB0WriteAccessErrorW :: new (self , 17) } # [doc = "Bit 24 - 24:24\\]
Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_read_access_error (& mut self) -> TpccBReadAccessErrorW < AppssTpccBErraggStatusRawSpec > { TpccBReadAccessErrorW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_read_access_error (& mut self) -> TptcB0ReadAccessErrorW < AppssTpccBErraggStatusRawSpec > { TptcB0ReadAccessErrorW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_read_access_error (& mut self) -> TptcB1ReadAccessErrorW < AppssTpccBErraggStatusRawSpec > { TptcB1ReadAccessErrorW :: new (self , 26) } } # [doc = "APPSS_TPCC_B_ERRAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_erragg_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_erragg_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccBErraggStatusRawSpec ; impl crate :: RegisterSpec for AppssTpccBErraggStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_b_erragg_status_raw::R`](R) reader structure"]
impl crate :: Readable for AppssTpccBErraggStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_b_erragg_status_raw::W`](W) writer structure"]
impl crate :: Writable for AppssTpccBErraggStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_B_ERRAGG_STATUS_RAW to value 0"]
impl crate :: Resettable for AppssTpccBErraggStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_B_INTAGG_MASK (rw) register accessor: APPSS_TPCC_B_INTAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_intagg_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_intagg_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_b_intagg_mask`]
module"]
# [doc (alias = "APPSS_TPCC_B_INTAGG_MASK")]
pub type AppssTpccBIntaggMask = crate :: Reg < appss_tpcc_b_intagg_mask :: AppssTpccBIntaggMaskSpec > ; # [doc = "APPSS_TPCC_B_INTAGG_MASK"]
pub mod appss_tpcc_b_intagg_mask { # [doc = "Register `APPSS_TPCC_B_INTAGG_MASK` reader"]
pub type R = crate :: R < AppssTpccBIntaggMaskSpec > ; # [doc = "Register `APPSS_TPCC_B_INTAGG_MASK` writer"]
pub type W = crate :: W < AppssTpccBIntaggMaskSpec > ; # [doc = "Field `tpcc_b_intg` reader - 0:0\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBIntgR = crate :: BitReader ; # [doc = "Field `tpcc_b_intg` writer - 0:0\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBIntgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int0` reader - 1:1\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt0R = crate :: BitReader ; # [doc = "Field `tpcc_b_int0` writer - 1:1\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int1` reader - 2:2\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt1R = crate :: BitReader ; # [doc = "Field `tpcc_b_int1` writer - 2:2\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int2` reader - 3:3\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt2R = crate :: BitReader ; # [doc = "Field `tpcc_b_int2` writer - 3:3\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int3` reader - 4:4\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt3R = crate :: BitReader ; # [doc = "Field `tpcc_b_int3` writer - 4:4\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int4` reader - 5:5\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt4R = crate :: BitReader ; # [doc = "Field `tpcc_b_int4` writer - 5:5\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int5` reader - 6:6\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt5R = crate :: BitReader ; # [doc = "Field `tpcc_b_int5` writer - 6:6\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int6` reader - 7:7\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt6R = crate :: BitReader ; # [doc = "Field `tpcc_b_int6` writer - 7:7\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int7` reader - 8:8\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt7R = crate :: BitReader ; # [doc = "Field `tpcc_b_int7` writer - 8:8\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TpccBInt7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0` reader - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcB0R = crate :: BitReader ; # [doc = "Field `tptc_b0` writer - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcB0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1` reader - 17:17\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcB1R = crate :: BitReader ; # [doc = "Field `tptc_b1` writer - 17:17\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type TptcB1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_intg (& self) -> TpccBIntgR { TpccBIntgR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int0 (& self) -> TpccBInt0R { TpccBInt0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int1 (& self) -> TpccBInt1R { TpccBInt1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int2 (& self) -> TpccBInt2R { TpccBInt2R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int3 (& self) -> TpccBInt3R { TpccBInt3R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int4 (& self) -> TpccBInt4R { TpccBInt4R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int5 (& self) -> TpccBInt5R { TpccBInt5R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int6 (& self) -> TpccBInt6R { TpccBInt6R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tpcc_b_int7 (& self) -> TpccBInt7R { TpccBInt7R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tptc_b0 (& self) -> TptcB0R { TptcB0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn tptc_b1 (& self) -> TptcB1R { TptcB1R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_intg (& mut self) -> TpccBIntgW < AppssTpccBIntaggMaskSpec > { TpccBIntgW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int0 (& mut self) -> TpccBInt0W < AppssTpccBIntaggMaskSpec > { TpccBInt0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int1 (& mut self) -> TpccBInt1W < AppssTpccBIntaggMaskSpec > { TpccBInt1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int2 (& mut self) -> TpccBInt2W < AppssTpccBIntaggMaskSpec > { TpccBInt2W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int3 (& mut self) -> TpccBInt3W < AppssTpccBIntaggMaskSpec > { TpccBInt3W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int4 (& mut self) -> TpccBInt4W < AppssTpccBIntaggMaskSpec > { TpccBInt4W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int5 (& mut self) -> TpccBInt5W < AppssTpccBIntaggMaskSpec > { TpccBInt5W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int6 (& mut self) -> TpccBInt6W < AppssTpccBIntaggMaskSpec > { TpccBInt6W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int7 (& mut self) -> TpccBInt7W < AppssTpccBIntaggMaskSpec > { TpccBInt7W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b0 (& mut self) -> TptcB0W < AppssTpccBIntaggMaskSpec > { TptcB0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn tptc_b1 (& mut self) -> TptcB1W < AppssTpccBIntaggMaskSpec > { TptcB1W :: new (self , 17) } } # [doc = "APPSS_TPCC_B_INTAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_intagg_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_intagg_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccBIntaggMaskSpec ; impl crate :: RegisterSpec for AppssTpccBIntaggMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_b_intagg_mask::R`](R) reader structure"]
impl crate :: Readable for AppssTpccBIntaggMaskSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_b_intagg_mask::W`](W) writer structure"]
impl crate :: Writable for AppssTpccBIntaggMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_B_INTAGG_MASK to value 0"]
impl crate :: Resettable for AppssTpccBIntaggMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_B_INTAGG_STATUS (rw) register accessor: APPSS_TPCC_B_INTAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_intagg_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_intagg_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_b_intagg_status`]
module"]
# [doc (alias = "APPSS_TPCC_B_INTAGG_STATUS")]
pub type AppssTpccBIntaggStatus = crate :: Reg < appss_tpcc_b_intagg_status :: AppssTpccBIntaggStatusSpec > ; # [doc = "APPSS_TPCC_B_INTAGG_STATUS"]
pub mod appss_tpcc_b_intagg_status { # [doc = "Register `APPSS_TPCC_B_INTAGG_STATUS` reader"]
pub type R = crate :: R < AppssTpccBIntaggStatusSpec > ; # [doc = "Register `APPSS_TPCC_B_INTAGG_STATUS` writer"]
pub type W = crate :: W < AppssTpccBIntaggStatusSpec > ; # [doc = "Field `tpcc_b_intg` reader - 0:0\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBIntgR = crate :: BitReader ; # [doc = "Field `tpcc_b_intg` writer - 0:0\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBIntgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int0` reader - 1:1\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt0R = crate :: BitReader ; # [doc = "Field `tpcc_b_int0` writer - 1:1\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int1` reader - 2:2\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt1R = crate :: BitReader ; # [doc = "Field `tpcc_b_int1` writer - 2:2\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int2` reader - 3:3\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt2R = crate :: BitReader ; # [doc = "Field `tpcc_b_int2` writer - 3:3\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int3` reader - 4:4\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt3R = crate :: BitReader ; # [doc = "Field `tpcc_b_int3` writer - 4:4\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int4` reader - 5:5\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt4R = crate :: BitReader ; # [doc = "Field `tpcc_b_int4` writer - 5:5\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int5` reader - 6:6\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt5R = crate :: BitReader ; # [doc = "Field `tpcc_b_int5` writer - 6:6\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int6` reader - 7:7\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt6R = crate :: BitReader ; # [doc = "Field `tpcc_b_int6` writer - 7:7\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int7` reader - 8:8\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt7R = crate :: BitReader ; # [doc = "Field `tpcc_b_int7` writer - 8:8\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TpccBInt7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0` reader - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcB0R = crate :: BitReader ; # [doc = "Field `tptc_b0` writer - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcB0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1` reader - 17:17\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcB1R = crate :: BitReader ; # [doc = "Field `tptc_b1` writer - 17:17\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type TptcB1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_intg (& self) -> TpccBIntgR { TpccBIntgR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int0 (& self) -> TpccBInt0R { TpccBInt0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int1 (& self) -> TpccBInt1R { TpccBInt1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int2 (& self) -> TpccBInt2R { TpccBInt2R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int3 (& self) -> TpccBInt3R { TpccBInt3R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int4 (& self) -> TpccBInt4R { TpccBInt4R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int5 (& self) -> TpccBInt5R { TpccBInt5R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int6 (& self) -> TpccBInt6R { TpccBInt6R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tpcc_b_int7 (& self) -> TpccBInt7R { TpccBInt7R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tptc_b0 (& self) -> TptcB0R { TptcB0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn tptc_b1 (& self) -> TptcB1R { TptcB1R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_intg (& mut self) -> TpccBIntgW < AppssTpccBIntaggStatusSpec > { TpccBIntgW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int0 (& mut self) -> TpccBInt0W < AppssTpccBIntaggStatusSpec > { TpccBInt0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int1 (& mut self) -> TpccBInt1W < AppssTpccBIntaggStatusSpec > { TpccBInt1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int2 (& mut self) -> TpccBInt2W < AppssTpccBIntaggStatusSpec > { TpccBInt2W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int3 (& mut self) -> TpccBInt3W < AppssTpccBIntaggStatusSpec > { TpccBInt3W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int4 (& mut self) -> TpccBInt4W < AppssTpccBIntaggStatusSpec > { TpccBInt4W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int5 (& mut self) -> TpccBInt5W < AppssTpccBIntaggStatusSpec > { TpccBInt5W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int6 (& mut self) -> TpccBInt6W < AppssTpccBIntaggStatusSpec > { TpccBInt6W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int7 (& mut self) -> TpccBInt7W < AppssTpccBIntaggStatusSpec > { TpccBInt7W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tptc_b0 (& mut self) -> TptcB0W < AppssTpccBIntaggStatusSpec > { TptcB0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn tptc_b1 (& mut self) -> TptcB1W < AppssTpccBIntaggStatusSpec > { TptcB1W :: new (self , 17) } } # [doc = "APPSS_TPCC_B_INTAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_intagg_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_intagg_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccBIntaggStatusSpec ; impl crate :: RegisterSpec for AppssTpccBIntaggStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_b_intagg_status::R`](R) reader structure"]
impl crate :: Readable for AppssTpccBIntaggStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_b_intagg_status::W`](W) writer structure"]
impl crate :: Writable for AppssTpccBIntaggStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_B_INTAGG_STATUS to value 0"]
impl crate :: Resettable for AppssTpccBIntaggStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPCC_B_INTAGG_STATUS_RAW (rw) register accessor: APPSS_TPCC_B_INTAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_intagg_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_intagg_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tpcc_b_intagg_status_raw`]
module"]
# [doc (alias = "APPSS_TPCC_B_INTAGG_STATUS_RAW")]
pub type AppssTpccBIntaggStatusRaw = crate :: Reg < appss_tpcc_b_intagg_status_raw :: AppssTpccBIntaggStatusRawSpec > ; # [doc = "APPSS_TPCC_B_INTAGG_STATUS_RAW"]
pub mod appss_tpcc_b_intagg_status_raw { # [doc = "Register `APPSS_TPCC_B_INTAGG_STATUS_RAW` reader"]
pub type R = crate :: R < AppssTpccBIntaggStatusRawSpec > ; # [doc = "Register `APPSS_TPCC_B_INTAGG_STATUS_RAW` writer"]
pub type W = crate :: W < AppssTpccBIntaggStatusRawSpec > ; # [doc = "Field `tpcc_b_intg` reader - 0:0\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBIntgR = crate :: BitReader ; # [doc = "Field `tpcc_b_intg` writer - 0:0\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBIntgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int0` reader - 1:1\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt0R = crate :: BitReader ; # [doc = "Field `tpcc_b_int0` writer - 1:1\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int1` reader - 2:2\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt1R = crate :: BitReader ; # [doc = "Field `tpcc_b_int1` writer - 2:2\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int2` reader - 3:3\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt2R = crate :: BitReader ; # [doc = "Field `tpcc_b_int2` writer - 3:3\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int3` reader - 4:4\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt3R = crate :: BitReader ; # [doc = "Field `tpcc_b_int3` writer - 4:4\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int4` reader - 5:5\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt4R = crate :: BitReader ; # [doc = "Field `tpcc_b_int4` writer - 5:5\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int5` reader - 6:6\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt5R = crate :: BitReader ; # [doc = "Field `tpcc_b_int5` writer - 6:6\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int6` reader - 7:7\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt6R = crate :: BitReader ; # [doc = "Field `tpcc_b_int6` writer - 7:7\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tpcc_b_int7` reader - 8:8\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt7R = crate :: BitReader ; # [doc = "Field `tpcc_b_int7` writer - 8:8\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
pub type TpccBInt7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0` reader - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcB0R = crate :: BitReader ; # [doc = "Field `tptc_b0` writer - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcB0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1` reader - 17:17\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcB1R = crate :: BitReader ; # [doc = "Field `tptc_b1` writer - 17:17\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
pub type TptcB1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_intg (& self) -> TpccBIntgR { TpccBIntgR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int0 (& self) -> TpccBInt0R { TpccBInt0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int1 (& self) -> TpccBInt1R { TpccBInt1R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int2 (& self) -> TpccBInt2R { TpccBInt2R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int3 (& self) -> TpccBInt3R { TpccBInt3R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int4 (& self) -> TpccBInt4R { TpccBInt4R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int5 (& self) -> TpccBInt5R { TpccBInt5R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int6 (& self) -> TpccBInt6R { TpccBInt6R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
pub fn tpcc_b_int7 (& self) -> TpccBInt7R { TpccBInt7R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
pub fn tptc_b0 (& self) -> TptcB0R { TptcB0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
pub fn tptc_b1 (& self) -> TptcB1R { TptcB1R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_intg (& mut self) -> TpccBIntgW < AppssTpccBIntaggStatusRawSpec > { TpccBIntgW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int0 (& mut self) -> TpccBInt0W < AppssTpccBIntaggStatusRawSpec > { TpccBInt0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int1 (& mut self) -> TpccBInt1W < AppssTpccBIntaggStatusRawSpec > { TpccBInt1W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int2 (& mut self) -> TpccBInt2W < AppssTpccBIntaggStatusRawSpec > { TpccBInt2W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int3 (& mut self) -> TpccBInt3W < AppssTpccBIntaggStatusRawSpec > { TpccBInt3W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int4 (& mut self) -> TpccBInt4W < AppssTpccBIntaggStatusRawSpec > { TpccBInt4W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int5 (& mut self) -> TpccBInt5W < AppssTpccBIntaggStatusRawSpec > { TpccBInt5W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int6 (& mut self) -> TpccBInt6W < AppssTpccBIntaggStatusRawSpec > { TpccBInt6W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tpcc_b_int7 (& mut self) -> TpccBInt7W < AppssTpccBIntaggStatusRawSpec > { TpccBInt7W :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b0 (& mut self) -> TptcB0W < AppssTpccBIntaggStatusRawSpec > { TptcB0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn tptc_b1 (& mut self) -> TptcB1W < AppssTpccBIntaggStatusRawSpec > { TptcB1W :: new (self , 17) } } # [doc = "APPSS_TPCC_B_INTAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tpcc_b_intagg_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tpcc_b_intagg_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTpccBIntaggStatusRawSpec ; impl crate :: RegisterSpec for AppssTpccBIntaggStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tpcc_b_intagg_status_raw::R`](R) reader structure"]
impl crate :: Readable for AppssTpccBIntaggStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tpcc_b_intagg_status_raw::W`](W) writer structure"]
impl crate :: Writable for AppssTpccBIntaggStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPCC_B_INTAGG_STATUS_RAW to value 0"]
impl crate :: Resettable for AppssTpccBIntaggStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MPU_ERRAGG_MASK (rw) register accessor: APPSS_MPU_ERRAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mpu_erragg_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mpu_erragg_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mpu_erragg_mask`]
module"]
# [doc (alias = "APPSS_MPU_ERRAGG_MASK")]
pub type AppssMpuErraggMask = crate :: Reg < appss_mpu_erragg_mask :: AppssMpuErraggMaskSpec > ; # [doc = "APPSS_MPU_ERRAGG_MASK"]
pub mod appss_mpu_erragg_mask { # [doc = "Register `APPSS_MPU_ERRAGG_MASK` reader"]
pub type R = crate :: R < AppssMpuErraggMaskSpec > ; # [doc = "Register `APPSS_MPU_ERRAGG_MASK` writer"]
pub type W = crate :: W < AppssMpuErraggMaskSpec > ; # [doc = "Field `appss_mpu` reader - 0:0\\]
Mask Interrupt from APSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppssMpuR = crate :: BitReader ; # [doc = "Field `appss_mpu` writer - 0:0\\]
Mask Interrupt from APSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type AppssMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fecss_mpu` reader - 16:16\\]
Mask Interrupt from FECSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FecssMpuR = crate :: BitReader ; # [doc = "Field `fecss_mpu` writer - 16:16\\]
Mask Interrupt from FECSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type FecssMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from APSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn appss_mpu (& self) -> AppssMpuR { AppssMpuR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from FECSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn fecss_mpu (& self) -> FecssMpuR { FecssMpuR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from APSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn appss_mpu (& mut self) -> AppssMpuW < AppssMpuErraggMaskSpec > { AppssMpuW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
Mask Interrupt from FECSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn fecss_mpu (& mut self) -> FecssMpuW < AppssMpuErraggMaskSpec > { FecssMpuW :: new (self , 16) } } # [doc = "APPSS_MPU_ERRAGG_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mpu_erragg_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mpu_erragg_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMpuErraggMaskSpec ; impl crate :: RegisterSpec for AppssMpuErraggMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mpu_erragg_mask::R`](R) reader structure"]
impl crate :: Readable for AppssMpuErraggMaskSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mpu_erragg_mask::W`](W) writer structure"]
impl crate :: Writable for AppssMpuErraggMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MPU_ERRAGG_MASK to value 0"]
impl crate :: Resettable for AppssMpuErraggMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MPU_ERRAGG_STATUS (rw) register accessor: APPSS_MPU_ERRAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mpu_erragg_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mpu_erragg_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mpu_erragg_status`]
module"]
# [doc (alias = "APPSS_MPU_ERRAGG_STATUS")]
pub type AppssMpuErraggStatus = crate :: Reg < appss_mpu_erragg_status :: AppssMpuErraggStatusSpec > ; # [doc = "APPSS_MPU_ERRAGG_STATUS"]
pub mod appss_mpu_erragg_status { # [doc = "Register `APPSS_MPU_ERRAGG_STATUS` reader"]
pub type R = crate :: R < AppssMpuErraggStatusSpec > ; # [doc = "Register `APPSS_MPU_ERRAGG_STATUS` writer"]
pub type W = crate :: W < AppssMpuErraggStatusSpec > ; # [doc = "Field `appss_mpu` reader - 0:0\\]
Status of Interrupt from APSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type AppssMpuR = crate :: BitReader ; # [doc = "Field `appss_mpu` writer - 0:0\\]
Status of Interrupt from APSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type AppssMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fecss_mpu` reader - 16:16\\]
Status of Interrupt from FECSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type FecssMpuR = crate :: BitReader ; # [doc = "Field `fecss_mpu` writer - 16:16\\]
Status of Interrupt from FECSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
pub type FecssMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from APSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn appss_mpu (& self) -> AppssMpuR { AppssMpuR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from FECSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn fecss_mpu (& self) -> FecssMpuR { FecssMpuR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from APSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn appss_mpu (& mut self) -> AppssMpuW < AppssMpuErraggStatusSpec > { AppssMpuW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
Status of Interrupt from FECSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn fecss_mpu (& mut self) -> FecssMpuW < AppssMpuErraggStatusSpec > { FecssMpuW :: new (self , 16) } } # [doc = "APPSS_MPU_ERRAGG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mpu_erragg_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mpu_erragg_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMpuErraggStatusSpec ; impl crate :: RegisterSpec for AppssMpuErraggStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mpu_erragg_status::R`](R) reader structure"]
impl crate :: Readable for AppssMpuErraggStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mpu_erragg_status::W`](W) writer structure"]
impl crate :: Writable for AppssMpuErraggStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MPU_ERRAGG_STATUS to value 0"]
impl crate :: Resettable for AppssMpuErraggStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MPU_ERRAGG_STATUS_RAW (rw) register accessor: APPSS_MPU_ERRAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mpu_erragg_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mpu_erragg_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mpu_erragg_status_raw`]
module"]
# [doc (alias = "APPSS_MPU_ERRAGG_STATUS_RAW")]
pub type AppssMpuErraggStatusRaw = crate :: Reg < appss_mpu_erragg_status_raw :: AppssMpuErraggStatusRawSpec > ; # [doc = "APPSS_MPU_ERRAGG_STATUS_RAW"]
pub mod appss_mpu_erragg_status_raw { # [doc = "Register `APPSS_MPU_ERRAGG_STATUS_RAW` reader"]
pub type R = crate :: R < AppssMpuErraggStatusRawSpec > ; # [doc = "Register `APPSS_MPU_ERRAGG_STATUS_RAW` writer"]
pub type W = crate :: W < AppssMpuErraggStatusRawSpec > ; # [doc = "Field `appss_mpu` reader - 0:0\\]
Raw Status of Interrupt from APSS MPU PROT ERR Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
pub type AppssMpuR = crate :: BitReader ; # [doc = "Field `appss_mpu` writer - 0:0\\]
Raw Status of Interrupt from APSS MPU PROT ERR Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
pub type AppssMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fecss_mpu` reader - 16:16\\]
Raw Status of FECSS MPU PROT ERR. Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
pub type FecssMpuR = crate :: BitReader ; # [doc = "Field `fecss_mpu` writer - 16:16\\]
Raw Status of FECSS MPU PROT ERR. Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
pub type FecssMpuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Raw Status of Interrupt from APSS MPU PROT ERR Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
# [inline (always)]
pub fn appss_mpu (& self) -> AppssMpuR { AppssMpuR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Raw Status of FECSS MPU PROT ERR. Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
# [inline (always)]
pub fn fecss_mpu (& self) -> FecssMpuR { FecssMpuR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Raw Status of Interrupt from APSS MPU PROT ERR Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn appss_mpu (& mut self) -> AppssMpuW < AppssMpuErraggStatusRawSpec > { AppssMpuW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
Raw Status of FECSS MPU PROT ERR. Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK"]
# [inline (always)]
# [must_use]
pub fn fecss_mpu (& mut self) -> FecssMpuW < AppssMpuErraggStatusRawSpec > { FecssMpuW :: new (self , 16) } } # [doc = "APPSS_MPU_ERRAGG_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mpu_erragg_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mpu_erragg_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMpuErraggStatusRawSpec ; impl crate :: RegisterSpec for AppssMpuErraggStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mpu_erragg_status_raw::R`](R) reader structure"]
impl crate :: Readable for AppssMpuErraggStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mpu_erragg_status_raw::W`](W) writer structure"]
impl crate :: Writable for AppssMpuErraggStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MPU_ERRAGG_STATUS_RAW to value 0"]
impl crate :: Resettable for AppssMpuErraggStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_QSPI_CONFIG (rw) register accessor: APPSS_QSPI_CONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_qspi_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_qspi_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_qspi_config`]
module"]
# [doc (alias = "APPSS_QSPI_CONFIG")]
pub type AppssQspiConfig = crate :: Reg < appss_qspi_config :: AppssQspiConfigSpec > ; # [doc = "APPSS_QSPI_CONFIG"]
pub mod appss_qspi_config { # [doc = "Register `APPSS_QSPI_CONFIG` reader"]
pub type R = crate :: R < AppssQspiConfigSpec > ; # [doc = "Register `APPSS_QSPI_CONFIG` writer"]
pub type W = crate :: W < AppssQspiConfigSpec > ; # [doc = "Field `ext_clk` reader - 0:0\\]
Reserved"]
pub type ExtClkR = crate :: BitReader ; # [doc = "Field `ext_clk` writer - 0:0\\]
Reserved"]
pub type ExtClkW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clk_loopback` reader - 8:8\\]
Reserved"]
pub type ClkLoopbackR = crate :: BitReader ; # [doc = "Field `clk_loopback` writer - 8:8\\]
Reserved"]
pub type ClkLoopbackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn ext_clk (& self) -> ExtClkR { ExtClkR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Reserved"]
# [inline (always)]
pub fn clk_loopback (& self) -> ClkLoopbackR { ClkLoopbackR :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn ext_clk (& mut self) -> ExtClkW < AppssQspiConfigSpec > { ExtClkW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn clk_loopback (& mut self) -> ClkLoopbackW < AppssQspiConfigSpec > { ClkLoopbackW :: new (self , 8) } } # [doc = "APPSS_QSPI_CONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_qspi_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_qspi_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssQspiConfigSpec ; impl crate :: RegisterSpec for AppssQspiConfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_qspi_config::R`](R) reader structure"]
impl crate :: Readable for AppssQspiConfigSpec { } # [doc = "`write(|w| ..)` method takes [`appss_qspi_config::W`](W) writer structure"]
impl crate :: Writable for AppssQspiConfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_QSPI_CONFIG to value 0"]
impl crate :: Resettable for AppssQspiConfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_CTI_TRIG_SEL (rw) register accessor: APPSS_CTI_TRIG_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cti_trig_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cti_trig_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_cti_trig_sel`]
module"]
# [doc (alias = "APPSS_CTI_TRIG_SEL")]
pub type AppssCtiTrigSel = crate :: Reg < appss_cti_trig_sel :: AppssCtiTrigSelSpec > ; # [doc = "APPSS_CTI_TRIG_SEL"]
pub mod appss_cti_trig_sel { # [doc = "Register `APPSS_CTI_TRIG_SEL` reader"]
pub type R = crate :: R < AppssCtiTrigSelSpec > ; # [doc = "Register `APPSS_CTI_TRIG_SEL` writer"]
pub type W = crate :: W < AppssCtiTrigSelSpec > ; # [doc = "Field `trig8_sel` reader - 7:0\\]
Used for selecting the trigger source for 8th trigger of CTI"]
pub type Trig8SelR = crate :: FieldReader ; # [doc = "Field `trig8_sel` writer - 7:0\\]
Used for selecting the trigger source for 8th trigger of CTI"]
pub type Trig8SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Used for selecting the trigger source for 8th trigger of CTI"]
# [inline (always)]
pub fn trig8_sel (& self) -> Trig8SelR { Trig8SelR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Used for selecting the trigger source for 8th trigger of CTI"]
# [inline (always)]
# [must_use]
pub fn trig8_sel (& mut self) -> Trig8SelW < AppssCtiTrigSelSpec > { Trig8SelW :: new (self , 0) } } # [doc = "APPSS_CTI_TRIG_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_cti_trig_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_cti_trig_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssCtiTrigSelSpec ; impl crate :: RegisterSpec for AppssCtiTrigSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_cti_trig_sel::R`](R) reader structure"]
impl crate :: Readable for AppssCtiTrigSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_cti_trig_sel::W`](W) writer structure"]
impl crate :: Writable for AppssCtiTrigSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_CTI_TRIG_SEL to value 0"]
impl crate :: Resettable for AppssCtiTrigSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_DBGSS_CTI_TRIG_SEL (rw) register accessor: APPSS_DBGSS_CTI_TRIG_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dbgss_cti_trig_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dbgss_cti_trig_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_dbgss_cti_trig_sel`]
module"]
# [doc (alias = "APPSS_DBGSS_CTI_TRIG_SEL")]
pub type AppssDbgssCtiTrigSel = crate :: Reg < appss_dbgss_cti_trig_sel :: AppssDbgssCtiTrigSelSpec > ; # [doc = "APPSS_DBGSS_CTI_TRIG_SEL"]
pub mod appss_dbgss_cti_trig_sel { # [doc = "Register `APPSS_DBGSS_CTI_TRIG_SEL` reader"]
pub type R = crate :: R < AppssDbgssCtiTrigSelSpec > ; # [doc = "Register `APPSS_DBGSS_CTI_TRIG_SEL` writer"]
pub type W = crate :: W < AppssDbgssCtiTrigSelSpec > ; # [doc = "Field `trig1` reader - 7:0\\]
Reserved"]
pub type Trig1R = crate :: FieldReader ; # [doc = "Field `trig1` writer - 7:0\\]
Reserved"]
pub type Trig1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `trig2` reader - 15:8\\]
Reserved"]
pub type Trig2R = crate :: FieldReader ; # [doc = "Field `trig2` writer - 15:8\\]
Reserved"]
pub type Trig2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `trig3` reader - 23:16\\]
Reserved"]
pub type Trig3R = crate :: FieldReader ; # [doc = "Field `trig3` writer - 23:16\\]
Reserved"]
pub type Trig3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
pub fn trig1 (& self) -> Trig1R { Trig1R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
pub fn trig2 (& self) -> Trig2R { Trig2R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Reserved"]
# [inline (always)]
pub fn trig3 (& self) -> Trig3R { Trig3R :: new (((self . bits >> 16) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn trig1 (& mut self) -> Trig1W < AppssDbgssCtiTrigSelSpec > { Trig1W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn trig2 (& mut self) -> Trig2W < AppssDbgssCtiTrigSelSpec > { Trig2W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn trig3 (& mut self) -> Trig3W < AppssDbgssCtiTrigSelSpec > { Trig3W :: new (self , 16) } } # [doc = "APPSS_DBGSS_CTI_TRIG_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dbgss_cti_trig_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dbgss_cti_trig_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssDbgssCtiTrigSelSpec ; impl crate :: RegisterSpec for AppssDbgssCtiTrigSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_dbgss_cti_trig_sel::R`](R) reader structure"]
impl crate :: Readable for AppssDbgssCtiTrigSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_dbgss_cti_trig_sel::W`](W) writer structure"]
impl crate :: Writable for AppssDbgssCtiTrigSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_DBGSS_CTI_TRIG_SEL to value 0"]
impl crate :: Resettable for AppssDbgssCtiTrigSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG0 (rw) register accessor: APPSS_BOOT_INFO_REG0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg0`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG0")]
pub type AppssBootInfoReg0 = crate :: Reg < appss_boot_info_reg0 :: AppssBootInfoReg0Spec > ; # [doc = "APPSS_BOOT_INFO_REG0"]
pub mod appss_boot_info_reg0 { # [doc = "Register `APPSS_BOOT_INFO_REG0` reader"]
pub type R = crate :: R < AppssBootInfoReg0Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG0` writer"]
pub type W = crate :: W < AppssBootInfoReg0Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg0Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG0\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg0Spec ; impl crate :: RegisterSpec for AppssBootInfoReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg0::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg0Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg0::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG0 to value 0"]
impl crate :: Resettable for AppssBootInfoReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG1 (rw) register accessor: APPSS_BOOT_INFO_REG1\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg1`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG1")]
pub type AppssBootInfoReg1 = crate :: Reg < appss_boot_info_reg1 :: AppssBootInfoReg1Spec > ; # [doc = "APPSS_BOOT_INFO_REG1"]
pub mod appss_boot_info_reg1 { # [doc = "Register `APPSS_BOOT_INFO_REG1` reader"]
pub type R = crate :: R < AppssBootInfoReg1Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG1` writer"]
pub type W = crate :: W < AppssBootInfoReg1Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg1Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG1\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg1Spec ; impl crate :: RegisterSpec for AppssBootInfoReg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg1::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg1Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg1::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG1 to value 0"]
impl crate :: Resettable for AppssBootInfoReg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG2 (rw) register accessor: APPSS_BOOT_INFO_REG2\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg2`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG2")]
pub type AppssBootInfoReg2 = crate :: Reg < appss_boot_info_reg2 :: AppssBootInfoReg2Spec > ; # [doc = "APPSS_BOOT_INFO_REG2"]
pub mod appss_boot_info_reg2 { # [doc = "Register `APPSS_BOOT_INFO_REG2` reader"]
pub type R = crate :: R < AppssBootInfoReg2Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG2` writer"]
pub type W = crate :: W < AppssBootInfoReg2Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg2Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG2\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg2Spec ; impl crate :: RegisterSpec for AppssBootInfoReg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg2::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg2Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg2::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG2 to value 0"]
impl crate :: Resettable for AppssBootInfoReg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG3 (rw) register accessor: APPSS_BOOT_INFO_REG3\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg3`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG3")]
pub type AppssBootInfoReg3 = crate :: Reg < appss_boot_info_reg3 :: AppssBootInfoReg3Spec > ; # [doc = "APPSS_BOOT_INFO_REG3"]
pub mod appss_boot_info_reg3 { # [doc = "Register `APPSS_BOOT_INFO_REG3` reader"]
pub type R = crate :: R < AppssBootInfoReg3Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG3` writer"]
pub type W = crate :: W < AppssBootInfoReg3Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg3Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG3\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg3Spec ; impl crate :: RegisterSpec for AppssBootInfoReg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg3::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg3Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg3::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG3 to value 0"]
impl crate :: Resettable for AppssBootInfoReg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG4 (rw) register accessor: APPSS_BOOT_INFO_REG4\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg4`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG4")]
pub type AppssBootInfoReg4 = crate :: Reg < appss_boot_info_reg4 :: AppssBootInfoReg4Spec > ; # [doc = "APPSS_BOOT_INFO_REG4"]
pub mod appss_boot_info_reg4 { # [doc = "Register `APPSS_BOOT_INFO_REG4` reader"]
pub type R = crate :: R < AppssBootInfoReg4Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG4` writer"]
pub type W = crate :: W < AppssBootInfoReg4Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg4Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG4\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg4Spec ; impl crate :: RegisterSpec for AppssBootInfoReg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg4::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg4Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg4::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG4 to value 0"]
impl crate :: Resettable for AppssBootInfoReg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG5 (rw) register accessor: APPSS_BOOT_INFO_REG5\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg5`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG5")]
pub type AppssBootInfoReg5 = crate :: Reg < appss_boot_info_reg5 :: AppssBootInfoReg5Spec > ; # [doc = "APPSS_BOOT_INFO_REG5"]
pub mod appss_boot_info_reg5 { # [doc = "Register `APPSS_BOOT_INFO_REG5` reader"]
pub type R = crate :: R < AppssBootInfoReg5Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG5` writer"]
pub type W = crate :: W < AppssBootInfoReg5Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg5Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG5\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg5Spec ; impl crate :: RegisterSpec for AppssBootInfoReg5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg5::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg5Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg5::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG5 to value 0"]
impl crate :: Resettable for AppssBootInfoReg5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG6 (rw) register accessor: APPSS_BOOT_INFO_REG6\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg6`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG6")]
pub type AppssBootInfoReg6 = crate :: Reg < appss_boot_info_reg6 :: AppssBootInfoReg6Spec > ; # [doc = "APPSS_BOOT_INFO_REG6"]
pub mod appss_boot_info_reg6 { # [doc = "Register `APPSS_BOOT_INFO_REG6` reader"]
pub type R = crate :: R < AppssBootInfoReg6Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG6` writer"]
pub type W = crate :: W < AppssBootInfoReg6Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg6Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG6\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg6Spec ; impl crate :: RegisterSpec for AppssBootInfoReg6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg6::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg6Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg6::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG6 to value 0"]
impl crate :: Resettable for AppssBootInfoReg6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_BOOT_INFO_REG7 (rw) register accessor: APPSS_BOOT_INFO_REG7\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_boot_info_reg7`]
module"]
# [doc (alias = "APPSS_BOOT_INFO_REG7")]
pub type AppssBootInfoReg7 = crate :: Reg < appss_boot_info_reg7 :: AppssBootInfoReg7Spec > ; # [doc = "APPSS_BOOT_INFO_REG7"]
pub mod appss_boot_info_reg7 { # [doc = "Register `APPSS_BOOT_INFO_REG7` reader"]
pub type R = crate :: R < AppssBootInfoReg7Spec > ; # [doc = "Register `APPSS_BOOT_INFO_REG7` writer"]
pub type W = crate :: W < AppssBootInfoReg7Spec > ; # [doc = "Field `config` reader - 31:0\\]
Reserved Register for Software use"]
pub type ConfigR = crate :: FieldReader < u32 > ; # [doc = "Field `config` writer - 31:0\\]
Reserved Register for Software use"]
pub type ConfigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
pub fn config (& self) -> ConfigR { ConfigR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved Register for Software use"]
# [inline (always)]
# [must_use]
pub fn config (& mut self) -> ConfigW < AppssBootInfoReg7Spec > { ConfigW :: new (self , 0) } } # [doc = "APPSS_BOOT_INFO_REG7\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_boot_info_reg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_boot_info_reg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssBootInfoReg7Spec ; impl crate :: RegisterSpec for AppssBootInfoReg7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_boot_info_reg7::R`](R) reader structure"]
impl crate :: Readable for AppssBootInfoReg7Spec { } # [doc = "`write(|w| ..)` method takes [`appss_boot_info_reg7::W`](W) writer structure"]
impl crate :: Writable for AppssBootInfoReg7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_BOOT_INFO_REG7 to value 0"]
impl crate :: Resettable for AppssBootInfoReg7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPTC_ECCAGGR_CLK_CNTRL (rw) register accessor: APPSS_TPTC_ECCAGGR_CLK_CNTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tptc_eccaggr_clk_cntrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tptc_eccaggr_clk_cntrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tptc_eccaggr_clk_cntrl`]
module"]
# [doc (alias = "APPSS_TPTC_ECCAGGR_CLK_CNTRL")]
pub type AppssTptcEccaggrClkCntrl = crate :: Reg < appss_tptc_eccaggr_clk_cntrl :: AppssTptcEccaggrClkCntrlSpec > ; # [doc = "APPSS_TPTC_ECCAGGR_CLK_CNTRL"]
pub mod appss_tptc_eccaggr_clk_cntrl { # [doc = "Register `APPSS_TPTC_ECCAGGR_CLK_CNTRL` reader"]
pub type R = crate :: R < AppssTptcEccaggrClkCntrlSpec > ; # [doc = "Register `APPSS_TPTC_ECCAGGR_CLK_CNTRL` writer"]
pub type W = crate :: W < AppssTptcEccaggrClkCntrlSpec > ; # [doc = "Field `tptc_A0` reader - 0:0\\]
Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)"]
pub type TptcA0R = crate :: BitReader ; # [doc = "Field `tptc_A0` writer - 0:0\\]
Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)"]
pub type TptcA0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_A1` reader - 1:1\\]
Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)"]
pub type TptcA1R = crate :: BitReader ; # [doc = "Field `tptc_A1` writer - 1:1\\]
Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)"]
pub type TptcA1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_B0` reader - 2:2\\]
Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)"]
pub type TptcB0R = crate :: BitReader ; # [doc = "Field `tptc_B0` writer - 2:2\\]
Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)"]
pub type TptcB0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)"]
# [inline (always)]
pub fn tptc_a0 (& self) -> TptcA0R { TptcA0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)"]
# [inline (always)]
pub fn tptc_a1 (& self) -> TptcA1R { TptcA1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)"]
# [inline (always)]
pub fn tptc_b0 (& self) -> TptcB0R { TptcB0R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)"]
# [inline (always)]
# [must_use]
pub fn tptc_a0 (& mut self) -> TptcA0W < AppssTptcEccaggrClkCntrlSpec > { TptcA0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)"]
# [inline (always)]
# [must_use]
pub fn tptc_a1 (& mut self) -> TptcA1W < AppssTptcEccaggrClkCntrlSpec > { TptcA1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)"]
# [inline (always)]
# [must_use]
pub fn tptc_b0 (& mut self) -> TptcB0W < AppssTptcEccaggrClkCntrlSpec > { TptcB0W :: new (self , 2) } } # [doc = "APPSS_TPTC_ECCAGGR_CLK_CNTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tptc_eccaggr_clk_cntrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tptc_eccaggr_clk_cntrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTptcEccaggrClkCntrlSpec ; impl crate :: RegisterSpec for AppssTptcEccaggrClkCntrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tptc_eccaggr_clk_cntrl::R`](R) reader structure"]
impl crate :: Readable for AppssTptcEccaggrClkCntrlSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tptc_eccaggr_clk_cntrl::W`](W) writer structure"]
impl crate :: Writable for AppssTptcEccaggrClkCntrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPTC_ECCAGGR_CLK_CNTRL to value 0"]
impl crate :: Resettable for AppssTptcEccaggrClkCntrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPTC_BOUNDARY_CFG (rw) register accessor: APPSS_TPTC_BOUNDARY_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tptc_boundary_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tptc_boundary_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tptc_boundary_cfg`]
module"]
# [doc (alias = "APPSS_TPTC_BOUNDARY_CFG")]
pub type AppssTptcBoundaryCfg = crate :: Reg < appss_tptc_boundary_cfg :: AppssTptcBoundaryCfgSpec > ; # [doc = "APPSS_TPTC_BOUNDARY_CFG"]
pub mod appss_tptc_boundary_cfg { # [doc = "Register `APPSS_TPTC_BOUNDARY_CFG` reader"]
pub type R = crate :: R < AppssTptcBoundaryCfgSpec > ; # [doc = "Register `APPSS_TPTC_BOUNDARY_CFG` writer"]
pub type W = crate :: W < AppssTptcBoundaryCfgSpec > ; # [doc = "Field `tptc_a0_size` reader - 5:0\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcA0SizeR = crate :: FieldReader ; # [doc = "Field `tptc_a0_size` writer - 5:0\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcA0SizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `tptc_a1_size` reader - 13:8\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcA1SizeR = crate :: FieldReader ; # [doc = "Field `tptc_a1_size` writer - 13:8\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcA1SizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `tptc_b0_size` reader - 21:16\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcB0SizeR = crate :: FieldReader ; # [doc = "Field `tptc_b0_size` writer - 21:16\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcB0SizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `tptc_b1_size` reader - 29:24\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcB1SizeR = crate :: FieldReader ; # [doc = "Field `tptc_b1_size` writer - 29:24\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
pub type TptcB1SizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
pub fn tptc_a0_size (& self) -> TptcA0SizeR { TptcA0SizeR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 8:13 - 13:8\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
pub fn tptc_a1_size (& self) -> TptcA1SizeR { TptcA1SizeR :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 16:21 - 21:16\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
pub fn tptc_b0_size (& self) -> TptcB0SizeR { TptcB0SizeR :: new (((self . bits >> 16) & 0x3f) as u8) } # [doc = "Bits 24:29 - 29:24\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
pub fn tptc_b1_size (& self) -> TptcB1SizeR { TptcB1SizeR :: new (((self . bits >> 24) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_size (& mut self) -> TptcA0SizeW < AppssTptcBoundaryCfgSpec > { TptcA0SizeW :: new (self , 0) } # [doc = "Bits 8:13 - 13:8\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_size (& mut self) -> TptcA1SizeW < AppssTptcBoundaryCfgSpec > { TptcA1SizeW :: new (self , 8) } # [doc = "Bits 16:21 - 21:16\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_size (& mut self) -> TptcB0SizeW < AppssTptcBoundaryCfgSpec > { TptcB0SizeW :: new (self , 16) } # [doc = "Bits 24:29 - 29:24\\]
6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_size (& mut self) -> TptcB1SizeW < AppssTptcBoundaryCfgSpec > { TptcB1SizeW :: new (self , 24) } } # [doc = "APPSS_TPTC_BOUNDARY_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tptc_boundary_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tptc_boundary_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTptcBoundaryCfgSpec ; impl crate :: RegisterSpec for AppssTptcBoundaryCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tptc_boundary_cfg::R`](R) reader structure"]
impl crate :: Readable for AppssTptcBoundaryCfgSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tptc_boundary_cfg::W`](W) writer structure"]
impl crate :: Writable for AppssTptcBoundaryCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPTC_BOUNDARY_CFG to value 0"]
impl crate :: Resettable for AppssTptcBoundaryCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_TPTC_XID_REORDER_CFG (rw) register accessor: APPSS_TPTC_XID_REORDER_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tptc_xid_reorder_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tptc_xid_reorder_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_tptc_xid_reorder_cfg`]
module"]
# [doc (alias = "APPSS_TPTC_XID_REORDER_CFG")]
pub type AppssTptcXidReorderCfg = crate :: Reg < appss_tptc_xid_reorder_cfg :: AppssTptcXidReorderCfgSpec > ; # [doc = "APPSS_TPTC_XID_REORDER_CFG"]
pub mod appss_tptc_xid_reorder_cfg { # [doc = "Register `APPSS_TPTC_XID_REORDER_CFG` reader"]
pub type R = crate :: R < AppssTptcXidReorderCfgSpec > ; # [doc = "Register `APPSS_TPTC_XID_REORDER_CFG` writer"]
pub type W = crate :: W < AppssTptcXidReorderCfgSpec > ; # [doc = "Field `tptc_a0_disable` reader - 0:0\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A0"]
pub type TptcA0DisableR = crate :: BitReader ; # [doc = "Field `tptc_a0_disable` writer - 0:0\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A0"]
pub type TptcA0DisableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_a1_disable` reader - 8:8\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A1"]
pub type TptcA1DisableR = crate :: BitReader ; # [doc = "Field `tptc_a1_disable` writer - 8:8\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A1"]
pub type TptcA1DisableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b0_disable` reader - 16:16\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B0"]
pub type TptcB0DisableR = crate :: BitReader ; # [doc = "Field `tptc_b0_disable` writer - 16:16\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B0"]
pub type TptcB0DisableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc_b1_disable` reader - 24:24\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B1"]
pub type TptcB1DisableR = crate :: BitReader ; # [doc = "Field `tptc_b1_disable` writer - 24:24\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B1"]
pub type TptcB1DisableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A0"]
# [inline (always)]
pub fn tptc_a0_disable (& self) -> TptcA0DisableR { TptcA0DisableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A1"]
# [inline (always)]
pub fn tptc_a1_disable (& self) -> TptcA1DisableR { TptcA1DisableR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B0"]
# [inline (always)]
pub fn tptc_b0_disable (& self) -> TptcB0DisableR { TptcB0DisableR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B1"]
# [inline (always)]
pub fn tptc_b1_disable (& self) -> TptcB1DisableR { TptcB1DisableR :: new (((self . bits >> 24) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A0"]
# [inline (always)]
# [must_use]
pub fn tptc_a0_disable (& mut self) -> TptcA0DisableW < AppssTptcXidReorderCfgSpec > { TptcA0DisableW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A1"]
# [inline (always)]
# [must_use]
pub fn tptc_a1_disable (& mut self) -> TptcA1DisableW < AppssTptcXidReorderCfgSpec > { TptcA1DisableW :: new (self , 8) } # [doc = "Bit 16 - 16:16\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B0"]
# [inline (always)]
# [must_use]
pub fn tptc_b0_disable (& mut self) -> TptcB0DisableW < AppssTptcXidReorderCfgSpec > { TptcB0DisableW :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B1"]
# [inline (always)]
# [must_use]
pub fn tptc_b1_disable (& mut self) -> TptcB1DisableW < AppssTptcXidReorderCfgSpec > { TptcB1DisableW :: new (self , 24) } } # [doc = "APPSS_TPTC_XID_REORDER_CFG\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_tptc_xid_reorder_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_tptc_xid_reorder_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssTptcXidReorderCfgSpec ; impl crate :: RegisterSpec for AppssTptcXidReorderCfgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_tptc_xid_reorder_cfg::R`](R) reader structure"]
impl crate :: Readable for AppssTptcXidReorderCfgSpec { } # [doc = "`write(|w| ..)` method takes [`appss_tptc_xid_reorder_cfg::W`](W) writer structure"]
impl crate :: Writable for AppssTptcXidReorderCfgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_TPTC_XID_REORDER_CFG to value 0"]
impl crate :: Resettable for AppssTptcXidReorderCfgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_Sync_FE_CTRL (rw) register accessor: HW_Sync_FE_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_sync_fe_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_sync_fe_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_sync_fe_ctrl`]
module"]
# [doc (alias = "HW_Sync_FE_CTRL")]
pub type HwSyncFeCtrl = crate :: Reg < hw_sync_fe_ctrl :: HwSyncFeCtrlSpec > ; # [doc = "HW_Sync_FE_CTRL"]
pub mod hw_sync_fe_ctrl { # [doc = "Register `HW_Sync_FE_CTRL` reader"]
pub type R = crate :: R < HwSyncFeCtrlSpec > ; # [doc = "Register `HW_Sync_FE_CTRL` writer"]
pub type W = crate :: W < HwSyncFeCtrlSpec > ; # [doc = "Field `fe1_sel` reader - 0:0\\]
RESERVED"]
pub type Fe1SelR = crate :: BitReader ; # [doc = "Field `fe1_sel` writer - 0:0\\]
RESERVED"]
pub type Fe1SelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fe2_sel` reader - 8:8\\]
RESERVED"]
pub type Fe2SelR = crate :: BitReader ; # [doc = "Field `fe2_sel` writer - 8:8\\]
RESERVED"]
pub type Fe2SelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
pub fn fe1_sel (& self) -> Fe1SelR { Fe1SelR :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
pub fn fe2_sel (& self) -> Fe2SelR { Fe2SelR :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn fe1_sel (& mut self) -> Fe1SelW < HwSyncFeCtrlSpec > { Fe1SelW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn fe2_sel (& mut self) -> Fe2SelW < HwSyncFeCtrlSpec > { Fe2SelW :: new (self , 8) } } # [doc = "HW_Sync_FE_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_sync_fe_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_sync_fe_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSyncFeCtrlSpec ; impl crate :: RegisterSpec for HwSyncFeCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_sync_fe_ctrl::R`](R) reader structure"]
impl crate :: Readable for HwSyncFeCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`hw_sync_fe_ctrl::W`](W) writer structure"]
impl crate :: Writable for HwSyncFeCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_Sync_FE_CTRL to value 0"]
impl crate :: Resettable for HwSyncFeCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_REG1 (rw) register accessor: HW_SPARE_REG1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_reg1`]
module"]
# [doc (alias = "HW_SPARE_REG1")]
pub type HwSpareReg1 = crate :: Reg < hw_spare_reg1 :: HwSpareReg1Spec > ; # [doc = "HW_SPARE_REG1"]
pub mod hw_spare_reg1 { # [doc = "Register `HW_SPARE_REG1` reader"]
pub type R = crate :: R < HwSpareReg1Spec > ; # [doc = "Register `HW_SPARE_REG1` writer"]
pub type W = crate :: W < HwSpareReg1Spec > ; # [doc = "Field `NU` reader - 31:0\\]
Resereved for R&amp;D"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:0\\]
Resereved for R&amp;D"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Resereved for R&amp;D"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Resereved for R&amp;D"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwSpareReg1Spec > { NuW :: new (self , 0) } } # [doc = "HW_SPARE_REG1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareReg1Spec ; impl crate :: RegisterSpec for HwSpareReg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_reg1::R`](R) reader structure"]
impl crate :: Readable for HwSpareReg1Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_reg1::W`](W) writer structure"]
impl crate :: Writable for HwSpareReg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_REG1 to value 0"]
impl crate :: Resettable for HwSpareReg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_REG2 (rw) register accessor: HW_SPARE_REG2\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_reg2`]
module"]
# [doc (alias = "HW_SPARE_REG2")]
pub type HwSpareReg2 = crate :: Reg < hw_spare_reg2 :: HwSpareReg2Spec > ; # [doc = "HW_SPARE_REG2"]
pub mod hw_spare_reg2 { # [doc = "Register `HW_SPARE_REG2` reader"]
pub type R = crate :: R < HwSpareReg2Spec > ; # [doc = "Register `HW_SPARE_REG2` writer"]
pub type W = crate :: W < HwSpareReg2Spec > ; # [doc = "Field `NU` reader - 31:0\\]
Resereved for R&amp;D"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:0\\]
Resereved for R&amp;D"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Resereved for R&amp;D"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Resereved for R&amp;D"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwSpareReg2Spec > { NuW :: new (self , 0) } } # [doc = "HW_SPARE_REG2\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareReg2Spec ; impl crate :: RegisterSpec for HwSpareReg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_reg2::R`](R) reader structure"]
impl crate :: Readable for HwSpareReg2Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_reg2::W`](W) writer structure"]
impl crate :: Writable for HwSpareReg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_REG2 to value 0"]
impl crate :: Resettable for HwSpareReg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_REG3 (rw) register accessor: HW_SPARE_REG3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_reg3`]
module"]
# [doc (alias = "HW_SPARE_REG3")]
pub type HwSpareReg3 = crate :: Reg < hw_spare_reg3 :: HwSpareReg3Spec > ; # [doc = "HW_SPARE_REG3"]
pub mod hw_spare_reg3 { # [doc = "Register `HW_SPARE_REG3` reader"]
pub type R = crate :: R < HwSpareReg3Spec > ; # [doc = "Register `HW_SPARE_REG3` writer"]
pub type W = crate :: W < HwSpareReg3Spec > ; # [doc = "Field `NU` reader - 31:0\\]
Resereved for R&amp;D"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:0\\]
Resereved for R&amp;D"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Resereved for R&amp;D"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Resereved for R&amp;D"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < HwSpareReg3Spec > { NuW :: new (self , 0) } } # [doc = "HW_SPARE_REG3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareReg3Spec ; impl crate :: RegisterSpec for HwSpareReg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_reg3::R`](R) reader structure"]
impl crate :: Readable for HwSpareReg3Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_reg3::W`](W) writer structure"]
impl crate :: Writable for HwSpareReg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_REG3 to value 0"]
impl crate :: Resettable for HwSpareReg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "NERROR_MASK (rw) register accessor: NERROR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`nerror_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nerror_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nerror_mask`]
module"]
# [doc (alias = "NERROR_MASK")]
pub type NerrorMask = crate :: Reg < nerror_mask :: NerrorMaskSpec > ; # [doc = "NERROR_MASK"]
pub mod nerror_mask { # [doc = "Register `NERROR_MASK` reader"]
pub type R = crate :: R < NerrorMaskSpec > ; # [doc = "Register `NERROR_MASK` writer"]
pub type W = crate :: W < NerrorMaskSpec > ; # [doc = "Field `mask` reader - 0:0\\]
writing 1'b1 will mask the Nerror propagation to pad Writing 1'b0 will unmask the Nerror propagation to pad"]
pub type MaskR = crate :: BitReader ; # [doc = "Field `mask` writer - 0:0\\]
writing 1'b1 will mask the Nerror propagation to pad Writing 1'b0 will unmask the Nerror propagation to pad"]
pub type MaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
writing 1'b1 will mask the Nerror propagation to pad Writing 1'b0 will unmask the Nerror propagation to pad"]
# [inline (always)]
pub fn mask (& self) -> MaskR { MaskR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
writing 1'b1 will mask the Nerror propagation to pad Writing 1'b0 will unmask the Nerror propagation to pad"]
# [inline (always)]
# [must_use]
pub fn mask (& mut self) -> MaskW < NerrorMaskSpec > { MaskW :: new (self , 0) } } # [doc = "NERROR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`nerror_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nerror_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NerrorMaskSpec ; impl crate :: RegisterSpec for NerrorMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`nerror_mask::R`](R) reader structure"]
impl crate :: Readable for NerrorMaskSpec { } # [doc = "`write(|w| ..)` method takes [`nerror_mask::W`](W) writer structure"]
impl crate :: Writable for NerrorMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets NERROR_MASK to value 0"]
impl crate :: Resettable for NerrorMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW0 (rw) register accessor: HW_SPARE_RW0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw0`]
module"]
# [doc (alias = "HW_SPARE_RW0")]
pub type HwSpareRw0 = crate :: Reg < hw_spare_rw0 :: HwSpareRw0Spec > ; # [doc = "HW_SPARE_RW0"]
pub mod hw_spare_rw0 { # [doc = "Register `HW_SPARE_RW0` reader"]
pub type R = crate :: R < HwSpareRw0Spec > ; # [doc = "Register `HW_SPARE_RW0` writer"]
pub type W = crate :: W < HwSpareRw0Spec > ; # [doc = "Field `hw_spare_rw0` reader - 31:0\\]
Bit 0: Writing 1'b1 will mask the hwa local ram agg serr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg serr propagation to ESM Bit 1 : Writing 1'b1 will mask the hwa local ram agg uerr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg uerr propagation to ESM Bit 2 to 31 Reserved"]
pub type HwSpareRw0R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw0` writer - 31:0\\]
Bit 0: Writing 1'b1 will mask the hwa local ram agg serr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg serr propagation to ESM Bit 1 : Writing 1'b1 will mask the hwa local ram agg uerr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg uerr propagation to ESM Bit 2 to 31 Reserved"]
pub type HwSpareRw0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Bit 0: Writing 1'b1 will mask the hwa local ram agg serr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg serr propagation to ESM Bit 1 : Writing 1'b1 will mask the hwa local ram agg uerr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg uerr propagation to ESM Bit 2 to 31 Reserved"]
# [inline (always)]
pub fn hw_spare_rw0 (& self) -> HwSpareRw0R { HwSpareRw0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Bit 0: Writing 1'b1 will mask the hwa local ram agg serr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg serr propagation to ESM Bit 1 : Writing 1'b1 will mask the hwa local ram agg uerr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg uerr propagation to ESM Bit 2 to 31 Reserved"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw0 (& mut self) -> HwSpareRw0W < HwSpareRw0Spec > { HwSpareRw0W :: new (self , 0) } } # [doc = "HW_SPARE_RW0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw0Spec ; impl crate :: RegisterSpec for HwSpareRw0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw0::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw0Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw0::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW0 to value 0"]
impl crate :: Resettable for HwSpareRw0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW1 (rw) register accessor: HW_SPARE_RW1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw1`]
module"]
# [doc (alias = "HW_SPARE_RW1")]
pub type HwSpareRw1 = crate :: Reg < hw_spare_rw1 :: HwSpareRw1Spec > ; # [doc = "HW_SPARE_RW1"]
pub mod hw_spare_rw1 { # [doc = "Register `HW_SPARE_RW1` reader"]
pub type R = crate :: R < HwSpareRw1Spec > ; # [doc = "Register `HW_SPARE_RW1` writer"]
pub type W = crate :: W < HwSpareRw1Spec > ; # [doc = "Field `hw_spare_rw1` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw1R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw1` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw1 (& self) -> HwSpareRw1R { HwSpareRw1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw1 (& mut self) -> HwSpareRw1W < HwSpareRw1Spec > { HwSpareRw1W :: new (self , 0) } } # [doc = "HW_SPARE_RW1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw1Spec ; impl crate :: RegisterSpec for HwSpareRw1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw1::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw1Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw1::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW1 to value 0"]
impl crate :: Resettable for HwSpareRw1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW2 (rw) register accessor: HW_SPARE_RW2\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw2`]
module"]
# [doc (alias = "HW_SPARE_RW2")]
pub type HwSpareRw2 = crate :: Reg < hw_spare_rw2 :: HwSpareRw2Spec > ; # [doc = "HW_SPARE_RW2"]
pub mod hw_spare_rw2 { # [doc = "Register `HW_SPARE_RW2` reader"]
pub type R = crate :: R < HwSpareRw2Spec > ; # [doc = "Register `HW_SPARE_RW2` writer"]
pub type W = crate :: W < HwSpareRw2Spec > ; # [doc = "Field `hw_spare_rw2` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw2R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw2` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw2 (& self) -> HwSpareRw2R { HwSpareRw2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw2 (& mut self) -> HwSpareRw2W < HwSpareRw2Spec > { HwSpareRw2W :: new (self , 0) } } # [doc = "HW_SPARE_RW2\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw2Spec ; impl crate :: RegisterSpec for HwSpareRw2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw2::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw2Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw2::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW2 to value 0"]
impl crate :: Resettable for HwSpareRw2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW3 (rw) register accessor: HW_SPARE_RW3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw3`]
module"]
# [doc (alias = "HW_SPARE_RW3")]
pub type HwSpareRw3 = crate :: Reg < hw_spare_rw3 :: HwSpareRw3Spec > ; # [doc = "HW_SPARE_RW3"]
pub mod hw_spare_rw3 { # [doc = "Register `HW_SPARE_RW3` reader"]
pub type R = crate :: R < HwSpareRw3Spec > ; # [doc = "Register `HW_SPARE_RW3` writer"]
pub type W = crate :: W < HwSpareRw3Spec > ; # [doc = "Field `hw_spare_rw3` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw3R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw3` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw3 (& self) -> HwSpareRw3R { HwSpareRw3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw3 (& mut self) -> HwSpareRw3W < HwSpareRw3Spec > { HwSpareRw3W :: new (self , 0) } } # [doc = "HW_SPARE_RW3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw3Spec ; impl crate :: RegisterSpec for HwSpareRw3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw3::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw3Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw3::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW3 to value 0"]
impl crate :: Resettable for HwSpareRw3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW4 (rw) register accessor: HW_SPARE_RW4\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw4`]
module"]
# [doc (alias = "HW_SPARE_RW4")]
pub type HwSpareRw4 = crate :: Reg < hw_spare_rw4 :: HwSpareRw4Spec > ; # [doc = "HW_SPARE_RW4"]
pub mod hw_spare_rw4 { # [doc = "Register `HW_SPARE_RW4` reader"]
pub type R = crate :: R < HwSpareRw4Spec > ; # [doc = "Register `HW_SPARE_RW4` writer"]
pub type W = crate :: W < HwSpareRw4Spec > ; # [doc = "Field `hw_spare_rw4` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw4R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw4` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw4 (& self) -> HwSpareRw4R { HwSpareRw4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw4 (& mut self) -> HwSpareRw4W < HwSpareRw4Spec > { HwSpareRw4W :: new (self , 0) } } # [doc = "HW_SPARE_RW4\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw4Spec ; impl crate :: RegisterSpec for HwSpareRw4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw4::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw4Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw4::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW4 to value 0"]
impl crate :: Resettable for HwSpareRw4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW5 (rw) register accessor: HW_SPARE_RW5\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw5`]
module"]
# [doc (alias = "HW_SPARE_RW5")]
pub type HwSpareRw5 = crate :: Reg < hw_spare_rw5 :: HwSpareRw5Spec > ; # [doc = "HW_SPARE_RW5"]
pub mod hw_spare_rw5 { # [doc = "Register `HW_SPARE_RW5` reader"]
pub type R = crate :: R < HwSpareRw5Spec > ; # [doc = "Register `HW_SPARE_RW5` writer"]
pub type W = crate :: W < HwSpareRw5Spec > ; # [doc = "Field `hw_spare_rw5` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw5R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw5` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw5 (& self) -> HwSpareRw5R { HwSpareRw5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw5 (& mut self) -> HwSpareRw5W < HwSpareRw5Spec > { HwSpareRw5W :: new (self , 0) } } # [doc = "HW_SPARE_RW5\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw5Spec ; impl crate :: RegisterSpec for HwSpareRw5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw5::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw5Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw5::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW5 to value 0"]
impl crate :: Resettable for HwSpareRw5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RO0 (rw) register accessor: HW_SPARE_RO0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_ro0`]
module"]
# [doc (alias = "HW_SPARE_RO0")]
pub type HwSpareRo0 = crate :: Reg < hw_spare_ro0 :: HwSpareRo0Spec > ; # [doc = "HW_SPARE_RO0"]
pub mod hw_spare_ro0 { # [doc = "Register `HW_SPARE_RO0` reader"]
pub type R = crate :: R < HwSpareRo0Spec > ; # [doc = "Register `HW_SPARE_RO0` writer"]
pub type W = crate :: W < HwSpareRo0Spec > ; # [doc = "Field `hw_spare_ro0` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo0R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_ro0` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_ro0 (& self) -> HwSpareRo0R { HwSpareRo0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_ro0 (& mut self) -> HwSpareRo0W < HwSpareRo0Spec > { HwSpareRo0W :: new (self , 0) } } # [doc = "HW_SPARE_RO0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRo0Spec ; impl crate :: RegisterSpec for HwSpareRo0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_ro0::R`](R) reader structure"]
impl crate :: Readable for HwSpareRo0Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_ro0::W`](W) writer structure"]
impl crate :: Writable for HwSpareRo0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RO0 to value 0"]
impl crate :: Resettable for HwSpareRo0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RO1 (rw) register accessor: HW_SPARE_RO1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_ro1`]
module"]
# [doc (alias = "HW_SPARE_RO1")]
pub type HwSpareRo1 = crate :: Reg < hw_spare_ro1 :: HwSpareRo1Spec > ; # [doc = "HW_SPARE_RO1"]
pub mod hw_spare_ro1 { # [doc = "Register `HW_SPARE_RO1` reader"]
pub type R = crate :: R < HwSpareRo1Spec > ; # [doc = "Register `HW_SPARE_RO1` writer"]
pub type W = crate :: W < HwSpareRo1Spec > ; # [doc = "Field `hw_spare_ro1` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo1R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_ro1` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_ro1 (& self) -> HwSpareRo1R { HwSpareRo1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_ro1 (& mut self) -> HwSpareRo1W < HwSpareRo1Spec > { HwSpareRo1W :: new (self , 0) } } # [doc = "HW_SPARE_RO1\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRo1Spec ; impl crate :: RegisterSpec for HwSpareRo1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_ro1::R`](R) reader structure"]
impl crate :: Readable for HwSpareRo1Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_ro1::W`](W) writer structure"]
impl crate :: Writable for HwSpareRo1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RO1 to value 0"]
impl crate :: Resettable for HwSpareRo1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RO2 (rw) register accessor: HW_SPARE_RO2\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_ro2`]
module"]
# [doc (alias = "HW_SPARE_RO2")]
pub type HwSpareRo2 = crate :: Reg < hw_spare_ro2 :: HwSpareRo2Spec > ; # [doc = "HW_SPARE_RO2"]
pub mod hw_spare_ro2 { # [doc = "Register `HW_SPARE_RO2` reader"]
pub type R = crate :: R < HwSpareRo2Spec > ; # [doc = "Register `HW_SPARE_RO2` writer"]
pub type W = crate :: W < HwSpareRo2Spec > ; # [doc = "Field `hw_spare_ro2` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo2R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_ro2` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_ro2 (& self) -> HwSpareRo2R { HwSpareRo2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_ro2 (& mut self) -> HwSpareRo2W < HwSpareRo2Spec > { HwSpareRo2W :: new (self , 0) } } # [doc = "HW_SPARE_RO2\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRo2Spec ; impl crate :: RegisterSpec for HwSpareRo2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_ro2::R`](R) reader structure"]
impl crate :: Readable for HwSpareRo2Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_ro2::W`](W) writer structure"]
impl crate :: Writable for HwSpareRo2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RO2 to value 0"]
impl crate :: Resettable for HwSpareRo2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RO3 (rw) register accessor: HW_SPARE_RO3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_ro3`]
module"]
# [doc (alias = "HW_SPARE_RO3")]
pub type HwSpareRo3 = crate :: Reg < hw_spare_ro3 :: HwSpareRo3Spec > ; # [doc = "HW_SPARE_RO3"]
pub mod hw_spare_ro3 { # [doc = "Register `HW_SPARE_RO3` reader"]
pub type R = crate :: R < HwSpareRo3Spec > ; # [doc = "Register `HW_SPARE_RO3` writer"]
pub type W = crate :: W < HwSpareRo3Spec > ; # [doc = "Field `hw_spare_ro3` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo3R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_ro3` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRo3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_ro3 (& self) -> HwSpareRo3R { HwSpareRo3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_ro3 (& mut self) -> HwSpareRo3W < HwSpareRo3Spec > { HwSpareRo3W :: new (self , 0) } } # [doc = "HW_SPARE_RO3\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_ro3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_ro3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRo3Spec ; impl crate :: RegisterSpec for HwSpareRo3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_ro3::R`](R) reader structure"]
impl crate :: Readable for HwSpareRo3Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_ro3::W`](W) writer structure"]
impl crate :: Writable for HwSpareRo3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RO3 to value 0"]
impl crate :: Resettable for HwSpareRo3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_REC (rw) register accessor: HW_SPARE_REC\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rec`]
module"]
# [doc (alias = "HW_SPARE_REC")]
pub type HwSpareRec = crate :: Reg < hw_spare_rec :: HwSpareRecSpec > ; # [doc = "HW_SPARE_REC"]
pub mod hw_spare_rec { # [doc = "Register `HW_SPARE_REC` reader"]
pub type R = crate :: R < HwSpareRecSpec > ; # [doc = "Register `HW_SPARE_REC` writer"]
pub type W = crate :: W < HwSpareRecSpec > ; # [doc = "Field `hw_spare_rec0` reader - 0:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec0R = crate :: BitReader ; # [doc = "Field `hw_spare_rec0` writer - 0:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec1` reader - 1:1\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec1R = crate :: BitReader ; # [doc = "Field `hw_spare_rec1` writer - 1:1\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec2` reader - 2:2\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec2R = crate :: BitReader ; # [doc = "Field `hw_spare_rec2` writer - 2:2\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec3` reader - 3:3\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec3R = crate :: BitReader ; # [doc = "Field `hw_spare_rec3` writer - 3:3\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec4` reader - 4:4\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec4R = crate :: BitReader ; # [doc = "Field `hw_spare_rec4` writer - 4:4\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec5` reader - 5:5\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec5R = crate :: BitReader ; # [doc = "Field `hw_spare_rec5` writer - 5:5\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec6` reader - 6:6\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec6R = crate :: BitReader ; # [doc = "Field `hw_spare_rec6` writer - 6:6\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec7` reader - 7:7\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec7R = crate :: BitReader ; # [doc = "Field `hw_spare_rec7` writer - 7:7\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec8` reader - 8:8\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec8R = crate :: BitReader ; # [doc = "Field `hw_spare_rec8` writer - 8:8\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec8W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec9` reader - 9:9\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec9R = crate :: BitReader ; # [doc = "Field `hw_spare_rec9` writer - 9:9\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec10` reader - 10:10\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec10R = crate :: BitReader ; # [doc = "Field `hw_spare_rec10` writer - 10:10\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec11` reader - 11:11\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec11R = crate :: BitReader ; # [doc = "Field `hw_spare_rec11` writer - 11:11\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec11W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec12` reader - 12:12\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec12R = crate :: BitReader ; # [doc = "Field `hw_spare_rec12` writer - 12:12\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec12W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec13` reader - 13:13\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec13R = crate :: BitReader ; # [doc = "Field `hw_spare_rec13` writer - 13:13\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec13W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec14` reader - 14:14\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec14R = crate :: BitReader ; # [doc = "Field `hw_spare_rec14` writer - 14:14\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec14W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec15` reader - 15:15\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec15R = crate :: BitReader ; # [doc = "Field `hw_spare_rec15` writer - 15:15\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec15W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec16` reader - 16:16\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec16R = crate :: BitReader ; # [doc = "Field `hw_spare_rec16` writer - 16:16\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec16W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec17` reader - 17:17\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec17R = crate :: BitReader ; # [doc = "Field `hw_spare_rec17` writer - 17:17\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec17W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec18` reader - 18:18\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec18R = crate :: BitReader ; # [doc = "Field `hw_spare_rec18` writer - 18:18\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec18W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec19` reader - 19:19\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec19R = crate :: BitReader ; # [doc = "Field `hw_spare_rec19` writer - 19:19\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec19W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec20` reader - 20:20\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec20R = crate :: BitReader ; # [doc = "Field `hw_spare_rec20` writer - 20:20\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec20W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec21` reader - 21:21\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec21R = crate :: BitReader ; # [doc = "Field `hw_spare_rec21` writer - 21:21\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec21W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec22` reader - 22:22\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec22R = crate :: BitReader ; # [doc = "Field `hw_spare_rec22` writer - 22:22\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec22W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec23` reader - 23:23\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec23R = crate :: BitReader ; # [doc = "Field `hw_spare_rec23` writer - 23:23\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec23W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec24` reader - 24:24\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec24R = crate :: BitReader ; # [doc = "Field `hw_spare_rec24` writer - 24:24\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec24W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec25` reader - 25:25\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec25R = crate :: BitReader ; # [doc = "Field `hw_spare_rec25` writer - 25:25\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec25W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec26` reader - 26:26\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec26R = crate :: BitReader ; # [doc = "Field `hw_spare_rec26` writer - 26:26\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec26W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec27` reader - 27:27\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec27R = crate :: BitReader ; # [doc = "Field `hw_spare_rec27` writer - 27:27\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec27W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec28` reader - 28:28\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec28R = crate :: BitReader ; # [doc = "Field `hw_spare_rec28` writer - 28:28\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec28W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec29` reader - 29:29\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec29R = crate :: BitReader ; # [doc = "Field `hw_spare_rec29` writer - 29:29\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec29W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec30` reader - 30:30\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec30R = crate :: BitReader ; # [doc = "Field `hw_spare_rec30` writer - 30:30\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hw_spare_rec31` reader - 31:31\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec31R = crate :: BitReader ; # [doc = "Field `hw_spare_rec31` writer - 31:31\\]
Reserved for HW R&amp;D"]
pub type HwSpareRec31W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec0 (& self) -> HwSpareRec0R { HwSpareRec0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec1 (& self) -> HwSpareRec1R { HwSpareRec1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec2 (& self) -> HwSpareRec2R { HwSpareRec2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec3 (& self) -> HwSpareRec3R { HwSpareRec3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec4 (& self) -> HwSpareRec4R { HwSpareRec4R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec5 (& self) -> HwSpareRec5R { HwSpareRec5R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec6 (& self) -> HwSpareRec6R { HwSpareRec6R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec7 (& self) -> HwSpareRec7R { HwSpareRec7R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec8 (& self) -> HwSpareRec8R { HwSpareRec8R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec9 (& self) -> HwSpareRec9R { HwSpareRec9R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec10 (& self) -> HwSpareRec10R { HwSpareRec10R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec11 (& self) -> HwSpareRec11R { HwSpareRec11R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec12 (& self) -> HwSpareRec12R { HwSpareRec12R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec13 (& self) -> HwSpareRec13R { HwSpareRec13R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec14 (& self) -> HwSpareRec14R { HwSpareRec14R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec15 (& self) -> HwSpareRec15R { HwSpareRec15R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec16 (& self) -> HwSpareRec16R { HwSpareRec16R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec17 (& self) -> HwSpareRec17R { HwSpareRec17R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec18 (& self) -> HwSpareRec18R { HwSpareRec18R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec19 (& self) -> HwSpareRec19R { HwSpareRec19R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec20 (& self) -> HwSpareRec20R { HwSpareRec20R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec21 (& self) -> HwSpareRec21R { HwSpareRec21R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec22 (& self) -> HwSpareRec22R { HwSpareRec22R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec23 (& self) -> HwSpareRec23R { HwSpareRec23R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec24 (& self) -> HwSpareRec24R { HwSpareRec24R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec25 (& self) -> HwSpareRec25R { HwSpareRec25R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec26 (& self) -> HwSpareRec26R { HwSpareRec26R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec27 (& self) -> HwSpareRec27R { HwSpareRec27R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec28 (& self) -> HwSpareRec28R { HwSpareRec28R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec29 (& self) -> HwSpareRec29R { HwSpareRec29R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - 30:30\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec30 (& self) -> HwSpareRec30R { HwSpareRec30R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - 31:31\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rec31 (& self) -> HwSpareRec31R { HwSpareRec31R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec0 (& mut self) -> HwSpareRec0W < HwSpareRecSpec > { HwSpareRec0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec1 (& mut self) -> HwSpareRec1W < HwSpareRecSpec > { HwSpareRec1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec2 (& mut self) -> HwSpareRec2W < HwSpareRecSpec > { HwSpareRec2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec3 (& mut self) -> HwSpareRec3W < HwSpareRecSpec > { HwSpareRec3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec4 (& mut self) -> HwSpareRec4W < HwSpareRecSpec > { HwSpareRec4W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec5 (& mut self) -> HwSpareRec5W < HwSpareRecSpec > { HwSpareRec5W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec6 (& mut self) -> HwSpareRec6W < HwSpareRecSpec > { HwSpareRec6W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec7 (& mut self) -> HwSpareRec7W < HwSpareRecSpec > { HwSpareRec7W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec8 (& mut self) -> HwSpareRec8W < HwSpareRecSpec > { HwSpareRec8W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec9 (& mut self) -> HwSpareRec9W < HwSpareRecSpec > { HwSpareRec9W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec10 (& mut self) -> HwSpareRec10W < HwSpareRecSpec > { HwSpareRec10W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec11 (& mut self) -> HwSpareRec11W < HwSpareRecSpec > { HwSpareRec11W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec12 (& mut self) -> HwSpareRec12W < HwSpareRecSpec > { HwSpareRec12W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec13 (& mut self) -> HwSpareRec13W < HwSpareRecSpec > { HwSpareRec13W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec14 (& mut self) -> HwSpareRec14W < HwSpareRecSpec > { HwSpareRec14W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec15 (& mut self) -> HwSpareRec15W < HwSpareRecSpec > { HwSpareRec15W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec16 (& mut self) -> HwSpareRec16W < HwSpareRecSpec > { HwSpareRec16W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec17 (& mut self) -> HwSpareRec17W < HwSpareRecSpec > { HwSpareRec17W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec18 (& mut self) -> HwSpareRec18W < HwSpareRecSpec > { HwSpareRec18W :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec19 (& mut self) -> HwSpareRec19W < HwSpareRecSpec > { HwSpareRec19W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec20 (& mut self) -> HwSpareRec20W < HwSpareRecSpec > { HwSpareRec20W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec21 (& mut self) -> HwSpareRec21W < HwSpareRecSpec > { HwSpareRec21W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec22 (& mut self) -> HwSpareRec22W < HwSpareRecSpec > { HwSpareRec22W :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec23 (& mut self) -> HwSpareRec23W < HwSpareRecSpec > { HwSpareRec23W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec24 (& mut self) -> HwSpareRec24W < HwSpareRecSpec > { HwSpareRec24W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec25 (& mut self) -> HwSpareRec25W < HwSpareRecSpec > { HwSpareRec25W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec26 (& mut self) -> HwSpareRec26W < HwSpareRecSpec > { HwSpareRec26W :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec27 (& mut self) -> HwSpareRec27W < HwSpareRecSpec > { HwSpareRec27W :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec28 (& mut self) -> HwSpareRec28W < HwSpareRecSpec > { HwSpareRec28W :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec29 (& mut self) -> HwSpareRec29W < HwSpareRecSpec > { HwSpareRec29W :: new (self , 29) } # [doc = "Bit 30 - 30:30\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec30 (& mut self) -> HwSpareRec30W < HwSpareRecSpec > { HwSpareRec30W :: new (self , 30) } # [doc = "Bit 31 - 31:31\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rec31 (& mut self) -> HwSpareRec31W < HwSpareRecSpec > { HwSpareRec31W :: new (self , 31) } } # [doc = "HW_SPARE_REC\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRecSpec ; impl crate :: RegisterSpec for HwSpareRecSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rec::R`](R) reader structure"]
impl crate :: Readable for HwSpareRecSpec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rec::W`](W) writer structure"]
impl crate :: Writable for HwSpareRecSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_REC to value 0"]
impl crate :: Resettable for HwSpareRecSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CTRL (rw) register accessor: APP_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_ctrl`]
module"]
# [doc (alias = "APP_CTRL")]
pub type AppCtrl = crate :: Reg < app_ctrl :: AppCtrlSpec > ; # [doc = "APP_CTRL"]
pub mod app_ctrl { # [doc = "Register `APP_CTRL` reader"]
pub type R = crate :: R < AppCtrlSpec > ; # [doc = "Register `APP_CTRL` writer"]
pub type W = crate :: W < AppCtrlSpec > ; # [doc = "Field `ecc_disable_2k_ram` reader - 0:0\\]
Reserved"]
pub type EccDisable2kRamR = crate :: BitReader ; # [doc = "Field `ecc_disable_2k_ram` writer - 0:0\\]
Reserved"]
pub type EccDisable2kRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn ecc_disable_2k_ram (& self) -> EccDisable2kRamR { EccDisable2kRamR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn ecc_disable_2k_ram (& mut self) -> EccDisable2kRamW < AppCtrlSpec > { EccDisable2kRamW :: new (self , 0) } } # [doc = "APP_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCtrlSpec ; impl crate :: RegisterSpec for AppCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_ctrl::R`](R) reader structure"]
impl crate :: Readable for AppCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`app_ctrl::W`](W) writer structure"]
impl crate :: Writable for AppCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CTRL to value 0"]
impl crate :: Resettable for AppCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WIC_CTRL (rw) register accessor: WIC_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wic_ctrl`]
module"]
# [doc (alias = "WIC_CTRL")]
pub type WicCtrl = crate :: Reg < wic_ctrl :: WicCtrlSpec > ; # [doc = "WIC_CTRL"]
pub mod wic_ctrl { # [doc = "Register `WIC_CTRL` reader"]
pub type R = crate :: R < WicCtrlSpec > ; # [doc = "Register `WIC_CTRL` writer"]
pub type W = crate :: W < WicCtrlSpec > ; # [doc = "Field `wicmask` reader - 31:0\\]
1 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
pub type WicmaskR = crate :: FieldReader < u32 > ; # [doc = "Field `wicmask` writer - 31:0\\]
1 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
pub type WicmaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
1 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
# [inline (always)]
pub fn wicmask (& self) -> WicmaskR { WicmaskR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
1 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
# [inline (always)]
# [must_use]
pub fn wicmask (& mut self) -> WicmaskW < WicCtrlSpec > { WicmaskW :: new (self , 0) } } # [doc = "WIC_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WicCtrlSpec ; impl crate :: RegisterSpec for WicCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wic_ctrl::R`](R) reader structure"]
impl crate :: Readable for WicCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`wic_ctrl::W`](W) writer structure"]
impl crate :: Writable for WicCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WIC_CTRL to value 0"]
impl crate :: Resettable for WicCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WIC_STAT_CLR (rw) register accessor: WIC_STAT_CLR\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_stat_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_stat_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wic_stat_clr`]
module"]
# [doc (alias = "WIC_STAT_CLR")]
pub type WicStatClr = crate :: Reg < wic_stat_clr :: WicStatClrSpec > ; # [doc = "WIC_STAT_CLR"]
pub mod wic_stat_clr { # [doc = "Register `WIC_STAT_CLR` reader"]
pub type R = crate :: R < WicStatClrSpec > ; # [doc = "Register `WIC_STAT_CLR` writer"]
pub type W = crate :: W < WicStatClrSpec > ; # [doc = "Field `wicstatclr` reader - 31:0\\]
1 => Writing 1 to this bit, will clear the WIC_STAT status register of the corresponding bit. Self-clearing 0 => Writing 0 to this bit, leavesWIC_STAT status register unchanged for the corresponding bit."]
pub type WicstatclrR = crate :: FieldReader < u32 > ; # [doc = "Field `wicstatclr` writer - 31:0\\]
1 => Writing 1 to this bit, will clear the WIC_STAT status register of the corresponding bit. Self-clearing 0 => Writing 0 to this bit, leavesWIC_STAT status register unchanged for the corresponding bit."]
pub type WicstatclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
1 => Writing 1 to this bit, will clear the WIC_STAT status register of the corresponding bit. Self-clearing 0 => Writing 0 to this bit, leavesWIC_STAT status register unchanged for the corresponding bit."]
# [inline (always)]
pub fn wicstatclr (& self) -> WicstatclrR { WicstatclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
1 => Writing 1 to this bit, will clear the WIC_STAT status register of the corresponding bit. Self-clearing 0 => Writing 0 to this bit, leavesWIC_STAT status register unchanged for the corresponding bit."]
# [inline (always)]
# [must_use]
pub fn wicstatclr (& mut self) -> WicstatclrW < WicStatClrSpec > { WicstatclrW :: new (self , 0) } } # [doc = "WIC_STAT_CLR\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_stat_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_stat_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WicStatClrSpec ; impl crate :: RegisterSpec for WicStatClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wic_stat_clr::R`](R) reader structure"]
impl crate :: Readable for WicStatClrSpec { } # [doc = "`write(|w| ..)` method takes [`wic_stat_clr::W`](W) writer structure"]
impl crate :: Writable for WicStatClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WIC_STAT_CLR to value 0"]
impl crate :: Resettable for WicStatClrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WIC_STAT (rw) register accessor: WIC_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wic_stat`]
module"]
# [doc (alias = "WIC_STAT")]
pub type WicStat = crate :: Reg < wic_stat :: WicStatSpec > ; # [doc = "WIC_STAT"]
pub mod wic_stat { # [doc = "Register `WIC_STAT` reader"]
pub type R = crate :: R < WicStatSpec > ; # [doc = "Register `WIC_STAT` writer"]
pub type W = crate :: W < WicStatSpec > ; # [doc = "Field `wicstat` reader - 31:0\\]
1 => Interrupt bit set. The interupt bit is sticky bit. Should be cleared using WIC_STAT_CLR register or subsystem reset. 0 -> Interrupt bit not set. Sticky bits keep their value when they changed to logical 1 and is cleared only by writing 1 to WIC_STAT_CLR register."]
pub type WicstatR = crate :: FieldReader < u32 > ; # [doc = "Field `wicstat` writer - 31:0\\]
1 => Interrupt bit set. The interupt bit is sticky bit. Should be cleared using WIC_STAT_CLR register or subsystem reset. 0 -> Interrupt bit not set. Sticky bits keep their value when they changed to logical 1 and is cleared only by writing 1 to WIC_STAT_CLR register."]
pub type WicstatW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
1 => Interrupt bit set. The interupt bit is sticky bit. Should be cleared using WIC_STAT_CLR register or subsystem reset. 0 -> Interrupt bit not set. Sticky bits keep their value when they changed to logical 1 and is cleared only by writing 1 to WIC_STAT_CLR register."]
# [inline (always)]
pub fn wicstat (& self) -> WicstatR { WicstatR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
1 => Interrupt bit set. The interupt bit is sticky bit. Should be cleared using WIC_STAT_CLR register or subsystem reset. 0 -> Interrupt bit not set. Sticky bits keep their value when they changed to logical 1 and is cleared only by writing 1 to WIC_STAT_CLR register."]
# [inline (always)]
# [must_use]
pub fn wicstat (& mut self) -> WicstatW < WicStatSpec > { WicstatW :: new (self , 0) } } # [doc = "WIC_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WicStatSpec ; impl crate :: RegisterSpec for WicStatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wic_stat::R`](R) reader structure"]
impl crate :: Readable for WicStatSpec { } # [doc = "`write(|w| ..)` method takes [`wic_stat::W`](W) writer structure"]
impl crate :: Writable for WicStatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WIC_STAT to value 0"]
impl crate :: Resettable for WicStatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WICEN (rw) register accessor: WICEN\n\nYou can [`read`](crate::Reg::read) this register and get [`wicen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wicen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wicen`]
module"]
# [doc (alias = "WICEN")]
pub type Wicen = crate :: Reg < wicen :: WicenSpec > ; # [doc = "WICEN"]
pub mod wicen { # [doc = "Register `WICEN` reader"]
pub type R = crate :: R < WicenSpec > ; # [doc = "Register `WICEN` writer"]
pub type W = crate :: W < WicenSpec > ; # [doc = "Field `wicen` reader - 0:0\\]
1 :> Wakeup Interrupt Controller (WIC) of CM4 is Enabled 0 :> Disabled"]
pub type WicenR = crate :: BitReader ; # [doc = "Field `wicen` writer - 0:0\\]
1 :> Wakeup Interrupt Controller (WIC) of CM4 is Enabled 0 :> Disabled"]
pub type WicenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 :> Wakeup Interrupt Controller (WIC) of CM4 is Enabled 0 :> Disabled"]
# [inline (always)]
pub fn wicen (& self) -> WicenR { WicenR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 :> Wakeup Interrupt Controller (WIC) of CM4 is Enabled 0 :> Disabled"]
# [inline (always)]
# [must_use]
pub fn wicen (& mut self) -> WicenW < WicenSpec > { WicenW :: new (self , 0) } } # [doc = "WICEN\n\nYou can [`read`](crate::Reg::read) this register and get [`wicen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wicen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WicenSpec ; impl crate :: RegisterSpec for WicenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wicen::R`](R) reader structure"]
impl crate :: Readable for WicenSpec { } # [doc = "`write(|w| ..)` method takes [`wicen::W`](W) writer structure"]
impl crate :: Writable for WicenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WICEN to value 0"]
impl crate :: Resettable for WicenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FORCEFCLKACTIVE (rw) register accessor: FORCEFCLKACTIVE\n\nYou can [`read`](crate::Reg::read) this register and get [`forcefclkactive::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`forcefclkactive::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@forcefclkactive`]
module"]
# [doc (alias = "FORCEFCLKACTIVE")]
pub type Forcefclkactive = crate :: Reg < forcefclkactive :: ForcefclkactiveSpec > ; # [doc = "FORCEFCLKACTIVE"]
pub mod forcefclkactive { # [doc = "Register `FORCEFCLKACTIVE` reader"]
pub type R = crate :: R < ForcefclkactiveSpec > ; # [doc = "Register `FORCEFCLKACTIVE` writer"]
pub type W = crate :: W < ForcefclkactiveSpec > ; # [doc = "Field `forcefclkactive` reader - 0:0\\]
1 :> Forces FCLK to be active and inhibits CM4 Entering CPU DeepSleep mode 0 :> Allows gating of FCLK based on CPU DEEPSLEEP entry mechanism"]
pub type ForcefclkactiveR = crate :: BitReader ; # [doc = "Field `forcefclkactive` writer - 0:0\\]
1 :> Forces FCLK to be active and inhibits CM4 Entering CPU DeepSleep mode 0 :> Allows gating of FCLK based on CPU DEEPSLEEP entry mechanism"]
pub type ForcefclkactiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 :> Forces FCLK to be active and inhibits CM4 Entering CPU DeepSleep mode 0 :> Allows gating of FCLK based on CPU DEEPSLEEP entry mechanism"]
# [inline (always)]
pub fn forcefclkactive (& self) -> ForcefclkactiveR { ForcefclkactiveR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 :> Forces FCLK to be active and inhibits CM4 Entering CPU DeepSleep mode 0 :> Allows gating of FCLK based on CPU DEEPSLEEP entry mechanism"]
# [inline (always)]
# [must_use]
pub fn forcefclkactive (& mut self) -> ForcefclkactiveW < ForcefclkactiveSpec > { ForcefclkactiveW :: new (self , 0) } } # [doc = "FORCEFCLKACTIVE\n\nYou can [`read`](crate::Reg::read) this register and get [`forcefclkactive::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`forcefclkactive::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ForcefclkactiveSpec ; impl crate :: RegisterSpec for ForcefclkactiveSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`forcefclkactive::R`](R) reader structure"]
impl crate :: Readable for ForcefclkactiveSpec { } # [doc = "`write(|w| ..)` method takes [`forcefclkactive::W`](W) writer structure"]
impl crate :: Writable for ForcefclkactiveSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FORCEFCLKACTIVE to value 0"]
impl crate :: Resettable for ForcefclkactiveSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FECSS_CLK_GATE (rw) register accessor: FECSS_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`fecss_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fecss_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fecss_clk_gate`]
module"]
# [doc (alias = "FECSS_CLK_GATE")]
pub type FecssClkGate = crate :: Reg < fecss_clk_gate :: FecssClkGateSpec > ; # [doc = "FECSS_CLK_GATE"]
pub mod fecss_clk_gate { # [doc = "Register `FECSS_CLK_GATE` reader"]
pub type R = crate :: R < FecssClkGateSpec > ; # [doc = "Register `FECSS_CLK_GATE` writer"]
pub type W = crate :: W < FecssClkGateSpec > ; # [doc = "Field `grp1` reader - 2:0\\]
Multibit: Writing 3'b111 will gate FEC_SYS_CLK and FECSS peripheral clocks except DFE and Timing Engine"]
pub type Grp1R = crate :: FieldReader ; # [doc = "Field `grp1` writer - 2:0\\]
Multibit: Writing 3'b111 will gate FEC_SYS_CLK and FECSS peripheral clocks except DFE and Timing Engine"]
pub type Grp1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `grp2` reader - 5:3\\]
Multibit: Writing 3'b111 will gate ADC_CLK going to DFE and Timing Engine"]
pub type Grp2R = crate :: FieldReader ; # [doc = "Field `grp2` writer - 5:3\\]
Multibit: Writing 3'b111 will gate ADC_CLK going to DFE and Timing Engine"]
pub type Grp2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Multibit: Writing 3'b111 will gate FEC_SYS_CLK and FECSS peripheral clocks except DFE and Timing Engine"]
# [inline (always)]
pub fn grp1 (& self) -> Grp1R { Grp1R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
Multibit: Writing 3'b111 will gate ADC_CLK going to DFE and Timing Engine"]
# [inline (always)]
pub fn grp2 (& self) -> Grp2R { Grp2R :: new (((self . bits >> 3) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Multibit: Writing 3'b111 will gate FEC_SYS_CLK and FECSS peripheral clocks except DFE and Timing Engine"]
# [inline (always)]
# [must_use]
pub fn grp1 (& mut self) -> Grp1W < FecssClkGateSpec > { Grp1W :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
Multibit: Writing 3'b111 will gate ADC_CLK going to DFE and Timing Engine"]
# [inline (always)]
# [must_use]
pub fn grp2 (& mut self) -> Grp2W < FecssClkGateSpec > { Grp2W :: new (self , 3) } } # [doc = "FECSS_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`fecss_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fecss_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecssClkGateSpec ; impl crate :: RegisterSpec for FecssClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fecss_clk_gate::R`](R) reader structure"]
impl crate :: Readable for FecssClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`fecss_clk_gate::W`](W) writer structure"]
impl crate :: Writable for FecssClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FECSS_CLK_GATE to value 0"]
impl crate :: Resettable for FecssClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SHARED_MEM_CLK_GATE (rw) register accessor: APPSS_SHARED_MEM_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_shared_mem_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_shared_mem_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_shared_mem_clk_gate`]
module"]
# [doc (alias = "APPSS_SHARED_MEM_CLK_GATE")]
pub type AppssSharedMemClkGate = crate :: Reg < appss_shared_mem_clk_gate :: AppssSharedMemClkGateSpec > ; # [doc = "APPSS_SHARED_MEM_CLK_GATE"]
pub mod appss_shared_mem_clk_gate { # [doc = "Register `APPSS_SHARED_MEM_CLK_GATE` reader"]
pub type R = crate :: R < AppssSharedMemClkGateSpec > ; # [doc = "Register `APPSS_SHARED_MEM_CLK_GATE` writer"]
pub type W = crate :: W < AppssSharedMemClkGateSpec > ; # [doc = "Field `mem0_hwa_enable` reader - 0:0\\]
1'b1 : Enable HWA CLK ICG for first 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for first 128 KB of shared mem"]
pub type Mem0HwaEnableR = crate :: BitReader ; # [doc = "Field `mem0_hwa_enable` writer - 0:0\\]
1'b1 : Enable HWA CLK ICG for first 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for first 128 KB of shared mem"]
pub type Mem0HwaEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `mem0_app_enable` reader - 1:1\\]
1'b1 : Enable APP CLK ICG for first 128KB of shared mem 1'b0 : Disable APP CLK ICG for first 128 KB of shared mem"]
pub type Mem0AppEnableR = crate :: BitReader ; # [doc = "Field `mem0_app_enable` writer - 1:1\\]
1'b1 : Enable APP CLK ICG for first 128KB of shared mem 1'b0 : Disable APP CLK ICG for first 128 KB of shared mem"]
pub type Mem0AppEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `mem1_hwa_enable` reader - 2:2\\]
1'b1 : Enable HWA CLK ICG for second 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for second 128 KB of shared mem"]
pub type Mem1HwaEnableR = crate :: BitReader ; # [doc = "Field `mem1_hwa_enable` writer - 2:2\\]
1'b1 : Enable HWA CLK ICG for second 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for second 128 KB of shared mem"]
pub type Mem1HwaEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `mem1_app_enable` reader - 3:3\\]
1'b1 : Enable APP CLK ICG for second 128KB of shared mem 1'b0 : Disable APP CLK ICG for second 128 KB of shared mem"]
pub type Mem1AppEnableR = crate :: BitReader ; # [doc = "Field `mem1_app_enable` writer - 3:3\\]
1'b1 : Enable APP CLK ICG for second 128KB of shared mem 1'b0 : Disable APP CLK ICG for second 128 KB of shared mem"]
pub type Mem1AppEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b1 : Enable HWA CLK ICG for first 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for first 128 KB of shared mem"]
# [inline (always)]
pub fn mem0_hwa_enable (& self) -> Mem0HwaEnableR { Mem0HwaEnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1'b1 : Enable APP CLK ICG for first 128KB of shared mem 1'b0 : Disable APP CLK ICG for first 128 KB of shared mem"]
# [inline (always)]
pub fn mem0_app_enable (& self) -> Mem0AppEnableR { Mem0AppEnableR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
1'b1 : Enable HWA CLK ICG for second 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for second 128 KB of shared mem"]
# [inline (always)]
pub fn mem1_hwa_enable (& self) -> Mem1HwaEnableR { Mem1HwaEnableR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
1'b1 : Enable APP CLK ICG for second 128KB of shared mem 1'b0 : Disable APP CLK ICG for second 128 KB of shared mem"]
# [inline (always)]
pub fn mem1_app_enable (& self) -> Mem1AppEnableR { Mem1AppEnableR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b1 : Enable HWA CLK ICG for first 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for first 128 KB of shared mem"]
# [inline (always)]
# [must_use]
pub fn mem0_hwa_enable (& mut self) -> Mem0HwaEnableW < AppssSharedMemClkGateSpec > { Mem0HwaEnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1'b1 : Enable APP CLK ICG for first 128KB of shared mem 1'b0 : Disable APP CLK ICG for first 128 KB of shared mem"]
# [inline (always)]
# [must_use]
pub fn mem0_app_enable (& mut self) -> Mem0AppEnableW < AppssSharedMemClkGateSpec > { Mem0AppEnableW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
1'b1 : Enable HWA CLK ICG for second 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for second 128 KB of shared mem"]
# [inline (always)]
# [must_use]
pub fn mem1_hwa_enable (& mut self) -> Mem1HwaEnableW < AppssSharedMemClkGateSpec > { Mem1HwaEnableW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
1'b1 : Enable APP CLK ICG for second 128KB of shared mem 1'b0 : Disable APP CLK ICG for second 128 KB of shared mem"]
# [inline (always)]
# [must_use]
pub fn mem1_app_enable (& mut self) -> Mem1AppEnableW < AppssSharedMemClkGateSpec > { Mem1AppEnableW :: new (self , 3) } } # [doc = "APPSS_SHARED_MEM_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_shared_mem_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_shared_mem_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssSharedMemClkGateSpec ; impl crate :: RegisterSpec for AppssSharedMemClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_shared_mem_clk_gate::R`](R) reader structure"]
impl crate :: Readable for AppssSharedMemClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`appss_shared_mem_clk_gate::W`](W) writer structure"]
impl crate :: Writable for AppssSharedMemClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SHARED_MEM_CLK_GATE to value 0"]
impl crate :: Resettable for AppssSharedMemClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_MEM_INIT_SLICE_SEL (rw) register accessor: APPSS_MEM_INIT_SLICE_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mem_init_slice_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mem_init_slice_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_mem_init_slice_sel`]
module"]
# [doc (alias = "APPSS_MEM_INIT_SLICE_SEL")]
pub type AppssMemInitSliceSel = crate :: Reg < appss_mem_init_slice_sel :: AppssMemInitSliceSelSpec > ; # [doc = "APPSS_MEM_INIT_SLICE_SEL"]
pub mod appss_mem_init_slice_sel { # [doc = "Register `APPSS_MEM_INIT_SLICE_SEL` reader"]
pub type R = crate :: R < AppssMemInitSliceSelSpec > ; # [doc = "Register `APPSS_MEM_INIT_SLICE_SEL` writer"]
pub type W = crate :: W < AppssMemInitSliceSelSpec > ; # [doc = "Field `cfg_bank1` reader - 2:0\\]
Selects the APPSS RAM1 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_1A (64KB) Bit#1 : Selects RAM_1B (64KB) Bit#2 : Selects RAM_1C (128KB) 1 => RAM selected for mem_init operation 0 => RAM not selected for mem_init operation."]
pub type CfgBank1R = crate :: FieldReader ; # [doc = "Field `cfg_bank1` writer - 2:0\\]
Selects the APPSS RAM1 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_1A (64KB) Bit#1 : Selects RAM_1B (64KB) Bit#2 : Selects RAM_1C (128KB) 1 => RAM selected for mem_init operation 0 => RAM not selected for mem_init operation."]
pub type CfgBank1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cfg_bank2` reader - 4:3\\]
Selects the APPSS RAM2 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_2A (16KB) Bit#1 : Selects RAM_2B (112KB) 1 => RAM partition selected for mem_init operation 0 => RAM partition not selected for mem_init operation."]
pub type CfgBank2R = crate :: FieldReader ; # [doc = "Field `cfg_bank2` writer - 4:3\\]
Selects the APPSS RAM2 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_2A (16KB) Bit#1 : Selects RAM_2B (112KB) 1 => RAM partition selected for mem_init operation 0 => RAM partition not selected for mem_init operation."]
pub type CfgBank2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Selects the APPSS RAM1 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_1A (64KB) Bit#1 : Selects RAM_1B (64KB) Bit#2 : Selects RAM_1C (128KB) 1 => RAM selected for mem_init operation 0 => RAM not selected for mem_init operation."]
# [inline (always)]
pub fn cfg_bank1 (& self) -> CfgBank1R { CfgBank1R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:4 - 4:3\\]
Selects the APPSS RAM2 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_2A (16KB) Bit#1 : Selects RAM_2B (112KB) 1 => RAM partition selected for mem_init operation 0 => RAM partition not selected for mem_init operation."]
# [inline (always)]
pub fn cfg_bank2 (& self) -> CfgBank2R { CfgBank2R :: new (((self . bits >> 3) & 3) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Selects the APPSS RAM1 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_1A (64KB) Bit#1 : Selects RAM_1B (64KB) Bit#2 : Selects RAM_1C (128KB) 1 => RAM selected for mem_init operation 0 => RAM not selected for mem_init operation."]
# [inline (always)]
# [must_use]
pub fn cfg_bank1 (& mut self) -> CfgBank1W < AppssMemInitSliceSelSpec > { CfgBank1W :: new (self , 0) } # [doc = "Bits 3:4 - 4:3\\]
Selects the APPSS RAM2 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_2A (16KB) Bit#1 : Selects RAM_2B (112KB) 1 => RAM partition selected for mem_init operation 0 => RAM partition not selected for mem_init operation."]
# [inline (always)]
# [must_use]
pub fn cfg_bank2 (& mut self) -> CfgBank2W < AppssMemInitSliceSelSpec > { CfgBank2W :: new (self , 3) } } # [doc = "APPSS_MEM_INIT_SLICE_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_mem_init_slice_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_mem_init_slice_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssMemInitSliceSelSpec ; impl crate :: RegisterSpec for AppssMemInitSliceSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_mem_init_slice_sel::R`](R) reader structure"]
impl crate :: Readable for AppssMemInitSliceSelSpec { } # [doc = "`write(|w| ..)` method takes [`appss_mem_init_slice_sel::W`](W) writer structure"]
impl crate :: Writable for AppssMemInitSliceSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_MEM_INIT_SLICE_SEL to value 0"]
impl crate :: Resettable for AppssMemInitSliceSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_QSPI_CHAR_EXT_CLK_EN (rw) register accessor: APPSS_QSPI_CHAR_EXT_CLK_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_qspi_char_ext_clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_qspi_char_ext_clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_qspi_char_ext_clk_en`]
module"]
# [doc (alias = "APPSS_QSPI_CHAR_EXT_CLK_EN")]
pub type AppssQspiCharExtClkEn = crate :: Reg < appss_qspi_char_ext_clk_en :: AppssQspiCharExtClkEnSpec > ; # [doc = "APPSS_QSPI_CHAR_EXT_CLK_EN"]
pub mod appss_qspi_char_ext_clk_en { # [doc = "Register `APPSS_QSPI_CHAR_EXT_CLK_EN` reader"]
pub type R = crate :: R < AppssQspiCharExtClkEnSpec > ; # [doc = "Register `APPSS_QSPI_CHAR_EXT_CLK_EN` writer"]
pub type W = crate :: W < AppssQspiCharExtClkEnSpec > ; # [doc = "Field `enable` reader - 0:0\\]
Selects the QSPI system clock. Only for DFT purposes. This should not be changed for functional operation. 0 => QSPI_CLK from APPSS RCM 1 => SPI1_CLK from APPSS RCM"]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
Selects the QSPI system clock. Only for DFT purposes. This should not be changed for functional operation. 0 => QSPI_CLK from APPSS RCM 1 => SPI1_CLK from APPSS RCM"]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Selects the QSPI system clock. Only for DFT purposes. This should not be changed for functional operation. 0 => QSPI_CLK from APPSS RCM 1 => SPI1_CLK from APPSS RCM"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Selects the QSPI system clock. Only for DFT purposes. This should not be changed for functional operation. 0 => QSPI_CLK from APPSS RCM 1 => SPI1_CLK from APPSS RCM"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppssQspiCharExtClkEnSpec > { EnableW :: new (self , 0) } } # [doc = "APPSS_QSPI_CHAR_EXT_CLK_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_qspi_char_ext_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_qspi_char_ext_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssQspiCharExtClkEnSpec ; impl crate :: RegisterSpec for AppssQspiCharExtClkEnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_qspi_char_ext_clk_en::R`](R) reader structure"]
impl crate :: Readable for AppssQspiCharExtClkEnSpec { } # [doc = "`write(|w| ..)` method takes [`appss_qspi_char_ext_clk_en::W`](W) writer structure"]
impl crate :: Writable for AppssQspiCharExtClkEnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_QSPI_CHAR_EXT_CLK_EN to value 0"]
impl crate :: Resettable for AppssQspiCharExtClkEnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_QSPI_EXT_CLK_EN (rw) register accessor: APPSS_QSPI_EXT_CLK_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_qspi_ext_clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_qspi_ext_clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_qspi_ext_clk_en`]
module"]
# [doc (alias = "APPSS_QSPI_EXT_CLK_EN")]
pub type AppssQspiExtClkEn = crate :: Reg < appss_qspi_ext_clk_en :: AppssQspiExtClkEnSpec > ; # [doc = "APPSS_QSPI_EXT_CLK_EN"]
pub mod appss_qspi_ext_clk_en { # [doc = "Register `APPSS_QSPI_EXT_CLK_EN` reader"]
pub type R = crate :: R < AppssQspiExtClkEnSpec > ; # [doc = "Register `APPSS_QSPI_EXT_CLK_EN` writer"]
pub type W = crate :: W < AppssQspiExtClkEnSpec > ; # [doc = "Field `enable` reader - 0:0\\]
Selects the QSPI interface clock. This register bit is used only for AC CHAR operation and not for functional usage. 0 => default QSPI IP clock return from PAD 1 => SPI1 IF CLK. (McSPI IF clock)."]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
Selects the QSPI interface clock. This register bit is used only for AC CHAR operation and not for functional usage. 0 => default QSPI IP clock return from PAD 1 => SPI1 IF CLK. (McSPI IF clock)."]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Selects the QSPI interface clock. This register bit is used only for AC CHAR operation and not for functional usage. 0 => default QSPI IP clock return from PAD 1 => SPI1 IF CLK. (McSPI IF clock)."]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Selects the QSPI interface clock. This register bit is used only for AC CHAR operation and not for functional usage. 0 => default QSPI IP clock return from PAD 1 => SPI1 IF CLK. (McSPI IF clock)."]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < AppssQspiExtClkEnSpec > { EnableW :: new (self , 0) } } # [doc = "APPSS_QSPI_EXT_CLK_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_qspi_ext_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_qspi_ext_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssQspiExtClkEnSpec ; impl crate :: RegisterSpec for AppssQspiExtClkEnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_qspi_ext_clk_en::R`](R) reader structure"]
impl crate :: Readable for AppssQspiExtClkEnSpec { } # [doc = "`write(|w| ..)` method takes [`appss_qspi_ext_clk_en::W`](W) writer structure"]
impl crate :: Writable for AppssQspiExtClkEnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_QSPI_EXT_CLK_EN to value 0"]
impl crate :: Resettable for AppssQspiExtClkEnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI1_SMART_IDLE (rw) register accessor: SPI1_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`spi1_smart_idle::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi1_smart_idle::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi1_smart_idle`]
module"]
# [doc (alias = "SPI1_SMART_IDLE")]
pub type Spi1SmartIdle = crate :: Reg < spi1_smart_idle :: Spi1SmartIdleSpec > ; # [doc = "SPI1_SMART_IDLE"]
pub mod spi1_smart_idle { # [doc = "Register `SPI1_SMART_IDLE` reader"]
pub type R = crate :: R < Spi1SmartIdleSpec > ; # [doc = "Register `SPI1_SMART_IDLE` writer"]
pub type W = crate :: W < Spi1SmartIdleSpec > ; # [doc = "Field `enable` reader - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI1 module. 0 => Disable Smart IDLE mode for SPI1"]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI1 module. 0 => Disable Smart IDLE mode for SPI1"]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack` reader - 1:1\\]
1 => SPI1 in smart idle mode 0 => SPI1 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type AckR = crate :: BitReader ; # [doc = "Field `ack` writer - 1:1\\]
1 => SPI1 in smart idle mode 0 => SPI1 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type AckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `auto_en` reader - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - Entry to smart idle mode Is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
pub type AutoEnR = crate :: BitReader ; # [doc = "Field `auto_en` writer - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - Entry to smart idle mode Is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
pub type AutoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup` reader - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type WakeupR = crate :: BitReader ; # [doc = "Field `wakeup` writer - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type WakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack_raw` reader - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI1) module. This should be interpreted along with SPI1_SMART_IDLE_ACK SPI1_SMART_IDLE_ACK_RAW, SPI1_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
pub type AckRawR = crate :: BitReader ; # [doc = "Field `ack_raw` writer - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI1) module. This should be interpreted along with SPI1_SMART_IDLE_ACK SPI1_SMART_IDLE_ACK_RAW, SPI1_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
pub type AckRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_raw` reader - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI1 module. This should be interpreted along with SPI1_SMART_IDLE_WAKEUP SPI1_SMART_IDLE_WAKEUP_RAW, SPI1_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
pub type WakeupRawR = crate :: BitReader ; # [doc = "Field `wakeup_raw` writer - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI1 module. This should be interpreted along with SPI1_SMART_IDLE_WAKEUP SPI1_SMART_IDLE_WAKEUP_RAW, SPI1_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
pub type WakeupRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI1 module. 0 => Disable Smart IDLE mode for SPI1"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1 => SPI1 in smart idle mode 0 => SPI1 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
pub fn ack (& self) -> AckR { AckR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - Entry to smart idle mode Is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
# [inline (always)]
pub fn auto_en (& self) -> AutoEnR { AutoEnR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
pub fn wakeup (& self) -> WakeupR { WakeupR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI1) module. This should be interpreted along with SPI1_SMART_IDLE_ACK SPI1_SMART_IDLE_ACK_RAW, SPI1_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
# [inline (always)]
pub fn ack_raw (& self) -> AckRawR { AckRawR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI1 module. This should be interpreted along with SPI1_SMART_IDLE_WAKEUP SPI1_SMART_IDLE_WAKEUP_RAW, SPI1_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
# [inline (always)]
pub fn wakeup_raw (& self) -> WakeupRawR { WakeupRawR :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI1 module. 0 => Disable Smart IDLE mode for SPI1"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < Spi1SmartIdleSpec > { EnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1 => SPI1 in smart idle mode 0 => SPI1 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
# [must_use]
pub fn ack (& mut self) -> AckW < Spi1SmartIdleSpec > { AckW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - Entry to smart idle mode Is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
# [inline (always)]
# [must_use]
pub fn auto_en (& mut self) -> AutoEnW < Spi1SmartIdleSpec > { AutoEnW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
# [must_use]
pub fn wakeup (& mut self) -> WakeupW < Spi1SmartIdleSpec > { WakeupW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI1) module. This should be interpreted along with SPI1_SMART_IDLE_ACK SPI1_SMART_IDLE_ACK_RAW, SPI1_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
# [inline (always)]
# [must_use]
pub fn ack_raw (& mut self) -> AckRawW < Spi1SmartIdleSpec > { AckRawW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI1 module. This should be interpreted along with SPI1_SMART_IDLE_WAKEUP SPI1_SMART_IDLE_WAKEUP_RAW, SPI1_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
# [inline (always)]
# [must_use]
pub fn wakeup_raw (& mut self) -> WakeupRawW < Spi1SmartIdleSpec > { WakeupRawW :: new (self , 5) } } # [doc = "SPI1_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`spi1_smart_idle::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi1_smart_idle::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Spi1SmartIdleSpec ; impl crate :: RegisterSpec for Spi1SmartIdleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi1_smart_idle::R`](R) reader structure"]
impl crate :: Readable for Spi1SmartIdleSpec { } # [doc = "`write(|w| ..)` method takes [`spi1_smart_idle::W`](W) writer structure"]
impl crate :: Writable for Spi1SmartIdleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI1_SMART_IDLE to value 0"]
impl crate :: Resettable for Spi1SmartIdleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI2_SMART_IDLE (rw) register accessor: SPI2_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`spi2_smart_idle::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi2_smart_idle::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi2_smart_idle`]
module"]
# [doc (alias = "SPI2_SMART_IDLE")]
pub type Spi2SmartIdle = crate :: Reg < spi2_smart_idle :: Spi2SmartIdleSpec > ; # [doc = "SPI2_SMART_IDLE"]
pub mod spi2_smart_idle { # [doc = "Register `SPI2_SMART_IDLE` reader"]
pub type R = crate :: R < Spi2SmartIdleSpec > ; # [doc = "Register `SPI2_SMART_IDLE` writer"]
pub type W = crate :: W < Spi2SmartIdleSpec > ; # [doc = "Field `enable` reader - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI2 module. 0 => Disable Smart IDLE mode for SPI2"]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI2 module. 0 => Disable Smart IDLE mode for SPI2"]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack` reader - 1:1\\]
1 => SPI2 in smart idle mode 0 => SPI2 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type AckR = crate :: BitReader ; # [doc = "Field `ack` writer - 1:1\\]
1 => SPI2 in smart idle mode 0 => SPI2 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type AckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `auto_en` reader - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
pub type AutoEnR = crate :: BitReader ; # [doc = "Field `auto_en` writer - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
pub type AutoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup` reader - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type WakeupR = crate :: BitReader ; # [doc = "Field `wakeup` writer - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type WakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack_raw` reader - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI2) module. This should be interpreted along with SPI2_SMART_IDLE_ACK SPI2_SMART_IDLE_ACK_RAW, SPI2_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
pub type AckRawR = crate :: BitReader ; # [doc = "Field `ack_raw` writer - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI2) module. This should be interpreted along with SPI2_SMART_IDLE_ACK SPI2_SMART_IDLE_ACK_RAW, SPI2_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
pub type AckRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_raw` reader - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI2 module. This should be interpreted along with SPI2_SMART_IDLE_WAKEUP SPI2_SMART_IDLE_WAKEUP_RAW, SPI2_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
pub type WakeupRawR = crate :: BitReader ; # [doc = "Field `wakeup_raw` writer - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI2 module. This should be interpreted along with SPI2_SMART_IDLE_WAKEUP SPI2_SMART_IDLE_WAKEUP_RAW, SPI2_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
pub type WakeupRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI2 module. 0 => Disable Smart IDLE mode for SPI2"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1 => SPI2 in smart idle mode 0 => SPI2 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
pub fn ack (& self) -> AckR { AckR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
# [inline (always)]
pub fn auto_en (& self) -> AutoEnR { AutoEnR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
pub fn wakeup (& self) -> WakeupR { WakeupR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI2) module. This should be interpreted along with SPI2_SMART_IDLE_ACK SPI2_SMART_IDLE_ACK_RAW, SPI2_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
# [inline (always)]
pub fn ack_raw (& self) -> AckRawR { AckRawR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI2 module. This should be interpreted along with SPI2_SMART_IDLE_WAKEUP SPI2_SMART_IDLE_WAKEUP_RAW, SPI2_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
# [inline (always)]
pub fn wakeup_raw (& self) -> WakeupRawR { WakeupRawR :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, request the clock gating of SPI2 module. 0 => Disable Smart IDLE mode for SPI2"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < Spi2SmartIdleSpec > { EnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1 => SPI2 in smart idle mode 0 => SPI2 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
# [must_use]
pub fn ack (& mut self) -> AckW < Spi2SmartIdleSpec > { AckW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
# [inline (always)]
# [must_use]
pub fn auto_en (& mut self) -> AutoEnW < Spi2SmartIdleSpec > { AutoEnW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
# [must_use]
pub fn wakeup (& mut self) -> WakeupW < Spi2SmartIdleSpec > { WakeupW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Description: RAW status of CLKSTOP_ACK from McSPI (SPI2) module. This should be interpreted along with SPI2_SMART_IDLE_ACK SPI2_SMART_IDLE_ACK_RAW, SPI2_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
# [inline (always)]
# [must_use]
pub fn ack_raw (& mut self) -> AckRawW < Spi2SmartIdleSpec > { AckRawW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from SPI2 module. This should be interpreted along with SPI2_SMART_IDLE_WAKEUP SPI2_SMART_IDLE_WAKEUP_RAW, SPI2_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
# [inline (always)]
# [must_use]
pub fn wakeup_raw (& mut self) -> WakeupRawW < Spi2SmartIdleSpec > { WakeupRawW :: new (self , 5) } } # [doc = "SPI2_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`spi2_smart_idle::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi2_smart_idle::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Spi2SmartIdleSpec ; impl crate :: RegisterSpec for Spi2SmartIdleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi2_smart_idle::R`](R) reader structure"]
impl crate :: Readable for Spi2SmartIdleSpec { } # [doc = "`write(|w| ..)` method takes [`spi2_smart_idle::W`](W) writer structure"]
impl crate :: Writable for Spi2SmartIdleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI2_SMART_IDLE to value 0"]
impl crate :: Resettable for Spi2SmartIdleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CAN_SMART_IDLE (rw) register accessor: CAN_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`can_smart_idle::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`can_smart_idle::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can_smart_idle`]
module"]
# [doc (alias = "CAN_SMART_IDLE")]
pub type CanSmartIdle = crate :: Reg < can_smart_idle :: CanSmartIdleSpec > ; # [doc = "CAN_SMART_IDLE"]
pub mod can_smart_idle { # [doc = "Register `CAN_SMART_IDLE` reader"]
pub type R = crate :: R < CanSmartIdleSpec > ; # [doc = "Register `CAN_SMART_IDLE` writer"]
pub type W = crate :: W < CanSmartIdleSpec > ; # [doc = "Field `enable` reader - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of CAN module.0 => Disable Smart IDLE mode for CAN"]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of CAN module.0 => Disable Smart IDLE mode for CAN"]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack` reader - 1:1\\]
1 => CAN in smart idle mode0 => CAN not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type AckR = crate :: BitReader ; # [doc = "Field `ack` writer - 1:1\\]
1 => CAN in smart idle mode0 => CAN not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type AckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `auto_en` reader - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
pub type AutoEnR = crate :: BitReader ; # [doc = "Field `auto_en` writer - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
pub type AutoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup` reader - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type WakeupR = crate :: BitReader ; # [doc = "Field `wakeup` writer - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
pub type WakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack_raw` reader - 4:4\\]
Description: RAW status of CLKSTOP_ACK from CANFD module. This should be interpreted along with CAN_SMART_IDLE_ACK CAN_SMART_IDLE_ACK_RAW, CAN_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
pub type AckRawR = crate :: BitReader ; # [doc = "Field `ack_raw` writer - 4:4\\]
Description: RAW status of CLKSTOP_ACK from CANFD module. This should be interpreted along with CAN_SMART_IDLE_ACK CAN_SMART_IDLE_ACK_RAW, CAN_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
pub type AckRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_raw` reader - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from CANFD module. This should be interpreted along with CAN_SMART_IDLE_WAKEUP CAN_SMART_IDLE_WAKEUP_RAW, CAN_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
pub type WakeupRawR = crate :: BitReader ; # [doc = "Field `wakeup_raw` writer - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from CANFD module. This should be interpreted along with CAN_SMART_IDLE_WAKEUP CAN_SMART_IDLE_WAKEUP_RAW, CAN_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
pub type WakeupRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of CAN module.0 => Disable Smart IDLE mode for CAN"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1 => CAN in smart idle mode0 => CAN not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
pub fn ack (& self) -> AckR { AckR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
# [inline (always)]
pub fn auto_en (& self) -> AutoEnR { AutoEnR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
pub fn wakeup (& self) -> WakeupR { WakeupR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Description: RAW status of CLKSTOP_ACK from CANFD module. This should be interpreted along with CAN_SMART_IDLE_ACK CAN_SMART_IDLE_ACK_RAW, CAN_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
# [inline (always)]
pub fn ack_raw (& self) -> AckRawR { AckRawR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from CANFD module. This should be interpreted along with CAN_SMART_IDLE_WAKEUP CAN_SMART_IDLE_WAKEUP_RAW, CAN_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
# [inline (always)]
pub fn wakeup_raw (& self) -> WakeupRawR { WakeupRawR :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of CAN module.0 => Disable Smart IDLE mode for CAN"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < CanSmartIdleSpec > { EnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1 => CAN in smart idle mode0 => CAN not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
# [must_use]
pub fn ack (& mut self) -> AckW < CanSmartIdleSpec > { AckW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP"]
# [inline (always)]
# [must_use]
pub fn auto_en (& mut self) -> AutoEnW < CanSmartIdleSpec > { AutoEnW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear."]
# [inline (always)]
# [must_use]
pub fn wakeup (& mut self) -> WakeupW < CanSmartIdleSpec > { WakeupW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Description: RAW status of CLKSTOP_ACK from CANFD module. This should be interpreted along with CAN_SMART_IDLE_ACK CAN_SMART_IDLE_ACK_RAW, CAN_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status"]
# [inline (always)]
# [must_use]
pub fn ack_raw (& mut self) -> AckRawW < CanSmartIdleSpec > { AckRawW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Description: RAW status of CLKSTOP_WAKEUP from CANFD module. This should be interpreted along with CAN_SMART_IDLE_WAKEUP CAN_SMART_IDLE_WAKEUP_RAW, CAN_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status"]
# [inline (always)]
# [must_use]
pub fn wakeup_raw (& mut self) -> WakeupRawW < CanSmartIdleSpec > { WakeupRawW :: new (self , 5) } } # [doc = "CAN_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`can_smart_idle::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`can_smart_idle::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CanSmartIdleSpec ; impl crate :: RegisterSpec for CanSmartIdleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`can_smart_idle::R`](R) reader structure"]
impl crate :: Readable for CanSmartIdleSpec { } # [doc = "`write(|w| ..)` method takes [`can_smart_idle::W`](W) writer structure"]
impl crate :: Writable for CanSmartIdleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CAN_SMART_IDLE to value 0"]
impl crate :: Resettable for CanSmartIdleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LIN_SMART_IDLE (rw) register accessor: LIN_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`lin_smart_idle::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lin_smart_idle::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lin_smart_idle`]
module"]
# [doc (alias = "LIN_SMART_IDLE")]
pub type LinSmartIdle = crate :: Reg < lin_smart_idle :: LinSmartIdleSpec > ; # [doc = "LIN_SMART_IDLE"]
pub mod lin_smart_idle { # [doc = "Register `LIN_SMART_IDLE` reader"]
pub type R = crate :: R < LinSmartIdleSpec > ; # [doc = "Register `LIN_SMART_IDLE` writer"]
pub type W = crate :: W < LinSmartIdleSpec > ; # [doc = "Field `enable` reader - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of LIN module.0 => Disable Smart IDLE mode for LIN"]
pub type EnableR = crate :: BitReader ; # [doc = "Field `enable` writer - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of LIN module.0 => Disable Smart IDLE mode for LIN"]
pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ack` reader - 1:1\\]
1 => LIN in smart idle mode0 => LIN not in smart idle mode"]
pub type AckR = crate :: BitReader ; # [doc = "Field `ack` writer - 1:1\\]
1 => LIN in smart idle mode0 => LIN not in smart idle mode"]
pub type AckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of LIN module.0 => Disable Smart IDLE mode for LIN"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
1 => LIN in smart idle mode0 => LIN not in smart idle mode"]
# [inline (always)]
pub fn ack (& self) -> AckR { AckR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 => Smart IDLE mode enabled. When set, Request the clock gating of LIN module.0 => Disable Smart IDLE mode for LIN"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < LinSmartIdleSpec > { EnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
1 => LIN in smart idle mode0 => LIN not in smart idle mode"]
# [inline (always)]
# [must_use]
pub fn ack (& mut self) -> AckW < LinSmartIdleSpec > { AckW :: new (self , 1) } } # [doc = "LIN_SMART_IDLE\n\nYou can [`read`](crate::Reg::read) this register and get [`lin_smart_idle::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lin_smart_idle::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LinSmartIdleSpec ; impl crate :: RegisterSpec for LinSmartIdleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`lin_smart_idle::R`](R) reader structure"]
impl crate :: Readable for LinSmartIdleSpec { } # [doc = "`write(|w| ..)` method takes [`lin_smart_idle::W`](W) writer structure"]
impl crate :: Writable for LinSmartIdleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LIN_SMART_IDLE to value 0"]
impl crate :: Resettable for LinSmartIdleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_CLK_GATE (rw) register accessor: HWASS_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_clk_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_clk_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_clk_gate`]
module"]
# [doc (alias = "HWASS_CLK_GATE")]
pub type HwassClkGate = crate :: Reg < hwass_clk_gate :: HwassClkGateSpec > ; # [doc = "HWASS_CLK_GATE"]
pub mod hwass_clk_gate { # [doc = "Register `HWASS_CLK_GATE` reader"]
pub type R = crate :: R < HwassClkGateSpec > ; # [doc = "Register `HWASS_CLK_GATE` writer"]
pub type W = crate :: W < HwassClkGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
RESERVED"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
RESERVED"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
RESERVED"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
RESERVED"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < HwassClkGateSpec > { EnableW :: new (self , 0) } } # [doc = "HWASS_CLK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassClkGateSpec ; impl crate :: RegisterSpec for HwassClkGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_clk_gate::R`](R) reader structure"]
impl crate :: Readable for HwassClkGateSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_clk_gate::W`](W) writer structure"]
impl crate :: Writable for HwassClkGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_CLK_GATE to value 0"]
impl crate :: Resettable for HwassClkGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFG_TIMEOUT_PCR3 (rw) register accessor: CFG_TIMEOUT_PCR3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_timeout_pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_timeout_pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_timeout_pcr3`]
module"]
# [doc (alias = "CFG_TIMEOUT_PCR3")]
pub type CfgTimeoutPcr3 = crate :: Reg < cfg_timeout_pcr3 :: CfgTimeoutPcr3Spec > ; # [doc = "CFG_TIMEOUT_PCR3"]
pub mod cfg_timeout_pcr3 { # [doc = "Register `CFG_TIMEOUT_PCR3` reader"]
pub type R = crate :: R < CfgTimeoutPcr3Spec > ; # [doc = "Register `CFG_TIMEOUT_PCR3` writer"]
pub type W = crate :: W < CfgTimeoutPcr3Spec > ; # [doc = "Field `value` reader - 31:0\\]
PCR3Timeout Value"]
pub type ValueR = crate :: FieldReader < u32 > ; # [doc = "Field `value` writer - 31:0\\]
PCR3Timeout Value"]
pub type ValueW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
PCR3Timeout Value"]
# [inline (always)]
pub fn value (& self) -> ValueR { ValueR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
PCR3Timeout Value"]
# [inline (always)]
# [must_use]
pub fn value (& mut self) -> ValueW < CfgTimeoutPcr3Spec > { ValueW :: new (self , 0) } } # [doc = "CFG_TIMEOUT_PCR3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_timeout_pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_timeout_pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgTimeoutPcr3Spec ; impl crate :: RegisterSpec for CfgTimeoutPcr3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg_timeout_pcr3::R`](R) reader structure"]
impl crate :: Readable for CfgTimeoutPcr3Spec { } # [doc = "`write(|w| ..)` method takes [`cfg_timeout_pcr3::W`](W) writer structure"]
impl crate :: Writable for CfgTimeoutPcr3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFG_TIMEOUT_PCR3 to value 0"]
impl crate :: Resettable for CfgTimeoutPcr3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED0 (rw) register accessor: RESERVED0\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved0`]
module"]
# [doc (alias = "RESERVED0")]
pub type Reserved0 = crate :: Reg < reserved0 :: Reserved0Spec > ; # [doc = "RESERVED0"]
pub mod reserved0 { # [doc = "Register `RESERVED0` reader"]
pub type R = crate :: R < Reserved0Spec > ; # [doc = "Register `RESERVED0` writer"]
pub type W = crate :: W < Reserved0Spec > ; impl W { } # [doc = "RESERVED0\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved0Spec ; impl crate :: RegisterSpec for Reserved0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved0::R`](R) reader structure"]
impl crate :: Readable for Reserved0Spec { } # [doc = "`write(|w| ..)` method takes [`reserved0::W`](W) writer structure"]
impl crate :: Writable for Reserved0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED0 to value 0"]
impl crate :: Resettable for Reserved0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_ERRAGG_MASK1 (rw) register accessor: APPSS_ERRAGG_MASK1\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_mask1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_mask1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_erragg_mask1`]
module"]
# [doc (alias = "APPSS_ERRAGG_MASK1")]
pub type AppssErraggMask1 = crate :: Reg < appss_erragg_mask1 :: AppssErraggMask1Spec > ; # [doc = "APPSS_ERRAGG_MASK1"]
pub mod appss_erragg_mask1 { # [doc = "Register `APPSS_ERRAGG_MASK1` reader"]
pub type R = crate :: R < AppssErraggMask1Spec > ; # [doc = "Register `APPSS_ERRAGG_MASK1` writer"]
pub type W = crate :: W < AppssErraggMask1Spec > ; # [doc = "Field `cluster1_power_down_access_err` reader - 0:0\\]
Mask Interrupt from cluster1_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster1PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster1_power_down_access_err` writer - 0:0\\]
Mask Interrupt from cluster1_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster1PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster2_power_down_access_err` reader - 1:1\\]
Mask Interrupt from cluster2_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster2PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster2_power_down_access_err` writer - 1:1\\]
Mask Interrupt from cluster2_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster2PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster3_power_down_access_err` reader - 2:2\\]
Mask Interrupt from cluster3_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster3PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster3_power_down_access_err` writer - 2:2\\]
Mask Interrupt from cluster3_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster3PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster4_power_down_access_err` reader - 3:3\\]
Mask Interrupt from cluster4_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster4PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster4_power_down_access_err` writer - 3:3\\]
Mask Interrupt from cluster4_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster4PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster5_power_down_access_err` reader - 4:4\\]
Mask Interrupt from cluster5_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster5PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster5_power_down_access_err` writer - 4:4\\]
Mask Interrupt from cluster5_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster5PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster6_power_down_access_err` reader - 5:5\\]
Mask Interrupt from cluster6_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster6PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster6_power_down_access_err` writer - 5:5\\]
Mask Interrupt from cluster6_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster6PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster7_power_down_access_err` reader - 6:6\\]
Mask Interrupt from cluster7_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster7PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster7_power_down_access_err` writer - 6:6\\]
Mask Interrupt from cluster7_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster7PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster8_power_down_access_err` reader - 7:7\\]
Mask Interrupt from cluster8_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster8PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster8_power_down_access_err` writer - 7:7\\]
Mask Interrupt from cluster8_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster8PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster9_power_down_access_err` reader - 8:8\\]
Mask Interrupt from cluster9_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster9PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster9_power_down_access_err` writer - 8:8\\]
Mask Interrupt from cluster9_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster9PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster10_power_down_access_err` reader - 9:9\\]
Mask Interrupt from cluster10_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster10PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster10_power_down_access_err` writer - 9:9\\]
Mask Interrupt from cluster10_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster10PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster11_power_down_access_err` reader - 10:10\\]
Mask Interrupt from cluster11_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster11PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster11_power_down_access_err` writer - 10:10\\]
Mask Interrupt from cluster11_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster11PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster12_power_down_access_err` reader - 11:11\\]
Mask Interrupt from cluster12_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster12PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster12_power_down_access_err` writer - 11:11\\]
Mask Interrupt from cluster12_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
pub type Cluster12PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from cluster1_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster1_power_down_access_err (& self) -> Cluster1PowerDownAccessErrR { Cluster1PowerDownAccessErrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from cluster2_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster2_power_down_access_err (& self) -> Cluster2PowerDownAccessErrR { Cluster2PowerDownAccessErrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from cluster3_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster3_power_down_access_err (& self) -> Cluster3PowerDownAccessErrR { Cluster3PowerDownAccessErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from cluster4_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster4_power_down_access_err (& self) -> Cluster4PowerDownAccessErrR { Cluster4PowerDownAccessErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from cluster5_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster5_power_down_access_err (& self) -> Cluster5PowerDownAccessErrR { Cluster5PowerDownAccessErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from cluster6_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster6_power_down_access_err (& self) -> Cluster6PowerDownAccessErrR { Cluster6PowerDownAccessErrR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from cluster7_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster7_power_down_access_err (& self) -> Cluster7PowerDownAccessErrR { Cluster7PowerDownAccessErrR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from cluster8_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster8_power_down_access_err (& self) -> Cluster8PowerDownAccessErrR { Cluster8PowerDownAccessErrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from cluster9_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster9_power_down_access_err (& self) -> Cluster9PowerDownAccessErrR { Cluster9PowerDownAccessErrR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Mask Interrupt from cluster10_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster10_power_down_access_err (& self) -> Cluster10PowerDownAccessErrR { Cluster10PowerDownAccessErrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Mask Interrupt from cluster11_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster11_power_down_access_err (& self) -> Cluster11PowerDownAccessErrR { Cluster11PowerDownAccessErrR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Mask Interrupt from cluster12_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
pub fn cluster12_power_down_access_err (& self) -> Cluster12PowerDownAccessErrR { Cluster12PowerDownAccessErrR :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Mask Interrupt from cluster1_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster1_power_down_access_err (& mut self) -> Cluster1PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster1PowerDownAccessErrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Mask Interrupt from cluster2_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster2_power_down_access_err (& mut self) -> Cluster2PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster2PowerDownAccessErrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Mask Interrupt from cluster3_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster3_power_down_access_err (& mut self) -> Cluster3PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster3PowerDownAccessErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Mask Interrupt from cluster4_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster4_power_down_access_err (& mut self) -> Cluster4PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster4PowerDownAccessErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Mask Interrupt from cluster5_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster5_power_down_access_err (& mut self) -> Cluster5PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster5PowerDownAccessErrW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Mask Interrupt from cluster6_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster6_power_down_access_err (& mut self) -> Cluster6PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster6PowerDownAccessErrW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Mask Interrupt from cluster7_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster7_power_down_access_err (& mut self) -> Cluster7PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster7PowerDownAccessErrW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Mask Interrupt from cluster8_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster8_power_down_access_err (& mut self) -> Cluster8PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster8PowerDownAccessErrW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Mask Interrupt from cluster9_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster9_power_down_access_err (& mut self) -> Cluster9PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster9PowerDownAccessErrW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Mask Interrupt from cluster10_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster10_power_down_access_err (& mut self) -> Cluster10PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster10PowerDownAccessErrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Mask Interrupt from cluster11_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster11_power_down_access_err (& mut self) -> Cluster11PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster11PowerDownAccessErrW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Mask Interrupt from cluster12_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
# [inline (always)]
# [must_use]
pub fn cluster12_power_down_access_err (& mut self) -> Cluster12PowerDownAccessErrW < AppssErraggMask1Spec > { Cluster12PowerDownAccessErrW :: new (self , 11) } } # [doc = "APPSS_ERRAGG_MASK1\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_mask1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_mask1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssErraggMask1Spec ; impl crate :: RegisterSpec for AppssErraggMask1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_erragg_mask1::R`](R) reader structure"]
impl crate :: Readable for AppssErraggMask1Spec { } # [doc = "`write(|w| ..)` method takes [`appss_erragg_mask1::W`](W) writer structure"]
impl crate :: Writable for AppssErraggMask1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_ERRAGG_MASK1 to value 0"]
impl crate :: Resettable for AppssErraggMask1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_ERRAGG_STATUS1 (rw) register accessor: APPSS_ERRAGG_STATUS1\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_status1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_status1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_erragg_status1`]
module"]
# [doc (alias = "APPSS_ERRAGG_STATUS1")]
pub type AppssErraggStatus1 = crate :: Reg < appss_erragg_status1 :: AppssErraggStatus1Spec > ; # [doc = "APPSS_ERRAGG_STATUS1"]
pub mod appss_erragg_status1 { # [doc = "Register `APPSS_ERRAGG_STATUS1` reader"]
pub type R = crate :: R < AppssErraggStatus1Spec > ; # [doc = "Register `APPSS_ERRAGG_STATUS1` writer"]
pub type W = crate :: W < AppssErraggStatus1Spec > ; # [doc = "Field `cluster1_power_down_access_err` reader - 0:0\\]
Status of Interrupt from cluster1_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster1PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster1_power_down_access_err` writer - 0:0\\]
Status of Interrupt from cluster1_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster1PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster2_power_down_access_err` reader - 1:1\\]
Status of Interrupt from cluster2_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster2PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster2_power_down_access_err` writer - 1:1\\]
Status of Interrupt from cluster2_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster2PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster3_power_down_access_err` reader - 2:2\\]
Status of Interrupt from cluster3_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster3PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster3_power_down_access_err` writer - 2:2\\]
Status of Interrupt from cluster3_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster3PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster4_power_down_access_err` reader - 3:3\\]
Status of Interrupt from cluster4_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster4PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster4_power_down_access_err` writer - 3:3\\]
Status of Interrupt from cluster4_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster4PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster5_power_down_access_err` reader - 4:4\\]
Status of Interrupt from cluster5_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster5PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster5_power_down_access_err` writer - 4:4\\]
Status of Interrupt from cluster5_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster5PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster6_power_down_access_err` reader - 5:5\\]
Status of Interrupt from cluster6_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster6PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster6_power_down_access_err` writer - 5:5\\]
Status of Interrupt from cluster6_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster6PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster7_power_down_access_err` reader - 6:6\\]
Status of Interrupt from cluster7_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster7PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster7_power_down_access_err` writer - 6:6\\]
Status of Interrupt from cluster7_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster7PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster8_power_down_access_err` reader - 7:7\\]
Status of Interrupt from cluster8_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster8PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster8_power_down_access_err` writer - 7:7\\]
Status of Interrupt from cluster8_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster8PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster9_power_down_access_err` reader - 8:8\\]
Status of Interrupt from cluster9_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster9PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster9_power_down_access_err` writer - 8:8\\]
Status of Interrupt from cluster9_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster9PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster10_power_down_access_err` reader - 9:9\\]
Status of Interrupt from cluster10_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster10PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster10_power_down_access_err` writer - 9:9\\]
Status of Interrupt from cluster10_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster10PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster11_power_down_access_err` reader - 10:10\\]
Status of Interrupt from cluster11_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster11PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster11_power_down_access_err` writer - 10:10\\]
Status of Interrupt from cluster11_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster11PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cluster12_power_down_access_err` reader - 11:11\\]
Status of Interrupt from cluster12_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster12PowerDownAccessErrR = crate :: BitReader ; # [doc = "Field `cluster12_power_down_access_err` writer - 11:11\\]
Status of Interrupt from cluster12_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
pub type Cluster12PowerDownAccessErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from cluster1_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster1_power_down_access_err (& self) -> Cluster1PowerDownAccessErrR { Cluster1PowerDownAccessErrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from cluster2_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster2_power_down_access_err (& self) -> Cluster2PowerDownAccessErrR { Cluster2PowerDownAccessErrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from cluster3_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster3_power_down_access_err (& self) -> Cluster3PowerDownAccessErrR { Cluster3PowerDownAccessErrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from cluster4_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster4_power_down_access_err (& self) -> Cluster4PowerDownAccessErrR { Cluster4PowerDownAccessErrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from cluster5_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster5_power_down_access_err (& self) -> Cluster5PowerDownAccessErrR { Cluster5PowerDownAccessErrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from cluster6_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster6_power_down_access_err (& self) -> Cluster6PowerDownAccessErrR { Cluster6PowerDownAccessErrR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from cluster7_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster7_power_down_access_err (& self) -> Cluster7PowerDownAccessErrR { Cluster7PowerDownAccessErrR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from cluster8_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster8_power_down_access_err (& self) -> Cluster8PowerDownAccessErrR { Cluster8PowerDownAccessErrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from cluster9_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster9_power_down_access_err (& self) -> Cluster9PowerDownAccessErrR { Cluster9PowerDownAccessErrR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Status of Interrupt from cluster10_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster10_power_down_access_err (& self) -> Cluster10PowerDownAccessErrR { Cluster10PowerDownAccessErrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Status of Interrupt from cluster11_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster11_power_down_access_err (& self) -> Cluster11PowerDownAccessErrR { Cluster11PowerDownAccessErrR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Status of Interrupt from cluster12_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
pub fn cluster12_power_down_access_err (& self) -> Cluster12PowerDownAccessErrR { Cluster12PowerDownAccessErrR :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Status of Interrupt from cluster1_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster1_power_down_access_err (& mut self) -> Cluster1PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster1PowerDownAccessErrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Status of Interrupt from cluster2_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster2_power_down_access_err (& mut self) -> Cluster2PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster2PowerDownAccessErrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Status of Interrupt from cluster3_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster3_power_down_access_err (& mut self) -> Cluster3PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster3PowerDownAccessErrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Status of Interrupt from cluster4_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster4_power_down_access_err (& mut self) -> Cluster4PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster4PowerDownAccessErrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Status of Interrupt from cluster5_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster5_power_down_access_err (& mut self) -> Cluster5PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster5PowerDownAccessErrW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Status of Interrupt from cluster6_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster6_power_down_access_err (& mut self) -> Cluster6PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster6PowerDownAccessErrW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Status of Interrupt from cluster7_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster7_power_down_access_err (& mut self) -> Cluster7PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster7PowerDownAccessErrW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Status of Interrupt from cluster8_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster8_power_down_access_err (& mut self) -> Cluster8PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster8PowerDownAccessErrW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Status of Interrupt from cluster9_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster9_power_down_access_err (& mut self) -> Cluster9PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster9PowerDownAccessErrW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Status of Interrupt from cluster10_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster10_power_down_access_err (& mut self) -> Cluster10PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster10PowerDownAccessErrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Status of Interrupt from cluster11_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster11_power_down_access_err (& mut self) -> Cluster11PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster11PowerDownAccessErrW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Status of Interrupt from cluster12_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt."]
# [inline (always)]
# [must_use]
pub fn cluster12_power_down_access_err (& mut self) -> Cluster12PowerDownAccessErrW < AppssErraggStatus1Spec > { Cluster12PowerDownAccessErrW :: new (self , 11) } } # [doc = "APPSS_ERRAGG_STATUS1\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_erragg_status1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_erragg_status1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssErraggStatus1Spec ; impl crate :: RegisterSpec for AppssErraggStatus1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_erragg_status1::R`](R) reader structure"]
impl crate :: Readable for AppssErraggStatus1Spec { } # [doc = "`write(|w| ..)` method takes [`appss_erragg_status1::W`](W) writer structure"]
impl crate :: Writable for AppssErraggStatus1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_ERRAGG_STATUS1 to value 0"]
impl crate :: Resettable for AppssErraggStatus1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FORCEHCLKACTIVE (rw) register accessor: FORCEHCLKACTIVE\n\nYou can [`read`](crate::Reg::read) this register and get [`forcehclkactive::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`forcehclkactive::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@forcehclkactive`]
module"]
# [doc (alias = "FORCEHCLKACTIVE")]
pub type Forcehclkactive = crate :: Reg < forcehclkactive :: ForcehclkactiveSpec > ; # [doc = "FORCEHCLKACTIVE"]
pub mod forcehclkactive { # [doc = "Register `FORCEHCLKACTIVE` reader"]
pub type R = crate :: R < ForcehclkactiveSpec > ; # [doc = "Register `FORCEHCLKACTIVE` writer"]
pub type W = crate :: W < ForcehclkactiveSpec > ; # [doc = "Field `forcehclkactive` reader - 0:0\\]
1 :> Gate HCLK 0 :> UnGate HCLK"]
pub type ForcehclkactiveR = crate :: BitReader ; # [doc = "Field `forcehclkactive` writer - 0:0\\]
1 :> Gate HCLK 0 :> UnGate HCLK"]
pub type ForcehclkactiveW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1 :> Gate HCLK 0 :> UnGate HCLK"]
# [inline (always)]
pub fn forcehclkactive (& self) -> ForcehclkactiveR { ForcehclkactiveR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1 :> Gate HCLK 0 :> UnGate HCLK"]
# [inline (always)]
# [must_use]
pub fn forcehclkactive (& mut self) -> ForcehclkactiveW < ForcehclkactiveSpec > { ForcehclkactiveW :: new (self , 0) } } # [doc = "FORCEHCLKACTIVE\n\nYou can [`read`](crate::Reg::read) this register and get [`forcehclkactive::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`forcehclkactive::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ForcehclkactiveSpec ; impl crate :: RegisterSpec for ForcehclkactiveSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`forcehclkactive::R`](R) reader structure"]
impl crate :: Readable for ForcehclkactiveSpec { } # [doc = "`write(|w| ..)` method takes [`forcehclkactive::W`](W) writer structure"]
impl crate :: Writable for ForcehclkactiveSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FORCEHCLKACTIVE to value 0"]
impl crate :: Resettable for ForcehclkactiveSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM1_OWRITE_ERR (rw) register accessor: APPSS_RAM1_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1_owrite_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1_owrite_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram1_owrite_err`]
module"]
# [doc (alias = "APPSS_RAM1_OWRITE_ERR")]
pub type AppssRam1OwriteErr = crate :: Reg < appss_ram1_owrite_err :: AppssRam1OwriteErrSpec > ; # [doc = "APPSS_RAM1_OWRITE_ERR"]
pub mod appss_ram1_owrite_err { # [doc = "Register `APPSS_RAM1_OWRITE_ERR` reader"]
pub type R = crate :: R < AppssRam1OwriteErrSpec > ; # [doc = "Register `APPSS_RAM1_OWRITE_ERR` writer"]
pub type W = crate :: W < AppssRam1OwriteErrSpec > ; # [doc = "Field `err` reader - 0:0\\]
RAM1 ahb2sram write error - Sticky Bit"]
pub type ErrR = crate :: BitReader ; # [doc = "Field `err` writer - 0:0\\]
RAM1 ahb2sram write error - Sticky Bit"]
pub type ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RAM1 ahb2sram write error - Sticky Bit"]
# [inline (always)]
pub fn err (& self) -> ErrR { ErrR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RAM1 ahb2sram write error - Sticky Bit"]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ErrW < AppssRam1OwriteErrSpec > { ErrW :: new (self , 0) } } # [doc = "APPSS_RAM1_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1_owrite_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1_owrite_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam1OwriteErrSpec ; impl crate :: RegisterSpec for AppssRam1OwriteErrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram1_owrite_err::R`](R) reader structure"]
impl crate :: Readable for AppssRam1OwriteErrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram1_owrite_err::W`](W) writer structure"]
impl crate :: Writable for AppssRam1OwriteErrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM1_OWRITE_ERR to value 0"]
impl crate :: Resettable for AppssRam1OwriteErrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM1_OWRITE_ERR_ADDR (rw) register accessor: APPSS_RAM1_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1_owrite_err_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1_owrite_err_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram1_owrite_err_addr`]
module"]
# [doc (alias = "APPSS_RAM1_OWRITE_ERR_ADDR")]
pub type AppssRam1OwriteErrAddr = crate :: Reg < appss_ram1_owrite_err_addr :: AppssRam1OwriteErrAddrSpec > ; # [doc = "APPSS_RAM1_OWRITE_ERR_ADDR"]
pub mod appss_ram1_owrite_err_addr { # [doc = "Register `APPSS_RAM1_OWRITE_ERR_ADDR` reader"]
pub type R = crate :: R < AppssRam1OwriteErrAddrSpec > ; # [doc = "Register `APPSS_RAM1_OWRITE_ERR_ADDR` writer"]
pub type W = crate :: W < AppssRam1OwriteErrAddrSpec > ; # [doc = "Field `address` reader - 31:0\\]
RAM1 ahb2sram write error Address"]
pub type AddressR = crate :: FieldReader < u32 > ; # [doc = "Field `address` writer - 31:0\\]
RAM1 ahb2sram write error Address"]
pub type AddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
RAM1 ahb2sram write error Address"]
# [inline (always)]
pub fn address (& self) -> AddressR { AddressR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
RAM1 ahb2sram write error Address"]
# [inline (always)]
# [must_use]
pub fn address (& mut self) -> AddressW < AppssRam1OwriteErrAddrSpec > { AddressW :: new (self , 0) } } # [doc = "APPSS_RAM1_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram1_owrite_err_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram1_owrite_err_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam1OwriteErrAddrSpec ; impl crate :: RegisterSpec for AppssRam1OwriteErrAddrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram1_owrite_err_addr::R`](R) reader structure"]
impl crate :: Readable for AppssRam1OwriteErrAddrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram1_owrite_err_addr::W`](W) writer structure"]
impl crate :: Writable for AppssRam1OwriteErrAddrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM1_OWRITE_ERR_ADDR to value 0"]
impl crate :: Resettable for AppssRam1OwriteErrAddrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM2_OWRITE_ERR (rw) register accessor: APPSS_RAM2_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2_owrite_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2_owrite_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram2_owrite_err`]
module"]
# [doc (alias = "APPSS_RAM2_OWRITE_ERR")]
pub type AppssRam2OwriteErr = crate :: Reg < appss_ram2_owrite_err :: AppssRam2OwriteErrSpec > ; # [doc = "APPSS_RAM2_OWRITE_ERR"]
pub mod appss_ram2_owrite_err { # [doc = "Register `APPSS_RAM2_OWRITE_ERR` reader"]
pub type R = crate :: R < AppssRam2OwriteErrSpec > ; # [doc = "Register `APPSS_RAM2_OWRITE_ERR` writer"]
pub type W = crate :: W < AppssRam2OwriteErrSpec > ; # [doc = "Field `err` reader - 0:0\\]
RAM2 ahb2sram write error - Sticky Bit"]
pub type ErrR = crate :: BitReader ; # [doc = "Field `err` writer - 0:0\\]
RAM2 ahb2sram write error - Sticky Bit"]
pub type ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RAM2 ahb2sram write error - Sticky Bit"]
# [inline (always)]
pub fn err (& self) -> ErrR { ErrR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RAM2 ahb2sram write error - Sticky Bit"]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ErrW < AppssRam2OwriteErrSpec > { ErrW :: new (self , 0) } } # [doc = "APPSS_RAM2_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2_owrite_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2_owrite_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam2OwriteErrSpec ; impl crate :: RegisterSpec for AppssRam2OwriteErrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram2_owrite_err::R`](R) reader structure"]
impl crate :: Readable for AppssRam2OwriteErrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram2_owrite_err::W`](W) writer structure"]
impl crate :: Writable for AppssRam2OwriteErrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM2_OWRITE_ERR to value 0"]
impl crate :: Resettable for AppssRam2OwriteErrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM2_OWRITE_ERR_ADDR (rw) register accessor: APPSS_RAM2_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2_owrite_err_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2_owrite_err_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram2_owrite_err_addr`]
module"]
# [doc (alias = "APPSS_RAM2_OWRITE_ERR_ADDR")]
pub type AppssRam2OwriteErrAddr = crate :: Reg < appss_ram2_owrite_err_addr :: AppssRam2OwriteErrAddrSpec > ; # [doc = "APPSS_RAM2_OWRITE_ERR_ADDR"]
pub mod appss_ram2_owrite_err_addr { # [doc = "Register `APPSS_RAM2_OWRITE_ERR_ADDR` reader"]
pub type R = crate :: R < AppssRam2OwriteErrAddrSpec > ; # [doc = "Register `APPSS_RAM2_OWRITE_ERR_ADDR` writer"]
pub type W = crate :: W < AppssRam2OwriteErrAddrSpec > ; # [doc = "Field `address` reader - 31:0\\]
RAM2 ahb2sram write error Address"]
pub type AddressR = crate :: FieldReader < u32 > ; # [doc = "Field `address` writer - 31:0\\]
RAM2 ahb2sram write error Address"]
pub type AddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
RAM2 ahb2sram write error Address"]
# [inline (always)]
pub fn address (& self) -> AddressR { AddressR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
RAM2 ahb2sram write error Address"]
# [inline (always)]
# [must_use]
pub fn address (& mut self) -> AddressW < AppssRam2OwriteErrAddrSpec > { AddressW :: new (self , 0) } } # [doc = "APPSS_RAM2_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram2_owrite_err_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram2_owrite_err_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam2OwriteErrAddrSpec ; impl crate :: RegisterSpec for AppssRam2OwriteErrAddrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram2_owrite_err_addr::R`](R) reader structure"]
impl crate :: Readable for AppssRam2OwriteErrAddrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram2_owrite_err_addr::W`](W) writer structure"]
impl crate :: Writable for AppssRam2OwriteErrAddrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM2_OWRITE_ERR_ADDR to value 0"]
impl crate :: Resettable for AppssRam2OwriteErrAddrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM3_OWRITE_ERR (rw) register accessor: APPSS_RAM3_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3_owrite_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3_owrite_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram3_owrite_err`]
module"]
# [doc (alias = "APPSS_RAM3_OWRITE_ERR")]
pub type AppssRam3OwriteErr = crate :: Reg < appss_ram3_owrite_err :: AppssRam3OwriteErrSpec > ; # [doc = "APPSS_RAM3_OWRITE_ERR"]
pub mod appss_ram3_owrite_err { # [doc = "Register `APPSS_RAM3_OWRITE_ERR` reader"]
pub type R = crate :: R < AppssRam3OwriteErrSpec > ; # [doc = "Register `APPSS_RAM3_OWRITE_ERR` writer"]
pub type W = crate :: W < AppssRam3OwriteErrSpec > ; # [doc = "Field `err` reader - 0:0\\]
RAM3 ahb2sram write error - Sticky Bit"]
pub type ErrR = crate :: BitReader ; # [doc = "Field `err` writer - 0:0\\]
RAM3 ahb2sram write error - Sticky Bit"]
pub type ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
RAM3 ahb2sram write error - Sticky Bit"]
# [inline (always)]
pub fn err (& self) -> ErrR { ErrR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
RAM3 ahb2sram write error - Sticky Bit"]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ErrW < AppssRam3OwriteErrSpec > { ErrW :: new (self , 0) } } # [doc = "APPSS_RAM3_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3_owrite_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3_owrite_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam3OwriteErrSpec ; impl crate :: RegisterSpec for AppssRam3OwriteErrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram3_owrite_err::R`](R) reader structure"]
impl crate :: Readable for AppssRam3OwriteErrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram3_owrite_err::W`](W) writer structure"]
impl crate :: Writable for AppssRam3OwriteErrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM3_OWRITE_ERR to value 0"]
impl crate :: Resettable for AppssRam3OwriteErrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_RAM3_OWRITE_ERR_ADDR (rw) register accessor: APPSS_RAM3_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3_owrite_err_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3_owrite_err_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_ram3_owrite_err_addr`]
module"]
# [doc (alias = "APPSS_RAM3_OWRITE_ERR_ADDR")]
pub type AppssRam3OwriteErrAddr = crate :: Reg < appss_ram3_owrite_err_addr :: AppssRam3OwriteErrAddrSpec > ; # [doc = "APPSS_RAM3_OWRITE_ERR_ADDR"]
pub mod appss_ram3_owrite_err_addr { # [doc = "Register `APPSS_RAM3_OWRITE_ERR_ADDR` reader"]
pub type R = crate :: R < AppssRam3OwriteErrAddrSpec > ; # [doc = "Register `APPSS_RAM3_OWRITE_ERR_ADDR` writer"]
pub type W = crate :: W < AppssRam3OwriteErrAddrSpec > ; # [doc = "Field `address` reader - 31:0\\]
RAM3 ahb2sram write error Address"]
pub type AddressR = crate :: FieldReader < u32 > ; # [doc = "Field `address` writer - 31:0\\]
RAM3 ahb2sram write error Address"]
pub type AddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
RAM3 ahb2sram write error Address"]
# [inline (always)]
pub fn address (& self) -> AddressR { AddressR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
RAM3 ahb2sram write error Address"]
# [inline (always)]
# [must_use]
pub fn address (& mut self) -> AddressW < AppssRam3OwriteErrAddrSpec > { AddressW :: new (self , 0) } } # [doc = "APPSS_RAM3_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_ram3_owrite_err_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_ram3_owrite_err_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssRam3OwriteErrAddrSpec ; impl crate :: RegisterSpec for AppssRam3OwriteErrAddrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_ram3_owrite_err_addr::R`](R) reader structure"]
impl crate :: Readable for AppssRam3OwriteErrAddrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_ram3_owrite_err_addr::W`](W) writer structure"]
impl crate :: Writable for AppssRam3OwriteErrAddrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_RAM3_OWRITE_ERR_ADDR to value 0"]
impl crate :: Resettable for AppssRam3OwriteErrAddrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SHRD_RAM_OWRITE_ERR (rw) register accessor: APPSS_SHRD_RAM_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_shrd_ram_owrite_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_shrd_ram_owrite_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_shrd_ram_owrite_err`]
module"]
# [doc (alias = "APPSS_SHRD_RAM_OWRITE_ERR")]
pub type AppssShrdRamOwriteErr = crate :: Reg < appss_shrd_ram_owrite_err :: AppssShrdRamOwriteErrSpec > ; # [doc = "APPSS_SHRD_RAM_OWRITE_ERR"]
pub mod appss_shrd_ram_owrite_err { # [doc = "Register `APPSS_SHRD_RAM_OWRITE_ERR` reader"]
pub type R = crate :: R < AppssShrdRamOwriteErrSpec > ; # [doc = "Register `APPSS_SHRD_RAM_OWRITE_ERR` writer"]
pub type W = crate :: W < AppssShrdRamOwriteErrSpec > ; # [doc = "Field `err` reader - 0:0\\]
SHARED RAM ahb2sram write error - Sticky Bit"]
pub type ErrR = crate :: BitReader ; # [doc = "Field `err` writer - 0:0\\]
SHARED RAM ahb2sram write error - Sticky Bit"]
pub type ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
SHARED RAM ahb2sram write error - Sticky Bit"]
# [inline (always)]
pub fn err (& self) -> ErrR { ErrR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
SHARED RAM ahb2sram write error - Sticky Bit"]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ErrW < AppssShrdRamOwriteErrSpec > { ErrW :: new (self , 0) } } # [doc = "APPSS_SHRD_RAM_OWRITE_ERR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_shrd_ram_owrite_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_shrd_ram_owrite_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssShrdRamOwriteErrSpec ; impl crate :: RegisterSpec for AppssShrdRamOwriteErrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_shrd_ram_owrite_err::R`](R) reader structure"]
impl crate :: Readable for AppssShrdRamOwriteErrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_shrd_ram_owrite_err::W`](W) writer structure"]
impl crate :: Writable for AppssShrdRamOwriteErrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SHRD_RAM_OWRITE_ERR to value 0"]
impl crate :: Resettable for AppssShrdRamOwriteErrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_SHRD_RAM_OWRITE_ERR_ADDR (rw) register accessor: APPSS_SHRD_RAM_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_shrd_ram_owrite_err_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_shrd_ram_owrite_err_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_shrd_ram_owrite_err_addr`]
module"]
# [doc (alias = "APPSS_SHRD_RAM_OWRITE_ERR_ADDR")]
pub type AppssShrdRamOwriteErrAddr = crate :: Reg < appss_shrd_ram_owrite_err_addr :: AppssShrdRamOwriteErrAddrSpec > ; # [doc = "APPSS_SHRD_RAM_OWRITE_ERR_ADDR"]
pub mod appss_shrd_ram_owrite_err_addr { # [doc = "Register `APPSS_SHRD_RAM_OWRITE_ERR_ADDR` reader"]
pub type R = crate :: R < AppssShrdRamOwriteErrAddrSpec > ; # [doc = "Register `APPSS_SHRD_RAM_OWRITE_ERR_ADDR` writer"]
pub type W = crate :: W < AppssShrdRamOwriteErrAddrSpec > ; # [doc = "Field `address` reader - 31:0\\]
SHARED RAM ahb2sram write error Address"]
pub type AddressR = crate :: FieldReader < u32 > ; # [doc = "Field `address` writer - 31:0\\]
SHARED RAM ahb2sram write error Address"]
pub type AddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
SHARED RAM ahb2sram write error Address"]
# [inline (always)]
pub fn address (& self) -> AddressR { AddressR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
SHARED RAM ahb2sram write error Address"]
# [inline (always)]
# [must_use]
pub fn address (& mut self) -> AddressW < AppssShrdRamOwriteErrAddrSpec > { AddressW :: new (self , 0) } } # [doc = "APPSS_SHRD_RAM_OWRITE_ERR_ADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_shrd_ram_owrite_err_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_shrd_ram_owrite_err_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssShrdRamOwriteErrAddrSpec ; impl crate :: RegisterSpec for AppssShrdRamOwriteErrAddrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_shrd_ram_owrite_err_addr::R`](R) reader structure"]
impl crate :: Readable for AppssShrdRamOwriteErrAddrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_shrd_ram_owrite_err_addr::W`](W) writer structure"]
impl crate :: Writable for AppssShrdRamOwriteErrAddrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_SHRD_RAM_OWRITE_ERR_ADDR to value 0"]
impl crate :: Resettable for AppssShrdRamOwriteErrAddrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_OWRITE_ERR_AGGR (rw) register accessor: APPSS_OWRITE_ERR_AGGR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_owrite_err_aggr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_owrite_err_aggr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_owrite_err_aggr`]
module"]
# [doc (alias = "APPSS_OWRITE_ERR_AGGR")]
pub type AppssOwriteErrAggr = crate :: Reg < appss_owrite_err_aggr :: AppssOwriteErrAggrSpec > ; # [doc = "APPSS_OWRITE_ERR_AGGR"]
pub mod appss_owrite_err_aggr { # [doc = "Register `APPSS_OWRITE_ERR_AGGR` reader"]
pub type R = crate :: R < AppssOwriteErrAggrSpec > ; # [doc = "Register `APPSS_OWRITE_ERR_AGGR` writer"]
pub type W = crate :: W < AppssOwriteErrAggrSpec > ; # [doc = "Field `err` reader - 0:0\\]
Ored error of all write error signals -Sticky Bit"]
pub type ErrR = crate :: BitReader ; # [doc = "Field `err` writer - 0:0\\]
Ored error of all write error signals -Sticky Bit"]
pub type ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Ored error of all write error signals -Sticky Bit"]
# [inline (always)]
pub fn err (& self) -> ErrR { ErrR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Ored error of all write error signals -Sticky Bit"]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ErrW < AppssOwriteErrAggrSpec > { ErrW :: new (self , 0) } } # [doc = "APPSS_OWRITE_ERR_AGGR\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_owrite_err_aggr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_owrite_err_aggr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssOwriteErrAggrSpec ; impl crate :: RegisterSpec for AppssOwriteErrAggrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_owrite_err_aggr::R`](R) reader structure"]
impl crate :: Readable for AppssOwriteErrAggrSpec { } # [doc = "`write(|w| ..)` method takes [`appss_owrite_err_aggr::W`](W) writer structure"]
impl crate :: Writable for AppssOwriteErrAggrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_OWRITE_ERR_AGGR to value 0"]
impl crate :: Resettable for AppssOwriteErrAggrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW6 (rw) register accessor: HW_SPARE_RW6\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw6`]
module"]
# [doc (alias = "HW_SPARE_RW6")]
pub type HwSpareRw6 = crate :: Reg < hw_spare_rw6 :: HwSpareRw6Spec > ; # [doc = "HW_SPARE_RW6"]
pub mod hw_spare_rw6 { # [doc = "Register `HW_SPARE_RW6` reader"]
pub type R = crate :: R < HwSpareRw6Spec > ; # [doc = "Register `HW_SPARE_RW6` writer"]
pub type W = crate :: W < HwSpareRw6Spec > ; # [doc = "Field `hw_spare_rw6` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw6R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw6` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw6 (& self) -> HwSpareRw6R { HwSpareRw6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw6 (& mut self) -> HwSpareRw6W < HwSpareRw6Spec > { HwSpareRw6W :: new (self , 0) } } # [doc = "HW_SPARE_RW6\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw6Spec ; impl crate :: RegisterSpec for HwSpareRw6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw6::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw6Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw6::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW6 to value 0"]
impl crate :: Resettable for HwSpareRw6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW7 (rw) register accessor: HW_SPARE_RW7\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw7`]
module"]
# [doc (alias = "HW_SPARE_RW7")]
pub type HwSpareRw7 = crate :: Reg < hw_spare_rw7 :: HwSpareRw7Spec > ; # [doc = "HW_SPARE_RW7"]
pub mod hw_spare_rw7 { # [doc = "Register `HW_SPARE_RW7` reader"]
pub type R = crate :: R < HwSpareRw7Spec > ; # [doc = "Register `HW_SPARE_RW7` writer"]
pub type W = crate :: W < HwSpareRw7Spec > ; # [doc = "Field `hw_spare_rw7` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw7R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw7` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw7 (& self) -> HwSpareRw7R { HwSpareRw7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw7 (& mut self) -> HwSpareRw7W < HwSpareRw7Spec > { HwSpareRw7W :: new (self , 0) } } # [doc = "HW_SPARE_RW7\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw7Spec ; impl crate :: RegisterSpec for HwSpareRw7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw7::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw7Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw7::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW7 to value 0"]
impl crate :: Resettable for HwSpareRw7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW8 (rw) register accessor: HW_SPARE_RW8\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw8`]
module"]
# [doc (alias = "HW_SPARE_RW8")]
pub type HwSpareRw8 = crate :: Reg < hw_spare_rw8 :: HwSpareRw8Spec > ; # [doc = "HW_SPARE_RW8"]
pub mod hw_spare_rw8 { # [doc = "Register `HW_SPARE_RW8` reader"]
pub type R = crate :: R < HwSpareRw8Spec > ; # [doc = "Register `HW_SPARE_RW8` writer"]
pub type W = crate :: W < HwSpareRw8Spec > ; # [doc = "Field `hw_spare_rw8` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw8R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw8` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw8 (& self) -> HwSpareRw8R { HwSpareRw8R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw8 (& mut self) -> HwSpareRw8W < HwSpareRw8Spec > { HwSpareRw8W :: new (self , 0) } } # [doc = "HW_SPARE_RW8\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw8Spec ; impl crate :: RegisterSpec for HwSpareRw8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw8::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw8Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw8::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW8 to value 0"]
impl crate :: Resettable for HwSpareRw8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_RW9 (rw) register accessor: HW_SPARE_RW9\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_rw9`]
module"]
# [doc (alias = "HW_SPARE_RW9")]
pub type HwSpareRw9 = crate :: Reg < hw_spare_rw9 :: HwSpareRw9Spec > ; # [doc = "HW_SPARE_RW9"]
pub mod hw_spare_rw9 { # [doc = "Register `HW_SPARE_RW9` reader"]
pub type R = crate :: R < HwSpareRw9Spec > ; # [doc = "Register `HW_SPARE_RW9` writer"]
pub type W = crate :: W < HwSpareRw9Spec > ; # [doc = "Field `hw_spare_rw9` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw9R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_rw9` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareRw9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_rw9 (& self) -> HwSpareRw9R { HwSpareRw9R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_rw9 (& mut self) -> HwSpareRw9W < HwSpareRw9Spec > { HwSpareRw9W :: new (self , 0) } } # [doc = "HW_SPARE_RW9\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_rw9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_rw9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareRw9Spec ; impl crate :: RegisterSpec for HwSpareRw9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_rw9::R`](R) reader structure"]
impl crate :: Readable for HwSpareRw9Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_rw9::W`](W) writer structure"]
impl crate :: Writable for HwSpareRw9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_RW9 to value 0"]
impl crate :: Resettable for HwSpareRw9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_SPARE_HWA_RW0 (rw) register accessor: HW_SPARE_HWA_RW0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_hwa_rw0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_hwa_rw0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_spare_hwa_rw0`]
module"]
# [doc (alias = "HW_SPARE_HWA_RW0")]
pub type HwSpareHwaRw0 = crate :: Reg < hw_spare_hwa_rw0 :: HwSpareHwaRw0Spec > ; # [doc = "HW_SPARE_HWA_RW0"]
pub mod hw_spare_hwa_rw0 { # [doc = "Register `HW_SPARE_HWA_RW0` reader"]
pub type R = crate :: R < HwSpareHwaRw0Spec > ; # [doc = "Register `HW_SPARE_HWA_RW0` writer"]
pub type W = crate :: W < HwSpareHwaRw0Spec > ; # [doc = "Field `hw_spare_hwa_rw0` reader - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareHwaRw0R = crate :: FieldReader < u32 > ; # [doc = "Field `hw_spare_hwa_rw0` writer - 31:0\\]
Reserved for HW R&amp;D"]
pub type HwSpareHwaRw0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
pub fn hw_spare_hwa_rw0 (& self) -> HwSpareHwaRw0R { HwSpareHwaRw0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved for HW R&amp;D"]
# [inline (always)]
# [must_use]
pub fn hw_spare_hwa_rw0 (& mut self) -> HwSpareHwaRw0W < HwSpareHwaRw0Spec > { HwSpareHwaRw0W :: new (self , 0) } } # [doc = "HW_SPARE_HWA_RW0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_spare_hwa_rw0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_spare_hwa_rw0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwSpareHwaRw0Spec ; impl crate :: RegisterSpec for HwSpareHwaRw0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_spare_hwa_rw0::R`](R) reader structure"]
impl crate :: Readable for HwSpareHwaRw0Spec { } # [doc = "`write(|w| ..)` method takes [`hw_spare_hwa_rw0::W`](W) writer structure"]
impl crate :: Writable for HwSpareHwaRw0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_SPARE_HWA_RW0 to value 0"]
impl crate :: Resettable for HwSpareHwaRw0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK0 (rw) register accessor: - KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick0`]
module"]
# [doc (alias = "LOCK0_KICK0")]
pub type Lock0Kick0 = crate :: Reg < lock0_kick0 :: Lock0Kick0Spec > ; # [doc = "- KICK0 component"]
pub mod lock0_kick0 { # [doc = "Register `LOCK0_KICK0` reader"]
pub type R = crate :: R < Lock0Kick0Spec > ; # [doc = "Register `LOCK0_KICK0` writer"]
pub type W = crate :: W < Lock0Kick0Spec > ; # [doc = "Field `KICK0_COMPONENT` reader - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK0_COMPONENT` writer - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
pub fn kick0_component (& self) -> Kick0ComponentR { Kick0ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
# [must_use]
pub fn kick0_component (& mut self) -> Kick0ComponentW < Lock0Kick0Spec > { Kick0ComponentW :: new (self , 0) } } # [doc = "- KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick0Spec ; impl crate :: RegisterSpec for Lock0Kick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick0::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick0Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick0::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK0 to value 0"]
impl crate :: Resettable for Lock0Kick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK1 (rw) register accessor: - KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick1`]
module"]
# [doc (alias = "LOCK0_KICK1")]
pub type Lock0Kick1 = crate :: Reg < lock0_kick1 :: Lock0Kick1Spec > ; # [doc = "- KICK1 component"]
pub mod lock0_kick1 { # [doc = "Register `LOCK0_KICK1` reader"]
pub type R = crate :: R < Lock0Kick1Spec > ; # [doc = "Register `LOCK0_KICK1` writer"]
pub type W = crate :: W < Lock0Kick1Spec > ; # [doc = "Field `KICK1_COMPONENT` reader - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK1_COMPONENT` writer - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
pub fn kick1_component (& self) -> Kick1ComponentR { Kick1ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
# [must_use]
pub fn kick1_component (& mut self) -> Kick1ComponentW < Lock0Kick1Spec > { Kick1ComponentW :: new (self , 0) } } # [doc = "- KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick1Spec ; impl crate :: RegisterSpec for Lock0Kick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick1::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick1Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick1::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK1 to value 0"]
impl crate :: Resettable for Lock0Kick1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_raw_status (rw) register accessor: Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw_status`]
module"]
# [doc (alias = "intr_raw_status")]
pub type IntrRawStatus = crate :: Reg < intr_raw_status :: IntrRawStatusSpec > ; # [doc = "Interrupt Raw Status/Set Register"]
pub mod intr_raw_status { # [doc = "Register `intr_raw_status` reader"]
pub type R = crate :: R < IntrRawStatusSpec > ; # [doc = "Register `intr_raw_status` writer"]
pub type W = crate :: W < IntrRawStatusSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrRawStatusSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrRawStatusSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrRawStatusSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrRawStatusSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrRawStatusSpec ; impl crate :: RegisterSpec for IntrRawStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_raw_status::R`](R) reader structure"]
impl crate :: Readable for IntrRawStatusSpec { } # [doc = "`write(|w| ..)` method takes [`intr_raw_status::W`](W) writer structure"]
impl crate :: Writable for IntrRawStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_raw_status to value 0"]
impl crate :: Resettable for IntrRawStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enabled_status_clear (rw) register accessor: Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enabled_status_clear`]
module"]
# [doc (alias = "intr_enabled_status_clear")]
pub type IntrEnabledStatusClear = crate :: Reg < intr_enabled_status_clear :: IntrEnabledStatusClearSpec > ; # [doc = "Interrupt Enabled Status/Clear register"]
pub mod intr_enabled_status_clear { # [doc = "Register `intr_enabled_status_clear` reader"]
pub type R = crate :: R < IntrEnabledStatusClearSpec > ; # [doc = "Register `intr_enabled_status_clear` writer"]
pub type W = crate :: W < IntrEnabledStatusClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrEnabledStatusClearSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrEnabledStatusClearSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnabledStatusClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnabledStatusClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnabledStatusClearSpec ; impl crate :: RegisterSpec for IntrEnabledStatusClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enabled_status_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnabledStatusClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enabled_status_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnabledStatusClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enabled_status_clear to value 0"]
impl crate :: Resettable for IntrEnabledStatusClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable`]
module"]
# [doc (alias = "intr_enable")]
pub type IntrEnable = crate :: Reg < intr_enable :: IntrEnableSpec > ; # [doc = "Interrupt Enable register"]
pub mod intr_enable { # [doc = "Register `intr_enable` reader"]
pub type R = crate :: R < IntrEnableSpec > ; # [doc = "Register `intr_enable` writer"]
pub type W = crate :: W < IntrEnableSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSpec ; impl crate :: RegisterSpec for IntrEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable to value 0"]
impl crate :: Resettable for IntrEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable_clear (rw) register accessor: Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "intr_enable_clear")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "Interrupt Enable Clear register"]
pub mod intr_enable_clear { # [doc = "Register `intr_enable_clear` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `intr_enable_clear` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableClearSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableClearSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable_clear to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "eoi (rw) register accessor: EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi`]
module"]
# [doc (alias = "eoi")]
pub type Eoi = crate :: Reg < eoi :: EoiSpec > ; # [doc = "EOI register"]
pub mod eoi { # [doc = "Register `eoi` reader"]
pub type R = crate :: R < EoiSpec > ; # [doc = "Register `eoi` writer"]
pub type W = crate :: W < EoiSpec > ; # [doc = "Field `EOI_VECTOR_VALUE_` reader - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_R = crate :: FieldReader ; # [doc = "Field `EOI_VECTOR_VALUE_` writer - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
pub fn eoi_vector_value_ (& self) -> EoiVectorValue_R { EoiVectorValue_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
# [must_use]
pub fn eoi_vector_value_ (& mut self) -> EoiVectorValue_W < EoiSpec > { EoiVectorValue_W :: new (self , 0) } } # [doc = "EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EoiSpec ; impl crate :: RegisterSpec for EoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eoi::R`](R) reader structure"]
impl crate :: Readable for EoiSpec { } # [doc = "`write(|w| ..)` method takes [`eoi::W`](W) writer structure"]
impl crate :: Writable for EoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets eoi to value 0"]
impl crate :: Resettable for EoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_address (rw) register accessor: Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_address`]
module"]
# [doc (alias = "fault_address")]
pub type FaultAddress = crate :: Reg < fault_address :: FaultAddressSpec > ; # [doc = "Fault Address register"]
pub mod fault_address { # [doc = "Register `fault_address` reader"]
pub type R = crate :: R < FaultAddressSpec > ; # [doc = "Register `fault_address` writer"]
pub type W = crate :: W < FaultAddressSpec > ; # [doc = "Field `FAULT_ADDRESS_` reader - 31:0\\]
Fault Address."]
pub type FaultAddress_R = crate :: FieldReader < u32 > ; # [doc = "Field `FAULT_ADDRESS_` writer - 31:0\\]
Fault Address."]
pub type FaultAddress_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
pub fn fault_address_ (& self) -> FaultAddress_R { FaultAddress_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
# [must_use]
pub fn fault_address_ (& mut self) -> FaultAddress_W < FaultAddressSpec > { FaultAddress_W :: new (self , 0) } } # [doc = "Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAddressSpec ; impl crate :: RegisterSpec for FaultAddressSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_address::R`](R) reader structure"]
impl crate :: Readable for FaultAddressSpec { } # [doc = "`write(|w| ..)` method takes [`fault_address::W`](W) writer structure"]
impl crate :: Writable for FaultAddressSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_address to value 0"]
impl crate :: Resettable for FaultAddressSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_type_status (rw) register accessor: Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_type_status`]
module"]
# [doc (alias = "fault_type_status")]
pub type FaultTypeStatus = crate :: Reg < fault_type_status :: FaultTypeStatusSpec > ; # [doc = "Fault Type Status register"]
pub mod fault_type_status { # [doc = "Register `fault_type_status` reader"]
pub type R = crate :: R < FaultTypeStatusSpec > ; # [doc = "Register `fault_type_status` writer"]
pub type W = crate :: W < FaultTypeStatusSpec > ; # [doc = "Field `FAULT_TYPE_10_0000` reader - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000R = crate :: FieldReader ; # [doc = "Field `FAULT_TYPE_10_0000` writer - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NONSECURE_ACCESS_` reader - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_R = crate :: BitReader ; # [doc = "Field `NONSECURE_ACCESS_` writer - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
pub fn fault_type_10_0000 (& self) -> FaultType10_0000R { FaultType10_0000R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
pub fn nonsecure_access_ (& self) -> NonsecureAccess_R { NonsecureAccess_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
# [must_use]
pub fn fault_type_10_0000 (& mut self) -> FaultType10_0000W < FaultTypeStatusSpec > { FaultType10_0000W :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
# [must_use]
pub fn nonsecure_access_ (& mut self) -> NonsecureAccess_W < FaultTypeStatusSpec > { NonsecureAccess_W :: new (self , 6) } } # [doc = "Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultTypeStatusSpec ; impl crate :: RegisterSpec for FaultTypeStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_type_status::R`](R) reader structure"]
impl crate :: Readable for FaultTypeStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_type_status::W`](W) writer structure"]
impl crate :: Writable for FaultTypeStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_type_status to value 0"]
impl crate :: Resettable for FaultTypeStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_attr_status (rw) register accessor: Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_attr_status`]
module"]
# [doc (alias = "fault_attr_status")]
pub type FaultAttrStatus = crate :: Reg < fault_attr_status :: FaultAttrStatusSpec > ; # [doc = "Fault Attribute Status register"]
pub mod fault_attr_status { # [doc = "Register `fault_attr_status` reader"]
pub type R = crate :: R < FaultAttrStatusSpec > ; # [doc = "Register `fault_attr_status` writer"]
pub type W = crate :: W < FaultAttrStatusSpec > ; # [doc = "Field `PRIVILEGE_ID_` reader - 7:0\\]
Privilege ID."]
pub type PrivilegeId_R = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID_` writer - 7:0\\]
Privilege ID."]
pub type PrivilegeId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ROUTE_ID_` reader - 19:8\\]
Route ID."]
pub type RouteId_R = crate :: FieldReader < u16 > ; # [doc = "Field `ROUTE_ID_` writer - 19:8\\]
Route ID."]
pub type RouteId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `XID_` reader - 31:20\\]
XID."]
pub type Xid_R = crate :: FieldReader < u16 > ; # [doc = "Field `XID_` writer - 31:20\\]
XID."]
pub type Xid_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
pub fn privilege_id_ (& self) -> PrivilegeId_R { PrivilegeId_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
pub fn route_id_ (& self) -> RouteId_R { RouteId_R :: new (((self . bits >> 8) & 0x0fff) as u16) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
pub fn xid_ (& self) -> Xid_R { Xid_R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
# [must_use]
pub fn privilege_id_ (& mut self) -> PrivilegeId_W < FaultAttrStatusSpec > { PrivilegeId_W :: new (self , 0) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
# [must_use]
pub fn route_id_ (& mut self) -> RouteId_W < FaultAttrStatusSpec > { RouteId_W :: new (self , 8) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
# [must_use]
pub fn xid_ (& mut self) -> Xid_W < FaultAttrStatusSpec > { Xid_W :: new (self , 20) } } # [doc = "Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAttrStatusSpec ; impl crate :: RegisterSpec for FaultAttrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_attr_status::R`](R) reader structure"]
impl crate :: Readable for FaultAttrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_attr_status::W`](W) writer structure"]
impl crate :: Writable for FaultAttrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_attr_status to value 0"]
impl crate :: Resettable for FaultAttrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_clear (rw) register accessor: Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_clear`]
module"]
# [doc (alias = "fault_clear")]
pub type FaultClear = crate :: Reg < fault_clear :: FaultClearSpec > ; # [doc = "Fault Clear register"]
pub mod fault_clear { # [doc = "Register `fault_clear` reader"]
pub type R = crate :: R < FaultClearSpec > ; # [doc = "Register `fault_clear` writer"]
pub type W = crate :: W < FaultClearSpec > ; # [doc = "Field `FAULT_CLEAR__WRITING` reader - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingR = crate :: BitReader ; # [doc = "Field `FAULT_CLEAR__WRITING` writer - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
pub fn fault_clear__writing (& self) -> FaultClear_WritingR { FaultClear_WritingR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn fault_clear__writing (& mut self) -> FaultClear_WritingW < FaultClearSpec > { FaultClear_WritingW :: new (self , 0) } } # [doc = "Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultClearSpec ; impl crate :: RegisterSpec for FaultClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_clear::R`](R) reader structure"]
impl crate :: Readable for FaultClearSpec { } # [doc = "`write(|w| ..)` method takes [`fault_clear::W`](W) writer structure"]
impl crate :: Writable for FaultClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_clear to value 0"]
impl crate :: Resettable for FaultClearSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_HWA_ADCBUF_CTRL"]
pub struct AppHwaAdcbufCtrl { _marker : PhantomData < * const () > } unsafe impl Send for AppHwaAdcbufCtrl { } impl AppHwaAdcbufCtrl { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_hwa_adcbuf_ctrl :: RegisterBlock = 0x5608_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_hwa_adcbuf_ctrl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppHwaAdcbufCtrl { type Target = app_hwa_adcbuf_ctrl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppHwaAdcbufCtrl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppHwaAdcbufCtrl") . finish () } } # [doc = "APP_HWA_ADCBUF_CTRL"]
pub mod app_hwa_adcbuf_ctrl { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , hw_reg0 : HwReg0 , adcbufcfg1 : Adcbufcfg1 , adcbufcfg1_extd : Adcbufcfg1Extd , adcbufcfg2 : Adcbufcfg2 , adcbufcfg3 : Adcbufcfg3 , adcbufcfg4 : Adcbufcfg4 , adcbufintgenditherdly : Adcbufintgenditherdly , adcbuff_ping_mem_init : AdcbuffPingMemInit , adcbuff_ping_mem_done : AdcbuffPingMemDone , adcbuff_ping_mem_status : AdcbuffPingMemStatus , adcbuff_pong_mem_init : AdcbuffPongMemInit , adcbuff_pong_mem_done : AdcbuffPongMemDone , adcbuff_pong_mem_status : AdcbuffPongMemStatus , hwass_shrd_ram_mem_init : HwassShrdRamMemInit , hwass_shrd_ram_mem_done : HwassShrdRamMemDone , hwass_shrd_ram_mem_status : HwassShrdRamMemStatus , hwass_shrd_ram_access_error_mask : HwassShrdRamAccessErrorMask , hwass_shrd_ram_access_error_status : HwassShrdRamAccessErrorStatus , hwass_shrd_ram_access_error_status_raw : HwassShrdRamAccessErrorStatusRaw , hwass_edma_clock_gate_control : HwassEdmaClockGateControl , hwass_ram_160kb_clock_gate : HwassRam160kbClockGate , _reserved22 : [u8 ; 0x0fb0]
, lock0_kick0 : Lock0Kick0 , lock0_kick1 : Lock0Kick1 , intr_raw_status : IntrRawStatus , intr_enabled_status_clear : IntrEnabledStatusClear , intr_enable : IntrEnable , intr_enable_clear : IntrEnableClear , eoi : Eoi , fault_address : FaultAddress , fault_type_status : FaultTypeStatus , fault_attr_status : FaultAttrStatus , fault_clear : FaultClear , } impl RegisterBlock { # [doc = "0x00 - PID register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - HW_REG0"]
# [inline (always)]
pub const fn hw_reg0 (& self) -> & HwReg0 { & self . hw_reg0 } # [doc = "0x08 - ADCBUFCFG1"]
# [inline (always)]
pub const fn adcbufcfg1 (& self) -> & Adcbufcfg1 { & self . adcbufcfg1 } # [doc = "0x0c - ADCBUFCFG1_EXTD"]
# [inline (always)]
pub const fn adcbufcfg1_extd (& self) -> & Adcbufcfg1Extd { & self . adcbufcfg1_extd } # [doc = "0x10 - ADCBUFCFG2"]
# [inline (always)]
pub const fn adcbufcfg2 (& self) -> & Adcbufcfg2 { & self . adcbufcfg2 } # [doc = "0x14 - ADCBUFCFG3"]
# [inline (always)]
pub const fn adcbufcfg3 (& self) -> & Adcbufcfg3 { & self . adcbufcfg3 } # [doc = "0x18 - ADCBUFCFG4"]
# [inline (always)]
pub const fn adcbufcfg4 (& self) -> & Adcbufcfg4 { & self . adcbufcfg4 } # [doc = "0x1c - ADCBUFINTGENDITHERDLY"]
# [inline (always)]
pub const fn adcbufintgenditherdly (& self) -> & Adcbufintgenditherdly { & self . adcbufintgenditherdly } # [doc = "0x20 - ADCBUFF_PING_MEM_INIT"]
# [inline (always)]
pub const fn adcbuff_ping_mem_init (& self) -> & AdcbuffPingMemInit { & self . adcbuff_ping_mem_init } # [doc = "0x24 - ADCBUFF_PING_MEM_DONE"]
# [inline (always)]
pub const fn adcbuff_ping_mem_done (& self) -> & AdcbuffPingMemDone { & self . adcbuff_ping_mem_done } # [doc = "0x28 - ADCBUFF_PING_MEM_STATUS"]
# [inline (always)]
pub const fn adcbuff_ping_mem_status (& self) -> & AdcbuffPingMemStatus { & self . adcbuff_ping_mem_status } # [doc = "0x2c - ADCBUFF_PONG_MEM_INIT"]
# [inline (always)]
pub const fn adcbuff_pong_mem_init (& self) -> & AdcbuffPongMemInit { & self . adcbuff_pong_mem_init } # [doc = "0x30 - ADCBUFF_PONG_MEM_DONE"]
# [inline (always)]
pub const fn adcbuff_pong_mem_done (& self) -> & AdcbuffPongMemDone { & self . adcbuff_pong_mem_done } # [doc = "0x34 - ADCBUFF_PONG_MEM_STATUS"]
# [inline (always)]
pub const fn adcbuff_pong_mem_status (& self) -> & AdcbuffPongMemStatus { & self . adcbuff_pong_mem_status } # [doc = "0x38 - HWASS_SHRD_RAM_MEM_INIT"]
# [inline (always)]
pub const fn hwass_shrd_ram_mem_init (& self) -> & HwassShrdRamMemInit { & self . hwass_shrd_ram_mem_init } # [doc = "0x3c - HWASS_SHRD_RAM_MEM_DONE"]
# [inline (always)]
pub const fn hwass_shrd_ram_mem_done (& self) -> & HwassShrdRamMemDone { & self . hwass_shrd_ram_mem_done } # [doc = "0x40 - HWASS_SHRD_RAM_MEM_STATUS"]
# [inline (always)]
pub const fn hwass_shrd_ram_mem_status (& self) -> & HwassShrdRamMemStatus { & self . hwass_shrd_ram_mem_status } # [doc = "0x44 - HWASS_SHRD_RAM_ACCESS_ERROR_MASK"]
# [inline (always)]
pub const fn hwass_shrd_ram_access_error_mask (& self) -> & HwassShrdRamAccessErrorMask { & self . hwass_shrd_ram_access_error_mask } # [doc = "0x48 - HWASS_SHRD_RAM_ACCESS_ERROR_STATUS"]
# [inline (always)]
pub const fn hwass_shrd_ram_access_error_status (& self) -> & HwassShrdRamAccessErrorStatus { & self . hwass_shrd_ram_access_error_status } # [doc = "0x4c - HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW"]
# [inline (always)]
pub const fn hwass_shrd_ram_access_error_status_raw (& self) -> & HwassShrdRamAccessErrorStatusRaw { & self . hwass_shrd_ram_access_error_status_raw } # [doc = "0x50 - HWASS_EDMA_CLOCK_GATE_CONTROL"]
# [inline (always)]
pub const fn hwass_edma_clock_gate_control (& self) -> & HwassEdmaClockGateControl { & self . hwass_edma_clock_gate_control } # [doc = "0x54 - HWASS_RAM_160KB_CLOCK_GATE"]
# [inline (always)]
pub const fn hwass_ram_160kb_clock_gate (& self) -> & HwassRam160kbClockGate { & self . hwass_ram_160kb_clock_gate } # [doc = "0x1008 - - KICK0 component"]
# [inline (always)]
pub const fn lock0_kick0 (& self) -> & Lock0Kick0 { & self . lock0_kick0 } # [doc = "0x100c - - KICK1 component"]
# [inline (always)]
pub const fn lock0_kick1 (& self) -> & Lock0Kick1 { & self . lock0_kick1 } # [doc = "0x1010 - Interrupt Raw Status/Set Register"]
# [inline (always)]
pub const fn intr_raw_status (& self) -> & IntrRawStatus { & self . intr_raw_status } # [doc = "0x1014 - Interrupt Enabled Status/Clear register"]
# [inline (always)]
pub const fn intr_enabled_status_clear (& self) -> & IntrEnabledStatusClear { & self . intr_enabled_status_clear } # [doc = "0x1018 - Interrupt Enable register"]
# [inline (always)]
pub const fn intr_enable (& self) -> & IntrEnable { & self . intr_enable } # [doc = "0x101c - Interrupt Enable Clear register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x1020 - EOI register"]
# [inline (always)]
pub const fn eoi (& self) -> & Eoi { & self . eoi } # [doc = "0x1024 - Fault Address register"]
# [inline (always)]
pub const fn fault_address (& self) -> & FaultAddress { & self . fault_address } # [doc = "0x1028 - Fault Type Status register"]
# [inline (always)]
pub const fn fault_type_status (& self) -> & FaultTypeStatus { & self . fault_type_status } # [doc = "0x102c - Fault Attribute Status register"]
# [inline (always)]
pub const fn fault_attr_status (& self) -> & FaultAttrStatus { & self . fault_attr_status } # [doc = "0x1030 - Fault Clear register"]
# [inline (always)]
pub const fn fault_clear (& self) -> & FaultClear { & self . fault_clear } } # [doc = "PID (rw) register accessor: PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `PID_W6_O0` reader - "]
pub type PidW6O0R = crate :: FieldReader ; # [doc = "Field `PID_W6_O0` writer - "]
pub type PidW6O0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PID_W2_O6` reader - "]
pub type PidW2O6R = crate :: FieldReader ; # [doc = "Field `PID_W2_O6` writer - "]
pub type PidW2O6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PID_W3_O8` reader - "]
pub type PidW3O8R = crate :: FieldReader ; # [doc = "Field `PID_W3_O8` writer - "]
pub type PidW3O8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PID_W5_O11` reader - "]
pub type PidW5O11R = crate :: FieldReader ; # [doc = "Field `PID_W5_O11` writer - "]
pub type PidW5O11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PID_W16_O16` reader - "]
pub type PidW16O16R = crate :: FieldReader < u16 > ; # [doc = "Field `PID_W16_O16` writer - "]
pub type PidW16O16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5"]
# [inline (always)]
pub fn pid_w6_o0 (& self) -> PidW6O0R { PidW6O0R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7"]
# [inline (always)]
pub fn pid_w2_o6 (& self) -> PidW2O6R { PidW2O6R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10"]
# [inline (always)]
pub fn pid_w3_o8 (& self) -> PidW3O8R { PidW3O8R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15"]
# [inline (always)]
pub fn pid_w5_o11 (& self) -> PidW5O11R { PidW5O11R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn pid_w16_o16 (& self) -> PidW16O16R { PidW16O16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5"]
# [inline (always)]
# [must_use]
pub fn pid_w6_o0 (& mut self) -> PidW6O0W < PidSpec > { PidW6O0W :: new (self , 0) } # [doc = "Bits 6:7"]
# [inline (always)]
# [must_use]
pub fn pid_w2_o6 (& mut self) -> PidW2O6W < PidSpec > { PidW2O6W :: new (self , 6) } # [doc = "Bits 8:10"]
# [inline (always)]
# [must_use]
pub fn pid_w3_o8 (& mut self) -> PidW3O8W < PidSpec > { PidW3O8W :: new (self , 8) } # [doc = "Bits 11:15"]
# [inline (always)]
# [must_use]
pub fn pid_w5_o11 (& mut self) -> PidW5O11W < PidSpec > { PidW5O11W :: new (self , 11) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn pid_w16_o16 (& mut self) -> PidW16O16W < PidSpec > { PidW16O16W :: new (self , 16) } } # [doc = "PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HW_REG0 (rw) register accessor: HW_REG0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_reg0`]
module"]
# [doc (alias = "HW_REG0")]
pub type HwReg0 = crate :: Reg < hw_reg0 :: HwReg0Spec > ; # [doc = "HW_REG0"]
pub mod hw_reg0 { # [doc = "Register `HW_REG0` reader"]
pub type R = crate :: R < HwReg0Spec > ; # [doc = "Register `HW_REG0` writer"]
pub type W = crate :: W < HwReg0Spec > ; # [doc = "Field `HW_REG0` reader - 31:0\\]
Reserved"]
pub type HwReg0R = crate :: FieldReader < u32 > ; # [doc = "Field `HW_REG0` writer - 31:0\\]
Reserved"]
pub type HwReg0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn hw_reg0 (& self) -> HwReg0R { HwReg0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn hw_reg0 (& mut self) -> HwReg0W < HwReg0Spec > { HwReg0W :: new (self , 0) } } # [doc = "HW_REG0\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwReg0Spec ; impl crate :: RegisterSpec for HwReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`hw_reg0::R`](R) reader structure"]
impl crate :: Readable for HwReg0Spec { } # [doc = "`write(|w| ..)` method takes [`hw_reg0::W`](W) writer structure"]
impl crate :: Writable for HwReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HW_REG0 to value 0"]
impl crate :: Resettable for HwReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFCFG1 (rw) register accessor: ADCBUFCFG1\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbufcfg1`]
module"]
# [doc (alias = "ADCBUFCFG1")]
pub type Adcbufcfg1 = crate :: Reg < adcbufcfg1 :: Adcbufcfg1Spec > ; # [doc = "ADCBUFCFG1"]
pub mod adcbufcfg1 { # [doc = "Register `ADCBUFCFG1` reader"]
pub type R = crate :: R < Adcbufcfg1Spec > ; # [doc = "Register `ADCBUFCFG1` writer"]
pub type W = crate :: W < Adcbufcfg1Spec > ; # [doc = "Field `ADCBUFWRSOURCE` reader - 0:0\\]
TI Internal Feature Write source for ADC Buffer. 0 --> DFE, 1 --> HWASS Interconnect"]
pub type AdcbufwrsourceR = crate :: BitReader ; # [doc = "Field `ADCBUFWRSOURCE` writer - 0:0\\]
TI Internal Feature Write source for ADC Buffer. 0 --> DFE, 1 --> HWASS Interconnect"]
pub type AdcbufwrsourceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFPIPOSELINV` reader - 1:1\\]
TI Internal Feature Inversion control for ADC Buffer Ping-pong select. By default ADC Buffer write starts with Pong write. By setting this bit to 1, it will start from Ping write after reset."]
pub type AdcbufpiposelinvR = crate :: BitReader ; # [doc = "Field `ADCBUFPIPOSELINV` writer - 1:1\\]
TI Internal Feature Inversion control for ADC Buffer Ping-pong select. By default ADC Buffer write starts with Pong write. By setting this bit to 1, it will start from Ping write after reset."]
pub type AdcbufpiposelinvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0EN` reader - 6:6\\]
Enable for Rx0 write"]
pub type Rx0enR = crate :: BitReader ; # [doc = "Field `RX0EN` writer - 6:6\\]
Enable for Rx0 write"]
pub type Rx0enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX1EN` reader - 7:7\\]
Enable for Rx1 write"]
pub type Rx1enR = crate :: BitReader ; # [doc = "Field `RX1EN` writer - 7:7\\]
Enable for Rx1 write"]
pub type Rx1enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX2EN` reader - 8:8\\]
Enable for Rx2 write"]
pub type Rx2enR = crate :: BitReader ; # [doc = "Field `RX2EN` writer - 8:8\\]
Enable for Rx2 write"]
pub type Rx2enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX3EN` reader - 9:9\\]
TI Reserved"]
pub type Rx3enR = crate :: BitReader ; # [doc = "Field `RX3EN` writer - 9:9\\]
TI Reserved"]
pub type Rx3enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFPIPOOVRCNT` reader - 10:10\\]
TI Internal Feature Override control for ADC Buffer Ping Pong select"]
pub type AdcbufpipoovrcntR = crate :: BitReader ; # [doc = "Field `ADCBUFPIPOOVRCNT` writer - 10:10\\]
TI Internal Feature Override control for ADC Buffer Ping Pong select"]
pub type AdcbufpipoovrcntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFPIPOOVRVAL` reader - 11:11\\]
TI Internal Feature SW override value for ADC Buffer Ping Pong select"]
pub type AdcbufpipoovrvalR = crate :: BitReader ; # [doc = "Field `ADCBUFPIPOOVRVAL` writer - 11:11\\]
TI Internal Feature SW override value for ADC Buffer Ping Pong select"]
pub type AdcbufpipoovrvalW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFCONTMODEEN` reader - 13:13\\]
Continuous mode enable for ADC Buffer. This is set when a fixed number of samples have to be stored in Ping/Pong and not depend on Chirp time-lines (Eg: Analog Lab characterization to stream out continuous data from DFE). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
pub type AdcbufcontmodeenR = crate :: BitReader ; # [doc = "Field `ADCBUFCONTMODEEN` writer - 13:13\\]
Continuous mode enable for ADC Buffer. This is set when a fixed number of samples have to be stored in Ping/Pong and not depend on Chirp time-lines (Eg: Analog Lab characterization to stream out continuous data from DFE). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
pub type AdcbufcontmodeenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFCONTSTRTPL` reader - 14:14\\]
Start Pulse for Continuous mode. The data capture will start from Address 0 once this register is set. All the other configurations like Enable, Sample Count are expected to be programmed before this pulse. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
pub type AdcbufcontstrtplR = crate :: BitReader ; # [doc = "Field `ADCBUFCONTSTRTPL` writer - 14:14\\]
Start Pulse for Continuous mode. The data capture will start from Address 0 once this register is set. All the other configurations like Enable, Sample Count are expected to be programmed before this pulse. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
pub type AdcbufcontstrtplW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFCONTSTOPPL` reader - 15:15\\]
Stop Pulse for Continuous mode. The data capture will stop once this register is set. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
pub type AdcbufcontstopplR = crate :: BitReader ; # [doc = "Field `ADCBUFCONTSTOPPL` writer - 15:15\\]
Stop Pulse for Continuous mode. The data capture will stop once this register is set. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
pub type AdcbufcontstopplW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUFPIPOSEL` reader - 16:16\\]
TI Internal Feature Ping-pong select value from ADC Buffer Packing logic. Even in SW override mode, this register will indicate the ping-pong select signal generated from the ADC Buffer Packing logic and not the override value."]
pub type AdcbufpiposelR = crate :: BitReader ; # [doc = "Field `ADCBUFPIPOSEL` writer - 16:16\\]
TI Internal Feature Ping-pong select value from ADC Buffer Packing logic. Even in SW override mode, this register will indicate the ping-pong select signal generated from the ADC Buffer Packing logic and not the override value."]
pub type AdcbufpiposelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCBUF_RST` reader - 17:17\\]
Writing 1'b1 : Resets ADC BUFFER Control logic. Writing 1'b0: Releases the reset for ADC BUFFER control logic."]
pub type AdcbufRstR = crate :: BitReader ; # [doc = "Field `ADCBUF_RST` writer - 17:17\\]
Writing 1'b1 : Resets ADC BUFFER Control logic. Writing 1'b0: Releases the reset for ADC BUFFER control logic."]
pub type AdcbufRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
TI Internal Feature Write source for ADC Buffer. 0 --> DFE, 1 --> HWASS Interconnect"]
# [inline (always)]
pub fn adcbufwrsource (& self) -> AdcbufwrsourceR { AdcbufwrsourceR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TI Internal Feature Inversion control for ADC Buffer Ping-pong select. By default ADC Buffer write starts with Pong write. By setting this bit to 1, it will start from Ping write after reset."]
# [inline (always)]
pub fn adcbufpiposelinv (& self) -> AdcbufpiposelinvR { AdcbufpiposelinvR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Enable for Rx0 write"]
# [inline (always)]
pub fn rx0en (& self) -> Rx0enR { Rx0enR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Enable for Rx1 write"]
# [inline (always)]
pub fn rx1en (& self) -> Rx1enR { Rx1enR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Enable for Rx2 write"]
# [inline (always)]
pub fn rx2en (& self) -> Rx2enR { Rx2enR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
TI Reserved"]
# [inline (always)]
pub fn rx3en (& self) -> Rx3enR { Rx3enR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
TI Internal Feature Override control for ADC Buffer Ping Pong select"]
# [inline (always)]
pub fn adcbufpipoovrcnt (& self) -> AdcbufpipoovrcntR { AdcbufpipoovrcntR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
TI Internal Feature SW override value for ADC Buffer Ping Pong select"]
# [inline (always)]
pub fn adcbufpipoovrval (& self) -> AdcbufpipoovrvalR { AdcbufpipoovrvalR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Continuous mode enable for ADC Buffer. This is set when a fixed number of samples have to be stored in Ping/Pong and not depend on Chirp time-lines (Eg: Analog Lab characterization to stream out continuous data from DFE). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
# [inline (always)]
pub fn adcbufcontmodeen (& self) -> AdcbufcontmodeenR { AdcbufcontmodeenR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Start Pulse for Continuous mode. The data capture will start from Address 0 once this register is set. All the other configurations like Enable, Sample Count are expected to be programmed before this pulse. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
# [inline (always)]
pub fn adcbufcontstrtpl (& self) -> AdcbufcontstrtplR { AdcbufcontstrtplR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Stop Pulse for Continuous mode. The data capture will stop once this register is set. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
# [inline (always)]
pub fn adcbufcontstoppl (& self) -> AdcbufcontstopplR { AdcbufcontstopplR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
TI Internal Feature Ping-pong select value from ADC Buffer Packing logic. Even in SW override mode, this register will indicate the ping-pong select signal generated from the ADC Buffer Packing logic and not the override value."]
# [inline (always)]
pub fn adcbufpiposel (& self) -> AdcbufpiposelR { AdcbufpiposelR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Writing 1'b1 : Resets ADC BUFFER Control logic. Writing 1'b0: Releases the reset for ADC BUFFER control logic."]
# [inline (always)]
pub fn adcbuf_rst (& self) -> AdcbufRstR { AdcbufRstR :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
TI Internal Feature Write source for ADC Buffer. 0 --> DFE, 1 --> HWASS Interconnect"]
# [inline (always)]
# [must_use]
pub fn adcbufwrsource (& mut self) -> AdcbufwrsourceW < Adcbufcfg1Spec > { AdcbufwrsourceW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TI Internal Feature Inversion control for ADC Buffer Ping-pong select. By default ADC Buffer write starts with Pong write. By setting this bit to 1, it will start from Ping write after reset."]
# [inline (always)]
# [must_use]
pub fn adcbufpiposelinv (& mut self) -> AdcbufpiposelinvW < Adcbufcfg1Spec > { AdcbufpiposelinvW :: new (self , 1) } # [doc = "Bit 6 - 6:6\\]
Enable for Rx0 write"]
# [inline (always)]
# [must_use]
pub fn rx0en (& mut self) -> Rx0enW < Adcbufcfg1Spec > { Rx0enW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Enable for Rx1 write"]
# [inline (always)]
# [must_use]
pub fn rx1en (& mut self) -> Rx1enW < Adcbufcfg1Spec > { Rx1enW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Enable for Rx2 write"]
# [inline (always)]
# [must_use]
pub fn rx2en (& mut self) -> Rx2enW < Adcbufcfg1Spec > { Rx2enW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
TI Reserved"]
# [inline (always)]
# [must_use]
pub fn rx3en (& mut self) -> Rx3enW < Adcbufcfg1Spec > { Rx3enW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
TI Internal Feature Override control for ADC Buffer Ping Pong select"]
# [inline (always)]
# [must_use]
pub fn adcbufpipoovrcnt (& mut self) -> AdcbufpipoovrcntW < Adcbufcfg1Spec > { AdcbufpipoovrcntW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
TI Internal Feature SW override value for ADC Buffer Ping Pong select"]
# [inline (always)]
# [must_use]
pub fn adcbufpipoovrval (& mut self) -> AdcbufpipoovrvalW < Adcbufcfg1Spec > { AdcbufpipoovrvalW :: new (self , 11) } # [doc = "Bit 13 - 13:13\\]
Continuous mode enable for ADC Buffer. This is set when a fixed number of samples have to be stored in Ping/Pong and not depend on Chirp time-lines (Eg: Analog Lab characterization to stream out continuous data from DFE). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
# [inline (always)]
# [must_use]
pub fn adcbufcontmodeen (& mut self) -> AdcbufcontmodeenW < Adcbufcfg1Spec > { AdcbufcontmodeenW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Start Pulse for Continuous mode. The data capture will start from Address 0 once this register is set. All the other configurations like Enable, Sample Count are expected to be programmed before this pulse. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
# [inline (always)]
# [must_use]
pub fn adcbufcontstrtpl (& mut self) -> AdcbufcontstrtplW < Adcbufcfg1Spec > { AdcbufcontstrtplW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Stop Pulse for Continuous mode. The data capture will stop once this register is set. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse"]
# [inline (always)]
# [must_use]
pub fn adcbufcontstoppl (& mut self) -> AdcbufcontstopplW < Adcbufcfg1Spec > { AdcbufcontstopplW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
TI Internal Feature Ping-pong select value from ADC Buffer Packing logic. Even in SW override mode, this register will indicate the ping-pong select signal generated from the ADC Buffer Packing logic and not the override value."]
# [inline (always)]
# [must_use]
pub fn adcbufpiposel (& mut self) -> AdcbufpiposelW < Adcbufcfg1Spec > { AdcbufpiposelW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Writing 1'b1 : Resets ADC BUFFER Control logic. Writing 1'b0: Releases the reset for ADC BUFFER control logic."]
# [inline (always)]
# [must_use]
pub fn adcbuf_rst (& mut self) -> AdcbufRstW < Adcbufcfg1Spec > { AdcbufRstW :: new (self , 17) } } # [doc = "ADCBUFCFG1\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adcbufcfg1Spec ; impl crate :: RegisterSpec for Adcbufcfg1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbufcfg1::R`](R) reader structure"]
impl crate :: Readable for Adcbufcfg1Spec { } # [doc = "`write(|w| ..)` method takes [`adcbufcfg1::W`](W) writer structure"]
impl crate :: Writable for Adcbufcfg1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFCFG1 to value 0"]
impl crate :: Resettable for Adcbufcfg1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFCFG1_EXTD (rw) register accessor: ADCBUFCFG1_EXTD\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg1_extd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg1_extd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbufcfg1_extd`]
module"]
# [doc (alias = "ADCBUFCFG1_EXTD")]
pub type Adcbufcfg1Extd = crate :: Reg < adcbufcfg1_extd :: Adcbufcfg1ExtdSpec > ; # [doc = "ADCBUFCFG1_EXTD"]
pub mod adcbufcfg1_extd { # [doc = "Register `ADCBUFCFG1_EXTD` reader"]
pub type R = crate :: R < Adcbufcfg1ExtdSpec > ; # [doc = "Register `ADCBUFCFG1_EXTD` writer"]
pub type W = crate :: W < Adcbufcfg1ExtdSpec > ; # [doc = "Field `ADCBUFINTGENDLY` reader - 31:0\\]
TI Intenal Feature. No of clocks to delay the ping-pong switch and interrupt generation w.r.t ADC Valid fall pulse. This will enable dithering the DSP activity for successive ping-pong switch cycles. This will not delay the ping pong toggle which will happen immediately after ADC Valid fall."]
pub type AdcbufintgendlyR = crate :: FieldReader < u32 > ; # [doc = "Field `ADCBUFINTGENDLY` writer - 31:0\\]
TI Intenal Feature. No of clocks to delay the ping-pong switch and interrupt generation w.r.t ADC Valid fall pulse. This will enable dithering the DSP activity for successive ping-pong switch cycles. This will not delay the ping pong toggle which will happen immediately after ADC Valid fall."]
pub type AdcbufintgendlyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI Intenal Feature. No of clocks to delay the ping-pong switch and interrupt generation w.r.t ADC Valid fall pulse. This will enable dithering the DSP activity for successive ping-pong switch cycles. This will not delay the ping pong toggle which will happen immediately after ADC Valid fall."]
# [inline (always)]
pub fn adcbufintgendly (& self) -> AdcbufintgendlyR { AdcbufintgendlyR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI Intenal Feature. No of clocks to delay the ping-pong switch and interrupt generation w.r.t ADC Valid fall pulse. This will enable dithering the DSP activity for successive ping-pong switch cycles. This will not delay the ping pong toggle which will happen immediately after ADC Valid fall."]
# [inline (always)]
# [must_use]
pub fn adcbufintgendly (& mut self) -> AdcbufintgendlyW < Adcbufcfg1ExtdSpec > { AdcbufintgendlyW :: new (self , 0) } } # [doc = "ADCBUFCFG1_EXTD\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg1_extd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg1_extd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adcbufcfg1ExtdSpec ; impl crate :: RegisterSpec for Adcbufcfg1ExtdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbufcfg1_extd::R`](R) reader structure"]
impl crate :: Readable for Adcbufcfg1ExtdSpec { } # [doc = "`write(|w| ..)` method takes [`adcbufcfg1_extd::W`](W) writer structure"]
impl crate :: Writable for Adcbufcfg1ExtdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFCFG1_EXTD to value 0"]
impl crate :: Resettable for Adcbufcfg1ExtdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFCFG2 (rw) register accessor: ADCBUFCFG2\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbufcfg2`]
module"]
# [doc (alias = "ADCBUFCFG2")]
pub type Adcbufcfg2 = crate :: Reg < adcbufcfg2 :: Adcbufcfg2Spec > ; # [doc = "ADCBUFCFG2"]
pub mod adcbufcfg2 { # [doc = "Register `ADCBUFCFG2` reader"]
pub type R = crate :: R < Adcbufcfg2Spec > ; # [doc = "Register `ADCBUFCFG2` writer"]
pub type W = crate :: W < Adcbufcfg2Spec > ; # [doc = "Field `ADCBUFADDRX0` reader - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx0 writes in Non-interleaved mode."]
pub type Adcbufaddrx0R = crate :: FieldReader < u16 > ; # [doc = "Field `ADCBUFADDRX0` writer - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx0 writes in Non-interleaved mode."]
pub type Adcbufaddrx0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `ADCBUFADDRX1` reader - 26:16\\]
128 bit Address offset to be added to the internal address pointer for Rx1 writes in Non-interleaved mode."]
pub type Adcbufaddrx1R = crate :: FieldReader < u16 > ; # [doc = "Field `ADCBUFADDRX1` writer - 26:16\\]
128 bit Address offset to be added to the internal address pointer for Rx1 writes in Non-interleaved mode."]
pub type Adcbufaddrx1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:10 - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx0 writes in Non-interleaved mode."]
# [inline (always)]
pub fn adcbufaddrx0 (& self) -> Adcbufaddrx0R { Adcbufaddrx0R :: new ((self . bits & 0x07ff) as u16) } # [doc = "Bits 16:26 - 26:16\\]
128 bit Address offset to be added to the internal address pointer for Rx1 writes in Non-interleaved mode."]
# [inline (always)]
pub fn adcbufaddrx1 (& self) -> Adcbufaddrx1R { Adcbufaddrx1R :: new (((self . bits >> 16) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:10 - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx0 writes in Non-interleaved mode."]
# [inline (always)]
# [must_use]
pub fn adcbufaddrx0 (& mut self) -> Adcbufaddrx0W < Adcbufcfg2Spec > { Adcbufaddrx0W :: new (self , 0) } # [doc = "Bits 16:26 - 26:16\\]
128 bit Address offset to be added to the internal address pointer for Rx1 writes in Non-interleaved mode."]
# [inline (always)]
# [must_use]
pub fn adcbufaddrx1 (& mut self) -> Adcbufaddrx1W < Adcbufcfg2Spec > { Adcbufaddrx1W :: new (self , 16) } } # [doc = "ADCBUFCFG2\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adcbufcfg2Spec ; impl crate :: RegisterSpec for Adcbufcfg2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbufcfg2::R`](R) reader structure"]
impl crate :: Readable for Adcbufcfg2Spec { } # [doc = "`write(|w| ..)` method takes [`adcbufcfg2::W`](W) writer structure"]
impl crate :: Writable for Adcbufcfg2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFCFG2 to value 0"]
impl crate :: Resettable for Adcbufcfg2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFCFG3 (rw) register accessor: ADCBUFCFG3\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbufcfg3`]
module"]
# [doc (alias = "ADCBUFCFG3")]
pub type Adcbufcfg3 = crate :: Reg < adcbufcfg3 :: Adcbufcfg3Spec > ; # [doc = "ADCBUFCFG3"]
pub mod adcbufcfg3 { # [doc = "Register `ADCBUFCFG3` reader"]
pub type R = crate :: R < Adcbufcfg3Spec > ; # [doc = "Register `ADCBUFCFG3` writer"]
pub type W = crate :: W < Adcbufcfg3Spec > ; # [doc = "Field `ADCBUFADDRX2` reader - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx2 writes in Non-interleaved mode."]
pub type Adcbufaddrx2R = crate :: FieldReader < u16 > ; # [doc = "Field `ADCBUFADDRX2` writer - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx2 writes in Non-interleaved mode."]
pub type Adcbufaddrx2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `ADCBUFADDRX3` reader - 26:16\\]
TI Reserved"]
pub type Adcbufaddrx3R = crate :: FieldReader < u16 > ; # [doc = "Field `ADCBUFADDRX3` writer - 26:16\\]
TI Reserved"]
pub type Adcbufaddrx3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R { # [doc = "Bits 0:10 - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx2 writes in Non-interleaved mode."]
# [inline (always)]
pub fn adcbufaddrx2 (& self) -> Adcbufaddrx2R { Adcbufaddrx2R :: new ((self . bits & 0x07ff) as u16) } # [doc = "Bits 16:26 - 26:16\\]
TI Reserved"]
# [inline (always)]
pub fn adcbufaddrx3 (& self) -> Adcbufaddrx3R { Adcbufaddrx3R :: new (((self . bits >> 16) & 0x07ff) as u16) } } impl W { # [doc = "Bits 0:10 - 10:0\\]
128 bit Address offset to be added to the internal address pointer for Rx2 writes in Non-interleaved mode."]
# [inline (always)]
# [must_use]
pub fn adcbufaddrx2 (& mut self) -> Adcbufaddrx2W < Adcbufcfg3Spec > { Adcbufaddrx2W :: new (self , 0) } # [doc = "Bits 16:26 - 26:16\\]
TI Reserved"]
# [inline (always)]
# [must_use]
pub fn adcbufaddrx3 (& mut self) -> Adcbufaddrx3W < Adcbufcfg3Spec > { Adcbufaddrx3W :: new (self , 16) } } # [doc = "ADCBUFCFG3\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adcbufcfg3Spec ; impl crate :: RegisterSpec for Adcbufcfg3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbufcfg3::R`](R) reader structure"]
impl crate :: Readable for Adcbufcfg3Spec { } # [doc = "`write(|w| ..)` method takes [`adcbufcfg3::W`](W) writer structure"]
impl crate :: Writable for Adcbufcfg3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFCFG3 to value 0"]
impl crate :: Resettable for Adcbufcfg3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFCFG4 (rw) register accessor: ADCBUFCFG4\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbufcfg4`]
module"]
# [doc (alias = "ADCBUFCFG4")]
pub type Adcbufcfg4 = crate :: Reg < adcbufcfg4 :: Adcbufcfg4Spec > ; # [doc = "ADCBUFCFG4"]
pub mod adcbufcfg4 { # [doc = "Register `ADCBUFCFG4` reader"]
pub type R = crate :: R < Adcbufcfg4Spec > ; # [doc = "Register `ADCBUFCFG4` writer"]
pub type W = crate :: W < Adcbufcfg4Spec > ; # [doc = "Field `ADCBUFSAMPCNT` reader - 15:0\\]
No of samples to store in each Ping and Pong register in continuous mode of ADC Buffer. In real only mode this refers to the number of real samples and in complex mode, this refers to number of complex samples. This refers to the number of samples per channel. This counter increments once for every new sample from DFE (as long as 1 or more channels are enabled). The max allowed value varies depending on other configurations (No of channels enabled and real/complex data). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
pub type AdcbufsampcntR = crate :: FieldReader < u16 > ; # [doc = "Field `ADCBUFSAMPCNT` writer - 15:0\\]
No of samples to store in each Ping and Pong register in continuous mode of ADC Buffer. In real only mode this refers to the number of real samples and in complex mode, this refers to number of complex samples. This refers to the number of samples per channel. This counter increments once for every new sample from DFE (as long as 1 or more channels are enabled). The max allowed value varies depending on other configurations (No of channels enabled and real/complex data). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
pub type AdcbufsampcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `ADCBUFNUMCHRPPING` reader - 20:16\\]
Number of chirps to be stored in Ping / Pong buffer. This register should be programmed with one less than the actual number needed."]
pub type AdcbufnumchrppingR = crate :: FieldReader ; # [doc = "Field `ADCBUFNUMCHRPPING` writer - 20:16\\]
Number of chirps to be stored in Ping / Pong buffer. This register should be programmed with one less than the actual number needed."]
pub type AdcbufnumchrppingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `ADCBUFPNGSELTGLDIS` reader - 30:30\\]
TI Internal Feature 0 --> Delay Interrupt Gen and Ping/Pong toggle together based on cfg_interrupt_gen_delay, 1 --> Delay only Interrupt Gen based on cfg_interrupt_gen_delay. But toggle Ping/Pong select signal as soon as the write is complete."]
pub type AdcbufpngseltgldisR = crate :: BitReader ; # [doc = "Field `ADCBUFPNGSELTGLDIS` writer - 30:30\\]
TI Internal Feature 0 --> Delay Interrupt Gen and Ping/Pong toggle together based on cfg_interrupt_gen_delay, 1 --> Delay only Interrupt Gen based on cfg_interrupt_gen_delay. But toggle Ping/Pong select signal as soon as the write is complete."]
pub type AdcbufpngseltgldisW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
No of samples to store in each Ping and Pong register in continuous mode of ADC Buffer. In real only mode this refers to the number of real samples and in complex mode, this refers to number of complex samples. This refers to the number of samples per channel. This counter increments once for every new sample from DFE (as long as 1 or more channels are enabled). The max allowed value varies depending on other configurations (No of channels enabled and real/complex data). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
# [inline (always)]
pub fn adcbufsampcnt (& self) -> AdcbufsampcntR { AdcbufsampcntR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:20 - 20:16\\]
Number of chirps to be stored in Ping / Pong buffer. This register should be programmed with one less than the actual number needed."]
# [inline (always)]
pub fn adcbufnumchrpping (& self) -> AdcbufnumchrppingR { AdcbufnumchrppingR :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bit 30 - 30:30\\]
TI Internal Feature 0 --> Delay Interrupt Gen and Ping/Pong toggle together based on cfg_interrupt_gen_delay, 1 --> Delay only Interrupt Gen based on cfg_interrupt_gen_delay. But toggle Ping/Pong select signal as soon as the write is complete."]
# [inline (always)]
pub fn adcbufpngseltgldis (& self) -> AdcbufpngseltgldisR { AdcbufpngseltgldisR :: new (((self . bits >> 30) & 1) != 0) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
No of samples to store in each Ping and Pong register in continuous mode of ADC Buffer. In real only mode this refers to the number of real samples and in complex mode, this refers to number of complex samples. This refers to the number of samples per channel. This counter increments once for every new sample from DFE (as long as 1 or more channels are enabled). The max allowed value varies depending on other configurations (No of channels enabled and real/complex data). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode"]
# [inline (always)]
# [must_use]
pub fn adcbufsampcnt (& mut self) -> AdcbufsampcntW < Adcbufcfg4Spec > { AdcbufsampcntW :: new (self , 0) } # [doc = "Bits 16:20 - 20:16\\]
Number of chirps to be stored in Ping / Pong buffer. This register should be programmed with one less than the actual number needed."]
# [inline (always)]
# [must_use]
pub fn adcbufnumchrpping (& mut self) -> AdcbufnumchrppingW < Adcbufcfg4Spec > { AdcbufnumchrppingW :: new (self , 16) } # [doc = "Bit 30 - 30:30\\]
TI Internal Feature 0 --> Delay Interrupt Gen and Ping/Pong toggle together based on cfg_interrupt_gen_delay, 1 --> Delay only Interrupt Gen based on cfg_interrupt_gen_delay. But toggle Ping/Pong select signal as soon as the write is complete."]
# [inline (always)]
# [must_use]
pub fn adcbufpngseltgldis (& mut self) -> AdcbufpngseltgldisW < Adcbufcfg4Spec > { AdcbufpngseltgldisW :: new (self , 30) } } # [doc = "ADCBUFCFG4\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufcfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufcfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adcbufcfg4Spec ; impl crate :: RegisterSpec for Adcbufcfg4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbufcfg4::R`](R) reader structure"]
impl crate :: Readable for Adcbufcfg4Spec { } # [doc = "`write(|w| ..)` method takes [`adcbufcfg4::W`](W) writer structure"]
impl crate :: Writable for Adcbufcfg4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFCFG4 to value 0"]
impl crate :: Resettable for Adcbufcfg4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFINTGENDITHERDLY (rw) register accessor: ADCBUFINTGENDITHERDLY\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufintgenditherdly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufintgenditherdly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbufintgenditherdly`]
module"]
# [doc (alias = "ADCBUFINTGENDITHERDLY")]
pub type Adcbufintgenditherdly = crate :: Reg < adcbufintgenditherdly :: AdcbufintgenditherdlySpec > ; # [doc = "ADCBUFINTGENDITHERDLY"]
pub mod adcbufintgenditherdly { # [doc = "Register `ADCBUFINTGENDITHERDLY` reader"]
pub type R = crate :: R < AdcbufintgenditherdlySpec > ; # [doc = "Register `ADCBUFINTGENDITHERDLY` writer"]
pub type W = crate :: W < AdcbufintgenditherdlySpec > ; # [doc = "Field `ADCBUFINTGENDITHERDLY` reader - 31:0\\]
TI Internal Feature. Additional dithering delay added on the Chirp Avilable interrupt"]
pub type AdcbufintgenditherdlyR = crate :: FieldReader < u32 > ; # [doc = "Field `ADCBUFINTGENDITHERDLY` writer - 31:0\\]
TI Internal Feature. Additional dithering delay added on the Chirp Avilable interrupt"]
pub type AdcbufintgenditherdlyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TI Internal Feature. Additional dithering delay added on the Chirp Avilable interrupt"]
# [inline (always)]
pub fn adcbufintgenditherdly (& self) -> AdcbufintgenditherdlyR { AdcbufintgenditherdlyR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TI Internal Feature. Additional dithering delay added on the Chirp Avilable interrupt"]
# [inline (always)]
# [must_use]
pub fn adcbufintgenditherdly (& mut self) -> AdcbufintgenditherdlyW < AdcbufintgenditherdlySpec > { AdcbufintgenditherdlyW :: new (self , 0) } } # [doc = "ADCBUFINTGENDITHERDLY\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbufintgenditherdly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbufintgenditherdly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbufintgenditherdlySpec ; impl crate :: RegisterSpec for AdcbufintgenditherdlySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbufintgenditherdly::R`](R) reader structure"]
impl crate :: Readable for AdcbufintgenditherdlySpec { } # [doc = "`write(|w| ..)` method takes [`adcbufintgenditherdly::W`](W) writer structure"]
impl crate :: Writable for AdcbufintgenditherdlySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFINTGENDITHERDLY to value 0"]
impl crate :: Resettable for AdcbufintgenditherdlySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFF_PING_MEM_INIT (rw) register accessor: ADCBUFF_PING_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_ping_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_ping_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbuff_ping_mem_init`]
module"]
# [doc (alias = "ADCBUFF_PING_MEM_INIT")]
pub type AdcbuffPingMemInit = crate :: Reg < adcbuff_ping_mem_init :: AdcbuffPingMemInitSpec > ; # [doc = "ADCBUFF_PING_MEM_INIT"]
pub mod adcbuff_ping_mem_init { # [doc = "Register `ADCBUFF_PING_MEM_INIT` reader"]
pub type R = crate :: R < AdcbuffPingMemInitSpec > ; # [doc = "Register `ADCBUFF_PING_MEM_INIT` writer"]
pub type W = crate :: W < AdcbuffPingMemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUFF PING Memory . Value in each row is initialized to 0x00_0000_0000"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUFF PING Memory . Value in each row is initialized to 0x00_0000_0000"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUFF PING Memory . Value in each row is initialized to 0x00_0000_0000"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUFF PING Memory . Value in each row is initialized to 0x00_0000_0000"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < AdcbuffPingMemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "ADCBUFF_PING_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_ping_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_ping_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbuffPingMemInitSpec ; impl crate :: RegisterSpec for AdcbuffPingMemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbuff_ping_mem_init::R`](R) reader structure"]
impl crate :: Readable for AdcbuffPingMemInitSpec { } # [doc = "`write(|w| ..)` method takes [`adcbuff_ping_mem_init::W`](W) writer structure"]
impl crate :: Writable for AdcbuffPingMemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFF_PING_MEM_INIT to value 0"]
impl crate :: Resettable for AdcbuffPingMemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFF_PING_MEM_DONE (rw) register accessor: ADCBUFF_PING_MEM_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_ping_mem_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_ping_mem_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbuff_ping_mem_done`]
module"]
# [doc (alias = "ADCBUFF_PING_MEM_DONE")]
pub type AdcbuffPingMemDone = crate :: Reg < adcbuff_ping_mem_done :: AdcbuffPingMemDoneSpec > ; # [doc = "ADCBUFF_PING_MEM_DONE"]
pub mod adcbuff_ping_mem_done { # [doc = "Register `ADCBUFF_PING_MEM_DONE` reader"]
pub type R = crate :: R < AdcbuffPingMemDoneSpec > ; # [doc = "Register `ADCBUFF_PING_MEM_DONE` writer"]
pub type W = crate :: W < AdcbuffPingMemDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once initialization of ADCBUFF PING Memory is finished. Writing '1' would clear the bit."]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once initialization of ADCBUFF PING Memory is finished. Writing '1' would clear the bit."]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of ADCBUFF PING Memory is finished. Writing '1' would clear the bit."]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of ADCBUFF PING Memory is finished. Writing '1' would clear the bit."]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < AdcbuffPingMemDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "ADCBUFF_PING_MEM_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_ping_mem_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_ping_mem_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbuffPingMemDoneSpec ; impl crate :: RegisterSpec for AdcbuffPingMemDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbuff_ping_mem_done::R`](R) reader structure"]
impl crate :: Readable for AdcbuffPingMemDoneSpec { } # [doc = "`write(|w| ..)` method takes [`adcbuff_ping_mem_done::W`](W) writer structure"]
impl crate :: Writable for AdcbuffPingMemDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFF_PING_MEM_DONE to value 0"]
impl crate :: Resettable for AdcbuffPingMemDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFF_PING_MEM_STATUS (rw) register accessor: ADCBUFF_PING_MEM_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_ping_mem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_ping_mem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbuff_ping_mem_status`]
module"]
# [doc (alias = "ADCBUFF_PING_MEM_STATUS")]
pub type AdcbuffPingMemStatus = crate :: Reg < adcbuff_ping_mem_status :: AdcbuffPingMemStatusSpec > ; # [doc = "ADCBUFF_PING_MEM_STATUS"]
pub mod adcbuff_ping_mem_status { # [doc = "Register `ADCBUFF_PING_MEM_STATUS` reader"]
pub type R = crate :: R < AdcbuffPingMemStatusSpec > ; # [doc = "Register `ADCBUFF_PING_MEM_STATUS` writer"]
pub type W = crate :: W < AdcbuffPingMemStatusSpec > ; # [doc = "Field `mem_init_status` reader - 0:0\\]
1'b0: No initialization is happening for ADCBUF PING Memory 1'b1: Initialization is in progress for ADCBUF PING Memory"]
pub type MemInitStatusR = crate :: BitReader ; # [doc = "Field `mem_init_status` writer - 0:0\\]
1'b0: No initialization is happening for ADCBUF PING Memory 1'b1: Initialization is in progress for ADCBUF PING Memory"]
pub type MemInitStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for ADCBUF PING Memory 1'b1: Initialization is in progress for ADCBUF PING Memory"]
# [inline (always)]
pub fn mem_init_status (& self) -> MemInitStatusR { MemInitStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for ADCBUF PING Memory 1'b1: Initialization is in progress for ADCBUF PING Memory"]
# [inline (always)]
# [must_use]
pub fn mem_init_status (& mut self) -> MemInitStatusW < AdcbuffPingMemStatusSpec > { MemInitStatusW :: new (self , 0) } } # [doc = "ADCBUFF_PING_MEM_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_ping_mem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_ping_mem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbuffPingMemStatusSpec ; impl crate :: RegisterSpec for AdcbuffPingMemStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbuff_ping_mem_status::R`](R) reader structure"]
impl crate :: Readable for AdcbuffPingMemStatusSpec { } # [doc = "`write(|w| ..)` method takes [`adcbuff_ping_mem_status::W`](W) writer structure"]
impl crate :: Writable for AdcbuffPingMemStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFF_PING_MEM_STATUS to value 0"]
impl crate :: Resettable for AdcbuffPingMemStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFF_PONG_MEM_INIT (rw) register accessor: ADCBUFF_PONG_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_pong_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_pong_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbuff_pong_mem_init`]
module"]
# [doc (alias = "ADCBUFF_PONG_MEM_INIT")]
pub type AdcbuffPongMemInit = crate :: Reg < adcbuff_pong_mem_init :: AdcbuffPongMemInitSpec > ; # [doc = "ADCBUFF_PONG_MEM_INIT"]
pub mod adcbuff_pong_mem_init { # [doc = "Register `ADCBUFF_PONG_MEM_INIT` reader"]
pub type R = crate :: R < AdcbuffPongMemInitSpec > ; # [doc = "Register `ADCBUFF_PONG_MEM_INIT` writer"]
pub type W = crate :: W < AdcbuffPongMemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUF PONG Memory . Value in each row is initialized to 0x00_0000_0000"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUF PONG Memory . Value in each row is initialized to 0x00_0000_0000"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUF PONG Memory . Value in each row is initialized to 0x00_0000_0000"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUF PONG Memory . Value in each row is initialized to 0x00_0000_0000"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < AdcbuffPongMemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "ADCBUFF_PONG_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_pong_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_pong_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbuffPongMemInitSpec ; impl crate :: RegisterSpec for AdcbuffPongMemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbuff_pong_mem_init::R`](R) reader structure"]
impl crate :: Readable for AdcbuffPongMemInitSpec { } # [doc = "`write(|w| ..)` method takes [`adcbuff_pong_mem_init::W`](W) writer structure"]
impl crate :: Writable for AdcbuffPongMemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFF_PONG_MEM_INIT to value 0"]
impl crate :: Resettable for AdcbuffPongMemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFF_PONG_MEM_DONE (rw) register accessor: ADCBUFF_PONG_MEM_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_pong_mem_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_pong_mem_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbuff_pong_mem_done`]
module"]
# [doc (alias = "ADCBUFF_PONG_MEM_DONE")]
pub type AdcbuffPongMemDone = crate :: Reg < adcbuff_pong_mem_done :: AdcbuffPongMemDoneSpec > ; # [doc = "ADCBUFF_PONG_MEM_DONE"]
pub mod adcbuff_pong_mem_done { # [doc = "Register `ADCBUFF_PONG_MEM_DONE` reader"]
pub type R = crate :: R < AdcbuffPongMemDoneSpec > ; # [doc = "Register `ADCBUFF_PONG_MEM_DONE` writer"]
pub type W = crate :: W < AdcbuffPongMemDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once initialization of ADCBUF PONG Memory is finished. Writing '1' would clear the bit."]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once initialization of ADCBUF PONG Memory is finished. Writing '1' would clear the bit."]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of ADCBUF PONG Memory is finished. Writing '1' would clear the bit."]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of ADCBUF PONG Memory is finished. Writing '1' would clear the bit."]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < AdcbuffPongMemDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "ADCBUFF_PONG_MEM_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_pong_mem_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_pong_mem_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbuffPongMemDoneSpec ; impl crate :: RegisterSpec for AdcbuffPongMemDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbuff_pong_mem_done::R`](R) reader structure"]
impl crate :: Readable for AdcbuffPongMemDoneSpec { } # [doc = "`write(|w| ..)` method takes [`adcbuff_pong_mem_done::W`](W) writer structure"]
impl crate :: Writable for AdcbuffPongMemDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFF_PONG_MEM_DONE to value 0"]
impl crate :: Resettable for AdcbuffPongMemDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ADCBUFF_PONG_MEM_STATUS (rw) register accessor: ADCBUFF_PONG_MEM_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_pong_mem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_pong_mem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcbuff_pong_mem_status`]
module"]
# [doc (alias = "ADCBUFF_PONG_MEM_STATUS")]
pub type AdcbuffPongMemStatus = crate :: Reg < adcbuff_pong_mem_status :: AdcbuffPongMemStatusSpec > ; # [doc = "ADCBUFF_PONG_MEM_STATUS"]
pub mod adcbuff_pong_mem_status { # [doc = "Register `ADCBUFF_PONG_MEM_STATUS` reader"]
pub type R = crate :: R < AdcbuffPongMemStatusSpec > ; # [doc = "Register `ADCBUFF_PONG_MEM_STATUS` writer"]
pub type W = crate :: W < AdcbuffPongMemStatusSpec > ; # [doc = "Field `mem_init_status` reader - 0:0\\]
1'b0: No initialization is happening for ADCBUF PONG Memory 1'b1: Initialization is in progress for ADCBUF PONG Memory"]
pub type MemInitStatusR = crate :: BitReader ; # [doc = "Field `mem_init_status` writer - 0:0\\]
1'b0: No initialization is happening for ADCBUF PONG Memory 1'b1: Initialization is in progress for ADCBUF PONG Memory"]
pub type MemInitStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for ADCBUF PONG Memory 1'b1: Initialization is in progress for ADCBUF PONG Memory"]
# [inline (always)]
pub fn mem_init_status (& self) -> MemInitStatusR { MemInitStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for ADCBUF PONG Memory 1'b1: Initialization is in progress for ADCBUF PONG Memory"]
# [inline (always)]
# [must_use]
pub fn mem_init_status (& mut self) -> MemInitStatusW < AdcbuffPongMemStatusSpec > { MemInitStatusW :: new (self , 0) } } # [doc = "ADCBUFF_PONG_MEM_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`adcbuff_pong_mem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcbuff_pong_mem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcbuffPongMemStatusSpec ; impl crate :: RegisterSpec for AdcbuffPongMemStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`adcbuff_pong_mem_status::R`](R) reader structure"]
impl crate :: Readable for AdcbuffPongMemStatusSpec { } # [doc = "`write(|w| ..)` method takes [`adcbuff_pong_mem_status::W`](W) writer structure"]
impl crate :: Writable for AdcbuffPongMemStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADCBUFF_PONG_MEM_STATUS to value 0"]
impl crate :: Resettable for AdcbuffPongMemStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM_MEM_INIT (rw) register accessor: HWASS_SHRD_RAM_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_mem_init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_mem_init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram_mem_init`]
module"]
# [doc (alias = "HWASS_SHRD_RAM_MEM_INIT")]
pub type HwassShrdRamMemInit = crate :: Reg < hwass_shrd_ram_mem_init :: HwassShrdRamMemInitSpec > ; # [doc = "HWASS_SHRD_RAM_MEM_INIT"]
pub mod hwass_shrd_ram_mem_init { # [doc = "Register `HWASS_SHRD_RAM_MEM_INIT` reader"]
pub type R = crate :: R < HwassShrdRamMemInitSpec > ; # [doc = "Register `HWASS_SHRD_RAM_MEM_INIT` writer"]
pub type W = crate :: W < HwassShrdRamMemInitSpec > ; # [doc = "Field `mem_init` reader - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of HWASS 160 kb shared memory bank . Value in each row is initialized to 0x00_0000_0000"]
pub type MemInitR = crate :: BitReader ; # [doc = "Field `mem_init` writer - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of HWASS 160 kb shared memory bank . Value in each row is initialized to 0x00_0000_0000"]
pub type MemInitW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of HWASS 160 kb shared memory bank . Value in each row is initialized to 0x00_0000_0000"]
# [inline (always)]
pub fn mem_init (& self) -> MemInitR { MemInitR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Write_pulse bit field: Writing 1'b1 will start initialization of HWASS 160 kb shared memory bank . Value in each row is initialized to 0x00_0000_0000"]
# [inline (always)]
# [must_use]
pub fn mem_init (& mut self) -> MemInitW < HwassShrdRamMemInitSpec > { MemInitW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM_MEM_INIT\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_mem_init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_mem_init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRamMemInitSpec ; impl crate :: RegisterSpec for HwassShrdRamMemInitSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram_mem_init::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRamMemInitSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram_mem_init::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRamMemInitSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM_MEM_INIT to value 0"]
impl crate :: Resettable for HwassShrdRamMemInitSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM_MEM_DONE (rw) register accessor: HWASS_SHRD_RAM_MEM_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_mem_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_mem_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram_mem_done`]
module"]
# [doc (alias = "HWASS_SHRD_RAM_MEM_DONE")]
pub type HwassShrdRamMemDone = crate :: Reg < hwass_shrd_ram_mem_done :: HwassShrdRamMemDoneSpec > ; # [doc = "HWASS_SHRD_RAM_MEM_DONE"]
pub mod hwass_shrd_ram_mem_done { # [doc = "Register `HWASS_SHRD_RAM_MEM_DONE` reader"]
pub type R = crate :: R < HwassShrdRamMemDoneSpec > ; # [doc = "Register `HWASS_SHRD_RAM_MEM_DONE` writer"]
pub type W = crate :: W < HwassShrdRamMemDoneSpec > ; # [doc = "Field `mem_init_done` reader - 0:0\\]
This field will be high once initialization of HWASS 160 kb shared memory bank is finished. Writing '1' would clear the bit."]
pub type MemInitDoneR = crate :: BitReader ; # [doc = "Field `mem_init_done` writer - 0:0\\]
This field will be high once initialization of HWASS 160 kb shared memory bank is finished. Writing '1' would clear the bit."]
pub type MemInitDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of HWASS 160 kb shared memory bank is finished. Writing '1' would clear the bit."]
# [inline (always)]
pub fn mem_init_done (& self) -> MemInitDoneR { MemInitDoneR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high once initialization of HWASS 160 kb shared memory bank is finished. Writing '1' would clear the bit."]
# [inline (always)]
# [must_use]
pub fn mem_init_done (& mut self) -> MemInitDoneW < HwassShrdRamMemDoneSpec > { MemInitDoneW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM_MEM_DONE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_mem_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_mem_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRamMemDoneSpec ; impl crate :: RegisterSpec for HwassShrdRamMemDoneSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram_mem_done::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRamMemDoneSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram_mem_done::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRamMemDoneSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM_MEM_DONE to value 0"]
impl crate :: Resettable for HwassShrdRamMemDoneSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM_MEM_STATUS (rw) register accessor: HWASS_SHRD_RAM_MEM_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_mem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_mem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram_mem_status`]
module"]
# [doc (alias = "HWASS_SHRD_RAM_MEM_STATUS")]
pub type HwassShrdRamMemStatus = crate :: Reg < hwass_shrd_ram_mem_status :: HwassShrdRamMemStatusSpec > ; # [doc = "HWASS_SHRD_RAM_MEM_STATUS"]
pub mod hwass_shrd_ram_mem_status { # [doc = "Register `HWASS_SHRD_RAM_MEM_STATUS` reader"]
pub type R = crate :: R < HwassShrdRamMemStatusSpec > ; # [doc = "Register `HWASS_SHRD_RAM_MEM_STATUS` writer"]
pub type W = crate :: W < HwassShrdRamMemStatusSpec > ; # [doc = "Field `mem_init_status` reader - 0:0\\]
1'b0: No initialization is happening for HWASS 160kb shared memory bank 1'b1: Initialization is in progress for HWASS 160kb shared memory bank"]
pub type MemInitStatusR = crate :: BitReader ; # [doc = "Field `mem_init_status` writer - 0:0\\]
1'b0: No initialization is happening for HWASS 160kb shared memory bank 1'b1: Initialization is in progress for HWASS 160kb shared memory bank"]
pub type MemInitStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for HWASS 160kb shared memory bank 1'b1: Initialization is in progress for HWASS 160kb shared memory bank"]
# [inline (always)]
pub fn mem_init_status (& self) -> MemInitStatusR { MemInitStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
1'b0: No initialization is happening for HWASS 160kb shared memory bank 1'b1: Initialization is in progress for HWASS 160kb shared memory bank"]
# [inline (always)]
# [must_use]
pub fn mem_init_status (& mut self) -> MemInitStatusW < HwassShrdRamMemStatusSpec > { MemInitStatusW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM_MEM_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_mem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_mem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRamMemStatusSpec ; impl crate :: RegisterSpec for HwassShrdRamMemStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram_mem_status::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRamMemStatusSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram_mem_status::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRamMemStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM_MEM_STATUS to value 0"]
impl crate :: Resettable for HwassShrdRamMemStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_MASK (rw) register accessor: HWASS_SHRD_RAM_ACCESS_ERROR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_access_error_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_access_error_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram_access_error_mask`]
module"]
# [doc (alias = "HWASS_SHRD_RAM_ACCESS_ERROR_MASK")]
pub type HwassShrdRamAccessErrorMask = crate :: Reg < hwass_shrd_ram_access_error_mask :: HwassShrdRamAccessErrorMaskSpec > ; # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_MASK"]
pub mod hwass_shrd_ram_access_error_mask { # [doc = "Register `HWASS_SHRD_RAM_ACCESS_ERROR_MASK` reader"]
pub type R = crate :: R < HwassShrdRamAccessErrorMaskSpec > ; # [doc = "Register `HWASS_SHRD_RAM_ACCESS_ERROR_MASK` writer"]
pub type W = crate :: W < HwassShrdRamAccessErrorMaskSpec > ; # [doc = "Field `shmem_access_error_mask` reader - 0:0\\]
When 1'b1 : shared ram access error is masked. 1'b0 : shared ram access error is not masked."]
pub type ShmemAccessErrorMaskR = crate :: BitReader ; # [doc = "Field `shmem_access_error_mask` writer - 0:0\\]
When 1'b1 : shared ram access error is masked. 1'b0 : shared ram access error is not masked."]
pub type ShmemAccessErrorMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
When 1'b1 : shared ram access error is masked. 1'b0 : shared ram access error is not masked."]
# [inline (always)]
pub fn shmem_access_error_mask (& self) -> ShmemAccessErrorMaskR { ShmemAccessErrorMaskR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
When 1'b1 : shared ram access error is masked. 1'b0 : shared ram access error is not masked."]
# [inline (always)]
# [must_use]
pub fn shmem_access_error_mask (& mut self) -> ShmemAccessErrorMaskW < HwassShrdRamAccessErrorMaskSpec > { ShmemAccessErrorMaskW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_access_error_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_access_error_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRamAccessErrorMaskSpec ; impl crate :: RegisterSpec for HwassShrdRamAccessErrorMaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram_access_error_mask::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRamAccessErrorMaskSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram_access_error_mask::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRamAccessErrorMaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM_ACCESS_ERROR_MASK to value 0"]
impl crate :: Resettable for HwassShrdRamAccessErrorMaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS (rw) register accessor: HWASS_SHRD_RAM_ACCESS_ERROR_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_access_error_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_access_error_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram_access_error_status`]
module"]
# [doc (alias = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS")]
pub type HwassShrdRamAccessErrorStatus = crate :: Reg < hwass_shrd_ram_access_error_status :: HwassShrdRamAccessErrorStatusSpec > ; # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS"]
pub mod hwass_shrd_ram_access_error_status { # [doc = "Register `HWASS_SHRD_RAM_ACCESS_ERROR_STATUS` reader"]
pub type R = crate :: R < HwassShrdRamAccessErrorStatusSpec > ; # [doc = "Register `HWASS_SHRD_RAM_ACCESS_ERROR_STATUS` writer"]
pub type W = crate :: W < HwassShrdRamAccessErrorStatusSpec > ; # [doc = "Field `shmem_access_error_status` reader - 0:0\\]
This field will be high whenever the invalid address of shared memory is accessed and the interrupt is not masked."]
pub type ShmemAccessErrorStatusR = crate :: BitReader ; # [doc = "Field `shmem_access_error_status` writer - 0:0\\]
This field will be high whenever the invalid address of shared memory is accessed and the interrupt is not masked."]
pub type ShmemAccessErrorStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This field will be high whenever the invalid address of shared memory is accessed and the interrupt is not masked."]
# [inline (always)]
pub fn shmem_access_error_status (& self) -> ShmemAccessErrorStatusR { ShmemAccessErrorStatusR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This field will be high whenever the invalid address of shared memory is accessed and the interrupt is not masked."]
# [inline (always)]
# [must_use]
pub fn shmem_access_error_status (& mut self) -> ShmemAccessErrorStatusW < HwassShrdRamAccessErrorStatusSpec > { ShmemAccessErrorStatusW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_access_error_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_access_error_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRamAccessErrorStatusSpec ; impl crate :: RegisterSpec for HwassShrdRamAccessErrorStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram_access_error_status::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRamAccessErrorStatusSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram_access_error_status::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRamAccessErrorStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM_ACCESS_ERROR_STATUS to value 0"]
impl crate :: Resettable for HwassShrdRamAccessErrorStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW (rw) register accessor: HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_access_error_status_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_access_error_status_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_shrd_ram_access_error_status_raw`]
module"]
# [doc (alias = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW")]
pub type HwassShrdRamAccessErrorStatusRaw = crate :: Reg < hwass_shrd_ram_access_error_status_raw :: HwassShrdRamAccessErrorStatusRawSpec > ; # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW"]
pub mod hwass_shrd_ram_access_error_status_raw { # [doc = "Register `HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW` reader"]
pub type R = crate :: R < HwassShrdRamAccessErrorStatusRawSpec > ; # [doc = "Register `HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW` writer"]
pub type W = crate :: W < HwassShrdRamAccessErrorStatusRawSpec > ; # [doc = "Field `shmem_access_errror_status_raw` reader - 0:0\\]
Indicates the shared ram access error (raw status). Set irrespective of HWASS_SHRD_RAM_ACCESS_ERROR_MASK bit"]
pub type ShmemAccessErrrorStatusRawR = crate :: BitReader ; # [doc = "Field `shmem_access_errror_status_raw` writer - 0:0\\]
Indicates the shared ram access error (raw status). Set irrespective of HWASS_SHRD_RAM_ACCESS_ERROR_MASK bit"]
pub type ShmemAccessErrrorStatusRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the shared ram access error (raw status). Set irrespective of HWASS_SHRD_RAM_ACCESS_ERROR_MASK bit"]
# [inline (always)]
pub fn shmem_access_errror_status_raw (& self) -> ShmemAccessErrrorStatusRawR { ShmemAccessErrrorStatusRawR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the shared ram access error (raw status). Set irrespective of HWASS_SHRD_RAM_ACCESS_ERROR_MASK bit"]
# [inline (always)]
# [must_use]
pub fn shmem_access_errror_status_raw (& mut self) -> ShmemAccessErrrorStatusRawW < HwassShrdRamAccessErrorStatusRawSpec > { ShmemAccessErrrorStatusRawW :: new (self , 0) } } # [doc = "HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_shrd_ram_access_error_status_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_shrd_ram_access_error_status_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassShrdRamAccessErrorStatusRawSpec ; impl crate :: RegisterSpec for HwassShrdRamAccessErrorStatusRawSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_shrd_ram_access_error_status_raw::R`](R) reader structure"]
impl crate :: Readable for HwassShrdRamAccessErrorStatusRawSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_shrd_ram_access_error_status_raw::W`](W) writer structure"]
impl crate :: Writable for HwassShrdRamAccessErrorStatusRawSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW to value 0"]
impl crate :: Resettable for HwassShrdRamAccessErrorStatusRawSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_EDMA_CLOCK_GATE_CONTROL (rw) register accessor: HWASS_EDMA_CLOCK_GATE_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_edma_clock_gate_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_edma_clock_gate_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_edma_clock_gate_control`]
module"]
# [doc (alias = "HWASS_EDMA_CLOCK_GATE_CONTROL")]
pub type HwassEdmaClockGateControl = crate :: Reg < hwass_edma_clock_gate_control :: HwassEdmaClockGateControlSpec > ; # [doc = "HWASS_EDMA_CLOCK_GATE_CONTROL"]
pub mod hwass_edma_clock_gate_control { # [doc = "Register `HWASS_EDMA_CLOCK_GATE_CONTROL` reader"]
pub type R = crate :: R < HwassEdmaClockGateControlSpec > ; # [doc = "Register `HWASS_EDMA_CLOCK_GATE_CONTROL` writer"]
pub type W = crate :: W < HwassEdmaClockGateControlSpec > ; # [doc = "Field `hwa_edma_clock_gating_en` reader - 2:0\\]
Writing 3'b111 will gate the clock to HWA EDMA.Writing 3'b000 will ungate the clock"]
pub type HwaEdmaClockGatingEnR = crate :: FieldReader ; # [doc = "Field `hwa_edma_clock_gating_en` writer - 2:0\\]
Writing 3'b111 will gate the clock to HWA EDMA.Writing 3'b000 will ungate the clock"]
pub type HwaEdmaClockGatingEnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the clock to HWA EDMA.Writing 3'b000 will ungate the clock"]
# [inline (always)]
pub fn hwa_edma_clock_gating_en (& self) -> HwaEdmaClockGatingEnR { HwaEdmaClockGatingEnR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Writing 3'b111 will gate the clock to HWA EDMA.Writing 3'b000 will ungate the clock"]
# [inline (always)]
# [must_use]
pub fn hwa_edma_clock_gating_en (& mut self) -> HwaEdmaClockGatingEnW < HwassEdmaClockGateControlSpec > { HwaEdmaClockGatingEnW :: new (self , 0) } } # [doc = "HWASS_EDMA_CLOCK_GATE_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_edma_clock_gate_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_edma_clock_gate_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassEdmaClockGateControlSpec ; impl crate :: RegisterSpec for HwassEdmaClockGateControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_edma_clock_gate_control::R`](R) reader structure"]
impl crate :: Readable for HwassEdmaClockGateControlSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_edma_clock_gate_control::W`](W) writer structure"]
impl crate :: Writable for HwassEdmaClockGateControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_EDMA_CLOCK_GATE_CONTROL to value 0"]
impl crate :: Resettable for HwassEdmaClockGateControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HWASS_RAM_160KB_CLOCK_GATE (rw) register accessor: HWASS_RAM_160KB_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_ram_160kb_clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_ram_160kb_clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwass_ram_160kb_clock_gate`]
module"]
# [doc (alias = "HWASS_RAM_160KB_CLOCK_GATE")]
pub type HwassRam160kbClockGate = crate :: Reg < hwass_ram_160kb_clock_gate :: HwassRam160kbClockGateSpec > ; # [doc = "HWASS_RAM_160KB_CLOCK_GATE"]
pub mod hwass_ram_160kb_clock_gate { # [doc = "Register `HWASS_RAM_160KB_CLOCK_GATE` reader"]
pub type R = crate :: R < HwassRam160kbClockGateSpec > ; # [doc = "Register `HWASS_RAM_160KB_CLOCK_GATE` writer"]
pub type W = crate :: W < HwassRam160kbClockGateSpec > ; # [doc = "Field `enable` reader - 2:0\\]
3'b000 : Ungate clock to 160KB RAM 3'b111 : Gate Clock to 160KB RAM"]
pub type EnableR = crate :: FieldReader ; # [doc = "Field `enable` writer - 2:0\\]
3'b000 : Ungate clock to 160KB RAM 3'b111 : Gate Clock to 160KB RAM"]
pub type EnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to 160KB RAM 3'b111 : Gate Clock to 160KB RAM"]
# [inline (always)]
pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
3'b000 : Ungate clock to 160KB RAM 3'b111 : Gate Clock to 160KB RAM"]
# [inline (always)]
# [must_use]
pub fn enable (& mut self) -> EnableW < HwassRam160kbClockGateSpec > { EnableW :: new (self , 0) } } # [doc = "HWASS_RAM_160KB_CLOCK_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`hwass_ram_160kb_clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwass_ram_160kb_clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwassRam160kbClockGateSpec ; impl crate :: RegisterSpec for HwassRam160kbClockGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hwass_ram_160kb_clock_gate::R`](R) reader structure"]
impl crate :: Readable for HwassRam160kbClockGateSpec { } # [doc = "`write(|w| ..)` method takes [`hwass_ram_160kb_clock_gate::W`](W) writer structure"]
impl crate :: Writable for HwassRam160kbClockGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HWASS_RAM_160KB_CLOCK_GATE to value 0"]
impl crate :: Resettable for HwassRam160kbClockGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK0 (rw) register accessor: - KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick0`]
module"]
# [doc (alias = "LOCK0_KICK0")]
pub type Lock0Kick0 = crate :: Reg < lock0_kick0 :: Lock0Kick0Spec > ; # [doc = "- KICK0 component"]
pub mod lock0_kick0 { # [doc = "Register `LOCK0_KICK0` reader"]
pub type R = crate :: R < Lock0Kick0Spec > ; # [doc = "Register `LOCK0_KICK0` writer"]
pub type W = crate :: W < Lock0Kick0Spec > ; # [doc = "Field `KICK0_COMPONENT` reader - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK0_COMPONENT` writer - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
pub fn kick0_component (& self) -> Kick0ComponentR { Kick0ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
# [must_use]
pub fn kick0_component (& mut self) -> Kick0ComponentW < Lock0Kick0Spec > { Kick0ComponentW :: new (self , 0) } } # [doc = "- KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick0Spec ; impl crate :: RegisterSpec for Lock0Kick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick0::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick0Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick0::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK0 to value 0"]
impl crate :: Resettable for Lock0Kick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK1 (rw) register accessor: - KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick1`]
module"]
# [doc (alias = "LOCK0_KICK1")]
pub type Lock0Kick1 = crate :: Reg < lock0_kick1 :: Lock0Kick1Spec > ; # [doc = "- KICK1 component"]
pub mod lock0_kick1 { # [doc = "Register `LOCK0_KICK1` reader"]
pub type R = crate :: R < Lock0Kick1Spec > ; # [doc = "Register `LOCK0_KICK1` writer"]
pub type W = crate :: W < Lock0Kick1Spec > ; # [doc = "Field `KICK1_COMPONENT` reader - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK1_COMPONENT` writer - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
pub fn kick1_component (& self) -> Kick1ComponentR { Kick1ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
# [must_use]
pub fn kick1_component (& mut self) -> Kick1ComponentW < Lock0Kick1Spec > { Kick1ComponentW :: new (self , 0) } } # [doc = "- KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick1Spec ; impl crate :: RegisterSpec for Lock0Kick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick1::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick1Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick1::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK1 to value 0"]
impl crate :: Resettable for Lock0Kick1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_raw_status (rw) register accessor: Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw_status`]
module"]
# [doc (alias = "intr_raw_status")]
pub type IntrRawStatus = crate :: Reg < intr_raw_status :: IntrRawStatusSpec > ; # [doc = "Interrupt Raw Status/Set Register"]
pub mod intr_raw_status { # [doc = "Register `intr_raw_status` reader"]
pub type R = crate :: R < IntrRawStatusSpec > ; # [doc = "Register `intr_raw_status` writer"]
pub type W = crate :: W < IntrRawStatusSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrRawStatusSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrRawStatusSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrRawStatusSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrRawStatusSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrRawStatusSpec ; impl crate :: RegisterSpec for IntrRawStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_raw_status::R`](R) reader structure"]
impl crate :: Readable for IntrRawStatusSpec { } # [doc = "`write(|w| ..)` method takes [`intr_raw_status::W`](W) writer structure"]
impl crate :: Writable for IntrRawStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_raw_status to value 0"]
impl crate :: Resettable for IntrRawStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enabled_status_clear (rw) register accessor: Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enabled_status_clear`]
module"]
# [doc (alias = "intr_enabled_status_clear")]
pub type IntrEnabledStatusClear = crate :: Reg < intr_enabled_status_clear :: IntrEnabledStatusClearSpec > ; # [doc = "Interrupt Enabled Status/Clear register"]
pub mod intr_enabled_status_clear { # [doc = "Register `intr_enabled_status_clear` reader"]
pub type R = crate :: R < IntrEnabledStatusClearSpec > ; # [doc = "Register `intr_enabled_status_clear` writer"]
pub type W = crate :: W < IntrEnabledStatusClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrEnabledStatusClearSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrEnabledStatusClearSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnabledStatusClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnabledStatusClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnabledStatusClearSpec ; impl crate :: RegisterSpec for IntrEnabledStatusClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enabled_status_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnabledStatusClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enabled_status_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnabledStatusClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enabled_status_clear to value 0"]
impl crate :: Resettable for IntrEnabledStatusClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable`]
module"]
# [doc (alias = "intr_enable")]
pub type IntrEnable = crate :: Reg < intr_enable :: IntrEnableSpec > ; # [doc = "Interrupt Enable register"]
pub mod intr_enable { # [doc = "Register `intr_enable` reader"]
pub type R = crate :: R < IntrEnableSpec > ; # [doc = "Register `intr_enable` writer"]
pub type W = crate :: W < IntrEnableSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSpec ; impl crate :: RegisterSpec for IntrEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable to value 0"]
impl crate :: Resettable for IntrEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable_clear (rw) register accessor: Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "intr_enable_clear")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "Interrupt Enable Clear register"]
pub mod intr_enable_clear { # [doc = "Register `intr_enable_clear` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `intr_enable_clear` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableClearSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableClearSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable_clear to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "eoi (rw) register accessor: EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi`]
module"]
# [doc (alias = "eoi")]
pub type Eoi = crate :: Reg < eoi :: EoiSpec > ; # [doc = "EOI register"]
pub mod eoi { # [doc = "Register `eoi` reader"]
pub type R = crate :: R < EoiSpec > ; # [doc = "Register `eoi` writer"]
pub type W = crate :: W < EoiSpec > ; # [doc = "Field `EOI_VECTOR_VALUE_` reader - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_R = crate :: FieldReader ; # [doc = "Field `EOI_VECTOR_VALUE_` writer - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
pub fn eoi_vector_value_ (& self) -> EoiVectorValue_R { EoiVectorValue_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
# [must_use]
pub fn eoi_vector_value_ (& mut self) -> EoiVectorValue_W < EoiSpec > { EoiVectorValue_W :: new (self , 0) } } # [doc = "EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EoiSpec ; impl crate :: RegisterSpec for EoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eoi::R`](R) reader structure"]
impl crate :: Readable for EoiSpec { } # [doc = "`write(|w| ..)` method takes [`eoi::W`](W) writer structure"]
impl crate :: Writable for EoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets eoi to value 0"]
impl crate :: Resettable for EoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_address (rw) register accessor: Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_address`]
module"]
# [doc (alias = "fault_address")]
pub type FaultAddress = crate :: Reg < fault_address :: FaultAddressSpec > ; # [doc = "Fault Address register"]
pub mod fault_address { # [doc = "Register `fault_address` reader"]
pub type R = crate :: R < FaultAddressSpec > ; # [doc = "Register `fault_address` writer"]
pub type W = crate :: W < FaultAddressSpec > ; # [doc = "Field `FAULT_ADDRESS_` reader - 31:0\\]
Fault Address."]
pub type FaultAddress_R = crate :: FieldReader < u32 > ; # [doc = "Field `FAULT_ADDRESS_` writer - 31:0\\]
Fault Address."]
pub type FaultAddress_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
pub fn fault_address_ (& self) -> FaultAddress_R { FaultAddress_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
# [must_use]
pub fn fault_address_ (& mut self) -> FaultAddress_W < FaultAddressSpec > { FaultAddress_W :: new (self , 0) } } # [doc = "Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAddressSpec ; impl crate :: RegisterSpec for FaultAddressSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_address::R`](R) reader structure"]
impl crate :: Readable for FaultAddressSpec { } # [doc = "`write(|w| ..)` method takes [`fault_address::W`](W) writer structure"]
impl crate :: Writable for FaultAddressSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_address to value 0"]
impl crate :: Resettable for FaultAddressSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_type_status (rw) register accessor: Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_type_status`]
module"]
# [doc (alias = "fault_type_status")]
pub type FaultTypeStatus = crate :: Reg < fault_type_status :: FaultTypeStatusSpec > ; # [doc = "Fault Type Status register"]
pub mod fault_type_status { # [doc = "Register `fault_type_status` reader"]
pub type R = crate :: R < FaultTypeStatusSpec > ; # [doc = "Register `fault_type_status` writer"]
pub type W = crate :: W < FaultTypeStatusSpec > ; # [doc = "Field `FAULT_TYPE_10_0000` reader - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000R = crate :: FieldReader ; # [doc = "Field `FAULT_TYPE_10_0000` writer - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NONSECURE_ACCESS_` reader - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_R = crate :: BitReader ; # [doc = "Field `NONSECURE_ACCESS_` writer - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
pub fn fault_type_10_0000 (& self) -> FaultType10_0000R { FaultType10_0000R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
pub fn nonsecure_access_ (& self) -> NonsecureAccess_R { NonsecureAccess_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
# [must_use]
pub fn fault_type_10_0000 (& mut self) -> FaultType10_0000W < FaultTypeStatusSpec > { FaultType10_0000W :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
# [must_use]
pub fn nonsecure_access_ (& mut self) -> NonsecureAccess_W < FaultTypeStatusSpec > { NonsecureAccess_W :: new (self , 6) } } # [doc = "Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultTypeStatusSpec ; impl crate :: RegisterSpec for FaultTypeStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_type_status::R`](R) reader structure"]
impl crate :: Readable for FaultTypeStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_type_status::W`](W) writer structure"]
impl crate :: Writable for FaultTypeStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_type_status to value 0"]
impl crate :: Resettable for FaultTypeStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_attr_status (rw) register accessor: Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_attr_status`]
module"]
# [doc (alias = "fault_attr_status")]
pub type FaultAttrStatus = crate :: Reg < fault_attr_status :: FaultAttrStatusSpec > ; # [doc = "Fault Attribute Status register"]
pub mod fault_attr_status { # [doc = "Register `fault_attr_status` reader"]
pub type R = crate :: R < FaultAttrStatusSpec > ; # [doc = "Register `fault_attr_status` writer"]
pub type W = crate :: W < FaultAttrStatusSpec > ; # [doc = "Field `PRIVILEGE_ID_` reader - 7:0\\]
Privilege ID."]
pub type PrivilegeId_R = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID_` writer - 7:0\\]
Privilege ID."]
pub type PrivilegeId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ROUTE_ID_` reader - 19:8\\]
Route ID."]
pub type RouteId_R = crate :: FieldReader < u16 > ; # [doc = "Field `ROUTE_ID_` writer - 19:8\\]
Route ID."]
pub type RouteId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `XID_` reader - 31:20\\]
XID."]
pub type Xid_R = crate :: FieldReader < u16 > ; # [doc = "Field `XID_` writer - 31:20\\]
XID."]
pub type Xid_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
pub fn privilege_id_ (& self) -> PrivilegeId_R { PrivilegeId_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
pub fn route_id_ (& self) -> RouteId_R { RouteId_R :: new (((self . bits >> 8) & 0x0fff) as u16) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
pub fn xid_ (& self) -> Xid_R { Xid_R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
# [must_use]
pub fn privilege_id_ (& mut self) -> PrivilegeId_W < FaultAttrStatusSpec > { PrivilegeId_W :: new (self , 0) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
# [must_use]
pub fn route_id_ (& mut self) -> RouteId_W < FaultAttrStatusSpec > { RouteId_W :: new (self , 8) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
# [must_use]
pub fn xid_ (& mut self) -> Xid_W < FaultAttrStatusSpec > { Xid_W :: new (self , 20) } } # [doc = "Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAttrStatusSpec ; impl crate :: RegisterSpec for FaultAttrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_attr_status::R`](R) reader structure"]
impl crate :: Readable for FaultAttrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_attr_status::W`](W) writer structure"]
impl crate :: Writable for FaultAttrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_attr_status to value 0"]
impl crate :: Resettable for FaultAttrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_clear (rw) register accessor: Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_clear`]
module"]
# [doc (alias = "fault_clear")]
pub type FaultClear = crate :: Reg < fault_clear :: FaultClearSpec > ; # [doc = "Fault Clear register"]
pub mod fault_clear { # [doc = "Register `fault_clear` reader"]
pub type R = crate :: R < FaultClearSpec > ; # [doc = "Register `fault_clear` writer"]
pub type W = crate :: W < FaultClearSpec > ; # [doc = "Field `FAULT_CLEAR__WRITING` reader - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingR = crate :: BitReader ; # [doc = "Field `FAULT_CLEAR__WRITING` writer - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
pub fn fault_clear__writing (& self) -> FaultClear_WritingR { FaultClear_WritingR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn fault_clear__writing (& mut self) -> FaultClear_WritingW < FaultClearSpec > { FaultClear_WritingW :: new (self , 0) } } # [doc = "Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultClearSpec ; impl crate :: RegisterSpec for FaultClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_clear::R`](R) reader structure"]
impl crate :: Readable for FaultClearSpec { } # [doc = "`write(|w| ..)` method takes [`fault_clear::W`](W) writer structure"]
impl crate :: Writable for FaultClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_clear to value 0"]
impl crate :: Resettable for FaultClearSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_ECC_AGG"]
pub struct AppEccAgg { _marker : PhantomData < * const () > } unsafe impl Send for AppEccAgg { } impl AppEccAgg { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_ecc_agg :: RegisterBlock = 0x56f7_ec00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_ecc_agg :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppEccAgg { type Target = app_ecc_agg :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppEccAgg { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppEccAgg") . finish () } } # [doc = "APP_ECC_AGG"]
pub mod app_ecc_agg { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { aggr_revision : AggrRevision , _reserved1 : [u8 ; 0x04]
, ecc_vector : EccVector , misc_status : MiscStatus , ecc_wrap_revision : EccWrapRevision , control : Control , error_ctrl1 : ErrorCtrl1 , error_ctrl2 : ErrorCtrl2 , error_status1 : ErrorStatus1 , error_status2 : ErrorStatus2 , error_status3 : ErrorStatus3 , _reserved10 : [u8 ; 0x10]
, sec_eoi_reg : SecEoiReg , sec_status_reg0 : SecStatusReg0 , _reserved12 : [u8 ; 0x3c]
, sec_enable_set_reg0 : SecEnableSetReg0 , _reserved13 : [u8 ; 0x3c]
, sec_enable_clr_reg0 : SecEnableClrReg0 , _reserved14 : [u8 ; 0x78]
, ded_eoi_reg : DedEoiReg , ded_status_reg0 : DedStatusReg0 , _reserved16 : [u8 ; 0x3c]
, ded_enable_set_reg0 : DedEnableSetReg0 , _reserved17 : [u8 ; 0x3c]
, ded_enable_clr_reg0 : DedEnableClrReg0 , _reserved18 : [u8 ; 0x3c]
, aggr_enable_set : AggrEnableSet , aggr_enable_clr : AggrEnableClr , aggr_status_set : AggrStatusSet , aggr_status_clr : AggrStatusClr , } impl RegisterBlock { # [doc = "0x00 - Revision parameters"]
# [inline (always)]
pub const fn aggr_revision (& self) -> & AggrRevision { & self . aggr_revision } # [doc = "0x08 - ECC Vector Register"]
# [inline (always)]
pub const fn ecc_vector (& self) -> & EccVector { & self . ecc_vector } # [doc = "0x0c - Misc Status"]
# [inline (always)]
pub const fn misc_status (& self) -> & MiscStatus { & self . misc_status } # [doc = "0x10 - Revision parameters"]
# [inline (always)]
pub const fn ecc_wrap_revision (& self) -> & EccWrapRevision { & self . ecc_wrap_revision } # [doc = "0x14 - ECC Control Register"]
# [inline (always)]
pub const fn control (& self) -> & Control { & self . control } # [doc = "0x18 - ECC Error Control1 Register"]
# [inline (always)]
pub const fn error_ctrl1 (& self) -> & ErrorCtrl1 { & self . error_ctrl1 } # [doc = "0x1c - ECC Error Control2 Register"]
# [inline (always)]
pub const fn error_ctrl2 (& self) -> & ErrorCtrl2 { & self . error_ctrl2 } # [doc = "0x20 - ECC Error Status1 Register"]
# [inline (always)]
pub const fn error_status1 (& self) -> & ErrorStatus1 { & self . error_status1 } # [doc = "0x24 - ECC Error Status2 Register"]
# [inline (always)]
pub const fn error_status2 (& self) -> & ErrorStatus2 { & self . error_status2 } # [doc = "0x28 - ECC Error Status3 Register"]
# [inline (always)]
pub const fn error_status3 (& self) -> & ErrorStatus3 { & self . error_status3 } # [doc = "0x3c - EOI Register"]
# [inline (always)]
pub const fn sec_eoi_reg (& self) -> & SecEoiReg { & self . sec_eoi_reg } # [doc = "0x40 - Interrupt Status Register 0"]
# [inline (always)]
pub const fn sec_status_reg0 (& self) -> & SecStatusReg0 { & self . sec_status_reg0 } # [doc = "0x80 - Interrupt Enable Set Register 0"]
# [inline (always)]
pub const fn sec_enable_set_reg0 (& self) -> & SecEnableSetReg0 { & self . sec_enable_set_reg0 } # [doc = "0xc0 - Interrupt Enable Clear Register 0"]
# [inline (always)]
pub const fn sec_enable_clr_reg0 (& self) -> & SecEnableClrReg0 { & self . sec_enable_clr_reg0 } # [doc = "0x13c - EOI Register"]
# [inline (always)]
pub const fn ded_eoi_reg (& self) -> & DedEoiReg { & self . ded_eoi_reg } # [doc = "0x140 - Interrupt Status Register 0"]
# [inline (always)]
pub const fn ded_status_reg0 (& self) -> & DedStatusReg0 { & self . ded_status_reg0 } # [doc = "0x180 - Interrupt Enable Set Register 0"]
# [inline (always)]
pub const fn ded_enable_set_reg0 (& self) -> & DedEnableSetReg0 { & self . ded_enable_set_reg0 } # [doc = "0x1c0 - Interrupt Enable Clear Register 0"]
# [inline (always)]
pub const fn ded_enable_clr_reg0 (& self) -> & DedEnableClrReg0 { & self . ded_enable_clr_reg0 } # [doc = "0x200 - AGGR interrupt enable set Register"]
# [inline (always)]
pub const fn aggr_enable_set (& self) -> & AggrEnableSet { & self . aggr_enable_set } # [doc = "0x204 - AGGR interrupt enable clear Register"]
# [inline (always)]
pub const fn aggr_enable_clr (& self) -> & AggrEnableClr { & self . aggr_enable_clr } # [doc = "0x208 - AGGR interrupt status set Register"]
# [inline (always)]
pub const fn aggr_status_set (& self) -> & AggrStatusSet { & self . aggr_status_set } # [doc = "0x20c - AGGR interrupt status clear Register"]
# [inline (always)]
pub const fn aggr_status_clr (& self) -> & AggrStatusClr { & self . aggr_status_clr } } # [doc = "AGGR_REVISION (rw) register accessor: Revision parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_revision::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_revision::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_revision`]
module"]
# [doc (alias = "AGGR_REVISION")]
pub type AggrRevision = crate :: Reg < aggr_revision :: AggrRevisionSpec > ; # [doc = "Revision parameters"]
pub mod aggr_revision { # [doc = "Register `AGGR_REVISION` reader"]
pub type R = crate :: R < AggrRevisionSpec > ; # [doc = "Register `AGGR_REVISION` writer"]
pub type W = crate :: W < AggrRevisionSpec > ; # [doc = "Field `REVMIN` reader - 5:0\\]
Minor version - (RO )"]
pub type RevminR = crate :: FieldReader ; # [doc = "Field `REVMIN` writer - 5:0\\]
Minor version - (RO )"]
pub type RevminW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom version - (RO )"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom version - (RO )"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `REVMAJ` reader - 10:8\\]
Major version - (RO )"]
pub type RevmajR = crate :: FieldReader ; # [doc = "Field `REVMAJ` writer - 10:8\\]
Major version - (RO )"]
pub type RevmajW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `REVRTL` reader - 15:11\\]
RTL version - (RO )"]
pub type RevrtlR = crate :: FieldReader ; # [doc = "Field `REVRTL` writer - 15:11\\]
RTL version - (RO )"]
pub type RevrtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `MODULE_ID` reader - 27:16\\]
Module ID - (RO )"]
pub type ModuleIdR = crate :: FieldReader < u16 > ; # [doc = "Field `MODULE_ID` writer - 27:16\\]
Module ID - (RO )"]
pub type ModuleIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `BU` reader - 29:28\\]
bu - (RO )"]
pub type BuR = crate :: FieldReader ; # [doc = "Field `BU` writer - 29:28\\]
bu - (RO )"]
pub type BuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
Scheme - (RO )"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
Scheme - (RO )"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor version - (RO )"]
# [inline (always)]
pub fn revmin (& self) -> RevminR { RevminR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom version - (RO )"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major version - (RO )"]
# [inline (always)]
pub fn revmaj (& self) -> RevmajR { RevmajR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL version - (RO )"]
# [inline (always)]
pub fn revrtl (& self) -> RevrtlR { RevrtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Module ID - (RO )"]
# [inline (always)]
pub fn module_id (& self) -> ModuleIdR { ModuleIdR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
bu - (RO )"]
# [inline (always)]
pub fn bu (& self) -> BuR { BuR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Scheme - (RO )"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor version - (RO )"]
# [inline (always)]
# [must_use]
pub fn revmin (& mut self) -> RevminW < AggrRevisionSpec > { RevminW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom version - (RO )"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < AggrRevisionSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major version - (RO )"]
# [inline (always)]
# [must_use]
pub fn revmaj (& mut self) -> RevmajW < AggrRevisionSpec > { RevmajW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL version - (RO )"]
# [inline (always)]
# [must_use]
pub fn revrtl (& mut self) -> RevrtlW < AggrRevisionSpec > { RevrtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Module ID - (RO )"]
# [inline (always)]
# [must_use]
pub fn module_id (& mut self) -> ModuleIdW < AggrRevisionSpec > { ModuleIdW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
bu - (RO )"]
# [inline (always)]
# [must_use]
pub fn bu (& mut self) -> BuW < AggrRevisionSpec > { BuW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
Scheme - (RO )"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < AggrRevisionSpec > { SchemeW :: new (self , 30) } } # [doc = "Revision parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_revision::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_revision::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrRevisionSpec ; impl crate :: RegisterSpec for AggrRevisionSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_revision::R`](R) reader structure"]
impl crate :: Readable for AggrRevisionSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_revision::W`](W) writer structure"]
impl crate :: Writable for AggrRevisionSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_REVISION to value 0"]
impl crate :: Resettable for AggrRevisionSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECC_VECTOR (rw) register accessor: ECC Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_vector::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_vector::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecc_vector`]
module"]
# [doc (alias = "ECC_VECTOR")]
pub type EccVector = crate :: Reg < ecc_vector :: EccVectorSpec > ; # [doc = "ECC Vector Register"]
pub mod ecc_vector { # [doc = "Register `ECC_VECTOR` reader"]
pub type R = crate :: R < EccVectorSpec > ; # [doc = "Register `ECC_VECTOR` writer"]
pub type W = crate :: W < EccVectorSpec > ; # [doc = "Field `ECC_VECTOR` reader - 10:0\\]
Value written to select the corresponding ECC RAM for control or status - (RW )"]
pub type EccVectorR = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_VECTOR` writer - 10:0\\]
Value written to select the corresponding ECC RAM for control or status - (RW )"]
pub type EccVectorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `RES2` reader - 14:11\\]
RESERVE FIELD"]
pub type Res2R = crate :: FieldReader ; # [doc = "Field `RES2` writer - 14:11\\]
RESERVE FIELD"]
pub type Res2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RD_SVBUS` reader - 15:15\\]
Write 1 to trigger a read on the serial VBUS - (RW )"]
pub type RdSvbusR = crate :: BitReader ; # [doc = "Field `RD_SVBUS` writer - 15:15\\]
Write 1 to trigger a read on the serial VBUS - (RW )"]
pub type RdSvbusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RD_SVBUS_ADDRESS` reader - 23:16\\]
Read address - (RW )"]
pub type RdSvbusAddressR = crate :: FieldReader ; # [doc = "Field `RD_SVBUS_ADDRESS` writer - 23:16\\]
Read address - (RW )"]
pub type RdSvbusAddressW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RD_SVBUS_DONE` reader - 24:24\\]
Status to indicate if read on serial VBUS is complete - (RO )"]
pub type RdSvbusDoneR = crate :: BitReader ; # [doc = "Field `RD_SVBUS_DONE` writer - 24:24\\]
Status to indicate if read on serial VBUS is complete - (RO )"]
pub type RdSvbusDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES1` reader - 31:25\\]
RESERVE FIELD"]
pub type Res1R = crate :: FieldReader ; # [doc = "Field `RES1` writer - 31:25\\]
RESERVE FIELD"]
pub type Res1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:10 - 10:0\\]
Value written to select the corresponding ECC RAM for control or status - (RW )"]
# [inline (always)]
pub fn ecc_vector (& self) -> EccVectorR { EccVectorR :: new ((self . bits & 0x07ff) as u16) } # [doc = "Bits 11:14 - 14:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res2 (& self) -> Res2R { Res2R :: new (((self . bits >> 11) & 0x0f) as u8) } # [doc = "Bit 15 - 15:15\\]
Write 1 to trigger a read on the serial VBUS - (RW )"]
# [inline (always)]
pub fn rd_svbus (& self) -> RdSvbusR { RdSvbusR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - 23:16\\]
Read address - (RW )"]
# [inline (always)]
pub fn rd_svbus_address (& self) -> RdSvbusAddressR { RdSvbusAddressR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 24 - 24:24\\]
Status to indicate if read on serial VBUS is complete - (RO )"]
# [inline (always)]
pub fn rd_svbus_done (& self) -> RdSvbusDoneR { RdSvbusDoneR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:31 - 31:25\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res1 (& self) -> Res1R { Res1R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:10 - 10:0\\]
Value written to select the corresponding ECC RAM for control or status - (RW )"]
# [inline (always)]
# [must_use]
pub fn ecc_vector (& mut self) -> EccVectorW < EccVectorSpec > { EccVectorW :: new (self , 0) } # [doc = "Bits 11:14 - 14:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res2 (& mut self) -> Res2W < EccVectorSpec > { Res2W :: new (self , 11) } # [doc = "Bit 15 - 15:15\\]
Write 1 to trigger a read on the serial VBUS - (RW )"]
# [inline (always)]
# [must_use]
pub fn rd_svbus (& mut self) -> RdSvbusW < EccVectorSpec > { RdSvbusW :: new (self , 15) } # [doc = "Bits 16:23 - 23:16\\]
Read address - (RW )"]
# [inline (always)]
# [must_use]
pub fn rd_svbus_address (& mut self) -> RdSvbusAddressW < EccVectorSpec > { RdSvbusAddressW :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
Status to indicate if read on serial VBUS is complete - (RO )"]
# [inline (always)]
# [must_use]
pub fn rd_svbus_done (& mut self) -> RdSvbusDoneW < EccVectorSpec > { RdSvbusDoneW :: new (self , 24) } # [doc = "Bits 25:31 - 31:25\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res1 (& mut self) -> Res1W < EccVectorSpec > { Res1W :: new (self , 25) } } # [doc = "ECC Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_vector::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_vector::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EccVectorSpec ; impl crate :: RegisterSpec for EccVectorSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecc_vector::R`](R) reader structure"]
impl crate :: Readable for EccVectorSpec { } # [doc = "`write(|w| ..)` method takes [`ecc_vector::W`](W) writer structure"]
impl crate :: Writable for EccVectorSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECC_VECTOR to value 0"]
impl crate :: Resettable for EccVectorSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MISC_STATUS (rw) register accessor: Misc Status\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_status`]
module"]
# [doc (alias = "MISC_STATUS")]
pub type MiscStatus = crate :: Reg < misc_status :: MiscStatusSpec > ; # [doc = "Misc Status"]
pub mod misc_status { # [doc = "Register `MISC_STATUS` reader"]
pub type R = crate :: R < MiscStatusSpec > ; # [doc = "Register `MISC_STATUS` writer"]
pub type W = crate :: W < MiscStatusSpec > ; # [doc = "Field `NUM_RAMS` reader - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator - (RO )"]
pub type NumRamsR = crate :: FieldReader < u16 > ; # [doc = "Field `NUM_RAMS` writer - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator - (RO )"]
pub type NumRamsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `RES3` reader - 31:11\\]
RESERVE FIELD"]
pub type Res3R = crate :: FieldReader < u32 > ; # [doc = "Field `RES3` writer - 31:11\\]
RESERVE FIELD"]
pub type Res3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:10 - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator - (RO )"]
# [inline (always)]
pub fn num_rams (& self) -> NumRamsR { NumRamsR :: new ((self . bits & 0x07ff) as u16) } # [doc = "Bits 11:31 - 31:11\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res3 (& self) -> Res3R { Res3R :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:10 - 10:0\\]
Indicates the number of RAMS serviced by the ECC aggregator - (RO )"]
# [inline (always)]
# [must_use]
pub fn num_rams (& mut self) -> NumRamsW < MiscStatusSpec > { NumRamsW :: new (self , 0) } # [doc = "Bits 11:31 - 31:11\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res3 (& mut self) -> Res3W < MiscStatusSpec > { Res3W :: new (self , 11) } } # [doc = "Misc Status\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscStatusSpec ; impl crate :: RegisterSpec for MiscStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`misc_status::R`](R) reader structure"]
impl crate :: Readable for MiscStatusSpec { } # [doc = "`write(|w| ..)` method takes [`misc_status::W`](W) writer structure"]
impl crate :: Writable for MiscStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MISC_STATUS to value 0"]
impl crate :: Resettable for MiscStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ECC_WRAP_REVISION (rw) register accessor: Revision parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_wrap_revision::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_wrap_revision::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecc_wrap_revision`]
module"]
# [doc (alias = "ECC_WRAP_REVISION")]
pub type EccWrapRevision = crate :: Reg < ecc_wrap_revision :: EccWrapRevisionSpec > ; # [doc = "Revision parameters"]
pub mod ecc_wrap_revision { # [doc = "Register `ECC_WRAP_REVISION` reader"]
pub type R = crate :: R < EccWrapRevisionSpec > ; # [doc = "Register `ECC_WRAP_REVISION` writer"]
pub type W = crate :: W < EccWrapRevisionSpec > ; # [doc = "Field `REVMIN` reader - 5:0\\]
Minor version - (RO )"]
pub type RevminR = crate :: FieldReader ; # [doc = "Field `REVMIN` writer - 5:0\\]
Minor version - (RO )"]
pub type RevminW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom version - (RO )"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom version - (RO )"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `REVMAJ` reader - 10:8\\]
Major version - (RO )"]
pub type RevmajR = crate :: FieldReader ; # [doc = "Field `REVMAJ` writer - 10:8\\]
Major version - (RO )"]
pub type RevmajW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `REVRTL` reader - 15:11\\]
RTL version - (RO )"]
pub type RevrtlR = crate :: FieldReader ; # [doc = "Field `REVRTL` writer - 15:11\\]
RTL version - (RO )"]
pub type RevrtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `MODULE_ID` reader - 27:16\\]
Module ID - (RO )"]
pub type ModuleIdR = crate :: FieldReader < u16 > ; # [doc = "Field `MODULE_ID` writer - 27:16\\]
Module ID - (RO )"]
pub type ModuleIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `BU` reader - 29:28\\]
bu - (RO )"]
pub type BuR = crate :: FieldReader ; # [doc = "Field `BU` writer - 29:28\\]
bu - (RO )"]
pub type BuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
Scheme - (RO )"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
Scheme - (RO )"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor version - (RO )"]
# [inline (always)]
pub fn revmin (& self) -> RevminR { RevminR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom version - (RO )"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major version - (RO )"]
# [inline (always)]
pub fn revmaj (& self) -> RevmajR { RevmajR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL version - (RO )"]
# [inline (always)]
pub fn revrtl (& self) -> RevrtlR { RevrtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Module ID - (RO )"]
# [inline (always)]
pub fn module_id (& self) -> ModuleIdR { ModuleIdR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
bu - (RO )"]
# [inline (always)]
pub fn bu (& self) -> BuR { BuR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Scheme - (RO )"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor version - (RO )"]
# [inline (always)]
# [must_use]
pub fn revmin (& mut self) -> RevminW < EccWrapRevisionSpec > { RevminW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom version - (RO )"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < EccWrapRevisionSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major version - (RO )"]
# [inline (always)]
# [must_use]
pub fn revmaj (& mut self) -> RevmajW < EccWrapRevisionSpec > { RevmajW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL version - (RO )"]
# [inline (always)]
# [must_use]
pub fn revrtl (& mut self) -> RevrtlW < EccWrapRevisionSpec > { RevrtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Module ID - (RO )"]
# [inline (always)]
# [must_use]
pub fn module_id (& mut self) -> ModuleIdW < EccWrapRevisionSpec > { ModuleIdW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
bu - (RO )"]
# [inline (always)]
# [must_use]
pub fn bu (& mut self) -> BuW < EccWrapRevisionSpec > { BuW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
Scheme - (RO )"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < EccWrapRevisionSpec > { SchemeW :: new (self , 30) } } # [doc = "Revision parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_wrap_revision::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_wrap_revision::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EccWrapRevisionSpec ; impl crate :: RegisterSpec for EccWrapRevisionSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ecc_wrap_revision::R`](R) reader structure"]
impl crate :: Readable for EccWrapRevisionSpec { } # [doc = "`write(|w| ..)` method takes [`ecc_wrap_revision::W`](W) writer structure"]
impl crate :: Writable for EccWrapRevisionSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECC_WRAP_REVISION to value 0"]
impl crate :: Resettable for EccWrapRevisionSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CONTROL (rw) register accessor: ECC Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`]
module"]
# [doc (alias = "CONTROL")]
pub type Control = crate :: Reg < control :: ControlSpec > ; # [doc = "ECC Control Register"]
pub mod control { # [doc = "Register `CONTROL` reader"]
pub type R = crate :: R < ControlSpec > ; # [doc = "Register `CONTROL` writer"]
pub type W = crate :: W < ControlSpec > ; # [doc = "Field `ECC_ENABLE` reader - 0:0\\]
Enable ECC - (RW )"]
pub type EccEnableR = crate :: BitReader ; # [doc = "Field `ECC_ENABLE` writer - 0:0\\]
Enable ECC - (RW )"]
pub type EccEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ECC_CHECK` reader - 1:1\\]
Enable ECC check - (RW )"]
pub type EccCheckR = crate :: BitReader ; # [doc = "Field `ECC_CHECK` writer - 1:1\\]
Enable ECC check - (RW )"]
pub type EccCheckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENABLE_RMW` reader - 2:2\\]
Enable rmw - (RW )"]
pub type EnableRmwR = crate :: BitReader ; # [doc = "Field `ENABLE_RMW` writer - 2:2\\]
Enable rmw - (RW )"]
pub type EnableRmwW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE_SEC` reader - 3:3\\]
Force Single Bit Error - (RW )"]
pub type ForceSecR = crate :: BitReader ; # [doc = "Field `FORCE_SEC` writer - 3:3\\]
Force Single Bit Error - (RW )"]
pub type ForceSecW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE_DED` reader - 4:4\\]
Force Double Bit Error - (RW )"]
pub type ForceDedR = crate :: BitReader ; # [doc = "Field `FORCE_DED` writer - 4:4\\]
Force Double Bit Error - (RW )"]
pub type ForceDedW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE_N_ROW` reader - 5:5\\]
Force Error on any RAM read - (RW )"]
pub type ForceNRowR = crate :: BitReader ; # [doc = "Field `FORCE_N_ROW` writer - 5:5\\]
Force Error on any RAM read - (RW )"]
pub type ForceNRowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERROR_ONCE` reader - 6:6\\]
Force Error only once - (RW )"]
pub type ErrorOnceR = crate :: BitReader ; # [doc = "Field `ERROR_ONCE` writer - 6:6\\]
Force Error only once - (RW )"]
pub type ErrorOnceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHECK_PARITY` reader - 7:7\\]
check for parity errors - (RW )"]
pub type CheckParityR = crate :: BitReader ; # [doc = "Field `CHECK_PARITY` writer - 7:7\\]
check for parity errors - (RW )"]
pub type CheckParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHECK_SVBUS_TIMEOUT` reader - 8:8\\]
check for svbus timeout errors - (RW )"]
pub type CheckSvbusTimeoutR = crate :: BitReader ; # [doc = "Field `CHECK_SVBUS_TIMEOUT` writer - 8:8\\]
check for svbus timeout errors - (RW )"]
pub type CheckSvbusTimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES4` reader - 31:9\\]
RESERVE FIELD"]
pub type Res4R = crate :: FieldReader < u32 > ; # [doc = "Field `RES4` writer - 31:9\\]
RESERVE FIELD"]
pub type Res4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Enable ECC - (RW )"]
# [inline (always)]
pub fn ecc_enable (& self) -> EccEnableR { EccEnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Enable ECC check - (RW )"]
# [inline (always)]
pub fn ecc_check (& self) -> EccCheckR { EccCheckR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Enable rmw - (RW )"]
# [inline (always)]
pub fn enable_rmw (& self) -> EnableRmwR { EnableRmwR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Force Single Bit Error - (RW )"]
# [inline (always)]
pub fn force_sec (& self) -> ForceSecR { ForceSecR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Force Double Bit Error - (RW )"]
# [inline (always)]
pub fn force_ded (& self) -> ForceDedR { ForceDedR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Force Error on any RAM read - (RW )"]
# [inline (always)]
pub fn force_n_row (& self) -> ForceNRowR { ForceNRowR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Force Error only once - (RW )"]
# [inline (always)]
pub fn error_once (& self) -> ErrorOnceR { ErrorOnceR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
check for parity errors - (RW )"]
# [inline (always)]
pub fn check_parity (& self) -> CheckParityR { CheckParityR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
check for svbus timeout errors - (RW )"]
# [inline (always)]
pub fn check_svbus_timeout (& self) -> CheckSvbusTimeoutR { CheckSvbusTimeoutR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:31 - 31:9\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res4 (& self) -> Res4R { Res4R :: new ((self . bits >> 9) & 0x007f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Enable ECC - (RW )"]
# [inline (always)]
# [must_use]
pub fn ecc_enable (& mut self) -> EccEnableW < ControlSpec > { EccEnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Enable ECC check - (RW )"]
# [inline (always)]
# [must_use]
pub fn ecc_check (& mut self) -> EccCheckW < ControlSpec > { EccCheckW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Enable rmw - (RW )"]
# [inline (always)]
# [must_use]
pub fn enable_rmw (& mut self) -> EnableRmwW < ControlSpec > { EnableRmwW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Force Single Bit Error - (RW )"]
# [inline (always)]
# [must_use]
pub fn force_sec (& mut self) -> ForceSecW < ControlSpec > { ForceSecW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Force Double Bit Error - (RW )"]
# [inline (always)]
# [must_use]
pub fn force_ded (& mut self) -> ForceDedW < ControlSpec > { ForceDedW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Force Error on any RAM read - (RW )"]
# [inline (always)]
# [must_use]
pub fn force_n_row (& mut self) -> ForceNRowW < ControlSpec > { ForceNRowW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Force Error only once - (RW )"]
# [inline (always)]
# [must_use]
pub fn error_once (& mut self) -> ErrorOnceW < ControlSpec > { ErrorOnceW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
check for parity errors - (RW )"]
# [inline (always)]
# [must_use]
pub fn check_parity (& mut self) -> CheckParityW < ControlSpec > { CheckParityW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
check for svbus timeout errors - (RW )"]
# [inline (always)]
# [must_use]
pub fn check_svbus_timeout (& mut self) -> CheckSvbusTimeoutW < ControlSpec > { CheckSvbusTimeoutW :: new (self , 8) } # [doc = "Bits 9:31 - 31:9\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res4 (& mut self) -> Res4W < ControlSpec > { Res4W :: new (self , 9) } } # [doc = "ECC Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ControlSpec ; impl crate :: RegisterSpec for ControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`control::R`](R) reader structure"]
impl crate :: Readable for ControlSpec { } # [doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
impl crate :: Writable for ControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CONTROL to value 0"]
impl crate :: Resettable for ControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERROR_CTRL1 (rw) register accessor: ECC Error Control1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@error_ctrl1`]
module"]
# [doc (alias = "ERROR_CTRL1")]
pub type ErrorCtrl1 = crate :: Reg < error_ctrl1 :: ErrorCtrl1Spec > ; # [doc = "ECC Error Control1 Register"]
pub mod error_ctrl1 { # [doc = "Register `ERROR_CTRL1` reader"]
pub type R = crate :: R < ErrorCtrl1Spec > ; # [doc = "Register `ERROR_CTRL1` writer"]
pub type W = crate :: W < ErrorCtrl1Spec > ; # [doc = "Field `ECC_ROW` reader - 31:0\\]
Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set - (RW )"]
pub type EccRowR = crate :: FieldReader < u32 > ; # [doc = "Field `ECC_ROW` writer - 31:0\\]
Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set - (RW )"]
pub type EccRowW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set - (RW )"]
# [inline (always)]
pub fn ecc_row (& self) -> EccRowR { EccRowR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ecc_row (& mut self) -> EccRowW < ErrorCtrl1Spec > { EccRowW :: new (self , 0) } } # [doc = "ECC Error Control1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrorCtrl1Spec ; impl crate :: RegisterSpec for ErrorCtrl1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`error_ctrl1::R`](R) reader structure"]
impl crate :: Readable for ErrorCtrl1Spec { } # [doc = "`write(|w| ..)` method takes [`error_ctrl1::W`](W) writer structure"]
impl crate :: Writable for ErrorCtrl1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERROR_CTRL1 to value 0"]
impl crate :: Resettable for ErrorCtrl1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERROR_CTRL2 (rw) register accessor: ECC Error Control2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@error_ctrl2`]
module"]
# [doc (alias = "ERROR_CTRL2")]
pub type ErrorCtrl2 = crate :: Reg < error_ctrl2 :: ErrorCtrl2Spec > ; # [doc = "ECC Error Control2 Register"]
pub mod error_ctrl2 { # [doc = "Register `ERROR_CTRL2` reader"]
pub type R = crate :: R < ErrorCtrl2Spec > ; # [doc = "Register `ERROR_CTRL2` writer"]
pub type W = crate :: W < ErrorCtrl2Spec > ; # [doc = "Field `ECC_BIT1` reader - 15:0\\]
Data bit that needs to be flipped when force_sec is set - (RW )"]
pub type EccBit1R = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_BIT1` writer - 15:0\\]
Data bit that needs to be flipped when force_sec is set - (RW )"]
pub type EccBit1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `ECC_BIT2` reader - 31:16\\]
Data bit that needs to be flipped if double bit error needs to be forced - (RW )"]
pub type EccBit2R = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_BIT2` writer - 31:16\\]
Data bit that needs to be flipped if double bit error needs to be forced - (RW )"]
pub type EccBit2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Data bit that needs to be flipped when force_sec is set - (RW )"]
# [inline (always)]
pub fn ecc_bit1 (& self) -> EccBit1R { EccBit1R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Data bit that needs to be flipped if double bit error needs to be forced - (RW )"]
# [inline (always)]
pub fn ecc_bit2 (& self) -> EccBit2R { EccBit2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Data bit that needs to be flipped when force_sec is set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ecc_bit1 (& mut self) -> EccBit1W < ErrorCtrl2Spec > { EccBit1W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Data bit that needs to be flipped if double bit error needs to be forced - (RW )"]
# [inline (always)]
# [must_use]
pub fn ecc_bit2 (& mut self) -> EccBit2W < ErrorCtrl2Spec > { EccBit2W :: new (self , 16) } } # [doc = "ECC Error Control2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrorCtrl2Spec ; impl crate :: RegisterSpec for ErrorCtrl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`error_ctrl2::R`](R) reader structure"]
impl crate :: Readable for ErrorCtrl2Spec { } # [doc = "`write(|w| ..)` method takes [`error_ctrl2::W`](W) writer structure"]
impl crate :: Writable for ErrorCtrl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERROR_CTRL2 to value 0"]
impl crate :: Resettable for ErrorCtrl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERROR_STATUS1 (rw) register accessor: ECC Error Status1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_status1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_status1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@error_status1`]
module"]
# [doc (alias = "ERROR_STATUS1")]
pub type ErrorStatus1 = crate :: Reg < error_status1 :: ErrorStatus1Spec > ; # [doc = "ECC Error Status1 Register"]
pub mod error_status1 { # [doc = "Register `ERROR_STATUS1` reader"]
pub type R = crate :: R < ErrorStatus1Spec > ; # [doc = "Register `ERROR_STATUS1` writer"]
pub type W = crate :: W < ErrorStatus1Spec > ; # [doc = "Field `ECC_SEC` reader - 1:0\\]
Level Single Bit Error Status - (RW incr)"]
pub type EccSecR = crate :: FieldReader ; # [doc = "Field `ECC_SEC` writer - 1:0\\]
Level Single Bit Error Status - (RW incr)"]
pub type EccSecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECC_DED` reader - 3:2\\]
Level Double Bit Error Status - (RW incr)"]
pub type EccDedR = crate :: FieldReader ; # [doc = "Field `ECC_DED` writer - 3:2\\]
Level Double Bit Error Status - (RW incr)"]
pub type EccDedW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECC_OTHER` reader - 4:4\\]
successive single-bit errors have occurred while a writeback is still pending Level interrupt - (RW"]
pub type EccOtherR = crate :: BitReader ; # [doc = "Field `ECC_OTHER` writer - 4:4\\]
successive single-bit errors have occurred while a writeback is still pending Level interrupt - (RW"]
pub type EccOtherW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITY_ERR` reader - 6:5\\]
Level parity error Error Status - (RW )"]
pub type ParityErrR = crate :: FieldReader ; # [doc = "Field `PARITY_ERR` writer - 6:5\\]
Level parity error Error Status - (RW )"]
pub type ParityErrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CTR_REG_ERR` reader - 7:7\\]
control register error pending Level interrupt - (RW"]
pub type CtrRegErrR = crate :: BitReader ; # [doc = "Field `CTR_REG_ERR` writer - 7:7\\]
control register error pending Level interrupt - (RW"]
pub type CtrRegErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_ECC_SEC` reader - 9:8\\]
Clear Single Bit Error Status - (RW decr)"]
pub type ClrEccSecR = crate :: FieldReader ; # [doc = "Field `CLR_ECC_SEC` writer - 9:8\\]
Clear Single Bit Error Status - (RW decr)"]
pub type ClrEccSecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_ECC_DED` reader - 11:10\\]
Clear Double Bit Error Status - (RW decr)"]
pub type ClrEccDedR = crate :: FieldReader ; # [doc = "Field `CLR_ECC_DED` writer - 11:10\\]
Clear Double Bit Error Status - (RW decr)"]
pub type ClrEccDedW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_ECC_OTHER` reader - 12:12\\]
Clear other Error Status - (RW )"]
pub type ClrEccOtherR = crate :: BitReader ; # [doc = "Field `CLR_ECC_OTHER` writer - 12:12\\]
Clear other Error Status - (RW )"]
pub type ClrEccOtherW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_PARITY_ERR` reader - 14:13\\]
Clear parity Error Status - (RW decr)"]
pub type ClrParityErrR = crate :: FieldReader ; # [doc = "Field `CLR_PARITY_ERR` writer - 14:13\\]
Clear parity Error Status - (RW decr)"]
pub type ClrParityErrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_CTRL_REG_ERR` reader - 15:15\\]
Clear control reg error Error Status you must also re write the contorl ergister itself to clear this - (RW )"]
pub type ClrCtrlRegErrR = crate :: BitReader ; # [doc = "Field `CLR_CTRL_REG_ERR` writer - 15:15\\]
Clear control reg error Error Status you must also re write the contorl ergister itself to clear this - (RW )"]
pub type ClrCtrlRegErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ECC_BIT1` reader - 31:16\\]
Data bit that corresponds to the single-bit error - (RO )"]
pub type EccBit1R = crate :: FieldReader < u16 > ; # [doc = "Field `ECC_BIT1` writer - 31:16\\]
Data bit that corresponds to the single-bit error - (RO )"]
pub type EccBit1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Level Single Bit Error Status - (RW incr)"]
# [inline (always)]
pub fn ecc_sec (& self) -> EccSecR { EccSecR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Level Double Bit Error Status - (RW incr)"]
# [inline (always)]
pub fn ecc_ded (& self) -> EccDedR { EccDedR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bit 4 - 4:4\\]
successive single-bit errors have occurred while a writeback is still pending Level interrupt - (RW"]
# [inline (always)]
pub fn ecc_other (& self) -> EccOtherR { EccOtherR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:6 - 6:5\\]
Level parity error Error Status - (RW )"]
# [inline (always)]
pub fn parity_err (& self) -> ParityErrR { ParityErrR :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - 7:7\\]
control register error pending Level interrupt - (RW"]
# [inline (always)]
pub fn ctr_reg_err (& self) -> CtrRegErrR { CtrRegErrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - 9:8\\]
Clear Single Bit Error Status - (RW decr)"]
# [inline (always)]
pub fn clr_ecc_sec (& self) -> ClrEccSecR { ClrEccSecR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Clear Double Bit Error Status - (RW decr)"]
# [inline (always)]
pub fn clr_ecc_ded (& self) -> ClrEccDedR { ClrEccDedR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - 12:12\\]
Clear other Error Status - (RW )"]
# [inline (always)]
pub fn clr_ecc_other (& self) -> ClrEccOtherR { ClrEccOtherR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - 14:13\\]
Clear parity Error Status - (RW decr)"]
# [inline (always)]
pub fn clr_parity_err (& self) -> ClrParityErrR { ClrParityErrR :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - 15:15\\]
Clear control reg error Error Status you must also re write the contorl ergister itself to clear this - (RW )"]
# [inline (always)]
pub fn clr_ctrl_reg_err (& self) -> ClrCtrlRegErrR { ClrCtrlRegErrR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Data bit that corresponds to the single-bit error - (RO )"]
# [inline (always)]
pub fn ecc_bit1 (& self) -> EccBit1R { EccBit1R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Level Single Bit Error Status - (RW incr)"]
# [inline (always)]
# [must_use]
pub fn ecc_sec (& mut self) -> EccSecW < ErrorStatus1Spec > { EccSecW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Level Double Bit Error Status - (RW incr)"]
# [inline (always)]
# [must_use]
pub fn ecc_ded (& mut self) -> EccDedW < ErrorStatus1Spec > { EccDedW :: new (self , 2) } # [doc = "Bit 4 - 4:4\\]
successive single-bit errors have occurred while a writeback is still pending Level interrupt - (RW"]
# [inline (always)]
# [must_use]
pub fn ecc_other (& mut self) -> EccOtherW < ErrorStatus1Spec > { EccOtherW :: new (self , 4) } # [doc = "Bits 5:6 - 6:5\\]
Level parity error Error Status - (RW )"]
# [inline (always)]
# [must_use]
pub fn parity_err (& mut self) -> ParityErrW < ErrorStatus1Spec > { ParityErrW :: new (self , 5) } # [doc = "Bit 7 - 7:7\\]
control register error pending Level interrupt - (RW"]
# [inline (always)]
# [must_use]
pub fn ctr_reg_err (& mut self) -> CtrRegErrW < ErrorStatus1Spec > { CtrRegErrW :: new (self , 7) } # [doc = "Bits 8:9 - 9:8\\]
Clear Single Bit Error Status - (RW decr)"]
# [inline (always)]
# [must_use]
pub fn clr_ecc_sec (& mut self) -> ClrEccSecW < ErrorStatus1Spec > { ClrEccSecW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Clear Double Bit Error Status - (RW decr)"]
# [inline (always)]
# [must_use]
pub fn clr_ecc_ded (& mut self) -> ClrEccDedW < ErrorStatus1Spec > { ClrEccDedW :: new (self , 10) } # [doc = "Bit 12 - 12:12\\]
Clear other Error Status - (RW )"]
# [inline (always)]
# [must_use]
pub fn clr_ecc_other (& mut self) -> ClrEccOtherW < ErrorStatus1Spec > { ClrEccOtherW :: new (self , 12) } # [doc = "Bits 13:14 - 14:13\\]
Clear parity Error Status - (RW decr)"]
# [inline (always)]
# [must_use]
pub fn clr_parity_err (& mut self) -> ClrParityErrW < ErrorStatus1Spec > { ClrParityErrW :: new (self , 13) } # [doc = "Bit 15 - 15:15\\]
Clear control reg error Error Status you must also re write the contorl ergister itself to clear this - (RW )"]
# [inline (always)]
# [must_use]
pub fn clr_ctrl_reg_err (& mut self) -> ClrCtrlRegErrW < ErrorStatus1Spec > { ClrCtrlRegErrW :: new (self , 15) } # [doc = "Bits 16:31 - 31:16\\]
Data bit that corresponds to the single-bit error - (RO )"]
# [inline (always)]
# [must_use]
pub fn ecc_bit1 (& mut self) -> EccBit1W < ErrorStatus1Spec > { EccBit1W :: new (self , 16) } } # [doc = "ECC Error Status1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_status1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_status1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrorStatus1Spec ; impl crate :: RegisterSpec for ErrorStatus1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`error_status1::R`](R) reader structure"]
impl crate :: Readable for ErrorStatus1Spec { } # [doc = "`write(|w| ..)` method takes [`error_status1::W`](W) writer structure"]
impl crate :: Writable for ErrorStatus1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERROR_STATUS1 to value 0"]
impl crate :: Resettable for ErrorStatus1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERROR_STATUS2 (rw) register accessor: ECC Error Status2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_status2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_status2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@error_status2`]
module"]
# [doc (alias = "ERROR_STATUS2")]
pub type ErrorStatus2 = crate :: Reg < error_status2 :: ErrorStatus2Spec > ; # [doc = "ECC Error Status2 Register"]
pub mod error_status2 { # [doc = "Register `ERROR_STATUS2` reader"]
pub type R = crate :: R < ErrorStatus2Spec > ; # [doc = "Register `ERROR_STATUS2` writer"]
pub type W = crate :: W < ErrorStatus2Spec > ; # [doc = "Field `ECC_ROW` reader - 31:0\\]
Row address where the single or double-bit error has occurred - (RO )"]
pub type EccRowR = crate :: FieldReader < u32 > ; # [doc = "Field `ECC_ROW` writer - 31:0\\]
Row address where the single or double-bit error has occurred - (RO )"]
pub type EccRowW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Row address where the single or double-bit error has occurred - (RO )"]
# [inline (always)]
pub fn ecc_row (& self) -> EccRowR { EccRowR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Row address where the single or double-bit error has occurred - (RO )"]
# [inline (always)]
# [must_use]
pub fn ecc_row (& mut self) -> EccRowW < ErrorStatus2Spec > { EccRowW :: new (self , 0) } } # [doc = "ECC Error Status2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_status2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_status2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrorStatus2Spec ; impl crate :: RegisterSpec for ErrorStatus2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`error_status2::R`](R) reader structure"]
impl crate :: Readable for ErrorStatus2Spec { } # [doc = "`write(|w| ..)` method takes [`error_status2::W`](W) writer structure"]
impl crate :: Writable for ErrorStatus2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERROR_STATUS2 to value 0"]
impl crate :: Resettable for ErrorStatus2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ERROR_STATUS3 (rw) register accessor: ECC Error Status3 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_status3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_status3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@error_status3`]
module"]
# [doc (alias = "ERROR_STATUS3")]
pub type ErrorStatus3 = crate :: Reg < error_status3 :: ErrorStatus3Spec > ; # [doc = "ECC Error Status3 Register"]
pub mod error_status3 { # [doc = "Register `ERROR_STATUS3` reader"]
pub type R = crate :: R < ErrorStatus3Spec > ; # [doc = "Register `ERROR_STATUS3` writer"]
pub type W = crate :: W < ErrorStatus3Spec > ; # [doc = "Field `WB_PEND` reader - 0:0\\]
delayed write back pending Status - (RO )"]
pub type WbPendR = crate :: BitReader ; # [doc = "Field `WB_PEND` writer - 0:0\\]
delayed write back pending Status - (RO )"]
pub type WbPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SVBUS_TIMEOUT_ERR` reader - 1:1\\]
Level svbus timeout error Error Status - (RW )"]
pub type SvbusTimeoutErrR = crate :: BitReader ; # [doc = "Field `SVBUS_TIMEOUT_ERR` writer - 1:1\\]
Level svbus timeout error Error Status - (RW )"]
pub type SvbusTimeoutErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES6` reader - 8:2\\]
RESERVE FIELD"]
pub type Res6R = crate :: FieldReader ; # [doc = "Field `RES6` writer - 8:2\\]
RESERVE FIELD"]
pub type Res6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `CLR_SVBUS_TIMEOUT_ERR` reader - 9:9\\]
Clear svbus timeout Error Status - (RW )"]
pub type ClrSvbusTimeoutErrR = crate :: BitReader ; # [doc = "Field `CLR_SVBUS_TIMEOUT_ERR` writer - 9:9\\]
Clear svbus timeout Error Status - (RW )"]
pub type ClrSvbusTimeoutErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES5` reader - 31:10\\]
RESERVE FIELD"]
pub type Res5R = crate :: FieldReader < u32 > ; # [doc = "Field `RES5` writer - 31:10\\]
RESERVE FIELD"]
pub type Res5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
delayed write back pending Status - (RO )"]
# [inline (always)]
pub fn wb_pend (& self) -> WbPendR { WbPendR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Level svbus timeout error Error Status - (RW )"]
# [inline (always)]
pub fn svbus_timeout_err (& self) -> SvbusTimeoutErrR { SvbusTimeoutErrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:8 - 8:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res6 (& self) -> Res6R { Res6R :: new (((self . bits >> 2) & 0x7f) as u8) } # [doc = "Bit 9 - 9:9\\]
Clear svbus timeout Error Status - (RW )"]
# [inline (always)]
pub fn clr_svbus_timeout_err (& self) -> ClrSvbusTimeoutErrR { ClrSvbusTimeoutErrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:31 - 31:10\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res5 (& self) -> Res5R { Res5R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
delayed write back pending Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn wb_pend (& mut self) -> WbPendW < ErrorStatus3Spec > { WbPendW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Level svbus timeout error Error Status - (RW )"]
# [inline (always)]
# [must_use]
pub fn svbus_timeout_err (& mut self) -> SvbusTimeoutErrW < ErrorStatus3Spec > { SvbusTimeoutErrW :: new (self , 1) } # [doc = "Bits 2:8 - 8:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res6 (& mut self) -> Res6W < ErrorStatus3Spec > { Res6W :: new (self , 2) } # [doc = "Bit 9 - 9:9\\]
Clear svbus timeout Error Status - (RW )"]
# [inline (always)]
# [must_use]
pub fn clr_svbus_timeout_err (& mut self) -> ClrSvbusTimeoutErrW < ErrorStatus3Spec > { ClrSvbusTimeoutErrW :: new (self , 9) } # [doc = "Bits 10:31 - 31:10\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res5 (& mut self) -> Res5W < ErrorStatus3Spec > { Res5W :: new (self , 10) } } # [doc = "ECC Error Status3 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`error_status3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`error_status3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ErrorStatus3Spec ; impl crate :: RegisterSpec for ErrorStatus3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`error_status3::R`](R) reader structure"]
impl crate :: Readable for ErrorStatus3Spec { } # [doc = "`write(|w| ..)` method takes [`error_status3::W`](W) writer structure"]
impl crate :: Writable for ErrorStatus3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ERROR_STATUS3 to value 0"]
impl crate :: Resettable for ErrorStatus3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_EOI_REG (rw) register accessor: EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_eoi_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_eoi_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_eoi_reg`]
module"]
# [doc (alias = "SEC_EOI_REG")]
pub type SecEoiReg = crate :: Reg < sec_eoi_reg :: SecEoiRegSpec > ; # [doc = "EOI Register"]
pub mod sec_eoi_reg { # [doc = "Register `SEC_EOI_REG` reader"]
pub type R = crate :: R < SecEoiRegSpec > ; # [doc = "Register `SEC_EOI_REG` writer"]
pub type W = crate :: W < SecEoiRegSpec > ; # [doc = "Field `EOI_WR` reader - 0:0\\]
EOI Register - (RW )"]
pub type EoiWrR = crate :: BitReader ; # [doc = "Field `EOI_WR` writer - 0:0\\]
EOI Register - (RW )"]
pub type EoiWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES7` reader - 31:1\\]
RESERVE FIELD"]
pub type Res7R = crate :: FieldReader < u32 > ; # [doc = "Field `RES7` writer - 31:1\\]
RESERVE FIELD"]
pub type Res7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
EOI Register - (RW )"]
# [inline (always)]
pub fn eoi_wr (& self) -> EoiWrR { EoiWrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res7 (& self) -> Res7R { Res7R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
EOI Register - (RW )"]
# [inline (always)]
# [must_use]
pub fn eoi_wr (& mut self) -> EoiWrW < SecEoiRegSpec > { EoiWrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res7 (& mut self) -> Res7W < SecEoiRegSpec > { Res7W :: new (self , 1) } } # [doc = "EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_eoi_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_eoi_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecEoiRegSpec ; impl crate :: RegisterSpec for SecEoiRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_eoi_reg::R`](R) reader structure"]
impl crate :: Readable for SecEoiRegSpec { } # [doc = "`write(|w| ..)` method takes [`sec_eoi_reg::W`](W) writer structure"]
impl crate :: Writable for SecEoiRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_EOI_REG to value 0"]
impl crate :: Resettable for SecEoiRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_STATUS_REG0 (rw) register accessor: Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_status_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_status_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_status_reg0`]
module"]
# [doc (alias = "SEC_STATUS_REG0")]
pub type SecStatusReg0 = crate :: Reg < sec_status_reg0 :: SecStatusReg0Spec > ; # [doc = "Interrupt Status Register 0"]
pub mod sec_status_reg0 { # [doc = "Register `SEC_STATUS_REG0` reader"]
pub type R = crate :: R < SecStatusReg0Spec > ; # [doc = "Register `SEC_STATUS_REG0` writer"]
pub type W = crate :: W < SecStatusReg0Spec > ; # [doc = "Field `APP_SS_ROM_PEND` reader - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
pub type AppSsRomPendR = crate :: BitReader ; # [doc = "Field `APP_SS_ROM_PEND` writer - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
pub type AppSsRomPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM1_PEND` reader - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1PendR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM1_PEND` writer - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM2_PEND` reader - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2PendR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM2_PEND` writer - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM3_PEND` reader - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3PendR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM3_PEND` writer - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC1_PEND` reader - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1PendR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC1_PEND` writer - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC2_PEND` reader - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2PendR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC2_PEND` writer - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC1_PEND` reader - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1PendR = crate :: BitReader ; # [doc = "Field `HWA_TPTC1_PEND` writer - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC2_PEND` reader - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2PendR = crate :: BitReader ; # [doc = "Field `HWA_TPTC2_PEND` writer - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM0_RAMECC_PEND` reader - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccPendR = crate :: BitReader ; # [doc = "Field `SHARED_MEM0_RAMECC_PEND` writer - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM1_RAMECC_PEND` reader - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccPendR = crate :: BitReader ; # [doc = "Field `SHARED_MEM1_RAMECC_PEND` writer - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_PARAM_MEM_PEND` reader - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemPendR = crate :: BitReader ; # [doc = "Field `HWA_PARAM_MEM_PEND` writer - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM2_RAMECC_PEND` reader - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccPendR = crate :: BitReader ; # [doc = "Field `SHARED_MEM2_RAMECC_PEND` writer - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPING_RAMECC_PEND` reader - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccPendR = crate :: BitReader ; # [doc = "Field `ADCPING_RAMECC_PEND` writer - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPONG_RAMECC_PEND` reader - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccPendR = crate :: BitReader ; # [doc = "Field `ADCPONG_RAMECC_PEND` writer - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES8` reader - 31:14\\]
RESERVE FIELD"]
pub type Res8R = crate :: FieldReader < u32 > ; # [doc = "Field `RES8` writer - 31:14\\]
RESERVE FIELD"]
pub type Res8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
# [inline (always)]
pub fn app_ss_rom_pend (& self) -> AppSsRomPendR { AppSsRomPendR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram1_pend (& self) -> AppSsRam1PendR { AppSsRam1PendR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram2_pend (& self) -> AppSsRam2PendR { AppSsRam2PendR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram3_pend (& self) -> AppSsRam3PendR { AppSsRam3PendR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc1_pend (& self) -> AppSsTptc1PendR { AppSsTptc1PendR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc2_pend (& self) -> AppSsTptc2PendR { AppSsTptc2PendR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc1_pend (& self) -> HwaTptc1PendR { HwaTptc1PendR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc2_pend (& self) -> HwaTptc2PendR { HwaTptc2PendR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem0_ramecc_pend (& self) -> SharedMem0RameccPendR { SharedMem0RameccPendR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem1_ramecc_pend (& self) -> SharedMem1RameccPendR { SharedMem1RameccPendR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
# [inline (always)]
pub fn hwa_param_mem_pend (& self) -> HwaParamMemPendR { HwaParamMemPendR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem2_ramecc_pend (& self) -> SharedMem2RameccPendR { SharedMem2RameccPendR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcping_ramecc_pend (& self) -> AdcpingRameccPendR { AdcpingRameccPendR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcpong_ramecc_pend (& self) -> AdcpongRameccPendR { AdcpongRameccPendR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res8 (& self) -> Res8R { Res8R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_rom_pend (& mut self) -> AppSsRomPendW < SecStatusReg0Spec > { AppSsRomPendW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram1_pend (& mut self) -> AppSsRam1PendW < SecStatusReg0Spec > { AppSsRam1PendW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram2_pend (& mut self) -> AppSsRam2PendW < SecStatusReg0Spec > { AppSsRam2PendW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram3_pend (& mut self) -> AppSsRam3PendW < SecStatusReg0Spec > { AppSsRam3PendW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc1_pend (& mut self) -> AppSsTptc1PendW < SecStatusReg0Spec > { AppSsTptc1PendW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc2_pend (& mut self) -> AppSsTptc2PendW < SecStatusReg0Spec > { AppSsTptc2PendW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc1_pend (& mut self) -> HwaTptc1PendW < SecStatusReg0Spec > { HwaTptc1PendW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc2_pend (& mut self) -> HwaTptc2PendW < SecStatusReg0Spec > { HwaTptc2PendW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem0_ramecc_pend (& mut self) -> SharedMem0RameccPendW < SecStatusReg0Spec > { SharedMem0RameccPendW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem1_ramecc_pend (& mut self) -> SharedMem1RameccPendW < SecStatusReg0Spec > { SharedMem1RameccPendW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_param_mem_pend (& mut self) -> HwaParamMemPendW < SecStatusReg0Spec > { HwaParamMemPendW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem2_ramecc_pend (& mut self) -> SharedMem2RameccPendW < SecStatusReg0Spec > { SharedMem2RameccPendW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcping_ramecc_pend (& mut self) -> AdcpingRameccPendW < SecStatusReg0Spec > { AdcpingRameccPendW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcpong_ramecc_pend (& mut self) -> AdcpongRameccPendW < SecStatusReg0Spec > { AdcpongRameccPendW :: new (self , 13) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res8 (& mut self) -> Res8W < SecStatusReg0Spec > { Res8W :: new (self , 14) } } # [doc = "Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_status_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_status_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecStatusReg0Spec ; impl crate :: RegisterSpec for SecStatusReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_status_reg0::R`](R) reader structure"]
impl crate :: Readable for SecStatusReg0Spec { } # [doc = "`write(|w| ..)` method takes [`sec_status_reg0::W`](W) writer structure"]
impl crate :: Writable for SecStatusReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_STATUS_REG0 to value 0"]
impl crate :: Resettable for SecStatusReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_ENABLE_SET_REG0 (rw) register accessor: Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_set_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_set_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_enable_set_reg0`]
module"]
# [doc (alias = "SEC_ENABLE_SET_REG0")]
pub type SecEnableSetReg0 = crate :: Reg < sec_enable_set_reg0 :: SecEnableSetReg0Spec > ; # [doc = "Interrupt Enable Set Register 0"]
pub mod sec_enable_set_reg0 { # [doc = "Register `SEC_ENABLE_SET_REG0` reader"]
pub type R = crate :: R < SecEnableSetReg0Spec > ; # [doc = "Register `SEC_ENABLE_SET_REG0` writer"]
pub type W = crate :: W < SecEnableSetReg0Spec > ; # [doc = "Field `APP_SS_ROM_ENABLE_SET` reader - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_ROM_ENABLE_SET` writer - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM1_ENABLE_SET` reader - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM1_ENABLE_SET` writer - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM2_ENABLE_SET` reader - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM2_ENABLE_SET` writer - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM3_ENABLE_SET` reader - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM3_ENABLE_SET` writer - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC1_ENABLE_SET` reader - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC1_ENABLE_SET` writer - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC2_ENABLE_SET` reader - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC2_ENABLE_SET` writer - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC1_ENABLE_SET` reader - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableSetR = crate :: BitReader ; # [doc = "Field `HWA_TPTC1_ENABLE_SET` writer - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC2_ENABLE_SET` reader - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableSetR = crate :: BitReader ; # [doc = "Field `HWA_TPTC2_ENABLE_SET` writer - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_SET` reader - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableSetR = crate :: BitReader ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_SET` writer - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_SET` reader - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableSetR = crate :: BitReader ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_SET` writer - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_SET` reader - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableSetR = crate :: BitReader ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_SET` writer - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_SET` reader - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableSetR = crate :: BitReader ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_SET` writer - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPING_RAMECC_ENABLE_SET` reader - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableSetR = crate :: BitReader ; # [doc = "Field `ADCPING_RAMECC_ENABLE_SET` writer - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_SET` reader - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableSetR = crate :: BitReader ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_SET` writer - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES9` reader - 31:14\\]
RESERVE FIELD"]
pub type Res9R = crate :: FieldReader < u32 > ; # [doc = "Field `RES9` writer - 31:14\\]
RESERVE FIELD"]
pub type Res9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
pub fn app_ss_rom_enable_set (& self) -> AppSsRomEnableSetR { AppSsRomEnableSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram1_enable_set (& self) -> AppSsRam1EnableSetR { AppSsRam1EnableSetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram2_enable_set (& self) -> AppSsRam2EnableSetR { AppSsRam2EnableSetR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram3_enable_set (& self) -> AppSsRam3EnableSetR { AppSsRam3EnableSetR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc1_enable_set (& self) -> AppSsTptc1EnableSetR { AppSsTptc1EnableSetR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc2_enable_set (& self) -> AppSsTptc2EnableSetR { AppSsTptc2EnableSetR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc1_enable_set (& self) -> HwaTptc1EnableSetR { HwaTptc1EnableSetR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc2_enable_set (& self) -> HwaTptc2EnableSetR { HwaTptc2EnableSetR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem0_ramecc_enable_set (& self) -> SharedMem0RameccEnableSetR { SharedMem0RameccEnableSetR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem1_ramecc_enable_set (& self) -> SharedMem1RameccEnableSetR { SharedMem1RameccEnableSetR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
pub fn hwa_param_mem_enable_set (& self) -> HwaParamMemEnableSetR { HwaParamMemEnableSetR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem2_ramecc_enable_set (& self) -> SharedMem2RameccEnableSetR { SharedMem2RameccEnableSetR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcping_ramecc_enable_set (& self) -> AdcpingRameccEnableSetR { AdcpingRameccEnableSetR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcpong_ramecc_enable_set (& self) -> AdcpongRameccEnableSetR { AdcpongRameccEnableSetR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res9 (& self) -> Res9R { Res9R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_rom_enable_set (& mut self) -> AppSsRomEnableSetW < SecEnableSetReg0Spec > { AppSsRomEnableSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram1_enable_set (& mut self) -> AppSsRam1EnableSetW < SecEnableSetReg0Spec > { AppSsRam1EnableSetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram2_enable_set (& mut self) -> AppSsRam2EnableSetW < SecEnableSetReg0Spec > { AppSsRam2EnableSetW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram3_enable_set (& mut self) -> AppSsRam3EnableSetW < SecEnableSetReg0Spec > { AppSsRam3EnableSetW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc1_enable_set (& mut self) -> AppSsTptc1EnableSetW < SecEnableSetReg0Spec > { AppSsTptc1EnableSetW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc2_enable_set (& mut self) -> AppSsTptc2EnableSetW < SecEnableSetReg0Spec > { AppSsTptc2EnableSetW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc1_enable_set (& mut self) -> HwaTptc1EnableSetW < SecEnableSetReg0Spec > { HwaTptc1EnableSetW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc2_enable_set (& mut self) -> HwaTptc2EnableSetW < SecEnableSetReg0Spec > { HwaTptc2EnableSetW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem0_ramecc_enable_set (& mut self) -> SharedMem0RameccEnableSetW < SecEnableSetReg0Spec > { SharedMem0RameccEnableSetW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem1_ramecc_enable_set (& mut self) -> SharedMem1RameccEnableSetW < SecEnableSetReg0Spec > { SharedMem1RameccEnableSetW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_param_mem_enable_set (& mut self) -> HwaParamMemEnableSetW < SecEnableSetReg0Spec > { HwaParamMemEnableSetW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem2_ramecc_enable_set (& mut self) -> SharedMem2RameccEnableSetW < SecEnableSetReg0Spec > { SharedMem2RameccEnableSetW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcping_ramecc_enable_set (& mut self) -> AdcpingRameccEnableSetW < SecEnableSetReg0Spec > { AdcpingRameccEnableSetW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcpong_ramecc_enable_set (& mut self) -> AdcpongRameccEnableSetW < SecEnableSetReg0Spec > { AdcpongRameccEnableSetW :: new (self , 13) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res9 (& mut self) -> Res9W < SecEnableSetReg0Spec > { Res9W :: new (self , 14) } } # [doc = "Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_set_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_set_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecEnableSetReg0Spec ; impl crate :: RegisterSpec for SecEnableSetReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_enable_set_reg0::R`](R) reader structure"]
impl crate :: Readable for SecEnableSetReg0Spec { } # [doc = "`write(|w| ..)` method takes [`sec_enable_set_reg0::W`](W) writer structure"]
impl crate :: Writable for SecEnableSetReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_ENABLE_SET_REG0 to value 0"]
impl crate :: Resettable for SecEnableSetReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SEC_ENABLE_CLR_REG0 (rw) register accessor: Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_clr_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_clr_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_enable_clr_reg0`]
module"]
# [doc (alias = "SEC_ENABLE_CLR_REG0")]
pub type SecEnableClrReg0 = crate :: Reg < sec_enable_clr_reg0 :: SecEnableClrReg0Spec > ; # [doc = "Interrupt Enable Clear Register 0"]
pub mod sec_enable_clr_reg0 { # [doc = "Register `SEC_ENABLE_CLR_REG0` reader"]
pub type R = crate :: R < SecEnableClrReg0Spec > ; # [doc = "Register `SEC_ENABLE_CLR_REG0` writer"]
pub type W = crate :: W < SecEnableClrReg0Spec > ; # [doc = "Field `APP_SS_ROM_ENABLE_CLR` reader - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_ROM_ENABLE_CLR` writer - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM1_ENABLE_CLR` reader - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM1_ENABLE_CLR` writer - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM2_ENABLE_CLR` reader - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM2_ENABLE_CLR` writer - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM3_ENABLE_CLR` reader - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM3_ENABLE_CLR` writer - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC1_ENABLE_CLR` reader - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC1_ENABLE_CLR` writer - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC2_ENABLE_CLR` reader - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC2_ENABLE_CLR` writer - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC1_ENABLE_CLR` reader - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableClrR = crate :: BitReader ; # [doc = "Field `HWA_TPTC1_ENABLE_CLR` writer - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC2_ENABLE_CLR` reader - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableClrR = crate :: BitReader ; # [doc = "Field `HWA_TPTC2_ENABLE_CLR` writer - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_CLR` reader - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableClrR = crate :: BitReader ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_CLR` writer - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_CLR` reader - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableClrR = crate :: BitReader ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_CLR` writer - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_CLR` reader - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableClrR = crate :: BitReader ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_CLR` writer - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_CLR` reader - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableClrR = crate :: BitReader ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_CLR` writer - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPING_RAMECC_ENABLE_CLR` reader - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableClrR = crate :: BitReader ; # [doc = "Field `ADCPING_RAMECC_ENABLE_CLR` writer - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_CLR` reader - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableClrR = crate :: BitReader ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_CLR` writer - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES10` reader - 31:14\\]
RESERVE FIELD"]
pub type Res10R = crate :: FieldReader < u32 > ; # [doc = "Field `RES10` writer - 31:14\\]
RESERVE FIELD"]
pub type Res10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
pub fn app_ss_rom_enable_clr (& self) -> AppSsRomEnableClrR { AppSsRomEnableClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram1_enable_clr (& self) -> AppSsRam1EnableClrR { AppSsRam1EnableClrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram2_enable_clr (& self) -> AppSsRam2EnableClrR { AppSsRam2EnableClrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram3_enable_clr (& self) -> AppSsRam3EnableClrR { AppSsRam3EnableClrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc1_enable_clr (& self) -> AppSsTptc1EnableClrR { AppSsTptc1EnableClrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc2_enable_clr (& self) -> AppSsTptc2EnableClrR { AppSsTptc2EnableClrR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc1_enable_clr (& self) -> HwaTptc1EnableClrR { HwaTptc1EnableClrR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc2_enable_clr (& self) -> HwaTptc2EnableClrR { HwaTptc2EnableClrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem0_ramecc_enable_clr (& self) -> SharedMem0RameccEnableClrR { SharedMem0RameccEnableClrR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem1_ramecc_enable_clr (& self) -> SharedMem1RameccEnableClrR { SharedMem1RameccEnableClrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
pub fn hwa_param_mem_enable_clr (& self) -> HwaParamMemEnableClrR { HwaParamMemEnableClrR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem2_ramecc_enable_clr (& self) -> SharedMem2RameccEnableClrR { SharedMem2RameccEnableClrR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcping_ramecc_enable_clr (& self) -> AdcpingRameccEnableClrR { AdcpingRameccEnableClrR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcpong_ramecc_enable_clr (& self) -> AdcpongRameccEnableClrR { AdcpongRameccEnableClrR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res10 (& self) -> Res10R { Res10R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_rom_enable_clr (& mut self) -> AppSsRomEnableClrW < SecEnableClrReg0Spec > { AppSsRomEnableClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram1_enable_clr (& mut self) -> AppSsRam1EnableClrW < SecEnableClrReg0Spec > { AppSsRam1EnableClrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram2_enable_clr (& mut self) -> AppSsRam2EnableClrW < SecEnableClrReg0Spec > { AppSsRam2EnableClrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram3_enable_clr (& mut self) -> AppSsRam3EnableClrW < SecEnableClrReg0Spec > { AppSsRam3EnableClrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc1_enable_clr (& mut self) -> AppSsTptc1EnableClrW < SecEnableClrReg0Spec > { AppSsTptc1EnableClrW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc2_enable_clr (& mut self) -> AppSsTptc2EnableClrW < SecEnableClrReg0Spec > { AppSsTptc2EnableClrW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc1_enable_clr (& mut self) -> HwaTptc1EnableClrW < SecEnableClrReg0Spec > { HwaTptc1EnableClrW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc2_enable_clr (& mut self) -> HwaTptc2EnableClrW < SecEnableClrReg0Spec > { HwaTptc2EnableClrW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem0_ramecc_enable_clr (& mut self) -> SharedMem0RameccEnableClrW < SecEnableClrReg0Spec > { SharedMem0RameccEnableClrW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem1_ramecc_enable_clr (& mut self) -> SharedMem1RameccEnableClrW < SecEnableClrReg0Spec > { SharedMem1RameccEnableClrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_param_mem_enable_clr (& mut self) -> HwaParamMemEnableClrW < SecEnableClrReg0Spec > { HwaParamMemEnableClrW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem2_ramecc_enable_clr (& mut self) -> SharedMem2RameccEnableClrW < SecEnableClrReg0Spec > { SharedMem2RameccEnableClrW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcping_ramecc_enable_clr (& mut self) -> AdcpingRameccEnableClrW < SecEnableClrReg0Spec > { AdcpingRameccEnableClrW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcpong_ramecc_enable_clr (& mut self) -> AdcpongRameccEnableClrW < SecEnableClrReg0Spec > { AdcpongRameccEnableClrW :: new (self , 13) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res10 (& mut self) -> Res10W < SecEnableClrReg0Spec > { Res10W :: new (self , 14) } } # [doc = "Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_enable_clr_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_enable_clr_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecEnableClrReg0Spec ; impl crate :: RegisterSpec for SecEnableClrReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sec_enable_clr_reg0::R`](R) reader structure"]
impl crate :: Readable for SecEnableClrReg0Spec { } # [doc = "`write(|w| ..)` method takes [`sec_enable_clr_reg0::W`](W) writer structure"]
impl crate :: Writable for SecEnableClrReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SEC_ENABLE_CLR_REG0 to value 0"]
impl crate :: Resettable for SecEnableClrReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_EOI_REG (rw) register accessor: EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_eoi_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_eoi_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_eoi_reg`]
module"]
# [doc (alias = "DED_EOI_REG")]
pub type DedEoiReg = crate :: Reg < ded_eoi_reg :: DedEoiRegSpec > ; # [doc = "EOI Register"]
pub mod ded_eoi_reg { # [doc = "Register `DED_EOI_REG` reader"]
pub type R = crate :: R < DedEoiRegSpec > ; # [doc = "Register `DED_EOI_REG` writer"]
pub type W = crate :: W < DedEoiRegSpec > ; # [doc = "Field `EOI_WR` reader - 0:0\\]
EOI Register - (RW )"]
pub type EoiWrR = crate :: BitReader ; # [doc = "Field `EOI_WR` writer - 0:0\\]
EOI Register - (RW )"]
pub type EoiWrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES11` reader - 31:1\\]
RESERVE FIELD"]
pub type Res11R = crate :: FieldReader < u32 > ; # [doc = "Field `RES11` writer - 31:1\\]
RESERVE FIELD"]
pub type Res11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
EOI Register - (RW )"]
# [inline (always)]
pub fn eoi_wr (& self) -> EoiWrR { EoiWrR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res11 (& self) -> Res11R { Res11R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
EOI Register - (RW )"]
# [inline (always)]
# [must_use]
pub fn eoi_wr (& mut self) -> EoiWrW < DedEoiRegSpec > { EoiWrW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res11 (& mut self) -> Res11W < DedEoiRegSpec > { Res11W :: new (self , 1) } } # [doc = "EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_eoi_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_eoi_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedEoiRegSpec ; impl crate :: RegisterSpec for DedEoiRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_eoi_reg::R`](R) reader structure"]
impl crate :: Readable for DedEoiRegSpec { } # [doc = "`write(|w| ..)` method takes [`ded_eoi_reg::W`](W) writer structure"]
impl crate :: Writable for DedEoiRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_EOI_REG to value 0"]
impl crate :: Resettable for DedEoiRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_STATUS_REG0 (rw) register accessor: Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_status_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_status_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_status_reg0`]
module"]
# [doc (alias = "DED_STATUS_REG0")]
pub type DedStatusReg0 = crate :: Reg < ded_status_reg0 :: DedStatusReg0Spec > ; # [doc = "Interrupt Status Register 0"]
pub mod ded_status_reg0 { # [doc = "Register `DED_STATUS_REG0` reader"]
pub type R = crate :: R < DedStatusReg0Spec > ; # [doc = "Register `DED_STATUS_REG0` writer"]
pub type W = crate :: W < DedStatusReg0Spec > ; # [doc = "Field `APP_SS_ROM_PEND` reader - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
pub type AppSsRomPendR = crate :: BitReader ; # [doc = "Field `APP_SS_ROM_PEND` writer - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
pub type AppSsRomPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM1_PEND` reader - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1PendR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM1_PEND` writer - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM2_PEND` reader - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2PendR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM2_PEND` writer - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM3_PEND` reader - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3PendR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM3_PEND` writer - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC1_PEND` reader - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1PendR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC1_PEND` writer - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC2_PEND` reader - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2PendR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC2_PEND` writer - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC1_PEND` reader - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1PendR = crate :: BitReader ; # [doc = "Field `HWA_TPTC1_PEND` writer - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC2_PEND` reader - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2PendR = crate :: BitReader ; # [doc = "Field `HWA_TPTC2_PEND` writer - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2PendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM0_RAMECC_PEND` reader - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccPendR = crate :: BitReader ; # [doc = "Field `SHARED_MEM0_RAMECC_PEND` writer - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM1_RAMECC_PEND` reader - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccPendR = crate :: BitReader ; # [doc = "Field `SHARED_MEM1_RAMECC_PEND` writer - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_PARAM_MEM_PEND` reader - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemPendR = crate :: BitReader ; # [doc = "Field `HWA_PARAM_MEM_PEND` writer - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM2_RAMECC_PEND` reader - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccPendR = crate :: BitReader ; # [doc = "Field `SHARED_MEM2_RAMECC_PEND` writer - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPING_RAMECC_PEND` reader - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccPendR = crate :: BitReader ; # [doc = "Field `ADCPING_RAMECC_PEND` writer - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPONG_RAMECC_PEND` reader - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccPendR = crate :: BitReader ; # [doc = "Field `ADCPONG_RAMECC_PEND` writer - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccPendW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES12` reader - 31:14\\]
RESERVE FIELD"]
pub type Res12R = crate :: FieldReader < u32 > ; # [doc = "Field `RES12` writer - 31:14\\]
RESERVE FIELD"]
pub type Res12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
# [inline (always)]
pub fn app_ss_rom_pend (& self) -> AppSsRomPendR { AppSsRomPendR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram1_pend (& self) -> AppSsRam1PendR { AppSsRam1PendR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram2_pend (& self) -> AppSsRam2PendR { AppSsRam2PendR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram3_pend (& self) -> AppSsRam3PendR { AppSsRam3PendR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc1_pend (& self) -> AppSsTptc1PendR { AppSsTptc1PendR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc2_pend (& self) -> AppSsTptc2PendR { AppSsTptc2PendR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc1_pend (& self) -> HwaTptc1PendR { HwaTptc1PendR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc2_pend (& self) -> HwaTptc2PendR { HwaTptc2PendR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem0_ramecc_pend (& self) -> SharedMem0RameccPendR { SharedMem0RameccPendR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem1_ramecc_pend (& self) -> SharedMem1RameccPendR { SharedMem1RameccPendR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
# [inline (always)]
pub fn hwa_param_mem_pend (& self) -> HwaParamMemPendR { HwaParamMemPendR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem2_ramecc_pend (& self) -> SharedMem2RameccPendR { SharedMem2RameccPendR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcping_ramecc_pend (& self) -> AdcpingRameccPendR { AdcpingRameccPendR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcpong_ramecc_pend (& self) -> AdcpongRameccPendR { AdcpongRameccPendR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res12 (& self) -> Res12R { Res12R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for app_ss_rom_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_rom_pend (& mut self) -> AppSsRomPendW < DedStatusReg0Spec > { AppSsRomPendW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for app_ss_ram1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram1_pend (& mut self) -> AppSsRam1PendW < DedStatusReg0Spec > { AppSsRam1PendW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt Pending Status for app_ss_ram2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram2_pend (& mut self) -> AppSsRam2PendW < DedStatusReg0Spec > { AppSsRam2PendW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt Pending Status for app_ss_ram3_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram3_pend (& mut self) -> AppSsRam3PendW < DedStatusReg0Spec > { AppSsRam3PendW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt Pending Status for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc1_pend (& mut self) -> AppSsTptc1PendW < DedStatusReg0Spec > { AppSsTptc1PendW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt Pending Status for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc2_pend (& mut self) -> AppSsTptc2PendW < DedStatusReg0Spec > { AppSsTptc2PendW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt Pending Status for hwa_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc1_pend (& mut self) -> HwaTptc1PendW < DedStatusReg0Spec > { HwaTptc1PendW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt Pending Status for hwa_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc2_pend (& mut self) -> HwaTptc2PendW < DedStatusReg0Spec > { HwaTptc2PendW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt Pending Status for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem0_ramecc_pend (& mut self) -> SharedMem0RameccPendW < DedStatusReg0Spec > { SharedMem0RameccPendW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt Pending Status for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem1_ramecc_pend (& mut self) -> SharedMem1RameccPendW < DedStatusReg0Spec > { SharedMem1RameccPendW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt Pending Status for hwa_param_mem_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_param_mem_pend (& mut self) -> HwaParamMemPendW < DedStatusReg0Spec > { HwaParamMemPendW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt Pending Status for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem2_ramecc_pend (& mut self) -> SharedMem2RameccPendW < DedStatusReg0Spec > { SharedMem2RameccPendW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt Pending Status for adcping_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcping_ramecc_pend (& mut self) -> AdcpingRameccPendW < DedStatusReg0Spec > { AdcpingRameccPendW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt Pending Status for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcpong_ramecc_pend (& mut self) -> AdcpongRameccPendW < DedStatusReg0Spec > { AdcpongRameccPendW :: new (self , 13) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res12 (& mut self) -> Res12W < DedStatusReg0Spec > { Res12W :: new (self , 14) } } # [doc = "Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_status_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_status_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedStatusReg0Spec ; impl crate :: RegisterSpec for DedStatusReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_status_reg0::R`](R) reader structure"]
impl crate :: Readable for DedStatusReg0Spec { } # [doc = "`write(|w| ..)` method takes [`ded_status_reg0::W`](W) writer structure"]
impl crate :: Writable for DedStatusReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_STATUS_REG0 to value 0"]
impl crate :: Resettable for DedStatusReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_ENABLE_SET_REG0 (rw) register accessor: Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_set_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_set_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_enable_set_reg0`]
module"]
# [doc (alias = "DED_ENABLE_SET_REG0")]
pub type DedEnableSetReg0 = crate :: Reg < ded_enable_set_reg0 :: DedEnableSetReg0Spec > ; # [doc = "Interrupt Enable Set Register 0"]
pub mod ded_enable_set_reg0 { # [doc = "Register `DED_ENABLE_SET_REG0` reader"]
pub type R = crate :: R < DedEnableSetReg0Spec > ; # [doc = "Register `DED_ENABLE_SET_REG0` writer"]
pub type W = crate :: W < DedEnableSetReg0Spec > ; # [doc = "Field `APP_SS_ROM_ENABLE_SET` reader - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_ROM_ENABLE_SET` writer - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM1_ENABLE_SET` reader - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM1_ENABLE_SET` writer - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM2_ENABLE_SET` reader - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM2_ENABLE_SET` writer - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM3_ENABLE_SET` reader - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM3_ENABLE_SET` writer - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC1_ENABLE_SET` reader - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC1_ENABLE_SET` writer - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC2_ENABLE_SET` reader - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableSetR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC2_ENABLE_SET` writer - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC1_ENABLE_SET` reader - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableSetR = crate :: BitReader ; # [doc = "Field `HWA_TPTC1_ENABLE_SET` writer - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC2_ENABLE_SET` reader - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableSetR = crate :: BitReader ; # [doc = "Field `HWA_TPTC2_ENABLE_SET` writer - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_SET` reader - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableSetR = crate :: BitReader ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_SET` writer - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_SET` reader - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableSetR = crate :: BitReader ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_SET` writer - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_SET` reader - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableSetR = crate :: BitReader ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_SET` writer - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_SET` reader - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableSetR = crate :: BitReader ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_SET` writer - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPING_RAMECC_ENABLE_SET` reader - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableSetR = crate :: BitReader ; # [doc = "Field `ADCPING_RAMECC_ENABLE_SET` writer - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_SET` reader - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableSetR = crate :: BitReader ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_SET` writer - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES13` reader - 31:14\\]
RESERVE FIELD"]
pub type Res13R = crate :: FieldReader < u32 > ; # [doc = "Field `RES13` writer - 31:14\\]
RESERVE FIELD"]
pub type Res13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
pub fn app_ss_rom_enable_set (& self) -> AppSsRomEnableSetR { AppSsRomEnableSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram1_enable_set (& self) -> AppSsRam1EnableSetR { AppSsRam1EnableSetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram2_enable_set (& self) -> AppSsRam2EnableSetR { AppSsRam2EnableSetR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram3_enable_set (& self) -> AppSsRam3EnableSetR { AppSsRam3EnableSetR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc1_enable_set (& self) -> AppSsTptc1EnableSetR { AppSsTptc1EnableSetR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc2_enable_set (& self) -> AppSsTptc2EnableSetR { AppSsTptc2EnableSetR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc1_enable_set (& self) -> HwaTptc1EnableSetR { HwaTptc1EnableSetR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc2_enable_set (& self) -> HwaTptc2EnableSetR { HwaTptc2EnableSetR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem0_ramecc_enable_set (& self) -> SharedMem0RameccEnableSetR { SharedMem0RameccEnableSetR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem1_ramecc_enable_set (& self) -> SharedMem1RameccEnableSetR { SharedMem1RameccEnableSetR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
pub fn hwa_param_mem_enable_set (& self) -> HwaParamMemEnableSetR { HwaParamMemEnableSetR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem2_ramecc_enable_set (& self) -> SharedMem2RameccEnableSetR { SharedMem2RameccEnableSetR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcping_ramecc_enable_set (& self) -> AdcpingRameccEnableSetR { AdcpingRameccEnableSetR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcpong_ramecc_enable_set (& self) -> AdcpongRameccEnableSetR { AdcpongRameccEnableSetR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res13 (& self) -> Res13R { Res13R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_rom_enable_set (& mut self) -> AppSsRomEnableSetW < DedEnableSetReg0Spec > { AppSsRomEnableSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram1_enable_set (& mut self) -> AppSsRam1EnableSetW < DedEnableSetReg0Spec > { AppSsRam1EnableSetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Set Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram2_enable_set (& mut self) -> AppSsRam2EnableSetW < DedEnableSetReg0Spec > { AppSsRam2EnableSetW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Set Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram3_enable_set (& mut self) -> AppSsRam3EnableSetW < DedEnableSetReg0Spec > { AppSsRam3EnableSetW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Set Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc1_enable_set (& mut self) -> AppSsTptc1EnableSetW < DedEnableSetReg0Spec > { AppSsTptc1EnableSetW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Set Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc2_enable_set (& mut self) -> AppSsTptc2EnableSetW < DedEnableSetReg0Spec > { AppSsTptc2EnableSetW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Set Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc1_enable_set (& mut self) -> HwaTptc1EnableSetW < DedEnableSetReg0Spec > { HwaTptc1EnableSetW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Set Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc2_enable_set (& mut self) -> HwaTptc2EnableSetW < DedEnableSetReg0Spec > { HwaTptc2EnableSetW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem0_ramecc_enable_set (& mut self) -> SharedMem0RameccEnableSetW < DedEnableSetReg0Spec > { SharedMem0RameccEnableSetW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem1_ramecc_enable_set (& mut self) -> SharedMem1RameccEnableSetW < DedEnableSetReg0Spec > { SharedMem1RameccEnableSetW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Set Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_param_mem_enable_set (& mut self) -> HwaParamMemEnableSetW < DedEnableSetReg0Spec > { HwaParamMemEnableSetW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem2_ramecc_enable_set (& mut self) -> SharedMem2RameccEnableSetW < DedEnableSetReg0Spec > { SharedMem2RameccEnableSetW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Set Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcping_ramecc_enable_set (& mut self) -> AdcpingRameccEnableSetW < DedEnableSetReg0Spec > { AdcpingRameccEnableSetW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Set Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcpong_ramecc_enable_set (& mut self) -> AdcpongRameccEnableSetW < DedEnableSetReg0Spec > { AdcpongRameccEnableSetW :: new (self , 13) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res13 (& mut self) -> Res13W < DedEnableSetReg0Spec > { Res13W :: new (self , 14) } } # [doc = "Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_set_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_set_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedEnableSetReg0Spec ; impl crate :: RegisterSpec for DedEnableSetReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_enable_set_reg0::R`](R) reader structure"]
impl crate :: Readable for DedEnableSetReg0Spec { } # [doc = "`write(|w| ..)` method takes [`ded_enable_set_reg0::W`](W) writer structure"]
impl crate :: Writable for DedEnableSetReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_ENABLE_SET_REG0 to value 0"]
impl crate :: Resettable for DedEnableSetReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DED_ENABLE_CLR_REG0 (rw) register accessor: Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_clr_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_clr_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ded_enable_clr_reg0`]
module"]
# [doc (alias = "DED_ENABLE_CLR_REG0")]
pub type DedEnableClrReg0 = crate :: Reg < ded_enable_clr_reg0 :: DedEnableClrReg0Spec > ; # [doc = "Interrupt Enable Clear Register 0"]
pub mod ded_enable_clr_reg0 { # [doc = "Register `DED_ENABLE_CLR_REG0` reader"]
pub type R = crate :: R < DedEnableClrReg0Spec > ; # [doc = "Register `DED_ENABLE_CLR_REG0` writer"]
pub type W = crate :: W < DedEnableClrReg0Spec > ; # [doc = "Field `APP_SS_ROM_ENABLE_CLR` reader - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_ROM_ENABLE_CLR` writer - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
pub type AppSsRomEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM1_ENABLE_CLR` reader - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM1_ENABLE_CLR` writer - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
pub type AppSsRam1EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM2_ENABLE_CLR` reader - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM2_ENABLE_CLR` writer - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
pub type AppSsRam2EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_RAM3_ENABLE_CLR` reader - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_RAM3_ENABLE_CLR` writer - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
pub type AppSsRam3EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC1_ENABLE_CLR` reader - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC1_ENABLE_CLR` writer - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
pub type AppSsTptc1EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `APP_SS_TPTC2_ENABLE_CLR` reader - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableClrR = crate :: BitReader ; # [doc = "Field `APP_SS_TPTC2_ENABLE_CLR` writer - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
pub type AppSsTptc2EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC1_ENABLE_CLR` reader - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableClrR = crate :: BitReader ; # [doc = "Field `HWA_TPTC1_ENABLE_CLR` writer - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
pub type HwaTptc1EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_TPTC2_ENABLE_CLR` reader - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableClrR = crate :: BitReader ; # [doc = "Field `HWA_TPTC2_ENABLE_CLR` writer - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
pub type HwaTptc2EnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_CLR` reader - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableClrR = crate :: BitReader ; # [doc = "Field `SHARED_MEM0_RAMECC_ENABLE_CLR` writer - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
pub type SharedMem0RameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_CLR` reader - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableClrR = crate :: BitReader ; # [doc = "Field `SHARED_MEM1_RAMECC_ENABLE_CLR` writer - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
pub type SharedMem1RameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_CLR` reader - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableClrR = crate :: BitReader ; # [doc = "Field `HWA_PARAM_MEM_ENABLE_CLR` writer - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
pub type HwaParamMemEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_CLR` reader - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableClrR = crate :: BitReader ; # [doc = "Field `SHARED_MEM2_RAMECC_ENABLE_CLR` writer - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
pub type SharedMem2RameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPING_RAMECC_ENABLE_CLR` reader - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableClrR = crate :: BitReader ; # [doc = "Field `ADCPING_RAMECC_ENABLE_CLR` writer - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
pub type AdcpingRameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_CLR` reader - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableClrR = crate :: BitReader ; # [doc = "Field `ADCPONG_RAMECC_ENABLE_CLR` writer - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
pub type AdcpongRameccEnableClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES14` reader - 31:14\\]
RESERVE FIELD"]
pub type Res14R = crate :: FieldReader < u32 > ; # [doc = "Field `RES14` writer - 31:14\\]
RESERVE FIELD"]
pub type Res14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 18 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
pub fn app_ss_rom_enable_clr (& self) -> AppSsRomEnableClrR { AppSsRomEnableClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram1_enable_clr (& self) -> AppSsRam1EnableClrR { AppSsRam1EnableClrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram2_enable_clr (& self) -> AppSsRam2EnableClrR { AppSsRam2EnableClrR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
pub fn app_ss_ram3_enable_clr (& self) -> AppSsRam3EnableClrR { AppSsRam3EnableClrR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc1_enable_clr (& self) -> AppSsTptc1EnableClrR { AppSsTptc1EnableClrR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
pub fn app_ss_tptc2_enable_clr (& self) -> AppSsTptc2EnableClrR { AppSsTptc2EnableClrR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc1_enable_clr (& self) -> HwaTptc1EnableClrR { HwaTptc1EnableClrR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
pub fn hwa_tptc2_enable_clr (& self) -> HwaTptc2EnableClrR { HwaTptc2EnableClrR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem0_ramecc_enable_clr (& self) -> SharedMem0RameccEnableClrR { SharedMem0RameccEnableClrR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem1_ramecc_enable_clr (& self) -> SharedMem1RameccEnableClrR { SharedMem1RameccEnableClrR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
pub fn hwa_param_mem_enable_clr (& self) -> HwaParamMemEnableClrR { HwaParamMemEnableClrR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
pub fn shared_mem2_ramecc_enable_clr (& self) -> SharedMem2RameccEnableClrR { SharedMem2RameccEnableClrR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcping_ramecc_enable_clr (& self) -> AdcpingRameccEnableClrR { AdcpingRameccEnableClrR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
pub fn adcpong_ramecc_enable_clr (& self) -> AdcpongRameccEnableClrR { AdcpongRameccEnableClrR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res14 (& self) -> Res14R { Res14R :: new ((self . bits >> 14) & 0x0003_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for app_ss_rom_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_rom_enable_clr (& mut self) -> AppSsRomEnableClrW < DedEnableClrReg0Spec > { AppSsRomEnableClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for app_ss_ram1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram1_enable_clr (& mut self) -> AppSsRam1EnableClrW < DedEnableClrReg0Spec > { AppSsRam1EnableClrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Interrupt Enable Clear Register for app_ss_ram2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram2_enable_clr (& mut self) -> AppSsRam2EnableClrW < DedEnableClrReg0Spec > { AppSsRam2EnableClrW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Interrupt Enable Clear Register for app_ss_ram3_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_ram3_enable_clr (& mut self) -> AppSsRam3EnableClrW < DedEnableClrReg0Spec > { AppSsRam3EnableClrW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc1_enable_clr (& mut self) -> AppSsTptc1EnableClrW < DedEnableClrReg0Spec > { AppSsTptc1EnableClrW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn app_ss_tptc2_enable_clr (& mut self) -> AppSsTptc2EnableClrW < DedEnableClrReg0Spec > { AppSsTptc2EnableClrW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Interrupt Enable Clear Register for hwa_tptc1_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc1_enable_clr (& mut self) -> HwaTptc1EnableClrW < DedEnableClrReg0Spec > { HwaTptc1EnableClrW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Interrupt Enable Clear Register for hwa_tptc2_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_tptc2_enable_clr (& mut self) -> HwaTptc2EnableClrW < DedEnableClrReg0Spec > { HwaTptc2EnableClrW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem0_ramecc_enable_clr (& mut self) -> SharedMem0RameccEnableClrW < DedEnableClrReg0Spec > { SharedMem0RameccEnableClrW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem1_ramecc_enable_clr (& mut self) -> SharedMem1RameccEnableClrW < DedEnableClrReg0Spec > { SharedMem1RameccEnableClrW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Interrupt Enable Clear Register for hwa_param_mem_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn hwa_param_mem_enable_clr (& mut self) -> HwaParamMemEnableClrW < DedEnableClrReg0Spec > { HwaParamMemEnableClrW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn shared_mem2_ramecc_enable_clr (& mut self) -> SharedMem2RameccEnableClrW < DedEnableClrReg0Spec > { SharedMem2RameccEnableClrW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Interrupt Enable Clear Register for adcping_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcping_ramecc_enable_clr (& mut self) -> AdcpingRameccEnableClrW < DedEnableClrReg0Spec > { AdcpingRameccEnableClrW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW )"]
# [inline (always)]
# [must_use]
pub fn adcpong_ramecc_enable_clr (& mut self) -> AdcpongRameccEnableClrW < DedEnableClrReg0Spec > { AdcpongRameccEnableClrW :: new (self , 13) } # [doc = "Bits 14:31 - 31:14\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res14 (& mut self) -> Res14W < DedEnableClrReg0Spec > { Res14W :: new (self , 14) } } # [doc = "Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ded_enable_clr_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ded_enable_clr_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DedEnableClrReg0Spec ; impl crate :: RegisterSpec for DedEnableClrReg0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`ded_enable_clr_reg0::R`](R) reader structure"]
impl crate :: Readable for DedEnableClrReg0Spec { } # [doc = "`write(|w| ..)` method takes [`ded_enable_clr_reg0::W`](W) writer structure"]
impl crate :: Writable for DedEnableClrReg0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DED_ENABLE_CLR_REG0 to value 0"]
impl crate :: Resettable for DedEnableClrReg0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_ENABLE_SET (rw) register accessor: AGGR interrupt enable set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_enable_set`]
module"]
# [doc (alias = "AGGR_ENABLE_SET")]
pub type AggrEnableSet = crate :: Reg < aggr_enable_set :: AggrEnableSetSpec > ; # [doc = "AGGR interrupt enable set Register"]
pub mod aggr_enable_set { # [doc = "Register `AGGR_ENABLE_SET` reader"]
pub type R = crate :: R < AggrEnableSetSpec > ; # [doc = "Register `AGGR_ENABLE_SET` writer"]
pub type W = crate :: W < AggrEnableSetSpec > ; # [doc = "Field `PARITY` reader - 0:0\\]
interrupt enable set for parity errors - (RW )"]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 0:0\\]
interrupt enable set for parity errors - (RW )"]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT` reader - 1:1\\]
interrupt enable set for svbus timeout errors - (RW )"]
pub type TimeoutR = crate :: BitReader ; # [doc = "Field `TIMEOUT` writer - 1:1\\]
interrupt enable set for svbus timeout errors - (RW )"]
pub type TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES15` reader - 31:2\\]
RESERVE FIELD"]
pub type Res15R = crate :: FieldReader < u32 > ; # [doc = "Field `RES15` writer - 31:2\\]
RESERVE FIELD"]
pub type Res15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
interrupt enable set for parity errors - (RW )"]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
interrupt enable set for svbus timeout errors - (RW )"]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res15 (& self) -> Res15R { Res15R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
interrupt enable set for parity errors - (RW )"]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrEnableSetSpec > { ParityW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
interrupt enable set for svbus timeout errors - (RW )"]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrEnableSetSpec > { TimeoutW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res15 (& mut self) -> Res15W < AggrEnableSetSpec > { Res15W :: new (self , 2) } } # [doc = "AGGR interrupt enable set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrEnableSetSpec ; impl crate :: RegisterSpec for AggrEnableSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_enable_set::R`](R) reader structure"]
impl crate :: Readable for AggrEnableSetSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_enable_set::W`](W) writer structure"]
impl crate :: Writable for AggrEnableSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_ENABLE_SET to value 0"]
impl crate :: Resettable for AggrEnableSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_ENABLE_CLR (rw) register accessor: AGGR interrupt enable clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_enable_clr`]
module"]
# [doc (alias = "AGGR_ENABLE_CLR")]
pub type AggrEnableClr = crate :: Reg < aggr_enable_clr :: AggrEnableClrSpec > ; # [doc = "AGGR interrupt enable clear Register"]
pub mod aggr_enable_clr { # [doc = "Register `AGGR_ENABLE_CLR` reader"]
pub type R = crate :: R < AggrEnableClrSpec > ; # [doc = "Register `AGGR_ENABLE_CLR` writer"]
pub type W = crate :: W < AggrEnableClrSpec > ; # [doc = "Field `PARITY` reader - 0:0\\]
interrupt enable clear for parity errors - (RW )"]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 0:0\\]
interrupt enable clear for parity errors - (RW )"]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT` reader - 1:1\\]
interrupt enable clear for svbus timeout errors - (RW )"]
pub type TimeoutR = crate :: BitReader ; # [doc = "Field `TIMEOUT` writer - 1:1\\]
interrupt enable clear for svbus timeout errors - (RW )"]
pub type TimeoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RES16` reader - 31:2\\]
RESERVE FIELD"]
pub type Res16R = crate :: FieldReader < u32 > ; # [doc = "Field `RES16` writer - 31:2\\]
RESERVE FIELD"]
pub type Res16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
interrupt enable clear for parity errors - (RW )"]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
interrupt enable clear for svbus timeout errors - (RW )"]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res16 (& self) -> Res16R { Res16R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
interrupt enable clear for parity errors - (RW )"]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrEnableClrSpec > { ParityW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
interrupt enable clear for svbus timeout errors - (RW )"]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrEnableClrSpec > { TimeoutW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res16 (& mut self) -> Res16W < AggrEnableClrSpec > { Res16W :: new (self , 2) } } # [doc = "AGGR interrupt enable clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_enable_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_enable_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrEnableClrSpec ; impl crate :: RegisterSpec for AggrEnableClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_enable_clr::R`](R) reader structure"]
impl crate :: Readable for AggrEnableClrSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_enable_clr::W`](W) writer structure"]
impl crate :: Writable for AggrEnableClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_ENABLE_CLR to value 0"]
impl crate :: Resettable for AggrEnableClrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_STATUS_SET (rw) register accessor: AGGR interrupt status set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_status_set`]
module"]
# [doc (alias = "AGGR_STATUS_SET")]
pub type AggrStatusSet = crate :: Reg < aggr_status_set :: AggrStatusSetSpec > ; # [doc = "AGGR interrupt status set Register"]
pub mod aggr_status_set { # [doc = "Register `AGGR_STATUS_SET` reader"]
pub type R = crate :: R < AggrStatusSetSpec > ; # [doc = "Register `AGGR_STATUS_SET` writer"]
pub type W = crate :: W < AggrStatusSetSpec > ; # [doc = "Field `PARITY` reader - 1:0\\]
interrupt status set for parity errors - (RW incr)"]
pub type ParityR = crate :: FieldReader ; # [doc = "Field `PARITY` writer - 1:0\\]
interrupt status set for parity errors - (RW incr)"]
pub type ParityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIMEOUT` reader - 3:2\\]
interrupt status set for svbus timeout errors - (RW incr)"]
pub type TimeoutR = crate :: FieldReader ; # [doc = "Field `TIMEOUT` writer - 3:2\\]
interrupt status set for svbus timeout errors - (RW incr)"]
pub type TimeoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES17` reader - 31:4\\]
RESERVE FIELD"]
pub type Res17R = crate :: FieldReader < u32 > ; # [doc = "Field `RES17` writer - 31:4\\]
RESERVE FIELD"]
pub type Res17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
interrupt status set for parity errors - (RW incr)"]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
interrupt status set for svbus timeout errors - (RW incr)"]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:31 - 31:4\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res17 (& self) -> Res17R { Res17R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
interrupt status set for parity errors - (RW incr)"]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrStatusSetSpec > { ParityW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
interrupt status set for svbus timeout errors - (RW incr)"]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrStatusSetSpec > { TimeoutW :: new (self , 2) } # [doc = "Bits 4:31 - 31:4\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res17 (& mut self) -> Res17W < AggrStatusSetSpec > { Res17W :: new (self , 4) } } # [doc = "AGGR interrupt status set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrStatusSetSpec ; impl crate :: RegisterSpec for AggrStatusSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_status_set::R`](R) reader structure"]
impl crate :: Readable for AggrStatusSetSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_status_set::W`](W) writer structure"]
impl crate :: Writable for AggrStatusSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_STATUS_SET to value 0"]
impl crate :: Resettable for AggrStatusSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AGGR_STATUS_CLR (rw) register accessor: AGGR interrupt status clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aggr_status_clr`]
module"]
# [doc (alias = "AGGR_STATUS_CLR")]
pub type AggrStatusClr = crate :: Reg < aggr_status_clr :: AggrStatusClrSpec > ; # [doc = "AGGR interrupt status clear Register"]
pub mod aggr_status_clr { # [doc = "Register `AGGR_STATUS_CLR` reader"]
pub type R = crate :: R < AggrStatusClrSpec > ; # [doc = "Register `AGGR_STATUS_CLR` writer"]
pub type W = crate :: W < AggrStatusClrSpec > ; # [doc = "Field `PARITY` reader - 1:0\\]
interrupt status clear for parity errors - (RW decr)"]
pub type ParityR = crate :: FieldReader ; # [doc = "Field `PARITY` writer - 1:0\\]
interrupt status clear for parity errors - (RW decr)"]
pub type ParityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIMEOUT` reader - 3:2\\]
interrupt status clear for svbus timeout errors - (RW decr)"]
pub type TimeoutR = crate :: FieldReader ; # [doc = "Field `TIMEOUT` writer - 3:2\\]
interrupt status clear for svbus timeout errors - (RW decr)"]
pub type TimeoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RES18` reader - 31:4\\]
RESERVE FIELD"]
pub type Res18R = crate :: FieldReader < u32 > ; # [doc = "Field `RES18` writer - 31:4\\]
RESERVE FIELD"]
pub type Res18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
interrupt status clear for parity errors - (RW decr)"]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
interrupt status clear for svbus timeout errors - (RW decr)"]
# [inline (always)]
pub fn timeout (& self) -> TimeoutR { TimeoutR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:31 - 31:4\\]
RESERVE FIELD"]
# [inline (always)]
pub fn res18 (& self) -> Res18R { Res18R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
interrupt status clear for parity errors - (RW decr)"]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < AggrStatusClrSpec > { ParityW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
interrupt status clear for svbus timeout errors - (RW decr)"]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TimeoutW < AggrStatusClrSpec > { TimeoutW :: new (self , 2) } # [doc = "Bits 4:31 - 31:4\\]
RESERVE FIELD"]
# [inline (always)]
# [must_use]
pub fn res18 (& mut self) -> Res18W < AggrStatusClrSpec > { Res18W :: new (self , 4) } } # [doc = "AGGR interrupt status clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aggr_status_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aggr_status_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AggrStatusClrSpec ; impl crate :: RegisterSpec for AggrStatusClrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aggr_status_clr::R`](R) reader structure"]
impl crate :: Readable for AggrStatusClrSpec { } # [doc = "`write(|w| ..)` method takes [`aggr_status_clr::W`](W) writer structure"]
impl crate :: Writable for AggrStatusClrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AGGR_STATUS_CLR to value 0"]
impl crate :: Resettable for AggrStatusClrSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_RTI"]
pub struct AppRti { _marker : PhantomData < * const () > } unsafe impl Send for AppRti { } impl AppRti { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_rti :: RegisterBlock = 0x56f7_f000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_rti :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppRti { type Target = app_rti :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppRti { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppRti") . finish () } } # [doc = "APP_RTI"]
pub mod app_rti { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { rtigctrl : Rtigctrl , rtitbctrl : Rtitbctrl , rticapctrl : Rticapctrl , rticompctrl : Rticompctrl , rtifrc0 : Rtifrc0 , rtiuc0 : Rtiuc0 , rticpuc0 : Rticpuc0 , _reserved7 : [u8 ; 0x04]
, rticafrc0 : Rticafrc0 , rticauc0 : Rticauc0 , _reserved9 : [u8 ; 0x08]
, rtifrc1 : Rtifrc1 , rtiuc1 : Rtiuc1 , rticpuc1 : Rticpuc1 , _reserved12 : [u8 ; 0x04]
, rticafrc1 : Rticafrc1 , rticauc1 : Rticauc1 , _reserved14 : [u8 ; 0x08]
, rticomp0 : Rticomp0 , rtiudcp0 : Rtiudcp0 , rticomp1 : Rticomp1 , rtiudcp1 : Rtiudcp1 , rticomp2 : Rticomp2 , rtiudcp2 : Rtiudcp2 , rticomp3 : Rticomp3 , rtiudcp3 : Rtiudcp3 , rtitblcomp : Rtitblcomp , rtitbhcomp : Rtitbhcomp , _reserved24 : [u8 ; 0x08]
, rtisetint : Rtisetint , rticlearint : Rticlearint , rtiintflag : Rtiintflag , _reserved27 : [u8 ; 0x04]
, rtidwdctrl : Rtidwdctrl , rtidwdprld : Rtidwdprld , rtiwdstatus : Rtiwdstatus , rtiwdkey : Rtiwdkey , rtidwdcntr : Rtidwdcntr , rtiwwdrxnctrl : Rtiwwdrxnctrl , rtiwwdsizectrl : Rtiwwdsizectrl , rtiintclrenable : Rtiintclrenable , rticomp0clr : Rticomp0clr , rticomp1clr : Rticomp1clr , rticomp2clr : Rticomp2clr , rticomp3clr : Rticomp3clr , } impl RegisterBlock { # [doc = "0x00 - Global Control Register starts / stops the counters"]
# [inline (always)]
pub const fn rtigctrl (& self) -> & Rtigctrl { & self . rtigctrl } # [doc = "0x04 - Timebase Control selection which source triggers free running counter 0"]
# [inline (always)]
pub const fn rtitbctrl (& self) -> & Rtitbctrl { & self . rtitbctrl } # [doc = "0x08 - Capture Control controls the capture source for the counters"]
# [inline (always)]
pub const fn rticapctrl (& self) -> & Rticapctrl { & self . rticapctrl } # [doc = "0x0c - Compare Control controls the source for the compare registers"]
# [inline (always)]
pub const fn rticompctrl (& self) -> & Rticompctrl { & self . rticompctrl } # [doc = "0x10 - Free Running Counter 0 current value of free running counter 0"]
# [inline (always)]
pub const fn rtifrc0 (& self) -> & Rtifrc0 { & self . rtifrc0 } # [doc = "0x14 - Up Counter 0 current value of prescale counter 0"]
# [inline (always)]
pub const fn rtiuc0 (& self) -> & Rtiuc0 { & self . rtiuc0 } # [doc = "0x18 - Compare Up Counter 0 compare value compared with prescale counter 0"]
# [inline (always)]
pub const fn rticpuc0 (& self) -> & Rticpuc0 { & self . rticpuc0 } # [doc = "0x20 - Capture Free Running Counter 0 current value of free running counter 0 on external event"]
# [inline (always)]
pub const fn rticafrc0 (& self) -> & Rticafrc0 { & self . rticafrc0 } # [doc = "0x24 - Capture Up Counter 0 current value of prescale counter 0 on external event"]
# [inline (always)]
pub const fn rticauc0 (& self) -> & Rticauc0 { & self . rticauc0 } # [doc = "0x30 - Free Running Counter 1 current value of free running counter 1"]
# [inline (always)]
pub const fn rtifrc1 (& self) -> & Rtifrc1 { & self . rtifrc1 } # [doc = "0x34 - Up Counter 1 current value of prescale counter 1"]
# [inline (always)]
pub const fn rtiuc1 (& self) -> & Rtiuc1 { & self . rtiuc1 } # [doc = "0x38 - Compare Up Counter 1 compare value compared with prescale counter 1"]
# [inline (always)]
pub const fn rticpuc1 (& self) -> & Rticpuc1 { & self . rticpuc1 } # [doc = "0x40 - Capture Free Running Counter 1 current value of free running counter 1 on external event"]
# [inline (always)]
pub const fn rticafrc1 (& self) -> & Rticafrc1 { & self . rticafrc1 } # [doc = "0x44 - Capture Up Counter 1 current value of prescale counter 1 on external event"]
# [inline (always)]
pub const fn rticauc1 (& self) -> & Rticauc1 { & self . rticauc1 } # [doc = "0x50 - Compare 0 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp0 (& self) -> & Rticomp0 { & self . rticomp0 } # [doc = "0x54 - Update Compare 0 value to be added to the compare register 0 value on compare match"]
# [inline (always)]
pub const fn rtiudcp0 (& self) -> & Rtiudcp0 { & self . rtiudcp0 } # [doc = "0x58 - Compare 1 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp1 (& self) -> & Rticomp1 { & self . rticomp1 } # [doc = "0x5c - Update Compare 1 value to be added to the compare register 1 value on compare match"]
# [inline (always)]
pub const fn rtiudcp1 (& self) -> & Rtiudcp1 { & self . rtiudcp1 } # [doc = "0x60 - Compare 2 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp2 (& self) -> & Rticomp2 { & self . rticomp2 } # [doc = "0x64 - Update Compare 2 value to be added to the compare register 2 value on compare match"]
# [inline (always)]
pub const fn rtiudcp2 (& self) -> & Rtiudcp2 { & self . rtiudcp2 } # [doc = "0x68 - Compare 3 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp3 (& self) -> & Rticomp3 { & self . rticomp3 } # [doc = "0x6c - Update Compare 3 value to be added to the compare register 3 value on compare match"]
# [inline (always)]
pub const fn rtiudcp3 (& self) -> & Rtiudcp3 { & self . rtiudcp3 } # [doc = "0x70 - Timebase Low Compare compare value to activate edge detection circuit"]
# [inline (always)]
pub const fn rtitblcomp (& self) -> & Rtitblcomp { & self . rtitblcomp } # [doc = "0x74 - Timebase High Compare compare value to deactivate edge detection circuit"]
# [inline (always)]
pub const fn rtitbhcomp (& self) -> & Rtitbhcomp { & self . rtitbhcomp } # [doc = "0x80 - Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
# [inline (always)]
pub const fn rtisetint (& self) -> & Rtisetint { & self . rtisetint } # [doc = "0x84 - Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
# [inline (always)]
pub const fn rticlearint (& self) -> & Rticlearint { & self . rticlearint } # [doc = "0x88 - Interrupt Flags interrupt pending bits"]
# [inline (always)]
pub const fn rtiintflag (& self) -> & Rtiintflag { & self . rtiintflag } # [doc = "0x90 - Digital Watchdog Control Enables the Digital Watchdog"]
# [inline (always)]
pub const fn rtidwdctrl (& self) -> & Rtidwdctrl { & self . rtidwdctrl } # [doc = "0x94 - Digital Watchdog Preload sets the experation time of the Digital Watchdog"]
# [inline (always)]
pub const fn rtidwdprld (& self) -> & Rtidwdprld { & self . rtidwdprld } # [doc = "0x98 - Watchdog Status reflects the status of Analog and Digital Watchdog"]
# [inline (always)]
pub const fn rtiwdstatus (& self) -> & Rtiwdstatus { & self . rtiwdstatus } # [doc = "0x9c - Watchdog Key correct written key values discharge the external capacitor"]
# [inline (always)]
pub const fn rtiwdkey (& self) -> & Rtiwdkey { & self . rtiwdkey } # [doc = "0xa0 - Digital Watchdog Down Counter current value of DWD down counter"]
# [inline (always)]
pub const fn rtidwdcntr (& self) -> & Rtidwdcntr { & self . rtidwdcntr } # [doc = "0xa4 - Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"]
# [inline (always)]
pub const fn rtiwwdrxnctrl (& self) -> & Rtiwwdrxnctrl { & self . rtiwwdrxnctrl } # [doc = "0xa8 - Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"]
# [inline (always)]
pub const fn rtiwwdsizectrl (& self) -> & Rtiwwdsizectrl { & self . rtiwwdsizectrl } # [doc = "0xac - RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"]
# [inline (always)]
pub const fn rtiintclrenable (& self) -> & Rtiintclrenable { & self . rtiintclrenable } # [doc = "0xb0 - Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"]
# [inline (always)]
pub const fn rticomp0clr (& self) -> & Rticomp0clr { & self . rticomp0clr } # [doc = "0xb4 - Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"]
# [inline (always)]
pub const fn rticomp1clr (& self) -> & Rticomp1clr { & self . rticomp1clr } # [doc = "0xb8 - Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"]
# [inline (always)]
pub const fn rticomp2clr (& self) -> & Rticomp2clr { & self . rticomp2clr } # [doc = "0xbc - Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"]
# [inline (always)]
pub const fn rticomp3clr (& self) -> & Rticomp3clr { & self . rticomp3clr } } # [doc = "RTIGCTRL (rw) register accessor: Global Control Register starts / stops the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rtigctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtigctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtigctrl`]
module"]
# [doc (alias = "RTIGCTRL")]
pub type Rtigctrl = crate :: Reg < rtigctrl :: RtigctrlSpec > ; # [doc = "Global Control Register starts / stops the counters"]
pub mod rtigctrl { # [doc = "Register `RTIGCTRL` reader"]
pub type R = crate :: R < RtigctrlSpec > ; # [doc = "Register `RTIGCTRL` writer"]
pub type W = crate :: W < RtigctrlSpec > ; # [doc = "Field `CNT0EN` reader - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
pub type Cnt0enR = crate :: BitReader ; # [doc = "Field `CNT0EN` writer - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
pub type Cnt0enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CNT1EN` reader - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
pub type Cnt1enR = crate :: BitReader ; # [doc = "Field `CNT1EN` writer - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
pub type Cnt1enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED1` writer - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `COS` reader - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
pub type CosR = crate :: BitReader ; # [doc = "Field `COS` writer - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
pub type CosW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NTUSEL` reader - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
pub type NtuselR = crate :: FieldReader ; # [doc = "Field `NTUSEL` writer - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
pub type NtuselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED2` reader - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED2` writer - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
# [inline (always)]
pub fn cnt0en (& self) -> Cnt0enR { Cnt0enR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
# [inline (always)]
pub fn cnt1en (& self) -> Cnt1enR { Cnt1enR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:14 - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x1fff) as u16) } # [doc = "Bit 15 - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
# [inline (always)]
pub fn cos (& self) -> CosR { CosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
# [inline (always)]
pub fn ntusel (& self) -> NtuselR { NtuselR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:31 - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
# [inline (always)]
# [must_use]
pub fn cnt0en (& mut self) -> Cnt0enW < RtigctrlSpec > { Cnt0enW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
# [inline (always)]
# [must_use]
pub fn cnt1en (& mut self) -> Cnt1enW < RtigctrlSpec > { Cnt1enW :: new (self , 1) } # [doc = "Bits 2:14 - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < RtigctrlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 15 - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
# [inline (always)]
# [must_use]
pub fn cos (& mut self) -> CosW < RtigctrlSpec > { CosW :: new (self , 15) } # [doc = "Bits 16:19 - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
# [inline (always)]
# [must_use]
pub fn ntusel (& mut self) -> NtuselW < RtigctrlSpec > { NtuselW :: new (self , 16) } # [doc = "Bits 20:31 - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < RtigctrlSpec > { Reserved2W :: new (self , 20) } } # [doc = "Global Control Register starts / stops the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rtigctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtigctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtigctrlSpec ; impl crate :: RegisterSpec for RtigctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtigctrl::R`](R) reader structure"]
impl crate :: Readable for RtigctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtigctrl::W`](W) writer structure"]
impl crate :: Writable for RtigctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIGCTRL to value 0"]
impl crate :: Resettable for RtigctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTITBCTRL (rw) register accessor: Timebase Control selection which source triggers free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtitbctrl`]
module"]
# [doc (alias = "RTITBCTRL")]
pub type Rtitbctrl = crate :: Reg < rtitbctrl :: RtitbctrlSpec > ; # [doc = "Timebase Control selection which source triggers free running counter 0"]
pub mod rtitbctrl { # [doc = "Register `RTITBCTRL` reader"]
pub type R = crate :: R < RtitbctrlSpec > ; # [doc = "Register `RTITBCTRL` writer"]
pub type W = crate :: W < RtitbctrlSpec > ; # [doc = "Field `TBEXT` reader - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
pub type TbextR = crate :: BitReader ; # [doc = "Field `TBEXT` writer - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
pub type TbextW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INC` reader - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
pub type IncR = crate :: BitReader ; # [doc = "Field `INC` writer - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
pub type IncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 31:2\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED3` writer - 31:2\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
# [inline (always)]
pub fn tbext (& self) -> TbextR { TbextR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
# [inline (always)]
pub fn inc (& self) -> IncR { IncR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
# [inline (always)]
# [must_use]
pub fn tbext (& mut self) -> TbextW < RtitbctrlSpec > { TbextW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
# [inline (always)]
# [must_use]
pub fn inc (& mut self) -> IncW < RtitbctrlSpec > { IncW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < RtitbctrlSpec > { Reserved3W :: new (self , 2) } } # [doc = "Timebase Control selection which source triggers free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtitbctrlSpec ; impl crate :: RegisterSpec for RtitbctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtitbctrl::R`](R) reader structure"]
impl crate :: Readable for RtitbctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtitbctrl::W`](W) writer structure"]
impl crate :: Writable for RtitbctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTITBCTRL to value 0"]
impl crate :: Resettable for RtitbctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAPCTRL (rw) register accessor: Capture Control controls the capture source for the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticapctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticapctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticapctrl`]
module"]
# [doc (alias = "RTICAPCTRL")]
pub type Rticapctrl = crate :: Reg < rticapctrl :: RticapctrlSpec > ; # [doc = "Capture Control controls the capture source for the counters"]
pub mod rticapctrl { # [doc = "Register `RTICAPCTRL` reader"]
pub type R = crate :: R < RticapctrlSpec > ; # [doc = "Register `RTICAPCTRL` writer"]
pub type W = crate :: W < RticapctrlSpec > ; # [doc = "Field `CAPCNTR0` reader - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
pub type Capcntr0R = crate :: BitReader ; # [doc = "Field `CAPCNTR0` writer - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
pub type Capcntr0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAPCNTR1` reader - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
pub type Capcntr1R = crate :: BitReader ; # [doc = "Field `CAPCNTR1` writer - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
pub type Capcntr1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved4R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED4` writer - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
# [inline (always)]
pub fn capcntr0 (& self) -> Capcntr0R { Capcntr0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
# [inline (always)]
pub fn capcntr1 (& self) -> Capcntr1R { Capcntr1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
# [inline (always)]
# [must_use]
pub fn capcntr0 (& mut self) -> Capcntr0W < RticapctrlSpec > { Capcntr0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
# [inline (always)]
# [must_use]
pub fn capcntr1 (& mut self) -> Capcntr1W < RticapctrlSpec > { Capcntr1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < RticapctrlSpec > { Reserved4W :: new (self , 2) } } # [doc = "Capture Control controls the capture source for the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticapctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticapctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticapctrlSpec ; impl crate :: RegisterSpec for RticapctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticapctrl::R`](R) reader structure"]
impl crate :: Readable for RticapctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rticapctrl::W`](W) writer structure"]
impl crate :: Writable for RticapctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAPCTRL to value 0"]
impl crate :: Resettable for RticapctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMPCTRL (rw) register accessor: Compare Control controls the source for the compare registers\n\nYou can [`read`](crate::Reg::read) this register and get [`rticompctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticompctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticompctrl`]
module"]
# [doc (alias = "RTICOMPCTRL")]
pub type Rticompctrl = crate :: Reg < rticompctrl :: RticompctrlSpec > ; # [doc = "Compare Control controls the source for the compare registers"]
pub mod rticompctrl { # [doc = "Register `RTICOMPCTRL` reader"]
pub type R = crate :: R < RticompctrlSpec > ; # [doc = "Register `RTICOMPCTRL` writer"]
pub type W = crate :: W < RticompctrlSpec > ; # [doc = "Field `COMP0SEL` reader - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp0selR = crate :: BitReader ; # [doc = "Field `COMP0SEL` writer - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp0selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED5` reader - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `RESERVED5` writer - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMP1SEL` reader - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp1selR = crate :: BitReader ; # [doc = "Field `COMP1SEL` writer - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp1selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED6` reader - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved6R = crate :: FieldReader ; # [doc = "Field `RESERVED6` writer - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMP2SEL` reader - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp2selR = crate :: BitReader ; # [doc = "Field `COMP2SEL` writer - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp2selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED7` reader - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved7R = crate :: FieldReader ; # [doc = "Field `RESERVED7` writer - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMP3SEL` reader - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp3selR = crate :: BitReader ; # [doc = "Field `COMP3SEL` writer - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp3selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED8` reader - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved8R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED8` writer - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 19 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp0sel (& self) -> Comp0selR { Comp0selR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:3 - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 1) & 7) as u8) } # [doc = "Bit 4 - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp1sel (& self) -> Comp1selR { Comp1selR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:7 - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved6 (& self) -> Reserved6R { Reserved6R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp2sel (& self) -> Comp2selR { Comp2selR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:11 - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved7 (& self) -> Reserved7R { Reserved7R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bit 12 - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp3sel (& self) -> Comp3selR { Comp3selR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:31 - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved8 (& self) -> Reserved8R { Reserved8R :: new ((self . bits >> 13) & 0x0007_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp0sel (& mut self) -> Comp0selW < RticompctrlSpec > { Comp0selW :: new (self , 0) } # [doc = "Bits 1:3 - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < RticompctrlSpec > { Reserved5W :: new (self , 1) } # [doc = "Bit 4 - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp1sel (& mut self) -> Comp1selW < RticompctrlSpec > { Comp1selW :: new (self , 4) } # [doc = "Bits 5:7 - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved6 (& mut self) -> Reserved6W < RticompctrlSpec > { Reserved6W :: new (self , 5) } # [doc = "Bit 8 - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp2sel (& mut self) -> Comp2selW < RticompctrlSpec > { Comp2selW :: new (self , 8) } # [doc = "Bits 9:11 - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved7 (& mut self) -> Reserved7W < RticompctrlSpec > { Reserved7W :: new (self , 9) } # [doc = "Bit 12 - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp3sel (& mut self) -> Comp3selW < RticompctrlSpec > { Comp3selW :: new (self , 12) } # [doc = "Bits 13:31 - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved8 (& mut self) -> Reserved8W < RticompctrlSpec > { Reserved8W :: new (self , 13) } } # [doc = "Compare Control controls the source for the compare registers\n\nYou can [`read`](crate::Reg::read) this register and get [`rticompctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticompctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticompctrlSpec ; impl crate :: RegisterSpec for RticompctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticompctrl::R`](R) reader structure"]
impl crate :: Readable for RticompctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rticompctrl::W`](W) writer structure"]
impl crate :: Writable for RticompctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMPCTRL to value 0"]
impl crate :: Resettable for RticompctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIFRC0 (rw) register accessor: Free Running Counter 0 current value of free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtifrc0`]
module"]
# [doc (alias = "RTIFRC0")]
pub type Rtifrc0 = crate :: Reg < rtifrc0 :: Rtifrc0Spec > ; # [doc = "Free Running Counter 0 current value of free running counter 0"]
pub mod rtifrc0 { # [doc = "Register `RTIFRC0` reader"]
pub type R = crate :: R < Rtifrc0Spec > ; # [doc = "Register `RTIFRC0` writer"]
pub type W = crate :: W < Rtifrc0Spec > ; # [doc = "Field `FRC0` reader - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
pub type Frc0R = crate :: FieldReader < u32 > ; # [doc = "Field `FRC0` writer - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
pub type Frc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
# [inline (always)]
pub fn frc0 (& self) -> Frc0R { Frc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
# [inline (always)]
# [must_use]
pub fn frc0 (& mut self) -> Frc0W < Rtifrc0Spec > { Frc0W :: new (self , 0) } } # [doc = "Free Running Counter 0 current value of free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtifrc0Spec ; impl crate :: RegisterSpec for Rtifrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtifrc0::R`](R) reader structure"]
impl crate :: Readable for Rtifrc0Spec { } # [doc = "`write(|w| ..)` method takes [`rtifrc0::W`](W) writer structure"]
impl crate :: Writable for Rtifrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIFRC0 to value 0"]
impl crate :: Resettable for Rtifrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUC0 (rw) register accessor: Up Counter 0 current value of prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiuc0`]
module"]
# [doc (alias = "RTIUC0")]
pub type Rtiuc0 = crate :: Reg < rtiuc0 :: Rtiuc0Spec > ; # [doc = "Up Counter 0 current value of prescale counter 0"]
pub mod rtiuc0 { # [doc = "Register `RTIUC0` reader"]
pub type R = crate :: R < Rtiuc0Spec > ; # [doc = "Register `RTIUC0` writer"]
pub type W = crate :: W < Rtiuc0Spec > ; # [doc = "Field `UC0` reader - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
pub type Uc0R = crate :: FieldReader < u32 > ; # [doc = "Field `UC0` writer - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
pub type Uc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
# [inline (always)]
pub fn uc0 (& self) -> Uc0R { Uc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
# [inline (always)]
# [must_use]
pub fn uc0 (& mut self) -> Uc0W < Rtiuc0Spec > { Uc0W :: new (self , 0) } } # [doc = "Up Counter 0 current value of prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiuc0Spec ; impl crate :: RegisterSpec for Rtiuc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiuc0::R`](R) reader structure"]
impl crate :: Readable for Rtiuc0Spec { } # [doc = "`write(|w| ..)` method takes [`rtiuc0::W`](W) writer structure"]
impl crate :: Writable for Rtiuc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUC0 to value 0"]
impl crate :: Resettable for Rtiuc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICPUC0 (rw) register accessor: Compare Up Counter 0 compare value compared with prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticpuc0`]
module"]
# [doc (alias = "RTICPUC0")]
pub type Rticpuc0 = crate :: Reg < rticpuc0 :: Rticpuc0Spec > ; # [doc = "Compare Up Counter 0 compare value compared with prescale counter 0"]
pub mod rticpuc0 { # [doc = "Register `RTICPUC0` reader"]
pub type R = crate :: R < Rticpuc0Spec > ; # [doc = "Register `RTICPUC0` writer"]
pub type W = crate :: W < Rticpuc0Spec > ; # [doc = "Field `CPUC0` reader - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc0R = crate :: FieldReader < u32 > ; # [doc = "Field `CPUC0` writer - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
pub fn cpuc0 (& self) -> Cpuc0R { Cpuc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
# [must_use]
pub fn cpuc0 (& mut self) -> Cpuc0W < Rticpuc0Spec > { Cpuc0W :: new (self , 0) } } # [doc = "Compare Up Counter 0 compare value compared with prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticpuc0Spec ; impl crate :: RegisterSpec for Rticpuc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticpuc0::R`](R) reader structure"]
impl crate :: Readable for Rticpuc0Spec { } # [doc = "`write(|w| ..)` method takes [`rticpuc0::W`](W) writer structure"]
impl crate :: Writable for Rticpuc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICPUC0 to value 0"]
impl crate :: Resettable for Rticpuc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAFRC0 (rw) register accessor: Capture Free Running Counter 0 current value of free running counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticafrc0`]
module"]
# [doc (alias = "RTICAFRC0")]
pub type Rticafrc0 = crate :: Reg < rticafrc0 :: Rticafrc0Spec > ; # [doc = "Capture Free Running Counter 0 current value of free running counter 0 on external event"]
pub mod rticafrc0 { # [doc = "Register `RTICAFRC0` reader"]
pub type R = crate :: R < Rticafrc0Spec > ; # [doc = "Register `RTICAFRC0` writer"]
pub type W = crate :: W < Rticafrc0Spec > ; # [doc = "Field `CAFRC0` reader - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
pub type Cafrc0R = crate :: FieldReader < u32 > ; # [doc = "Field `CAFRC0` writer - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
pub type Cafrc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
# [inline (always)]
pub fn cafrc0 (& self) -> Cafrc0R { Cafrc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cafrc0 (& mut self) -> Cafrc0W < Rticafrc0Spec > { Cafrc0W :: new (self , 0) } } # [doc = "Capture Free Running Counter 0 current value of free running counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticafrc0Spec ; impl crate :: RegisterSpec for Rticafrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticafrc0::R`](R) reader structure"]
impl crate :: Readable for Rticafrc0Spec { } # [doc = "`write(|w| ..)` method takes [`rticafrc0::W`](W) writer structure"]
impl crate :: Writable for Rticafrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAFRC0 to value 0"]
impl crate :: Resettable for Rticafrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAUC0 (rw) register accessor: Capture Up Counter 0 current value of prescale counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticauc0`]
module"]
# [doc (alias = "RTICAUC0")]
pub type Rticauc0 = crate :: Reg < rticauc0 :: Rticauc0Spec > ; # [doc = "Capture Up Counter 0 current value of prescale counter 0 on external event"]
pub mod rticauc0 { # [doc = "Register `RTICAUC0` reader"]
pub type R = crate :: R < Rticauc0Spec > ; # [doc = "Register `RTICAUC0` writer"]
pub type W = crate :: W < Rticauc0Spec > ; # [doc = "Field `CAUC0` reader - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
pub type Cauc0R = crate :: FieldReader < u32 > ; # [doc = "Field `CAUC0` writer - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
pub type Cauc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
# [inline (always)]
pub fn cauc0 (& self) -> Cauc0R { Cauc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cauc0 (& mut self) -> Cauc0W < Rticauc0Spec > { Cauc0W :: new (self , 0) } } # [doc = "Capture Up Counter 0 current value of prescale counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticauc0Spec ; impl crate :: RegisterSpec for Rticauc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticauc0::R`](R) reader structure"]
impl crate :: Readable for Rticauc0Spec { } # [doc = "`write(|w| ..)` method takes [`rticauc0::W`](W) writer structure"]
impl crate :: Writable for Rticauc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAUC0 to value 0"]
impl crate :: Resettable for Rticauc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIFRC1 (rw) register accessor: Free Running Counter 1 current value of free running counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtifrc1`]
module"]
# [doc (alias = "RTIFRC1")]
pub type Rtifrc1 = crate :: Reg < rtifrc1 :: Rtifrc1Spec > ; # [doc = "Free Running Counter 1 current value of free running counter 1"]
pub mod rtifrc1 { # [doc = "Register `RTIFRC1` reader"]
pub type R = crate :: R < Rtifrc1Spec > ; # [doc = "Register `RTIFRC1` writer"]
pub type W = crate :: W < Rtifrc1Spec > ; # [doc = "Field `FRC1` reader - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
pub type Frc1R = crate :: FieldReader < u32 > ; # [doc = "Field `FRC1` writer - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
pub type Frc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
# [inline (always)]
pub fn frc1 (& self) -> Frc1R { Frc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
# [inline (always)]
# [must_use]
pub fn frc1 (& mut self) -> Frc1W < Rtifrc1Spec > { Frc1W :: new (self , 0) } } # [doc = "Free Running Counter 1 current value of free running counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtifrc1Spec ; impl crate :: RegisterSpec for Rtifrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtifrc1::R`](R) reader structure"]
impl crate :: Readable for Rtifrc1Spec { } # [doc = "`write(|w| ..)` method takes [`rtifrc1::W`](W) writer structure"]
impl crate :: Writable for Rtifrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIFRC1 to value 0"]
impl crate :: Resettable for Rtifrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUC1 (rw) register accessor: Up Counter 1 current value of prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiuc1`]
module"]
# [doc (alias = "RTIUC1")]
pub type Rtiuc1 = crate :: Reg < rtiuc1 :: Rtiuc1Spec > ; # [doc = "Up Counter 1 current value of prescale counter 1"]
pub mod rtiuc1 { # [doc = "Register `RTIUC1` reader"]
pub type R = crate :: R < Rtiuc1Spec > ; # [doc = "Register `RTIUC1` writer"]
pub type W = crate :: W < Rtiuc1Spec > ; # [doc = "Field `UC1` reader - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
pub type Uc1R = crate :: FieldReader < u32 > ; # [doc = "Field `UC1` writer - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
pub type Uc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
# [inline (always)]
pub fn uc1 (& self) -> Uc1R { Uc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
# [inline (always)]
# [must_use]
pub fn uc1 (& mut self) -> Uc1W < Rtiuc1Spec > { Uc1W :: new (self , 0) } } # [doc = "Up Counter 1 current value of prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiuc1Spec ; impl crate :: RegisterSpec for Rtiuc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiuc1::R`](R) reader structure"]
impl crate :: Readable for Rtiuc1Spec { } # [doc = "`write(|w| ..)` method takes [`rtiuc1::W`](W) writer structure"]
impl crate :: Writable for Rtiuc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUC1 to value 0"]
impl crate :: Resettable for Rtiuc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICPUC1 (rw) register accessor: Compare Up Counter 1 compare value compared with prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticpuc1`]
module"]
# [doc (alias = "RTICPUC1")]
pub type Rticpuc1 = crate :: Reg < rticpuc1 :: Rticpuc1Spec > ; # [doc = "Compare Up Counter 1 compare value compared with prescale counter 1"]
pub mod rticpuc1 { # [doc = "Register `RTICPUC1` reader"]
pub type R = crate :: R < Rticpuc1Spec > ; # [doc = "Register `RTICPUC1` writer"]
pub type W = crate :: W < Rticpuc1Spec > ; # [doc = "Field `CPUC1` reader - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc1R = crate :: FieldReader < u32 > ; # [doc = "Field `CPUC1` writer - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
pub fn cpuc1 (& self) -> Cpuc1R { Cpuc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
# [must_use]
pub fn cpuc1 (& mut self) -> Cpuc1W < Rticpuc1Spec > { Cpuc1W :: new (self , 0) } } # [doc = "Compare Up Counter 1 compare value compared with prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticpuc1Spec ; impl crate :: RegisterSpec for Rticpuc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticpuc1::R`](R) reader structure"]
impl crate :: Readable for Rticpuc1Spec { } # [doc = "`write(|w| ..)` method takes [`rticpuc1::W`](W) writer structure"]
impl crate :: Writable for Rticpuc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICPUC1 to value 0"]
impl crate :: Resettable for Rticpuc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAFRC1 (rw) register accessor: Capture Free Running Counter 1 current value of free running counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticafrc1`]
module"]
# [doc (alias = "RTICAFRC1")]
pub type Rticafrc1 = crate :: Reg < rticafrc1 :: Rticafrc1Spec > ; # [doc = "Capture Free Running Counter 1 current value of free running counter 1 on external event"]
pub mod rticafrc1 { # [doc = "Register `RTICAFRC1` reader"]
pub type R = crate :: R < Rticafrc1Spec > ; # [doc = "Register `RTICAFRC1` writer"]
pub type W = crate :: W < Rticafrc1Spec > ; # [doc = "Field `CAFRC1` reader - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
pub type Cafrc1R = crate :: FieldReader < u32 > ; # [doc = "Field `CAFRC1` writer - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
pub type Cafrc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
# [inline (always)]
pub fn cafrc1 (& self) -> Cafrc1R { Cafrc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cafrc1 (& mut self) -> Cafrc1W < Rticafrc1Spec > { Cafrc1W :: new (self , 0) } } # [doc = "Capture Free Running Counter 1 current value of free running counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticafrc1Spec ; impl crate :: RegisterSpec for Rticafrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticafrc1::R`](R) reader structure"]
impl crate :: Readable for Rticafrc1Spec { } # [doc = "`write(|w| ..)` method takes [`rticafrc1::W`](W) writer structure"]
impl crate :: Writable for Rticafrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAFRC1 to value 0"]
impl crate :: Resettable for Rticafrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAUC1 (rw) register accessor: Capture Up Counter 1 current value of prescale counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticauc1`]
module"]
# [doc (alias = "RTICAUC1")]
pub type Rticauc1 = crate :: Reg < rticauc1 :: Rticauc1Spec > ; # [doc = "Capture Up Counter 1 current value of prescale counter 1 on external event"]
pub mod rticauc1 { # [doc = "Register `RTICAUC1` reader"]
pub type R = crate :: R < Rticauc1Spec > ; # [doc = "Register `RTICAUC1` writer"]
pub type W = crate :: W < Rticauc1Spec > ; # [doc = "Field `CAUC1` reader - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
pub type Cauc1R = crate :: FieldReader < u32 > ; # [doc = "Field `CAUC1` writer - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
pub type Cauc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
# [inline (always)]
pub fn cauc1 (& self) -> Cauc1R { Cauc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cauc1 (& mut self) -> Cauc1W < Rticauc1Spec > { Cauc1W :: new (self , 0) } } # [doc = "Capture Up Counter 1 current value of prescale counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticauc1Spec ; impl crate :: RegisterSpec for Rticauc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticauc1::R`](R) reader structure"]
impl crate :: Readable for Rticauc1Spec { } # [doc = "`write(|w| ..)` method takes [`rticauc1::W`](W) writer structure"]
impl crate :: Writable for Rticauc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAUC1 to value 0"]
impl crate :: Resettable for Rticauc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP0 (rw) register accessor: Compare 0 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp0`]
module"]
# [doc (alias = "RTICOMP0")]
pub type Rticomp0 = crate :: Reg < rticomp0 :: Rticomp0Spec > ; # [doc = "Compare 0 compare value to be compared with the counters"]
pub mod rticomp0 { # [doc = "Register `RTICOMP0` reader"]
pub type R = crate :: R < Rticomp0Spec > ; # [doc = "Register `RTICOMP0` writer"]
pub type W = crate :: W < Rticomp0Spec > ; # [doc = "Field `COMP0` reader - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP0` writer - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp0 (& self) -> Comp0R { Comp0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp0 (& mut self) -> Comp0W < Rticomp0Spec > { Comp0W :: new (self , 0) } } # [doc = "Compare 0 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp0Spec ; impl crate :: RegisterSpec for Rticomp0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp0::R`](R) reader structure"]
impl crate :: Readable for Rticomp0Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp0::W`](W) writer structure"]
impl crate :: Writable for Rticomp0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP0 to value 0"]
impl crate :: Resettable for Rticomp0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP0 (rw) register accessor: Update Compare 0 value to be added to the compare register 0 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp0`]
module"]
# [doc (alias = "RTIUDCP0")]
pub type Rtiudcp0 = crate :: Reg < rtiudcp0 :: Rtiudcp0Spec > ; # [doc = "Update Compare 0 value to be added to the compare register 0 value on compare match"]
pub mod rtiudcp0 { # [doc = "Register `RTIUDCP0` reader"]
pub type R = crate :: R < Rtiudcp0Spec > ; # [doc = "Register `RTIUDCP0` writer"]
pub type W = crate :: W < Rtiudcp0Spec > ; # [doc = "Field `UDCP0` reader - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp0R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP0` writer - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp0 (& self) -> Udcp0R { Udcp0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp0 (& mut self) -> Udcp0W < Rtiudcp0Spec > { Udcp0W :: new (self , 0) } } # [doc = "Update Compare 0 value to be added to the compare register 0 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp0Spec ; impl crate :: RegisterSpec for Rtiudcp0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp0::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp0Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp0::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP0 to value 0"]
impl crate :: Resettable for Rtiudcp0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP1 (rw) register accessor: Compare 1 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp1`]
module"]
# [doc (alias = "RTICOMP1")]
pub type Rticomp1 = crate :: Reg < rticomp1 :: Rticomp1Spec > ; # [doc = "Compare 1 compare value to be compared with the counters"]
pub mod rticomp1 { # [doc = "Register `RTICOMP1` reader"]
pub type R = crate :: R < Rticomp1Spec > ; # [doc = "Register `RTICOMP1` writer"]
pub type W = crate :: W < Rticomp1Spec > ; # [doc = "Field `COMP1` reader - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP1` writer - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp1 (& self) -> Comp1R { Comp1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp1 (& mut self) -> Comp1W < Rticomp1Spec > { Comp1W :: new (self , 0) } } # [doc = "Compare 1 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp1Spec ; impl crate :: RegisterSpec for Rticomp1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp1::R`](R) reader structure"]
impl crate :: Readable for Rticomp1Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp1::W`](W) writer structure"]
impl crate :: Writable for Rticomp1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP1 to value 0"]
impl crate :: Resettable for Rticomp1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP1 (rw) register accessor: Update Compare 1 value to be added to the compare register 1 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp1`]
module"]
# [doc (alias = "RTIUDCP1")]
pub type Rtiudcp1 = crate :: Reg < rtiudcp1 :: Rtiudcp1Spec > ; # [doc = "Update Compare 1 value to be added to the compare register 1 value on compare match"]
pub mod rtiudcp1 { # [doc = "Register `RTIUDCP1` reader"]
pub type R = crate :: R < Rtiudcp1Spec > ; # [doc = "Register `RTIUDCP1` writer"]
pub type W = crate :: W < Rtiudcp1Spec > ; # [doc = "Field `UDCP1` reader - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp1R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP1` writer - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp1 (& self) -> Udcp1R { Udcp1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp1 (& mut self) -> Udcp1W < Rtiudcp1Spec > { Udcp1W :: new (self , 0) } } # [doc = "Update Compare 1 value to be added to the compare register 1 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp1Spec ; impl crate :: RegisterSpec for Rtiudcp1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp1::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp1Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp1::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP1 to value 0"]
impl crate :: Resettable for Rtiudcp1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP2 (rw) register accessor: Compare 2 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp2`]
module"]
# [doc (alias = "RTICOMP2")]
pub type Rticomp2 = crate :: Reg < rticomp2 :: Rticomp2Spec > ; # [doc = "Compare 2 compare value to be compared with the counters"]
pub mod rticomp2 { # [doc = "Register `RTICOMP2` reader"]
pub type R = crate :: R < Rticomp2Spec > ; # [doc = "Register `RTICOMP2` writer"]
pub type W = crate :: W < Rticomp2Spec > ; # [doc = "Field `COMP2` reader - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP2` writer - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp2 (& self) -> Comp2R { Comp2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp2 (& mut self) -> Comp2W < Rticomp2Spec > { Comp2W :: new (self , 0) } } # [doc = "Compare 2 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp2Spec ; impl crate :: RegisterSpec for Rticomp2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp2::R`](R) reader structure"]
impl crate :: Readable for Rticomp2Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp2::W`](W) writer structure"]
impl crate :: Writable for Rticomp2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP2 to value 0"]
impl crate :: Resettable for Rticomp2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP2 (rw) register accessor: Update Compare 2 value to be added to the compare register 2 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp2`]
module"]
# [doc (alias = "RTIUDCP2")]
pub type Rtiudcp2 = crate :: Reg < rtiudcp2 :: Rtiudcp2Spec > ; # [doc = "Update Compare 2 value to be added to the compare register 2 value on compare match"]
pub mod rtiudcp2 { # [doc = "Register `RTIUDCP2` reader"]
pub type R = crate :: R < Rtiudcp2Spec > ; # [doc = "Register `RTIUDCP2` writer"]
pub type W = crate :: W < Rtiudcp2Spec > ; # [doc = "Field `UDCP2` reader - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp2R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP2` writer - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp2 (& self) -> Udcp2R { Udcp2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp2 (& mut self) -> Udcp2W < Rtiudcp2Spec > { Udcp2W :: new (self , 0) } } # [doc = "Update Compare 2 value to be added to the compare register 2 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp2Spec ; impl crate :: RegisterSpec for Rtiudcp2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp2::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp2Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp2::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP2 to value 0"]
impl crate :: Resettable for Rtiudcp2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP3 (rw) register accessor: Compare 3 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp3`]
module"]
# [doc (alias = "RTICOMP3")]
pub type Rticomp3 = crate :: Reg < rticomp3 :: Rticomp3Spec > ; # [doc = "Compare 3 compare value to be compared with the counters"]
pub mod rticomp3 { # [doc = "Register `RTICOMP3` reader"]
pub type R = crate :: R < Rticomp3Spec > ; # [doc = "Register `RTICOMP3` writer"]
pub type W = crate :: W < Rticomp3Spec > ; # [doc = "Field `COMP3` reader - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP3` writer - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp3 (& self) -> Comp3R { Comp3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp3 (& mut self) -> Comp3W < Rticomp3Spec > { Comp3W :: new (self , 0) } } # [doc = "Compare 3 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp3Spec ; impl crate :: RegisterSpec for Rticomp3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp3::R`](R) reader structure"]
impl crate :: Readable for Rticomp3Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp3::W`](W) writer structure"]
impl crate :: Writable for Rticomp3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP3 to value 0"]
impl crate :: Resettable for Rticomp3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP3 (rw) register accessor: Update Compare 3 value to be added to the compare register 3 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp3`]
module"]
# [doc (alias = "RTIUDCP3")]
pub type Rtiudcp3 = crate :: Reg < rtiudcp3 :: Rtiudcp3Spec > ; # [doc = "Update Compare 3 value to be added to the compare register 3 value on compare match"]
pub mod rtiudcp3 { # [doc = "Register `RTIUDCP3` reader"]
pub type R = crate :: R < Rtiudcp3Spec > ; # [doc = "Register `RTIUDCP3` writer"]
pub type W = crate :: W < Rtiudcp3Spec > ; # [doc = "Field `UDCP3` reader - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp3R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP3` writer - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp3 (& self) -> Udcp3R { Udcp3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp3 (& mut self) -> Udcp3W < Rtiudcp3Spec > { Udcp3W :: new (self , 0) } } # [doc = "Update Compare 3 value to be added to the compare register 3 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp3Spec ; impl crate :: RegisterSpec for Rtiudcp3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp3::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp3Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp3::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP3 to value 0"]
impl crate :: Resettable for Rtiudcp3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTITBLCOMP (rw) register accessor: Timebase Low Compare compare value to activate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitblcomp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitblcomp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtitblcomp`]
module"]
# [doc (alias = "RTITBLCOMP")]
pub type Rtitblcomp = crate :: Reg < rtitblcomp :: RtitblcompSpec > ; # [doc = "Timebase Low Compare compare value to activate edge detection circuit"]
pub mod rtitblcomp { # [doc = "Register `RTITBLCOMP` reader"]
pub type R = crate :: R < RtitblcompSpec > ; # [doc = "Register `RTITBLCOMP` writer"]
pub type W = crate :: W < RtitblcompSpec > ; # [doc = "Field `TBLCOMP` reader - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TblcompR = crate :: FieldReader < u32 > ; # [doc = "Field `TBLCOMP` writer - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TblcompW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
pub fn tblcomp (& self) -> TblcompR { TblcompR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
# [must_use]
pub fn tblcomp (& mut self) -> TblcompW < RtitblcompSpec > { TblcompW :: new (self , 0) } } # [doc = "Timebase Low Compare compare value to activate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitblcomp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitblcomp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtitblcompSpec ; impl crate :: RegisterSpec for RtitblcompSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtitblcomp::R`](R) reader structure"]
impl crate :: Readable for RtitblcompSpec { } # [doc = "`write(|w| ..)` method takes [`rtitblcomp::W`](W) writer structure"]
impl crate :: Writable for RtitblcompSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTITBLCOMP to value 0"]
impl crate :: Resettable for RtitblcompSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTITBHCOMP (rw) register accessor: Timebase High Compare compare value to deactivate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbhcomp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbhcomp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtitbhcomp`]
module"]
# [doc (alias = "RTITBHCOMP")]
pub type Rtitbhcomp = crate :: Reg < rtitbhcomp :: RtitbhcompSpec > ; # [doc = "Timebase High Compare compare value to deactivate edge detection circuit"]
pub mod rtitbhcomp { # [doc = "Register `RTITBHCOMP` reader"]
pub type R = crate :: R < RtitbhcompSpec > ; # [doc = "Register `RTITBHCOMP` writer"]
pub type W = crate :: W < RtitbhcompSpec > ; # [doc = "Field `TBHCOMP` reader - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TbhcompR = crate :: FieldReader < u32 > ; # [doc = "Field `TBHCOMP` writer - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TbhcompW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
pub fn tbhcomp (& self) -> TbhcompR { TbhcompR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
# [must_use]
pub fn tbhcomp (& mut self) -> TbhcompW < RtitbhcompSpec > { TbhcompW :: new (self , 0) } } # [doc = "Timebase High Compare compare value to deactivate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbhcomp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbhcomp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtitbhcompSpec ; impl crate :: RegisterSpec for RtitbhcompSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtitbhcomp::R`](R) reader structure"]
impl crate :: Readable for RtitbhcompSpec { } # [doc = "`write(|w| ..)` method takes [`rtitbhcomp::W`](W) writer structure"]
impl crate :: Writable for RtitbhcompSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTITBHCOMP to value 0"]
impl crate :: Resettable for RtitbhcompSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTISETINT (rw) register accessor: Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rtisetint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtisetint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtisetint`]
module"]
# [doc (alias = "RTISETINT")]
pub type Rtisetint = crate :: Reg < rtisetint :: RtisetintSpec > ; # [doc = "Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
pub mod rtisetint { # [doc = "Register `RTISETINT` reader"]
pub type R = crate :: R < RtisetintSpec > ; # [doc = "Register `RTISETINT` writer"]
pub type W = crate :: W < RtisetintSpec > ; # [doc = "Field `SETINT0` reader - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint0R = crate :: BitReader ; # [doc = "Field `SETINT0` writer - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETINT1` reader - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint1R = crate :: BitReader ; # [doc = "Field `SETINT1` writer - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETINT2` reader - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint2R = crate :: BitReader ; # [doc = "Field `SETINT2` writer - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETINT3` reader - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
pub type Setint3R = crate :: BitReader ; # [doc = "Field `SETINT3` writer - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
pub type Setint3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED9` reader - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved9R = crate :: FieldReader ; # [doc = "Field `RESERVED9` writer - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `SETDMA0` reader - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma0R = crate :: BitReader ; # [doc = "Field `SETDMA0` writer - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETDMA1` reader - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma1R = crate :: BitReader ; # [doc = "Field `SETDMA1` writer - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETDMA2` reader - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma2R = crate :: BitReader ; # [doc = "Field `SETDMA2` writer - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETDMA3` reader - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma3R = crate :: BitReader ; # [doc = "Field `SETDMA3` writer - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED10` reader - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved10R = crate :: FieldReader ; # [doc = "Field `RESERVED10` writer - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `SETTBINT` reader - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SettbintR = crate :: BitReader ; # [doc = "Field `SETTBINT` writer - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SettbintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETOVL0INT` reader - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl0intR = crate :: BitReader ; # [doc = "Field `SETOVL0INT` writer - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl0intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETOVL1INT` reader - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl1intR = crate :: BitReader ; # [doc = "Field `SETOVL1INT` writer - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl1intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED11` reader - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved11R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED11` writer - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setint0 (& self) -> Setint0R { Setint0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setint1 (& self) -> Setint1R { Setint1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setint2 (& self) -> Setint2R { Setint2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
# [inline (always)]
pub fn setint3 (& self) -> Setint3R { Setint3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved9 (& self) -> Reserved9R { Reserved9R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma0 (& self) -> Setdma0R { Setdma0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma1 (& self) -> Setdma1R { Setdma1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma2 (& self) -> Setdma2R { Setdma2R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma3 (& self) -> Setdma3R { Setdma3R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved10 (& self) -> Reserved10R { Reserved10R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn settbint (& self) -> SettbintR { SettbintR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setovl0int (& self) -> Setovl0intR { Setovl0intR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setovl1int (& self) -> Setovl1intR { Setovl1intR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved11 (& self) -> Reserved11R { Reserved11R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setint0 (& mut self) -> Setint0W < RtisetintSpec > { Setint0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setint1 (& mut self) -> Setint1W < RtisetintSpec > { Setint1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setint2 (& mut self) -> Setint2W < RtisetintSpec > { Setint2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
# [inline (always)]
# [must_use]
pub fn setint3 (& mut self) -> Setint3W < RtisetintSpec > { Setint3W :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved9 (& mut self) -> Reserved9W < RtisetintSpec > { Reserved9W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma0 (& mut self) -> Setdma0W < RtisetintSpec > { Setdma0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma1 (& mut self) -> Setdma1W < RtisetintSpec > { Setdma1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma2 (& mut self) -> Setdma2W < RtisetintSpec > { Setdma2W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma3 (& mut self) -> Setdma3W < RtisetintSpec > { Setdma3W :: new (self , 11) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved10 (& mut self) -> Reserved10W < RtisetintSpec > { Reserved10W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn settbint (& mut self) -> SettbintW < RtisetintSpec > { SettbintW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setovl0int (& mut self) -> Setovl0intW < RtisetintSpec > { Setovl0intW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setovl1int (& mut self) -> Setovl1intW < RtisetintSpec > { Setovl1intW :: new (self , 18) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved11 (& mut self) -> Reserved11W < RtisetintSpec > { Reserved11W :: new (self , 19) } } # [doc = "Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rtisetint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtisetint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtisetintSpec ; impl crate :: RegisterSpec for RtisetintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtisetint::R`](R) reader structure"]
impl crate :: Readable for RtisetintSpec { } # [doc = "`write(|w| ..)` method takes [`rtisetint::W`](W) writer structure"]
impl crate :: Writable for RtisetintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTISETINT to value 0"]
impl crate :: Resettable for RtisetintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICLEARINT (rw) register accessor: Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rticlearint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticlearint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticlearint`]
module"]
# [doc (alias = "RTICLEARINT")]
pub type Rticlearint = crate :: Reg < rticlearint :: RticlearintSpec > ; # [doc = "Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
pub mod rticlearint { # [doc = "Register `RTICLEARINT` reader"]
pub type R = crate :: R < RticlearintSpec > ; # [doc = "Register `RTICLEARINT` writer"]
pub type W = crate :: W < RticlearintSpec > ; # [doc = "Field `CLEARINT0` reader - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint0R = crate :: BitReader ; # [doc = "Field `CLEARINT0` writer - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARINT1` reader - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint1R = crate :: BitReader ; # [doc = "Field `CLEARINT1` writer - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARINT2` reader - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint2R = crate :: BitReader ; # [doc = "Field `CLEARINT2` writer - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARINT3` reader - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint3R = crate :: BitReader ; # [doc = "Field `CLEARINT3` writer - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED12` reader - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved12R = crate :: FieldReader ; # [doc = "Field `RESERVED12` writer - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CLEARDMA0` reader - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma0R = crate :: BitReader ; # [doc = "Field `CLEARDMA0` writer - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARDMA1` reader - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma1R = crate :: BitReader ; # [doc = "Field `CLEARDMA1` writer - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARDMA2` reader - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma2R = crate :: BitReader ; # [doc = "Field `CLEARDMA2` writer - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARDMA3` reader - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma3R = crate :: BitReader ; # [doc = "Field `CLEARDMA3` writer - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED13` reader - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved13R = crate :: FieldReader ; # [doc = "Field `RESERVED13` writer - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CLEARTBINT` reader - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type CleartbintR = crate :: BitReader ; # [doc = "Field `CLEARTBINT` writer - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type CleartbintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEAROVL0INT` reader - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl0intR = crate :: BitReader ; # [doc = "Field `CLEAROVL0INT` writer - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl0intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEAROVL1INT` reader - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl1intR = crate :: BitReader ; # [doc = "Field `CLEAROVL1INT` writer - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl1intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED14` reader - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved14R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED14` writer - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint0 (& self) -> Clearint0R { Clearint0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint1 (& self) -> Clearint1R { Clearint1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint2 (& self) -> Clearint2R { Clearint2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint3 (& self) -> Clearint3R { Clearint3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved12 (& self) -> Reserved12R { Reserved12R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma0 (& self) -> Cleardma0R { Cleardma0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma1 (& self) -> Cleardma1R { Cleardma1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma2 (& self) -> Cleardma2R { Cleardma2R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma3 (& self) -> Cleardma3R { Cleardma3R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved13 (& self) -> Reserved13R { Reserved13R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn cleartbint (& self) -> CleartbintR { CleartbintR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearovl0int (& self) -> Clearovl0intR { Clearovl0intR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearovl1int (& self) -> Clearovl1intR { Clearovl1intR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved14 (& self) -> Reserved14R { Reserved14R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint0 (& mut self) -> Clearint0W < RticlearintSpec > { Clearint0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint1 (& mut self) -> Clearint1W < RticlearintSpec > { Clearint1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint2 (& mut self) -> Clearint2W < RticlearintSpec > { Clearint2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint3 (& mut self) -> Clearint3W < RticlearintSpec > { Clearint3W :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved12 (& mut self) -> Reserved12W < RticlearintSpec > { Reserved12W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma0 (& mut self) -> Cleardma0W < RticlearintSpec > { Cleardma0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma1 (& mut self) -> Cleardma1W < RticlearintSpec > { Cleardma1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma2 (& mut self) -> Cleardma2W < RticlearintSpec > { Cleardma2W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma3 (& mut self) -> Cleardma3W < RticlearintSpec > { Cleardma3W :: new (self , 11) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved13 (& mut self) -> Reserved13W < RticlearintSpec > { Reserved13W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn cleartbint (& mut self) -> CleartbintW < RticlearintSpec > { CleartbintW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearovl0int (& mut self) -> Clearovl0intW < RticlearintSpec > { Clearovl0intW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearovl1int (& mut self) -> Clearovl1intW < RticlearintSpec > { Clearovl1intW :: new (self , 18) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved14 (& mut self) -> Reserved14W < RticlearintSpec > { Reserved14W :: new (self , 19) } } # [doc = "Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rticlearint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticlearint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticlearintSpec ; impl crate :: RegisterSpec for RticlearintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticlearint::R`](R) reader structure"]
impl crate :: Readable for RticlearintSpec { } # [doc = "`write(|w| ..)` method takes [`rticlearint::W`](W) writer structure"]
impl crate :: Writable for RticlearintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICLEARINT to value 0"]
impl crate :: Resettable for RticlearintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIINTFLAG (rw) register accessor: Interrupt Flags interrupt pending bits\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiintflag`]
module"]
# [doc (alias = "RTIINTFLAG")]
pub type Rtiintflag = crate :: Reg < rtiintflag :: RtiintflagSpec > ; # [doc = "Interrupt Flags interrupt pending bits"]
pub mod rtiintflag { # [doc = "Register `RTIINTFLAG` reader"]
pub type R = crate :: R < RtiintflagSpec > ; # [doc = "Register `RTIINTFLAG` writer"]
pub type W = crate :: W < RtiintflagSpec > ; # [doc = "Field `INT0` reader - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int0R = crate :: BitReader ; # [doc = "Field `INT0` writer - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INT1` reader - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int1R = crate :: BitReader ; # [doc = "Field `INT1` writer - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INT2` reader - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int2R = crate :: BitReader ; # [doc = "Field `INT2` writer - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INT3` reader - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int3R = crate :: BitReader ; # [doc = "Field `INT3` writer - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED15` reader - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved15R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED15` writer - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `TBINT` reader - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type TbintR = crate :: BitReader ; # [doc = "Field `TBINT` writer - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type TbintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVL0INT` reader - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl0intR = crate :: BitReader ; # [doc = "Field `OVL0INT` writer - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl0intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVL1INT` reader - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl1intR = crate :: BitReader ; # [doc = "Field `OVL1INT` writer - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl1intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED16` reader - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved16R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED16` writer - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int0 (& self) -> Int0R { Int0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int1 (& self) -> Int1R { Int1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int2 (& self) -> Int2R { Int2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int3 (& self) -> Int3R { Int3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:15 - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved15 (& self) -> Reserved15R { Reserved15R :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bit 16 - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn tbint (& self) -> TbintR { TbintR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn ovl0int (& self) -> Ovl0intR { Ovl0intR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn ovl1int (& self) -> Ovl1intR { Ovl1intR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved16 (& self) -> Reserved16R { Reserved16R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int0 (& mut self) -> Int0W < RtiintflagSpec > { Int0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int1 (& mut self) -> Int1W < RtiintflagSpec > { Int1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int2 (& mut self) -> Int2W < RtiintflagSpec > { Int2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int3 (& mut self) -> Int3W < RtiintflagSpec > { Int3W :: new (self , 3) } # [doc = "Bits 4:15 - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved15 (& mut self) -> Reserved15W < RtiintflagSpec > { Reserved15W :: new (self , 4) } # [doc = "Bit 16 - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn tbint (& mut self) -> TbintW < RtiintflagSpec > { TbintW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn ovl0int (& mut self) -> Ovl0intW < RtiintflagSpec > { Ovl0intW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn ovl1int (& mut self) -> Ovl1intW < RtiintflagSpec > { Ovl1intW :: new (self , 18) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved16 (& mut self) -> Reserved16W < RtiintflagSpec > { Reserved16W :: new (self , 19) } } # [doc = "Interrupt Flags interrupt pending bits\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintflag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintflag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiintflagSpec ; impl crate :: RegisterSpec for RtiintflagSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiintflag::R`](R) reader structure"]
impl crate :: Readable for RtiintflagSpec { } # [doc = "`write(|w| ..)` method takes [`rtiintflag::W`](W) writer structure"]
impl crate :: Writable for RtiintflagSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIINTFLAG to value 0"]
impl crate :: Resettable for RtiintflagSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIDWDCTRL (rw) register accessor: Digital Watchdog Control Enables the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtidwdctrl`]
module"]
# [doc (alias = "RTIDWDCTRL")]
pub type Rtidwdctrl = crate :: Reg < rtidwdctrl :: RtidwdctrlSpec > ; # [doc = "Digital Watchdog Control Enables the Digital Watchdog"]
pub mod rtidwdctrl { # [doc = "Register `RTIDWDCTRL` reader"]
pub type R = crate :: R < RtidwdctrlSpec > ; # [doc = "Register `RTIDWDCTRL` writer"]
pub type W = crate :: W < RtidwdctrlSpec > ; # [doc = "Field `DWDCTRL` reader - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
pub type DwdctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `DWDCTRL` writer - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
pub type DwdctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
# [inline (always)]
pub fn dwdctrl (& self) -> DwdctrlR { DwdctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
# [inline (always)]
# [must_use]
pub fn dwdctrl (& mut self) -> DwdctrlW < RtidwdctrlSpec > { DwdctrlW :: new (self , 0) } } # [doc = "Digital Watchdog Control Enables the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtidwdctrlSpec ; impl crate :: RegisterSpec for RtidwdctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtidwdctrl::R`](R) reader structure"]
impl crate :: Readable for RtidwdctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtidwdctrl::W`](W) writer structure"]
impl crate :: Writable for RtidwdctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIDWDCTRL to value 0"]
impl crate :: Resettable for RtidwdctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIDWDPRLD (rw) register accessor: Digital Watchdog Preload sets the experation time of the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdprld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdprld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtidwdprld`]
module"]
# [doc (alias = "RTIDWDPRLD")]
pub type Rtidwdprld = crate :: Reg < rtidwdprld :: RtidwdprldSpec > ; # [doc = "Digital Watchdog Preload sets the experation time of the Digital Watchdog"]
pub mod rtidwdprld { # [doc = "Register `RTIDWDPRLD` reader"]
pub type R = crate :: R < RtidwdprldSpec > ; # [doc = "Register `RTIDWDPRLD` writer"]
pub type W = crate :: W < RtidwdprldSpec > ; # [doc = "Field `DWDPRLD` reader - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
pub type DwdprldR = crate :: FieldReader < u16 > ; # [doc = "Field `DWDPRLD` writer - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
pub type DwdprldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `RESERVED17` reader - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved17R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED17` writer - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
# [inline (always)]
pub fn dwdprld (& self) -> DwdprldR { DwdprldR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31 - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved17 (& self) -> Reserved17R { Reserved17R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
# [inline (always)]
# [must_use]
pub fn dwdprld (& mut self) -> DwdprldW < RtidwdprldSpec > { DwdprldW :: new (self , 0) } # [doc = "Bits 12:31 - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved17 (& mut self) -> Reserved17W < RtidwdprldSpec > { Reserved17W :: new (self , 12) } } # [doc = "Digital Watchdog Preload sets the experation time of the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdprld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdprld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtidwdprldSpec ; impl crate :: RegisterSpec for RtidwdprldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtidwdprld::R`](R) reader structure"]
impl crate :: Readable for RtidwdprldSpec { } # [doc = "`write(|w| ..)` method takes [`rtidwdprld::W`](W) writer structure"]
impl crate :: Writable for RtidwdprldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIDWDPRLD to value 0"]
impl crate :: Resettable for RtidwdprldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWDSTATUS (rw) register accessor: Watchdog Status reflects the status of Analog and Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwdstatus`]
module"]
# [doc (alias = "RTIWDSTATUS")]
pub type Rtiwdstatus = crate :: Reg < rtiwdstatus :: RtiwdstatusSpec > ; # [doc = "Watchdog Status reflects the status of Analog and Digital Watchdog"]
pub mod rtiwdstatus { # [doc = "Register `RTIWDSTATUS` reader"]
pub type R = crate :: R < RtiwdstatusSpec > ; # [doc = "Register `RTIWDSTATUS` writer"]
pub type W = crate :: W < RtiwdstatusSpec > ; # [doc = "Field `AWDST` reader - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type AwdstR = crate :: BitReader ; # [doc = "Field `AWDST` writer - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type AwdstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DWDST` reader - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type DwdstR = crate :: BitReader ; # [doc = "Field `DWDST` writer - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type DwdstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KEYST` reader - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type KeystR = crate :: BitReader ; # [doc = "Field `KEYST` writer - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type KeystW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STARTTIMEVIOL` reader - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type StarttimeviolR = crate :: BitReader ; # [doc = "Field `STARTTIMEVIOL` writer - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type StarttimeviolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENDTIMEVIOL` reader - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type EndtimeviolR = crate :: BitReader ; # [doc = "Field `ENDTIMEVIOL` writer - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type EndtimeviolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DWWD_ST` reader - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
pub type DwwdStR = crate :: BitReader ; # [doc = "Field `DWWD_ST` writer - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
pub type DwwdStW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED18` reader - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved18R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED18` writer - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
pub fn awdst (& self) -> AwdstR { AwdstR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
pub fn dwdst (& self) -> DwdstR { DwdstR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
pub fn keyst (& self) -> KeystR { KeystR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
pub fn starttimeviol (& self) -> StarttimeviolR { StarttimeviolR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
pub fn endtimeviol (& self) -> EndtimeviolR { EndtimeviolR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
# [inline (always)]
pub fn dwwd_st (& self) -> DwwdStR { DwwdStR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved18 (& self) -> Reserved18R { Reserved18R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
# [must_use]
pub fn awdst (& mut self) -> AwdstW < RtiwdstatusSpec > { AwdstW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
# [must_use]
pub fn dwdst (& mut self) -> DwdstW < RtiwdstatusSpec > { DwdstW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
# [must_use]
pub fn keyst (& mut self) -> KeystW < RtiwdstatusSpec > { KeystW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
# [must_use]
pub fn starttimeviol (& mut self) -> StarttimeviolW < RtiwdstatusSpec > { StarttimeviolW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
# [must_use]
pub fn endtimeviol (& mut self) -> EndtimeviolW < RtiwdstatusSpec > { EndtimeviolW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
# [inline (always)]
# [must_use]
pub fn dwwd_st (& mut self) -> DwwdStW < RtiwdstatusSpec > { DwwdStW :: new (self , 5) } # [doc = "Bits 6:31 - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved18 (& mut self) -> Reserved18W < RtiwdstatusSpec > { Reserved18W :: new (self , 6) } } # [doc = "Watchdog Status reflects the status of Analog and Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwdstatusSpec ; impl crate :: RegisterSpec for RtiwdstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwdstatus::R`](R) reader structure"]
impl crate :: Readable for RtiwdstatusSpec { } # [doc = "`write(|w| ..)` method takes [`rtiwdstatus::W`](W) writer structure"]
impl crate :: Writable for RtiwdstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWDSTATUS to value 0"]
impl crate :: Resettable for RtiwdstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWDKEY (rw) register accessor: Watchdog Key correct written key values discharge the external capacitor\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdkey::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdkey::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwdkey`]
module"]
# [doc (alias = "RTIWDKEY")]
pub type Rtiwdkey = crate :: Reg < rtiwdkey :: RtiwdkeySpec > ; # [doc = "Watchdog Key correct written key values discharge the external capacitor"]
pub mod rtiwdkey { # [doc = "Register `RTIWDKEY` reader"]
pub type R = crate :: R < RtiwdkeySpec > ; # [doc = "Register `RTIWDKEY` writer"]
pub type W = crate :: W < RtiwdkeySpec > ; # [doc = "Field `WDKEY` reader - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
pub type WdkeyR = crate :: FieldReader < u16 > ; # [doc = "Field `WDKEY` writer - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
pub type WdkeyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `RESERVED19` reader - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved19R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED19` writer - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved19W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
# [inline (always)]
pub fn wdkey (& self) -> WdkeyR { WdkeyR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved19 (& self) -> Reserved19R { Reserved19R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
# [inline (always)]
# [must_use]
pub fn wdkey (& mut self) -> WdkeyW < RtiwdkeySpec > { WdkeyW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved19 (& mut self) -> Reserved19W < RtiwdkeySpec > { Reserved19W :: new (self , 16) } } # [doc = "Watchdog Key correct written key values discharge the external capacitor\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdkey::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdkey::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwdkeySpec ; impl crate :: RegisterSpec for RtiwdkeySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwdkey::R`](R) reader structure"]
impl crate :: Readable for RtiwdkeySpec { } # [doc = "`write(|w| ..)` method takes [`rtiwdkey::W`](W) writer structure"]
impl crate :: Writable for RtiwdkeySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWDKEY to value 0"]
impl crate :: Resettable for RtiwdkeySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIDWDCNTR (rw) register accessor: Digital Watchdog Down Counter current value of DWD down counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdcntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdcntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtidwdcntr`]
module"]
# [doc (alias = "RTIDWDCNTR")]
pub type Rtidwdcntr = crate :: Reg < rtidwdcntr :: RtidwdcntrSpec > ; # [doc = "Digital Watchdog Down Counter current value of DWD down counter"]
pub mod rtidwdcntr { # [doc = "Register `RTIDWDCNTR` reader"]
pub type R = crate :: R < RtidwdcntrSpec > ; # [doc = "Register `RTIDWDCNTR` writer"]
pub type W = crate :: W < RtidwdcntrSpec > ; # [doc = "Field `DWDCNTR` reader - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
pub type DwdcntrR = crate :: FieldReader < u32 > ; # [doc = "Field `DWDCNTR` writer - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
pub type DwdcntrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; # [doc = "Field `RESERVED20` reader - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved20R = crate :: FieldReader ; # [doc = "Field `RESERVED20` writer - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved20W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:24 - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
# [inline (always)]
pub fn dwdcntr (& self) -> DwdcntrR { DwdcntrR :: new (self . bits & 0x01ff_ffff) } # [doc = "Bits 25:31 - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved20 (& self) -> Reserved20R { Reserved20R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:24 - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
# [inline (always)]
# [must_use]
pub fn dwdcntr (& mut self) -> DwdcntrW < RtidwdcntrSpec > { DwdcntrW :: new (self , 0) } # [doc = "Bits 25:31 - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved20 (& mut self) -> Reserved20W < RtidwdcntrSpec > { Reserved20W :: new (self , 25) } } # [doc = "Digital Watchdog Down Counter current value of DWD down counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdcntr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdcntr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtidwdcntrSpec ; impl crate :: RegisterSpec for RtidwdcntrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtidwdcntr::R`](R) reader structure"]
impl crate :: Readable for RtidwdcntrSpec { } # [doc = "`write(|w| ..)` method takes [`rtidwdcntr::W`](W) writer structure"]
impl crate :: Writable for RtidwdcntrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIDWDCNTR to value 0"]
impl crate :: Resettable for RtidwdcntrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWWDRXNCTRL (rw) register accessor: Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdrxnctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdrxnctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwwdrxnctrl`]
module"]
# [doc (alias = "RTIWWDRXNCTRL")]
pub type Rtiwwdrxnctrl = crate :: Reg < rtiwwdrxnctrl :: RtiwwdrxnctrlSpec > ; # [doc = "Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"]
pub mod rtiwwdrxnctrl { # [doc = "Register `RTIWWDRXNCTRL` reader"]
pub type R = crate :: R < RtiwwdrxnctrlSpec > ; # [doc = "Register `RTIWWDRXNCTRL` writer"]
pub type W = crate :: W < RtiwwdrxnctrlSpec > ; # [doc = "Field `WWDRXN` reader - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
pub type WwdrxnR = crate :: FieldReader ; # [doc = "Field `WWDRXN` writer - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
pub type WwdrxnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED21` reader - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved21R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED21` writer - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved21W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
# [inline (always)]
pub fn wwdrxn (& self) -> WwdrxnR { WwdrxnR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved21 (& self) -> Reserved21R { Reserved21R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
# [inline (always)]
# [must_use]
pub fn wwdrxn (& mut self) -> WwdrxnW < RtiwwdrxnctrlSpec > { WwdrxnW :: new (self , 0) } # [doc = "Bits 4:31 - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved21 (& mut self) -> Reserved21W < RtiwwdrxnctrlSpec > { Reserved21W :: new (self , 4) } } # [doc = "Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdrxnctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdrxnctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwwdrxnctrlSpec ; impl crate :: RegisterSpec for RtiwwdrxnctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwwdrxnctrl::R`](R) reader structure"]
impl crate :: Readable for RtiwwdrxnctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtiwwdrxnctrl::W`](W) writer structure"]
impl crate :: Writable for RtiwwdrxnctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWWDRXNCTRL to value 0"]
impl crate :: Resettable for RtiwwdrxnctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWWDSIZECTRL (rw) register accessor: Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdsizectrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdsizectrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwwdsizectrl`]
module"]
# [doc (alias = "RTIWWDSIZECTRL")]
pub type Rtiwwdsizectrl = crate :: Reg < rtiwwdsizectrl :: RtiwwdsizectrlSpec > ; # [doc = "Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"]
pub mod rtiwwdsizectrl { # [doc = "Register `RTIWWDSIZECTRL` reader"]
pub type R = crate :: R < RtiwwdsizectrlSpec > ; # [doc = "Register `RTIWWDSIZECTRL` writer"]
pub type W = crate :: W < RtiwwdsizectrlSpec > ; # [doc = "Field `WWDSIZE` reader - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
pub type WwdsizeR = crate :: FieldReader < u32 > ; # [doc = "Field `WWDSIZE` writer - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
pub type WwdsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
# [inline (always)]
pub fn wwdsize (& self) -> WwdsizeR { WwdsizeR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
# [inline (always)]
# [must_use]
pub fn wwdsize (& mut self) -> WwdsizeW < RtiwwdsizectrlSpec > { WwdsizeW :: new (self , 0) } } # [doc = "Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdsizectrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdsizectrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwwdsizectrlSpec ; impl crate :: RegisterSpec for RtiwwdsizectrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwwdsizectrl::R`](R) reader structure"]
impl crate :: Readable for RtiwwdsizectrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtiwwdsizectrl::W`](W) writer structure"]
impl crate :: Writable for RtiwwdsizectrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWWDSIZECTRL to value 0"]
impl crate :: Resettable for RtiwwdsizectrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIINTCLRENABLE (rw) register accessor: RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintclrenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintclrenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiintclrenable`]
module"]
# [doc (alias = "RTIINTCLRENABLE")]
pub type Rtiintclrenable = crate :: Reg < rtiintclrenable :: RtiintclrenableSpec > ; # [doc = "RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"]
pub mod rtiintclrenable { # [doc = "Register `RTIINTCLRENABLE` reader"]
pub type R = crate :: R < RtiintclrenableSpec > ; # [doc = "Register `RTIINTCLRENABLE` writer"]
pub type W = crate :: W < RtiintclrenableSpec > ; # [doc = "Field `INTCLRENABLE0` reader - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
pub type Intclrenable0R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE0` writer - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
pub type Intclrenable0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED22` reader - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved22R = crate :: FieldReader ; # [doc = "Field `RESERVED22` writer - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved22W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `INTCLRENABLE1` reader - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
pub type Intclrenable1R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE1` writer - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
pub type Intclrenable1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED23` reader - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved23R = crate :: FieldReader ; # [doc = "Field `RESERVED23` writer - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved23W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `INTCLRENABLE2` reader - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
pub type Intclrenable2R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE2` writer - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
pub type Intclrenable2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED24` reader - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved24R = crate :: FieldReader ; # [doc = "Field `RESERVED24` writer - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved24W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `INTCLRENABLE3` reader - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
pub type Intclrenable3R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE3` writer - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
pub type Intclrenable3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED25` reader - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved25R = crate :: FieldReader ; # [doc = "Field `RESERVED25` writer - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved25W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
# [inline (always)]
pub fn intclrenable0 (& self) -> Intclrenable0R { Intclrenable0R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved22 (& self) -> Reserved22R { Reserved22R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
# [inline (always)]
pub fn intclrenable1 (& self) -> Intclrenable1R { Intclrenable1R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved23 (& self) -> Reserved23R { Reserved23R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
# [inline (always)]
pub fn intclrenable2 (& self) -> Intclrenable2R { Intclrenable2R :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved24 (& self) -> Reserved24R { Reserved24R :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
# [inline (always)]
pub fn intclrenable3 (& self) -> Intclrenable3R { Intclrenable3R :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:31 - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved25 (& self) -> Reserved25R { Reserved25R :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable0 (& mut self) -> Intclrenable0W < RtiintclrenableSpec > { Intclrenable0W :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved22 (& mut self) -> Reserved22W < RtiintclrenableSpec > { Reserved22W :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable1 (& mut self) -> Intclrenable1W < RtiintclrenableSpec > { Intclrenable1W :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved23 (& mut self) -> Reserved23W < RtiintclrenableSpec > { Reserved23W :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable2 (& mut self) -> Intclrenable2W < RtiintclrenableSpec > { Intclrenable2W :: new (self , 16) } # [doc = "Bits 20:23 - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved24 (& mut self) -> Reserved24W < RtiintclrenableSpec > { Reserved24W :: new (self , 20) } # [doc = "Bits 24:27 - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable3 (& mut self) -> Intclrenable3W < RtiintclrenableSpec > { Intclrenable3W :: new (self , 24) } # [doc = "Bits 28:31 - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved25 (& mut self) -> Reserved25W < RtiintclrenableSpec > { Reserved25W :: new (self , 28) } } # [doc = "RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintclrenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintclrenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiintclrenableSpec ; impl crate :: RegisterSpec for RtiintclrenableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiintclrenable::R`](R) reader structure"]
impl crate :: Readable for RtiintclrenableSpec { } # [doc = "`write(|w| ..)` method takes [`rtiintclrenable::W`](W) writer structure"]
impl crate :: Writable for RtiintclrenableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIINTCLRENABLE to value 0"]
impl crate :: Resettable for RtiintclrenableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP0CLR (rw) register accessor: Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp0clr`]
module"]
# [doc (alias = "RTICOMP0CLR")]
pub type Rticomp0clr = crate :: Reg < rticomp0clr :: Rticomp0clrSpec > ; # [doc = "Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"]
pub mod rticomp0clr { # [doc = "Register `RTICOMP0CLR` reader"]
pub type R = crate :: R < Rticomp0clrSpec > ; # [doc = "Register `RTICOMP0CLR` writer"]
pub type W = crate :: W < Rticomp0clrSpec > ; # [doc = "Field `COMP0CLR` reader - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP0CLR` writer - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp0clr (& self) -> Comp0clrR { Comp0clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp0clr (& mut self) -> Comp0clrW < Rticomp0clrSpec > { Comp0clrW :: new (self , 0) } } # [doc = "Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp0clrSpec ; impl crate :: RegisterSpec for Rticomp0clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp0clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp0clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp0clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp0clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP0CLR to value 0"]
impl crate :: Resettable for Rticomp0clrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP1CLR (rw) register accessor: Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp1clr`]
module"]
# [doc (alias = "RTICOMP1CLR")]
pub type Rticomp1clr = crate :: Reg < rticomp1clr :: Rticomp1clrSpec > ; # [doc = "Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"]
pub mod rticomp1clr { # [doc = "Register `RTICOMP1CLR` reader"]
pub type R = crate :: R < Rticomp1clrSpec > ; # [doc = "Register `RTICOMP1CLR` writer"]
pub type W = crate :: W < Rticomp1clrSpec > ; # [doc = "Field `COMP1CLR` reader - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP1CLR` writer - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp1clr (& self) -> Comp1clrR { Comp1clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp1clr (& mut self) -> Comp1clrW < Rticomp1clrSpec > { Comp1clrW :: new (self , 0) } } # [doc = "Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp1clrSpec ; impl crate :: RegisterSpec for Rticomp1clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp1clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp1clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp1clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp1clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP1CLR to value 0"]
impl crate :: Resettable for Rticomp1clrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP2CLR (rw) register accessor: Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp2clr`]
module"]
# [doc (alias = "RTICOMP2CLR")]
pub type Rticomp2clr = crate :: Reg < rticomp2clr :: Rticomp2clrSpec > ; # [doc = "Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"]
pub mod rticomp2clr { # [doc = "Register `RTICOMP2CLR` reader"]
pub type R = crate :: R < Rticomp2clrSpec > ; # [doc = "Register `RTICOMP2CLR` writer"]
pub type W = crate :: W < Rticomp2clrSpec > ; # [doc = "Field `COMP2CLR` reader - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP2CLR` writer - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp2clr (& self) -> Comp2clrR { Comp2clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp2clr (& mut self) -> Comp2clrW < Rticomp2clrSpec > { Comp2clrW :: new (self , 0) } } # [doc = "Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp2clrSpec ; impl crate :: RegisterSpec for Rticomp2clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp2clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp2clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp2clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp2clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP2CLR to value 0"]
impl crate :: Resettable for Rticomp2clrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP3CLR (rw) register accessor: Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp3clr`]
module"]
# [doc (alias = "RTICOMP3CLR")]
pub type Rticomp3clr = crate :: Reg < rticomp3clr :: Rticomp3clrSpec > ; # [doc = "Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"]
pub mod rticomp3clr { # [doc = "Register `RTICOMP3CLR` reader"]
pub type R = crate :: R < Rticomp3clrSpec > ; # [doc = "Register `RTICOMP3CLR` writer"]
pub type W = crate :: W < Rticomp3clrSpec > ; # [doc = "Field `COMP3CLR` reader - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP3CLR` writer - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp3clr (& self) -> Comp3clrR { Comp3clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp3clr (& mut self) -> Comp3clrW < Rticomp3clrSpec > { Comp3clrW :: new (self , 0) } } # [doc = "Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp3clrSpec ; impl crate :: RegisterSpec for Rticomp3clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp3clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp3clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp3clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp3clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP3CLR to value 0"]
impl crate :: Resettable for Rticomp3clrSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_WD"]
pub struct AppWd { _marker : PhantomData < * const () > } unsafe impl Send for AppWd { } impl AppWd { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_wd :: RegisterBlock = 0x56f7_f400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_wd :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppWd { type Target = app_wd :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppWd { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppWd") . finish () } } # [doc = "APP_WD"]
pub mod app_wd { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { rtigctrl : Rtigctrl , rtitbctrl : Rtitbctrl , rticapctrl : Rticapctrl , rticompctrl : Rticompctrl , rtifrc0 : Rtifrc0 , rtiuc0 : Rtiuc0 , rticpuc0 : Rticpuc0 , _reserved7 : [u8 ; 0x04]
, rticafrc0 : Rticafrc0 , rticauc0 : Rticauc0 , _reserved9 : [u8 ; 0x08]
, rtifrc1 : Rtifrc1 , rtiuc1 : Rtiuc1 , rticpuc1 : Rticpuc1 , _reserved12 : [u8 ; 0x04]
, rticafrc1 : Rticafrc1 , rticauc1 : Rticauc1 , _reserved14 : [u8 ; 0x08]
, rticomp0 : Rticomp0 , rtiudcp0 : Rtiudcp0 , rticomp1 : Rticomp1 , rtiudcp1 : Rtiudcp1 , rticomp2 : Rticomp2 , rtiudcp2 : Rtiudcp2 , rticomp3 : Rticomp3 , rtiudcp3 : Rtiudcp3 , rtitblcomp : Rtitblcomp , rtitbhcomp : Rtitbhcomp , _reserved24 : [u8 ; 0x08]
, rtisetint : Rtisetint , rticlearint : Rticlearint , rtiintflag : Rtiintflag , _reserved27 : [u8 ; 0x04]
, rtidwdctrl : Rtidwdctrl , rtidwdprld : Rtidwdprld , rtiwdstatus : Rtiwdstatus , rtiwdkey : Rtiwdkey , rtidwdcntr : Rtidwdcntr , rtiwwdrxnctrl : Rtiwwdrxnctrl , rtiwwdsizectrl : Rtiwwdsizectrl , rtiintclrenable : Rtiintclrenable , rticomp0clr : Rticomp0clr , rticomp1clr : Rticomp1clr , rticomp2clr : Rticomp2clr , rticomp3clr : Rticomp3clr , } impl RegisterBlock { # [doc = "0x00 - Global Control Register starts / stops the counters"]
# [inline (always)]
pub const fn rtigctrl (& self) -> & Rtigctrl { & self . rtigctrl } # [doc = "0x04 - Timebase Control selection which source triggers free running counter 0"]
# [inline (always)]
pub const fn rtitbctrl (& self) -> & Rtitbctrl { & self . rtitbctrl } # [doc = "0x08 - Capture Control controls the capture source for the counters"]
# [inline (always)]
pub const fn rticapctrl (& self) -> & Rticapctrl { & self . rticapctrl } # [doc = "0x0c - Compare Control controls the source for the compare registers"]
# [inline (always)]
pub const fn rticompctrl (& self) -> & Rticompctrl { & self . rticompctrl } # [doc = "0x10 - Free Running Counter 0 current value of free running counter 0"]
# [inline (always)]
pub const fn rtifrc0 (& self) -> & Rtifrc0 { & self . rtifrc0 } # [doc = "0x14 - Up Counter 0 current value of prescale counter 0"]
# [inline (always)]
pub const fn rtiuc0 (& self) -> & Rtiuc0 { & self . rtiuc0 } # [doc = "0x18 - Compare Up Counter 0 compare value compared with prescale counter 0"]
# [inline (always)]
pub const fn rticpuc0 (& self) -> & Rticpuc0 { & self . rticpuc0 } # [doc = "0x20 - Capture Free Running Counter 0 current value of free running counter 0 on external event"]
# [inline (always)]
pub const fn rticafrc0 (& self) -> & Rticafrc0 { & self . rticafrc0 } # [doc = "0x24 - Capture Up Counter 0 current value of prescale counter 0 on external event"]
# [inline (always)]
pub const fn rticauc0 (& self) -> & Rticauc0 { & self . rticauc0 } # [doc = "0x30 - Free Running Counter 1 current value of free running counter 1"]
# [inline (always)]
pub const fn rtifrc1 (& self) -> & Rtifrc1 { & self . rtifrc1 } # [doc = "0x34 - Up Counter 1 current value of prescale counter 1"]
# [inline (always)]
pub const fn rtiuc1 (& self) -> & Rtiuc1 { & self . rtiuc1 } # [doc = "0x38 - Compare Up Counter 1 compare value compared with prescale counter 1"]
# [inline (always)]
pub const fn rticpuc1 (& self) -> & Rticpuc1 { & self . rticpuc1 } # [doc = "0x40 - Capture Free Running Counter 1 current value of free running counter 1 on external event"]
# [inline (always)]
pub const fn rticafrc1 (& self) -> & Rticafrc1 { & self . rticafrc1 } # [doc = "0x44 - Capture Up Counter 1 current value of prescale counter 1 on external event"]
# [inline (always)]
pub const fn rticauc1 (& self) -> & Rticauc1 { & self . rticauc1 } # [doc = "0x50 - Compare 0 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp0 (& self) -> & Rticomp0 { & self . rticomp0 } # [doc = "0x54 - Update Compare 0 value to be added to the compare register 0 value on compare match"]
# [inline (always)]
pub const fn rtiudcp0 (& self) -> & Rtiudcp0 { & self . rtiudcp0 } # [doc = "0x58 - Compare 1 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp1 (& self) -> & Rticomp1 { & self . rticomp1 } # [doc = "0x5c - Update Compare 1 value to be added to the compare register 1 value on compare match"]
# [inline (always)]
pub const fn rtiudcp1 (& self) -> & Rtiudcp1 { & self . rtiudcp1 } # [doc = "0x60 - Compare 2 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp2 (& self) -> & Rticomp2 { & self . rticomp2 } # [doc = "0x64 - Update Compare 2 value to be added to the compare register 2 value on compare match"]
# [inline (always)]
pub const fn rtiudcp2 (& self) -> & Rtiudcp2 { & self . rtiudcp2 } # [doc = "0x68 - Compare 3 compare value to be compared with the counters"]
# [inline (always)]
pub const fn rticomp3 (& self) -> & Rticomp3 { & self . rticomp3 } # [doc = "0x6c - Update Compare 3 value to be added to the compare register 3 value on compare match"]
# [inline (always)]
pub const fn rtiudcp3 (& self) -> & Rtiudcp3 { & self . rtiudcp3 } # [doc = "0x70 - Timebase Low Compare compare value to activate edge detection circuit"]
# [inline (always)]
pub const fn rtitblcomp (& self) -> & Rtitblcomp { & self . rtitblcomp } # [doc = "0x74 - Timebase High Compare compare value to deactivate edge detection circuit"]
# [inline (always)]
pub const fn rtitbhcomp (& self) -> & Rtitbhcomp { & self . rtitbhcomp } # [doc = "0x80 - Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
# [inline (always)]
pub const fn rtisetint (& self) -> & Rtisetint { & self . rtisetint } # [doc = "0x84 - Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
# [inline (always)]
pub const fn rticlearint (& self) -> & Rticlearint { & self . rticlearint } # [doc = "0x88 - Interrupt Flags interrupt pending bits"]
# [inline (always)]
pub const fn rtiintflag (& self) -> & Rtiintflag { & self . rtiintflag } # [doc = "0x90 - Digital Watchdog Control Enables the Digital Watchdog"]
# [inline (always)]
pub const fn rtidwdctrl (& self) -> & Rtidwdctrl { & self . rtidwdctrl } # [doc = "0x94 - Digital Watchdog Preload sets the experation time of the Digital Watchdog"]
# [inline (always)]
pub const fn rtidwdprld (& self) -> & Rtidwdprld { & self . rtidwdprld } # [doc = "0x98 - Watchdog Status reflects the status of Analog and Digital Watchdog"]
# [inline (always)]
pub const fn rtiwdstatus (& self) -> & Rtiwdstatus { & self . rtiwdstatus } # [doc = "0x9c - Watchdog Key correct written key values discharge the external capacitor"]
# [inline (always)]
pub const fn rtiwdkey (& self) -> & Rtiwdkey { & self . rtiwdkey } # [doc = "0xa0 - Digital Watchdog Down Counter current value of DWD down counter"]
# [inline (always)]
pub const fn rtidwdcntr (& self) -> & Rtidwdcntr { & self . rtidwdcntr } # [doc = "0xa4 - Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"]
# [inline (always)]
pub const fn rtiwwdrxnctrl (& self) -> & Rtiwwdrxnctrl { & self . rtiwwdrxnctrl } # [doc = "0xa8 - Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"]
# [inline (always)]
pub const fn rtiwwdsizectrl (& self) -> & Rtiwwdsizectrl { & self . rtiwwdsizectrl } # [doc = "0xac - RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"]
# [inline (always)]
pub const fn rtiintclrenable (& self) -> & Rtiintclrenable { & self . rtiintclrenable } # [doc = "0xb0 - Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"]
# [inline (always)]
pub const fn rticomp0clr (& self) -> & Rticomp0clr { & self . rticomp0clr } # [doc = "0xb4 - Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"]
# [inline (always)]
pub const fn rticomp1clr (& self) -> & Rticomp1clr { & self . rticomp1clr } # [doc = "0xb8 - Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"]
# [inline (always)]
pub const fn rticomp2clr (& self) -> & Rticomp2clr { & self . rticomp2clr } # [doc = "0xbc - Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"]
# [inline (always)]
pub const fn rticomp3clr (& self) -> & Rticomp3clr { & self . rticomp3clr } } # [doc = "RTIGCTRL (rw) register accessor: Global Control Register starts / stops the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rtigctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtigctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtigctrl`]
module"]
# [doc (alias = "RTIGCTRL")]
pub type Rtigctrl = crate :: Reg < rtigctrl :: RtigctrlSpec > ; # [doc = "Global Control Register starts / stops the counters"]
pub mod rtigctrl { # [doc = "Register `RTIGCTRL` reader"]
pub type R = crate :: R < RtigctrlSpec > ; # [doc = "Register `RTIGCTRL` writer"]
pub type W = crate :: W < RtigctrlSpec > ; # [doc = "Field `CNT0EN` reader - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
pub type Cnt0enR = crate :: BitReader ; # [doc = "Field `CNT0EN` writer - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
pub type Cnt0enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CNT1EN` reader - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
pub type Cnt1enR = crate :: BitReader ; # [doc = "Field `CNT1EN` writer - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
pub type Cnt1enW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED1` writer - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `COS` reader - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
pub type CosR = crate :: BitReader ; # [doc = "Field `COS` writer - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
pub type CosW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NTUSEL` reader - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
pub type NtuselR = crate :: FieldReader ; # [doc = "Field `NTUSEL` writer - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
pub type NtuselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED2` reader - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED2` writer - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
# [inline (always)]
pub fn cnt0en (& self) -> Cnt0enR { Cnt0enR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
# [inline (always)]
pub fn cnt1en (& self) -> Cnt1enR { Cnt1enR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:14 - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x1fff) as u16) } # [doc = "Bit 15 - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
# [inline (always)]
pub fn cos (& self) -> CosR { CosR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
# [inline (always)]
pub fn ntusel (& self) -> NtuselR { NtuselR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:31 - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical)."]
# [inline (always)]
# [must_use]
pub fn cnt0en (& mut self) -> Cnt0enW < RtigctrlSpec > { Cnt0enW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical)."]
# [inline (always)]
# [must_use]
pub fn cnt1en (& mut self) -> Cnt1enW < RtigctrlSpec > { Cnt1enW :: new (self , 1) } # [doc = "Bits 2:14 - 14:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < RtigctrlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 15 - 15:15\\]
COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode"]
# [inline (always)]
# [must_use]
pub fn cos (& mut self) -> CosW < RtigctrlSpec > { CosW :: new (self , 15) } # [doc = "Bits 16:19 - 19:16\\]
NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ΓÇÿ0ΓÇÖ"]
# [inline (always)]
# [must_use]
pub fn ntusel (& mut self) -> NtuselW < RtigctrlSpec > { NtuselW :: new (self , 16) } # [doc = "Bits 20:31 - 31:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < RtigctrlSpec > { Reserved2W :: new (self , 20) } } # [doc = "Global Control Register starts / stops the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rtigctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtigctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtigctrlSpec ; impl crate :: RegisterSpec for RtigctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtigctrl::R`](R) reader structure"]
impl crate :: Readable for RtigctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtigctrl::W`](W) writer structure"]
impl crate :: Writable for RtigctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIGCTRL to value 0"]
impl crate :: Resettable for RtigctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTITBCTRL (rw) register accessor: Timebase Control selection which source triggers free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtitbctrl`]
module"]
# [doc (alias = "RTITBCTRL")]
pub type Rtitbctrl = crate :: Reg < rtitbctrl :: RtitbctrlSpec > ; # [doc = "Timebase Control selection which source triggers free running counter 0"]
pub mod rtitbctrl { # [doc = "Register `RTITBCTRL` reader"]
pub type R = crate :: R < RtitbctrlSpec > ; # [doc = "Register `RTITBCTRL` writer"]
pub type W = crate :: W < RtitbctrlSpec > ; # [doc = "Field `TBEXT` reader - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
pub type TbextR = crate :: BitReader ; # [doc = "Field `TBEXT` writer - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
pub type TbextW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INC` reader - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
pub type IncR = crate :: BitReader ; # [doc = "Field `INC` writer - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
pub type IncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 31:2\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED3` writer - 31:2\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
# [inline (always)]
pub fn tbext (& self) -> TbextR { TbextR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
# [inline (always)]
pub fn inc (& self) -> IncR { IncR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme"]
# [inline (always)]
# [must_use]
pub fn tbext (& mut self) -> TbextW < RtitbctrlSpec > { TbextW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock"]
# [inline (always)]
# [must_use]
pub fn inc (& mut self) -> IncW < RtitbctrlSpec > { IncW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < RtitbctrlSpec > { Reserved3W :: new (self , 2) } } # [doc = "Timebase Control selection which source triggers free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtitbctrlSpec ; impl crate :: RegisterSpec for RtitbctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtitbctrl::R`](R) reader structure"]
impl crate :: Readable for RtitbctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtitbctrl::W`](W) writer structure"]
impl crate :: Writable for RtitbctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTITBCTRL to value 0"]
impl crate :: Resettable for RtitbctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAPCTRL (rw) register accessor: Capture Control controls the capture source for the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticapctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticapctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticapctrl`]
module"]
# [doc (alias = "RTICAPCTRL")]
pub type Rticapctrl = crate :: Reg < rticapctrl :: RticapctrlSpec > ; # [doc = "Capture Control controls the capture source for the counters"]
pub mod rticapctrl { # [doc = "Register `RTICAPCTRL` reader"]
pub type R = crate :: R < RticapctrlSpec > ; # [doc = "Register `RTICAPCTRL` writer"]
pub type W = crate :: W < RticapctrlSpec > ; # [doc = "Field `CAPCNTR0` reader - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
pub type Capcntr0R = crate :: BitReader ; # [doc = "Field `CAPCNTR0` writer - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
pub type Capcntr0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAPCNTR1` reader - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
pub type Capcntr1R = crate :: BitReader ; # [doc = "Field `CAPCNTR1` writer - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
pub type Capcntr1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved4R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED4` writer - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
# [inline (always)]
pub fn capcntr0 (& self) -> Capcntr0R { Capcntr0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
# [inline (always)]
pub fn capcntr1 (& self) -> Capcntr1R { Capcntr1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant"]
# [inline (always)]
# [must_use]
pub fn capcntr0 (& mut self) -> Capcntr0W < RticapctrlSpec > { Capcntr0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1"]
# [inline (always)]
# [must_use]
pub fn capcntr1 (& mut self) -> Capcntr1W < RticapctrlSpec > { Capcntr1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < RticapctrlSpec > { Reserved4W :: new (self , 2) } } # [doc = "Capture Control controls the capture source for the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticapctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticapctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticapctrlSpec ; impl crate :: RegisterSpec for RticapctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticapctrl::R`](R) reader structure"]
impl crate :: Readable for RticapctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rticapctrl::W`](W) writer structure"]
impl crate :: Writable for RticapctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAPCTRL to value 0"]
impl crate :: Resettable for RticapctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMPCTRL (rw) register accessor: Compare Control controls the source for the compare registers\n\nYou can [`read`](crate::Reg::read) this register and get [`rticompctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticompctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticompctrl`]
module"]
# [doc (alias = "RTICOMPCTRL")]
pub type Rticompctrl = crate :: Reg < rticompctrl :: RticompctrlSpec > ; # [doc = "Compare Control controls the source for the compare registers"]
pub mod rticompctrl { # [doc = "Register `RTICOMPCTRL` reader"]
pub type R = crate :: R < RticompctrlSpec > ; # [doc = "Register `RTICOMPCTRL` writer"]
pub type W = crate :: W < RticompctrlSpec > ; # [doc = "Field `COMP0SEL` reader - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp0selR = crate :: BitReader ; # [doc = "Field `COMP0SEL` writer - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp0selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED5` reader - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `RESERVED5` writer - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMP1SEL` reader - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp1selR = crate :: BitReader ; # [doc = "Field `COMP1SEL` writer - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp1selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED6` reader - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved6R = crate :: FieldReader ; # [doc = "Field `RESERVED6` writer - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMP2SEL` reader - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp2selR = crate :: BitReader ; # [doc = "Field `COMP2SEL` writer - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp2selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED7` reader - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved7R = crate :: FieldReader ; # [doc = "Field `RESERVED7` writer - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `COMP3SEL` reader - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp3selR = crate :: BitReader ; # [doc = "Field `COMP3SEL` writer - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
pub type Comp3selW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED8` reader - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved8R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED8` writer - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 19 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp0sel (& self) -> Comp0selR { Comp0selR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:3 - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 1) & 7) as u8) } # [doc = "Bit 4 - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp1sel (& self) -> Comp1selR { Comp1selR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:7 - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved6 (& self) -> Reserved6R { Reserved6R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp2sel (& self) -> Comp2selR { Comp2selR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:11 - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved7 (& self) -> Reserved7R { Reserved7R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bit 12 - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
pub fn comp3sel (& self) -> Comp3selR { Comp3selR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:31 - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved8 (& self) -> Reserved8R { Reserved8R :: new ((self . bits >> 13) & 0x0007_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp0sel (& mut self) -> Comp0selW < RticompctrlSpec > { Comp0selW :: new (self , 0) } # [doc = "Bits 1:3 - 3:1\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < RticompctrlSpec > { Reserved5W :: new (self , 1) } # [doc = "Bit 4 - 4:4\\]
COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp1sel (& mut self) -> Comp1selW < RticompctrlSpec > { Comp1selW :: new (self , 4) } # [doc = "Bits 5:7 - 7:5\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved6 (& mut self) -> Reserved6W < RticompctrlSpec > { Reserved6W :: new (self , 5) } # [doc = "Bit 8 - 8:8\\]
COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp2sel (& mut self) -> Comp2selW < RticompctrlSpec > { Comp2selW :: new (self , 8) } # [doc = "Bits 9:11 - 11:9\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved7 (& mut self) -> Reserved7W < RticompctrlSpec > { Reserved7W :: new (self , 9) } # [doc = "Bit 12 - 12:12\\]
COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1"]
# [inline (always)]
# [must_use]
pub fn comp3sel (& mut self) -> Comp3selW < RticompctrlSpec > { Comp3selW :: new (self , 12) } # [doc = "Bits 13:31 - 31:13\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved8 (& mut self) -> Reserved8W < RticompctrlSpec > { Reserved8W :: new (self , 13) } } # [doc = "Compare Control controls the source for the compare registers\n\nYou can [`read`](crate::Reg::read) this register and get [`rticompctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticompctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticompctrlSpec ; impl crate :: RegisterSpec for RticompctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticompctrl::R`](R) reader structure"]
impl crate :: Readable for RticompctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rticompctrl::W`](W) writer structure"]
impl crate :: Writable for RticompctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMPCTRL to value 0"]
impl crate :: Resettable for RticompctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIFRC0 (rw) register accessor: Free Running Counter 0 current value of free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtifrc0`]
module"]
# [doc (alias = "RTIFRC0")]
pub type Rtifrc0 = crate :: Reg < rtifrc0 :: Rtifrc0Spec > ; # [doc = "Free Running Counter 0 current value of free running counter 0"]
pub mod rtifrc0 { # [doc = "Register `RTIFRC0` reader"]
pub type R = crate :: R < Rtifrc0Spec > ; # [doc = "Register `RTIFRC0` writer"]
pub type W = crate :: W < Rtifrc0Spec > ; # [doc = "Field `FRC0` reader - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
pub type Frc0R = crate :: FieldReader < u32 > ; # [doc = "Field `FRC0` writer - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
pub type Frc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
# [inline (always)]
pub fn frc0 (& self) -> Frc0R { Frc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0."]
# [inline (always)]
# [must_use]
pub fn frc0 (& mut self) -> Frc0W < Rtifrc0Spec > { Frc0W :: new (self , 0) } } # [doc = "Free Running Counter 0 current value of free running counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtifrc0Spec ; impl crate :: RegisterSpec for Rtifrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtifrc0::R`](R) reader structure"]
impl crate :: Readable for Rtifrc0Spec { } # [doc = "`write(|w| ..)` method takes [`rtifrc0::W`](W) writer structure"]
impl crate :: Writable for Rtifrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIFRC0 to value 0"]
impl crate :: Resettable for Rtifrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUC0 (rw) register accessor: Up Counter 0 current value of prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiuc0`]
module"]
# [doc (alias = "RTIUC0")]
pub type Rtiuc0 = crate :: Reg < rtiuc0 :: Rtiuc0Spec > ; # [doc = "Up Counter 0 current value of prescale counter 0"]
pub mod rtiuc0 { # [doc = "Register `RTIUC0` reader"]
pub type R = crate :: R < Rtiuc0Spec > ; # [doc = "Register `RTIUC0` writer"]
pub type W = crate :: W < Rtiuc0Spec > ; # [doc = "Field `UC0` reader - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
pub type Uc0R = crate :: FieldReader < u32 > ; # [doc = "Field `UC0` writer - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
pub type Uc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
# [inline (always)]
pub fn uc0 (& self) -> Uc0R { Uc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows."]
# [inline (always)]
# [must_use]
pub fn uc0 (& mut self) -> Uc0W < Rtiuc0Spec > { Uc0W :: new (self , 0) } } # [doc = "Up Counter 0 current value of prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiuc0Spec ; impl crate :: RegisterSpec for Rtiuc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiuc0::R`](R) reader structure"]
impl crate :: Readable for Rtiuc0Spec { } # [doc = "`write(|w| ..)` method takes [`rtiuc0::W`](W) writer structure"]
impl crate :: Writable for Rtiuc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUC0 to value 0"]
impl crate :: Resettable for Rtiuc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICPUC0 (rw) register accessor: Compare Up Counter 0 compare value compared with prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticpuc0`]
module"]
# [doc (alias = "RTICPUC0")]
pub type Rticpuc0 = crate :: Reg < rticpuc0 :: Rticpuc0Spec > ; # [doc = "Compare Up Counter 0 compare value compared with prescale counter 0"]
pub mod rticpuc0 { # [doc = "Register `RTICPUC0` reader"]
pub type R = crate :: R < Rticpuc0Spec > ; # [doc = "Register `RTICPUC0` writer"]
pub type W = crate :: W < Rticpuc0Spec > ; # [doc = "Field `CPUC0` reader - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc0R = crate :: FieldReader < u32 > ; # [doc = "Field `CPUC0` writer - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
pub fn cpuc0 (& self) -> Cpuc0R { Cpuc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 Γëá 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
# [must_use]
pub fn cpuc0 (& mut self) -> Cpuc0W < Rticpuc0Spec > { Cpuc0W :: new (self , 0) } } # [doc = "Compare Up Counter 0 compare value compared with prescale counter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticpuc0Spec ; impl crate :: RegisterSpec for Rticpuc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticpuc0::R`](R) reader structure"]
impl crate :: Readable for Rticpuc0Spec { } # [doc = "`write(|w| ..)` method takes [`rticpuc0::W`](W) writer structure"]
impl crate :: Writable for Rticpuc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICPUC0 to value 0"]
impl crate :: Resettable for Rticpuc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAFRC0 (rw) register accessor: Capture Free Running Counter 0 current value of free running counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticafrc0`]
module"]
# [doc (alias = "RTICAFRC0")]
pub type Rticafrc0 = crate :: Reg < rticafrc0 :: Rticafrc0Spec > ; # [doc = "Capture Free Running Counter 0 current value of free running counter 0 on external event"]
pub mod rticafrc0 { # [doc = "Register `RTICAFRC0` reader"]
pub type R = crate :: R < Rticafrc0Spec > ; # [doc = "Register `RTICAFRC0` writer"]
pub type W = crate :: W < Rticafrc0Spec > ; # [doc = "Field `CAFRC0` reader - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
pub type Cafrc0R = crate :: FieldReader < u32 > ; # [doc = "Field `CAFRC0` writer - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
pub type Cafrc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
# [inline (always)]
pub fn cafrc0 (& self) -> Cafrc0R { Cafrc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cafrc0 (& mut self) -> Cafrc0W < Rticafrc0Spec > { Cafrc0W :: new (self , 0) } } # [doc = "Capture Free Running Counter 0 current value of free running counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticafrc0Spec ; impl crate :: RegisterSpec for Rticafrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticafrc0::R`](R) reader structure"]
impl crate :: Readable for Rticafrc0Spec { } # [doc = "`write(|w| ..)` method takes [`rticafrc0::W`](W) writer structure"]
impl crate :: Writable for Rticafrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAFRC0 to value 0"]
impl crate :: Resettable for Rticafrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAUC0 (rw) register accessor: Capture Up Counter 0 current value of prescale counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticauc0`]
module"]
# [doc (alias = "RTICAUC0")]
pub type Rticauc0 = crate :: Reg < rticauc0 :: Rticauc0Spec > ; # [doc = "Capture Up Counter 0 current value of prescale counter 0 on external event"]
pub mod rticauc0 { # [doc = "Register `RTICAUC0` reader"]
pub type R = crate :: R < Rticauc0Spec > ; # [doc = "Register `RTICAUC0` writer"]
pub type W = crate :: W < Rticauc0Spec > ; # [doc = "Field `CAUC0` reader - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
pub type Cauc0R = crate :: FieldReader < u32 > ; # [doc = "Field `CAUC0` writer - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
pub type Cauc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
# [inline (always)]
pub fn cauc0 (& self) -> Cauc0R { Cauc0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cauc0 (& mut self) -> Cauc0W < Rticauc0Spec > { Cauc0W :: new (self , 0) } } # [doc = "Capture Up Counter 0 current value of prescale counter 0 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticauc0Spec ; impl crate :: RegisterSpec for Rticauc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticauc0::R`](R) reader structure"]
impl crate :: Readable for Rticauc0Spec { } # [doc = "`write(|w| ..)` method takes [`rticauc0::W`](W) writer structure"]
impl crate :: Writable for Rticauc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAUC0 to value 0"]
impl crate :: Resettable for Rticauc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIFRC1 (rw) register accessor: Free Running Counter 1 current value of free running counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtifrc1`]
module"]
# [doc (alias = "RTIFRC1")]
pub type Rtifrc1 = crate :: Reg < rtifrc1 :: Rtifrc1Spec > ; # [doc = "Free Running Counter 1 current value of free running counter 1"]
pub mod rtifrc1 { # [doc = "Register `RTIFRC1` reader"]
pub type R = crate :: R < Rtifrc1Spec > ; # [doc = "Register `RTIFRC1` writer"]
pub type W = crate :: W < Rtifrc1Spec > ; # [doc = "Field `FRC1` reader - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
pub type Frc1R = crate :: FieldReader < u32 > ; # [doc = "Field `FRC1` writer - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
pub type Frc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
# [inline (always)]
pub fn frc1 (& self) -> Frc1R { Frc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1."]
# [inline (always)]
# [must_use]
pub fn frc1 (& mut self) -> Frc1W < Rtifrc1Spec > { Frc1W :: new (self , 0) } } # [doc = "Free Running Counter 1 current value of free running counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtifrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtifrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtifrc1Spec ; impl crate :: RegisterSpec for Rtifrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtifrc1::R`](R) reader structure"]
impl crate :: Readable for Rtifrc1Spec { } # [doc = "`write(|w| ..)` method takes [`rtifrc1::W`](W) writer structure"]
impl crate :: Writable for Rtifrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIFRC1 to value 0"]
impl crate :: Resettable for Rtifrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUC1 (rw) register accessor: Up Counter 1 current value of prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiuc1`]
module"]
# [doc (alias = "RTIUC1")]
pub type Rtiuc1 = crate :: Reg < rtiuc1 :: Rtiuc1Spec > ; # [doc = "Up Counter 1 current value of prescale counter 1"]
pub mod rtiuc1 { # [doc = "Register `RTIUC1` reader"]
pub type R = crate :: R < Rtiuc1Spec > ; # [doc = "Register `RTIUC1` writer"]
pub type W = crate :: W < Rtiuc1Spec > ; # [doc = "Field `UC1` reader - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
pub type Uc1R = crate :: FieldReader < u32 > ; # [doc = "Field `UC1` writer - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
pub type Uc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
# [inline (always)]
pub fn uc1 (& self) -> Uc1R { Uc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows."]
# [inline (always)]
# [must_use]
pub fn uc1 (& mut self) -> Uc1W < Rtiuc1Spec > { Uc1W :: new (self , 0) } } # [doc = "Up Counter 1 current value of prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiuc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiuc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiuc1Spec ; impl crate :: RegisterSpec for Rtiuc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiuc1::R`](R) reader structure"]
impl crate :: Readable for Rtiuc1Spec { } # [doc = "`write(|w| ..)` method takes [`rtiuc1::W`](W) writer structure"]
impl crate :: Writable for Rtiuc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUC1 to value 0"]
impl crate :: Resettable for Rtiuc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICPUC1 (rw) register accessor: Compare Up Counter 1 compare value compared with prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticpuc1`]
module"]
# [doc (alias = "RTICPUC1")]
pub type Rticpuc1 = crate :: Reg < rticpuc1 :: Rticpuc1Spec > ; # [doc = "Compare Up Counter 1 compare value compared with prescale counter 1"]
pub mod rticpuc1 { # [doc = "Register `RTICPUC1` reader"]
pub type R = crate :: R < Rticpuc1Spec > ; # [doc = "Register `RTICPUC1` writer"]
pub type W = crate :: W < Rticpuc1Spec > ; # [doc = "Field `CPUC1` reader - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc1R = crate :: FieldReader < u32 > ; # [doc = "Field `CPUC1` writer - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
pub type Cpuc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
pub fn cpuc1 (& self) -> Cpuc1R { Cpuc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 Γëá 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"]
# [inline (always)]
# [must_use]
pub fn cpuc1 (& mut self) -> Cpuc1W < Rticpuc1Spec > { Cpuc1W :: new (self , 0) } } # [doc = "Compare Up Counter 1 compare value compared with prescale counter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rticpuc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticpuc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticpuc1Spec ; impl crate :: RegisterSpec for Rticpuc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticpuc1::R`](R) reader structure"]
impl crate :: Readable for Rticpuc1Spec { } # [doc = "`write(|w| ..)` method takes [`rticpuc1::W`](W) writer structure"]
impl crate :: Writable for Rticpuc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICPUC1 to value 0"]
impl crate :: Resettable for Rticpuc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAFRC1 (rw) register accessor: Capture Free Running Counter 1 current value of free running counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticafrc1`]
module"]
# [doc (alias = "RTICAFRC1")]
pub type Rticafrc1 = crate :: Reg < rticafrc1 :: Rticafrc1Spec > ; # [doc = "Capture Free Running Counter 1 current value of free running counter 1 on external event"]
pub mod rticafrc1 { # [doc = "Register `RTICAFRC1` reader"]
pub type R = crate :: R < Rticafrc1Spec > ; # [doc = "Register `RTICAFRC1` writer"]
pub type W = crate :: W < Rticafrc1Spec > ; # [doc = "Field `CAFRC1` reader - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
pub type Cafrc1R = crate :: FieldReader < u32 > ; # [doc = "Field `CAFRC1` writer - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
pub type Cafrc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
# [inline (always)]
pub fn cafrc1 (& self) -> Cafrc1R { Cafrc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cafrc1 (& mut self) -> Cafrc1W < Rticafrc1Spec > { Cafrc1W :: new (self , 0) } } # [doc = "Capture Free Running Counter 1 current value of free running counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticafrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticafrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticafrc1Spec ; impl crate :: RegisterSpec for Rticafrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticafrc1::R`](R) reader structure"]
impl crate :: Readable for Rticafrc1Spec { } # [doc = "`write(|w| ..)` method takes [`rticafrc1::W`](W) writer structure"]
impl crate :: Writable for Rticafrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAFRC1 to value 0"]
impl crate :: Resettable for Rticafrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICAUC1 (rw) register accessor: Capture Up Counter 1 current value of prescale counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticauc1`]
module"]
# [doc (alias = "RTICAUC1")]
pub type Rticauc1 = crate :: Reg < rticauc1 :: Rticauc1Spec > ; # [doc = "Capture Up Counter 1 current value of prescale counter 1 on external event"]
pub mod rticauc1 { # [doc = "Register `RTICAUC1` reader"]
pub type R = crate :: R < Rticauc1Spec > ; # [doc = "Register `RTICAUC1` writer"]
pub type W = crate :: W < Rticauc1Spec > ; # [doc = "Field `CAUC1` reader - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
pub type Cauc1R = crate :: FieldReader < u32 > ; # [doc = "Field `CAUC1` writer - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
pub type Cauc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
# [inline (always)]
pub fn cauc1 (& self) -> Cauc1R { Cauc1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event"]
# [inline (always)]
# [must_use]
pub fn cauc1 (& mut self) -> Cauc1W < Rticauc1Spec > { Cauc1W :: new (self , 0) } } # [doc = "Capture Up Counter 1 current value of prescale counter 1 on external event\n\nYou can [`read`](crate::Reg::read) this register and get [`rticauc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticauc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticauc1Spec ; impl crate :: RegisterSpec for Rticauc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticauc1::R`](R) reader structure"]
impl crate :: Readable for Rticauc1Spec { } # [doc = "`write(|w| ..)` method takes [`rticauc1::W`](W) writer structure"]
impl crate :: Writable for Rticauc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICAUC1 to value 0"]
impl crate :: Resettable for Rticauc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP0 (rw) register accessor: Compare 0 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp0`]
module"]
# [doc (alias = "RTICOMP0")]
pub type Rticomp0 = crate :: Reg < rticomp0 :: Rticomp0Spec > ; # [doc = "Compare 0 compare value to be compared with the counters"]
pub mod rticomp0 { # [doc = "Register `RTICOMP0` reader"]
pub type R = crate :: R < Rticomp0Spec > ; # [doc = "Register `RTICOMP0` writer"]
pub type W = crate :: W < Rticomp0Spec > ; # [doc = "Field `COMP0` reader - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP0` writer - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp0 (& self) -> Comp0R { Comp0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp0 (& mut self) -> Comp0W < Rticomp0Spec > { Comp0W :: new (self , 0) } } # [doc = "Compare 0 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp0Spec ; impl crate :: RegisterSpec for Rticomp0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp0::R`](R) reader structure"]
impl crate :: Readable for Rticomp0Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp0::W`](W) writer structure"]
impl crate :: Writable for Rticomp0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP0 to value 0"]
impl crate :: Resettable for Rticomp0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP0 (rw) register accessor: Update Compare 0 value to be added to the compare register 0 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp0`]
module"]
# [doc (alias = "RTIUDCP0")]
pub type Rtiudcp0 = crate :: Reg < rtiudcp0 :: Rtiudcp0Spec > ; # [doc = "Update Compare 0 value to be added to the compare register 0 value on compare match"]
pub mod rtiudcp0 { # [doc = "Register `RTIUDCP0` reader"]
pub type R = crate :: R < Rtiudcp0Spec > ; # [doc = "Register `RTIUDCP0` writer"]
pub type W = crate :: W < Rtiudcp0Spec > ; # [doc = "Field `UDCP0` reader - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp0R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP0` writer - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp0 (& self) -> Udcp0R { Udcp0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp0 (& mut self) -> Udcp0W < Rtiudcp0Spec > { Udcp0W :: new (self , 0) } } # [doc = "Update Compare 0 value to be added to the compare register 0 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp0Spec ; impl crate :: RegisterSpec for Rtiudcp0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp0::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp0Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp0::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP0 to value 0"]
impl crate :: Resettable for Rtiudcp0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP1 (rw) register accessor: Compare 1 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp1`]
module"]
# [doc (alias = "RTICOMP1")]
pub type Rticomp1 = crate :: Reg < rticomp1 :: Rticomp1Spec > ; # [doc = "Compare 1 compare value to be compared with the counters"]
pub mod rticomp1 { # [doc = "Register `RTICOMP1` reader"]
pub type R = crate :: R < Rticomp1Spec > ; # [doc = "Register `RTICOMP1` writer"]
pub type W = crate :: W < Rticomp1Spec > ; # [doc = "Field `COMP1` reader - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP1` writer - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp1 (& self) -> Comp1R { Comp1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp1 (& mut self) -> Comp1W < Rticomp1Spec > { Comp1W :: new (self , 0) } } # [doc = "Compare 1 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp1Spec ; impl crate :: RegisterSpec for Rticomp1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp1::R`](R) reader structure"]
impl crate :: Readable for Rticomp1Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp1::W`](W) writer structure"]
impl crate :: Writable for Rticomp1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP1 to value 0"]
impl crate :: Resettable for Rticomp1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP1 (rw) register accessor: Update Compare 1 value to be added to the compare register 1 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp1`]
module"]
# [doc (alias = "RTIUDCP1")]
pub type Rtiudcp1 = crate :: Reg < rtiudcp1 :: Rtiudcp1Spec > ; # [doc = "Update Compare 1 value to be added to the compare register 1 value on compare match"]
pub mod rtiudcp1 { # [doc = "Register `RTIUDCP1` reader"]
pub type R = crate :: R < Rtiudcp1Spec > ; # [doc = "Register `RTIUDCP1` writer"]
pub type W = crate :: W < Rtiudcp1Spec > ; # [doc = "Field `UDCP1` reader - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp1R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP1` writer - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp1 (& self) -> Udcp1R { Udcp1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp1 (& mut self) -> Udcp1W < Rtiudcp1Spec > { Udcp1W :: new (self , 0) } } # [doc = "Update Compare 1 value to be added to the compare register 1 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp1Spec ; impl crate :: RegisterSpec for Rtiudcp1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp1::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp1Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp1::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP1 to value 0"]
impl crate :: Resettable for Rtiudcp1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP2 (rw) register accessor: Compare 2 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp2`]
module"]
# [doc (alias = "RTICOMP2")]
pub type Rticomp2 = crate :: Reg < rticomp2 :: Rticomp2Spec > ; # [doc = "Compare 2 compare value to be compared with the counters"]
pub mod rticomp2 { # [doc = "Register `RTICOMP2` reader"]
pub type R = crate :: R < Rticomp2Spec > ; # [doc = "Register `RTICOMP2` writer"]
pub type W = crate :: W < Rticomp2Spec > ; # [doc = "Field `COMP2` reader - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP2` writer - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp2 (& self) -> Comp2R { Comp2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp2 (& mut self) -> Comp2W < Rticomp2Spec > { Comp2W :: new (self , 0) } } # [doc = "Compare 2 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp2Spec ; impl crate :: RegisterSpec for Rticomp2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp2::R`](R) reader structure"]
impl crate :: Readable for Rticomp2Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp2::W`](W) writer structure"]
impl crate :: Writable for Rticomp2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP2 to value 0"]
impl crate :: Resettable for Rticomp2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP2 (rw) register accessor: Update Compare 2 value to be added to the compare register 2 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp2`]
module"]
# [doc (alias = "RTIUDCP2")]
pub type Rtiudcp2 = crate :: Reg < rtiudcp2 :: Rtiudcp2Spec > ; # [doc = "Update Compare 2 value to be added to the compare register 2 value on compare match"]
pub mod rtiudcp2 { # [doc = "Register `RTIUDCP2` reader"]
pub type R = crate :: R < Rtiudcp2Spec > ; # [doc = "Register `RTIUDCP2` writer"]
pub type W = crate :: W < Rtiudcp2Spec > ; # [doc = "Field `UDCP2` reader - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp2R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP2` writer - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp2 (& self) -> Udcp2R { Udcp2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp2 (& mut self) -> Udcp2W < Rtiudcp2Spec > { Udcp2W :: new (self , 0) } } # [doc = "Update Compare 2 value to be added to the compare register 2 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp2Spec ; impl crate :: RegisterSpec for Rtiudcp2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp2::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp2Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp2::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP2 to value 0"]
impl crate :: Resettable for Rtiudcp2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP3 (rw) register accessor: Compare 3 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp3`]
module"]
# [doc (alias = "RTICOMP3")]
pub type Rticomp3 = crate :: Reg < rticomp3 :: Rticomp3Spec > ; # [doc = "Compare 3 compare value to be compared with the counters"]
pub mod rticomp3 { # [doc = "Register `RTICOMP3` reader"]
pub type R = crate :: R < Rticomp3Spec > ; # [doc = "Register `RTICOMP3` writer"]
pub type W = crate :: W < Rticomp3Spec > ; # [doc = "Field `COMP3` reader - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3R = crate :: FieldReader < u32 > ; # [doc = "Field `COMP3` writer - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp3 (& self) -> Comp3R { Comp3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp3 (& mut self) -> Comp3W < Rticomp3Spec > { Comp3W :: new (self , 0) } } # [doc = "Compare 3 compare value to be compared with the counters\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp3Spec ; impl crate :: RegisterSpec for Rticomp3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp3::R`](R) reader structure"]
impl crate :: Readable for Rticomp3Spec { } # [doc = "`write(|w| ..)` method takes [`rticomp3::W`](W) writer structure"]
impl crate :: Writable for Rticomp3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP3 to value 0"]
impl crate :: Resettable for Rticomp3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIUDCP3 (rw) register accessor: Update Compare 3 value to be added to the compare register 3 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiudcp3`]
module"]
# [doc (alias = "RTIUDCP3")]
pub type Rtiudcp3 = crate :: Reg < rtiudcp3 :: Rtiudcp3Spec > ; # [doc = "Update Compare 3 value to be added to the compare register 3 value on compare match"]
pub mod rtiudcp3 { # [doc = "Register `RTIUDCP3` reader"]
pub type R = crate :: R < Rtiudcp3Spec > ; # [doc = "Register `RTIUDCP3` writer"]
pub type W = crate :: W < Rtiudcp3Spec > ; # [doc = "Field `UDCP3` reader - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp3R = crate :: FieldReader < u32 > ; # [doc = "Field `UDCP3` writer - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
pub type Udcp3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
pub fn udcp3 (& self) -> Udcp3R { Udcp3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"]
# [inline (always)]
# [must_use]
pub fn udcp3 (& mut self) -> Udcp3W < Rtiudcp3Spec > { Udcp3W :: new (self , 0) } } # [doc = "Update Compare 3 value to be added to the compare register 3 value on compare match\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiudcp3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiudcp3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtiudcp3Spec ; impl crate :: RegisterSpec for Rtiudcp3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiudcp3::R`](R) reader structure"]
impl crate :: Readable for Rtiudcp3Spec { } # [doc = "`write(|w| ..)` method takes [`rtiudcp3::W`](W) writer structure"]
impl crate :: Writable for Rtiudcp3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIUDCP3 to value 0"]
impl crate :: Resettable for Rtiudcp3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTITBLCOMP (rw) register accessor: Timebase Low Compare compare value to activate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitblcomp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitblcomp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtitblcomp`]
module"]
# [doc (alias = "RTITBLCOMP")]
pub type Rtitblcomp = crate :: Reg < rtitblcomp :: RtitblcompSpec > ; # [doc = "Timebase Low Compare compare value to activate edge detection circuit"]
pub mod rtitblcomp { # [doc = "Register `RTITBLCOMP` reader"]
pub type R = crate :: R < RtitblcompSpec > ; # [doc = "Register `RTITBLCOMP` writer"]
pub type W = crate :: W < RtitblcompSpec > ; # [doc = "Field `TBLCOMP` reader - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TblcompR = crate :: FieldReader < u32 > ; # [doc = "Field `TBLCOMP` writer - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TblcompW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
pub fn tblcomp (& self) -> TblcompR { TblcompR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
# [must_use]
pub fn tblcomp (& mut self) -> TblcompW < RtitblcompSpec > { TblcompW :: new (self , 0) } } # [doc = "Timebase Low Compare compare value to activate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitblcomp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitblcomp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtitblcompSpec ; impl crate :: RegisterSpec for RtitblcompSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtitblcomp::R`](R) reader structure"]
impl crate :: Readable for RtitblcompSpec { } # [doc = "`write(|w| ..)` method takes [`rtitblcomp::W`](W) writer structure"]
impl crate :: Writable for RtitblcompSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTITBLCOMP to value 0"]
impl crate :: Resettable for RtitblcompSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTITBHCOMP (rw) register accessor: Timebase High Compare compare value to deactivate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbhcomp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbhcomp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtitbhcomp`]
module"]
# [doc (alias = "RTITBHCOMP")]
pub type Rtitbhcomp = crate :: Reg < rtitbhcomp :: RtitbhcompSpec > ; # [doc = "Timebase High Compare compare value to deactivate edge detection circuit"]
pub mod rtitbhcomp { # [doc = "Register `RTITBHCOMP` reader"]
pub type R = crate :: R < RtitbhcompSpec > ; # [doc = "Register `RTITBHCOMP` writer"]
pub type W = crate :: W < RtitbhcompSpec > ; # [doc = "Field `TBHCOMP` reader - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TbhcompR = crate :: FieldReader < u32 > ; # [doc = "Field `TBHCOMP` writer - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
pub type TbhcompW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
pub fn tbhcomp (& self) -> TbhcompR { TbhcompR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match."]
# [inline (always)]
# [must_use]
pub fn tbhcomp (& mut self) -> TbhcompW < RtitbhcompSpec > { TbhcompW :: new (self , 0) } } # [doc = "Timebase High Compare compare value to deactivate edge detection circuit\n\nYou can [`read`](crate::Reg::read) this register and get [`rtitbhcomp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtitbhcomp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtitbhcompSpec ; impl crate :: RegisterSpec for RtitbhcompSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtitbhcomp::R`](R) reader structure"]
impl crate :: Readable for RtitbhcompSpec { } # [doc = "`write(|w| ..)` method takes [`rtitbhcomp::W`](W) writer structure"]
impl crate :: Writable for RtitbhcompSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTITBHCOMP to value 0"]
impl crate :: Resettable for RtitbhcompSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTISETINT (rw) register accessor: Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rtisetint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtisetint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtisetint`]
module"]
# [doc (alias = "RTISETINT")]
pub type Rtisetint = crate :: Reg < rtisetint :: RtisetintSpec > ; # [doc = "Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
pub mod rtisetint { # [doc = "Register `RTISETINT` reader"]
pub type R = crate :: R < RtisetintSpec > ; # [doc = "Register `RTISETINT` writer"]
pub type W = crate :: W < RtisetintSpec > ; # [doc = "Field `SETINT0` reader - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint0R = crate :: BitReader ; # [doc = "Field `SETINT0` writer - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETINT1` reader - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint1R = crate :: BitReader ; # [doc = "Field `SETINT1` writer - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETINT2` reader - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint2R = crate :: BitReader ; # [doc = "Field `SETINT2` writer - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setint2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETINT3` reader - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
pub type Setint3R = crate :: BitReader ; # [doc = "Field `SETINT3` writer - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
pub type Setint3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED9` reader - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved9R = crate :: FieldReader ; # [doc = "Field `RESERVED9` writer - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `SETDMA0` reader - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma0R = crate :: BitReader ; # [doc = "Field `SETDMA0` writer - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETDMA1` reader - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma1R = crate :: BitReader ; # [doc = "Field `SETDMA1` writer - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETDMA2` reader - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma2R = crate :: BitReader ; # [doc = "Field `SETDMA2` writer - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETDMA3` reader - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma3R = crate :: BitReader ; # [doc = "Field `SETDMA3` writer - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type Setdma3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED10` reader - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved10R = crate :: FieldReader ; # [doc = "Field `RESERVED10` writer - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `SETTBINT` reader - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SettbintR = crate :: BitReader ; # [doc = "Field `SETTBINT` writer - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SettbintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETOVL0INT` reader - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl0intR = crate :: BitReader ; # [doc = "Field `SETOVL0INT` writer - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl0intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETOVL1INT` reader - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl1intR = crate :: BitReader ; # [doc = "Field `SETOVL1INT` writer - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type Setovl1intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED11` reader - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved11R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED11` writer - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setint0 (& self) -> Setint0R { Setint0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setint1 (& self) -> Setint1R { Setint1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setint2 (& self) -> Setint2R { Setint2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
# [inline (always)]
pub fn setint3 (& self) -> Setint3R { Setint3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved9 (& self) -> Reserved9R { Reserved9R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma0 (& self) -> Setdma0R { Setdma0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma1 (& self) -> Setdma1R { Setdma1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma2 (& self) -> Setdma2R { Setdma2R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn setdma3 (& self) -> Setdma3R { Setdma3R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved10 (& self) -> Reserved10R { Reserved10R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn settbint (& self) -> SettbintR { SettbintR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setovl0int (& self) -> Setovl0intR { Setovl0intR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn setovl1int (& self) -> Setovl1intR { Setovl1intR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved11 (& self) -> Reserved11R { Reserved11R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setint0 (& mut self) -> Setint0W < RtisetintSpec > { Setint0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setint1 (& mut self) -> Setint1W < RtisetintSpec > { Setint1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setint2 (& mut self) -> Setint2W < RtisetintSpec > { Setint2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged"]
# [inline (always)]
# [must_use]
pub fn setint3 (& mut self) -> Setint3W < RtisetintSpec > { Setint3W :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved9 (& mut self) -> Reserved9W < RtisetintSpec > { Reserved9W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma0 (& mut self) -> Setdma0W < RtisetintSpec > { Setdma0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma1 (& mut self) -> Setdma1W < RtisetintSpec > { Setdma1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma2 (& mut self) -> Setdma2W < RtisetintSpec > { Setdma2W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn setdma3 (& mut self) -> Setdma3W < RtisetintSpec > { Setdma3W :: new (self , 11) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved10 (& mut self) -> Reserved10W < RtisetintSpec > { Reserved10W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn settbint (& mut self) -> SettbintW < RtisetintSpec > { SettbintW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setovl0int (& mut self) -> Setovl0intW < RtisetintSpec > { Setovl0intW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn setovl1int (& mut self) -> Setovl1intW < RtisetintSpec > { Setovl1intW :: new (self , 18) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved11 (& mut self) -> Reserved11W < RtisetintSpec > { Reserved11W :: new (self , 19) } } # [doc = "Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rtisetint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtisetint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtisetintSpec ; impl crate :: RegisterSpec for RtisetintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtisetint::R`](R) reader structure"]
impl crate :: Readable for RtisetintSpec { } # [doc = "`write(|w| ..)` method takes [`rtisetint::W`](W) writer structure"]
impl crate :: Writable for RtisetintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTISETINT to value 0"]
impl crate :: Resettable for RtisetintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICLEARINT (rw) register accessor: Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rticlearint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticlearint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticlearint`]
module"]
# [doc (alias = "RTICLEARINT")]
pub type Rticlearint = crate :: Reg < rticlearint :: RticlearintSpec > ; # [doc = "Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"]
pub mod rticlearint { # [doc = "Register `RTICLEARINT` reader"]
pub type R = crate :: R < RticlearintSpec > ; # [doc = "Register `RTICLEARINT` writer"]
pub type W = crate :: W < RticlearintSpec > ; # [doc = "Field `CLEARINT0` reader - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint0R = crate :: BitReader ; # [doc = "Field `CLEARINT0` writer - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARINT1` reader - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint1R = crate :: BitReader ; # [doc = "Field `CLEARINT1` writer - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARINT2` reader - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint2R = crate :: BitReader ; # [doc = "Field `CLEARINT2` writer - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARINT3` reader - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint3R = crate :: BitReader ; # [doc = "Field `CLEARINT3` writer - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearint3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED12` reader - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved12R = crate :: FieldReader ; # [doc = "Field `RESERVED12` writer - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CLEARDMA0` reader - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma0R = crate :: BitReader ; # [doc = "Field `CLEARDMA0` writer - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARDMA1` reader - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma1R = crate :: BitReader ; # [doc = "Field `CLEARDMA1` writer - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARDMA2` reader - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma2R = crate :: BitReader ; # [doc = "Field `CLEARDMA2` writer - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEARDMA3` reader - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma3R = crate :: BitReader ; # [doc = "Field `CLEARDMA3` writer - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type Cleardma3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED13` reader - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved13R = crate :: FieldReader ; # [doc = "Field `RESERVED13` writer - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CLEARTBINT` reader - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type CleartbintR = crate :: BitReader ; # [doc = "Field `CLEARTBINT` writer - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type CleartbintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEAROVL0INT` reader - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl0intR = crate :: BitReader ; # [doc = "Field `CLEAROVL0INT` writer - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl0intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLEAROVL1INT` reader - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl1intR = crate :: BitReader ; # [doc = "Field `CLEAROVL1INT` writer - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type Clearovl1intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED14` reader - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved14R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED14` writer - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint0 (& self) -> Clearint0R { Clearint0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint1 (& self) -> Clearint1R { Clearint1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint2 (& self) -> Clearint2R { Clearint2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearint3 (& self) -> Clearint3R { Clearint3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved12 (& self) -> Reserved12R { Reserved12R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma0 (& self) -> Cleardma0R { Cleardma0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma1 (& self) -> Cleardma1R { Cleardma1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma2 (& self) -> Cleardma2R { Cleardma2R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn cleardma3 (& self) -> Cleardma3R { Cleardma3R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved13 (& self) -> Reserved13R { Reserved13R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn cleartbint (& self) -> CleartbintR { CleartbintR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearovl0int (& self) -> Clearovl0intR { Clearovl0intR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clearovl1int (& self) -> Clearovl1intR { Clearovl1intR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved14 (& self) -> Reserved14R { Reserved14R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint0 (& mut self) -> Clearint0W < RticlearintSpec > { Clearint0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint1 (& mut self) -> Clearint1W < RticlearintSpec > { Clearint1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint2 (& mut self) -> Clearint2W < RticlearintSpec > { Clearint2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearint3 (& mut self) -> Clearint3W < RticlearintSpec > { Clearint3W :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved12 (& mut self) -> Reserved12W < RticlearintSpec > { Reserved12W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma0 (& mut self) -> Cleardma0W < RticlearintSpec > { Cleardma0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma1 (& mut self) -> Cleardma1W < RticlearintSpec > { Cleardma1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma2 (& mut self) -> Cleardma2W < RticlearintSpec > { Cleardma2W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn cleardma3 (& mut self) -> Cleardma3W < RticlearintSpec > { Cleardma3W :: new (self , 11) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved13 (& mut self) -> Reserved13W < RticlearintSpec > { Reserved13W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn cleartbint (& mut self) -> CleartbintW < RticlearintSpec > { CleartbintW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearovl0int (& mut self) -> Clearovl0intW < RticlearintSpec > { Clearovl0intW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clearovl1int (& mut self) -> Clearovl1intW < RticlearintSpec > { Clearovl1intW :: new (self , 18) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved14 (& mut self) -> Reserved14W < RticlearintSpec > { Reserved14W :: new (self , 19) } } # [doc = "Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation\n\nYou can [`read`](crate::Reg::read) this register and get [`rticlearint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticlearint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticlearintSpec ; impl crate :: RegisterSpec for RticlearintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticlearint::R`](R) reader structure"]
impl crate :: Readable for RticlearintSpec { } # [doc = "`write(|w| ..)` method takes [`rticlearint::W`](W) writer structure"]
impl crate :: Writable for RticlearintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICLEARINT to value 0"]
impl crate :: Resettable for RticlearintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIINTFLAG (rw) register accessor: Interrupt Flags interrupt pending bits\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintflag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintflag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiintflag`]
module"]
# [doc (alias = "RTIINTFLAG")]
pub type Rtiintflag = crate :: Reg < rtiintflag :: RtiintflagSpec > ; # [doc = "Interrupt Flags interrupt pending bits"]
pub mod rtiintflag { # [doc = "Register `RTIINTFLAG` reader"]
pub type R = crate :: R < RtiintflagSpec > ; # [doc = "Register `RTIINTFLAG` writer"]
pub type W = crate :: W < RtiintflagSpec > ; # [doc = "Field `INT0` reader - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int0R = crate :: BitReader ; # [doc = "Field `INT0` writer - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INT1` reader - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int1R = crate :: BitReader ; # [doc = "Field `INT1` writer - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INT2` reader - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int2R = crate :: BitReader ; # [doc = "Field `INT2` writer - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INT3` reader - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int3R = crate :: BitReader ; # [doc = "Field `INT3` writer - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Int3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED15` reader - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved15R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED15` writer - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `TBINT` reader - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type TbintR = crate :: BitReader ; # [doc = "Field `TBINT` writer - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type TbintW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVL0INT` reader - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl0intR = crate :: BitReader ; # [doc = "Field `OVL0INT` writer - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl0intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVL1INT` reader - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl1intR = crate :: BitReader ; # [doc = "Field `OVL1INT` writer - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
pub type Ovl1intW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED16` reader - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved16R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED16` writer - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int0 (& self) -> Int0R { Int0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int1 (& self) -> Int1R { Int1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int2 (& self) -> Int2R { Int2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn int3 (& self) -> Int3R { Int3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:15 - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved15 (& self) -> Reserved15R { Reserved15R :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bit 16 - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn tbint (& self) -> TbintR { TbintR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn ovl0int (& self) -> Ovl0intR { Ovl0intR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
pub fn ovl1int (& self) -> Ovl1intR { Ovl1intR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved16 (& self) -> Reserved16R { Reserved16R :: new (((self . bits >> 19) & 0x1fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int0 (& mut self) -> Int0W < RtiintflagSpec > { Int0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int1 (& mut self) -> Int1W < RtiintflagSpec > { Int1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int2 (& mut self) -> Int2W < RtiintflagSpec > { Int2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn int3 (& mut self) -> Int3W < RtiintflagSpec > { Int3W :: new (self , 3) } # [doc = "Bits 4:15 - 15:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved15 (& mut self) -> Reserved15W < RtiintflagSpec > { Reserved15W :: new (self , 4) } # [doc = "Bit 16 - 16:16\\]
User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn tbint (& mut self) -> TbintW < RtiintflagSpec > { TbintW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn ovl0int (& mut self) -> Ovl0intW < RtiintflagSpec > { Ovl0intW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0"]
# [inline (always)]
# [must_use]
pub fn ovl1int (& mut self) -> Ovl1intW < RtiintflagSpec > { Ovl1intW :: new (self , 18) } # [doc = "Bits 19:31 - 31:19\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved16 (& mut self) -> Reserved16W < RtiintflagSpec > { Reserved16W :: new (self , 19) } } # [doc = "Interrupt Flags interrupt pending bits\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintflag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintflag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiintflagSpec ; impl crate :: RegisterSpec for RtiintflagSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiintflag::R`](R) reader structure"]
impl crate :: Readable for RtiintflagSpec { } # [doc = "`write(|w| ..)` method takes [`rtiintflag::W`](W) writer structure"]
impl crate :: Writable for RtiintflagSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIINTFLAG to value 0"]
impl crate :: Resettable for RtiintflagSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIDWDCTRL (rw) register accessor: Digital Watchdog Control Enables the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtidwdctrl`]
module"]
# [doc (alias = "RTIDWDCTRL")]
pub type Rtidwdctrl = crate :: Reg < rtidwdctrl :: RtidwdctrlSpec > ; # [doc = "Digital Watchdog Control Enables the Digital Watchdog"]
pub mod rtidwdctrl { # [doc = "Register `RTIDWDCTRL` reader"]
pub type R = crate :: R < RtidwdctrlSpec > ; # [doc = "Register `RTIDWDCTRL` writer"]
pub type W = crate :: W < RtidwdctrlSpec > ; # [doc = "Field `DWDCTRL` reader - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
pub type DwdctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `DWDCTRL` writer - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
pub type DwdctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
# [inline (always)]
pub fn dwdctrl (& self) -> DwdctrlR { DwdctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again."]
# [inline (always)]
# [must_use]
pub fn dwdctrl (& mut self) -> DwdctrlW < RtidwdctrlSpec > { DwdctrlW :: new (self , 0) } } # [doc = "Digital Watchdog Control Enables the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtidwdctrlSpec ; impl crate :: RegisterSpec for RtidwdctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtidwdctrl::R`](R) reader structure"]
impl crate :: Readable for RtidwdctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtidwdctrl::W`](W) writer structure"]
impl crate :: Writable for RtidwdctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIDWDCTRL to value 0"]
impl crate :: Resettable for RtidwdctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIDWDPRLD (rw) register accessor: Digital Watchdog Preload sets the experation time of the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdprld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdprld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtidwdprld`]
module"]
# [doc (alias = "RTIDWDPRLD")]
pub type Rtidwdprld = crate :: Reg < rtidwdprld :: RtidwdprldSpec > ; # [doc = "Digital Watchdog Preload sets the experation time of the Digital Watchdog"]
pub mod rtidwdprld { # [doc = "Register `RTIDWDPRLD` reader"]
pub type R = crate :: R < RtidwdprldSpec > ; # [doc = "Register `RTIDWDPRLD` writer"]
pub type W = crate :: W < RtidwdprldSpec > ; # [doc = "Field `DWDPRLD` reader - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
pub type DwdprldR = crate :: FieldReader < u16 > ; # [doc = "Field `DWDPRLD` writer - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
pub type DwdprldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `RESERVED17` reader - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved17R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED17` writer - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
# [inline (always)]
pub fn dwdprld (& self) -> DwdprldR { DwdprldR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:31 - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved17 (& self) -> Reserved17R { Reserved17R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095"]
# [inline (always)]
# [must_use]
pub fn dwdprld (& mut self) -> DwdprldW < RtidwdprldSpec > { DwdprldW :: new (self , 0) } # [doc = "Bits 12:31 - 31:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved17 (& mut self) -> Reserved17W < RtidwdprldSpec > { Reserved17W :: new (self , 12) } } # [doc = "Digital Watchdog Preload sets the experation time of the Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdprld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdprld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtidwdprldSpec ; impl crate :: RegisterSpec for RtidwdprldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtidwdprld::R`](R) reader structure"]
impl crate :: Readable for RtidwdprldSpec { } # [doc = "`write(|w| ..)` method takes [`rtidwdprld::W`](W) writer structure"]
impl crate :: Writable for RtidwdprldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIDWDPRLD to value 0"]
impl crate :: Resettable for RtidwdprldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWDSTATUS (rw) register accessor: Watchdog Status reflects the status of Analog and Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwdstatus`]
module"]
# [doc (alias = "RTIWDSTATUS")]
pub type Rtiwdstatus = crate :: Reg < rtiwdstatus :: RtiwdstatusSpec > ; # [doc = "Watchdog Status reflects the status of Analog and Digital Watchdog"]
pub mod rtiwdstatus { # [doc = "Register `RTIWDSTATUS` reader"]
pub type R = crate :: R < RtiwdstatusSpec > ; # [doc = "Register `RTIWDSTATUS` writer"]
pub type W = crate :: W < RtiwdstatusSpec > ; # [doc = "Field `AWDST` reader - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type AwdstR = crate :: BitReader ; # [doc = "Field `AWDST` writer - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type AwdstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DWDST` reader - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type DwdstR = crate :: BitReader ; # [doc = "Field `DWDST` writer - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type DwdstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KEYST` reader - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type KeystR = crate :: BitReader ; # [doc = "Field `KEYST` writer - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
pub type KeystW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STARTTIMEVIOL` reader - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type StarttimeviolR = crate :: BitReader ; # [doc = "Field `STARTTIMEVIOL` writer - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type StarttimeviolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENDTIMEVIOL` reader - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type EndtimeviolR = crate :: BitReader ; # [doc = "Field `ENDTIMEVIOL` writer - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
pub type EndtimeviolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DWWD_ST` reader - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
pub type DwwdStR = crate :: BitReader ; # [doc = "Field `DWWD_ST` writer - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
pub type DwwdStW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED18` reader - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved18R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED18` writer - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
pub fn awdst (& self) -> AwdstR { AwdstR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
pub fn dwdst (& self) -> DwdstR { DwdstR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
pub fn keyst (& self) -> KeystR { KeystR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
pub fn starttimeviol (& self) -> StarttimeviolR { StarttimeviolR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
pub fn endtimeviol (& self) -> EndtimeviolR { EndtimeviolR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
# [inline (always)]
pub fn dwwd_st (& self) -> DwwdStR { DwwdStR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved18 (& self) -> Reserved18R { Reserved18R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 ΓÇô> 1 threshold not exceeded 1 = AWD pin 0 ΓÇô> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
# [must_use]
pub fn awdst (& mut self) -> AwdstW < RtiwdstatusSpec > { AwdstW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
# [must_use]
pub fn dwdst (& mut self) -> DwdstW < RtiwdstatusSpec > { DwdstW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0"]
# [inline (always)]
# [must_use]
pub fn keyst (& mut self) -> KeystW < RtiwdstatusSpec > { KeystW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
# [must_use]
pub fn starttimeviol (& mut self) -> StarttimeviolW < RtiwdstatusSpec > { StarttimeviolW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0."]
# [inline (always)]
# [must_use]
pub fn endtimeviol (& mut self) -> EndtimeviolW < RtiwdstatusSpec > { EndtimeviolW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD."]
# [inline (always)]
# [must_use]
pub fn dwwd_st (& mut self) -> DwwdStW < RtiwdstatusSpec > { DwwdStW :: new (self , 5) } # [doc = "Bits 6:31 - 31:6\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved18 (& mut self) -> Reserved18W < RtiwdstatusSpec > { Reserved18W :: new (self , 6) } } # [doc = "Watchdog Status reflects the status of Analog and Digital Watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwdstatusSpec ; impl crate :: RegisterSpec for RtiwdstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwdstatus::R`](R) reader structure"]
impl crate :: Readable for RtiwdstatusSpec { } # [doc = "`write(|w| ..)` method takes [`rtiwdstatus::W`](W) writer structure"]
impl crate :: Writable for RtiwdstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWDSTATUS to value 0"]
impl crate :: Resettable for RtiwdstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWDKEY (rw) register accessor: Watchdog Key correct written key values discharge the external capacitor\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdkey::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdkey::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwdkey`]
module"]
# [doc (alias = "RTIWDKEY")]
pub type Rtiwdkey = crate :: Reg < rtiwdkey :: RtiwdkeySpec > ; # [doc = "Watchdog Key correct written key values discharge the external capacitor"]
pub mod rtiwdkey { # [doc = "Register `RTIWDKEY` reader"]
pub type R = crate :: R < RtiwdkeySpec > ; # [doc = "Register `RTIWDKEY` writer"]
pub type W = crate :: W < RtiwdkeySpec > ; # [doc = "Field `WDKEY` reader - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
pub type WdkeyR = crate :: FieldReader < u16 > ; # [doc = "Field `WDKEY` writer - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
pub type WdkeyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `RESERVED19` reader - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved19R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED19` writer - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved19W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
# [inline (always)]
pub fn wdkey (& self) -> WdkeyR { WdkeyR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved19 (& self) -> Reserved19R { Reserved19R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1ΓÇÖs. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation."]
# [inline (always)]
# [must_use]
pub fn wdkey (& mut self) -> WdkeyW < RtiwdkeySpec > { WdkeyW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved19 (& mut self) -> Reserved19W < RtiwdkeySpec > { Reserved19W :: new (self , 16) } } # [doc = "Watchdog Key correct written key values discharge the external capacitor\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwdkey::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwdkey::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwdkeySpec ; impl crate :: RegisterSpec for RtiwdkeySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwdkey::R`](R) reader structure"]
impl crate :: Readable for RtiwdkeySpec { } # [doc = "`write(|w| ..)` method takes [`rtiwdkey::W`](W) writer structure"]
impl crate :: Writable for RtiwdkeySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWDKEY to value 0"]
impl crate :: Resettable for RtiwdkeySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIDWDCNTR (rw) register accessor: Digital Watchdog Down Counter current value of DWD down counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdcntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdcntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtidwdcntr`]
module"]
# [doc (alias = "RTIDWDCNTR")]
pub type Rtidwdcntr = crate :: Reg < rtidwdcntr :: RtidwdcntrSpec > ; # [doc = "Digital Watchdog Down Counter current value of DWD down counter"]
pub mod rtidwdcntr { # [doc = "Register `RTIDWDCNTR` reader"]
pub type R = crate :: R < RtidwdcntrSpec > ; # [doc = "Register `RTIDWDCNTR` writer"]
pub type W = crate :: W < RtidwdcntrSpec > ; # [doc = "Field `DWDCNTR` reader - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
pub type DwdcntrR = crate :: FieldReader < u32 > ; # [doc = "Field `DWDCNTR` writer - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
pub type DwdcntrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; # [doc = "Field `RESERVED20` reader - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved20R = crate :: FieldReader ; # [doc = "Field `RESERVED20` writer - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved20W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:24 - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
# [inline (always)]
pub fn dwdcntr (& self) -> DwdcntrR { DwdcntrR :: new (self . bits & 0x01ff_ffff) } # [doc = "Bits 25:31 - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved20 (& self) -> Reserved20R { Reserved20R :: new (((self . bits >> 25) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:24 - 24:0\\]
DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes donΓÇÖt have an effect."]
# [inline (always)]
# [must_use]
pub fn dwdcntr (& mut self) -> DwdcntrW < RtidwdcntrSpec > { DwdcntrW :: new (self , 0) } # [doc = "Bits 25:31 - 31:25\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved20 (& mut self) -> Reserved20W < RtidwdcntrSpec > { Reserved20W :: new (self , 25) } } # [doc = "Digital Watchdog Down Counter current value of DWD down counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rtidwdcntr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtidwdcntr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtidwdcntrSpec ; impl crate :: RegisterSpec for RtidwdcntrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtidwdcntr::R`](R) reader structure"]
impl crate :: Readable for RtidwdcntrSpec { } # [doc = "`write(|w| ..)` method takes [`rtidwdcntr::W`](W) writer structure"]
impl crate :: Writable for RtidwdcntrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIDWDCNTR to value 0"]
impl crate :: Resettable for RtidwdcntrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWWDRXNCTRL (rw) register accessor: Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdrxnctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdrxnctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwwdrxnctrl`]
module"]
# [doc (alias = "RTIWWDRXNCTRL")]
pub type Rtiwwdrxnctrl = crate :: Reg < rtiwwdrxnctrl :: RtiwwdrxnctrlSpec > ; # [doc = "Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"]
pub mod rtiwwdrxnctrl { # [doc = "Register `RTIWWDRXNCTRL` reader"]
pub type R = crate :: R < RtiwwdrxnctrlSpec > ; # [doc = "Register `RTIWWDRXNCTRL` writer"]
pub type W = crate :: W < RtiwwdrxnctrlSpec > ; # [doc = "Field `WWDRXN` reader - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
pub type WwdrxnR = crate :: FieldReader ; # [doc = "Field `WWDRXN` writer - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
pub type WwdrxnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED21` reader - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved21R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED21` writer - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved21W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
# [inline (always)]
pub fn wwdrxn (& self) -> WwdrxnR { WwdrxnR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved21 (& self) -> Reserved21R { Reserved21R :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."]
# [inline (always)]
# [must_use]
pub fn wwdrxn (& mut self) -> WwdrxnW < RtiwwdrxnctrlSpec > { WwdrxnW :: new (self , 0) } # [doc = "Bits 4:31 - 31:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved21 (& mut self) -> Reserved21W < RtiwwdrxnctrlSpec > { Reserved21W :: new (self , 4) } } # [doc = "Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdrxnctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdrxnctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwwdrxnctrlSpec ; impl crate :: RegisterSpec for RtiwwdrxnctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwwdrxnctrl::R`](R) reader structure"]
impl crate :: Readable for RtiwwdrxnctrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtiwwdrxnctrl::W`](W) writer structure"]
impl crate :: Writable for RtiwwdrxnctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWWDRXNCTRL to value 0"]
impl crate :: Resettable for RtiwwdrxnctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIWWDSIZECTRL (rw) register accessor: Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdsizectrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdsizectrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiwwdsizectrl`]
module"]
# [doc (alias = "RTIWWDSIZECTRL")]
pub type Rtiwwdsizectrl = crate :: Reg < rtiwwdsizectrl :: RtiwwdsizectrlSpec > ; # [doc = "Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"]
pub mod rtiwwdsizectrl { # [doc = "Register `RTIWWDSIZECTRL` reader"]
pub type R = crate :: R < RtiwwdsizectrlSpec > ; # [doc = "Register `RTIWWDSIZECTRL` writer"]
pub type W = crate :: W < RtiwwdsizectrlSpec > ; # [doc = "Field `WWDSIZE` reader - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
pub type WwdsizeR = crate :: FieldReader < u32 > ; # [doc = "Field `WWDSIZE` writer - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
pub type WwdsizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
# [inline (always)]
pub fn wwdsize (& self) -> WwdsizeR { WwdsizeR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then"]
# [inline (always)]
# [must_use]
pub fn wwdsize (& mut self) -> WwdsizeW < RtiwwdsizectrlSpec > { WwdsizeW :: new (self , 0) } } # [doc = "Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiwwdsizectrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiwwdsizectrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiwwdsizectrlSpec ; impl crate :: RegisterSpec for RtiwwdsizectrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiwwdsizectrl::R`](R) reader structure"]
impl crate :: Readable for RtiwwdsizectrlSpec { } # [doc = "`write(|w| ..)` method takes [`rtiwwdsizectrl::W`](W) writer structure"]
impl crate :: Writable for RtiwwdsizectrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIWWDSIZECTRL to value 0"]
impl crate :: Resettable for RtiwwdsizectrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTIINTCLRENABLE (rw) register accessor: RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintclrenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintclrenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtiintclrenable`]
module"]
# [doc (alias = "RTIINTCLRENABLE")]
pub type Rtiintclrenable = crate :: Reg < rtiintclrenable :: RtiintclrenableSpec > ; # [doc = "RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"]
pub mod rtiintclrenable { # [doc = "Register `RTIINTCLRENABLE` reader"]
pub type R = crate :: R < RtiintclrenableSpec > ; # [doc = "Register `RTIINTCLRENABLE` writer"]
pub type W = crate :: W < RtiintclrenableSpec > ; # [doc = "Field `INTCLRENABLE0` reader - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
pub type Intclrenable0R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE0` writer - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
pub type Intclrenable0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED22` reader - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved22R = crate :: FieldReader ; # [doc = "Field `RESERVED22` writer - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved22W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `INTCLRENABLE1` reader - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
pub type Intclrenable1R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE1` writer - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
pub type Intclrenable1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED23` reader - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved23R = crate :: FieldReader ; # [doc = "Field `RESERVED23` writer - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved23W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `INTCLRENABLE2` reader - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
pub type Intclrenable2R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE2` writer - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
pub type Intclrenable2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED24` reader - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved24R = crate :: FieldReader ; # [doc = "Field `RESERVED24` writer - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved24W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `INTCLRENABLE3` reader - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
pub type Intclrenable3R = crate :: FieldReader ; # [doc = "Field `INTCLRENABLE3` writer - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
pub type Intclrenable3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED25` reader - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved25R = crate :: FieldReader ; # [doc = "Field `RESERVED25` writer - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
pub type Reserved25W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
# [inline (always)]
pub fn intclrenable0 (& self) -> Intclrenable0R { Intclrenable0R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved22 (& self) -> Reserved22R { Reserved22R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
# [inline (always)]
pub fn intclrenable1 (& self) -> Intclrenable1R { Intclrenable1R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved23 (& self) -> Reserved23R { Reserved23R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
# [inline (always)]
pub fn intclrenable2 (& self) -> Intclrenable2R { Intclrenable2R :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved24 (& self) -> Reserved24R { Reserved24R :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:27 - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
# [inline (always)]
pub fn intclrenable3 (& self) -> Intclrenable3R { Intclrenable3R :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bits 28:31 - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
pub fn reserved25 (& self) -> Reserved25R { Reserved25R :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable0 (& mut self) -> Intclrenable0W < RtiintclrenableSpec > { Intclrenable0W :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved22 (& mut self) -> Reserved22W < RtiintclrenableSpec > { Reserved22W :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable1 (& mut self) -> Intclrenable1W < RtiintclrenableSpec > { Intclrenable1W :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved23 (& mut self) -> Reserved23W < RtiintclrenableSpec > { Reserved23W :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable2 (& mut self) -> Intclrenable2W < RtiintclrenableSpec > { Intclrenable2W :: new (self , 16) } # [doc = "Bits 20:23 - 23:20\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved24 (& mut self) -> Reserved24W < RtiintclrenableSpec > { Reserved24W :: new (self , 20) } # [doc = "Bits 24:27 - 27:24\\]
INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt."]
# [inline (always)]
# [must_use]
pub fn intclrenable3 (& mut self) -> Intclrenable3W < RtiintclrenableSpec > { Intclrenable3W :: new (self , 24) } # [doc = "Bits 28:31 - 31:28\\]
Reserved. Reads return 0 and writes have no effect"]
# [inline (always)]
# [must_use]
pub fn reserved25 (& mut self) -> Reserved25W < RtiintclrenableSpec > { Reserved25W :: new (self , 28) } } # [doc = "RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts\n\nYou can [`read`](crate::Reg::read) this register and get [`rtiintclrenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtiintclrenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtiintclrenableSpec ; impl crate :: RegisterSpec for RtiintclrenableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rtiintclrenable::R`](R) reader structure"]
impl crate :: Readable for RtiintclrenableSpec { } # [doc = "`write(|w| ..)` method takes [`rtiintclrenable::W`](W) writer structure"]
impl crate :: Writable for RtiintclrenableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTIINTCLRENABLE to value 0"]
impl crate :: Resettable for RtiintclrenableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP0CLR (rw) register accessor: Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp0clr`]
module"]
# [doc (alias = "RTICOMP0CLR")]
pub type Rticomp0clr = crate :: Reg < rticomp0clr :: Rticomp0clrSpec > ; # [doc = "Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"]
pub mod rticomp0clr { # [doc = "Register `RTICOMP0CLR` reader"]
pub type R = crate :: R < Rticomp0clrSpec > ; # [doc = "Register `RTICOMP0CLR` writer"]
pub type W = crate :: W < Rticomp0clrSpec > ; # [doc = "Field `COMP0CLR` reader - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP0CLR` writer - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp0clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp0clr (& self) -> Comp0clrR { Comp0clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp0clr (& mut self) -> Comp0clrW < Rticomp0clrSpec > { Comp0clrW :: new (self , 0) } } # [doc = "Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp0clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp0clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp0clrSpec ; impl crate :: RegisterSpec for Rticomp0clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp0clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp0clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp0clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp0clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP0CLR to value 0"]
impl crate :: Resettable for Rticomp0clrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP1CLR (rw) register accessor: Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp1clr`]
module"]
# [doc (alias = "RTICOMP1CLR")]
pub type Rticomp1clr = crate :: Reg < rticomp1clr :: Rticomp1clrSpec > ; # [doc = "Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"]
pub mod rticomp1clr { # [doc = "Register `RTICOMP1CLR` reader"]
pub type R = crate :: R < Rticomp1clrSpec > ; # [doc = "Register `RTICOMP1CLR` writer"]
pub type W = crate :: W < Rticomp1clrSpec > ; # [doc = "Field `COMP1CLR` reader - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP1CLR` writer - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp1clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp1clr (& self) -> Comp1clrR { Comp1clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp1clr (& mut self) -> Comp1clrW < Rticomp1clrSpec > { Comp1clrW :: new (self , 0) } } # [doc = "Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp1clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp1clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp1clrSpec ; impl crate :: RegisterSpec for Rticomp1clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp1clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp1clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp1clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp1clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP1CLR to value 0"]
impl crate :: Resettable for Rticomp1clrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP2CLR (rw) register accessor: Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp2clr`]
module"]
# [doc (alias = "RTICOMP2CLR")]
pub type Rticomp2clr = crate :: Reg < rticomp2clr :: Rticomp2clrSpec > ; # [doc = "Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"]
pub mod rticomp2clr { # [doc = "Register `RTICOMP2CLR` reader"]
pub type R = crate :: R < Rticomp2clrSpec > ; # [doc = "Register `RTICOMP2CLR` writer"]
pub type W = crate :: W < Rticomp2clrSpec > ; # [doc = "Field `COMP2CLR` reader - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP2CLR` writer - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp2clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp2clr (& self) -> Comp2clrR { Comp2clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp2clr (& mut self) -> Comp2clrW < Rticomp2clrSpec > { Comp2clrW :: new (self , 0) } } # [doc = "Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp2clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp2clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp2clrSpec ; impl crate :: RegisterSpec for Rticomp2clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp2clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp2clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp2clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp2clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP2CLR to value 0"]
impl crate :: Resettable for Rticomp2clrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICOMP3CLR (rw) register accessor: Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticomp3clr`]
module"]
# [doc (alias = "RTICOMP3CLR")]
pub type Rticomp3clr = crate :: Reg < rticomp3clr :: Rticomp3clrSpec > ; # [doc = "Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"]
pub mod rticomp3clr { # [doc = "Register `RTICOMP3CLR` reader"]
pub type R = crate :: R < Rticomp3clrSpec > ; # [doc = "Register `RTICOMP3CLR` writer"]
pub type W = crate :: W < Rticomp3clrSpec > ; # [doc = "Field `COMP3CLR` reader - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3clrR = crate :: FieldReader < u32 > ; # [doc = "Field `COMP3CLR` writer - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
pub type Comp3clrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
pub fn comp3clr (& self) -> Comp3clrR { Comp3clrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."]
# [inline (always)]
# [must_use]
pub fn comp3clr (& mut self) -> Comp3clrW < Rticomp3clrSpec > { Comp3clrW :: new (self , 0) } } # [doc = "Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line\n\nYou can [`read`](crate::Reg::read) this register and get [`rticomp3clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticomp3clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rticomp3clrSpec ; impl crate :: RegisterSpec for Rticomp3clrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticomp3clr::R`](R) reader structure"]
impl crate :: Readable for Rticomp3clrSpec { } # [doc = "`write(|w| ..)` method takes [`rticomp3clr::W`](W) writer structure"]
impl crate :: Writable for Rticomp3clrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICOMP3CLR to value 0"]
impl crate :: Resettable for Rticomp3clrSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_DCC"]
pub struct AppDcc { _marker : PhantomData < * const () > } unsafe impl Send for AppDcc { } impl AppDcc { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_dcc :: RegisterBlock = 0x56f7_f800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_dcc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppDcc { type Target = app_dcc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppDcc { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppDcc") . finish () } } # [doc = "APP_DCC"]
pub mod app_dcc { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { dccgctrl : Dccgctrl , dccrev : Dccrev , dcccntseed0 : Dcccntseed0 , dccvalidseed0 : Dccvalidseed0 , dcccntseed1 : Dcccntseed1 , dccstat : Dccstat , dcccnt0 : Dcccnt0 , dccvalid0 : Dccvalid0 , dcccnt1 : Dcccnt1 , dccclkssrc1 : Dccclkssrc1 , dccclkssrc0 : Dccclkssrc0 , _reserved11 : [u8 ; 0x04]
, dccgctrl2 : Dccgctrl2 , dccstatus2 : Dccstatus2 , dccerrcnt : Dccerrcnt , } impl RegisterBlock { # [doc = "0x00 - Starts / stops the counters clears the error signal"]
# [inline (always)]
pub const fn dccgctrl (& self) -> & Dccgctrl { & self . dccgctrl } # [doc = "0x04 - Module version"]
# [inline (always)]
pub const fn dccrev (& self) -> & Dccrev { & self . dccrev } # [doc = "0x08 - Seed value for the counter attached to clock source 0"]
# [inline (always)]
pub const fn dcccntseed0 (& self) -> & Dcccntseed0 { & self . dcccntseed0 } # [doc = "0x0c - Seed value for the timeout counter attached to clock source 0"]
# [inline (always)]
pub const fn dccvalidseed0 (& self) -> & Dccvalidseed0 { & self . dccvalidseed0 } # [doc = "0x10 - Seed value for the counter attached to clock source 1"]
# [inline (always)]
pub const fn dcccntseed1 (& self) -> & Dcccntseed1 { & self . dcccntseed1 } # [doc = "0x14 - Contains the error &amp; done flag bit"]
# [inline (always)]
pub const fn dccstat (& self) -> & Dccstat { & self . dccstat } # [doc = "0x18 - Value of the counter attached to clock source 0"]
# [inline (always)]
pub const fn dcccnt0 (& self) -> & Dcccnt0 { & self . dcccnt0 } # [doc = "0x1c - Value of the valid counter attached to clock source 0"]
# [inline (always)]
pub const fn dccvalid0 (& self) -> & Dccvalid0 { & self . dccvalid0 } # [doc = "0x20 - Value of the counter attached to clock source 1"]
# [inline (always)]
pub const fn dcccnt1 (& self) -> & Dcccnt1 { & self . dcccnt1 } # [doc = "0x24 - Clock source1 selection control"]
# [inline (always)]
pub const fn dccclkssrc1 (& self) -> & Dccclkssrc1 { & self . dccclkssrc1 } # [doc = "0x28 - Clock source0 selection control"]
# [inline (always)]
pub const fn dccclkssrc0 (& self) -> & Dccclkssrc0 { & self . dccclkssrc0 } # [doc = "0x30 - Global control register 2"]
# [inline (always)]
pub const fn dccgctrl2 (& self) -> & Dccgctrl2 { & self . dccgctrl2 } # [doc = "0x34 - FIFO status register"]
# [inline (always)]
pub const fn dccstatus2 (& self) -> & Dccstatus2 { & self . dccstatus2 } # [doc = "0x38 - Error count register"]
# [inline (always)]
pub const fn dccerrcnt (& self) -> & Dccerrcnt { & self . dccerrcnt } } # [doc = "DCCGCTRL (rw) register accessor: Starts / stops the counters clears the error signal\n\nYou can [`read`](crate::Reg::read) this register and get [`dccgctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccgctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccgctrl`]
module"]
# [doc (alias = "DCCGCTRL")]
pub type Dccgctrl = crate :: Reg < dccgctrl :: DccgctrlSpec > ; # [doc = "Starts / stops the counters clears the error signal"]
pub mod dccgctrl { # [doc = "Register `DCCGCTRL` reader"]
pub type R = crate :: R < DccgctrlSpec > ; # [doc = "Register `DCCGCTRL` writer"]
pub type W = crate :: W < DccgctrlSpec > ; # [doc = "Field `DCCENA` reader - 3:0\\]
The DCCENA bit starts and stops the operation of the dcc 0101 = disabled &amp; 1010 = enabled"]
pub type DccenaR = crate :: FieldReader ; # [doc = "Field `DCCENA` writer - 3:0\\]
The DCCENA bit starts and stops the operation of the dcc 0101 = disabled &amp; 1010 = enabled"]
pub type DccenaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ERRENA` reader - 7:4\\]
The ERRENA bit enables/disables the error signal. 0101 = disabled &amp; 1010 = enabled"]
pub type ErrenaR = crate :: FieldReader ; # [doc = "Field `ERRENA` writer - 7:4\\]
The ERRENA bit enables/disables the error signal. 0101 = disabled &amp; 1010 = enabled"]
pub type ErrenaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `SINGLESHOT` reader - 11:8\\]
Single/Continuous checking mode. 0101 = Continuous &amp; 1010 = Single"]
pub type SingleshotR = crate :: FieldReader ; # [doc = "Field `SINGLESHOT` writer - 11:8\\]
Single/Continuous checking mode. 0101 = Continuous &amp; 1010 = Single"]
pub type SingleshotW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DONENA` reader - 15:12\\]
The DONEENA bit enables/disables the done signal. 0101 = disabled &amp; 1010 = enabled"]
pub type DonenaR = crate :: FieldReader ; # [doc = "Field `DONENA` writer - 15:12\\]
The DONEENA bit enables/disables the done signal. 0101 = disabled &amp; 1010 = enabled"]
pub type DonenaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU` reader - 31:16\\]
Reserved"]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:16\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
The DCCENA bit starts and stops the operation of the dcc 0101 = disabled &amp; 1010 = enabled"]
# [inline (always)]
pub fn dccena (& self) -> DccenaR { DccenaR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
The ERRENA bit enables/disables the error signal. 0101 = disabled &amp; 1010 = enabled"]
# [inline (always)]
pub fn errena (& self) -> ErrenaR { ErrenaR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Single/Continuous checking mode. 0101 = Continuous &amp; 1010 = Single"]
# [inline (always)]
pub fn singleshot (& self) -> SingleshotR { SingleshotR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
The DONEENA bit enables/disables the done signal. 0101 = disabled &amp; 1010 = enabled"]
# [inline (always)]
pub fn donena (& self) -> DonenaR { DonenaR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
The DCCENA bit starts and stops the operation of the dcc 0101 = disabled &amp; 1010 = enabled"]
# [inline (always)]
# [must_use]
pub fn dccena (& mut self) -> DccenaW < DccgctrlSpec > { DccenaW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
The ERRENA bit enables/disables the error signal. 0101 = disabled &amp; 1010 = enabled"]
# [inline (always)]
# [must_use]
pub fn errena (& mut self) -> ErrenaW < DccgctrlSpec > { ErrenaW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Single/Continuous checking mode. 0101 = Continuous &amp; 1010 = Single"]
# [inline (always)]
# [must_use]
pub fn singleshot (& mut self) -> SingleshotW < DccgctrlSpec > { SingleshotW :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
The DONEENA bit enables/disables the done signal. 0101 = disabled &amp; 1010 = enabled"]
# [inline (always)]
# [must_use]
pub fn donena (& mut self) -> DonenaW < DccgctrlSpec > { DonenaW :: new (self , 12) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < DccgctrlSpec > { NuW :: new (self , 16) } } # [doc = "Starts / stops the counters clears the error signal\n\nYou can [`read`](crate::Reg::read) this register and get [`dccgctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccgctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DccgctrlSpec ; impl crate :: RegisterSpec for DccgctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccgctrl::R`](R) reader structure"]
impl crate :: Readable for DccgctrlSpec { } # [doc = "`write(|w| ..)` method takes [`dccgctrl::W`](W) writer structure"]
impl crate :: Writable for DccgctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCGCTRL to value 0"]
impl crate :: Resettable for DccgctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCREV (rw) register accessor: Module version\n\nYou can [`read`](crate::Reg::read) this register and get [`dccrev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccrev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccrev`]
module"]
# [doc (alias = "DCCREV")]
pub type Dccrev = crate :: Reg < dccrev :: DccrevSpec > ; # [doc = "Module version"]
pub mod dccrev { # [doc = "Register `DCCREV` reader"]
pub type R = crate :: R < DccrevSpec > ; # [doc = "Register `DCCREV` writer"]
pub type W = crate :: W < DccrevSpec > ; # [doc = "Field `MINOR` reader - 5:0\\]
Minor revision number. - (RO )"]
pub type MinorR = crate :: FieldReader ; # [doc = "Field `MINOR` writer - 5:0\\]
Minor revision number. - (RO )"]
pub type MinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Indicates a special version of the module. May not be supported by standard software - (RO )"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Indicates a special version of the module. May not be supported by standard software - (RO )"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR` reader - 10:8\\]
Major Revision Number - (RO )"]
pub type MajorR = crate :: FieldReader ; # [doc = "Field `MAJOR` writer - 10:8\\]
Major Revision Number - (RO )"]
pub type MajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL` reader - 15:11\\]
Design Release Number - (RO )"]
pub type RtlR = crate :: FieldReader ; # [doc = "Field `RTL` writer - 15:11\\]
Design Release Number - (RO )"]
pub type RtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNC` reader - 27:16\\]
Functional release number - (RO )"]
pub type FuncR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNC` writer - 27:16\\]
Functional release number - (RO )"]
pub type FuncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `NU1` reader - 29:28\\]
Reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 29:28\\]
Reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
SCHEME. - (RO )"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
SCHEME. - (RO )"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor revision number. - (RO )"]
# [inline (always)]
pub fn minor (& self) -> MinorR { MinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Indicates a special version of the module. May not be supported by standard software - (RO )"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision Number - (RO )"]
# [inline (always)]
pub fn major (& self) -> MajorR { MajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
Design Release Number - (RO )"]
# [inline (always)]
pub fn rtl (& self) -> RtlR { RtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Functional release number - (RO )"]
# [inline (always)]
pub fn func (& self) -> FuncR { FuncR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
Reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
SCHEME. - (RO )"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor revision number. - (RO )"]
# [inline (always)]
# [must_use]
pub fn minor (& mut self) -> MinorW < DccrevSpec > { MinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Indicates a special version of the module. May not be supported by standard software - (RO )"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < DccrevSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision Number - (RO )"]
# [inline (always)]
# [must_use]
pub fn major (& mut self) -> MajorW < DccrevSpec > { MajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
Design Release Number - (RO )"]
# [inline (always)]
# [must_use]
pub fn rtl (& mut self) -> RtlW < DccrevSpec > { RtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Functional release number - (RO )"]
# [inline (always)]
# [must_use]
pub fn func (& mut self) -> FuncW < DccrevSpec > { FuncW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < DccrevSpec > { Nu1W :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
SCHEME. - (RO )"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < DccrevSpec > { SchemeW :: new (self , 30) } } # [doc = "Module version\n\nYou can [`read`](crate::Reg::read) this register and get [`dccrev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccrev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DccrevSpec ; impl crate :: RegisterSpec for DccrevSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccrev::R`](R) reader structure"]
impl crate :: Readable for DccrevSpec { } # [doc = "`write(|w| ..)` method takes [`dccrev::W`](W) writer structure"]
impl crate :: Writable for DccrevSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCREV to value 0"]
impl crate :: Resettable for DccrevSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCCNTSEED0 (rw) register accessor: Seed value for the counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccntseed0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccntseed0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcccntseed0`]
module"]
# [doc (alias = "DCCCNTSEED0")]
pub type Dcccntseed0 = crate :: Reg < dcccntseed0 :: Dcccntseed0Spec > ; # [doc = "Seed value for the counter attached to clock source 0"]
pub mod dcccntseed0 { # [doc = "Register `DCCCNTSEED0` reader"]
pub type R = crate :: R < Dcccntseed0Spec > ; # [doc = "Register `DCCCNTSEED0` writer"]
pub type W = crate :: W < Dcccntseed0Spec > ; # [doc = "Field `COUNTSEED0` reader - 19:0\\]
The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"]
pub type Countseed0R = crate :: FieldReader < u32 > ; # [doc = "Field `COUNTSEED0` writer - 19:0\\]
The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"]
pub type Countseed0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `NU3` reader - 31:20\\]
Reserved"]
pub type Nu3R = crate :: FieldReader < u16 > ; # [doc = "Field `NU3` writer - 31:20\\]
Reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"]
# [inline (always)]
pub fn countseed0 (& self) -> Countseed0R { Countseed0R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"]
# [inline (always)]
# [must_use]
pub fn countseed0 (& mut self) -> Countseed0W < Dcccntseed0Spec > { Countseed0W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < Dcccntseed0Spec > { Nu3W :: new (self , 20) } } # [doc = "Seed value for the counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccntseed0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccntseed0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcccntseed0Spec ; impl crate :: RegisterSpec for Dcccntseed0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcccntseed0::R`](R) reader structure"]
impl crate :: Readable for Dcccntseed0Spec { } # [doc = "`write(|w| ..)` method takes [`dcccntseed0::W`](W) writer structure"]
impl crate :: Writable for Dcccntseed0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCCNTSEED0 to value 0"]
impl crate :: Resettable for Dcccntseed0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCVALIDSEED0 (rw) register accessor: Seed value for the timeout counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dccvalidseed0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccvalidseed0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccvalidseed0`]
module"]
# [doc (alias = "DCCVALIDSEED0")]
pub type Dccvalidseed0 = crate :: Reg < dccvalidseed0 :: Dccvalidseed0Spec > ; # [doc = "Seed value for the timeout counter attached to clock source 0"]
pub mod dccvalidseed0 { # [doc = "Register `DCCVALIDSEED0` reader"]
pub type R = crate :: R < Dccvalidseed0Spec > ; # [doc = "Register `DCCVALIDSEED0` writer"]
pub type W = crate :: W < Dccvalidseed0Spec > ; # [doc = "Field `VALIDSEED0` reader - 15:0\\]
The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"]
pub type Validseed0R = crate :: FieldReader < u16 > ; # [doc = "Field `VALIDSEED0` writer - 15:0\\]
The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"]
pub type Validseed0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU4` reader - 31:16\\]
Reserved"]
pub type Nu4R = crate :: FieldReader < u16 > ; # [doc = "Field `NU4` writer - 31:16\\]
Reserved"]
pub type Nu4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"]
# [inline (always)]
pub fn validseed0 (& self) -> Validseed0R { Validseed0R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"]
# [inline (always)]
# [must_use]
pub fn validseed0 (& mut self) -> Validseed0W < Dccvalidseed0Spec > { Validseed0W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < Dccvalidseed0Spec > { Nu4W :: new (self , 16) } } # [doc = "Seed value for the timeout counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dccvalidseed0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccvalidseed0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dccvalidseed0Spec ; impl crate :: RegisterSpec for Dccvalidseed0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccvalidseed0::R`](R) reader structure"]
impl crate :: Readable for Dccvalidseed0Spec { } # [doc = "`write(|w| ..)` method takes [`dccvalidseed0::W`](W) writer structure"]
impl crate :: Writable for Dccvalidseed0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCVALIDSEED0 to value 0"]
impl crate :: Resettable for Dccvalidseed0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCCNTSEED1 (rw) register accessor: Seed value for the counter attached to clock source 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccntseed1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccntseed1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcccntseed1`]
module"]
# [doc (alias = "DCCCNTSEED1")]
pub type Dcccntseed1 = crate :: Reg < dcccntseed1 :: Dcccntseed1Spec > ; # [doc = "Seed value for the counter attached to clock source 1"]
pub mod dcccntseed1 { # [doc = "Register `DCCCNTSEED1` reader"]
pub type R = crate :: R < Dcccntseed1Spec > ; # [doc = "Register `DCCCNTSEED1` writer"]
pub type W = crate :: W < Dcccntseed1Spec > ; # [doc = "Field `COUNTSEED1` reader - 19:0\\]
The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"]
pub type Countseed1R = crate :: FieldReader < u32 > ; # [doc = "Field `COUNTSEED1` writer - 19:0\\]
The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"]
pub type Countseed1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `NU5` reader - 31:20\\]
Reserved"]
pub type Nu5R = crate :: FieldReader < u16 > ; # [doc = "Field `NU5` writer - 31:20\\]
Reserved"]
pub type Nu5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"]
# [inline (always)]
pub fn countseed1 (& self) -> Countseed1R { Countseed1R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn nu5 (& self) -> Nu5R { Nu5R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"]
# [inline (always)]
# [must_use]
pub fn countseed1 (& mut self) -> Countseed1W < Dcccntseed1Spec > { Countseed1W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu5 (& mut self) -> Nu5W < Dcccntseed1Spec > { Nu5W :: new (self , 20) } } # [doc = "Seed value for the counter attached to clock source 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccntseed1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccntseed1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcccntseed1Spec ; impl crate :: RegisterSpec for Dcccntseed1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcccntseed1::R`](R) reader structure"]
impl crate :: Readable for Dcccntseed1Spec { } # [doc = "`write(|w| ..)` method takes [`dcccntseed1::W`](W) writer structure"]
impl crate :: Writable for Dcccntseed1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCCNTSEED1 to value 0"]
impl crate :: Resettable for Dcccntseed1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCSTAT (rw) register accessor: Contains the error &amp; done flag bit\n\nYou can [`read`](crate::Reg::read) this register and get [`dccstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccstat`]
module"]
# [doc (alias = "DCCSTAT")]
pub type Dccstat = crate :: Reg < dccstat :: DccstatSpec > ; # [doc = "Contains the error &amp; done flag bit"]
pub mod dccstat { # [doc = "Register `DCCSTAT` reader"]
pub type R = crate :: R < DccstatSpec > ; # [doc = "Register `DCCSTAT` writer"]
pub type W = crate :: W < DccstatSpec > ; # [doc = "Field `ERR` reader - 0:0\\]
Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag."]
pub type ErrR = crate :: BitReader ; # [doc = "Field `ERR` writer - 0:0\\]
Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag."]
pub type ErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DONE` reader - 1:1\\]
Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag."]
pub type DoneR = crate :: BitReader ; # [doc = "Field `DONE` writer - 1:1\\]
Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag."]
pub type DoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU6` reader - 31:2\\]
Reserved"]
pub type Nu6R = crate :: FieldReader < u32 > ; # [doc = "Field `NU6` writer - 31:2\\]
Reserved"]
pub type Nu6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag."]
# [inline (always)]
pub fn err (& self) -> ErrR { ErrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag."]
# [inline (always)]
pub fn done (& self) -> DoneR { DoneR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu6 (& self) -> Nu6R { Nu6R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag."]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ErrW < DccstatSpec > { ErrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag."]
# [inline (always)]
# [must_use]
pub fn done (& mut self) -> DoneW < DccstatSpec > { DoneW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu6 (& mut self) -> Nu6W < DccstatSpec > { Nu6W :: new (self , 2) } } # [doc = "Contains the error &amp; done flag bit\n\nYou can [`read`](crate::Reg::read) this register and get [`dccstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DccstatSpec ; impl crate :: RegisterSpec for DccstatSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccstat::R`](R) reader structure"]
impl crate :: Readable for DccstatSpec { } # [doc = "`write(|w| ..)` method takes [`dccstat::W`](W) writer structure"]
impl crate :: Writable for DccstatSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCSTAT to value 0"]
impl crate :: Resettable for DccstatSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCCNT0 (rw) register accessor: Value of the counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcccnt0`]
module"]
# [doc (alias = "DCCCNT0")]
pub type Dcccnt0 = crate :: Reg < dcccnt0 :: Dcccnt0Spec > ; # [doc = "Value of the counter attached to clock source 0"]
pub mod dcccnt0 { # [doc = "Register `DCCCNT0` reader"]
pub type R = crate :: R < Dcccnt0Spec > ; # [doc = "Register `DCCCNT0` writer"]
pub type W = crate :: W < Dcccnt0Spec > ; # [doc = "Field `COUNT0` reader - 19:0\\]
This field contains the current value of counter 0. - (RO )"]
pub type Count0R = crate :: FieldReader < u32 > ; # [doc = "Field `COUNT0` writer - 19:0\\]
This field contains the current value of counter 0. - (RO )"]
pub type Count0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `NU7` reader - 31:20\\]
Reserved"]
pub type Nu7R = crate :: FieldReader < u16 > ; # [doc = "Field `NU7` writer - 31:20\\]
Reserved"]
pub type Nu7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
This field contains the current value of counter 0. - (RO )"]
# [inline (always)]
pub fn count0 (& self) -> Count0R { Count0R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn nu7 (& self) -> Nu7R { Nu7R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
This field contains the current value of counter 0. - (RO )"]
# [inline (always)]
# [must_use]
pub fn count0 (& mut self) -> Count0W < Dcccnt0Spec > { Count0W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu7 (& mut self) -> Nu7W < Dcccnt0Spec > { Nu7W :: new (self , 20) } } # [doc = "Value of the counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcccnt0Spec ; impl crate :: RegisterSpec for Dcccnt0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcccnt0::R`](R) reader structure"]
impl crate :: Readable for Dcccnt0Spec { } # [doc = "`write(|w| ..)` method takes [`dcccnt0::W`](W) writer structure"]
impl crate :: Writable for Dcccnt0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCCNT0 to value 0"]
impl crate :: Resettable for Dcccnt0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCVALID0 (rw) register accessor: Value of the valid counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dccvalid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccvalid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccvalid0`]
module"]
# [doc (alias = "DCCVALID0")]
pub type Dccvalid0 = crate :: Reg < dccvalid0 :: Dccvalid0Spec > ; # [doc = "Value of the valid counter attached to clock source 0"]
pub mod dccvalid0 { # [doc = "Register `DCCVALID0` reader"]
pub type R = crate :: R < Dccvalid0Spec > ; # [doc = "Register `DCCVALID0` writer"]
pub type W = crate :: W < Dccvalid0Spec > ; # [doc = "Field `VALID0` reader - 15:0\\]
This field contains the current value of valid counter 0. - (RO )"]
pub type Valid0R = crate :: FieldReader < u16 > ; # [doc = "Field `VALID0` writer - 15:0\\]
This field contains the current value of valid counter 0. - (RO )"]
pub type Valid0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU8` reader - 31:16\\]
Reserved"]
pub type Nu8R = crate :: FieldReader < u16 > ; # [doc = "Field `NU8` writer - 31:16\\]
Reserved"]
pub type Nu8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
This field contains the current value of valid counter 0. - (RO )"]
# [inline (always)]
pub fn valid0 (& self) -> Valid0R { Valid0R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu8 (& self) -> Nu8R { Nu8R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
This field contains the current value of valid counter 0. - (RO )"]
# [inline (always)]
# [must_use]
pub fn valid0 (& mut self) -> Valid0W < Dccvalid0Spec > { Valid0W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu8 (& mut self) -> Nu8W < Dccvalid0Spec > { Nu8W :: new (self , 16) } } # [doc = "Value of the valid counter attached to clock source 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dccvalid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccvalid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dccvalid0Spec ; impl crate :: RegisterSpec for Dccvalid0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccvalid0::R`](R) reader structure"]
impl crate :: Readable for Dccvalid0Spec { } # [doc = "`write(|w| ..)` method takes [`dccvalid0::W`](W) writer structure"]
impl crate :: Writable for Dccvalid0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCVALID0 to value 0"]
impl crate :: Resettable for Dccvalid0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCCNT1 (rw) register accessor: Value of the counter attached to clock source 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcccnt1`]
module"]
# [doc (alias = "DCCCNT1")]
pub type Dcccnt1 = crate :: Reg < dcccnt1 :: Dcccnt1Spec > ; # [doc = "Value of the counter attached to clock source 1"]
pub mod dcccnt1 { # [doc = "Register `DCCCNT1` reader"]
pub type R = crate :: R < Dcccnt1Spec > ; # [doc = "Register `DCCCNT1` writer"]
pub type W = crate :: W < Dcccnt1Spec > ; # [doc = "Field `COUNT1` reader - 19:0\\]
This field contains the current value of counter 1. - (RO )"]
pub type Count1R = crate :: FieldReader < u32 > ; # [doc = "Field `COUNT1` writer - 19:0\\]
This field contains the current value of counter 1. - (RO )"]
pub type Count1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; # [doc = "Field `NU9` reader - 31:20\\]
Reserved"]
pub type Nu9R = crate :: FieldReader < u16 > ; # [doc = "Field `NU9` writer - 31:20\\]
Reserved"]
pub type Nu9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:19 - 19:0\\]
This field contains the current value of counter 1. - (RO )"]
# [inline (always)]
pub fn count1 (& self) -> Count1R { Count1R :: new (self . bits & 0x000f_ffff) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn nu9 (& self) -> Nu9R { Nu9R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:19 - 19:0\\]
This field contains the current value of counter 1. - (RO )"]
# [inline (always)]
# [must_use]
pub fn count1 (& mut self) -> Count1W < Dcccnt1Spec > { Count1W :: new (self , 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu9 (& mut self) -> Nu9W < Dcccnt1Spec > { Nu9W :: new (self , 20) } } # [doc = "Value of the counter attached to clock source 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dcccnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcccnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dcccnt1Spec ; impl crate :: RegisterSpec for Dcccnt1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcccnt1::R`](R) reader structure"]
impl crate :: Readable for Dcccnt1Spec { } # [doc = "`write(|w| ..)` method takes [`dcccnt1::W`](W) writer structure"]
impl crate :: Writable for Dcccnt1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCCNT1 to value 0"]
impl crate :: Resettable for Dcccnt1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCCLKSSRC1 (rw) register accessor: Clock source1 selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`dccclkssrc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccclkssrc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccclkssrc1`]
module"]
# [doc (alias = "DCCCLKSSRC1")]
pub type Dccclkssrc1 = crate :: Reg < dccclkssrc1 :: Dccclkssrc1Spec > ; # [doc = "Clock source1 selection control"]
pub mod dccclkssrc1 { # [doc = "Register `DCCCLKSSRC1` reader"]
pub type R = crate :: R < Dccclkssrc1Spec > ; # [doc = "Register `DCCCLKSSRC1` writer"]
pub type W = crate :: W < Dccclkssrc1Spec > ; # [doc = "Field `CLK_SRC1` reader - 3:0\\]
RCOSC Input1_clksrc\\[10\\]
CANFD_GCM Input1_clksrc\\[9\\]
APPSS_GCM Input1_clksrc\\[8\\]
OSC_CLK Input1_clksrc\\[7\\]
LIN_CLK Input1_clksrc\\[6\\]
MDLL_CLK Input1_clksrc\\[5\\]
SYNTH_CLK Input1_clksrc\\[4\\]
RAMPGEN/DFE CLK Input1_clksrc\\[3\\]
GPADC CLK Input1_clksrc\\[2\\]
FECSS_GCM Input1_clksrc\\[1\\]
fast_clk(muxed apll and pll_dig_clk )(root mux) Input1_clksrc\\[0\\]"]
pub type ClkSrc1R = crate :: FieldReader ; # [doc = "Field `CLK_SRC1` writer - 3:0\\]
RCOSC Input1_clksrc\\[10\\]
CANFD_GCM Input1_clksrc\\[9\\]
APPSS_GCM Input1_clksrc\\[8\\]
OSC_CLK Input1_clksrc\\[7\\]
LIN_CLK Input1_clksrc\\[6\\]
MDLL_CLK Input1_clksrc\\[5\\]
SYNTH_CLK Input1_clksrc\\[4\\]
RAMPGEN/DFE CLK Input1_clksrc\\[3\\]
GPADC CLK Input1_clksrc\\[2\\]
FECSS_GCM Input1_clksrc\\[1\\]
fast_clk(muxed apll and pll_dig_clk )(root mux) Input1_clksrc\\[0\\]"]
pub type ClkSrc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU10` reader - 11:4\\]
Reserved"]
pub type Nu10R = crate :: FieldReader ; # [doc = "Field `NU10` writer - 11:4\\]
Reserved"]
pub type Nu10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `KEY_B4` reader - 15:12\\]
Key Programing (1010 is the KEY Value)"]
pub type KeyB4R = crate :: FieldReader ; # [doc = "Field `KEY_B4` writer - 15:12\\]
Key Programing (1010 is the KEY Value)"]
pub type KeyB4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU11` reader - 31:16\\]
Reserved"]
pub type Nu11R = crate :: FieldReader < u16 > ; # [doc = "Field `NU11` writer - 31:16\\]
Reserved"]
pub type Nu11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
RCOSC Input1_clksrc\\[10\\]
CANFD_GCM Input1_clksrc\\[9\\]
APPSS_GCM Input1_clksrc\\[8\\]
OSC_CLK Input1_clksrc\\[7\\]
LIN_CLK Input1_clksrc\\[6\\]
MDLL_CLK Input1_clksrc\\[5\\]
SYNTH_CLK Input1_clksrc\\[4\\]
RAMPGEN/DFE CLK Input1_clksrc\\[3\\]
GPADC CLK Input1_clksrc\\[2\\]
FECSS_GCM Input1_clksrc\\[1\\]
fast_clk(muxed apll and pll_dig_clk )(root mux) Input1_clksrc\\[0\\]"]
# [inline (always)]
pub fn clk_src1 (& self) -> ClkSrc1R { ClkSrc1R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Reserved"]
# [inline (always)]
pub fn nu10 (& self) -> Nu10R { Nu10R :: new (((self . bits >> 4) & 0xff) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Key Programing (1010 is the KEY Value)"]
# [inline (always)]
pub fn key_b4 (& self) -> KeyB4R { KeyB4R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu11 (& self) -> Nu11R { Nu11R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
RCOSC Input1_clksrc\\[10\\]
CANFD_GCM Input1_clksrc\\[9\\]
APPSS_GCM Input1_clksrc\\[8\\]
OSC_CLK Input1_clksrc\\[7\\]
LIN_CLK Input1_clksrc\\[6\\]
MDLL_CLK Input1_clksrc\\[5\\]
SYNTH_CLK Input1_clksrc\\[4\\]
RAMPGEN/DFE CLK Input1_clksrc\\[3\\]
GPADC CLK Input1_clksrc\\[2\\]
FECSS_GCM Input1_clksrc\\[1\\]
fast_clk(muxed apll and pll_dig_clk )(root mux) Input1_clksrc\\[0\\]"]
# [inline (always)]
# [must_use]
pub fn clk_src1 (& mut self) -> ClkSrc1W < Dccclkssrc1Spec > { ClkSrc1W :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu10 (& mut self) -> Nu10W < Dccclkssrc1Spec > { Nu10W :: new (self , 4) } # [doc = "Bits 12:15 - 15:12\\]
Key Programing (1010 is the KEY Value)"]
# [inline (always)]
# [must_use]
pub fn key_b4 (& mut self) -> KeyB4W < Dccclkssrc1Spec > { KeyB4W :: new (self , 12) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu11 (& mut self) -> Nu11W < Dccclkssrc1Spec > { Nu11W :: new (self , 16) } } # [doc = "Clock source1 selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`dccclkssrc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccclkssrc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dccclkssrc1Spec ; impl crate :: RegisterSpec for Dccclkssrc1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccclkssrc1::R`](R) reader structure"]
impl crate :: Readable for Dccclkssrc1Spec { } # [doc = "`write(|w| ..)` method takes [`dccclkssrc1::W`](W) writer structure"]
impl crate :: Writable for Dccclkssrc1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCCLKSSRC1 to value 0"]
impl crate :: Resettable for Dccclkssrc1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCCLKSSRC0 (rw) register accessor: Clock source0 selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`dccclkssrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccclkssrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccclkssrc0`]
module"]
# [doc (alias = "DCCCLKSSRC0")]
pub type Dccclkssrc0 = crate :: Reg < dccclkssrc0 :: Dccclkssrc0Spec > ; # [doc = "Clock source0 selection control"]
pub mod dccclkssrc0 { # [doc = "Register `DCCCLKSSRC0` reader"]
pub type R = crate :: R < Dccclkssrc0Spec > ; # [doc = "Register `DCCCLKSSRC0` writer"]
pub type W = crate :: W < Dccclkssrc0Spec > ; # [doc = "Field `CLK_SRC0` reader - 3:0\\]
APLL clock 400MHz Input0_clksrc\\[2\\]
PLL_DIG clock 400MHz Input0_clksrc\\[1\\]
OSC_CLK Input0_clksrc\\[0\\]"]
pub type ClkSrc0R = crate :: FieldReader ; # [doc = "Field `CLK_SRC0` writer - 3:0\\]
APLL clock 400MHz Input0_clksrc\\[2\\]
PLL_DIG clock 400MHz Input0_clksrc\\[1\\]
OSC_CLK Input0_clksrc\\[0\\]"]
pub type ClkSrc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU12` reader - 11:4\\]
Reserved"]
pub type Nu12R = crate :: FieldReader ; # [doc = "Field `NU12` writer - 11:4\\]
Reserved"]
pub type Nu12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `KEY_B4` reader - 15:12\\]
Key Programing (1010 is the KEY Value)"]
pub type KeyB4R = crate :: FieldReader ; # [doc = "Field `KEY_B4` writer - 15:12\\]
Key Programing (1010 is the KEY Value)"]
pub type KeyB4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU13` reader - 31:16\\]
Reserved"]
pub type Nu13R = crate :: FieldReader < u16 > ; # [doc = "Field `NU13` writer - 31:16\\]
Reserved"]
pub type Nu13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
APLL clock 400MHz Input0_clksrc\\[2\\]
PLL_DIG clock 400MHz Input0_clksrc\\[1\\]
OSC_CLK Input0_clksrc\\[0\\]"]
# [inline (always)]
pub fn clk_src0 (& self) -> ClkSrc0R { ClkSrc0R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:11 - 11:4\\]
Reserved"]
# [inline (always)]
pub fn nu12 (& self) -> Nu12R { Nu12R :: new (((self . bits >> 4) & 0xff) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Key Programing (1010 is the KEY Value)"]
# [inline (always)]
pub fn key_b4 (& self) -> KeyB4R { KeyB4R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu13 (& self) -> Nu13R { Nu13R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
APLL clock 400MHz Input0_clksrc\\[2\\]
PLL_DIG clock 400MHz Input0_clksrc\\[1\\]
OSC_CLK Input0_clksrc\\[0\\]"]
# [inline (always)]
# [must_use]
pub fn clk_src0 (& mut self) -> ClkSrc0W < Dccclkssrc0Spec > { ClkSrc0W :: new (self , 0) } # [doc = "Bits 4:11 - 11:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu12 (& mut self) -> Nu12W < Dccclkssrc0Spec > { Nu12W :: new (self , 4) } # [doc = "Bits 12:15 - 15:12\\]
Key Programing (1010 is the KEY Value)"]
# [inline (always)]
# [must_use]
pub fn key_b4 (& mut self) -> KeyB4W < Dccclkssrc0Spec > { KeyB4W :: new (self , 12) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu13 (& mut self) -> Nu13W < Dccclkssrc0Spec > { Nu13W :: new (self , 16) } } # [doc = "Clock source0 selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`dccclkssrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccclkssrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dccclkssrc0Spec ; impl crate :: RegisterSpec for Dccclkssrc0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccclkssrc0::R`](R) reader structure"]
impl crate :: Readable for Dccclkssrc0Spec { } # [doc = "`write(|w| ..)` method takes [`dccclkssrc0::W`](W) writer structure"]
impl crate :: Writable for Dccclkssrc0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCCLKSSRC0 to value 0"]
impl crate :: Resettable for Dccclkssrc0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCGCTRL2 (rw) register accessor: Global control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dccgctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccgctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccgctrl2`]
module"]
# [doc (alias = "DCCGCTRL2")]
pub type Dccgctrl2 = crate :: Reg < dccgctrl2 :: Dccgctrl2Spec > ; # [doc = "Global control register 2"]
pub mod dccgctrl2 { # [doc = "Register `DCCGCTRL2` reader"]
pub type R = crate :: R < Dccgctrl2Spec > ; # [doc = "Register `DCCGCTRL2` writer"]
pub type W = crate :: W < Dccgctrl2Spec > ; # [doc = "Field `CONT_ON_ERR` reader - 3:0\\]
Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue counting despite the error condition. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
pub type ContOnErrR = crate :: FieldReader ; # [doc = "Field `CONT_ON_ERR` writer - 3:0\\]
Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue counting despite the error condition. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
pub type ContOnErrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `FIFO_READ` reader - 7:4\\]
FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
pub type FifoReadR = crate :: FieldReader ; # [doc = "Field `FIFO_READ` writer - 7:4\\]
FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
pub type FifoReadW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `FIFO_NONERR` reader - 11:8\\]
FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon completion of comparison window regardless of error or not. Note this setting is applicable only in Continuous mode; in single shot mode FIFO captures counts only on Error. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
pub type FifoNonerrR = crate :: FieldReader ; # [doc = "Field `FIFO_NONERR` writer - 11:8\\]
FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon completion of comparison window regardless of error or not. Note this setting is applicable only in Continuous mode; in single shot mode FIFO captures counts only on Error. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
pub type FifoNonerrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU13` reader - "]
pub type Nu13R = crate :: FieldReader < u32 > ; # [doc = "Field `NU13` writer - "]
pub type Nu13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue counting despite the error condition. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
# [inline (always)]
pub fn cont_on_err (& self) -> ContOnErrR { ContOnErrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
# [inline (always)]
pub fn fifo_read (& self) -> FifoReadR { FifoReadR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon completion of comparison window regardless of error or not. Note this setting is applicable only in Continuous mode; in single shot mode FIFO captures counts only on Error. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
# [inline (always)]
pub fn fifo_nonerr (& self) -> FifoNonerrR { FifoNonerrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:31"]
# [inline (always)]
pub fn nu13 (& self) -> Nu13R { Nu13R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue counting despite the error condition. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
# [inline (always)]
# [must_use]
pub fn cont_on_err (& mut self) -> ContOnErrW < Dccgctrl2Spec > { ContOnErrW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
# [inline (always)]
# [must_use]
pub fn fifo_read (& mut self) -> FifoReadW < Dccgctrl2Spec > { FifoReadW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon completion of comparison window regardless of error or not. Note this setting is applicable only in Continuous mode; in single shot mode FIFO captures counts only on Error. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors."]
# [inline (always)]
# [must_use]
pub fn fifo_nonerr (& mut self) -> FifoNonerrW < Dccgctrl2Spec > { FifoNonerrW :: new (self , 8) } # [doc = "Bits 12:31"]
# [inline (always)]
# [must_use]
pub fn nu13 (& mut self) -> Nu13W < Dccgctrl2Spec > { Nu13W :: new (self , 12) } } # [doc = "Global control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dccgctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccgctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dccgctrl2Spec ; impl crate :: RegisterSpec for Dccgctrl2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccgctrl2::R`](R) reader structure"]
impl crate :: Readable for Dccgctrl2Spec { } # [doc = "`write(|w| ..)` method takes [`dccgctrl2::W`](W) writer structure"]
impl crate :: Writable for Dccgctrl2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCGCTRL2 to value 0"]
impl crate :: Resettable for Dccgctrl2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCSTATUS2 (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dccstatus2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccstatus2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccstatus2`]
module"]
# [doc (alias = "DCCSTATUS2")]
pub type Dccstatus2 = crate :: Reg < dccstatus2 :: Dccstatus2Spec > ; # [doc = "FIFO status register"]
pub mod dccstatus2 { # [doc = "Register `DCCSTATUS2` reader"]
pub type R = crate :: R < Dccstatus2Spec > ; # [doc = "Register `DCCSTATUS2` writer"]
pub type W = crate :: W < Dccstatus2Spec > ; # [doc = "Field `COUNT0_FIFO_EMPTY` reader - 0:0\\]
Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty."]
pub type Count0FifoEmptyR = crate :: BitReader ; # [doc = "Field `COUNT0_FIFO_EMPTY` writer - 0:0\\]
Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty."]
pub type Count0FifoEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VALID0_FIFO_EMPTY` reader - 1:1\\]
Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty."]
pub type Valid0FifoEmptyR = crate :: BitReader ; # [doc = "Field `VALID0_FIFO_EMPTY` writer - 1:1\\]
Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty."]
pub type Valid0FifoEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COUNT1_FIFO_EMPTY` reader - 2:2\\]
Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty."]
pub type Count1FifoEmptyR = crate :: BitReader ; # [doc = "Field `COUNT1_FIFO_EMPTY` writer - 2:2\\]
Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty."]
pub type Count1FifoEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COUNT0_FIFO_FULL` reader - 3:3\\]
Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full."]
pub type Count0FifoFullR = crate :: BitReader ; # [doc = "Field `COUNT0_FIFO_FULL` writer - 3:3\\]
Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full."]
pub type Count0FifoFullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `VALID0_FIFO_FULL` reader - 4:4\\]
Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full."]
pub type Valid0FifoFullR = crate :: BitReader ; # [doc = "Field `VALID0_FIFO_FULL` writer - 4:4\\]
Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full."]
pub type Valid0FifoFullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COUNT1_FIFO_FULL` reader - 5:5\\]
Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full."]
pub type Count1FifoFullR = crate :: BitReader ; # [doc = "Field `COUNT1_FIFO_FULL` writer - 5:5\\]
Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full."]
pub type Count1FifoFullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU14` reader - 31:6\\]
Reserved"]
pub type Nu14R = crate :: FieldReader < u32 > ; # [doc = "Field `NU14` writer - 31:6\\]
Reserved"]
pub type Nu14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty."]
# [inline (always)]
pub fn count0_fifo_empty (& self) -> Count0FifoEmptyR { Count0FifoEmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty."]
# [inline (always)]
pub fn valid0_fifo_empty (& self) -> Valid0FifoEmptyR { Valid0FifoEmptyR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty."]
# [inline (always)]
pub fn count1_fifo_empty (& self) -> Count1FifoEmptyR { Count1FifoEmptyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full."]
# [inline (always)]
pub fn count0_fifo_full (& self) -> Count0FifoFullR { Count0FifoFullR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full."]
# [inline (always)]
pub fn valid0_fifo_full (& self) -> Valid0FifoFullR { Valid0FifoFullR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full."]
# [inline (always)]
pub fn count1_fifo_full (& self) -> Count1FifoFullR { Count1FifoFullR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu14 (& self) -> Nu14R { Nu14R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty."]
# [inline (always)]
# [must_use]
pub fn count0_fifo_empty (& mut self) -> Count0FifoEmptyW < Dccstatus2Spec > { Count0FifoEmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty."]
# [inline (always)]
# [must_use]
pub fn valid0_fifo_empty (& mut self) -> Valid0FifoEmptyW < Dccstatus2Spec > { Valid0FifoEmptyW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty."]
# [inline (always)]
# [must_use]
pub fn count1_fifo_empty (& mut self) -> Count1FifoEmptyW < Dccstatus2Spec > { Count1FifoEmptyW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full."]
# [inline (always)]
# [must_use]
pub fn count0_fifo_full (& mut self) -> Count0FifoFullW < Dccstatus2Spec > { Count0FifoFullW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full."]
# [inline (always)]
# [must_use]
pub fn valid0_fifo_full (& mut self) -> Valid0FifoFullW < Dccstatus2Spec > { Valid0FifoFullW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full."]
# [inline (always)]
# [must_use]
pub fn count1_fifo_full (& mut self) -> Count1FifoFullW < Dccstatus2Spec > { Count1FifoFullW :: new (self , 5) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu14 (& mut self) -> Nu14W < Dccstatus2Spec > { Nu14W :: new (self , 6) } } # [doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dccstatus2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccstatus2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dccstatus2Spec ; impl crate :: RegisterSpec for Dccstatus2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccstatus2::R`](R) reader structure"]
impl crate :: Readable for Dccstatus2Spec { } # [doc = "`write(|w| ..)` method takes [`dccstatus2::W`](W) writer structure"]
impl crate :: Writable for Dccstatus2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCSTATUS2 to value 0"]
impl crate :: Resettable for Dccstatus2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCERRCNT (rw) register accessor: Error count register\n\nYou can [`read`](crate::Reg::read) this register and get [`dccerrcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccerrcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccerrcnt`]
module"]
# [doc (alias = "DCCERRCNT")]
pub type Dccerrcnt = crate :: Reg < dccerrcnt :: DccerrcntSpec > ; # [doc = "Error count register"]
pub mod dccerrcnt { # [doc = "Register `DCCERRCNT` reader"]
pub type R = crate :: R < DccerrcntSpec > ; # [doc = "Register `DCCERRCNT` writer"]
pub type W = crate :: W < DccerrcntSpec > ; # [doc = "Field `ERRCNT` reader - 9:0\\]
Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."]
pub type ErrcntR = crate :: FieldReader < u16 > ; # [doc = "Field `ERRCNT` writer - 9:0\\]
Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."]
pub type ErrcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU15` reader - 31:10\\]
Reserved"]
pub type Nu15R = crate :: FieldReader < u32 > ; # [doc = "Field `NU15` writer - 31:10\\]
Reserved"]
pub type Nu15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."]
# [inline (always)]
pub fn errcnt (& self) -> ErrcntR { ErrcntR :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:31 - 31:10\\]
Reserved"]
# [inline (always)]
pub fn nu15 (& self) -> Nu15R { Nu15R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."]
# [inline (always)]
# [must_use]
pub fn errcnt (& mut self) -> ErrcntW < DccerrcntSpec > { ErrcntW :: new (self , 0) } # [doc = "Bits 10:31 - 31:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu15 (& mut self) -> Nu15W < DccerrcntSpec > { Nu15W :: new (self , 10) } } # [doc = "Error count register\n\nYou can [`read`](crate::Reg::read) this register and get [`dccerrcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccerrcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DccerrcntSpec ; impl crate :: RegisterSpec for DccerrcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccerrcnt::R`](R) reader structure"]
impl crate :: Readable for DccerrcntSpec { } # [doc = "`write(|w| ..)` method takes [`dccerrcnt::W`](W) writer structure"]
impl crate :: Writable for DccerrcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCERRCNT to value 0"]
impl crate :: Resettable for DccerrcntSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_ESM"]
pub struct AppEsm { _marker : PhantomData < * const () > } unsafe impl Send for AppEsm { } impl AppEsm { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_esm :: RegisterBlock = 0x56f7_fc00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_esm :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppEsm { type Target = app_esm :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppEsm { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppEsm") . finish () } } # [doc = "APP_ESM"]
pub mod app_esm { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { esmiepsr1 : Esmiepsr1 , esmiepcr1 : Esmiepcr1 , esmiesr1 : Esmiesr1 , esmiecr1 : Esmiecr1 , esmilsr1 : Esmilsr1 , esmilcr1 : Esmilcr1 , esmsr1 : Esmsr1 , esmsr2 : Esmsr2 , esmsr3 : Esmsr3 , esmepsr : Esmepsr , esmioffhr : Esmioffhr , esmiofflr : Esmiofflr , esmltcr : Esmltcr , esmltcpr : Esmltcpr , esmekr : Esmekr , esmssr2 : Esmssr2 , esmiepsr4 : Esmiepsr4 , esmiepcr4 : Esmiepcr4 , esmiesr4 : Esmiesr4 , esmiecr4 : Esmiecr4 , esmilsr4 : Esmilsr4 , esmilcr4 : Esmilcr4 , esmsr4 : Esmsr4 , _reserved23 : [u8 ; 0x24]
, esmiepsr7 : Esmiepsr7 , esmiepcr7 : Esmiepcr7 , esmiesr7 : Esmiesr7 , esmiecr7 : Esmiecr7 , esmilsr7 : Esmilsr7 , esmilcr7 : Esmilcr7 , esmsr7 : Esmsr7 , _reserved30 : [u8 ; 0x24]
, esmiepsr10 : Esmiepsr10 , esmiepcr10 : Esmiepcr10 , esmiesr10 : Esmiesr10 , esmiecr10 : Esmiecr10 , esmilsr10 : Esmilsr10 , esmilcr10 : Esmilcr10 , esmsr10 : Esmsr10 , } impl RegisterBlock { # [doc = "0x00 - ESM Enable ERROR Pin Action/Response Register 1"]
# [inline (always)]
pub const fn esmiepsr1 (& self) -> & Esmiepsr1 { & self . esmiepsr1 } # [doc = "0x04 - ESM Disable ERROR Pin Action/Response Register 1"]
# [inline (always)]
pub const fn esmiepcr1 (& self) -> & Esmiepcr1 { & self . esmiepcr1 } # [doc = "0x08 - ESM Interrupt Enable Set/Status Register 1"]
# [inline (always)]
pub const fn esmiesr1 (& self) -> & Esmiesr1 { & self . esmiesr1 } # [doc = "0x0c - ESM Interrupt Enable Clear/Status Register 1"]
# [inline (always)]
pub const fn esmiecr1 (& self) -> & Esmiecr1 { & self . esmiecr1 } # [doc = "0x10 - Interrupt Level Set/Status Register 1"]
# [inline (always)]
pub const fn esmilsr1 (& self) -> & Esmilsr1 { & self . esmilsr1 } # [doc = "0x14 - Interrupt Level Clear/Status Register 1"]
# [inline (always)]
pub const fn esmilcr1 (& self) -> & Esmilcr1 { & self . esmilcr1 } # [doc = "0x18 - ESM Status Register 1"]
# [inline (always)]
pub const fn esmsr1 (& self) -> & Esmsr1 { & self . esmsr1 } # [doc = "0x1c - ESM Status Register 2"]
# [inline (always)]
pub const fn esmsr2 (& self) -> & Esmsr2 { & self . esmsr2 } # [doc = "0x20 - ESM Status Register 3"]
# [inline (always)]
pub const fn esmsr3 (& self) -> & Esmsr3 { & self . esmsr3 } # [doc = "0x24 - ESM ERROR Pin Status Register"]
# [inline (always)]
pub const fn esmepsr (& self) -> & Esmepsr { & self . esmepsr } # [doc = "0x28 - ESM Interrupt Offset High Register"]
# [inline (always)]
pub const fn esmioffhr (& self) -> & Esmioffhr { & self . esmioffhr } # [doc = "0x2c - ESM Interrupt Offset Low Register"]
# [inline (always)]
pub const fn esmiofflr (& self) -> & Esmiofflr { & self . esmiofflr } # [doc = "0x30 - ESM Low-Time Counter Register"]
# [inline (always)]
pub const fn esmltcr (& self) -> & Esmltcr { & self . esmltcr } # [doc = "0x34 - ESM Low-Time Counter Preload Register"]
# [inline (always)]
pub const fn esmltcpr (& self) -> & Esmltcpr { & self . esmltcpr } # [doc = "0x38 - ESM Error Key Register"]
# [inline (always)]
pub const fn esmekr (& self) -> & Esmekr { & self . esmekr } # [doc = "0x3c - ESM Status Shadow Register 2"]
# [inline (always)]
pub const fn esmssr2 (& self) -> & Esmssr2 { & self . esmssr2 } # [doc = "0x40 - ESM Enable ERROR Pin Action/Response Register 4"]
# [inline (always)]
pub const fn esmiepsr4 (& self) -> & Esmiepsr4 { & self . esmiepsr4 } # [doc = "0x44 - ESM Disable ERROR Pin Action/Response Register 4"]
# [inline (always)]
pub const fn esmiepcr4 (& self) -> & Esmiepcr4 { & self . esmiepcr4 } # [doc = "0x48 - ESM Interrupt Enable Set/Status Register 4"]
# [inline (always)]
pub const fn esmiesr4 (& self) -> & Esmiesr4 { & self . esmiesr4 } # [doc = "0x4c - ESM Interrupt Enable Clear/Status Register 4"]
# [inline (always)]
pub const fn esmiecr4 (& self) -> & Esmiecr4 { & self . esmiecr4 } # [doc = "0x50 - Interrupt Level Set/Status Register 4"]
# [inline (always)]
pub const fn esmilsr4 (& self) -> & Esmilsr4 { & self . esmilsr4 } # [doc = "0x54 - Interrupt Level Clear/Status Register 4"]
# [inline (always)]
pub const fn esmilcr4 (& self) -> & Esmilcr4 { & self . esmilcr4 } # [doc = "0x58 - ESM Status Register 4"]
# [inline (always)]
pub const fn esmsr4 (& self) -> & Esmsr4 { & self . esmsr4 } # [doc = "0x80 - ESM Enable ERROR Pin Action/Response Register 7"]
# [inline (always)]
pub const fn esmiepsr7 (& self) -> & Esmiepsr7 { & self . esmiepsr7 } # [doc = "0x84 - ESM Disable ERROR Pin Action/Response Register 7"]
# [inline (always)]
pub const fn esmiepcr7 (& self) -> & Esmiepcr7 { & self . esmiepcr7 } # [doc = "0x88 - ESM Interrupt Enable Set/Status Register 7"]
# [inline (always)]
pub const fn esmiesr7 (& self) -> & Esmiesr7 { & self . esmiesr7 } # [doc = "0x8c - ESM Interrupt Enable Clear/Status Register 7"]
# [inline (always)]
pub const fn esmiecr7 (& self) -> & Esmiecr7 { & self . esmiecr7 } # [doc = "0x90 - Interrupt Level Set/Status Register 7"]
# [inline (always)]
pub const fn esmilsr7 (& self) -> & Esmilsr7 { & self . esmilsr7 } # [doc = "0x94 - Interrupt Level Clear/Status Register 7"]
# [inline (always)]
pub const fn esmilcr7 (& self) -> & Esmilcr7 { & self . esmilcr7 } # [doc = "0x98 - ESM Status Register 7"]
# [inline (always)]
pub const fn esmsr7 (& self) -> & Esmsr7 { & self . esmsr7 } # [doc = "0xc0 - ESM Enable ERROR Pin Action/Response Register 10"]
# [inline (always)]
pub const fn esmiepsr10 (& self) -> & Esmiepsr10 { & self . esmiepsr10 } # [doc = "0xc4 - ESM Disable ERROR Pin Action/Response Register 10"]
# [inline (always)]
pub const fn esmiepcr10 (& self) -> & Esmiepcr10 { & self . esmiepcr10 } # [doc = "0xc8 - ESM Interrupt Enable Set/Status Register 10"]
# [inline (always)]
pub const fn esmiesr10 (& self) -> & Esmiesr10 { & self . esmiesr10 } # [doc = "0xcc - ESM Interrupt Enable Clear/Status Register 10"]
# [inline (always)]
pub const fn esmiecr10 (& self) -> & Esmiecr10 { & self . esmiecr10 } # [doc = "0xd0 - Interrupt Level Set/Status Register 10"]
# [inline (always)]
pub const fn esmilsr10 (& self) -> & Esmilsr10 { & self . esmilsr10 } # [doc = "0xd4 - Interrupt Level Clear/Status Register 10"]
# [inline (always)]
pub const fn esmilcr10 (& self) -> & Esmilcr10 { & self . esmilcr10 } # [doc = "0xd8 - ESM Status Register 10"]
# [inline (always)]
pub const fn esmsr10 (& self) -> & Esmsr10 { & self . esmsr10 } } # [doc = "ESMIEPSR1 (rw) register accessor: ESM Enable ERROR Pin Action/Response Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepsr1`]
module"]
# [doc (alias = "ESMIEPSR1")]
pub type Esmiepsr1 = crate :: Reg < esmiepsr1 :: Esmiepsr1Spec > ; # [doc = "ESM Enable ERROR Pin Action/Response Register 1"]
pub mod esmiepsr1 { # [doc = "Register `ESMIEPSR1` reader"]
pub type R = crate :: R < Esmiepsr1Spec > ; # [doc = "Register `ESMIEPSR1` writer"]
pub type W = crate :: W < Esmiepsr1Spec > ; # [doc = "Field `IEPSET` reader - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register."]
pub type IepsetR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPSET` writer - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register."]
pub type IepsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register."]
# [inline (always)]
pub fn iepset (& self) -> IepsetR { IepsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register."]
# [inline (always)]
# [must_use]
pub fn iepset (& mut self) -> IepsetW < Esmiepsr1Spec > { IepsetW :: new (self , 0) } } # [doc = "ESM Enable ERROR Pin Action/Response Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepsr1Spec ; impl crate :: RegisterSpec for Esmiepsr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepsr1::R`](R) reader structure"]
impl crate :: Readable for Esmiepsr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepsr1::W`](W) writer structure"]
impl crate :: Writable for Esmiepsr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPSR1 to value 0"]
impl crate :: Resettable for Esmiepsr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPCR1 (rw) register accessor: ESM Disable ERROR Pin Action/Response Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepcr1`]
module"]
# [doc (alias = "ESMIEPCR1")]
pub type Esmiepcr1 = crate :: Reg < esmiepcr1 :: Esmiepcr1Spec > ; # [doc = "ESM Disable ERROR Pin Action/Response Register 1"]
pub mod esmiepcr1 { # [doc = "Register `ESMIEPCR1` reader"]
pub type R = crate :: R < Esmiepcr1Spec > ; # [doc = "Register `ESMIEPCR1` writer"]
pub type W = crate :: W < Esmiepcr1Spec > ; # [doc = "Field `IEPCLR` reader - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register."]
pub type IepclrR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPCLR` writer - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register."]
pub type IepclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register."]
# [inline (always)]
pub fn iepclr (& self) -> IepclrR { IepclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register."]
# [inline (always)]
# [must_use]
pub fn iepclr (& mut self) -> IepclrW < Esmiepcr1Spec > { IepclrW :: new (self , 0) } } # [doc = "ESM Disable ERROR Pin Action/Response Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepcr1Spec ; impl crate :: RegisterSpec for Esmiepcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepcr1::R`](R) reader structure"]
impl crate :: Readable for Esmiepcr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepcr1::W`](W) writer structure"]
impl crate :: Writable for Esmiepcr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPCR1 to value 0"]
impl crate :: Resettable for Esmiepcr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIESR1 (rw) register accessor: ESM Interrupt Enable Set/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiesr1`]
module"]
# [doc (alias = "ESMIESR1")]
pub type Esmiesr1 = crate :: Reg < esmiesr1 :: Esmiesr1Spec > ; # [doc = "ESM Interrupt Enable Set/Status Register 1"]
pub mod esmiesr1 { # [doc = "Register `ESMIESR1` reader"]
pub type R = crate :: R < Esmiesr1Spec > ; # [doc = "Register `ESMIESR1` writer"]
pub type W = crate :: W < Esmiesr1Spec > ; # [doc = "Field `INTENSET` reader - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register."]
pub type IntensetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENSET` writer - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register."]
pub type IntensetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register."]
# [inline (always)]
pub fn intenset (& self) -> IntensetR { IntensetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register."]
# [inline (always)]
# [must_use]
pub fn intenset (& mut self) -> IntensetW < Esmiesr1Spec > { IntensetW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Set/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiesr1Spec ; impl crate :: RegisterSpec for Esmiesr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiesr1::R`](R) reader structure"]
impl crate :: Readable for Esmiesr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmiesr1::W`](W) writer structure"]
impl crate :: Writable for Esmiesr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIESR1 to value 0"]
impl crate :: Resettable for Esmiesr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIECR1 (rw) register accessor: ESM Interrupt Enable Clear/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiecr1`]
module"]
# [doc (alias = "ESMIECR1")]
pub type Esmiecr1 = crate :: Reg < esmiecr1 :: Esmiecr1Spec > ; # [doc = "ESM Interrupt Enable Clear/Status Register 1"]
pub mod esmiecr1 { # [doc = "Register `ESMIECR1` reader"]
pub type R = crate :: R < Esmiecr1Spec > ; # [doc = "Register `ESMIECR1` writer"]
pub type W = crate :: W < Esmiecr1Spec > ; # [doc = "Field `INTENCLR` reader - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register."]
pub type IntenclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENCLR` writer - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register."]
pub type IntenclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register."]
# [inline (always)]
pub fn intenclr (& self) -> IntenclrR { IntenclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register."]
# [inline (always)]
# [must_use]
pub fn intenclr (& mut self) -> IntenclrW < Esmiecr1Spec > { IntenclrW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Clear/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiecr1Spec ; impl crate :: RegisterSpec for Esmiecr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiecr1::R`](R) reader structure"]
impl crate :: Readable for Esmiecr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmiecr1::W`](W) writer structure"]
impl crate :: Writable for Esmiecr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIECR1 to value 0"]
impl crate :: Resettable for Esmiecr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILSR1 (rw) register accessor: Interrupt Level Set/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilsr1`]
module"]
# [doc (alias = "ESMILSR1")]
pub type Esmilsr1 = crate :: Reg < esmilsr1 :: Esmilsr1Spec > ; # [doc = "Interrupt Level Set/Status Register 1"]
pub mod esmilsr1 { # [doc = "Register `ESMILSR1` reader"]
pub type R = crate :: R < Esmilsr1Spec > ; # [doc = "Register `ESMILSR1` writer"]
pub type W = crate :: W < Esmilsr1Spec > ; # [doc = "Field `INTLVLSET` reader - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register."]
pub type IntlvlsetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLSET` writer - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register."]
pub type IntlvlsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register."]
# [inline (always)]
pub fn intlvlset (& self) -> IntlvlsetR { IntlvlsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register."]
# [inline (always)]
# [must_use]
pub fn intlvlset (& mut self) -> IntlvlsetW < Esmilsr1Spec > { IntlvlsetW :: new (self , 0) } } # [doc = "Interrupt Level Set/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilsr1Spec ; impl crate :: RegisterSpec for Esmilsr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilsr1::R`](R) reader structure"]
impl crate :: Readable for Esmilsr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmilsr1::W`](W) writer structure"]
impl crate :: Writable for Esmilsr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILSR1 to value 0"]
impl crate :: Resettable for Esmilsr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILCR1 (rw) register accessor: Interrupt Level Clear/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilcr1`]
module"]
# [doc (alias = "ESMILCR1")]
pub type Esmilcr1 = crate :: Reg < esmilcr1 :: Esmilcr1Spec > ; # [doc = "Interrupt Level Clear/Status Register 1"]
pub mod esmilcr1 { # [doc = "Register `ESMILCR1` reader"]
pub type R = crate :: R < Esmilcr1Spec > ; # [doc = "Register `ESMILCR1` writer"]
pub type W = crate :: W < Esmilcr1Spec > ; # [doc = "Field `INTLVLCLR` reader - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR1 register."]
pub type IntlvlclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLCLR` writer - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR1 register."]
pub type IntlvlclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR1 register."]
# [inline (always)]
pub fn intlvlclr (& self) -> IntlvlclrR { IntlvlclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR1 register."]
# [inline (always)]
# [must_use]
pub fn intlvlclr (& mut self) -> IntlvlclrW < Esmilcr1Spec > { IntlvlclrW :: new (self , 0) } } # [doc = "Interrupt Level Clear/Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilcr1Spec ; impl crate :: RegisterSpec for Esmilcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilcr1::R`](R) reader structure"]
impl crate :: Readable for Esmilcr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmilcr1::W`](W) writer structure"]
impl crate :: Writable for Esmilcr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILCR1 to value 0"]
impl crate :: Resettable for Esmilcr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSR1 (rw) register accessor: ESM Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmsr1`]
module"]
# [doc (alias = "ESMSR1")]
pub type Esmsr1 = crate :: Reg < esmsr1 :: Esmsr1Spec > ; # [doc = "ESM Status Register 1"]
pub mod esmsr1 { # [doc = "Register `ESMSR1` reader"]
pub type R = crate :: R < Esmsr1Spec > ; # [doc = "Register `ESMSR1` writer"]
pub type W = crate :: W < Esmsr1Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmsr1Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmsr1Spec ; impl crate :: RegisterSpec for Esmsr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmsr1::R`](R) reader structure"]
impl crate :: Readable for Esmsr1Spec { } # [doc = "`write(|w| ..)` method takes [`esmsr1::W`](W) writer structure"]
impl crate :: Writable for Esmsr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSR1 to value 0"]
impl crate :: Resettable for Esmsr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSR2 (rw) register accessor: ESM Status Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmsr2`]
module"]
# [doc (alias = "ESMSR2")]
pub type Esmsr2 = crate :: Reg < esmsr2 :: Esmsr2Spec > ; # [doc = "ESM Status Register 2"]
pub mod esmsr2 { # [doc = "Register `ESMSR2` reader"]
pub type R = crate :: R < Esmsr2Spec > ; # [doc = "Register `ESMSR2` writer"]
pub type W = crate :: W < Esmsr2Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. ESMSSR2 is not impacted by this action. Note: In normal operation the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. ESMSSR2 is not impacted by this action. Note: In normal operation the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. ESMSSR2 is not impacted by this action. Note: In normal operation the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. ESMSSR2 is not impacted by this action. Note: In normal operation the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmsr2Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmsr2Spec ; impl crate :: RegisterSpec for Esmsr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmsr2::R`](R) reader structure"]
impl crate :: Readable for Esmsr2Spec { } # [doc = "`write(|w| ..)` method takes [`esmsr2::W`](W) writer structure"]
impl crate :: Writable for Esmsr2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSR2 to value 0"]
impl crate :: Resettable for Esmsr2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSR3 (rw) register accessor: ESM Status Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmsr3`]
module"]
# [doc (alias = "ESMSR3")]
pub type Esmsr3 = crate :: Reg < esmsr3 :: Esmsr3Spec > ; # [doc = "ESM Status Register 3"]
pub mod esmsr3 { # [doc = "Register `ESMSR3` reader"]
pub type R = crate :: R < Esmsr3Spec > ; # [doc = "Register `ESMSR3` writer"]
pub type W = crate :: W < Esmsr3Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmsr3Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmsr3Spec ; impl crate :: RegisterSpec for Esmsr3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmsr3::R`](R) reader structure"]
impl crate :: Readable for Esmsr3Spec { } # [doc = "`write(|w| ..)` method takes [`esmsr3::W`](W) writer structure"]
impl crate :: Writable for Esmsr3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSR3 to value 0"]
impl crate :: Resettable for Esmsr3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMEPSR (rw) register accessor: ESM ERROR Pin Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmepsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmepsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmepsr`]
module"]
# [doc (alias = "ESMEPSR")]
pub type Esmepsr = crate :: Reg < esmepsr :: EsmepsrSpec > ; # [doc = "ESM ERROR Pin Status Register"]
pub mod esmepsr { # [doc = "Register `ESMEPSR` reader"]
pub type R = crate :: R < EsmepsrSpec > ; # [doc = "Register `ESMEPSR` writer"]
pub type W = crate :: W < EsmepsrSpec > ; # [doc = "Field `EPSF` reader - 0:0\\]
ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has occurred. Write: Writes have no effect. Note: This flag will be set to 1 after PORRST. The value will be unchanged after nRST. The ERROR pin status remains un-changed during after nRST."]
pub type EpsfR = crate :: BitReader ; # [doc = "Field `EPSF` writer - 0:0\\]
ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has occurred. Write: Writes have no effect. Note: This flag will be set to 1 after PORRST. The value will be unchanged after nRST. The ERROR pin status remains un-changed during after nRST."]
pub type EpsfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has occurred. Write: Writes have no effect. Note: This flag will be set to 1 after PORRST. The value will be unchanged after nRST. The ERROR pin status remains un-changed during after nRST."]
# [inline (always)]
pub fn epsf (& self) -> EpsfR { EpsfR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has occurred. Write: Writes have no effect. Note: This flag will be set to 1 after PORRST. The value will be unchanged after nRST. The ERROR pin status remains un-changed during after nRST."]
# [inline (always)]
# [must_use]
pub fn epsf (& mut self) -> EpsfW < EsmepsrSpec > { EpsfW :: new (self , 0) } } # [doc = "ESM ERROR Pin Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmepsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmepsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmepsrSpec ; impl crate :: RegisterSpec for EsmepsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmepsr::R`](R) reader structure"]
impl crate :: Readable for EsmepsrSpec { } # [doc = "`write(|w| ..)` method takes [`esmepsr::W`](W) writer structure"]
impl crate :: Writable for EsmepsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMEPSR to value 0"]
impl crate :: Resettable for EsmepsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIOFFHR (rw) register accessor: ESM Interrupt Offset High Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmioffhr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmioffhr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmioffhr`]
module"]
# [doc (alias = "ESMIOFFHR")]
pub type Esmioffhr = crate :: Reg < esmioffhr :: EsmioffhrSpec > ; # [doc = "ESM Interrupt Offset High Register"]
pub mod esmioffhr { # [doc = "Register `ESMIOFFHR` reader"]
pub type R = crate :: R < EsmioffhrSpec > ; # [doc = "Register `ESMIOFFHR` writer"]
pub type W = crate :: W < EsmioffhrSpec > ; # [doc = "Field `INTOFFH` reader - 8:0\\]
Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the high level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 0, error Group2. ... 40h Interrupt pending for channel 31, error Group2. 41h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect."]
pub type IntoffhR = crate :: FieldReader < u16 > ; # [doc = "Field `INTOFFH` writer - 8:0\\]
Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the high level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 0, error Group2. ... 40h Interrupt pending for channel 31, error Group2. 41h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect."]
pub type IntoffhW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bits 0:8 - 8:0\\]
Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the high level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 0, error Group2. ... 40h Interrupt pending for channel 31, error Group2. 41h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect."]
# [inline (always)]
pub fn intoffh (& self) -> IntoffhR { IntoffhR :: new ((self . bits & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:8 - 8:0\\]
Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the high level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 0, error Group2. ... 40h Interrupt pending for channel 31, error Group2. 41h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect."]
# [inline (always)]
# [must_use]
pub fn intoffh (& mut self) -> IntoffhW < EsmioffhrSpec > { IntoffhW :: new (self , 0) } } # [doc = "ESM Interrupt Offset High Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmioffhr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmioffhr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmioffhrSpec ; impl crate :: RegisterSpec for EsmioffhrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmioffhr::R`](R) reader structure"]
impl crate :: Readable for EsmioffhrSpec { } # [doc = "`write(|w| ..)` method takes [`esmioffhr::W`](W) writer structure"]
impl crate :: Writable for EsmioffhrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIOFFHR to value 0"]
impl crate :: Resettable for EsmioffhrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIOFFLR (rw) register accessor: ESM Interrupt Offset Low Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiofflr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiofflr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiofflr`]
module"]
# [doc (alias = "ESMIOFFLR")]
pub type Esmiofflr = crate :: Reg < esmiofflr :: EsmiofflrSpec > ; # [doc = "ESM Interrupt Offset Low Register"]
pub mod esmiofflr { # [doc = "Register `ESMIOFFLR` reader"]
pub type R = crate :: R < EsmiofflrSpec > ; # [doc = "Register `ESMIOFFLR` writer"]
pub type W = crate :: W < EsmiofflrSpec > ; # [doc = "Field `INTOFFL` reader - 7:0\\]
Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the low level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high level interrupt line only. User and privileged mode (write): Writes have no effect."]
pub type IntofflR = crate :: FieldReader ; # [doc = "Field `INTOFFL` writer - 7:0\\]
Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the low level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high level interrupt line only. User and privileged mode (write): Writes have no effect."]
pub type IntofflW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the low level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high level interrupt line only. User and privileged mode (write): Writes have no effect."]
# [inline (always)]
pub fn intoffl (& self) -> IntofflR { IntofflR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the low level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high level interrupt line only. User and privileged mode (write): Writes have no effect."]
# [inline (always)]
# [must_use]
pub fn intoffl (& mut self) -> IntofflW < EsmiofflrSpec > { IntofflW :: new (self , 0) } } # [doc = "ESM Interrupt Offset Low Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiofflr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiofflr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmiofflrSpec ; impl crate :: RegisterSpec for EsmiofflrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiofflr::R`](R) reader structure"]
impl crate :: Readable for EsmiofflrSpec { } # [doc = "`write(|w| ..)` method takes [`esmiofflr::W`](W) writer structure"]
impl crate :: Writable for EsmiofflrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIOFFLR to value 0"]
impl crate :: Resettable for EsmiofflrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMLTCR (rw) register accessor: ESM Low-Time Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmltcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmltcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmltcr`]
module"]
# [doc (alias = "ESMLTCR")]
pub type Esmltcr = crate :: Reg < esmltcr :: EsmltcrSpec > ; # [doc = "ESM Low-Time Counter Register"]
pub mod esmltcr { # [doc = "Register `ESMLTCR` reader"]
pub type R = crate :: R < EsmltcrSpec > ; # [doc = "Register `ESMLTCR` writer"]
pub type W = crate :: W < EsmltcrSpec > ; # [doc = "Field `LTCP` reader - 15:0\\]
ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the following cases: 1. Reset (power on reset or warm reset) 2. An error occurs 3. User forces an error"]
pub type LtcpR = crate :: FieldReader < u16 > ; # [doc = "Field `LTCP` writer - 15:0\\]
ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the following cases: 1. Reset (power on reset or warm reset) 2. An error occurs 3. User forces an error"]
pub type LtcpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the following cases: 1. Reset (power on reset or warm reset) 2. An error occurs 3. User forces an error"]
# [inline (always)]
pub fn ltcp (& self) -> LtcpR { LtcpR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the following cases: 1. Reset (power on reset or warm reset) 2. An error occurs 3. User forces an error"]
# [inline (always)]
# [must_use]
pub fn ltcp (& mut self) -> LtcpW < EsmltcrSpec > { LtcpW :: new (self , 0) } } # [doc = "ESM Low-Time Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmltcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmltcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmltcrSpec ; impl crate :: RegisterSpec for EsmltcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmltcr::R`](R) reader structure"]
impl crate :: Readable for EsmltcrSpec { } # [doc = "`write(|w| ..)` method takes [`esmltcr::W`](W) writer structure"]
impl crate :: Writable for EsmltcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMLTCR to value 0"]
impl crate :: Resettable for EsmltcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMLTCPR (rw) register accessor: ESM Low-Time Counter Preload Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmltcpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmltcpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmltcpr`]
module"]
# [doc (alias = "ESMLTCPR")]
pub type Esmltcpr = crate :: Reg < esmltcpr :: EsmltcprSpec > ; # [doc = "ESM Low-Time Counter Preload Register"]
pub mod esmltcpr { # [doc = "Register `ESMLTCPR` reader"]
pub type R = crate :: R < EsmltcprSpec > ; # [doc = "Register `ESMLTCPR` writer"]
pub type W = crate :: W < EsmltcprSpec > ; # [doc = "Field `LTCP` reader - 15:0\\]
ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write)."]
pub type LtcpR = crate :: FieldReader < u16 > ; # [doc = "Field `LTCP` writer - 15:0\\]
ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write)."]
pub type LtcpW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write)."]
# [inline (always)]
pub fn ltcp (& self) -> LtcpR { LtcpR :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write)."]
# [inline (always)]
# [must_use]
pub fn ltcp (& mut self) -> LtcpW < EsmltcprSpec > { LtcpW :: new (self , 0) } } # [doc = "ESM Low-Time Counter Preload Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmltcpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmltcpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmltcprSpec ; impl crate :: RegisterSpec for EsmltcprSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmltcpr::R`](R) reader structure"]
impl crate :: Readable for EsmltcprSpec { } # [doc = "`write(|w| ..)` method takes [`esmltcpr::W`](W) writer structure"]
impl crate :: Writable for EsmltcprSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMLTCPR to value 0"]
impl crate :: Resettable for EsmltcprSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMEKR (rw) register accessor: ESM Error Key Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmekr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmekr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmekr`]
module"]
# [doc (alias = "ESMEKR")]
pub type Esmekr = crate :: Reg < esmekr :: EsmekrSpec > ; # [doc = "ESM Error Key Register"]
pub mod esmekr { # [doc = "Register `ESMEKR` reader"]
pub type R = crate :: R < EsmekrSpec > ; # [doc = "Register `ESMEKR` writer"]
pub type W = crate :: W < EsmekrSpec > ; # [doc = "Field `EKEY` reader - 3:0\\]
Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on ERROR pin. 5h The ERROR pin set to high when the low time counter (LTC) has completed; then the EKEY bit will switch back to normal mode (EKEY = 0000) All other values Activates normal mode."]
pub type EkeyR = crate :: FieldReader ; # [doc = "Field `EKEY` writer - 3:0\\]
Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on ERROR pin. 5h The ERROR pin set to high when the low time counter (LTC) has completed; then the EKEY bit will switch back to normal mode (EKEY = 0000) All other values Activates normal mode."]
pub type EkeyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on ERROR pin. 5h The ERROR pin set to high when the low time counter (LTC) has completed; then the EKEY bit will switch back to normal mode (EKEY = 0000) All other values Activates normal mode."]
# [inline (always)]
pub fn ekey (& self) -> EkeyR { EkeyR :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on ERROR pin. 5h The ERROR pin set to high when the low time counter (LTC) has completed; then the EKEY bit will switch back to normal mode (EKEY = 0000) All other values Activates normal mode."]
# [inline (always)]
# [must_use]
pub fn ekey (& mut self) -> EkeyW < EsmekrSpec > { EkeyW :: new (self , 0) } } # [doc = "ESM Error Key Register\n\nYou can [`read`](crate::Reg::read) this register and get [`esmekr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmekr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EsmekrSpec ; impl crate :: RegisterSpec for EsmekrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmekr::R`](R) reader structure"]
impl crate :: Readable for EsmekrSpec { } # [doc = "`write(|w| ..)` method takes [`esmekr::W`](W) writer structure"]
impl crate :: Writable for EsmekrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMEKR to value 0"]
impl crate :: Resettable for EsmekrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSSR2 (rw) register accessor: ESM Status Shadow Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esmssr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmssr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmssr2`]
module"]
# [doc (alias = "ESMSSR2")]
pub type Esmssr2 = crate :: Reg < esmssr2 :: Esmssr2Spec > ; # [doc = "ESM Status Shadow Register 2"]
pub mod esmssr2 { # [doc = "Register `ESMSSR2` reader"]
pub type R = crate :: R < Esmssr2Spec > ; # [doc = "Register `ESMSSR2` writer"]
pub type W = crate :: W < Esmssr2Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST)."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST)."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST)."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST)."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmssr2Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Shadow Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esmssr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmssr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmssr2Spec ; impl crate :: RegisterSpec for Esmssr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmssr2::R`](R) reader structure"]
impl crate :: Readable for Esmssr2Spec { } # [doc = "`write(|w| ..)` method takes [`esmssr2::W`](W) writer structure"]
impl crate :: Writable for Esmssr2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSSR2 to value 0"]
impl crate :: Resettable for Esmssr2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPSR4 (rw) register accessor: ESM Enable ERROR Pin Action/Response Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepsr4`]
module"]
# [doc (alias = "ESMIEPSR4")]
pub type Esmiepsr4 = crate :: Reg < esmiepsr4 :: Esmiepsr4Spec > ; # [doc = "ESM Enable ERROR Pin Action/Response Register 4"]
pub mod esmiepsr4 { # [doc = "Register `ESMIEPSR4` reader"]
pub type R = crate :: R < Esmiepsr4Spec > ; # [doc = "Register `ESMIEPSR4` writer"]
pub type W = crate :: W < Esmiepsr4Spec > ; # [doc = "Field `IEPSET` reader - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register."]
pub type IepsetR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPSET` writer - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register."]
pub type IepsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register."]
# [inline (always)]
pub fn iepset (& self) -> IepsetR { IepsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register."]
# [inline (always)]
# [must_use]
pub fn iepset (& mut self) -> IepsetW < Esmiepsr4Spec > { IepsetW :: new (self , 0) } } # [doc = "ESM Enable ERROR Pin Action/Response Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepsr4Spec ; impl crate :: RegisterSpec for Esmiepsr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepsr4::R`](R) reader structure"]
impl crate :: Readable for Esmiepsr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepsr4::W`](W) writer structure"]
impl crate :: Writable for Esmiepsr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPSR4 to value 0"]
impl crate :: Resettable for Esmiepsr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPCR4 (rw) register accessor: ESM Disable ERROR Pin Action/Response Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepcr4`]
module"]
# [doc (alias = "ESMIEPCR4")]
pub type Esmiepcr4 = crate :: Reg < esmiepcr4 :: Esmiepcr4Spec > ; # [doc = "ESM Disable ERROR Pin Action/Response Register 4"]
pub mod esmiepcr4 { # [doc = "Register `ESMIEPCR4` reader"]
pub type R = crate :: R < Esmiepcr4Spec > ; # [doc = "Register `ESMIEPCR4` writer"]
pub type W = crate :: W < Esmiepcr4Spec > ; # [doc = "Field `IEPCLR` reader - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR4 register."]
pub type IepclrR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPCLR` writer - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR4 register."]
pub type IepclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR4 register."]
# [inline (always)]
pub fn iepclr (& self) -> IepclrR { IepclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR4 register."]
# [inline (always)]
# [must_use]
pub fn iepclr (& mut self) -> IepclrW < Esmiepcr4Spec > { IepclrW :: new (self , 0) } } # [doc = "ESM Disable ERROR Pin Action/Response Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepcr4Spec ; impl crate :: RegisterSpec for Esmiepcr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepcr4::R`](R) reader structure"]
impl crate :: Readable for Esmiepcr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepcr4::W`](W) writer structure"]
impl crate :: Writable for Esmiepcr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPCR4 to value 0"]
impl crate :: Resettable for Esmiepcr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIESR4 (rw) register accessor: ESM Interrupt Enable Set/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiesr4`]
module"]
# [doc (alias = "ESMIESR4")]
pub type Esmiesr4 = crate :: Reg < esmiesr4 :: Esmiesr4Spec > ; # [doc = "ESM Interrupt Enable Set/Status Register 4"]
pub mod esmiesr4 { # [doc = "Register `ESMIESR4` reader"]
pub type R = crate :: R < Esmiesr4Spec > ; # [doc = "Register `ESMIESR4` writer"]
pub type W = crate :: W < Esmiesr4Spec > ; # [doc = "Field `INTENSET` reader - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register."]
pub type IntensetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENSET` writer - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register."]
pub type IntensetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register."]
# [inline (always)]
pub fn intenset (& self) -> IntensetR { IntensetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register."]
# [inline (always)]
# [must_use]
pub fn intenset (& mut self) -> IntensetW < Esmiesr4Spec > { IntensetW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Set/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiesr4Spec ; impl crate :: RegisterSpec for Esmiesr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiesr4::R`](R) reader structure"]
impl crate :: Readable for Esmiesr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmiesr4::W`](W) writer structure"]
impl crate :: Writable for Esmiesr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIESR4 to value 0"]
impl crate :: Resettable for Esmiesr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIECR4 (rw) register accessor: ESM Interrupt Enable Clear/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiecr4`]
module"]
# [doc (alias = "ESMIECR4")]
pub type Esmiecr4 = crate :: Reg < esmiecr4 :: Esmiecr4Spec > ; # [doc = "ESM Interrupt Enable Clear/Status Register 4"]
pub mod esmiecr4 { # [doc = "Register `ESMIECR4` reader"]
pub type R = crate :: R < Esmiecr4Spec > ; # [doc = "Register `ESMIECR4` writer"]
pub type W = crate :: W < Esmiecr4Spec > ; # [doc = "Field `INTENCLR` reader - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register."]
pub type IntenclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENCLR` writer - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register."]
pub type IntenclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register."]
# [inline (always)]
pub fn intenclr (& self) -> IntenclrR { IntenclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register."]
# [inline (always)]
# [must_use]
pub fn intenclr (& mut self) -> IntenclrW < Esmiecr4Spec > { IntenclrW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Clear/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiecr4Spec ; impl crate :: RegisterSpec for Esmiecr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiecr4::R`](R) reader structure"]
impl crate :: Readable for Esmiecr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmiecr4::W`](W) writer structure"]
impl crate :: Writable for Esmiecr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIECR4 to value 0"]
impl crate :: Resettable for Esmiecr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILSR4 (rw) register accessor: Interrupt Level Set/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilsr4`]
module"]
# [doc (alias = "ESMILSR4")]
pub type Esmilsr4 = crate :: Reg < esmilsr4 :: Esmilsr4Spec > ; # [doc = "Interrupt Level Set/Status Register 4"]
pub mod esmilsr4 { # [doc = "Register `ESMILSR4` reader"]
pub type R = crate :: R < Esmilsr4Spec > ; # [doc = "Register `ESMILSR4` writer"]
pub type W = crate :: W < Esmilsr4Spec > ; # [doc = "Field `INTLVLSET` reader - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register."]
pub type IntlvlsetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLSET` writer - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register."]
pub type IntlvlsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register."]
# [inline (always)]
pub fn intlvlset (& self) -> IntlvlsetR { IntlvlsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register."]
# [inline (always)]
# [must_use]
pub fn intlvlset (& mut self) -> IntlvlsetW < Esmilsr4Spec > { IntlvlsetW :: new (self , 0) } } # [doc = "Interrupt Level Set/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilsr4Spec ; impl crate :: RegisterSpec for Esmilsr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilsr4::R`](R) reader structure"]
impl crate :: Readable for Esmilsr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmilsr4::W`](W) writer structure"]
impl crate :: Writable for Esmilsr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILSR4 to value 0"]
impl crate :: Resettable for Esmilsr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILCR4 (rw) register accessor: Interrupt Level Clear/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilcr4`]
module"]
# [doc (alias = "ESMILCR4")]
pub type Esmilcr4 = crate :: Reg < esmilcr4 :: Esmilcr4Spec > ; # [doc = "Interrupt Level Clear/Status Register 4"]
pub mod esmilcr4 { # [doc = "Register `ESMILCR4` reader"]
pub type R = crate :: R < Esmilcr4Spec > ; # [doc = "Register `ESMILCR4` writer"]
pub type W = crate :: W < Esmilcr4Spec > ; # [doc = "Field `INTLVLCLR` reader - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR4 register."]
pub type IntlvlclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLCLR` writer - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR4 register."]
pub type IntlvlclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR4 register."]
# [inline (always)]
pub fn intlvlclr (& self) -> IntlvlclrR { IntlvlclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR4 register."]
# [inline (always)]
# [must_use]
pub fn intlvlclr (& mut self) -> IntlvlclrW < Esmilcr4Spec > { IntlvlclrW :: new (self , 0) } } # [doc = "Interrupt Level Clear/Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilcr4Spec ; impl crate :: RegisterSpec for Esmilcr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilcr4::R`](R) reader structure"]
impl crate :: Readable for Esmilcr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmilcr4::W`](W) writer structure"]
impl crate :: Writable for Esmilcr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILCR4 to value 0"]
impl crate :: Resettable for Esmilcr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSR4 (rw) register accessor: ESM Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmsr4`]
module"]
# [doc (alias = "ESMSR4")]
pub type Esmsr4 = crate :: Reg < esmsr4 :: Esmsr4Spec > ; # [doc = "ESM Status Register 4"]
pub mod esmsr4 { # [doc = "Register `ESMSR4` reader"]
pub type R = crate :: R < Esmsr4Spec > ; # [doc = "Register `ESMSR4` writer"]
pub type W = crate :: W < Esmsr4Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmsr4Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmsr4Spec ; impl crate :: RegisterSpec for Esmsr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmsr4::R`](R) reader structure"]
impl crate :: Readable for Esmsr4Spec { } # [doc = "`write(|w| ..)` method takes [`esmsr4::W`](W) writer structure"]
impl crate :: Writable for Esmsr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSR4 to value 0"]
impl crate :: Resettable for Esmsr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPSR7 (rw) register accessor: ESM Enable ERROR Pin Action/Response Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepsr7`]
module"]
# [doc (alias = "ESMIEPSR7")]
pub type Esmiepsr7 = crate :: Reg < esmiepsr7 :: Esmiepsr7Spec > ; # [doc = "ESM Enable ERROR Pin Action/Response Register 7"]
pub mod esmiepsr7 { # [doc = "Register `ESMIEPSR7` reader"]
pub type R = crate :: R < Esmiepsr7Spec > ; # [doc = "Register `ESMIEPSR7` writer"]
pub type W = crate :: W < Esmiepsr7Spec > ; # [doc = "Field `IEPSET` reader - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR7 register."]
pub type IepsetR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPSET` writer - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR7 register."]
pub type IepsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR7 register."]
# [inline (always)]
pub fn iepset (& self) -> IepsetR { IepsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR7 register."]
# [inline (always)]
# [must_use]
pub fn iepset (& mut self) -> IepsetW < Esmiepsr7Spec > { IepsetW :: new (self , 0) } } # [doc = "ESM Enable ERROR Pin Action/Response Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepsr7Spec ; impl crate :: RegisterSpec for Esmiepsr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepsr7::R`](R) reader structure"]
impl crate :: Readable for Esmiepsr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepsr7::W`](W) writer structure"]
impl crate :: Writable for Esmiepsr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPSR7 to value 0"]
impl crate :: Resettable for Esmiepsr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPCR7 (rw) register accessor: ESM Disable ERROR Pin Action/Response Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepcr7`]
module"]
# [doc (alias = "ESMIEPCR7")]
pub type Esmiepcr7 = crate :: Reg < esmiepcr7 :: Esmiepcr7Spec > ; # [doc = "ESM Disable ERROR Pin Action/Response Register 7"]
pub mod esmiepcr7 { # [doc = "Register `ESMIEPCR7` reader"]
pub type R = crate :: R < Esmiepcr7Spec > ; # [doc = "Register `ESMIEPCR7` writer"]
pub type W = crate :: W < Esmiepcr7Spec > ; # [doc = "Field `IEPCLR` reader - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR7 register."]
pub type IepclrR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPCLR` writer - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR7 register."]
pub type IepclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR7 register."]
# [inline (always)]
pub fn iepclr (& self) -> IepclrR { IepclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR7 register."]
# [inline (always)]
# [must_use]
pub fn iepclr (& mut self) -> IepclrW < Esmiepcr7Spec > { IepclrW :: new (self , 0) } } # [doc = "ESM Disable ERROR Pin Action/Response Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepcr7Spec ; impl crate :: RegisterSpec for Esmiepcr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepcr7::R`](R) reader structure"]
impl crate :: Readable for Esmiepcr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepcr7::W`](W) writer structure"]
impl crate :: Writable for Esmiepcr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPCR7 to value 0"]
impl crate :: Resettable for Esmiepcr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIESR7 (rw) register accessor: ESM Interrupt Enable Set/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiesr7`]
module"]
# [doc (alias = "ESMIESR7")]
pub type Esmiesr7 = crate :: Reg < esmiesr7 :: Esmiesr7Spec > ; # [doc = "ESM Interrupt Enable Set/Status Register 7"]
pub mod esmiesr7 { # [doc = "Register `ESMIESR7` reader"]
pub type R = crate :: R < Esmiesr7Spec > ; # [doc = "Register `ESMIESR7` writer"]
pub type W = crate :: W < Esmiesr7Spec > ; # [doc = "Field `INTENSET` reader - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register."]
pub type IntensetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENSET` writer - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register."]
pub type IntensetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register."]
# [inline (always)]
pub fn intenset (& self) -> IntensetR { IntensetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register."]
# [inline (always)]
# [must_use]
pub fn intenset (& mut self) -> IntensetW < Esmiesr7Spec > { IntensetW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Set/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiesr7Spec ; impl crate :: RegisterSpec for Esmiesr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiesr7::R`](R) reader structure"]
impl crate :: Readable for Esmiesr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmiesr7::W`](W) writer structure"]
impl crate :: Writable for Esmiesr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIESR7 to value 0"]
impl crate :: Resettable for Esmiesr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIECR7 (rw) register accessor: ESM Interrupt Enable Clear/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiecr7`]
module"]
# [doc (alias = "ESMIECR7")]
pub type Esmiecr7 = crate :: Reg < esmiecr7 :: Esmiecr7Spec > ; # [doc = "ESM Interrupt Enable Clear/Status Register 7"]
pub mod esmiecr7 { # [doc = "Register `ESMIECR7` reader"]
pub type R = crate :: R < Esmiecr7Spec > ; # [doc = "Register `ESMIECR7` writer"]
pub type W = crate :: W < Esmiecr7Spec > ; # [doc = "Field `INTENCLR` reader - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR7 register."]
pub type IntenclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENCLR` writer - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR7 register."]
pub type IntenclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR7 register."]
# [inline (always)]
pub fn intenclr (& self) -> IntenclrR { IntenclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR7 register."]
# [inline (always)]
# [must_use]
pub fn intenclr (& mut self) -> IntenclrW < Esmiecr7Spec > { IntenclrW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Clear/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiecr7Spec ; impl crate :: RegisterSpec for Esmiecr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiecr7::R`](R) reader structure"]
impl crate :: Readable for Esmiecr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmiecr7::W`](W) writer structure"]
impl crate :: Writable for Esmiecr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIECR7 to value 0"]
impl crate :: Resettable for Esmiecr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILSR7 (rw) register accessor: Interrupt Level Set/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilsr7`]
module"]
# [doc (alias = "ESMILSR7")]
pub type Esmilsr7 = crate :: Reg < esmilsr7 :: Esmilsr7Spec > ; # [doc = "Interrupt Level Set/Status Register 7"]
pub mod esmilsr7 { # [doc = "Register `ESMILSR7` reader"]
pub type R = crate :: R < Esmilsr7Spec > ; # [doc = "Register `ESMILSR7` writer"]
pub type W = crate :: W < Esmilsr7Spec > ; # [doc = "Field `INTLVLSET` reader - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR7 register."]
pub type IntlvlsetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLSET` writer - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR7 register."]
pub type IntlvlsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR7 register."]
# [inline (always)]
pub fn intlvlset (& self) -> IntlvlsetR { IntlvlsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR7 register."]
# [inline (always)]
# [must_use]
pub fn intlvlset (& mut self) -> IntlvlsetW < Esmilsr7Spec > { IntlvlsetW :: new (self , 0) } } # [doc = "Interrupt Level Set/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilsr7Spec ; impl crate :: RegisterSpec for Esmilsr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilsr7::R`](R) reader structure"]
impl crate :: Readable for Esmilsr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmilsr7::W`](W) writer structure"]
impl crate :: Writable for Esmilsr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILSR7 to value 0"]
impl crate :: Resettable for Esmilsr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILCR7 (rw) register accessor: Interrupt Level Clear/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilcr7`]
module"]
# [doc (alias = "ESMILCR7")]
pub type Esmilcr7 = crate :: Reg < esmilcr7 :: Esmilcr7Spec > ; # [doc = "Interrupt Level Clear/Status Register 7"]
pub mod esmilcr7 { # [doc = "Register `ESMILCR7` reader"]
pub type R = crate :: R < Esmilcr7Spec > ; # [doc = "Register `ESMILCR7` writer"]
pub type W = crate :: W < Esmilcr7Spec > ; # [doc = "Field `INTLVLCLR` reader - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR7 register."]
pub type IntlvlclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLCLR` writer - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR7 register."]
pub type IntlvlclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR7 register."]
# [inline (always)]
pub fn intlvlclr (& self) -> IntlvlclrR { IntlvlclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR7 register."]
# [inline (always)]
# [must_use]
pub fn intlvlclr (& mut self) -> IntlvlclrW < Esmilcr7Spec > { IntlvlclrW :: new (self , 0) } } # [doc = "Interrupt Level Clear/Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilcr7Spec ; impl crate :: RegisterSpec for Esmilcr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilcr7::R`](R) reader structure"]
impl crate :: Readable for Esmilcr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmilcr7::W`](W) writer structure"]
impl crate :: Writable for Esmilcr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILCR7 to value 0"]
impl crate :: Resettable for Esmilcr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSR7 (rw) register accessor: ESM Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmsr7`]
module"]
# [doc (alias = "ESMSR7")]
pub type Esmsr7 = crate :: Reg < esmsr7 :: Esmsr7Spec > ; # [doc = "ESM Status Register 7"]
pub mod esmsr7 { # [doc = "Register `ESMSR7` reader"]
pub type R = crate :: R < Esmsr7Spec > ; # [doc = "Register `ESMSR7` writer"]
pub type W = crate :: W < Esmsr7Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmsr7Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmsr7Spec ; impl crate :: RegisterSpec for Esmsr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmsr7::R`](R) reader structure"]
impl crate :: Readable for Esmsr7Spec { } # [doc = "`write(|w| ..)` method takes [`esmsr7::W`](W) writer structure"]
impl crate :: Writable for Esmsr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSR7 to value 0"]
impl crate :: Resettable for Esmsr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPSR10 (rw) register accessor: ESM Enable ERROR Pin Action/Response Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepsr10`]
module"]
# [doc (alias = "ESMIEPSR10")]
pub type Esmiepsr10 = crate :: Reg < esmiepsr10 :: Esmiepsr10Spec > ; # [doc = "ESM Enable ERROR Pin Action/Response Register 10"]
pub mod esmiepsr10 { # [doc = "Register `ESMIEPSR10` reader"]
pub type R = crate :: R < Esmiepsr10Spec > ; # [doc = "Register `ESMIEPSR10` writer"]
pub type W = crate :: W < Esmiepsr10Spec > ; # [doc = "Field `IEPSET` reader - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR10 register."]
pub type IepsetR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPSET` writer - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR10 register."]
pub type IepsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR10 register."]
# [inline (always)]
pub fn iepset (& self) -> IepsetR { IepsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR10 register."]
# [inline (always)]
# [must_use]
pub fn iepset (& mut self) -> IepsetW < Esmiepsr10Spec > { IepsetW :: new (self , 0) } } # [doc = "ESM Enable ERROR Pin Action/Response Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepsr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepsr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepsr10Spec ; impl crate :: RegisterSpec for Esmiepsr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepsr10::R`](R) reader structure"]
impl crate :: Readable for Esmiepsr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepsr10::W`](W) writer structure"]
impl crate :: Writable for Esmiepsr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPSR10 to value 0"]
impl crate :: Resettable for Esmiepsr10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIEPCR10 (rw) register accessor: ESM Disable ERROR Pin Action/Response Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiepcr10`]
module"]
# [doc (alias = "ESMIEPCR10")]
pub type Esmiepcr10 = crate :: Reg < esmiepcr10 :: Esmiepcr10Spec > ; # [doc = "ESM Disable ERROR Pin Action/Response Register 10"]
pub mod esmiepcr10 { # [doc = "Register `ESMIEPCR10` reader"]
pub type R = crate :: R < Esmiepcr10Spec > ; # [doc = "Register `ESMIEPCR10` writer"]
pub type W = crate :: W < Esmiepcr10Spec > ; # [doc = "Field `IEPCLR` reader - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR10 register."]
pub type IepclrR = crate :: FieldReader < u32 > ; # [doc = "Field `IEPCLR` writer - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR10 register."]
pub type IepclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR10 register."]
# [inline (always)]
pub fn iepclr (& self) -> IepclrR { IepclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR10 register."]
# [inline (always)]
# [must_use]
pub fn iepclr (& mut self) -> IepclrW < Esmiepcr10Spec > { IepclrW :: new (self , 0) } } # [doc = "ESM Disable ERROR Pin Action/Response Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiepcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiepcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiepcr10Spec ; impl crate :: RegisterSpec for Esmiepcr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiepcr10::R`](R) reader structure"]
impl crate :: Readable for Esmiepcr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmiepcr10::W`](W) writer structure"]
impl crate :: Writable for Esmiepcr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIEPCR10 to value 0"]
impl crate :: Resettable for Esmiepcr10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIESR10 (rw) register accessor: ESM Interrupt Enable Set/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiesr10`]
module"]
# [doc (alias = "ESMIESR10")]
pub type Esmiesr10 = crate :: Reg < esmiesr10 :: Esmiesr10Spec > ; # [doc = "ESM Interrupt Enable Set/Status Register 10"]
pub mod esmiesr10 { # [doc = "Register `ESMIESR10` reader"]
pub type R = crate :: R < Esmiesr10Spec > ; # [doc = "Register `ESMIESR10` writer"]
pub type W = crate :: W < Esmiesr10Spec > ; # [doc = "Field `INTENSET` reader - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR10 register."]
pub type IntensetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENSET` writer - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR10 register."]
pub type IntensetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR10 register."]
# [inline (always)]
pub fn intenset (& self) -> IntensetR { IntensetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR10 register."]
# [inline (always)]
# [must_use]
pub fn intenset (& mut self) -> IntensetW < Esmiesr10Spec > { IntensetW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Set/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiesr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiesr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiesr10Spec ; impl crate :: RegisterSpec for Esmiesr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiesr10::R`](R) reader structure"]
impl crate :: Readable for Esmiesr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmiesr10::W`](W) writer structure"]
impl crate :: Writable for Esmiesr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIESR10 to value 0"]
impl crate :: Resettable for Esmiesr10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMIECR10 (rw) register accessor: ESM Interrupt Enable Clear/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmiecr10`]
module"]
# [doc (alias = "ESMIECR10")]
pub type Esmiecr10 = crate :: Reg < esmiecr10 :: Esmiecr10Spec > ; # [doc = "ESM Interrupt Enable Clear/Status Register 10"]
pub mod esmiecr10 { # [doc = "Register `ESMIECR10` reader"]
pub type R = crate :: R < Esmiecr10Spec > ; # [doc = "Register `ESMIECR10` writer"]
pub type W = crate :: W < Esmiecr10Spec > ; # [doc = "Field `INTENCLR` reader - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR10 register."]
pub type IntenclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTENCLR` writer - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR10 register."]
pub type IntenclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR10 register."]
# [inline (always)]
pub fn intenclr (& self) -> IntenclrR { IntenclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR10 register."]
# [inline (always)]
# [must_use]
pub fn intenclr (& mut self) -> IntenclrW < Esmiecr10Spec > { IntenclrW :: new (self , 0) } } # [doc = "ESM Interrupt Enable Clear/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmiecr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmiecr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmiecr10Spec ; impl crate :: RegisterSpec for Esmiecr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmiecr10::R`](R) reader structure"]
impl crate :: Readable for Esmiecr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmiecr10::W`](W) writer structure"]
impl crate :: Writable for Esmiecr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMIECR10 to value 0"]
impl crate :: Resettable for Esmiecr10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILSR10 (rw) register accessor: Interrupt Level Set/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilsr10`]
module"]
# [doc (alias = "ESMILSR10")]
pub type Esmilsr10 = crate :: Reg < esmilsr10 :: Esmilsr10Spec > ; # [doc = "Interrupt Level Set/Status Register 10"]
pub mod esmilsr10 { # [doc = "Register `ESMILSR10` reader"]
pub type R = crate :: R < Esmilsr10Spec > ; # [doc = "Register `ESMILSR10` writer"]
pub type W = crate :: W < Esmilsr10Spec > ; # [doc = "Field `INTLVLSET` reader - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR10 register."]
pub type IntlvlsetR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLSET` writer - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR10 register."]
pub type IntlvlsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR10 register."]
# [inline (always)]
pub fn intlvlset (& self) -> IntlvlsetR { IntlvlsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR10 register."]
# [inline (always)]
# [must_use]
pub fn intlvlset (& mut self) -> IntlvlsetW < Esmilsr10Spec > { IntlvlsetW :: new (self , 0) } } # [doc = "Interrupt Level Set/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilsr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilsr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilsr10Spec ; impl crate :: RegisterSpec for Esmilsr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilsr10::R`](R) reader structure"]
impl crate :: Readable for Esmilsr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmilsr10::W`](W) writer structure"]
impl crate :: Writable for Esmilsr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILSR10 to value 0"]
impl crate :: Resettable for Esmilsr10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMILCR10 (rw) register accessor: Interrupt Level Clear/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmilcr10`]
module"]
# [doc (alias = "ESMILCR10")]
pub type Esmilcr10 = crate :: Reg < esmilcr10 :: Esmilcr10Spec > ; # [doc = "Interrupt Level Clear/Status Register 10"]
pub mod esmilcr10 { # [doc = "Register `ESMILCR10` reader"]
pub type R = crate :: R < Esmilcr10Spec > ; # [doc = "Register `ESMILCR10` writer"]
pub type W = crate :: W < Esmilcr10Spec > ; # [doc = "Field `INTLVLCLR` reader - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR10 register."]
pub type IntlvlclrR = crate :: FieldReader < u32 > ; # [doc = "Field `INTLVLCLR` writer - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR10 register."]
pub type IntlvlclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR10 register."]
# [inline (always)]
pub fn intlvlclr (& self) -> IntlvlclrR { IntlvlclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR10 register."]
# [inline (always)]
# [must_use]
pub fn intlvlclr (& mut self) -> IntlvlclrW < Esmilcr10Spec > { IntlvlclrW :: new (self , 0) } } # [doc = "Interrupt Level Clear/Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmilcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmilcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmilcr10Spec ; impl crate :: RegisterSpec for Esmilcr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmilcr10::R`](R) reader structure"]
impl crate :: Readable for Esmilcr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmilcr10::W`](W) writer structure"]
impl crate :: Writable for Esmilcr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMILCR10 to value 0"]
impl crate :: Resettable for Esmilcr10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ESMSR10 (rw) register accessor: ESM Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esmsr10`]
module"]
# [doc (alias = "ESMSR10")]
pub type Esmsr10 = crate :: Reg < esmsr10 :: Esmsr10Spec > ; # [doc = "ESM Status Register 10"]
pub mod esmsr10 { # [doc = "Register `ESMSR10` reader"]
pub type R = crate :: R < Esmsr10Spec > ; # [doc = "Register `ESMSR10` writer"]
pub type W = crate :: W < Esmsr10Spec > ; # [doc = "Field `ESF` reader - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfR = crate :: FieldReader < u32 > ; # [doc = "Field `ESF` writer - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
pub type EsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
pub fn esf (& self) -> EsfR { EsfR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called."]
# [inline (always)]
# [must_use]
pub fn esf (& mut self) -> EsfW < Esmsr10Spec > { EsfW :: new (self , 0) } } # [doc = "ESM Status Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`esmsr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esmsr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esmsr10Spec ; impl crate :: RegisterSpec for Esmsr10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`esmsr10::R`](R) reader structure"]
impl crate :: Readable for Esmsr10Spec { } # [doc = "`write(|w| ..)` method takes [`esmsr10::W`](W) writer structure"]
impl crate :: Writable for Esmsr10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ESMSR10 to value 0"]
impl crate :: Resettable for Esmsr10Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_UART"]
pub struct AppUart1 { _marker : PhantomData < * const () > } unsafe impl Send for AppUart1 { } impl AppUart1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_uart_1 :: RegisterBlock = 0x57f7_f000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_uart_1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppUart1 { type Target = app_uart_1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppUart1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppUart1") . finish () } } # [doc = "APP_UART"]
pub mod app_uart_1 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { scigcr0 : Scigcr0 , scigcr1 : Scigcr1 , reserved1 : Reserved1 , scisetint : Scisetint , sciclearint : Sciclearint , scisetintlvl : Scisetintlvl , sciclearintlvl : Sciclearintlvl , sciflr : Sciflr , sciintvect0 : Sciintvect0 , sciintvect1 : Sciintvect1 , scichar : Scichar , scibaud : Scibaud , scied : Scied , scird : Scird , scitd : Scitd , scipio0 : Scipio0 , scipio1 : Scipio1 , scipio2 : Scipio2 , scipio3 : Scipio3 , scipio4 : Scipio4 , scipio5 : Scipio5 , scipio6 : Scipio6 , scipio7 : Scipio7 , scipio8 : Scipio8 , reserved2 : Reserved2 , reserved3 : Reserved3 , reserved4 : Reserved4 , reserved5 : Reserved5 , reserved6 : Reserved6 , reserved7 : Reserved7 , reserved8 : Reserved8 , reserved9 : Reserved9 , scipio9 : Scipio9 , _reserved33 : [u8 ; 0x0c]
, sciiodctrl : Sciiodctrl , } impl RegisterBlock { # [doc = "0x00 - The SCIGCR0 register defines the module reset"]
# [inline (always)]
pub const fn scigcr0 (& self) -> & Scigcr0 { & self . scigcr0 } # [doc = "0x04 - The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI"]
# [inline (always)]
pub const fn scigcr1 (& self) -> & Scigcr1 { & self . scigcr1 } # [doc = "0x08 - Reserved"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0x0c - SCI Set Interrupt Register"]
# [inline (always)]
pub const fn scisetint (& self) -> & Scisetint { & self . scisetint } # [doc = "0x10 - SCI Clear Interrupt Register"]
# [inline (always)]
pub const fn sciclearint (& self) -> & Sciclearint { & self . sciclearint } # [doc = "0x14 - SCI Set Interrupt Level Register"]
# [inline (always)]
pub const fn scisetintlvl (& self) -> & Scisetintlvl { & self . scisetintlvl } # [doc = "0x18 - SCI Clear Interrupt Level Register"]
# [inline (always)]
pub const fn sciclearintlvl (& self) -> & Sciclearintlvl { & self . sciclearintlvl } # [doc = "0x1c - SCI Flags Register"]
# [inline (always)]
pub const fn sciflr (& self) -> & Sciflr { & self . sciflr } # [doc = "0x20 - SCI Interrupt Offset Vector 0 Register"]
# [inline (always)]
pub const fn sciintvect0 (& self) -> & Sciintvect0 { & self . sciintvect0 } # [doc = "0x24 - SCI Interrupt Offset Vector 1 Register"]
# [inline (always)]
pub const fn sciintvect1 (& self) -> & Sciintvect1 { & self . sciintvect1 } # [doc = "0x28 - SCI Character Control Register"]
# [inline (always)]
pub const fn scichar (& self) -> & Scichar { & self . scichar } # [doc = "0x2c - SCI Baud Rate Selection Register"]
# [inline (always)]
pub const fn scibaud (& self) -> & Scibaud { & self . scibaud } # [doc = "0x30 - Receiver Emulation Data Buffer"]
# [inline (always)]
pub const fn scied (& self) -> & Scied { & self . scied } # [doc = "0x34 - Receiver Data Buffer"]
# [inline (always)]
pub const fn scird (& self) -> & Scird { & self . scird } # [doc = "0x38 - Transmit Data Buffer Register"]
# [inline (always)]
pub const fn scitd (& self) -> & Scitd { & self . scitd } # [doc = "0x3c - SCI Pin I/O Control Register 0"]
# [inline (always)]
pub const fn scipio0 (& self) -> & Scipio0 { & self . scipio0 } # [doc = "0x40 - SCI Pin I/O Control Register 1"]
# [inline (always)]
pub const fn scipio1 (& self) -> & Scipio1 { & self . scipio1 } # [doc = "0x44 - SCI Pin I/O Control Register 2"]
# [inline (always)]
pub const fn scipio2 (& self) -> & Scipio2 { & self . scipio2 } # [doc = "0x48 - SCI Pin I/O Control Register 3"]
# [inline (always)]
pub const fn scipio3 (& self) -> & Scipio3 { & self . scipio3 } # [doc = "0x4c - SCI Pin I/O Control Register 4"]
# [inline (always)]
pub const fn scipio4 (& self) -> & Scipio4 { & self . scipio4 } # [doc = "0x50 - SCI Pin I/O Control Register 5"]
# [inline (always)]
pub const fn scipio5 (& self) -> & Scipio5 { & self . scipio5 } # [doc = "0x54 - SCI Pin I/O Control Register 6"]
# [inline (always)]
pub const fn scipio6 (& self) -> & Scipio6 { & self . scipio6 } # [doc = "0x58 - SCI Pin I/O Control Register 7"]
# [inline (always)]
pub const fn scipio7 (& self) -> & Scipio7 { & self . scipio7 } # [doc = "0x5c - SCI Pin I/O Control Register 8"]
# [inline (always)]
pub const fn scipio8 (& self) -> & Scipio8 { & self . scipio8 } # [doc = "0x60 - Reserved"]
# [inline (always)]
pub const fn reserved2 (& self) -> & Reserved2 { & self . reserved2 } # [doc = "0x64 - Reserved"]
# [inline (always)]
pub const fn reserved3 (& self) -> & Reserved3 { & self . reserved3 } # [doc = "0x68 - Reserved"]
# [inline (always)]
pub const fn reserved4 (& self) -> & Reserved4 { & self . reserved4 } # [doc = "0x6c - Reserved"]
# [inline (always)]
pub const fn reserved5 (& self) -> & Reserved5 { & self . reserved5 } # [doc = "0x70 - Reserved"]
# [inline (always)]
pub const fn reserved6 (& self) -> & Reserved6 { & self . reserved6 } # [doc = "0x74 - Reserved"]
# [inline (always)]
pub const fn reserved7 (& self) -> & Reserved7 { & self . reserved7 } # [doc = "0x78 - Reserved"]
# [inline (always)]
pub const fn reserved8 (& self) -> & Reserved8 { & self . reserved8 } # [doc = "0x7c - Reserved"]
# [inline (always)]
pub const fn reserved9 (& self) -> & Reserved9 { & self . reserved9 } # [doc = "0x80 - SCI Pin I/O Control Register 9"]
# [inline (always)]
pub const fn scipio9 (& self) -> & Scipio9 { & self . scipio9 } # [doc = "0x90 - SCI IO DFT Control"]
# [inline (always)]
pub const fn sciiodctrl (& self) -> & Sciiodctrl { & self . sciiodctrl } } # [doc = "SCIGCR0 (rw) register accessor: The SCIGCR0 register defines the module reset\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr0`]
module"]
# [doc (alias = "SCIGCR0")]
pub type Scigcr0 = crate :: Reg < scigcr0 :: Scigcr0Spec > ; # [doc = "The SCIGCR0 register defines the module reset"]
pub mod scigcr0 { # [doc = "Register `SCIGCR0` reader"]
pub type R = crate :: R < Scigcr0Spec > ; # [doc = "Register `SCIGCR0` writer"]
pub type W = crate :: W < Scigcr0Spec > ; # [doc = "Field `RESET` reader - 0:0\\]
GIO reset"]
pub type ResetR = crate :: BitReader ; # [doc = "Field `RESET` writer - 0:0\\]
GIO reset"]
pub type ResetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
GIO reset"]
# [inline (always)]
pub fn reset (& self) -> ResetR { ResetR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
GIO reset"]
# [inline (always)]
# [must_use]
pub fn reset (& mut self) -> ResetW < Scigcr0Spec > { ResetW :: new (self , 0) } } # [doc = "The SCIGCR0 register defines the module reset\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr0Spec ; impl crate :: RegisterSpec for Scigcr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr0::R`](R) reader structure"]
impl crate :: Readable for Scigcr0Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr0::W`](W) writer structure"]
impl crate :: Writable for Scigcr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR0 to value 0"]
impl crate :: Resettable for Scigcr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIGCR1 (rw) register accessor: The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scigcr1`]
module"]
# [doc (alias = "SCIGCR1")]
pub type Scigcr1 = crate :: Reg < scigcr1 :: Scigcr1Spec > ; # [doc = "The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI"]
pub mod scigcr1 { # [doc = "Register `SCIGCR1` reader"]
pub type R = crate :: R < Scigcr1Spec > ; # [doc = "Register `SCIGCR1` writer"]
pub type W = crate :: W < Scigcr1Spec > ; # [doc = "Field `COMM_MODE` reader - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
pub type CommModeR = crate :: BitReader ; # [doc = "Field `COMM_MODE` writer - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
pub type CommModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMING_MODE` reader - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
pub type TimingModeR = crate :: BitReader ; # [doc = "Field `TIMING_MODE` writer - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
pub type TimingModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITY_ENA` reader - 2:2\\]
SCI parity enable"]
pub type ParityEnaR = crate :: BitReader ; # [doc = "Field `PARITY_ENA` writer - 2:2\\]
SCI parity enable"]
pub type ParityEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PARITY` reader - 3:3\\]
SCI parity odd/even selection"]
pub type ParityR = crate :: BitReader ; # [doc = "Field `PARITY` writer - 3:3\\]
SCI parity odd/even selection"]
pub type ParityW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STOP` reader - 4:4\\]
SCI number of stop bits"]
pub type StopR = crate :: BitReader ; # [doc = "Field `STOP` writer - 4:4\\]
SCI number of stop bits"]
pub type StopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLOCK` reader - 5:5\\]
SCI internal clock enable"]
pub type ClockR = crate :: BitReader ; # [doc = "Field `CLOCK` writer - 5:5\\]
SCI internal clock enable"]
pub type ClockW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 6:6\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `RESERVED1` writer - 6:6\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SW_nRESET` reader - 7:7\\]
Software reset (active low)"]
pub type SwNResetR = crate :: BitReader ; # [doc = "Field `SW_nRESET` writer - 7:7\\]
Software reset (active low)"]
pub type SwNResetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SLEEP` reader - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
pub type SleepR = crate :: BitReader ; # [doc = "Field `SLEEP` writer - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
pub type SleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POWERDOWN` reader - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
pub type PowerdownR = crate :: BitReader ; # [doc = "Field `POWERDOWN` writer - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
pub type PowerdownW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `LOOP_BACK` reader - 16:16\\]
Enable bit for loopback mode"]
pub type LoopBackR = crate :: BitReader ; # [doc = "Field `LOOP_BACK` writer - 16:16\\]
Enable bit for loopback mode"]
pub type LoopBackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONT` reader - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
pub type ContR = crate :: BitReader ; # [doc = "Field `CONT` writer - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
pub type ContW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 23:18\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:18\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `RXENA` reader - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
pub type RxenaR = crate :: BitReader ; # [doc = "Field `RXENA` writer - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
pub type RxenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXENA` reader - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
pub type TxenaR = crate :: BitReader ; # [doc = "Field `TXENA` writer - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
pub type TxenaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:26\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:26\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
# [inline (always)]
pub fn comm_mode (& self) -> CommModeR { CommModeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
# [inline (always)]
pub fn timing_mode (& self) -> TimingModeR { TimingModeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SCI parity enable"]
# [inline (always)]
pub fn parity_ena (& self) -> ParityEnaR { ParityEnaR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SCI parity odd/even selection"]
# [inline (always)]
pub fn parity (& self) -> ParityR { ParityR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
SCI number of stop bits"]
# [inline (always)]
pub fn stop (& self) -> StopR { StopR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
SCI internal clock enable"]
# [inline (always)]
pub fn clock (& self) -> ClockR { ClockR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Software reset (active low)"]
# [inline (always)]
pub fn sw_n_reset (& self) -> SwNResetR { SwNResetR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
# [inline (always)]
pub fn sleep (& self) -> SleepR { SleepR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
# [inline (always)]
pub fn powerdown (& self) -> PowerdownR { PowerdownR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Enable bit for loopback mode"]
# [inline (always)]
pub fn loop_back (& self) -> LoopBackR { LoopBackR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
# [inline (always)]
pub fn cont (& self) -> ContR { ContR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 18) & 0x3f) as u8) } # [doc = "Bit 24 - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
# [inline (always)]
pub fn rxena (& self) -> RxenaR { RxenaR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
# [inline (always)]
pub fn txena (& self) -> TxenaR { TxenaR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode)"]
# [inline (always)]
# [must_use]
pub fn comm_mode (& mut self) -> CommModeW < Scigcr1Spec > { CommModeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing)"]
# [inline (always)]
# [must_use]
pub fn timing_mode (& mut self) -> TimingModeW < Scigcr1Spec > { TimingModeW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SCI parity enable"]
# [inline (always)]
# [must_use]
pub fn parity_ena (& mut self) -> ParityEnaW < Scigcr1Spec > { ParityEnaW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SCI parity odd/even selection"]
# [inline (always)]
# [must_use]
pub fn parity (& mut self) -> ParityW < Scigcr1Spec > { ParityW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
SCI number of stop bits"]
# [inline (always)]
# [must_use]
pub fn stop (& mut self) -> StopW < Scigcr1Spec > { StopW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
SCI internal clock enable"]
# [inline (always)]
# [must_use]
pub fn clock (& mut self) -> ClockW < Scigcr1Spec > { ClockW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < Scigcr1Spec > { Reserved1W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Software reset (active low)"]
# [inline (always)]
# [must_use]
pub fn sw_n_reset (& mut self) -> SwNResetW < Scigcr1Spec > { SwNResetW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode"]
# [inline (always)]
# [must_use]
pub fn sleep (& mut self) -> SleepW < Scigcr1Spec > { SleepW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode"]
# [inline (always)]
# [must_use]
pub fn powerdown (& mut self) -> PowerdownW < Scigcr1Spec > { PowerdownW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < Scigcr1Spec > { Reserved2W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
Enable bit for loopback mode"]
# [inline (always)]
# [must_use]
pub fn loop_back (& mut self) -> LoopBackW < Scigcr1Spec > { LoopBackW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended"]
# [inline (always)]
# [must_use]
pub fn cont (& mut self) -> ContW < Scigcr1Spec > { ContW :: new (self , 17) } # [doc = "Bits 18:23 - 23:18\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < Scigcr1Spec > { Reserved3W :: new (self , 18) } # [doc = "Bit 24 - 24:24\\]
Allows the receiver to transfer data from the shift buffer to the receive buffer"]
# [inline (always)]
# [must_use]
pub fn rxena (& mut self) -> RxenaW < Scigcr1Spec > { RxenaW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set"]
# [inline (always)]
# [must_use]
pub fn txena (& mut self) -> TxenaW < Scigcr1Spec > { TxenaW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < Scigcr1Spec > { Reserved4W :: new (self , 26) } } # [doc = "The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI\n\nYou can [`read`](crate::Reg::read) this register and get [`scigcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scigcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scigcr1Spec ; impl crate :: RegisterSpec for Scigcr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scigcr1::R`](R) reader structure"]
impl crate :: Readable for Scigcr1Spec { } # [doc = "`write(|w| ..)` method takes [`scigcr1::W`](W) writer structure"]
impl crate :: Writable for Scigcr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIGCR1 to value 0"]
impl crate :: Resettable for Scigcr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
# [doc (alias = "RESERVED1")]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "Reserved"]
pub mod reserved1 { # [doc = "Register `RESERVED1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `RESERVED1` writer"]
pub type W = crate :: W < Reserved1Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCISETINT (rw) register accessor: SCI Set Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scisetint`]
module"]
# [doc (alias = "SCISETINT")]
pub type Scisetint = crate :: Reg < scisetint :: ScisetintSpec > ; # [doc = "SCI Set Interrupt Register"]
pub mod scisetint { # [doc = "Register `SCISETINT` reader"]
pub type R = crate :: R < ScisetintSpec > ; # [doc = "Register `SCISETINT` writer"]
pub type W = crate :: W < ScisetintSpec > ; # [doc = "Field `SET_BRKDT_INT` reader - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetBrkdtIntR = crate :: BitReader ; # [doc = "Field `SET_BRKDT_INT` writer - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetBrkdtIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_WAKEUP_INT` reader - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetWakeupIntR = crate :: BitReader ; # [doc = "Field `SET_WAKEUP_INT` writer - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetWakeupIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `SET_TX_INT` reader - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxIntR = crate :: BitReader ; # [doc = "Field `SET_TX_INT` writer - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_INT` reader - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetRxIntR = crate :: BitReader ; # [doc = "Field `SET_RX_INT` writer - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetRxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `SET_TX_DMA` reader - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxDmaR = crate :: BitReader ; # [doc = "Field `SET_TX_DMA` writer - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetTxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_DMA` reader - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type SetRxDmaR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA` writer - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
pub type SetRxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_DMA_ALL` reader - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
pub type SetRxDmaAllR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA_ALL` writer - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
pub type SetRxDmaAllW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 23:19\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:19\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SET_PE_INT` reader - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetPeIntR = crate :: BitReader ; # [doc = "Field `SET_PE_INT` writer - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetPeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_OE_INT` reader - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetOeIntR = crate :: BitReader ; # [doc = "Field `SET_OE_INT` writer - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetOeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_FE_INT` reader - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetFeIntR = crate :: BitReader ; # [doc = "Field `SET_FE_INT` writer - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type SetFeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:27\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:27\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_brkdt_int (& self) -> SetBrkdtIntR { SetBrkdtIntR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_wakeup_int (& self) -> SetWakeupIntR { SetWakeupIntR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_tx_int (& self) -> SetTxIntR { SetTxIntR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_rx_int (& self) -> SetRxIntR { SetRxIntR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_tx_dma (& self) -> SetTxDmaR { SetTxDmaR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
pub fn set_rx_dma (& self) -> SetRxDmaR { SetRxDmaR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
# [inline (always)]
pub fn set_rx_dma_all (& self) -> SetRxDmaAllR { SetRxDmaAllR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_pe_int (& self) -> SetPeIntR { SetPeIntR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_oe_int (& self) -> SetOeIntR { SetOeIntR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn set_fe_int (& self) -> SetFeIntR { SetFeIntR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_brkdt_int (& mut self) -> SetBrkdtIntW < ScisetintSpec > { SetBrkdtIntW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_wakeup_int (& mut self) -> SetWakeupIntW < ScisetintSpec > { SetWakeupIntW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < ScisetintSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_tx_int (& mut self) -> SetTxIntW < ScisetintSpec > { SetTxIntW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_rx_int (& mut self) -> SetRxIntW < ScisetintSpec > { SetRxIntW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < ScisetintSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_tx_dma (& mut self) -> SetTxDmaW < ScisetintSpec > { SetTxDmaW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request"]
# [inline (always)]
# [must_use]
pub fn set_rx_dma (& mut self) -> SetRxDmaW < ScisetintSpec > { SetRxDmaW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames"]
# [inline (always)]
# [must_use]
pub fn set_rx_dma_all (& mut self) -> SetRxDmaAllW < ScisetintSpec > { SetRxDmaAllW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < ScisetintSpec > { Reserved3W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_pe_int (& mut self) -> SetPeIntW < ScisetintSpec > { SetPeIntW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_oe_int (& mut self) -> SetOeIntW < ScisetintSpec > { SetOeIntW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn set_fe_int (& mut self) -> SetFeIntW < ScisetintSpec > { SetFeIntW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < ScisetintSpec > { Reserved4W :: new (self , 27) } } # [doc = "SCI Set Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScisetintSpec ; impl crate :: RegisterSpec for ScisetintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scisetint::R`](R) reader structure"]
impl crate :: Readable for ScisetintSpec { } # [doc = "`write(|w| ..)` method takes [`scisetint::W`](W) writer structure"]
impl crate :: Writable for ScisetintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCISETINT to value 0"]
impl crate :: Resettable for ScisetintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICLEARINT (rw) register accessor: SCI Clear Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciclearint`]
module"]
# [doc (alias = "SCICLEARINT")]
pub type Sciclearint = crate :: Reg < sciclearint :: SciclearintSpec > ; # [doc = "SCI Clear Interrupt Register"]
pub mod sciclearint { # [doc = "Register `SCICLEARINT` reader"]
pub type R = crate :: R < SciclearintSpec > ; # [doc = "Register `SCICLEARINT` writer"]
pub type W = crate :: W < SciclearintSpec > ; # [doc = "Field `CLR_BRKDT_INT` reader - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrBrkdtIntR = crate :: BitReader ; # [doc = "Field `CLR_BRKDT_INT` writer - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrBrkdtIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_WAKEUP_INT` reader - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrWakeupIntR = crate :: BitReader ; # [doc = "Field `CLR_WAKEUP_INT` writer - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrWakeupIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLR_TX_INT` reader - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrTxIntR = crate :: BitReader ; # [doc = "Field `CLR_TX_INT` writer - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrTxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_INT` reader - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrRxIntR = crate :: BitReader ; # [doc = "Field `CLR_RX_INT` writer - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrRxIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLR_TX_DMA` reader - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrTxDmaR = crate :: BitReader ; # [doc = "Field `CLR_TX_DMA` writer - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrTxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_DMA` reader - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrRxDmaR = crate :: BitReader ; # [doc = "Field `CLR_RX_DMA` writer - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
pub type ClrRxDmaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_DMA_ALL` reader - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
pub type ClrRxDmaAllR = crate :: BitReader ; # [doc = "Field `CLR_RX_DMA_ALL` writer - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
pub type ClrRxDmaAllW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 23:19\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:19\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLR_PE_INT` reader - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type ClrPeIntR = crate :: BitReader ; # [doc = "Field `CLR_PE_INT` writer - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
pub type ClrPeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_OE_INT` reader - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrOeIntR = crate :: BitReader ; # [doc = "Field `CLR_OE_INT` writer - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrOeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_FE_INT` reader - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrFeIntR = crate :: BitReader ; # [doc = "Field `CLR_FE_INT` writer - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
pub type ClrFeIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:27\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:27\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_brkdt_int (& self) -> ClrBrkdtIntR { ClrBrkdtIntR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_wakeup_int (& self) -> ClrWakeupIntR { ClrWakeupIntR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_tx_int (& self) -> ClrTxIntR { ClrTxIntR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_rx_int (& self) -> ClrRxIntR { ClrRxIntR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bit 16 - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn clr_tx_dma (& self) -> ClrTxDmaR { ClrTxDmaR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
pub fn clr_rx_dma (& self) -> ClrRxDmaR { ClrRxDmaR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
# [inline (always)]
pub fn clr_rx_dma_all (& self) -> ClrRxDmaAllR { ClrRxDmaAllR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
pub fn clr_pe_int (& self) -> ClrPeIntR { ClrPeIntR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_oe_int (& self) -> ClrOeIntR { ClrOeIntR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
pub fn clr_fe_int (& self) -> ClrFeIntR { ClrFeIntR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_brkdt_int (& mut self) -> ClrBrkdtIntW < SciclearintSpec > { ClrBrkdtIntW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_wakeup_int (& mut self) -> ClrWakeupIntW < SciclearintSpec > { ClrWakeupIntW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciclearintSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_tx_int (& mut self) -> ClrTxIntW < SciclearintSpec > { ClrTxIntW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_rx_int (& mut self) -> ClrRxIntW < SciclearintSpec > { ClrRxIntW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciclearintSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 16 - 16:16\\]
Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn clr_tx_dma (& mut self) -> ClrTxDmaW < SciclearintSpec > { ClrTxDmaW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request"]
# [inline (always)]
# [must_use]
pub fn clr_rx_dma (& mut self) -> ClrRxDmaW < SciclearintSpec > { ClrRxDmaW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames"]
# [inline (always)]
# [must_use]
pub fn clr_rx_dma_all (& mut self) -> ClrRxDmaAllW < SciclearintSpec > { ClrRxDmaAllW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciclearintSpec > { Reserved3W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_pe_int (& mut self) -> ClrPeIntW < SciclearintSpec > { ClrPeIntW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_oe_int (& mut self) -> ClrOeIntW < SciclearintSpec > { ClrOeIntW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt"]
# [inline (always)]
# [must_use]
pub fn clr_fe_int (& mut self) -> ClrFeIntW < SciclearintSpec > { ClrFeIntW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciclearintSpec > { Reserved4W :: new (self , 27) } } # [doc = "SCI Clear Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciclearintSpec ; impl crate :: RegisterSpec for SciclearintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciclearint::R`](R) reader structure"]
impl crate :: Readable for SciclearintSpec { } # [doc = "`write(|w| ..)` method takes [`sciclearint::W`](W) writer structure"]
impl crate :: Writable for SciclearintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICLEARINT to value 0"]
impl crate :: Resettable for SciclearintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCISETINTLVL (rw) register accessor: SCI Set Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetintlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetintlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scisetintlvl`]
module"]
# [doc (alias = "SCISETINTLVL")]
pub type Scisetintlvl = crate :: Reg < scisetintlvl :: ScisetintlvlSpec > ; # [doc = "SCI Set Interrupt Level Register"]
pub mod scisetintlvl { # [doc = "Register `SCISETINTLVL` reader"]
pub type R = crate :: R < ScisetintlvlSpec > ; # [doc = "Register `SCISETINTLVL` writer"]
pub type W = crate :: W < ScisetintlvlSpec > ; # [doc = "Field `SET_BRKDT_INT_LVL` reader - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetBrkdtIntLvlR = crate :: BitReader ; # [doc = "Field `SET_BRKDT_INT_LVL` writer - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetBrkdtIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_WAKEUP_INT_LVL` reader - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetWakeupIntLvlR = crate :: BitReader ; # [doc = "Field `SET_WAKEUP_INT_LVL` writer - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetWakeupIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `SET_TX_INT_LVL` reader - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetTxIntLvlR = crate :: BitReader ; # [doc = "Field `SET_TX_INT_LVL` writer - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetTxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_RX_INT_LVL` reader - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxIntLvlR = crate :: BitReader ; # [doc = "Field `SET_RX_INT_LVL` writer - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 14:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 14:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SET_INC_BR_INT_LVL` reader - 15:15\\]
Reserved"]
pub type SetIncBrIntLvlR = crate :: BitReader ; # [doc = "Field `SET_INC_BR_INT_LVL` writer - 15:15\\]
Reserved"]
pub type SetIncBrIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 17:16\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 17:16\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SET_RX_DMA_ALL_INT_LVL` reader - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxDmaAllIntLvlR = crate :: BitReader ; # [doc = "Field `SET_RX_DMA_ALL_INT_LVL` writer - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetRxDmaAllIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 23:19\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 23:19\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SET_PE_INT_LVL` reader - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetPeIntLvlR = crate :: BitReader ; # [doc = "Field `SET_PE_INT_LVL` writer - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetPeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_OE_INT_LVL` reader - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetOeIntLvlR = crate :: BitReader ; # [doc = "Field `SET_OE_INT_LVL` writer - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetOeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SET_FE_INT_LVL` reader - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetFeIntLvlR = crate :: BitReader ; # [doc = "Field `SET_FE_INT_LVL` writer - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
pub type SetFeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED5` reader - 31:27\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `RESERVED5` writer - 31:27\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_brkdt_int_lvl (& self) -> SetBrkdtIntLvlR { SetBrkdtIntLvlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_wakeup_int_lvl (& self) -> SetWakeupIntLvlR { SetWakeupIntLvlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_tx_int_lvl (& self) -> SetTxIntLvlR { SetTxIntLvlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_rx_int_lvl (& self) -> SetRxIntLvlR { SetRxIntLvlR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
pub fn set_inc_br_int_lvl (& self) -> SetIncBrIntLvlR { SetIncBrIntLvlR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_rx_dma_all_int_lvl (& self) -> SetRxDmaAllIntLvlR { SetRxDmaAllIntLvlR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_pe_int_lvl (& self) -> SetPeIntLvlR { SetPeIntLvlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_oe_int_lvl (& self) -> SetOeIntLvlR { SetOeIntLvlR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
pub fn set_fe_int_lvl (& self) -> SetFeIntLvlR { SetFeIntLvlR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_brkdt_int_lvl (& mut self) -> SetBrkdtIntLvlW < ScisetintlvlSpec > { SetBrkdtIntLvlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_wakeup_int_lvl (& mut self) -> SetWakeupIntLvlW < ScisetintlvlSpec > { SetWakeupIntLvlW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < ScisetintlvlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_tx_int_lvl (& mut self) -> SetTxIntLvlW < ScisetintlvlSpec > { SetTxIntLvlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_rx_int_lvl (& mut self) -> SetRxIntLvlW < ScisetintlvlSpec > { SetRxIntLvlW :: new (self , 9) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < ScisetintlvlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 15 - 15:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn set_inc_br_int_lvl (& mut self) -> SetIncBrIntLvlW < ScisetintlvlSpec > { SetIncBrIntLvlW :: new (self , 15) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < ScisetintlvlSpec > { Reserved3W :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_rx_dma_all_int_lvl (& mut self) -> SetRxDmaAllIntLvlW < ScisetintlvlSpec > { SetRxDmaAllIntLvlW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < ScisetintlvlSpec > { Reserved4W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_pe_int_lvl (& mut self) -> SetPeIntLvlW < ScisetintlvlSpec > { SetPeIntLvlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_oe_int_lvl (& mut self) -> SetOeIntLvlW < ScisetintlvlSpec > { SetOeIntLvlW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1"]
# [inline (always)]
# [must_use]
pub fn set_fe_int_lvl (& mut self) -> SetFeIntLvlW < ScisetintlvlSpec > { SetFeIntLvlW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < ScisetintlvlSpec > { Reserved5W :: new (self , 27) } } # [doc = "SCI Set Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetintlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetintlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScisetintlvlSpec ; impl crate :: RegisterSpec for ScisetintlvlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scisetintlvl::R`](R) reader structure"]
impl crate :: Readable for ScisetintlvlSpec { } # [doc = "`write(|w| ..)` method takes [`scisetintlvl::W`](W) writer structure"]
impl crate :: Writable for ScisetintlvlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCISETINTLVL to value 0"]
impl crate :: Resettable for ScisetintlvlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICLEARINTLVL (rw) register accessor: SCI Clear Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearintlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearintlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciclearintlvl`]
module"]
# [doc (alias = "SCICLEARINTLVL")]
pub type Sciclearintlvl = crate :: Reg < sciclearintlvl :: SciclearintlvlSpec > ; # [doc = "SCI Clear Interrupt Level Register"]
pub mod sciclearintlvl { # [doc = "Register `SCICLEARINTLVL` reader"]
pub type R = crate :: R < SciclearintlvlSpec > ; # [doc = "Register `SCICLEARINTLVL` writer"]
pub type W = crate :: W < SciclearintlvlSpec > ; # [doc = "Field `CLR_BRKDT_INT_LVL` reader - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrBrkdtIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_BRKDT_INT_LVL` writer - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrBrkdtIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_WAKEUP_INT_LVL` reader - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrWakeupIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_WAKEUP_INT_LVL` writer - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrWakeupIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CLR_TX_INT_LVL` reader - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrTxIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_TX_INT_LVL` writer - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrTxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_RX_INT_LVL` reader - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrRxIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_RX_INT_LVL` writer - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrRxIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 14:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 14:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLR_INC_BR_INT_LVL` reader - "]
pub type ClrIncBrIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_INC_BR_INT_LVL` writer - "]
pub type ClrIncBrIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 17:16\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 17:16\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CLR_RX_DMA_ALL_INT_LVL` reader - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
pub type ClrRxDmaAllIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_RX_DMA_ALL_INT_LVL` writer - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
pub type ClrRxDmaAllIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 23:19\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 23:19\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `CLR_PE_INT_LVL` reader - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrPeIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_PE_INT_LVL` writer - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrPeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_OE_INT_LVL` reader - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrOeIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_OE_INT_LVL` writer - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrOeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLR_FE_INT_LVL` reader - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrFeIntLvlR = crate :: BitReader ; # [doc = "Field `CLR_FE_INT_LVL` writer - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
pub type ClrFeIntLvlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED5` reader - 31:27\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader ; # [doc = "Field `RESERVED5` writer - 31:27\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_brkdt_int_lvl (& self) -> ClrBrkdtIntLvlR { ClrBrkdtIntLvlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_wakeup_int_lvl (& self) -> ClrWakeupIntLvlR { ClrWakeupIntLvlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_tx_int_lvl (& self) -> ClrTxIntLvlR { ClrTxIntLvlR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_rx_int_lvl (& self) -> ClrRxIntLvlR { ClrRxIntLvlR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bit 15"]
# [inline (always)]
pub fn clr_inc_br_int_lvl (& self) -> ClrIncBrIntLvlR { ClrIncBrIntLvlR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
# [inline (always)]
pub fn clr_rx_dma_all_int_lvl (& self) -> ClrRxDmaAllIntLvlR { ClrRxDmaAllIntLvlR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 19) & 0x1f) as u8) } # [doc = "Bit 24 - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_pe_int_lvl (& self) -> ClrPeIntLvlR { ClrPeIntLvlR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_oe_int_lvl (& self) -> ClrOeIntLvlR { ClrOeIntLvlR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
pub fn clr_fe_int_lvl (& self) -> ClrFeIntLvlR { ClrFeIntLvlR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_brkdt_int_lvl (& mut self) -> ClrBrkdtIntLvlW < SciclearintlvlSpec > { ClrBrkdtIntLvlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_wakeup_int_lvl (& mut self) -> ClrWakeupIntLvlW < SciclearintlvlSpec > { ClrWakeupIntLvlW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciclearintlvlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bit 8 - 8:8\\]
Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_tx_int_lvl (& mut self) -> ClrTxIntLvlW < SciclearintlvlSpec > { ClrTxIntLvlW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_rx_int_lvl (& mut self) -> ClrRxIntLvlW < SciclearintlvlSpec > { ClrRxIntLvlW :: new (self , 9) } # [doc = "Bits 10:14 - 14:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciclearintlvlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bit 15"]
# [inline (always)]
# [must_use]
pub fn clr_inc_br_int_lvl (& mut self) -> ClrIncBrIntLvlW < SciclearintlvlSpec > { ClrIncBrIntLvlW :: new (self , 15) } # [doc = "Bits 16:17 - 17:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciclearintlvlSpec > { Reserved3W :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0."]
# [inline (always)]
# [must_use]
pub fn clr_rx_dma_all_int_lvl (& mut self) -> ClrRxDmaAllIntLvlW < SciclearintlvlSpec > { ClrRxDmaAllIntLvlW :: new (self , 18) } # [doc = "Bits 19:23 - 23:19\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciclearintlvlSpec > { Reserved4W :: new (self , 19) } # [doc = "Bit 24 - 24:24\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_pe_int_lvl (& mut self) -> ClrPeIntLvlW < SciclearintlvlSpec > { ClrPeIntLvlW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_oe_int_lvl (& mut self) -> ClrOeIntLvlW < SciclearintlvlSpec > { ClrOeIntLvlW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0"]
# [inline (always)]
# [must_use]
pub fn clr_fe_int_lvl (& mut self) -> ClrFeIntLvlW < SciclearintlvlSpec > { ClrFeIntLvlW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved5 (& mut self) -> Reserved5W < SciclearintlvlSpec > { Reserved5W :: new (self , 27) } } # [doc = "SCI Clear Interrupt Level Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciclearintlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciclearintlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciclearintlvlSpec ; impl crate :: RegisterSpec for SciclearintlvlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciclearintlvl::R`](R) reader structure"]
impl crate :: Readable for SciclearintlvlSpec { } # [doc = "`write(|w| ..)` method takes [`sciclearintlvl::W`](W) writer structure"]
impl crate :: Writable for SciclearintlvlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICLEARINTLVL to value 0"]
impl crate :: Resettable for SciclearintlvlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIFLR (rw) register accessor: SCI Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciflr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciflr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciflr`]
module"]
# [doc (alias = "SCIFLR")]
pub type Sciflr = crate :: Reg < sciflr :: SciflrSpec > ; # [doc = "SCI Flags Register"]
pub mod sciflr { # [doc = "Register `SCIFLR` reader"]
pub type R = crate :: R < SciflrSpec > ; # [doc = "Register `SCIFLR` writer"]
pub type W = crate :: W < SciflrSpec > ; # [doc = "Field `BRKDT` reader - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
pub type BrkdtR = crate :: BitReader ; # [doc = "Field `BRKDT` writer - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
pub type BrkdtW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKEUP` reader - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
pub type WakeupR = crate :: BitReader ; # [doc = "Field `WAKEUP` writer - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
pub type WakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDLE` reader - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
pub type IdleR = crate :: BitReader ; # [doc = "Field `IDLE` writer - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
pub type IdleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Bus_busy_flag` reader - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
pub type BusBusyFlagR = crate :: BitReader ; # [doc = "Field `Bus_busy_flag` writer - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
pub type BusBusyFlagW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:4\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:4\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TXRDY` reader - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
pub type TxrdyR = crate :: BitReader ; # [doc = "Field `TXRDY` writer - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
pub type TxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXRDY` reader - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
pub type RxrdyR = crate :: BitReader ; # [doc = "Field `RXRDY` writer - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
pub type RxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXWAKE` reader - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
pub type TxwakeR = crate :: BitReader ; # [doc = "Field `TXWAKE` writer - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
pub type TxwakeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_EMPTY` reader - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
pub type TxEmptyR = crate :: BitReader ; # [doc = "Field `TX_EMPTY` writer - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
pub type TxEmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXWAKE` reader - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
pub type RxwakeR = crate :: BitReader ; # [doc = "Field `RXWAKE` writer - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
pub type RxwakeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED2` reader - 23:13\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED2` writer - 23:13\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; # [doc = "Field `PE` reader - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
pub type PeR = crate :: BitReader ; # [doc = "Field `PE` writer - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
pub type PeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OE` reader - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
pub type OeR = crate :: BitReader ; # [doc = "Field `OE` writer - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
pub type OeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FE` reader - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
pub type FeR = crate :: BitReader ; # [doc = "Field `FE` writer - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
pub type FeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED3` reader - 31:27\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 31:27\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
# [inline (always)]
pub fn brkdt (& self) -> BrkdtR { BrkdtR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
# [inline (always)]
pub fn wakeup (& self) -> WakeupR { WakeupR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
# [inline (always)]
pub fn idle (& self) -> IdleR { IdleR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
# [inline (always)]
pub fn bus_busy_flag (& self) -> BusBusyFlagR { BusBusyFlagR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
# [inline (always)]
pub fn txrdy (& self) -> TxrdyR { TxrdyR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
# [inline (always)]
pub fn rxrdy (& self) -> RxrdyR { RxrdyR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
# [inline (always)]
pub fn txwake (& self) -> TxwakeR { TxwakeR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
# [inline (always)]
pub fn tx_empty (& self) -> TxEmptyR { TxEmptyR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
# [inline (always)]
pub fn rxwake (& self) -> RxwakeR { RxwakeR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:23 - 23:13\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 13) & 0x07ff) as u16) } # [doc = "Bit 24 - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
# [inline (always)]
pub fn pe (& self) -> PeR { PeR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
# [inline (always)]
pub fn oe (& self) -> OeR { OeR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
# [inline (always)]
pub fn fe (& self) -> FeR { FeR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin."]
# [inline (always)]
# [must_use]
pub fn brkdt (& mut self) -> BrkdtW < SciflrSpec > { BrkdtW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode."]
# [inline (always)]
# [must_use]
pub fn wakeup (& mut self) -> WakeupW < SciflrSpec > { WakeupW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream."]
# [inline (always)]
# [must_use]
pub fn idle (& mut self) -> IdleW < SciflrSpec > { IdleW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
This bit indicates whether the receiver is in the process of receiving a frame."]
# [inline (always)]
# [must_use]
pub fn bus_busy_flag (& mut self) -> BusBusyFlagW < SciflrSpec > { BusBusyFlagW :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciflrSpec > { Reserved1W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character."]
# [inline (always)]
# [must_use]
pub fn txrdy (& mut self) -> TxrdyW < SciflrSpec > { TxrdyW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA."]
# [inline (always)]
# [must_use]
pub fn rxrdy (& mut self) -> RxrdyW < SciflrSpec > { RxrdyW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format"]
# [inline (always)]
# [must_use]
pub fn txwake (& mut self) -> TxwakeW < SciflrSpec > { TxwakeW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Transmitter empty flag. The value of this flag indicates the contents of the transmitterΓÇÖs buffer register (SCITD) and shift register (SCITXSHF)"]
# [inline (always)]
# [must_use]
pub fn tx_empty (& mut self) -> TxEmptyW < SciflrSpec > { TxEmptyW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address"]
# [inline (always)]
# [must_use]
pub fn rxwake (& mut self) -> RxwakeW < SciflrSpec > { RxwakeW :: new (self , 12) } # [doc = "Bits 13:23 - 23:13\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciflrSpec > { Reserved2W :: new (self , 13) } # [doc = "Bit 24 - 24:24\\]
SCI parity error flag. This bit is set when a parity error is detected in the received data"]
# [inline (always)]
# [must_use]
pub fn pe (& mut self) -> PeW < SciflrSpec > { PeW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD"]
# [inline (always)]
# [must_use]
pub fn oe (& mut self) -> OeW < SciflrSpec > { OeW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0"]
# [inline (always)]
# [must_use]
pub fn fe (& mut self) -> FeW < SciflrSpec > { FeW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciflrSpec > { Reserved3W :: new (self , 27) } } # [doc = "SCI Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciflr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciflr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciflrSpec ; impl crate :: RegisterSpec for SciflrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciflr::R`](R) reader structure"]
impl crate :: Readable for SciflrSpec { } # [doc = "`write(|w| ..)` method takes [`sciflr::W`](W) writer structure"]
impl crate :: Writable for SciflrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIFLR to value 0"]
impl crate :: Resettable for SciflrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIINTVECT0 (rw) register accessor: SCI Interrupt Offset Vector 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciintvect0`]
module"]
# [doc (alias = "SCIINTVECT0")]
pub type Sciintvect0 = crate :: Reg < sciintvect0 :: Sciintvect0Spec > ; # [doc = "SCI Interrupt Offset Vector 0 Register"]
pub mod sciintvect0 { # [doc = "Register `SCIINTVECT0` reader"]
pub type R = crate :: R < Sciintvect0Spec > ; # [doc = "Register `SCIINTVECT0` writer"]
pub type W = crate :: W < Sciintvect0Spec > ; # [doc = "Field `INTVECT0` reader - 3:0\\]
Interrupt vector offset for INT0"]
pub type Intvect0R = crate :: FieldReader ; # [doc = "Field `INTVECT0` writer - 3:0\\]
Interrupt vector offset for INT0"]
pub type Intvect0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT0"]
# [inline (always)]
pub fn intvect0 (& self) -> Intvect0R { Intvect0R :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT0"]
# [inline (always)]
# [must_use]
pub fn intvect0 (& mut self) -> Intvect0W < Sciintvect0Spec > { Intvect0W :: new (self , 0) } } # [doc = "SCI Interrupt Offset Vector 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sciintvect0Spec ; impl crate :: RegisterSpec for Sciintvect0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciintvect0::R`](R) reader structure"]
impl crate :: Readable for Sciintvect0Spec { } # [doc = "`write(|w| ..)` method takes [`sciintvect0::W`](W) writer structure"]
impl crate :: Writable for Sciintvect0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIINTVECT0 to value 0"]
impl crate :: Resettable for Sciintvect0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIINTVECT1 (rw) register accessor: SCI Interrupt Offset Vector 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciintvect1`]
module"]
# [doc (alias = "SCIINTVECT1")]
pub type Sciintvect1 = crate :: Reg < sciintvect1 :: Sciintvect1Spec > ; # [doc = "SCI Interrupt Offset Vector 1 Register"]
pub mod sciintvect1 { # [doc = "Register `SCIINTVECT1` reader"]
pub type R = crate :: R < Sciintvect1Spec > ; # [doc = "Register `SCIINTVECT1` writer"]
pub type W = crate :: W < Sciintvect1Spec > ; # [doc = "Field `INTVECT1` reader - 3:0\\]
Interrupt vector offset for INT1"]
pub type Intvect1R = crate :: FieldReader ; # [doc = "Field `INTVECT1` writer - 3:0\\]
Interrupt vector offset for INT1"]
pub type Intvect1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT1"]
# [inline (always)]
pub fn intvect1 (& self) -> Intvect1R { Intvect1R :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Interrupt vector offset for INT1"]
# [inline (always)]
# [must_use]
pub fn intvect1 (& mut self) -> Intvect1W < Sciintvect1Spec > { Intvect1W :: new (self , 0) } } # [doc = "SCI Interrupt Offset Vector 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sciintvect1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciintvect1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sciintvect1Spec ; impl crate :: RegisterSpec for Sciintvect1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciintvect1::R`](R) reader structure"]
impl crate :: Readable for Sciintvect1Spec { } # [doc = "`write(|w| ..)` method takes [`sciintvect1::W`](W) writer structure"]
impl crate :: Writable for Sciintvect1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIINTVECT1 to value 0"]
impl crate :: Resettable for Sciintvect1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCICHAR (rw) register accessor: SCI Character Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scichar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scichar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scichar`]
module"]
# [doc (alias = "SCICHAR")]
pub type Scichar = crate :: Reg < scichar :: ScicharSpec > ; # [doc = "SCI Character Control Register"]
pub mod scichar { # [doc = "Register `SCICHAR` reader"]
pub type R = crate :: R < ScicharSpec > ; # [doc = "Register `SCICHAR` writer"]
pub type W = crate :: W < ScicharSpec > ; # [doc = "Field `CHAR` reader - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
pub type CharR = crate :: FieldReader ; # [doc = "Field `CHAR` writer - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
pub type CharW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
# [inline (always)]
pub fn char (& self) -> CharR { CharR :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Sets the SCI data length from 1 to 8 bits"]
# [inline (always)]
# [must_use]
pub fn char (& mut self) -> CharW < ScicharSpec > { CharW :: new (self , 0) } } # [doc = "SCI Character Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scichar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scichar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScicharSpec ; impl crate :: RegisterSpec for ScicharSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scichar::R`](R) reader structure"]
impl crate :: Readable for ScicharSpec { } # [doc = "`write(|w| ..)` method takes [`scichar::W`](W) writer structure"]
impl crate :: Writable for ScicharSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCICHAR to value 0"]
impl crate :: Resettable for ScicharSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIBAUD (rw) register accessor: SCI Baud Rate Selection Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scibaud::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scibaud::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scibaud`]
module"]
# [doc (alias = "SCIBAUD")]
pub type Scibaud = crate :: Reg < scibaud :: ScibaudSpec > ; # [doc = "SCI Baud Rate Selection Register"]
pub mod scibaud { # [doc = "Register `SCIBAUD` reader"]
pub type R = crate :: R < ScibaudSpec > ; # [doc = "Register `SCIBAUD` writer"]
pub type W = crate :: W < ScibaudSpec > ; # [doc = "Field `BAUD` reader - 23:0\\]
SCI 24-bit baud selection"]
pub type BaudR = crate :: FieldReader < u32 > ; # [doc = "Field `BAUD` writer - 23:0\\]
SCI 24-bit baud selection"]
pub type BaudW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:23 - 23:0\\]
SCI 24-bit baud selection"]
# [inline (always)]
pub fn baud (& self) -> BaudR { BaudR :: new (self . bits & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:23 - 23:0\\]
SCI 24-bit baud selection"]
# [inline (always)]
# [must_use]
pub fn baud (& mut self) -> BaudW < ScibaudSpec > { BaudW :: new (self , 0) } } # [doc = "SCI Baud Rate Selection Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scibaud::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scibaud::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScibaudSpec ; impl crate :: RegisterSpec for ScibaudSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scibaud::R`](R) reader structure"]
impl crate :: Readable for ScibaudSpec { } # [doc = "`write(|w| ..)` method takes [`scibaud::W`](W) writer structure"]
impl crate :: Writable for ScibaudSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIBAUD to value 0"]
impl crate :: Resettable for ScibaudSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIED (rw) register accessor: Receiver Emulation Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scied::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scied::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scied`]
module"]
# [doc (alias = "SCIED")]
pub type Scied = crate :: Reg < scied :: SciedSpec > ; # [doc = "Receiver Emulation Data Buffer"]
pub mod scied { # [doc = "Register `SCIED` reader"]
pub type R = crate :: R < SciedSpec > ; # [doc = "Register `SCIED` writer"]
pub type W = crate :: W < SciedSpec > ; # [doc = "Field `ED` reader - 7:0\\]
Receiver Emulation Data Buffer"]
pub type EdR = crate :: FieldReader ; # [doc = "Field `ED` writer - 7:0\\]
Receiver Emulation Data Buffer"]
pub type EdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Receiver Emulation Data Buffer"]
# [inline (always)]
pub fn ed (& self) -> EdR { EdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Receiver Emulation Data Buffer"]
# [inline (always)]
# [must_use]
pub fn ed (& mut self) -> EdW < SciedSpec > { EdW :: new (self , 0) } } # [doc = "Receiver Emulation Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scied::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scied::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciedSpec ; impl crate :: RegisterSpec for SciedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scied::R`](R) reader structure"]
impl crate :: Readable for SciedSpec { } # [doc = "`write(|w| ..)` method takes [`scied::W`](W) writer structure"]
impl crate :: Writable for SciedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIED to value 0"]
impl crate :: Resettable for SciedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIRD (rw) register accessor: Receiver Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scird::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scird::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scird`]
module"]
# [doc (alias = "SCIRD")]
pub type Scird = crate :: Reg < scird :: ScirdSpec > ; # [doc = "Receiver Data Buffer"]
pub mod scird { # [doc = "Register `SCIRD` reader"]
pub type R = crate :: R < ScirdSpec > ; # [doc = "Register `SCIRD` writer"]
pub type W = crate :: W < ScirdSpec > ; # [doc = "Field `RD` reader - 7:0\\]
Contains received data."]
pub type RdR = crate :: FieldReader ; # [doc = "Field `RD` writer - 7:0\\]
Contains received data."]
pub type RdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Contains received data."]
# [inline (always)]
pub fn rd (& self) -> RdR { RdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Contains received data."]
# [inline (always)]
# [must_use]
pub fn rd (& mut self) -> RdW < ScirdSpec > { RdW :: new (self , 0) } } # [doc = "Receiver Data Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`scird::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scird::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScirdSpec ; impl crate :: RegisterSpec for ScirdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scird::R`](R) reader structure"]
impl crate :: Readable for ScirdSpec { } # [doc = "`write(|w| ..)` method takes [`scird::W`](W) writer structure"]
impl crate :: Writable for ScirdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIRD to value 0"]
impl crate :: Resettable for ScirdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCITD (rw) register accessor: Transmit Data Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scitd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scitd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scitd`]
module"]
# [doc (alias = "SCITD")]
pub type Scitd = crate :: Reg < scitd :: ScitdSpec > ; # [doc = "Transmit Data Buffer Register"]
pub mod scitd { # [doc = "Register `SCITD` reader"]
pub type R = crate :: R < ScitdSpec > ; # [doc = "Register `SCITD` writer"]
pub type W = crate :: W < ScitdSpec > ; # [doc = "Field `TD` reader - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
pub type TdR = crate :: FieldReader ; # [doc = "Field `TD` writer - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
pub type TdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
# [inline (always)]
pub fn td (& self) -> TdR { TdR :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."]
# [inline (always)]
# [must_use]
pub fn td (& mut self) -> TdW < ScitdSpec > { TdW :: new (self , 0) } } # [doc = "Transmit Data Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scitd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scitd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScitdSpec ; impl crate :: RegisterSpec for ScitdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`scitd::R`](R) reader structure"]
impl crate :: Readable for ScitdSpec { } # [doc = "`write(|w| ..)` method takes [`scitd::W`](W) writer structure"]
impl crate :: Writable for ScitdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCITD to value 0"]
impl crate :: Resettable for ScitdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO0 (rw) register accessor: SCI Pin I/O Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio0`]
module"]
# [doc (alias = "SCIPIO0")]
pub type Scipio0 = crate :: Reg < scipio0 :: Scipio0Spec > ; # [doc = "SCI Pin I/O Control Register 0"]
pub mod scipio0 { # [doc = "Register `SCIPIO0` reader"]
pub type R = crate :: R < Scipio0Spec > ; # [doc = "Register `SCIPIO0` writer"]
pub type W = crate :: W < Scipio0Spec > ; # [doc = "Field `CLK_FUNC` reader - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
pub type ClkFuncR = crate :: BitReader ; # [doc = "Field `CLK_FUNC` writer - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
pub type ClkFuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_FUNC` reader - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxFuncR = crate :: BitReader ; # [doc = "Field `RX_FUNC` writer - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxFuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_FUNC` reader - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
pub type TxFuncR = crate :: BitReader ; # [doc = "Field `TX_FUNC` writer - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
pub type TxFuncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
# [inline (always)]
pub fn clk_func (& self) -> ClkFuncR { ClkFuncR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
pub fn rx_func (& self) -> RxFuncR { RxFuncR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
# [inline (always)]
pub fn tx_func (& self) -> TxFuncR { TxFuncR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin."]
# [inline (always)]
# [must_use]
pub fn clk_func (& mut self) -> ClkFuncW < Scipio0Spec > { ClkFuncW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn rx_func (& mut self) -> RxFuncW < Scipio0Spec > { RxFuncW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin."]
# [inline (always)]
# [must_use]
pub fn tx_func (& mut self) -> TxFuncW < Scipio0Spec > { TxFuncW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio0Spec ; impl crate :: RegisterSpec for Scipio0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio0::R`](R) reader structure"]
impl crate :: Readable for Scipio0Spec { } # [doc = "`write(|w| ..)` method takes [`scipio0::W`](W) writer structure"]
impl crate :: Writable for Scipio0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO0 to value 0"]
impl crate :: Resettable for Scipio0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO1 (rw) register accessor: SCI Pin I/O Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio1`]
module"]
# [doc (alias = "SCIPIO1")]
pub type Scipio1 = crate :: Reg < scipio1 :: Scipio1Spec > ; # [doc = "SCI Pin I/O Control Register 1"]
pub mod scipio1 { # [doc = "Register `SCIPIO1` reader"]
pub type R = crate :: R < Scipio1Spec > ; # [doc = "Register `SCIPIO1` writer"]
pub type W = crate :: W < Scipio1Spec > ; # [doc = "Field `CLK_DIR` reader - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
pub type ClkDirR = crate :: BitReader ; # [doc = "Field `CLK_DIR` writer - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
pub type ClkDirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DIR` reader - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxDirR = crate :: BitReader ; # [doc = "Field `RX_DIR` writer - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
pub type RxDirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DIR` reader - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
pub type TxDirR = crate :: BitReader ; # [doc = "Field `TX_DIR` writer - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
pub type TxDirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
# [inline (always)]
pub fn clk_dir (& self) -> ClkDirR { ClkDirR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
pub fn rx_dir (& self) -> RxDirR { RxDirR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
# [inline (always)]
pub fn tx_dir (& self) -> TxDirR { TxDirR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn clk_dir (& mut self) -> ClkDirW < Scipio1Spec > { ClkDirW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn rx_dir (& mut self) -> RxDirW < Scipio1Spec > { RxDirW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin"]
# [inline (always)]
# [must_use]
pub fn tx_dir (& mut self) -> TxDirW < Scipio1Spec > { TxDirW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio1Spec ; impl crate :: RegisterSpec for Scipio1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio1::R`](R) reader structure"]
impl crate :: Readable for Scipio1Spec { } # [doc = "`write(|w| ..)` method takes [`scipio1::W`](W) writer structure"]
impl crate :: Writable for Scipio1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO1 to value 0"]
impl crate :: Resettable for Scipio1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO2 (rw) register accessor: SCI Pin I/O Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio2`]
module"]
# [doc (alias = "SCIPIO2")]
pub type Scipio2 = crate :: Reg < scipio2 :: Scipio2Spec > ; # [doc = "SCI Pin I/O Control Register 2"]
pub mod scipio2 { # [doc = "Register `SCIPIO2` reader"]
pub type R = crate :: R < Scipio2Spec > ; # [doc = "Register `SCIPIO2` writer"]
pub type W = crate :: W < Scipio2Spec > ; # [doc = "Field `CLK_DATA_IN` reader - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
pub type ClkDataInR = crate :: BitReader ; # [doc = "Field `CLK_DATA_IN` writer - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
pub type ClkDataInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_IN` reader - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
pub type RxDataInR = crate :: BitReader ; # [doc = "Field `RX_DATA_IN` writer - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
pub type RxDataInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_IN` reader - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
pub type TxDataInR = crate :: BitReader ; # [doc = "Field `TX_DATA_IN` writer - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
pub type TxDataInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
# [inline (always)]
pub fn clk_data_in (& self) -> ClkDataInR { ClkDataInR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
# [inline (always)]
pub fn rx_data_in (& self) -> RxDataInR { RxDataInR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
# [inline (always)]
pub fn tx_data_in (& self) -> TxDataInR { TxDataInR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high."]
# [inline (always)]
# [must_use]
pub fn clk_data_in (& mut self) -> ClkDataInW < Scipio2Spec > { ClkDataInW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high."]
# [inline (always)]
# [must_use]
pub fn rx_data_in (& mut self) -> RxDataInW < Scipio2Spec > { RxDataInW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high."]
# [inline (always)]
# [must_use]
pub fn tx_data_in (& mut self) -> TxDataInW < Scipio2Spec > { TxDataInW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio2Spec ; impl crate :: RegisterSpec for Scipio2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio2::R`](R) reader structure"]
impl crate :: Readable for Scipio2Spec { } # [doc = "`write(|w| ..)` method takes [`scipio2::W`](W) writer structure"]
impl crate :: Writable for Scipio2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO2 to value 0"]
impl crate :: Resettable for Scipio2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO3 (rw) register accessor: SCI Pin I/O Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio3`]
module"]
# [doc (alias = "SCIPIO3")]
pub type Scipio3 = crate :: Reg < scipio3 :: Scipio3Spec > ; # [doc = "SCI Pin I/O Control Register 3"]
pub mod scipio3 { # [doc = "Register `SCIPIO3` reader"]
pub type R = crate :: R < Scipio3Spec > ; # [doc = "Register `SCIPIO3` writer"]
pub type W = crate :: W < Scipio3Spec > ; # [doc = "Field `CLK_DATA_OUT` reader - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
pub type ClkDataOutR = crate :: BitReader ; # [doc = "Field `CLK_DATA_OUT` writer - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
pub type ClkDataOutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_OUT` reader - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
pub type RxDataOutR = crate :: BitReader ; # [doc = "Field `RX_DATA_OUT` writer - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
pub type RxDataOutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_OUT` reader - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
pub type TxDataOutR = crate :: BitReader ; # [doc = "Field `TX_DATA_OUT` writer - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
pub type TxDataOutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
# [inline (always)]
pub fn clk_data_out (& self) -> ClkDataOutR { ClkDataOutR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
# [inline (always)]
pub fn rx_data_out (& self) -> RxDataOutR { RxDataOutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
# [inline (always)]
pub fn tx_data_out (& self) -> TxDataOutR { TxDataOutR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high)."]
# [inline (always)]
# [must_use]
pub fn clk_data_out (& mut self) -> ClkDataOutW < Scipio3Spec > { ClkDataOutW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high)."]
# [inline (always)]
# [must_use]
pub fn rx_data_out (& mut self) -> RxDataOutW < Scipio3Spec > { RxDataOutW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high)."]
# [inline (always)]
# [must_use]
pub fn tx_data_out (& mut self) -> TxDataOutW < Scipio3Spec > { TxDataOutW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio3Spec ; impl crate :: RegisterSpec for Scipio3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio3::R`](R) reader structure"]
impl crate :: Readable for Scipio3Spec { } # [doc = "`write(|w| ..)` method takes [`scipio3::W`](W) writer structure"]
impl crate :: Writable for Scipio3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO3 to value 0"]
impl crate :: Resettable for Scipio3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO4 (rw) register accessor: SCI Pin I/O Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio4`]
module"]
# [doc (alias = "SCIPIO4")]
pub type Scipio4 = crate :: Reg < scipio4 :: Scipio4Spec > ; # [doc = "SCI Pin I/O Control Register 4"]
pub mod scipio4 { # [doc = "Register `SCIPIO4` reader"]
pub type R = crate :: R < Scipio4Spec > ; # [doc = "Register `SCIPIO4` writer"]
pub type W = crate :: W < Scipio4Spec > ; # [doc = "Field `CLK_DATA_SET` reader - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
pub type ClkDataSetR = crate :: BitReader ; # [doc = "Field `CLK_DATA_SET` writer - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
pub type ClkDataSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_SET` reader - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
pub type RxDataSetR = crate :: BitReader ; # [doc = "Field `RX_DATA_SET` writer - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
pub type RxDataSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_SET` reader - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataSetR = crate :: BitReader ; # [doc = "Field `TX_DATA_SET` writer - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
# [inline (always)]
pub fn clk_data_set (& self) -> ClkDataSetR { ClkDataSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
# [inline (always)]
pub fn rx_data_set (& self) -> RxDataSetR { RxDataSetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn tx_data_set (& self) -> TxDataSetR { TxDataSetR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn clk_data_set (& mut self) -> ClkDataSetW < Scipio4Spec > { ClkDataSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn rx_data_set (& mut self) -> RxDataSetW < Scipio4Spec > { RxDataSetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn tx_data_set (& mut self) -> TxDataSetW < Scipio4Spec > { TxDataSetW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio4Spec ; impl crate :: RegisterSpec for Scipio4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio4::R`](R) reader structure"]
impl crate :: Readable for Scipio4Spec { } # [doc = "`write(|w| ..)` method takes [`scipio4::W`](W) writer structure"]
impl crate :: Writable for Scipio4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO4 to value 0"]
impl crate :: Resettable for Scipio4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO5 (rw) register accessor: SCI Pin I/O Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio5`]
module"]
# [doc (alias = "SCIPIO5")]
pub type Scipio5 = crate :: Reg < scipio5 :: Scipio5Spec > ; # [doc = "SCI Pin I/O Control Register 5"]
pub mod scipio5 { # [doc = "Register `SCIPIO5` reader"]
pub type R = crate :: R < Scipio5Spec > ; # [doc = "Register `SCIPIO5` writer"]
pub type W = crate :: W < Scipio5Spec > ; # [doc = "Field `CLK_DATA_CLR` reader - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type ClkDataClrR = crate :: BitReader ; # [doc = "Field `CLK_DATA_CLR` writer - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type ClkDataClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_DATA_CLR` reader - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type RxDataClrR = crate :: BitReader ; # [doc = "Field `RX_DATA_CLR` writer - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type RxDataClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_DATA_CLR` reader - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataClrR = crate :: BitReader ; # [doc = "Field `TX_DATA_CLR` writer - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
pub type TxDataClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn clk_data_clr (& self) -> ClkDataClrR { ClkDataClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn rx_data_clr (& self) -> RxDataClrR { RxDataClrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
pub fn tx_data_clr (& self) -> TxDataClrR { TxDataClrR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn clk_data_clr (& mut self) -> ClkDataClrW < Scipio5Spec > { ClkDataClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn rx_data_clr (& mut self) -> RxDataClrW < Scipio5Spec > { RxDataClrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.)"]
# [inline (always)]
# [must_use]
pub fn tx_data_clr (& mut self) -> TxDataClrW < Scipio5Spec > { TxDataClrW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio5Spec ; impl crate :: RegisterSpec for Scipio5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio5::R`](R) reader structure"]
impl crate :: Readable for Scipio5Spec { } # [doc = "`write(|w| ..)` method takes [`scipio5::W`](W) writer structure"]
impl crate :: Writable for Scipio5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO5 to value 0"]
impl crate :: Resettable for Scipio5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO6 (rw) register accessor: SCI Pin I/O Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio6`]
module"]
# [doc (alias = "SCIPIO6")]
pub type Scipio6 = crate :: Reg < scipio6 :: Scipio6Spec > ; # [doc = "SCI Pin I/O Control Register 6"]
pub mod scipio6 { # [doc = "Register `SCIPIO6` reader"]
pub type R = crate :: R < Scipio6Spec > ; # [doc = "Register `SCIPIO6` writer"]
pub type W = crate :: W < Scipio6Spec > ; # [doc = "Field `CLK_PDR` reader - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
pub type ClkPdrR = crate :: BitReader ; # [doc = "Field `CLK_PDR` writer - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
pub type ClkPdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_PDR` reader - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
pub type RxPdrR = crate :: BitReader ; # [doc = "Field `RX_PDR` writer - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
pub type RxPdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_PDR` reader - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
pub type TxPdrR = crate :: BitReader ; # [doc = "Field `TX_PDR` writer - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
pub type TxPdrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
# [inline (always)]
pub fn clk_pdr (& self) -> ClkPdrR { ClkPdrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
# [inline (always)]
pub fn rx_pdr (& self) -> RxPdrR { RxPdrR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
# [inline (always)]
pub fn tx_pdr (& self) -> TxPdrR { TxPdrR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1"]
# [inline (always)]
# [must_use]
pub fn clk_pdr (& mut self) -> ClkPdrW < Scipio6Spec > { ClkPdrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1"]
# [inline (always)]
# [must_use]
pub fn rx_pdr (& mut self) -> RxPdrW < Scipio6Spec > { RxPdrW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1"]
# [inline (always)]
# [must_use]
pub fn tx_pdr (& mut self) -> TxPdrW < Scipio6Spec > { TxPdrW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio6Spec ; impl crate :: RegisterSpec for Scipio6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio6::R`](R) reader structure"]
impl crate :: Readable for Scipio6Spec { } # [doc = "`write(|w| ..)` method takes [`scipio6::W`](W) writer structure"]
impl crate :: Writable for Scipio6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO6 to value 0"]
impl crate :: Resettable for Scipio6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO7 (rw) register accessor: SCI Pin I/O Control Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio7`]
module"]
# [doc (alias = "SCIPIO7")]
pub type Scipio7 = crate :: Reg < scipio7 :: Scipio7Spec > ; # [doc = "SCI Pin I/O Control Register 7"]
pub mod scipio7 { # [doc = "Register `SCIPIO7` reader"]
pub type R = crate :: R < Scipio7Spec > ; # [doc = "Register `SCIPIO7` writer"]
pub type W = crate :: W < Scipio7Spec > ; # [doc = "Field `CLK_PD` reader - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
pub type ClkPdR = crate :: BitReader ; # [doc = "Field `CLK_PD` writer - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
pub type ClkPdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_PD` reader - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
pub type RxPdR = crate :: BitReader ; # [doc = "Field `RX_PD` writer - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
pub type RxPdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_PD` reader - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
pub type TxPdR = crate :: BitReader ; # [doc = "Field `TX_PD` writer - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
pub type TxPdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
# [inline (always)]
pub fn clk_pd (& self) -> ClkPdR { ClkPdR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
# [inline (always)]
pub fn rx_pd (& self) -> RxPdR { RxPdR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
# [inline (always)]
pub fn tx_pd (& self) -> TxPdR { TxPdR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled."]
# [inline (always)]
# [must_use]
pub fn clk_pd (& mut self) -> ClkPdW < Scipio7Spec > { ClkPdW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled."]
# [inline (always)]
# [must_use]
pub fn rx_pd (& mut self) -> RxPdW < Scipio7Spec > { RxPdW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled."]
# [inline (always)]
# [must_use]
pub fn tx_pd (& mut self) -> TxPdW < Scipio7Spec > { TxPdW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio7Spec ; impl crate :: RegisterSpec for Scipio7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio7::R`](R) reader structure"]
impl crate :: Readable for Scipio7Spec { } # [doc = "`write(|w| ..)` method takes [`scipio7::W`](W) writer structure"]
impl crate :: Writable for Scipio7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO7 to value 0"]
impl crate :: Resettable for Scipio7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO8 (rw) register accessor: SCI Pin I/O Control Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio8`]
module"]
# [doc (alias = "SCIPIO8")]
pub type Scipio8 = crate :: Reg < scipio8 :: Scipio8Spec > ; # [doc = "SCI Pin I/O Control Register 8"]
pub mod scipio8 { # [doc = "Register `SCIPIO8` reader"]
pub type R = crate :: R < Scipio8Spec > ; # [doc = "Register `SCIPIO8` writer"]
pub type W = crate :: W < Scipio8Spec > ; # [doc = "Field `CLK_PSL` reader - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
pub type ClkPslR = crate :: BitReader ; # [doc = "Field `CLK_PSL` writer - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
pub type ClkPslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_PSL` reader - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
pub type RxPslR = crate :: BitReader ; # [doc = "Field `RX_PSL` writer - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
pub type RxPslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_PSL` reader - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
pub type TxPslR = crate :: BitReader ; # [doc = "Field `TX_PSL` writer - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
pub type TxPslW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
# [inline (always)]
pub fn clk_psl (& self) -> ClkPslR { ClkPslR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
# [inline (always)]
pub fn rx_psl (& self) -> RxPslR { RxPslR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
# [inline (always)]
pub fn tx_psl (& self) -> TxPslR { TxPslR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin."]
# [inline (always)]
# [must_use]
pub fn clk_psl (& mut self) -> ClkPslW < Scipio8Spec > { ClkPslW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin."]
# [inline (always)]
# [must_use]
pub fn rx_psl (& mut self) -> RxPslW < Scipio8Spec > { RxPslW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin."]
# [inline (always)]
# [must_use]
pub fn tx_psl (& mut self) -> TxPslW < Scipio8Spec > { TxPslW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio8Spec ; impl crate :: RegisterSpec for Scipio8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio8::R`](R) reader structure"]
impl crate :: Readable for Scipio8Spec { } # [doc = "`write(|w| ..)` method takes [`scipio8::W`](W) writer structure"]
impl crate :: Writable for Scipio8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO8 to value 0"]
impl crate :: Resettable for Scipio8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved2`]
module"]
# [doc (alias = "RESERVED2")]
pub type Reserved2 = crate :: Reg < reserved2 :: Reserved2Spec > ; # [doc = "Reserved"]
pub mod reserved2 { # [doc = "Register `RESERVED2` reader"]
pub type R = crate :: R < Reserved2Spec > ; # [doc = "Register `RESERVED2` writer"]
pub type W = crate :: W < Reserved2Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved2Spec ; impl crate :: RegisterSpec for Reserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved2::R`](R) reader structure"]
impl crate :: Readable for Reserved2Spec { } # [doc = "`write(|w| ..)` method takes [`reserved2::W`](W) writer structure"]
impl crate :: Writable for Reserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED2 to value 0"]
impl crate :: Resettable for Reserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved3`]
module"]
# [doc (alias = "RESERVED3")]
pub type Reserved3 = crate :: Reg < reserved3 :: Reserved3Spec > ; # [doc = "Reserved"]
pub mod reserved3 { # [doc = "Register `RESERVED3` reader"]
pub type R = crate :: R < Reserved3Spec > ; # [doc = "Register `RESERVED3` writer"]
pub type W = crate :: W < Reserved3Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved3Spec ; impl crate :: RegisterSpec for Reserved3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved3::R`](R) reader structure"]
impl crate :: Readable for Reserved3Spec { } # [doc = "`write(|w| ..)` method takes [`reserved3::W`](W) writer structure"]
impl crate :: Writable for Reserved3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED3 to value 0"]
impl crate :: Resettable for Reserved3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED4 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved4`]
module"]
# [doc (alias = "RESERVED4")]
pub type Reserved4 = crate :: Reg < reserved4 :: Reserved4Spec > ; # [doc = "Reserved"]
pub mod reserved4 { # [doc = "Register `RESERVED4` reader"]
pub type R = crate :: R < Reserved4Spec > ; # [doc = "Register `RESERVED4` writer"]
pub type W = crate :: W < Reserved4Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved4Spec ; impl crate :: RegisterSpec for Reserved4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved4::R`](R) reader structure"]
impl crate :: Readable for Reserved4Spec { } # [doc = "`write(|w| ..)` method takes [`reserved4::W`](W) writer structure"]
impl crate :: Writable for Reserved4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED4 to value 0"]
impl crate :: Resettable for Reserved4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED5 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved5`]
module"]
# [doc (alias = "RESERVED5")]
pub type Reserved5 = crate :: Reg < reserved5 :: Reserved5Spec > ; # [doc = "Reserved"]
pub mod reserved5 { # [doc = "Register `RESERVED5` reader"]
pub type R = crate :: R < Reserved5Spec > ; # [doc = "Register `RESERVED5` writer"]
pub type W = crate :: W < Reserved5Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved5Spec ; impl crate :: RegisterSpec for Reserved5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved5::R`](R) reader structure"]
impl crate :: Readable for Reserved5Spec { } # [doc = "`write(|w| ..)` method takes [`reserved5::W`](W) writer structure"]
impl crate :: Writable for Reserved5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED5 to value 0"]
impl crate :: Resettable for Reserved5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED6 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved6`]
module"]
# [doc (alias = "RESERVED6")]
pub type Reserved6 = crate :: Reg < reserved6 :: Reserved6Spec > ; # [doc = "Reserved"]
pub mod reserved6 { # [doc = "Register `RESERVED6` reader"]
pub type R = crate :: R < Reserved6Spec > ; # [doc = "Register `RESERVED6` writer"]
pub type W = crate :: W < Reserved6Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved6Spec ; impl crate :: RegisterSpec for Reserved6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved6::R`](R) reader structure"]
impl crate :: Readable for Reserved6Spec { } # [doc = "`write(|w| ..)` method takes [`reserved6::W`](W) writer structure"]
impl crate :: Writable for Reserved6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED6 to value 0"]
impl crate :: Resettable for Reserved6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED7 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved7`]
module"]
# [doc (alias = "RESERVED7")]
pub type Reserved7 = crate :: Reg < reserved7 :: Reserved7Spec > ; # [doc = "Reserved"]
pub mod reserved7 { # [doc = "Register `RESERVED7` reader"]
pub type R = crate :: R < Reserved7Spec > ; # [doc = "Register `RESERVED7` writer"]
pub type W = crate :: W < Reserved7Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved7Spec ; impl crate :: RegisterSpec for Reserved7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved7::R`](R) reader structure"]
impl crate :: Readable for Reserved7Spec { } # [doc = "`write(|w| ..)` method takes [`reserved7::W`](W) writer structure"]
impl crate :: Writable for Reserved7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED7 to value 0"]
impl crate :: Resettable for Reserved7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED8 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved8`]
module"]
# [doc (alias = "RESERVED8")]
pub type Reserved8 = crate :: Reg < reserved8 :: Reserved8Spec > ; # [doc = "Reserved"]
pub mod reserved8 { # [doc = "Register `RESERVED8` reader"]
pub type R = crate :: R < Reserved8Spec > ; # [doc = "Register `RESERVED8` writer"]
pub type W = crate :: W < Reserved8Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved8Spec ; impl crate :: RegisterSpec for Reserved8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved8::R`](R) reader structure"]
impl crate :: Readable for Reserved8Spec { } # [doc = "`write(|w| ..)` method takes [`reserved8::W`](W) writer structure"]
impl crate :: Writable for Reserved8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED8 to value 0"]
impl crate :: Resettable for Reserved8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED9 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved9`]
module"]
# [doc (alias = "RESERVED9")]
pub type Reserved9 = crate :: Reg < reserved9 :: Reserved9Spec > ; # [doc = "Reserved"]
pub mod reserved9 { # [doc = "Register `RESERVED9` reader"]
pub type R = crate :: R < Reserved9Spec > ; # [doc = "Register `RESERVED9` writer"]
pub type W = crate :: W < Reserved9Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved9Spec ; impl crate :: RegisterSpec for Reserved9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved9::R`](R) reader structure"]
impl crate :: Readable for Reserved9Spec { } # [doc = "`write(|w| ..)` method takes [`reserved9::W`](W) writer structure"]
impl crate :: Writable for Reserved9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED9 to value 0"]
impl crate :: Resettable for Reserved9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIPIO9 (rw) register accessor: SCI Pin I/O Control Register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scipio9`]
module"]
# [doc (alias = "SCIPIO9")]
pub type Scipio9 = crate :: Reg < scipio9 :: Scipio9Spec > ; # [doc = "SCI Pin I/O Control Register 9"]
pub mod scipio9 { # [doc = "Register `SCIPIO9` reader"]
pub type R = crate :: R < Scipio9Spec > ; # [doc = "Register `SCIPIO9` writer"]
pub type W = crate :: W < Scipio9Spec > ; # [doc = "Field `CLK_SL` reader - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
pub type ClkSlR = crate :: BitReader ; # [doc = "Field `CLK_SL` writer - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
pub type ClkSlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX_SL` reader - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
pub type RxSlR = crate :: BitReader ; # [doc = "Field `RX_SL` writer - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
pub type RxSlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX_SL` reader - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
pub type TxSlR = crate :: BitReader ; # [doc = "Field `TX_SL` writer - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
pub type TxSlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
# [inline (always)]
pub fn clk_sl (& self) -> ClkSlR { ClkSlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
# [inline (always)]
pub fn rx_sl (& self) -> RxSlR { RxSlR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
# [inline (always)]
pub fn tx_sl (& self) -> TxSlR { TxSlR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin"]
# [inline (always)]
# [must_use]
pub fn clk_sl (& mut self) -> ClkSlW < Scipio9Spec > { ClkSlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin"]
# [inline (always)]
# [must_use]
pub fn rx_sl (& mut self) -> RxSlW < Scipio9Spec > { RxSlW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin."]
# [inline (always)]
# [must_use]
pub fn tx_sl (& mut self) -> TxSlW < Scipio9Spec > { TxSlW :: new (self , 2) } } # [doc = "SCI Pin I/O Control Register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`scipio9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scipio9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Scipio9Spec ; impl crate :: RegisterSpec for Scipio9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`scipio9::R`](R) reader structure"]
impl crate :: Readable for Scipio9Spec { } # [doc = "`write(|w| ..)` method takes [`scipio9::W`](W) writer structure"]
impl crate :: Writable for Scipio9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIPIO9 to value 0"]
impl crate :: Resettable for Scipio9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCIIODCTRL (rw) register accessor: SCI IO DFT Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sciiodctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciiodctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sciiodctrl`]
module"]
# [doc (alias = "SCIIODCTRL")]
pub type Sciiodctrl = crate :: Reg < sciiodctrl :: SciiodctrlSpec > ; # [doc = "SCI IO DFT Control"]
pub mod sciiodctrl { # [doc = "Register `SCIIODCTRL` reader"]
pub type R = crate :: R < SciiodctrlSpec > ; # [doc = "Register `SCIIODCTRL` writer"]
pub type W = crate :: W < SciiodctrlSpec > ; # [doc = "Field `RXP_ENA` reader - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
pub type RxpEnaR = crate :: BitReader ; # [doc = "Field `RXP_ENA` writer - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
pub type RxpEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LBP_ENA` reader - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
pub type LbpEnaR = crate :: BitReader ; # [doc = "Field `LBP_ENA` writer - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
pub type LbpEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED1` reader - 7:2\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED1` writer - 7:2\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `IODFTENA` reader - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type IodftenaR = crate :: FieldReader ; # [doc = "Field `IODFTENA` writer - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type IodftenaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `RESERVED2` reader - 15:12\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `RESERVED2` writer - 15:12\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `TX_SHIFT` reader - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type TxShiftR = crate :: FieldReader ; # [doc = "Field `TX_SHIFT` writer - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
pub type TxShiftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PIN_SAMPLE_MASK` reader - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
pub type PinSampleMaskR = crate :: FieldReader ; # [doc = "Field `PIN_SAMPLE_MASK` writer - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
pub type PinSampleMaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RESERVED3` reader - 23:21\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `RESERVED3` writer - 23:21\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `BRKDT_ENA` reader - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
pub type BrkdtEnaR = crate :: BitReader ; # [doc = "Field `BRKDT_ENA` writer - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
pub type BrkdtEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEN` reader - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
pub type PenR = crate :: BitReader ; # [doc = "Field `PEN` writer - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
pub type PenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FEN` reader - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
pub type FenR = crate :: BitReader ; # [doc = "Field `FEN` writer - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
pub type FenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED4` reader - 31:27\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `RESERVED4` writer - 31:27\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
# [inline (always)]
pub fn rxp_ena (& self) -> RxpEnaR { RxpEnaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
# [inline (always)]
pub fn lbp_ena (& self) -> LbpEnaR { LbpEnaR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
pub fn iodftena (& self) -> IodftenaR { IodftenaR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:18 - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
pub fn tx_shift (& self) -> TxShiftR { TxShiftR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bits 19:20 - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
# [inline (always)]
pub fn pin_sample_mask (& self) -> PinSampleMaskR { PinSampleMaskR :: new (((self . bits >> 19) & 3) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
# [inline (always)]
pub fn brkdt_ena (& self) -> BrkdtEnaR { BrkdtEnaR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
# [inline (always)]
pub fn pen (& self) -> PenR { PenR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
# [inline (always)]
pub fn fen (& self) -> FenR { FenR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 27) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
# [inline (always)]
# [must_use]
pub fn rxp_ena (& mut self) -> RxpEnaW < SciiodctrlSpec > { RxpEnaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
# [inline (always)]
# [must_use]
pub fn lbp_ena (& mut self) -> LbpEnaW < SciiodctrlSpec > { LbpEnaW :: new (self , 1) } # [doc = "Bits 2:7 - 7:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SciiodctrlSpec > { Reserved1W :: new (self , 2) } # [doc = "Bits 8:11 - 11:8\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
# [must_use]
pub fn iodftena (& mut self) -> IodftenaW < SciiodctrlSpec > { IodftenaW :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SciiodctrlSpec > { Reserved2W :: new (self , 12) } # [doc = "Bits 16:18 - 18:16\\]
These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
# [inline (always)]
# [must_use]
pub fn tx_shift (& mut self) -> TxShiftW < SciiodctrlSpec > { TxShiftW :: new (self , 16) } # [doc = "Bits 19:20 - 20:19\\]
PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
# [inline (always)]
# [must_use]
pub fn pin_sample_mask (& mut self) -> PinSampleMaskW < SciiodctrlSpec > { PinSampleMaskW :: new (self , 19) } # [doc = "Bits 21:23 - 23:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SciiodctrlSpec > { Reserved3W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
# [inline (always)]
# [must_use]
pub fn brkdt_ena (& mut self) -> BrkdtEnaW < SciiodctrlSpec > { BrkdtEnaW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
# [inline (always)]
# [must_use]
pub fn pen (& mut self) -> PenW < SciiodctrlSpec > { PenW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
# [inline (always)]
# [must_use]
pub fn fen (& mut self) -> FenW < SciiodctrlSpec > { FenW :: new (self , 26) } # [doc = "Bits 27:31 - 31:27\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SciiodctrlSpec > { Reserved4W :: new (self , 27) } } # [doc = "SCI IO DFT Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sciiodctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciiodctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SciiodctrlSpec ; impl crate :: RegisterSpec for SciiodctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sciiodctrl::R`](R) reader structure"]
impl crate :: Readable for SciiodctrlSpec { } # [doc = "`write(|w| ..)` method takes [`sciiodctrl::W`](W) writer structure"]
impl crate :: Writable for SciiodctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCIIODCTRL to value 0"]
impl crate :: Resettable for SciiodctrlSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_SPI"]
pub struct AppSpi1 { _marker : PhantomData < * const () > } unsafe impl Send for AppSpi1 { } impl AppSpi1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_spi_1 :: RegisterBlock = 0x57f7_f400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_spi_1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppSpi1 { type Target = app_spi_1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppSpi1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppSpi1") . finish () } } # [doc = "APP_SPI"]
pub mod app_spi_1 { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { hl_rev : HlRev , hl_hwinfo : HlHwinfo , _reserved2 : [u8 ; 0x08]
, hl_sysconfig : HlSysconfig , _reserved3 : [u8 ; 0xec]
, revision : Revision , _reserved4 : [u8 ; 0x0c]
, sysconfig : Sysconfig , sysstatus : Sysstatus , irqstatus : Irqstatus , irqenable : Irqenable , wakeupenable : Wakeupenable , syst : Syst , modulctrl : Modulctrl , ch0conf : Ch0conf , ch0stat : Ch0stat , ch0ctrl : Ch0ctrl , tx0 : Tx0 , rx0 : Rx0 , ch1conf : Ch1conf , ch1stat : Ch1stat , ch1ctrl : Ch1ctrl , tx1 : Tx1 , rx1 : Rx1 , ch2conf : Ch2conf , ch2stat : Ch2stat , ch2ctrl : Ch2ctrl , tx2 : Tx2 , rx2 : Rx2 , ch3conf : Ch3conf , ch3stat : Ch3stat , ch3ctrl : Ch3ctrl , tx3 : Tx3 , rx3 : Rx3 , xferlevel : Xferlevel , daftx : Daftx , _reserved33 : [u8 ; 0x1c]
, dafrx : Dafrx , } impl RegisterBlock { # [doc = "0x00 - IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility"]
# [inline (always)]
pub const fn hl_rev (& self) -> & HlRev { & self . hl_rev } # [doc = "0x04 - Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide."]
# [inline (always)]
pub const fn hl_hwinfo (& self) -> & HlHwinfo { & self . hl_hwinfo } # [doc = "0x10 - Clock management configuration"]
# [inline (always)]
pub const fn hl_sysconfig (& self) -> & HlSysconfig { & self . hl_sysconfig } # [doc = "0x100 - This register contains the hard coded RTL revision number."]
# [inline (always)]
pub const fn revision (& self) -> & Revision { & self . revision } # [doc = "0x110 - This register allows controlling various parameters of the OCP interface."]
# [inline (always)]
pub const fn sysconfig (& self) -> & Sysconfig { & self . sysconfig } # [doc = "0x114 - This register provides status information about the module excluding the interrupt status information"]
# [inline (always)]
pub const fn sysstatus (& self) -> & Sysstatus { & self . sysstatus } # [doc = "0x118 - The interrupt status regroups all the status of the module internal events that can generate an interrupt"]
# [inline (always)]
pub const fn irqstatus (& self) -> & Irqstatus { & self . irqstatus } # [doc = "0x11c - This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis."]
# [inline (always)]
pub const fn irqenable (& self) -> & Irqenable { & self . irqenable } # [doc = "0x120 - The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."]
# [inline (always)]
pub const fn wakeupenable (& self) -> & Wakeupenable { & self . wakeupenable } # [doc = "0x124 - This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode."]
# [inline (always)]
pub const fn syst (& self) -> & Syst { & self . syst } # [doc = "0x128 - This register is dedicated to the configuration of the serial port interface."]
# [inline (always)]
pub const fn modulctrl (& self) -> & Modulctrl { & self . modulctrl } # [doc = "0x12c - This register is dedicated to the configuration of the channel 0"]
# [inline (always)]
pub const fn ch0conf (& self) -> & Ch0conf { & self . ch0conf } # [doc = "0x130 - This register provides status information about transmitter and receiver registers of channel 0"]
# [inline (always)]
pub const fn ch0stat (& self) -> & Ch0stat { & self . ch0stat } # [doc = "0x134 - This register is dedicated to enable the channel 0"]
# [inline (always)]
pub const fn ch0ctrl (& self) -> & Ch0ctrl { & self . ch0ctrl } # [doc = "0x138 - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx0 (& self) -> & Tx0 { & self . tx0 } # [doc = "0x13c - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx0 (& self) -> & Rx0 { & self . rx0 } # [doc = "0x140 - This register is dedicated to the configuration of the channel."]
# [inline (always)]
pub const fn ch1conf (& self) -> & Ch1conf { & self . ch1conf } # [doc = "0x144 - This register provides status information about transmitter and receiver registers of channel 1"]
# [inline (always)]
pub const fn ch1stat (& self) -> & Ch1stat { & self . ch1stat } # [doc = "0x148 - This register is dedicated to enable the channel 1"]
# [inline (always)]
pub const fn ch1ctrl (& self) -> & Ch1ctrl { & self . ch1ctrl } # [doc = "0x14c - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx1 (& self) -> & Tx1 { & self . tx1 } # [doc = "0x150 - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx1 (& self) -> & Rx1 { & self . rx1 } # [doc = "0x154 - This register is dedicated to the configuration of the channel 2"]
# [inline (always)]
pub const fn ch2conf (& self) -> & Ch2conf { & self . ch2conf } # [doc = "0x158 - This register provides status information about transmitter and receiver registers of channel 2"]
# [inline (always)]
pub const fn ch2stat (& self) -> & Ch2stat { & self . ch2stat } # [doc = "0x15c - This register is dedicated to enable the channel 2"]
# [inline (always)]
pub const fn ch2ctrl (& self) -> & Ch2ctrl { & self . ch2ctrl } # [doc = "0x160 - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx2 (& self) -> & Tx2 { & self . tx2 } # [doc = "0x164 - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx2 (& self) -> & Rx2 { & self . rx2 } # [doc = "0x168 - This register is dedicated to the configuration of the channel 3"]
# [inline (always)]
pub const fn ch3conf (& self) -> & Ch3conf { & self . ch3conf } # [doc = "0x16c - This register provides status information about transmitter and receiver registers of channel 3"]
# [inline (always)]
pub const fn ch3stat (& self) -> & Ch3stat { & self . ch3stat } # [doc = "0x170 - This register is dedicated to enable the channel 3"]
# [inline (always)]
pub const fn ch3ctrl (& self) -> & Ch3ctrl { & self . ch3ctrl } # [doc = "0x174 - This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn tx3 (& self) -> & Tx3 { & self . tx3 } # [doc = "0x178 - This register contains a single SPI word received through the serial link what ever SPI word length is."]
# [inline (always)]
pub const fn rx3 (& self) -> & Rx3 { & self . rx3 } # [doc = "0x17c - This register provides transfer levels needed while using FIFO buffer during transfer."]
# [inline (always)]
pub const fn xferlevel (& self) -> & Xferlevel { & self . xferlevel } # [doc = "0x180 - This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."]
# [inline (always)]
pub const fn daftx (& self) -> & Daftx { & self . daftx } # [doc = "0x1a0 - This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."]
# [inline (always)]
pub const fn dafrx (& self) -> & Dafrx { & self . dafrx } } # [doc = "HL_REV (rw) register accessor: IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_rev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_rev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hl_rev`]
module"]
# [doc (alias = "HL_REV")]
pub type HlRev = crate :: Reg < hl_rev :: HlRevSpec > ; # [doc = "IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility"]
pub mod hl_rev { # [doc = "Register `HL_REV` reader"]
pub type R = crate :: R < HlRevSpec > ; # [doc = "Register `HL_REV` writer"]
pub type W = crate :: W < HlRevSpec > ; # [doc = "Field `Y_MINOR` reader - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
pub type YMinorR = crate :: FieldReader ; # [doc = "Field `Y_MINOR` writer - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
pub type YMinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `X_MAJOR` reader - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
pub type XMajorR = crate :: FieldReader ; # [doc = "Field `X_MAJOR` writer - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
pub type XMajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `R_RTL` reader - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
pub type RRtlR = crate :: FieldReader ; # [doc = "Field `R_RTL` writer - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
pub type RRtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNC` reader - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
pub type FuncR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNC` writer - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
pub type FuncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `RSVD` reader - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdR = crate :: FieldReader ; # [doc = "Field `RSVD` writer - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
# [inline (always)]
pub fn y_minor (& self) -> YMinorR { YMinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
# [inline (always)]
pub fn x_major (& self) -> XMajorR { XMajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
# [inline (always)]
pub fn r_rtl (& self) -> RRtlR { RRtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
# [inline (always)]
pub fn func (& self) -> FuncR { FuncR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:29 - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
pub fn rsvd (& self) -> RsvdR { RsvdR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Revision \\[Y\\]
maintained by IP specification owner Y changes ONLY when: \\[1\\]
Features are scaled \\[up or down\\]
Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available \\[2\\]
When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Typos or clarifications \\[3\\]
major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: \\[1\\]
Typos/clarifications \\[2\\]
Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release \\[say for silicon PG11\\]
that occurs due to bug fix should document the corresponding spec number \\[XYS\\]
in its release notes - (RO )"]
# [inline (always)]
# [must_use]
pub fn y_minor (& mut self) -> YMinorW < HlRevSpec > { YMinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library \\[CSL\\]
/ Drivers - (RO )"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < HlRevSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Revision \\[X\\]
maintained by IP specification owner X changes ONLY when: \\[1\\]
There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field \\[or Class/Type in old PID format\\]
will remain the same X does NOT change due to: \\[1\\]
Bug fixes \\[2\\]
Change in feature parameters - (RO )"]
# [inline (always)]
# [must_use]
pub fn x_major (& mut self) -> XMajorW < HlRevSpec > { XMajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Version \\[R\\]
maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: \\[1\\]
PDS uploads occur which may have been due to spec changes \\[2\\]
Bug fixes occur \\[3\\]
Resets to '0' when X or Y changes Design team has an internal 'Z' \\[customer invisible\\]
number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO )"]
# [inline (always)]
# [must_use]
pub fn r_rtl (& mut self) -> RRtlW < HlRevSpec > { RRtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
Function indicates a software compatible module family If there is no level of software compatibility a new Func number \\[and hence REVISION\\]
should be assigned - (RO )"]
# [inline (always)]
# [must_use]
pub fn func (& mut self) -> FuncW < HlRevSpec > { FuncW :: new (self , 16) } # [doc = "Bits 28:29 - 29:28\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
# [must_use]
pub fn rsvd (& mut self) -> RsvdW < HlRevSpec > { RsvdW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
Used to distinguish between old scheme and current - (RO )"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < HlRevSpec > { SchemeW :: new (self , 30) } } # [doc = "IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_rev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_rev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HlRevSpec ; impl crate :: RegisterSpec for HlRevSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hl_rev::R`](R) reader structure"]
impl crate :: Readable for HlRevSpec { } # [doc = "`write(|w| ..)` method takes [`hl_rev::W`](W) writer structure"]
impl crate :: Writable for HlRevSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HL_REV to value 0"]
impl crate :: Resettable for HlRevSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HL_HWINFO (rw) register accessor: Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide.\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_hwinfo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_hwinfo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hl_hwinfo`]
module"]
# [doc (alias = "HL_HWINFO")]
pub type HlHwinfo = crate :: Reg < hl_hwinfo :: HlHwinfoSpec > ; # [doc = "Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide."]
pub mod hl_hwinfo { # [doc = "Register `HL_HWINFO` reader"]
pub type R = crate :: R < HlHwinfoSpec > ; # [doc = "Register `HL_HWINFO` writer"]
pub type W = crate :: W < HlHwinfoSpec > ; # [doc = "Field `USEFIFO` reader - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
pub type UsefifoR = crate :: BitReader ; # [doc = "Field `USEFIFO` writer - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
pub type UsefifoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFNBYTE` reader - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
pub type FfnbyteR = crate :: FieldReader ; # [doc = "Field `FFNBYTE` writer - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
pub type FfnbyteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `RETMODE` reader - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
pub type RetmodeR = crate :: BitReader ; # [doc = "Field `RETMODE` writer - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
pub type RetmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RSVD` reader - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdR = crate :: FieldReader < u32 > ; # [doc = "Field `RSVD` writer - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
pub type RsvdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
# [inline (always)]
pub fn usefifo (& self) -> UsefifoR { UsefifoR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:5 - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
# [inline (always)]
pub fn ffnbyte (& self) -> FfnbyteR { FfnbyteR :: new (((self . bits >> 1) & 0x1f) as u8) } # [doc = "Bit 6 - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
# [inline (always)]
pub fn retmode (& self) -> RetmodeR { RetmodeR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
pub fn rsvd (& self) -> RsvdR { RsvdR :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO )"]
# [inline (always)]
# [must_use]
pub fn usefifo (& mut self) -> UsefifoW < HlHwinfoSpec > { UsefifoW :: new (self , 0) } # [doc = "Bits 1:5 - 5:1\\]
FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO )"]
# [inline (always)]
# [must_use]
pub fn ffnbyte (& mut self) -> FfnbyteW < HlHwinfoSpec > { FfnbyteW :: new (self , 1) } # [doc = "Bit 6 - 6:6\\]
This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO )"]
# [inline (always)]
# [must_use]
pub fn retmode (& mut self) -> RetmodeW < HlHwinfoSpec > { RetmodeW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Reserved These bits are initialized to zero and writes to them are ignored - (RO )"]
# [inline (always)]
# [must_use]
pub fn rsvd (& mut self) -> RsvdW < HlHwinfoSpec > { RsvdW :: new (self , 7) } } # [doc = "Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide.\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_hwinfo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_hwinfo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HlHwinfoSpec ; impl crate :: RegisterSpec for HlHwinfoSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hl_hwinfo::R`](R) reader structure"]
impl crate :: Readable for HlHwinfoSpec { } # [doc = "`write(|w| ..)` method takes [`hl_hwinfo::W`](W) writer structure"]
impl crate :: Writable for HlHwinfoSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HL_HWINFO to value 0"]
impl crate :: Resettable for HlHwinfoSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "HL_SYSCONFIG (rw) register accessor: Clock management configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_sysconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_sysconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hl_sysconfig`]
module"]
# [doc (alias = "HL_SYSCONFIG")]
pub type HlSysconfig = crate :: Reg < hl_sysconfig :: HlSysconfigSpec > ; # [doc = "Clock management configuration"]
pub mod hl_sysconfig { # [doc = "Register `HL_SYSCONFIG` reader"]
pub type R = crate :: R < HlSysconfigSpec > ; # [doc = "Register `HL_SYSCONFIG` writer"]
pub type W = crate :: W < HlSysconfigSpec > ; # [doc = "Field `SOFTRESET` reader - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
pub type SoftresetR = crate :: BitReader ; # [doc = "Field `SOFTRESET` writer - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
pub type SoftresetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FREEEMU` reader - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
pub type FreeemuR = crate :: BitReader ; # [doc = "Field `FREEEMU` writer - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
pub type FreeemuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDLEMODE` reader - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
pub type IdlemodeR = crate :: FieldReader ; # [doc = "Field `IDLEMODE` writer - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
pub type IdlemodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RSVD` reader - 31:4\\]
Reserved - (RO )"]
pub type RsvdR = crate :: FieldReader < u32 > ; # [doc = "Field `RSVD` writer - 31:4\\]
Reserved - (RO )"]
pub type RsvdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
# [inline (always)]
pub fn softreset (& self) -> SoftresetR { SoftresetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
# [inline (always)]
pub fn freeemu (& self) -> FreeemuR { FreeemuR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
# [inline (always)]
pub fn idlemode (& self) -> IdlemodeR { IdlemodeR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:31 - 31:4\\]
Reserved - (RO )"]
# [inline (always)]
pub fn rsvd (& self) -> RsvdR { RsvdR :: new ((self . bits >> 4) & 0x0fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Software reset \\[Optional\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn softreset (& mut self) -> SoftresetW < HlSysconfigSpec > { SoftresetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Sensitivity to emulation \\[debug\\]
suspend input signal - (RW )"]
# [inline (always)]
# [must_use]
pub fn freeemu (& mut self) -> FreeemuW < HlSysconfigSpec > { FreeemuW :: new (self , 1) } # [doc = "Bits 2:3 - 3:2\\]
Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW )"]
# [inline (always)]
# [must_use]
pub fn idlemode (& mut self) -> IdlemodeW < HlSysconfigSpec > { IdlemodeW :: new (self , 2) } # [doc = "Bits 4:31 - 31:4\\]
Reserved - (RO )"]
# [inline (always)]
# [must_use]
pub fn rsvd (& mut self) -> RsvdW < HlSysconfigSpec > { RsvdW :: new (self , 4) } } # [doc = "Clock management configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hl_sysconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hl_sysconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HlSysconfigSpec ; impl crate :: RegisterSpec for HlSysconfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`hl_sysconfig::R`](R) reader structure"]
impl crate :: Readable for HlSysconfigSpec { } # [doc = "`write(|w| ..)` method takes [`hl_sysconfig::W`](W) writer structure"]
impl crate :: Writable for HlSysconfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets HL_SYSCONFIG to value 0"]
impl crate :: Resettable for HlSysconfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "REVISION (rw) register accessor: This register contains the hard coded RTL revision number.\n\nYou can [`read`](crate::Reg::read) this register and get [`revision::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`revision::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@revision`]
module"]
# [doc (alias = "REVISION")]
pub type Revision = crate :: Reg < revision :: RevisionSpec > ; # [doc = "This register contains the hard coded RTL revision number."]
pub mod revision { # [doc = "Register `REVISION` reader"]
pub type R = crate :: R < RevisionSpec > ; # [doc = "Register `REVISION` writer"]
pub type W = crate :: W < RevisionSpec > ; # [doc = "Field `REV` reader - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
pub type RevR = crate :: FieldReader ; # [doc = "Field `REV` writer - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
pub type RevW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_13` reader - 31:8\\]
Reads returns 0 - (RO )"]
pub type Reserved13R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_13` writer - 31:8\\]
Reads returns 0 - (RO )"]
pub type Reserved13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
# [inline (always)]
pub fn rev (& self) -> RevR { RevR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_13 (& self) -> Reserved13R { Reserved13R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
IP revision \\[7:4\\]
Major revision \\[3:0\\]
Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO"]
# [inline (always)]
# [must_use]
pub fn rev (& mut self) -> RevW < RevisionSpec > { RevW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_13 (& mut self) -> Reserved13W < RevisionSpec > { Reserved13W :: new (self , 8) } } # [doc = "This register contains the hard coded RTL revision number.\n\nYou can [`read`](crate::Reg::read) this register and get [`revision::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`revision::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RevisionSpec ; impl crate :: RegisterSpec for RevisionSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`revision::R`](R) reader structure"]
impl crate :: Readable for RevisionSpec { } # [doc = "`write(|w| ..)` method takes [`revision::W`](W) writer structure"]
impl crate :: Writable for RevisionSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets REVISION to value 0"]
impl crate :: Resettable for RevisionSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYSCONFIG (rw) register accessor: This register allows controlling various parameters of the OCP interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysconfig`]
module"]
# [doc (alias = "SYSCONFIG")]
pub type Sysconfig = crate :: Reg < sysconfig :: SysconfigSpec > ; # [doc = "This register allows controlling various parameters of the OCP interface."]
pub mod sysconfig { # [doc = "Register `SYSCONFIG` reader"]
pub type R = crate :: R < SysconfigSpec > ; # [doc = "Register `SYSCONFIG` writer"]
pub type W = crate :: W < SysconfigSpec > ; # [doc = "Field `AUTOIDLE` reader - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
pub type AutoidleR = crate :: BitReader ; # [doc = "Field `AUTOIDLE` writer - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
pub type AutoidleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOFTRESET` reader - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
pub type SoftresetR = crate :: BitReader ; # [doc = "Field `SOFTRESET` writer - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
pub type SoftresetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENAWAKEUP` reader - 2:2\\]
WakeUp feature control - (RW )"]
pub type EnawakeupR = crate :: BitReader ; # [doc = "Field `ENAWAKEUP` writer - 2:2\\]
WakeUp feature control - (RW )"]
pub type EnawakeupW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SIDLEMODE` reader - 4:3\\]
Power management - (RW )"]
pub type SidlemodeR = crate :: FieldReader ; # [doc = "Field `SIDLEMODE` writer - 4:3\\]
Power management - (RW )"]
pub type SidlemodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RESERVED_15` reader - 7:5\\]
Reads returns 0 - (RO )"]
pub type Reserved15R = crate :: FieldReader ; # [doc = "Field `RESERVED_15` writer - 7:5\\]
Reads returns 0 - (RO )"]
pub type Reserved15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CLOCKACTIVITY` reader - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
pub type ClockactivityR = crate :: FieldReader ; # [doc = "Field `CLOCKACTIVITY` writer - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
pub type ClockactivityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RESERVED_14` reader - 31:10\\]
Reads returns 0 - (RO )"]
pub type Reserved14R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_14` writer - 31:10\\]
Reads returns 0 - (RO )"]
pub type Reserved14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
# [inline (always)]
pub fn autoidle (& self) -> AutoidleR { AutoidleR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
# [inline (always)]
pub fn softreset (& self) -> SoftresetR { SoftresetR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
WakeUp feature control - (RW )"]
# [inline (always)]
pub fn enawakeup (& self) -> EnawakeupR { EnawakeupR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:4 - 4:3\\]
Power management - (RW )"]
# [inline (always)]
pub fn sidlemode (& self) -> SidlemodeR { SidlemodeR :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 5:7 - 7:5\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_15 (& self) -> Reserved15R { Reserved15R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
# [inline (always)]
pub fn clockactivity (& self) -> ClockactivityR { ClockactivityR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:31 - 31:10\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_14 (& self) -> Reserved14R { Reserved14R :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Internal OCP Clock gating strategy - (RW )"]
# [inline (always)]
# [must_use]
pub fn autoidle (& mut self) -> AutoidleW < SysconfigSpec > { AutoidleW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Software reset During reads it always returns 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn softreset (& mut self) -> SoftresetW < SysconfigSpec > { SoftresetW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
WakeUp feature control - (RW )"]
# [inline (always)]
# [must_use]
pub fn enawakeup (& mut self) -> EnawakeupW < SysconfigSpec > { EnawakeupW :: new (self , 2) } # [doc = "Bits 3:4 - 4:3\\]
Power management - (RW )"]
# [inline (always)]
# [must_use]
pub fn sidlemode (& mut self) -> SidlemodeW < SysconfigSpec > { SidlemodeW :: new (self , 3) } # [doc = "Bits 5:7 - 7:5\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_15 (& mut self) -> Reserved15W < SysconfigSpec > { Reserved15W :: new (self , 5) } # [doc = "Bits 8:9 - 9:8\\]
Clocks activity during wake up mode period - (RW )"]
# [inline (always)]
# [must_use]
pub fn clockactivity (& mut self) -> ClockactivityW < SysconfigSpec > { ClockactivityW :: new (self , 8) } # [doc = "Bits 10:31 - 31:10\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_14 (& mut self) -> Reserved14W < SysconfigSpec > { Reserved14W :: new (self , 10) } } # [doc = "This register allows controlling various parameters of the OCP interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysconfigSpec ; impl crate :: RegisterSpec for SysconfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sysconfig::R`](R) reader structure"]
impl crate :: Readable for SysconfigSpec { } # [doc = "`write(|w| ..)` method takes [`sysconfig::W`](W) writer structure"]
impl crate :: Writable for SysconfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYSCONFIG to value 0"]
impl crate :: Resettable for SysconfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYSSTATUS (rw) register accessor: This register provides status information about the module excluding the interrupt status information\n\nYou can [`read`](crate::Reg::read) this register and get [`sysstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysstatus`]
module"]
# [doc (alias = "SYSSTATUS")]
pub type Sysstatus = crate :: Reg < sysstatus :: SysstatusSpec > ; # [doc = "This register provides status information about the module excluding the interrupt status information"]
pub mod sysstatus { # [doc = "Register `SYSSTATUS` reader"]
pub type R = crate :: R < SysstatusSpec > ; # [doc = "Register `SYSSTATUS` writer"]
pub type W = crate :: W < SysstatusSpec > ; # [doc = "Field `RESETDONE` reader - 0:0\\]
Internal Reset Monitoring - (RO )"]
pub type ResetdoneR = crate :: BitReader ; # [doc = "Field `RESETDONE` writer - 0:0\\]
Internal Reset Monitoring - (RO )"]
pub type ResetdoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_16` reader - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
pub type Reserved16R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_16` writer - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
pub type Reserved16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Internal Reset Monitoring - (RO )"]
# [inline (always)]
pub fn resetdone (& self) -> ResetdoneR { ResetdoneR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_16 (& self) -> Reserved16R { Reserved16R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Internal Reset Monitoring - (RO )"]
# [inline (always)]
# [must_use]
pub fn resetdone (& mut self) -> ResetdoneW < SysstatusSpec > { ResetdoneW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved for module specific status information Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_16 (& mut self) -> Reserved16W < SysstatusSpec > { Reserved16W :: new (self , 1) } } # [doc = "This register provides status information about the module excluding the interrupt status information\n\nYou can [`read`](crate::Reg::read) this register and get [`sysstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysstatusSpec ; impl crate :: RegisterSpec for SysstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sysstatus::R`](R) reader structure"]
impl crate :: Readable for SysstatusSpec { } # [doc = "`write(|w| ..)` method takes [`sysstatus::W`](W) writer structure"]
impl crate :: Writable for SysstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYSSTATUS to value 0"]
impl crate :: Resettable for SysstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IRQSTATUS (rw) register accessor: The interrupt status regroups all the status of the module internal events that can generate an interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`irqstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqstatus`]
module"]
# [doc (alias = "IRQSTATUS")]
pub type Irqstatus = crate :: Reg < irqstatus :: IrqstatusSpec > ; # [doc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt"]
pub mod irqstatus { # [doc = "Register `IRQSTATUS` reader"]
pub type R = crate :: R < IrqstatusSpec > ; # [doc = "Register `IRQSTATUS` writer"]
pub type W = crate :: W < IrqstatusSpec > ; # [doc = "Field `TX0_EMPTY` reader - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
pub type Tx0EmptyR = crate :: BitReader ; # [doc = "Field `TX0_EMPTY` writer - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
pub type Tx0EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX0_UNDERFLOW` reader - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
pub type Tx0UnderflowR = crate :: BitReader ; # [doc = "Field `TX0_UNDERFLOW` writer - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
pub type Tx0UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_FULL` reader - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
pub type Rx0FullR = crate :: BitReader ; # [doc = "Field `RX0_FULL` writer - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
pub type Rx0FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_OVERFLOW` reader - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
pub type Rx0OverflowR = crate :: BitReader ; # [doc = "Field `RX0_OVERFLOW` writer - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
pub type Rx0OverflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_EMPTY` reader - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
pub type Tx1EmptyR = crate :: BitReader ; # [doc = "Field `TX1_EMPTY` writer - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
pub type Tx1EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_UNDERFLOW` reader - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
pub type Tx1UnderflowR = crate :: BitReader ; # [doc = "Field `TX1_UNDERFLOW` writer - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
pub type Tx1UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX1_FULL` reader - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
pub type Rx1FullR = crate :: BitReader ; # [doc = "Field `RX1_FULL` writer - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
pub type Rx1FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_10` reader - 7:7\\]
Reads returns 0 - (RO )"]
pub type Reserved10R = crate :: BitReader ; # [doc = "Field `RESERVED_10` writer - 7:7\\]
Reads returns 0 - (RO )"]
pub type Reserved10W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_EMPTY` reader - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
pub type Tx2EmptyR = crate :: BitReader ; # [doc = "Field `TX2_EMPTY` writer - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
pub type Tx2EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_UNDERFLOW` reader - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
pub type Tx2UnderflowR = crate :: BitReader ; # [doc = "Field `TX2_UNDERFLOW` writer - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
pub type Tx2UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX2_FULL` reader - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
pub type Rx2FullR = crate :: BitReader ; # [doc = "Field `RX2_FULL` writer - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
pub type Rx2FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_9` reader - 11:11\\]
Reads returns 0 - (RO )"]
pub type Reserved9R = crate :: BitReader ; # [doc = "Field `RESERVED_9` writer - 11:11\\]
Reads returns 0 - (RO )"]
pub type Reserved9W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_EMPTY` reader - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
pub type Tx3EmptyR = crate :: BitReader ; # [doc = "Field `TX3_EMPTY` writer - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
pub type Tx3EmptyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_UNDERFLOW` reader - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
pub type Tx3UnderflowR = crate :: BitReader ; # [doc = "Field `TX3_UNDERFLOW` writer - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
pub type Tx3UnderflowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX3_FULL` reader - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
pub type Rx3FullR = crate :: BitReader ; # [doc = "Field `RX3_FULL` writer - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
pub type Rx3FullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_7` reader - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved7R = crate :: BitReader ; # [doc = "Field `RESERVED_7` writer - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WKS` reader - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WksR = crate :: BitReader ; # [doc = "Field `WKS` writer - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WksW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOW` reader - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
pub type EowR = crate :: BitReader ; # [doc = "Field `EOW` writer - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
pub type EowW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_8` reader - 31:18\\]
Reads returns 0 - (RO )"]
pub type Reserved8R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_8` writer - 31:18\\]
Reads returns 0 - (RO )"]
pub type Reserved8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
# [inline (always)]
pub fn tx0_empty (& self) -> Tx0EmptyR { Tx0EmptyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
# [inline (always)]
pub fn tx0_underflow (& self) -> Tx0UnderflowR { Tx0UnderflowR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
# [inline (always)]
pub fn rx0_full (& self) -> Rx0FullR { Rx0FullR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
# [inline (always)]
pub fn rx0_overflow (& self) -> Rx0OverflowR { Rx0OverflowR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
# [inline (always)]
pub fn tx1_empty (& self) -> Tx1EmptyR { Tx1EmptyR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
# [inline (always)]
pub fn tx1_underflow (& self) -> Tx1UnderflowR { Tx1UnderflowR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
# [inline (always)]
pub fn rx1_full (& self) -> Rx1FullR { Rx1FullR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_10 (& self) -> Reserved10R { Reserved10R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
# [inline (always)]
pub fn tx2_empty (& self) -> Tx2EmptyR { Tx2EmptyR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
# [inline (always)]
pub fn tx2_underflow (& self) -> Tx2UnderflowR { Tx2UnderflowR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
# [inline (always)]
pub fn rx2_full (& self) -> Rx2FullR { Rx2FullR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_9 (& self) -> Reserved9R { Reserved9R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
# [inline (always)]
pub fn tx3_empty (& self) -> Tx3EmptyR { Tx3EmptyR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
# [inline (always)]
pub fn tx3_underflow (& self) -> Tx3UnderflowR { Tx3UnderflowR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
# [inline (always)]
pub fn rx3_full (& self) -> Rx3FullR { Rx3FullR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_7 (& self) -> Reserved7R { Reserved7R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
pub fn wks (& self) -> WksR { WksR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
# [inline (always)]
pub fn eow (& self) -> EowR { EowR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:31 - 31:18\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_8 (& self) -> Reserved8R { Reserved8R :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Transmitter register empty or almost empty Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_empty (& mut self) -> Tx0EmptyW < IrqstatusSpec > { Tx0EmptyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register underflow Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_underflow (& mut self) -> Tx0UnderflowW < IrqstatusSpec > { Tx0UnderflowW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Receiver register full or almost full Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_full (& mut self) -> Rx0FullW < IrqstatusSpec > { Rx0FullW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Receiver register overflow \\[slave mode only\\]
Channel 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_overflow (& mut self) -> Rx0OverflowW < IrqstatusSpec > { Rx0OverflowW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Transmitter register empty or almost empty Channel 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_empty (& mut self) -> Tx1EmptyW < IrqstatusSpec > { Tx1EmptyW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Transmitter register underflow Channel 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_underflow (& mut self) -> Tx1UnderflowW < IrqstatusSpec > { Tx1UnderflowW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Receiver register full or almost full Channel 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx1_full (& mut self) -> Rx1FullW < IrqstatusSpec > { Rx1FullW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_10 (& mut self) -> Reserved10W < IrqstatusSpec > { Reserved10W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Transmitter register empty or almost empty Channel 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_empty (& mut self) -> Tx2EmptyW < IrqstatusSpec > { Tx2EmptyW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmitter register underflow Channel 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_underflow (& mut self) -> Tx2UnderflowW < IrqstatusSpec > { Tx2UnderflowW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Receiver register full or almost full Channel 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx2_full (& mut self) -> Rx2FullW < IrqstatusSpec > { Rx2FullW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_9 (& mut self) -> Reserved9W < IrqstatusSpec > { Reserved9W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_empty (& mut self) -> Tx3EmptyW < IrqstatusSpec > { Tx3EmptyW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty \\[not updated by Host or DMA with new data\\]
before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_underflow (& mut self) -> Tx3UnderflowW < IrqstatusSpec > { Tx3UnderflowW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Receiver register is full or almost full Only when Channel 3 is enabled - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx3_full (& mut self) -> Rx3FullW < IrqstatusSpec > { Rx3FullW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_7 (& mut self) -> Reserved7W < IrqstatusSpec > { Reserved7W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn wks (& mut self) -> WksW < IrqstatusSpec > { WksW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL\\[WCNT\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn eow (& mut self) -> EowW < IrqstatusSpec > { EowW :: new (self , 17) } # [doc = "Bits 18:31 - 31:18\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_8 (& mut self) -> Reserved8W < IrqstatusSpec > { Reserved8W :: new (self , 18) } } # [doc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`irqstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqstatusSpec ; impl crate :: RegisterSpec for IrqstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`irqstatus::R`](R) reader structure"]
impl crate :: Readable for IrqstatusSpec { } # [doc = "`write(|w| ..)` method takes [`irqstatus::W`](W) writer structure"]
impl crate :: Writable for IrqstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IRQSTATUS to value 0"]
impl crate :: Resettable for IrqstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IRQENABLE (rw) register accessor: This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`irqenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqenable`]
module"]
# [doc (alias = "IRQENABLE")]
pub type Irqenable = crate :: Reg < irqenable :: IrqenableSpec > ; # [doc = "This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis."]
pub mod irqenable { # [doc = "Register `IRQENABLE` reader"]
pub type R = crate :: R < IrqenableSpec > ; # [doc = "Register `IRQENABLE` writer"]
pub type W = crate :: W < IrqenableSpec > ; # [doc = "Field `TX0_EMPTY_ENABLE` reader - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
pub type Tx0EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX0_EMPTY_ENABLE` writer - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
pub type Tx0EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX0_UNDERFLOW_ENABLE` reader - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
pub type Tx0UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX0_UNDERFLOW_ENABLE` writer - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
pub type Tx0UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_FULL_ENABLE` reader - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
pub type Rx0FullEnableR = crate :: BitReader ; # [doc = "Field `RX0_FULL_ENABLE` writer - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
pub type Rx0FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX0_OVERFLOW_ENABLE` reader - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
pub type Rx0OverflowEnableR = crate :: BitReader ; # [doc = "Field `RX0_OVERFLOW_ENABLE` writer - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
pub type Rx0OverflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_EMPTY_ENABLE` reader - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
pub type Tx1EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX1_EMPTY_ENABLE` writer - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
pub type Tx1EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX1_UNDERFLOW_ENABLE` reader - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
pub type Tx1UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX1_UNDERFLOW_ENABLE` writer - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
pub type Tx1UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX1_FULL_ENABLE` reader - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
pub type Rx1FullEnableR = crate :: BitReader ; # [doc = "Field `RX1_FULL_ENABLE` writer - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
pub type Rx1FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_3` reader - 7:7\\]
Reads return 0 - (RO )"]
pub type Reserved3R = crate :: BitReader ; # [doc = "Field `RESERVED_3` writer - 7:7\\]
Reads return 0 - (RO )"]
pub type Reserved3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_EMPTY_ENABLE` reader - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
pub type Tx2EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX2_EMPTY_ENABLE` writer - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
pub type Tx2EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX2_UNDERFLOW_ENABLE` reader - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
pub type Tx2UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX2_UNDERFLOW_ENABLE` writer - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
pub type Tx2UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX2_FULL_ENABLE` reader - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
pub type Rx2FullEnableR = crate :: BitReader ; # [doc = "Field `RX2_FULL_ENABLE` writer - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
pub type Rx2FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_6` reader - 11:11\\]
Reads return 0 - (RO )"]
pub type Reserved6R = crate :: BitReader ; # [doc = "Field `RESERVED_6` writer - 11:11\\]
Reads return 0 - (RO )"]
pub type Reserved6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_EMPTY_ENABLE` reader - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
pub type Tx3EmptyEnableR = crate :: BitReader ; # [doc = "Field `TX3_EMPTY_ENABLE` writer - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
pub type Tx3EmptyEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TX3_UNDERFLOW_ENABLE` reader - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
pub type Tx3UnderflowEnableR = crate :: BitReader ; # [doc = "Field `TX3_UNDERFLOW_ENABLE` writer - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
pub type Tx3UnderflowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RX3_FULL_ENABLE` reader - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
pub type Rx3FullEnableR = crate :: BitReader ; # [doc = "Field `RX3_FULL_ENABLE` writer - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
pub type Rx3FullEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_4` reader - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved4R = crate :: BitReader ; # [doc = "Field `RESERVED_4` writer - 15:15\\]
Reads returns 0 - (RO )"]
pub type Reserved4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WKE` reader - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkeR = crate :: BitReader ; # [doc = "Field `WKE` writer - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOW_ENABLE` reader - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
pub type EowEnableR = crate :: BitReader ; # [doc = "Field `EOW_ENABLE` writer - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
pub type EowEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_5` reader - 31:18\\]
Reads return 0 - (RO )"]
pub type Reserved5R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_5` writer - 31:18\\]
Reads return 0 - (RO )"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 14 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn tx0_empty_enable (& self) -> Tx0EmptyEnableR { Tx0EmptyEnableR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn tx0_underflow_enable (& self) -> Tx0UnderflowEnableR { Tx0UnderflowEnableR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn rx0_full_enable (& self) -> Rx0FullEnableR { Rx0FullEnableR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
pub fn rx0_overflow_enable (& self) -> Rx0OverflowEnableR { Rx0OverflowEnableR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
pub fn tx1_empty_enable (& self) -> Tx1EmptyEnableR { Tx1EmptyEnableR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
pub fn tx1_underflow_enable (& self) -> Tx1UnderflowEnableR { Tx1UnderflowEnableR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
pub fn rx1_full_enable (& self) -> Rx1FullEnableR { Rx1FullEnableR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Reads return 0 - (RO )"]
# [inline (always)]
pub fn reserved_3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
pub fn tx2_empty_enable (& self) -> Tx2EmptyEnableR { Tx2EmptyEnableR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
pub fn tx2_underflow_enable (& self) -> Tx2UnderflowEnableR { Tx2UnderflowEnableR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
pub fn rx2_full_enable (& self) -> Rx2FullEnableR { Rx2FullEnableR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Reads return 0 - (RO )"]
# [inline (always)]
pub fn reserved_6 (& self) -> Reserved6R { Reserved6R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
# [inline (always)]
pub fn tx3_empty_enable (& self) -> Tx3EmptyEnableR { Tx3EmptyEnableR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
pub fn tx3_underflow_enable (& self) -> Tx3UnderflowEnableR { Tx3UnderflowEnableR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
pub fn rx3_full_enable (& self) -> Rx3FullEnableR { Rx3FullEnableR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
pub fn wke (& self) -> WkeR { WkeR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
# [inline (always)]
pub fn eow_enable (& self) -> EowEnableR { EowEnableR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:31 - 31:18\\]
Reads return 0 - (RO )"]
# [inline (always)]
pub fn reserved_5 (& self) -> Reserved5R { Reserved5R :: new (((self . bits >> 18) & 0x3fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Transmitter register Empty Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_empty_enable (& mut self) -> Tx0EmptyEnableW < IrqenableSpec > { Tx0EmptyEnableW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Transmitter register Underflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx0_underflow_enable (& mut self) -> Tx0UnderflowEnableW < IrqenableSpec > { Tx0UnderflowEnableW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Receiver register Full Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_full_enable (& mut self) -> Rx0FullEnableW < IrqenableSpec > { Rx0FullEnableW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Receiver register Overflow Interrupt Enable Ch 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx0_overflow_enable (& mut self) -> Rx0OverflowEnableW < IrqenableSpec > { Rx0OverflowEnableW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Transmitter register Empty Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_empty_enable (& mut self) -> Tx1EmptyEnableW < IrqenableSpec > { Tx1EmptyEnableW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Transmitter register Underflow Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx1_underflow_enable (& mut self) -> Tx1UnderflowEnableW < IrqenableSpec > { Tx1UnderflowEnableW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Receiver register Full Interrupt Enable Ch 1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx1_full_enable (& mut self) -> Rx1FullEnableW < IrqenableSpec > { Rx1FullEnableW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Reads return 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_3 (& mut self) -> Reserved3W < IrqenableSpec > { Reserved3W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Transmitter register Empty Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_empty_enable (& mut self) -> Tx2EmptyEnableW < IrqenableSpec > { Tx2EmptyEnableW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmitter register Underflow Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx2_underflow_enable (& mut self) -> Tx2UnderflowEnableW < IrqenableSpec > { Tx2UnderflowEnableW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Receiver register Full Interrupt Enable Ch 2 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx2_full_enable (& mut self) -> Rx2FullEnableW < IrqenableSpec > { Rx2FullEnableW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Reads return 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_6 (& mut self) -> Reserved6W < IrqenableSpec > { Reserved6W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Transmitter register Empty Interrupt Enable Ch3 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_empty_enable (& mut self) -> Tx3EmptyEnableW < IrqenableSpec > { Tx3EmptyEnableW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Transmitter register Underflow Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
# [must_use]
pub fn tx3_underflow_enable (& mut self) -> Tx3UnderflowEnableW < IrqenableSpec > { Tx3UnderflowEnableW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Receiver register Full Interrupt Enable Ch 3 - (RW )"]
# [inline (always)]
# [must_use]
pub fn rx3_full_enable (& mut self) -> Rx3FullEnableW < IrqenableSpec > { Rx3FullEnableW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_4 (& mut self) -> Reserved4W < IrqenableSpec > { Reserved4W :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn wke (& mut self) -> WkeW < IrqenableSpec > { WkeW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
End of Word count Interrupt Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn eow_enable (& mut self) -> EowEnableW < IrqenableSpec > { EowEnableW :: new (self , 17) } # [doc = "Bits 18:31 - 31:18\\]
Reads return 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_5 (& mut self) -> Reserved5W < IrqenableSpec > { Reserved5W :: new (self , 18) } } # [doc = "This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`irqenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqenableSpec ; impl crate :: RegisterSpec for IrqenableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`irqenable::R`](R) reader structure"]
impl crate :: Readable for IrqenableSpec { } # [doc = "`write(|w| ..)` method takes [`irqenable::W`](W) writer structure"]
impl crate :: Writable for IrqenableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IRQENABLE to value 0"]
impl crate :: Resettable for IrqenableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WAKEUPENABLE (rw) register accessor: The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeupenable`]
module"]
# [doc (alias = "WAKEUPENABLE")]
pub type Wakeupenable = crate :: Reg < wakeupenable :: WakeupenableSpec > ; # [doc = "The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."]
pub mod wakeupenable { # [doc = "Register `WAKEUPENABLE` reader"]
pub type R = crate :: R < WakeupenableSpec > ; # [doc = "Register `WAKEUPENABLE` writer"]
pub type W = crate :: W < WakeupenableSpec > ; # [doc = "Field `WKEN` reader - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkenR = crate :: BitReader ; # [doc = "Field `WKEN` writer - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
pub type WkenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_18` reader - 31:1\\]
Reads returns 0 - (RO )"]
pub type Reserved18R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_18` writer - 31:1\\]
Reads returns 0 - (RO )"]
pub type Reserved18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
pub fn wken (& self) -> WkenR { WkenR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_18 (& self) -> Reserved18R { Reserved18R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF\\[SPIENSLV\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn wken (& mut self) -> WkenW < WakeupenableSpec > { WkenW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_18 (& mut self) -> Reserved18W < WakeupenableSpec > { Reserved18W :: new (self , 1) } } # [doc = "The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis.\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WakeupenableSpec ; impl crate :: RegisterSpec for WakeupenableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wakeupenable::R`](R) reader structure"]
impl crate :: Readable for WakeupenableSpec { } # [doc = "`write(|w| ..)` method takes [`wakeupenable::W`](W) writer structure"]
impl crate :: Writable for WakeupenableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WAKEUPENABLE to value 0"]
impl crate :: Resettable for WakeupenableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYST (rw) register accessor: This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`syst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syst`]
module"]
# [doc (alias = "SYST")]
pub type Syst = crate :: Reg < syst :: SystSpec > ; # [doc = "This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode."]
pub mod syst { # [doc = "Register `SYST` reader"]
pub type R = crate :: R < SystSpec > ; # [doc = "Register `SYST` writer"]
pub type W = crate :: W < SystSpec > ; # [doc = "Field `SPIEN_0` reader - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien0R = crate :: BitReader ; # [doc = "Field `SPIEN_0` writer - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIEN_1` reader - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien1R = crate :: BitReader ; # [doc = "Field `SPIEN_1` writer - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIEN_2` reader - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien2R = crate :: BitReader ; # [doc = "Field `SPIEN_2` writer - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIEN_3` reader - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien3R = crate :: BitReader ; # [doc = "Field `SPIEN_3` writer - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spien3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDAT_0` reader - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat0R = crate :: BitReader ; # [doc = "Field `SPIDAT_0` writer - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDAT_1` reader - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat1R = crate :: BitReader ; # [doc = "Field `SPIDAT_1` writer - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
pub type Spidat1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPICLK` reader - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
pub type SpiclkR = crate :: BitReader ; # [doc = "Field `SPICLK` writer - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
pub type SpiclkW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKD` reader - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
pub type WakdR = crate :: BitReader ; # [doc = "Field `WAKD` writer - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
pub type WakdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDATDIR0` reader - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
pub type Spidatdir0R = crate :: BitReader ; # [doc = "Field `SPIDATDIR0` writer - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
pub type Spidatdir0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIDATDIR1` reader - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
pub type Spidatdir1R = crate :: BitReader ; # [doc = "Field `SPIDATDIR1` writer - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
pub type Spidatdir1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIENDIR` reader - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
pub type SpiendirR = crate :: BitReader ; # [doc = "Field `SPIENDIR` writer - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
pub type SpiendirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SSB` reader - 11:11\\]
Set status bit - (RW )"]
pub type SsbR = crate :: BitReader ; # [doc = "Field `SSB` writer - 11:11\\]
Set status bit - (RW )"]
pub type SsbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_17` reader - 31:12\\]
Reads returns 0 - (RO )"]
pub type Reserved17R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_17` writer - 31:12\\]
Reads returns 0 - (RO )"]
pub type Reserved17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_0 (& self) -> Spien0R { Spien0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_1 (& self) -> Spien1R { Spien1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_2 (& self) -> Spien2R { Spien2R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spien_3 (& self) -> Spien3R { Spien3R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spidat_0 (& self) -> Spidat0R { Spidat0R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
pub fn spidat_1 (& self) -> Spidat1R { Spidat1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
# [inline (always)]
pub fn spiclk (& self) -> SpiclkR { SpiclkR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
# [inline (always)]
pub fn wakd (& self) -> WakdR { WakdR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
# [inline (always)]
pub fn spidatdir0 (& self) -> Spidatdir0R { Spidatdir0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
# [inline (always)]
pub fn spidatdir1 (& self) -> Spidatdir1R { Spidatdir1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
# [inline (always)]
pub fn spiendir (& self) -> SpiendirR { SpiendirR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Set status bit - (RW )"]
# [inline (always)]
pub fn ssb (& self) -> SsbR { SsbR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:31 - 31:12\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_17 (& self) -> Reserved17R { Reserved17R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPIEN\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_0 (& mut self) -> Spien0W < SystSpec > { Spien0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPIEN\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_1 (& mut self) -> Spien1W < SystSpec > { Spien1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
SPIEN\\[2\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[2\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[2\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_2 (& mut self) -> Spien2W < SystSpec > { Spien2W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
SPIEN\\[3\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the SPIENT\\[3\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIEN\\[3\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spien_3 (& mut self) -> Spien3W < SystSpec > { Spien3W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
SPIDAT\\[0\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR0\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[0\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR0\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[0\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spidat_0 (& mut self) -> Spidat0W < SystSpec > { Spidat0W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
SPIDAT\\[1\\]
line \\[signal data value\\]
If MCSPI_SYST\\[SPIDATDIR1\\]
= 0 \\[output mode direction\\]
the SPIDAT\\[1\\]
line is driven high or low according to the value written into this register If MCSPI_SYST\\[SPIDATDIR1\\]
= 1 \\[input mode direction\\]
this bit returns the value on the SPIDAT\\[1\\]
line \\[high or low\\]
and a write into this bit has no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn spidat_1 (& mut self) -> Spidat1W < SystSpec > { Spidat1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
SPICLK line \\[signal data value\\]
If MCSPI_SYST\\[SPIENDIR\\]
= 1 \\[input mode direction\\]
this bit returns the value on the CLKSPI line \\[high or low\\]
and a write into this bit has no effect If MCSPI_SYST\\[SPIENDIR\\]
= 0 \\[output mode direction\\]
the CLKSPI line is driven high or low according to the value written into this register - (RW )"]
# [inline (always)]
# [must_use]
pub fn spiclk (& mut self) -> SpiclkW < SystSpec > { SpiclkW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
SWAKEUP output \\[signal data value of internal signal to system\\]
The signal is driven high or low according to the value written into this register bit - (RW )"]
# [inline (always)]
# [must_use]
pub fn wakd (& mut self) -> WakdW < SystSpec > { WakdW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Set the direction of the SPIDAT\\[0\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn spidatdir0 (& mut self) -> Spidatdir0W < SystSpec > { Spidatdir0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Set the direction of the SPIDAT\\[1\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn spidatdir1 (& mut self) -> Spidatdir1W < SystSpec > { Spidatdir1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Set the direction of the SPIEN\\[3:0\\]
lines and SPICLK line - (RW )"]
# [inline (always)]
# [must_use]
pub fn spiendir (& mut self) -> SpiendirW < SystSpec > { SpiendirW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Set status bit - (RW )"]
# [inline (always)]
# [must_use]
pub fn ssb (& mut self) -> SsbW < SystSpec > { SsbW :: new (self , 11) } # [doc = "Bits 12:31 - 31:12\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_17 (& mut self) -> Reserved17W < SystSpec > { Reserved17W :: new (self , 12) } } # [doc = "This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`syst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SystSpec ; impl crate :: RegisterSpec for SystSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`syst::R`](R) reader structure"]
impl crate :: Readable for SystSpec { } # [doc = "`write(|w| ..)` method takes [`syst::W`](W) writer structure"]
impl crate :: Writable for SystSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYST to value 0"]
impl crate :: Resettable for SystSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MODULCTRL (rw) register accessor: This register is dedicated to the configuration of the serial port interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`modulctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modulctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modulctrl`]
module"]
# [doc (alias = "MODULCTRL")]
pub type Modulctrl = crate :: Reg < modulctrl :: ModulctrlSpec > ; # [doc = "This register is dedicated to the configuration of the serial port interface."]
pub mod modulctrl { # [doc = "Register `MODULCTRL` reader"]
pub type R = crate :: R < ModulctrlSpec > ; # [doc = "Register `MODULCTRL` writer"]
pub type W = crate :: W < ModulctrlSpec > ; # [doc = "Field `SINGLE` reader - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
pub type SingleR = crate :: BitReader ; # [doc = "Field `SINGLE` writer - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
pub type SingleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PIN34` reader - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
pub type Pin34R = crate :: BitReader ; # [doc = "Field `PIN34` writer - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
pub type Pin34W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MS` reader - 2:2\\]
Master/ Slave - (RW )"]
pub type MsR = crate :: BitReader ; # [doc = "Field `MS` writer - 2:2\\]
Master/ Slave - (RW )"]
pub type MsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SYSTEM_TEST` reader - 3:3\\]
Enables the system test mode - (RW )"]
pub type SystemTestR = crate :: BitReader ; # [doc = "Field `SYSTEM_TEST` writer - 3:3\\]
Enables the system test mode - (RW )"]
pub type SystemTestW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `INITDLY` reader - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
pub type InitdlyR = crate :: FieldReader ; # [doc = "Field `INITDLY` writer - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
pub type InitdlyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `MOA` reader - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
pub type MoaR = crate :: BitReader ; # [doc = "Field `MOA` writer - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
pub type MoaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FDAA` reader - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
pub type FdaaR = crate :: BitReader ; # [doc = "Field `FDAA` writer - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
pub type FdaaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_11` reader - 31:9\\]
Reads returns 0 - (RO )"]
pub type Reserved11R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_11` writer - 31:9\\]
Reads returns 0 - (RO )"]
pub type Reserved11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 23 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
# [inline (always)]
pub fn single (& self) -> SingleR { SingleR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
# [inline (always)]
pub fn pin34 (& self) -> Pin34R { Pin34R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Master/ Slave - (RW )"]
# [inline (always)]
pub fn ms (& self) -> MsR { MsR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Enables the system test mode - (RW )"]
# [inline (always)]
pub fn system_test (& self) -> SystemTestR { SystemTestR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
# [inline (always)]
pub fn initdly (& self) -> InitdlyR { InitdlyR :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
# [inline (always)]
pub fn moa (& self) -> MoaR { MoaR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
# [inline (always)]
pub fn fdaa (& self) -> FdaaR { FdaaR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:31 - 31:9\\]
Reads returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_11 (& self) -> Reserved11R { Reserved11R :: new ((self . bits >> 9) & 0x007f_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Single channel / Multi Channel \\[master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn single (& mut self) -> SingleW < ModulctrlSpec > { SingleW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW )"]
# [inline (always)]
# [must_use]
pub fn pin34 (& mut self) -> Pin34W < ModulctrlSpec > { Pin34W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Master/ Slave - (RW )"]
# [inline (always)]
# [must_use]
pub fn ms (& mut self) -> MsW < ModulctrlSpec > { MsW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Enables the system test mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn system_test (& mut self) -> SystemTestW < ModulctrlSpec > { SystemTestW :: new (self , 3) } # [doc = "Bits 4:6 - 6:4\\]
Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW )"]
# [inline (always)]
# [must_use]
pub fn initdly (& mut self) -> InitdlyW < ModulctrlSpec > { InitdlyW :: new (self , 4) } # [doc = "Bit 7 - 7:7\\]
Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL &lt; 16 - (RW )"]
# [inline (always)]
# [must_use]
pub fn moa (& mut self) -> MoaW < ModulctrlSpec > { MoaW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX\\[i\\]
and MCSPI_RX\\[i\\]
registers - (RW )"]
# [inline (always)]
# [must_use]
pub fn fdaa (& mut self) -> FdaaW < ModulctrlSpec > { FdaaW :: new (self , 8) } # [doc = "Bits 9:31 - 31:9\\]
Reads returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_11 (& mut self) -> Reserved11W < ModulctrlSpec > { Reserved11W :: new (self , 9) } } # [doc = "This register is dedicated to the configuration of the serial port interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`modulctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modulctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ModulctrlSpec ; impl crate :: RegisterSpec for ModulctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`modulctrl::R`](R) reader structure"]
impl crate :: Readable for ModulctrlSpec { } # [doc = "`write(|w| ..)` method takes [`modulctrl::W`](W) writer structure"]
impl crate :: Writable for ModulctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MODULCTRL to value 0"]
impl crate :: Resettable for ModulctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH0CONF (rw) register accessor: This register is dedicated to the configuration of the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0conf`]
module"]
# [doc (alias = "CH0CONF")]
pub type Ch0conf = crate :: Reg < ch0conf :: Ch0confSpec > ; # [doc = "This register is dedicated to the configuration of the channel 0"]
pub mod ch0conf { # [doc = "Register `CH0CONF` reader"]
pub type R = crate :: R < Ch0confSpec > ; # [doc = "Register `CH0CONF` writer"]
pub type W = crate :: W < Ch0confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPIENSLV` reader - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
pub type SpienslvR = crate :: FieldReader ; # [doc = "Field `SPIENSLV` writer - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
pub type SpienslvW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS0` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs0R = crate :: FieldReader ; # [doc = "Field `TCS0` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
# [inline (always)]
pub fn spienslv (& self) -> SpienslvR { SpienslvR :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs0 (& self) -> Tcs0R { Tcs0R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch0confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch0confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch0confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch0confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch0confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch0confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch0confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch0confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch0confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch0confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch0confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch0confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch0confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW )"]
# [inline (always)]
# [must_use]
pub fn spienslv (& mut self) -> SpienslvW < Ch0confSpec > { SpienslvW :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch0confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch0confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs0 (& mut self) -> Tcs0W < Ch0confSpec > { Tcs0W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch0confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch0confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch0confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch0confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch0confSpec ; impl crate :: RegisterSpec for Ch0confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch0conf::R`](R) reader structure"]
impl crate :: Readable for Ch0confSpec { } # [doc = "`write(|w| ..)` method takes [`ch0conf::W`](W) writer structure"]
impl crate :: Writable for Ch0confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH0CONF to value 0"]
impl crate :: Resettable for Ch0confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH0STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0stat`]
module"]
# [doc (alias = "CH0STAT")]
pub type Ch0stat = crate :: Reg < ch0stat :: Ch0statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 0"]
pub mod ch0stat { # [doc = "Register `CH0STAT` reader"]
pub type R = crate :: R < Ch0statSpec > ; # [doc = "Register `CH0STAT` writer"]
pub type W = crate :: W < Ch0statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch0statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch0statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch0statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch0statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch0statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch0statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch0statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch0statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch0statSpec ; impl crate :: RegisterSpec for Ch0statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch0stat::R`](R) reader structure"]
impl crate :: Readable for Ch0statSpec { } # [doc = "`write(|w| ..)` method takes [`ch0stat::W`](W) writer structure"]
impl crate :: Writable for Ch0statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH0STAT to value 0"]
impl crate :: Resettable for Ch0statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH0CTRL (rw) register accessor: This register is dedicated to enable the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0ctrl`]
module"]
# [doc (alias = "CH0CTRL")]
pub type Ch0ctrl = crate :: Reg < ch0ctrl :: Ch0ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 0"]
pub mod ch0ctrl { # [doc = "Register `CH0CTRL` reader"]
pub type R = crate :: R < Ch0ctrlSpec > ; # [doc = "Register `CH0CTRL` writer"]
pub type W = crate :: W < Ch0ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch0ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch0ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch0ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch0ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch0ctrlSpec ; impl crate :: RegisterSpec for Ch0ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch0ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch0ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch0ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch0ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH0CTRL to value 0"]
impl crate :: Resettable for Ch0ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX0 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx0`]
module"]
# [doc (alias = "TX0")]
pub type Tx0 = crate :: Reg < tx0 :: Tx0Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx0 { # [doc = "Register `TX0` reader"]
pub type R = crate :: R < Tx0Spec > ; # [doc = "Register `TX0` writer"]
pub type W = crate :: W < Tx0Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 0 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 0 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx0Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx0Spec ; impl crate :: RegisterSpec for Tx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx0::R`](R) reader structure"]
impl crate :: Readable for Tx0Spec { } # [doc = "`write(|w| ..)` method takes [`tx0::W`](W) writer structure"]
impl crate :: Writable for Tx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX0 to value 0"]
impl crate :: Resettable for Tx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX0 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx0`]
module"]
# [doc (alias = "RX0")]
pub type Rx0 = crate :: Reg < rx0 :: Rx0Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx0 { # [doc = "Register `RX0` reader"]
pub type R = crate :: R < Rx0Spec > ; # [doc = "Register `RX0` writer"]
pub type W = crate :: W < Rx0Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 0 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 0 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 0 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx0Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx0Spec ; impl crate :: RegisterSpec for Rx0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx0::R`](R) reader structure"]
impl crate :: Readable for Rx0Spec { } # [doc = "`write(|w| ..)` method takes [`rx0::W`](W) writer structure"]
impl crate :: Writable for Rx0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX0 to value 0"]
impl crate :: Resettable for Rx0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1CONF (rw) register accessor: This register is dedicated to the configuration of the channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1conf`]
module"]
# [doc (alias = "CH1CONF")]
pub type Ch1conf = crate :: Reg < ch1conf :: Ch1confSpec > ; # [doc = "This register is dedicated to the configuration of the channel."]
pub mod ch1conf { # [doc = "Register `CH1CONF` reader"]
pub type R = crate :: R < Ch1confSpec > ; # [doc = "Register `CH1CONF` writer"]
pub type W = crate :: W < Ch1confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS1` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs1R = crate :: FieldReader ; # [doc = "Field `TCS1` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs1 (& self) -> Tcs1R { Tcs1R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch1confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch1confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch1confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch1confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch1confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch1confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch1confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch1confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch1confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch1confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch1confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch1confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch1confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch1confSpec > { Reserved1W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch1confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch1confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs1 (& mut self) -> Tcs1W < Ch1confSpec > { Tcs1W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch1confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch1confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch1confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch1confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch1confSpec ; impl crate :: RegisterSpec for Ch1confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1conf::R`](R) reader structure"]
impl crate :: Readable for Ch1confSpec { } # [doc = "`write(|w| ..)` method takes [`ch1conf::W`](W) writer structure"]
impl crate :: Writable for Ch1confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1CONF to value 0"]
impl crate :: Resettable for Ch1confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1stat`]
module"]
# [doc (alias = "CH1STAT")]
pub type Ch1stat = crate :: Reg < ch1stat :: Ch1statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 1"]
pub mod ch1stat { # [doc = "Register `CH1STAT` reader"]
pub type R = crate :: R < Ch1statSpec > ; # [doc = "Register `CH1STAT` writer"]
pub type W = crate :: W < Ch1statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch1statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch1statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch1statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch1statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch1statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch1statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch1statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch1statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch1statSpec ; impl crate :: RegisterSpec for Ch1statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1stat::R`](R) reader structure"]
impl crate :: Readable for Ch1statSpec { } # [doc = "`write(|w| ..)` method takes [`ch1stat::W`](W) writer structure"]
impl crate :: Writable for Ch1statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1STAT to value 0"]
impl crate :: Resettable for Ch1statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1CTRL (rw) register accessor: This register is dedicated to enable the channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1ctrl`]
module"]
# [doc (alias = "CH1CTRL")]
pub type Ch1ctrl = crate :: Reg < ch1ctrl :: Ch1ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 1"]
pub mod ch1ctrl { # [doc = "Register `CH1CTRL` reader"]
pub type R = crate :: R < Ch1ctrlSpec > ; # [doc = "Register `CH1CTRL` writer"]
pub type W = crate :: W < Ch1ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch1ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch1ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch1ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch1ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch1ctrlSpec ; impl crate :: RegisterSpec for Ch1ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch1ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch1ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch1ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1CTRL to value 0"]
impl crate :: Resettable for Ch1ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX1 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx1`]
module"]
# [doc (alias = "TX1")]
pub type Tx1 = crate :: Reg < tx1 :: Tx1Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx1 { # [doc = "Register `TX1` reader"]
pub type R = crate :: R < Tx1Spec > ; # [doc = "Register `TX1` writer"]
pub type W = crate :: W < Tx1Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 1 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 1 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx1Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx1Spec ; impl crate :: RegisterSpec for Tx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx1::R`](R) reader structure"]
impl crate :: Readable for Tx1Spec { } # [doc = "`write(|w| ..)` method takes [`tx1::W`](W) writer structure"]
impl crate :: Writable for Tx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX1 to value 0"]
impl crate :: Resettable for Tx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX1 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx1`]
module"]
# [doc (alias = "RX1")]
pub type Rx1 = crate :: Reg < rx1 :: Rx1Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx1 { # [doc = "Register `RX1` reader"]
pub type R = crate :: R < Rx1Spec > ; # [doc = "Register `RX1` writer"]
pub type W = crate :: W < Rx1Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 1 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 1 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 1 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx1Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx1Spec ; impl crate :: RegisterSpec for Rx1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx1::R`](R) reader structure"]
impl crate :: Readable for Rx1Spec { } # [doc = "`write(|w| ..)` method takes [`rx1::W`](W) writer structure"]
impl crate :: Writable for Rx1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX1 to value 0"]
impl crate :: Resettable for Rx1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2CONF (rw) register accessor: This register is dedicated to the configuration of the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2conf`]
module"]
# [doc (alias = "CH2CONF")]
pub type Ch2conf = crate :: Reg < ch2conf :: Ch2confSpec > ; # [doc = "This register is dedicated to the configuration of the channel 2"]
pub mod ch2conf { # [doc = "Register `CH2CONF` reader"]
pub type R = crate :: R < Ch2confSpec > ; # [doc = "Register `CH2CONF` writer"]
pub type W = crate :: W < Ch2confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS2` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs2R = crate :: FieldReader ; # [doc = "Field `TCS2` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs2 (& self) -> Tcs2R { Tcs2R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch2confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch2confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch2confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch2confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch2confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch2confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch2confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch2confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch2confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch2confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch2confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch2confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch2confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch2confSpec > { Reserved1W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch2confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch2confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs2 (& mut self) -> Tcs2W < Ch2confSpec > { Tcs2W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch2confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch2confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch2confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch2confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch2confSpec ; impl crate :: RegisterSpec for Ch2confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2conf::R`](R) reader structure"]
impl crate :: Readable for Ch2confSpec { } # [doc = "`write(|w| ..)` method takes [`ch2conf::W`](W) writer structure"]
impl crate :: Writable for Ch2confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2CONF to value 0"]
impl crate :: Resettable for Ch2confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2stat`]
module"]
# [doc (alias = "CH2STAT")]
pub type Ch2stat = crate :: Reg < ch2stat :: Ch2statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 2"]
pub mod ch2stat { # [doc = "Register `CH2STAT` reader"]
pub type R = crate :: R < Ch2statSpec > ; # [doc = "Register `CH2STAT` writer"]
pub type W = crate :: W < Ch2statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch2statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch2statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch2statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch2statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch2statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch2statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch2statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch2statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch2statSpec ; impl crate :: RegisterSpec for Ch2statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2stat::R`](R) reader structure"]
impl crate :: Readable for Ch2statSpec { } # [doc = "`write(|w| ..)` method takes [`ch2stat::W`](W) writer structure"]
impl crate :: Writable for Ch2statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2STAT to value 0"]
impl crate :: Resettable for Ch2statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2CTRL (rw) register accessor: This register is dedicated to enable the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2ctrl`]
module"]
# [doc (alias = "CH2CTRL")]
pub type Ch2ctrl = crate :: Reg < ch2ctrl :: Ch2ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 2"]
pub mod ch2ctrl { # [doc = "Register `CH2CTRL` reader"]
pub type R = crate :: R < Ch2ctrlSpec > ; # [doc = "Register `CH2CTRL` writer"]
pub type W = crate :: W < Ch2ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch2ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch2ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch2ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch2ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch2ctrlSpec ; impl crate :: RegisterSpec for Ch2ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch2ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch2ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch2ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2CTRL to value 0"]
impl crate :: Resettable for Ch2ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX2 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx2`]
module"]
# [doc (alias = "TX2")]
pub type Tx2 = crate :: Reg < tx2 :: Tx2Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx2 { # [doc = "Register `TX2` reader"]
pub type R = crate :: R < Tx2Spec > ; # [doc = "Register `TX2` writer"]
pub type W = crate :: W < Tx2Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 2 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 2 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx2Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx2Spec ; impl crate :: RegisterSpec for Tx2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx2::R`](R) reader structure"]
impl crate :: Readable for Tx2Spec { } # [doc = "`write(|w| ..)` method takes [`tx2::W`](W) writer structure"]
impl crate :: Writable for Tx2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX2 to value 0"]
impl crate :: Resettable for Tx2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX2 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx2`]
module"]
# [doc (alias = "RX2")]
pub type Rx2 = crate :: Reg < rx2 :: Rx2Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx2 { # [doc = "Register `RX2` reader"]
pub type R = crate :: R < Rx2Spec > ; # [doc = "Register `RX2` writer"]
pub type W = crate :: W < Rx2Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 2 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 2 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 2 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx2Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx2Spec ; impl crate :: RegisterSpec for Rx2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx2::R`](R) reader structure"]
impl crate :: Readable for Rx2Spec { } # [doc = "`write(|w| ..)` method takes [`rx2::W`](W) writer structure"]
impl crate :: Writable for Rx2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX2 to value 0"]
impl crate :: Resettable for Rx2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3CONF (rw) register accessor: This register is dedicated to the configuration of the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3conf`]
module"]
# [doc (alias = "CH3CONF")]
pub type Ch3conf = crate :: Reg < ch3conf :: Ch3confSpec > ; # [doc = "This register is dedicated to the configuration of the channel 3"]
pub mod ch3conf { # [doc = "Register `CH3CONF` reader"]
pub type R = crate :: R < Ch3confSpec > ; # [doc = "Register `CH3CONF` writer"]
pub type W = crate :: W < Ch3confSpec > ; # [doc = "Field `PHA` reader - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaR = crate :: BitReader ; # [doc = "Field `PHA` writer - 0:0\\]
SPICLK phase - (RW )"]
pub type PhaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POL` reader - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolR = crate :: BitReader ; # [doc = "Field `POL` writer - 1:1\\]
SPICLK polarity - (RW )"]
pub type PolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKD` reader - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdR = crate :: FieldReader ; # [doc = "Field `CLKD` writer - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
pub type ClkdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EPOL` reader - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolR = crate :: BitReader ; # [doc = "Field `EPOL` writer - 6:6\\]
SPIEN polarity - (RW )"]
pub type EpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WL` reader - 11:7\\]
SPI word length - (RW )"]
pub type WlR = crate :: FieldReader ; # [doc = "Field `WL` writer - 11:7\\]
SPI word length - (RW )"]
pub type WlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TRM` reader - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmR = crate :: FieldReader ; # [doc = "Field `TRM` writer - 13:12\\]
Transmit/Receive modes - (RW )"]
pub type TrmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DMAW` reader - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawR = crate :: BitReader ; # [doc = "Field `DMAW` writer - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
pub type DmawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarR = crate :: BitReader ; # [doc = "Field `DMAR` writer - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
pub type DmarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE0` reader - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0R = crate :: BitReader ; # [doc = "Field `DPE0` writer - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
pub type Dpe0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DPE1` reader - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1R = crate :: BitReader ; # [doc = "Field `DPE1` writer - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
pub type Dpe1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IS` reader - 18:18\\]
Input Select - (RW )"]
pub type IsR = crate :: BitReader ; # [doc = "Field `IS` writer - 18:18\\]
Input Select - (RW )"]
pub type IsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TURBO` reader - 19:19\\]
Turbo mode - (RW )"]
pub type TurboR = crate :: BitReader ; # [doc = "Field `TURBO` writer - 19:19\\]
Turbo mode - (RW )"]
pub type TurboW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FORCE` reader - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceR = crate :: BitReader ; # [doc = "Field `FORCE` writer - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
pub type ForceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 22:21\\]
read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SBE` reader - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeR = crate :: BitReader ; # [doc = "Field `SBE` writer - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
pub type SbeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SBPOL` reader - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolR = crate :: BitReader ; # [doc = "Field `SBPOL` writer - 24:24\\]
Start bit polarity - (RW )"]
pub type SbpolW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCS3` reader - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs3R = crate :: FieldReader ; # [doc = "Field `TCS3` writer - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
pub type Tcs3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `FFEW` reader - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewR = crate :: BitReader ; # [doc = "Field `FFEW` writer - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
pub type FfewW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FFER` reader - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferR = crate :: BitReader ; # [doc = "Field `FFER` writer - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
pub type FferW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKG` reader - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgR = crate :: BitReader ; # [doc = "Field `CLKG` writer - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
pub type ClkgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_0` reader - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0R = crate :: FieldReader ; # [doc = "Field `RESERVED_0` writer - 31:30\\]
read returns 0 - (RO )"]
pub type Reserved0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
pub fn pha (& self) -> PhaR { PhaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
pub fn pol (& self) -> PolR { PolR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
pub fn clkd (& self) -> ClkdR { ClkdR :: new (((self . bits >> 2) & 0x0f) as u8) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
pub fn epol (& self) -> EpolR { EpolR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
pub fn wl (& self) -> WlR { WlR :: new (((self . bits >> 7) & 0x1f) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
pub fn trm (& self) -> TrmR { TrmR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
pub fn dmaw (& self) -> DmawR { DmawR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
pub fn dmar (& self) -> DmarR { DmarR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe0 (& self) -> Dpe0R { Dpe0R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
pub fn dpe1 (& self) -> Dpe1R { Dpe1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
pub fn is (& self) -> IsR { IsR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
pub fn turbo (& self) -> TurboR { TurboR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
pub fn force (& self) -> ForceR { ForceR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 21) & 3) as u8) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
pub fn sbe (& self) -> SbeR { SbeR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
pub fn sbpol (& self) -> SbpolR { SbpolR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
pub fn tcs3 (& self) -> Tcs3R { Tcs3R :: new (((self . bits >> 25) & 3) as u8) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffew (& self) -> FfewR { FfewR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
pub fn ffer (& self) -> FferR { FferR :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
pub fn clkg (& self) -> ClkgR { ClkgR :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_0 (& self) -> Reserved0R { Reserved0R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
SPICLK phase - (RW )"]
# [inline (always)]
# [must_use]
pub fn pha (& mut self) -> PhaW < Ch3confSpec > { PhaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
SPICLK polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn pol (& mut self) -> PolW < Ch3confSpec > { PolW :: new (self , 1) } # [doc = "Bits 2:5 - 5:2\\]
Frequency divider for SPICLK \\[only when the module is a Master SPI device\\]
A programmable clock divider divides the SPI reference clock \\[CLKSPIREF\\]
with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF\\[CLKG\\]
is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL\\[EXTCLK\\]
registerThe value description below defines the clock ratio when MCSPI_CHCONF\\[CLKG\\]
is set to 0 - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkd (& mut self) -> ClkdW < Ch3confSpec > { ClkdW :: new (self , 2) } # [doc = "Bit 6 - 6:6\\]
SPIEN polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn epol (& mut self) -> EpolW < Ch3confSpec > { EpolW :: new (self , 6) } # [doc = "Bits 7:11 - 11:7\\]
SPI word length - (RW )"]
# [inline (always)]
# [must_use]
pub fn wl (& mut self) -> WlW < Ch3confSpec > { WlW :: new (self , 7) } # [doc = "Bits 12:13 - 13:12\\]
Transmit/Receive modes - (RW )"]
# [inline (always)]
# [must_use]
pub fn trm (& mut self) -> TrmW < Ch3confSpec > { TrmW :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmaw (& mut self) -> DmawW < Ch3confSpec > { DmawW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW )"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DmarW < Ch3confSpec > { DmarW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
Transmission Enable for data line 0 \\[SPIDATAGZEN\\[0\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe0 (& mut self) -> Dpe0W < Ch3confSpec > { Dpe0W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Transmission Enable for data line 1 \\[SPIDATAGZEN\\[1\\]\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn dpe1 (& mut self) -> Dpe1W < Ch3confSpec > { Dpe1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Input Select - (RW )"]
# [inline (always)]
# [must_use]
pub fn is (& mut self) -> IsW < Ch3confSpec > { IsW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Turbo mode - (RW )"]
# [inline (always)]
# [must_use]
pub fn turbo (& mut self) -> TurboW < Ch3confSpec > { TurboW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Manual SPIEN assertion to keep SPIEN active between SPI words \\[single channel master mode only\\]
- (RW )"]
# [inline (always)]
# [must_use]
pub fn force (& mut self) -> ForceW < Ch3confSpec > { ForceW :: new (self , 20) } # [doc = "Bits 21:22 - 22:21\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch3confSpec > { Reserved1W :: new (self , 21) } # [doc = "Bit 23 - 23:23\\]
Start bit enable for SPI transfer - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbe (& mut self) -> SbeW < Ch3confSpec > { SbeW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Start bit polarity - (RW )"]
# [inline (always)]
# [must_use]
pub fn sbpol (& mut self) -> SbpolW < Ch3confSpec > { SbpolW :: new (self , 24) } # [doc = "Bits 25:26 - 26:25\\]
Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW )"]
# [inline (always)]
# [must_use]
pub fn tcs3 (& mut self) -> Tcs3W < Ch3confSpec > { Tcs3W :: new (self , 25) } # [doc = "Bit 27 - 27:27\\]
FIFO enabled for Transmit:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffew (& mut self) -> FfewW < Ch3confSpec > { FfewW :: new (self , 27) } # [doc = "Bit 28 - 28:28\\]
FIFO enabled for receive:Only one channel can have this bit field set - (RW )"]
# [inline (always)]
# [must_use]
pub fn ffer (& mut self) -> FferW < Ch3confSpec > { FferW :: new (self , 28) } # [doc = "Bit 29 - 29:29\\]
Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL\\[EXTCLK\\]
must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF\\[CLKD\\]
and MCSPI_CHCTRL\\[EXTCLK\\]
values - (RW )"]
# [inline (always)]
# [must_use]
pub fn clkg (& mut self) -> ClkgW < Ch3confSpec > { ClkgW :: new (self , 29) } # [doc = "Bits 30:31 - 31:30\\]
read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_0 (& mut self) -> Reserved0W < Ch3confSpec > { Reserved0W :: new (self , 30) } } # [doc = "This register is dedicated to the configuration of the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch3confSpec ; impl crate :: RegisterSpec for Ch3confSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3conf::R`](R) reader structure"]
impl crate :: Readable for Ch3confSpec { } # [doc = "`write(|w| ..)` method takes [`ch3conf::W`](W) writer structure"]
impl crate :: Writable for Ch3confSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3CONF to value 0"]
impl crate :: Resettable for Ch3confSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3STAT (rw) register accessor: This register provides status information about transmitter and receiver registers of channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3stat`]
module"]
# [doc (alias = "CH3STAT")]
pub type Ch3stat = crate :: Reg < ch3stat :: Ch3statSpec > ; # [doc = "This register provides status information about transmitter and receiver registers of channel 3"]
pub mod ch3stat { # [doc = "Register `CH3STAT` reader"]
pub type R = crate :: R < Ch3statSpec > ; # [doc = "Register `CH3STAT` writer"]
pub type W = crate :: W < Ch3statSpec > ; # [doc = "Field `RXS` reader - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsR = crate :: BitReader ; # [doc = "Field `RXS` writer - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
pub type RxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXS` reader - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsR = crate :: BitReader ; # [doc = "Field `TXS` writer - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
pub type TxsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOT` reader - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotR = crate :: BitReader ; # [doc = "Field `EOT` writer - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
pub type EotW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFE` reader - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeR = crate :: BitReader ; # [doc = "Field `TXFFE` writer - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
pub type TxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXFFF` reader - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffR = crate :: BitReader ; # [doc = "Field `TXFFF` writer - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
pub type TxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFE` reader - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeR = crate :: BitReader ; # [doc = "Field `RXFFE` writer - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
pub type RxffeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXFFF` reader - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffR = crate :: BitReader ; # [doc = "Field `RXFFF` writer - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
pub type RxfffW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_2` reader - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `RESERVED_2` writer - 31:7\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
pub fn rxs (& self) -> RxsR { RxsR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
pub fn txs (& self) -> TxsR { TxsR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
pub fn eot (& self) -> EotR { EotR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn txffe (& self) -> TxffeR { TxffeR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
pub fn txfff (& self) -> TxfffR { TxfffR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
pub fn rxffe (& self) -> RxffeR { RxffeR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
pub fn rxfff (& self) -> RxfffR { RxfffR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel \"i\" Receiver Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxs (& mut self) -> RxsW < Ch3statSpec > { RxsW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Channel \"i\" Transmitter Register Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txs (& mut self) -> TxsW < Ch3statSpec > { TxsW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Channel \"i\" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format \\[Transmit/Receive modes Turbo mode\\]
See dedicated chapters for details - (RO )"]
# [inline (always)]
# [must_use]
pub fn eot (& mut self) -> EotW < Ch3statSpec > { EotW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Channel \"i\" FIFO Transmit Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txffe (& mut self) -> TxffeW < Ch3statSpec > { TxffeW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Channel \"i\" FIFO Transmit Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn txfff (& mut self) -> TxfffW < Ch3statSpec > { TxfffW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Channel \"i\" FIFO Receive Buffer Empty Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxffe (& mut self) -> RxffeW < Ch3statSpec > { RxffeW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Channel \"i\" FIFO Receive Buffer Full Status - (RO )"]
# [inline (always)]
# [must_use]
pub fn rxfff (& mut self) -> RxfffW < Ch3statSpec > { RxfffW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch3statSpec > { Reserved2W :: new (self , 7) } } # [doc = "This register provides status information about transmitter and receiver registers of channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch3statSpec ; impl crate :: RegisterSpec for Ch3statSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3stat::R`](R) reader structure"]
impl crate :: Readable for Ch3statSpec { } # [doc = "`write(|w| ..)` method takes [`ch3stat::W`](W) writer structure"]
impl crate :: Writable for Ch3statSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3STAT to value 0"]
impl crate :: Resettable for Ch3statSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3CTRL (rw) register accessor: This register is dedicated to enable the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3ctrl`]
module"]
# [doc (alias = "CH3CTRL")]
pub type Ch3ctrl = crate :: Reg < ch3ctrl :: Ch3ctrlSpec > ; # [doc = "This register is dedicated to enable the channel 3"]
pub mod ch3ctrl { # [doc = "Register `CH3CTRL` reader"]
pub type R = crate :: R < Ch3ctrlSpec > ; # [doc = "Register `CH3CTRL` writer"]
pub type W = crate :: W < Ch3ctrlSpec > ; # [doc = "Field `EN` reader - 0:0\\]
Channel Enable - (RW )"]
pub type EnR = crate :: BitReader ; # [doc = "Field `EN` writer - 0:0\\]
Channel Enable - (RW )"]
pub type EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESERVED_1` reader - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `RESERVED_1` writer - 7:1\\]
Read returns 0 - (RO )"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EXTCLK` reader - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkR = crate :: FieldReader ; # [doc = "Field `EXTCLK` writer - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
pub type ExtclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RESERVED_2` reader - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `RESERVED_2` writer - 31:16\\]
Read returns 0 - (RO )"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
pub fn en (& self) -> EnR { EnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
pub fn extclk (& self) -> ExtclkR { ExtclkR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Channel Enable - (RW )"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EnW < Ch3ctrlSpec > { EnW :: new (self , 0) } # [doc = "Bits 1:7 - 7:1\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < Ch3ctrlSpec > { Reserved1W :: new (self , 1) } # [doc = "Bits 8:15 - 15:8\\]
Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF\\[CLKD\\]
register for clock ratio only when granularity is one clock cycle \\[MCSPI_CHCONF\\[CLKG\\]
set to 1\\]
Then the max value reached is 4096 clock divider ratio - (RW )"]
# [inline (always)]
# [must_use]
pub fn extclk (& mut self) -> ExtclkW < Ch3ctrlSpec > { ExtclkW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Read returns 0 - (RO )"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < Ch3ctrlSpec > { Reserved2W :: new (self , 16) } } # [doc = "This register is dedicated to enable the channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ch3ctrlSpec ; impl crate :: RegisterSpec for Ch3ctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3ctrl::R`](R) reader structure"]
impl crate :: Readable for Ch3ctrlSpec { } # [doc = "`write(|w| ..)` method takes [`ch3ctrl::W`](W) writer structure"]
impl crate :: Writable for Ch3ctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3CTRL to value 0"]
impl crate :: Resettable for Ch3ctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TX3 (rw) register accessor: This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx3`]
module"]
# [doc (alias = "TX3")]
pub type Tx3 = crate :: Reg < tx3 :: Tx3Spec > ; # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is."]
pub mod tx3 { # [doc = "Register `TX3` reader"]
pub type R = crate :: R < Tx3Spec > ; # [doc = "Register `TX3` writer"]
pub type W = crate :: W < Tx3Spec > ; # [doc = "Field `TDATA` reader - 31:0\\]
Channel 3 Data to transmit - (RW )"]
pub type TdataR = crate :: FieldReader < u32 > ; # [doc = "Field `TDATA` writer - 31:0\\]
Channel 3 Data to transmit - (RW )"]
pub type TdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Data to transmit - (RW )"]
# [inline (always)]
pub fn tdata (& self) -> TdataR { TdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Data to transmit - (RW )"]
# [inline (always)]
# [must_use]
pub fn tdata (& mut self) -> TdataW < Tx3Spec > { TdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word to transmit on the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tx3Spec ; impl crate :: RegisterSpec for Tx3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`tx3::R`](R) reader structure"]
impl crate :: Readable for Tx3Spec { } # [doc = "`write(|w| ..)` method takes [`tx3::W`](W) writer structure"]
impl crate :: Writable for Tx3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TX3 to value 0"]
impl crate :: Resettable for Tx3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RX3 (rw) register accessor: This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx3`]
module"]
# [doc (alias = "RX3")]
pub type Rx3 = crate :: Reg < rx3 :: Rx3Spec > ; # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is."]
pub mod rx3 { # [doc = "Register `RX3` reader"]
pub type R = crate :: R < Rx3Spec > ; # [doc = "Register `RX3` writer"]
pub type W = crate :: W < Rx3Spec > ; # [doc = "Field `RDATA` reader - 31:0\\]
Channel 3 Received Data - (RO )"]
pub type RdataR = crate :: FieldReader < u32 > ; # [doc = "Field `RDATA` writer - 31:0\\]
Channel 3 Received Data - (RO )"]
pub type RdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Received Data - (RO )"]
# [inline (always)]
pub fn rdata (& self) -> RdataR { RdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Channel 3 Received Data - (RO )"]
# [inline (always)]
# [must_use]
pub fn rdata (& mut self) -> RdataW < Rx3Spec > { RdataW :: new (self , 0) } } # [doc = "This register contains a single SPI word received through the serial link what ever SPI word length is.\n\nYou can [`read`](crate::Reg::read) this register and get [`rx3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rx3Spec ; impl crate :: RegisterSpec for Rx3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rx3::R`](R) reader structure"]
impl crate :: Readable for Rx3Spec { } # [doc = "`write(|w| ..)` method takes [`rx3::W`](W) writer structure"]
impl crate :: Writable for Rx3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RX3 to value 0"]
impl crate :: Resettable for Rx3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XFERLEVEL (rw) register accessor: This register provides transfer levels needed while using FIFO buffer during transfer.\n\nYou can [`read`](crate::Reg::read) this register and get [`xferlevel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xferlevel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xferlevel`]
module"]
# [doc (alias = "XFERLEVEL")]
pub type Xferlevel = crate :: Reg < xferlevel :: XferlevelSpec > ; # [doc = "This register provides transfer levels needed while using FIFO buffer during transfer."]
pub mod xferlevel { # [doc = "Register `XFERLEVEL` reader"]
pub type R = crate :: R < XferlevelSpec > ; # [doc = "Register `XFERLEVEL` writer"]
pub type W = crate :: W < XferlevelSpec > ; # [doc = "Field `AEL` reader - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
pub type AelR = crate :: FieldReader ; # [doc = "Field `AEL` writer - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
pub type AelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `AFL` reader - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
pub type AflR = crate :: FieldReader ; # [doc = "Field `AFL` writer - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
pub type AflW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `WCNT` reader - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
pub type WcntR = crate :: FieldReader < u16 > ; # [doc = "Field `WCNT` writer - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
pub type WcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
# [inline (always)]
pub fn ael (& self) -> AelR { AelR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
# [inline (always)]
pub fn afl (& self) -> AflR { AflR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
# [inline (always)]
pub fn wcnt (& self) -> WcntR { WcntR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL\\[AEL\\]
must be set with n-1 - (RW )"]
# [inline (always)]
# [must_use]
pub fn ael (& mut self) -> AelW < XferlevelSpec > { AelW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL\\[AFL\\]
must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW )"]
# [inline (always)]
# [must_use]
pub fn afl (& mut self) -> AflW < XferlevelSpec > { AflW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW )"]
# [inline (always)]
# [must_use]
pub fn wcnt (& mut self) -> WcntW < XferlevelSpec > { WcntW :: new (self , 16) } } # [doc = "This register provides transfer levels needed while using FIFO buffer during transfer.\n\nYou can [`read`](crate::Reg::read) this register and get [`xferlevel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xferlevel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XferlevelSpec ; impl crate :: RegisterSpec for XferlevelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xferlevel::R`](R) reader structure"]
impl crate :: Readable for XferlevelSpec { } # [doc = "`write(|w| ..)` method takes [`xferlevel::W`](W) writer structure"]
impl crate :: Writable for XferlevelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XFERLEVEL to value 0"]
impl crate :: Resettable for XferlevelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DAFTX (rw) register accessor: This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`daftx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daftx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daftx`]
module"]
# [doc (alias = "DAFTX")]
pub type Daftx = crate :: Reg < daftx :: DaftxSpec > ; # [doc = "This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."]
pub mod daftx { # [doc = "Register `DAFTX` reader"]
pub type R = crate :: R < DaftxSpec > ; # [doc = "Register `DAFTX` writer"]
pub type W = crate :: W < DaftxSpec > ; # [doc = "Field `DAFTDATA` reader - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
pub type DaftdataR = crate :: FieldReader < u32 > ; # [doc = "Field `DAFTDATA` writer - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
pub type DaftdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
# [inline (always)]
pub fn daftdata (& self) -> DaftdataR { DaftdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW )"]
# [inline (always)]
# [must_use]
pub fn daftdata (& mut self) -> DaftdataW < DaftxSpec > { DaftdataW :: new (self , 0) } } # [doc = "This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`daftx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daftx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DaftxSpec ; impl crate :: RegisterSpec for DaftxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`daftx::R`](R) reader structure"]
impl crate :: Readable for DaftxSpec { } # [doc = "`write(|w| ..)` method takes [`daftx::W`](W) writer structure"]
impl crate :: Writable for DaftxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DAFTX to value 0"]
impl crate :: Resettable for DaftxSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DAFRX (rw) register accessor: This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`dafrx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dafrx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dafrx`]
module"]
# [doc (alias = "DAFRX")]
pub type Dafrx = crate :: Reg < dafrx :: DafrxSpec > ; # [doc = "This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."]
pub mod dafrx { # [doc = "Register `DAFRX` reader"]
pub type R = crate :: R < DafrxSpec > ; # [doc = "Register `DAFRX` writer"]
pub type W = crate :: W < DafrxSpec > ; # [doc = "Field `DAFRDATA` reader - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
pub type DafrdataR = crate :: FieldReader < u32 > ; # [doc = "Field `DAFRDATA` writer - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
pub type DafrdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
# [inline (always)]
pub fn dafrdata (& self) -> DafrdataR { DafrdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL\\[FDAA\\]
is set to \"1\" and only one of the MCSPI_CH\\[i\\]CONF\\[FFEW\\]
of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO )"]
# [inline (always)]
# [must_use]
pub fn dafrdata (& mut self) -> DafrdataW < DafrxSpec > { DafrdataW :: new (self , 0) } } # [doc = "This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled.\n\nYou can [`read`](crate::Reg::read) this register and get [`dafrx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dafrx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DafrxSpec ; impl crate :: RegisterSpec for DafrxSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dafrx::R`](R) reader structure"]
impl crate :: Readable for DafrxSpec { } # [doc = "`write(|w| ..)` method takes [`dafrx::W`](W) writer structure"]
impl crate :: Writable for DafrxSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DAFRX to value 0"]
impl crate :: Resettable for DafrxSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_I2C"]
pub struct AppI2c { _marker : PhantomData < * const () > } unsafe impl Send for AppI2c { } impl AppI2c { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_i2c :: RegisterBlock = 0x57f7_f800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_i2c :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppI2c { type Target = app_i2c :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppI2c { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppI2c") . finish () } } # [doc = "APP_I2C"]
pub mod app_i2c { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { icoar : Icoar , icimr : Icimr , icstr : Icstr , icclkl : Icclkl , icclkh : Icclkh , iccnt : Iccnt , icdrr : Icdrr , icsar : Icsar , icdxr : Icdxr , icmdr : Icmdr , icivr : Icivr , icemdr : Icemdr , icpsc : Icpsc , icpid1 : Icpid1 , icpid2 : Icpid2 , icdmac : Icdmac , i2c_reserved1 : I2cReserved1 , i2c_reserved2 : I2cReserved2 , icpfunc : Icpfunc , icpdir : Icpdir , icpdin : Icpdin , icpdout : Icpdout , icpdset : Icpdset , icpdclr : Icpdclr , icpdrv : Icpdrv , } impl RegisterBlock { # [doc = "0x00 - I2C Own Address register"]
# [inline (always)]
pub const fn icoar (& self) -> & Icoar { & self . icoar } # [doc = "0x04 - I2C Interrupt Mask/Status register"]
# [inline (always)]
pub const fn icimr (& self) -> & Icimr { & self . icimr } # [doc = "0x08 - I2C Interrupt Status register"]
# [inline (always)]
pub const fn icstr (& self) -> & Icstr { & self . icstr } # [doc = "0x0c - I2C Clock Divider Low register"]
# [inline (always)]
pub const fn icclkl (& self) -> & Icclkl { & self . icclkl } # [doc = "0x10 - I2C Clock Divider High register"]
# [inline (always)]
pub const fn icclkh (& self) -> & Icclkh { & self . icclkh } # [doc = "0x14 - I2C Data Count register"]
# [inline (always)]
pub const fn iccnt (& self) -> & Iccnt { & self . iccnt } # [doc = "0x18 - I2C Data Receive register"]
# [inline (always)]
pub const fn icdrr (& self) -> & Icdrr { & self . icdrr } # [doc = "0x1c - I2C Slave Address register"]
# [inline (always)]
pub const fn icsar (& self) -> & Icsar { & self . icsar } # [doc = "0x20 - I2C Data Transmit register"]
# [inline (always)]
pub const fn icdxr (& self) -> & Icdxr { & self . icdxr } # [doc = "0x24 - I2C Mode register"]
# [inline (always)]
pub const fn icmdr (& self) -> & Icmdr { & self . icmdr } # [doc = "0x28 - I2C Interrupt Vector register"]
# [inline (always)]
pub const fn icivr (& self) -> & Icivr { & self . icivr } # [doc = "0x2c - I2C Extended Mode register"]
# [inline (always)]
pub const fn icemdr (& self) -> & Icemdr { & self . icemdr } # [doc = "0x30 - I2C Prescaler register"]
# [inline (always)]
pub const fn icpsc (& self) -> & Icpsc { & self . icpsc } # [doc = "0x34 - I2C Peripheral ID register 1"]
# [inline (always)]
pub const fn icpid1 (& self) -> & Icpid1 { & self . icpid1 } # [doc = "0x38 - I2C Peripheral ID register 2"]
# [inline (always)]
pub const fn icpid2 (& self) -> & Icpid2 { & self . icpid2 } # [doc = "0x3c - I2C DMA Control Register"]
# [inline (always)]
pub const fn icdmac (& self) -> & Icdmac { & self . icdmac } # [doc = "0x40 - Reserved"]
# [inline (always)]
pub const fn i2c_reserved1 (& self) -> & I2cReserved1 { & self . i2c_reserved1 } # [doc = "0x44 - Reserved"]
# [inline (always)]
pub const fn i2c_reserved2 (& self) -> & I2cReserved2 { & self . i2c_reserved2 } # [doc = "0x48 - I2C Pin Function register"]
# [inline (always)]
pub const fn icpfunc (& self) -> & Icpfunc { & self . icpfunc } # [doc = "0x4c - I2C Pin Direction register"]
# [inline (always)]
pub const fn icpdir (& self) -> & Icpdir { & self . icpdir } # [doc = "0x50 - I2C Pin Data In register"]
# [inline (always)]
pub const fn icpdin (& self) -> & Icpdin { & self . icpdin } # [doc = "0x54 - I2C Pin Data Out register"]
# [inline (always)]
pub const fn icpdout (& self) -> & Icpdout { & self . icpdout } # [doc = "0x58 - I2C Pin Data Set register"]
# [inline (always)]
pub const fn icpdset (& self) -> & Icpdset { & self . icpdset } # [doc = "0x5c - I2C Pin Data Clear register"]
# [inline (always)]
pub const fn icpdclr (& self) -> & Icpdclr { & self . icpdclr } # [doc = "0x60 - I2C Pin Driver Mode Register"]
# [inline (always)]
pub const fn icpdrv (& self) -> & Icpdrv { & self . icpdrv } } # [doc = "ICOAR (rw) register accessor: I2C Own Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`icoar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icoar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icoar`]
module"]
# [doc (alias = "ICOAR")]
pub type Icoar = crate :: Reg < icoar :: IcoarSpec > ; # [doc = "I2C Own Address register"]
pub mod icoar { # [doc = "Register `ICOAR` reader"]
pub type R = crate :: R < IcoarSpec > ; # [doc = "Register `ICOAR` writer"]
pub type W = crate :: W < IcoarSpec > ; # [doc = "Field `A9_A0` reader - 9:0\\]
Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system."]
pub type A9A0R = crate :: FieldReader < u16 > ; # [doc = "Field `A9_A0` writer - 9:0\\]
Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system."]
pub type A9A0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU` reader - 31:10\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:10\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system."]
# [inline (always)]
pub fn a9_a0 (& self) -> A9A0R { A9A0R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:31 - 31:10\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system."]
# [inline (always)]
# [must_use]
pub fn a9_a0 (& mut self) -> A9A0W < IcoarSpec > { A9A0W :: new (self , 0) } # [doc = "Bits 10:31 - 31:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcoarSpec > { NuW :: new (self , 10) } } # [doc = "I2C Own Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`icoar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icoar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcoarSpec ; impl crate :: RegisterSpec for IcoarSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icoar::R`](R) reader structure"]
impl crate :: Readable for IcoarSpec { } # [doc = "`write(|w| ..)` method takes [`icoar::W`](W) writer structure"]
impl crate :: Writable for IcoarSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICOAR to value 0"]
impl crate :: Resettable for IcoarSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICIMR (rw) register accessor: I2C Interrupt Mask/Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`icimr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icimr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icimr`]
module"]
# [doc (alias = "ICIMR")]
pub type Icimr = crate :: Reg < icimr :: IcimrSpec > ; # [doc = "I2C Interrupt Mask/Status register"]
pub mod icimr { # [doc = "Register `ICIMR` reader"]
pub type R = crate :: R < IcimrSpec > ; # [doc = "Register `ICIMR` writer"]
pub type W = crate :: W < IcimrSpec > ; # [doc = "Field `AL` reader - 0:0\\]
Arbitration Lost interrupt mask bit. Setting a\"1\" to this bit unmasks the Arbitration Lost interrupt. Setting a\"0\" to this bit masks the Arbitration Lost interrupt."]
pub type AlR = crate :: BitReader ; # [doc = "Field `AL` writer - 0:0\\]
Arbitration Lost interrupt mask bit. Setting a\"1\" to this bit unmasks the Arbitration Lost interrupt. Setting a\"0\" to this bit masks the Arbitration Lost interrupt."]
pub type AlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NACK` reader - 1:1\\]
No Acknowledgement interrupt mask bit. Setting a\"1\" to this bit unmasks the No Acknowledgement interrupt. Setting a\"0\" to this bit masks the No Acknowledgement interrupt."]
pub type NackR = crate :: BitReader ; # [doc = "Field `NACK` writer - 1:1\\]
No Acknowledgement interrupt mask bit. Setting a\"1\" to this bit unmasks the No Acknowledgement interrupt. Setting a\"0\" to this bit masks the No Acknowledgement interrupt."]
pub type NackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ARDY` reader - 2:2\\]
Register access ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Register access ready interrupt. Setting a\"0\" to this bit masks the Register access ready interrupt."]
pub type ArdyR = crate :: BitReader ; # [doc = "Field `ARDY` writer - 2:2\\]
Register access ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Register access ready interrupt. Setting a\"0\" to this bit masks the Register access ready interrupt."]
pub type ArdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ICRRDY` reader - 3:3\\]
Receive Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Receive Data Ready interrupt. Setting a\"0\" to this bit masks the Receive Data Ready interrupt."]
pub type IcrrdyR = crate :: BitReader ; # [doc = "Field `ICRRDY` writer - 3:3\\]
Receive Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Receive Data Ready interrupt. Setting a\"0\" to this bit masks the Receive Data Ready interrupt."]
pub type IcrrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ICXRDY` reader - 4:4\\]
Transmit Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Transmit Data Ready interrupt. Setting a\"0\" to this bit masks the Transmit Data Ready interrupt."]
pub type IcxrdyR = crate :: BitReader ; # [doc = "Field `ICXRDY` writer - 4:4\\]
Transmit Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Transmit Data Ready interrupt. Setting a\"0\" to this bit masks the Transmit Data Ready interrupt."]
pub type IcxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SCD` reader - 5:5\\]
Stop Condition Detection mask bit. Setting a\"1\" to this bit unmasks the Stop Condition Detection interrupt. Setting a \"0\" to this bit masks the Stop Condition Detection interrupt."]
pub type ScdR = crate :: BitReader ; # [doc = "Field `SCD` writer - 5:5\\]
Stop Condition Detection mask bit. Setting a\"1\" to this bit unmasks the Stop Condition Detection interrupt. Setting a \"0\" to this bit masks the Stop Condition Detection interrupt."]
pub type ScdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AAS` reader - 6:6\\]
Address As Slave interrupt mask bit. Setting a\"1\" to this bit unmasks the Address As Slave interrupt. Setting a\"0\" to this bit masks the Address As Slave interrupt."]
pub type AasR = crate :: BitReader ; # [doc = "Field `AAS` writer - 6:6\\]
Address As Slave interrupt mask bit. Setting a\"1\" to this bit unmasks the Address As Slave interrupt. Setting a\"0\" to this bit masks the Address As Slave interrupt."]
pub type AasW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:7\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:7\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 25 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Arbitration Lost interrupt mask bit. Setting a\"1\" to this bit unmasks the Arbitration Lost interrupt. Setting a\"0\" to this bit masks the Arbitration Lost interrupt."]
# [inline (always)]
pub fn al (& self) -> AlR { AlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
No Acknowledgement interrupt mask bit. Setting a\"1\" to this bit unmasks the No Acknowledgement interrupt. Setting a\"0\" to this bit masks the No Acknowledgement interrupt."]
# [inline (always)]
pub fn nack (& self) -> NackR { NackR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Register access ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Register access ready interrupt. Setting a\"0\" to this bit masks the Register access ready interrupt."]
# [inline (always)]
pub fn ardy (& self) -> ArdyR { ArdyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Receive Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Receive Data Ready interrupt. Setting a\"0\" to this bit masks the Receive Data Ready interrupt."]
# [inline (always)]
pub fn icrrdy (& self) -> IcrrdyR { IcrrdyR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Transmit Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Transmit Data Ready interrupt. Setting a\"0\" to this bit masks the Transmit Data Ready interrupt."]
# [inline (always)]
pub fn icxrdy (& self) -> IcxrdyR { IcxrdyR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Stop Condition Detection mask bit. Setting a\"1\" to this bit unmasks the Stop Condition Detection interrupt. Setting a \"0\" to this bit masks the Stop Condition Detection interrupt."]
# [inline (always)]
pub fn scd (& self) -> ScdR { ScdR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Address As Slave interrupt mask bit. Setting a\"1\" to this bit unmasks the Address As Slave interrupt. Setting a\"0\" to this bit masks the Address As Slave interrupt."]
# [inline (always)]
pub fn aas (& self) -> AasR { AasR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:31 - 31:7\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 7) & 0x01ff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Arbitration Lost interrupt mask bit. Setting a\"1\" to this bit unmasks the Arbitration Lost interrupt. Setting a\"0\" to this bit masks the Arbitration Lost interrupt."]
# [inline (always)]
# [must_use]
pub fn al (& mut self) -> AlW < IcimrSpec > { AlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
No Acknowledgement interrupt mask bit. Setting a\"1\" to this bit unmasks the No Acknowledgement interrupt. Setting a\"0\" to this bit masks the No Acknowledgement interrupt."]
# [inline (always)]
# [must_use]
pub fn nack (& mut self) -> NackW < IcimrSpec > { NackW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Register access ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Register access ready interrupt. Setting a\"0\" to this bit masks the Register access ready interrupt."]
# [inline (always)]
# [must_use]
pub fn ardy (& mut self) -> ArdyW < IcimrSpec > { ArdyW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Receive Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Receive Data Ready interrupt. Setting a\"0\" to this bit masks the Receive Data Ready interrupt."]
# [inline (always)]
# [must_use]
pub fn icrrdy (& mut self) -> IcrrdyW < IcimrSpec > { IcrrdyW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Transmit Data Ready interrupt mask bit. Setting a\"1\" to this bit unmasks the Transmit Data Ready interrupt. Setting a\"0\" to this bit masks the Transmit Data Ready interrupt."]
# [inline (always)]
# [must_use]
pub fn icxrdy (& mut self) -> IcxrdyW < IcimrSpec > { IcxrdyW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Stop Condition Detection mask bit. Setting a\"1\" to this bit unmasks the Stop Condition Detection interrupt. Setting a \"0\" to this bit masks the Stop Condition Detection interrupt."]
# [inline (always)]
# [must_use]
pub fn scd (& mut self) -> ScdW < IcimrSpec > { ScdW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Address As Slave interrupt mask bit. Setting a\"1\" to this bit unmasks the Address As Slave interrupt. Setting a\"0\" to this bit masks the Address As Slave interrupt."]
# [inline (always)]
# [must_use]
pub fn aas (& mut self) -> AasW < IcimrSpec > { AasW :: new (self , 6) } # [doc = "Bits 7:31 - 31:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcimrSpec > { NuW :: new (self , 7) } } # [doc = "I2C Interrupt Mask/Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`icimr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icimr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcimrSpec ; impl crate :: RegisterSpec for IcimrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icimr::R`](R) reader structure"]
impl crate :: Readable for IcimrSpec { } # [doc = "`write(|w| ..)` method takes [`icimr::W`](W) writer structure"]
impl crate :: Writable for IcimrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICIMR to value 0"]
impl crate :: Resettable for IcimrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICSTR (rw) register accessor: I2C Interrupt Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`icstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icstr`]
module"]
# [doc (alias = "ICSTR")]
pub type Icstr = crate :: Reg < icstr :: IcstrSpec > ; # [doc = "I2C Interrupt Status register"]
pub mod icstr { # [doc = "Register `ICSTR` reader"]
pub type R = crate :: R < IcstrSpec > ; # [doc = "Register `ICSTR` writer"]
pub type W = crate :: W < IcstrSpec > ; # [doc = "Field `AL` reader - 0:0\\]
Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the \"master\" mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a transfer while BB (bus busy) is 1. When this is set to 1 due to arbitration lost the MST/STT/STP bits are clear the I2C becomes a slave. Write '1' or Read the ICIVR (as 001) will clear it."]
pub type AlR = crate :: BitReader ; # [doc = "Field `AL` writer - 0:0\\]
Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the \"master\" mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a transfer while BB (bus busy) is 1. When this is set to 1 due to arbitration lost the MST/STT/STP bits are clear the I2C becomes a slave. Write '1' or Read the ICIVR (as 001) will clear it."]
pub type AlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NACK` reader - 1:1\\]
No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in \"master\" mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010) will clear it."]
pub type NackR = crate :: BitReader ; # [doc = "Field `NACK` writer - 1:1\\]
No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in \"master\" mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010) will clear it."]
pub type NackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ARDY` reader - 2:2\\]
Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let it knows that the I2C registers are ready to be accessed again. When RM=0 ARDY is set when the internal data count is passed 0 if STP register bit has not been set. When RM=1 ARDY is set at each byte end. If the I2C is in FDF mode(FDF=1) ARDY is set just after Start condition. This bit is automatically cleared by hardware when writing data to ICDXR in transmit mode reading data from ICDRR in receive mode or setting STT or STP bit. Write '1' will clear it."]
pub type ArdyR = crate :: BitReader ; # [doc = "Field `ARDY` writer - 2:2\\]
Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let it knows that the I2C registers are ready to be accessed again. When RM=0 ARDY is set when the internal data count is passed 0 if STP register bit has not been set. When RM=1 ARDY is set at each byte end. If the I2C is in FDF mode(FDF=1) ARDY is set just after Start condition. This bit is automatically cleared by hardware when writing data to ICDXR in transmit mode reading data from ICDRR in receive mode or setting STT or STP bit. Write '1' will clear it."]
pub type ArdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ICRRDY` reader - 3:3\\]
Receive Data Ready interrupt flag bit. ICRRDY is set to\"1\" when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to\"0\" when the ICDRR is read. This bit can also be polled by the CPU to read the received data in the ICDRR. Write '1' or DRR Read will clear it."]
pub type IcrrdyR = crate :: BitReader ; # [doc = "Field `ICRRDY` writer - 3:3\\]
Receive Data Ready interrupt flag bit. ICRRDY is set to\"1\" when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to\"0\" when the ICDRR is read. This bit can also be polled by the CPU to read the received data in the ICDRR. Write '1' or DRR Read will clear it."]
pub type IcrrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ICXRDY` reader - 4:4\\]
Transmit Data Ready interrupt flag bit. ICXRDY is set to\"1\" is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to\"0\" when the ICDXR is written. This bit can also be polled by the CPU to write a new transmitted data into the ICDXR. Write '1' to this bit will set it and DXR Write will clear it."]
pub type IcxrdyR = crate :: BitReader ; # [doc = "Field `ICXRDY` writer - 4:4\\]
Transmit Data Ready interrupt flag bit. ICXRDY is set to\"1\" is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to\"0\" when the ICDXR is written. This bit can also be polled by the CPU to write a new transmitted data into the ICDXR. Write '1' to this bit will set it and DXR Write will clear it."]
pub type IcxrdyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SCD` reader - 5:5\\]
Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself."]
pub type ScdR = crate :: BitReader ; # [doc = "Field `SCD` writer - 5:5\\]
Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself."]
pub type ScdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 7:6\\]
Reserved"]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:6\\]
Reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AD0` reader - 8:8\\]
Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a\"start\" or\"stop\" condition is detected. - (RW )"]
pub type Ad0R = crate :: BitReader ; # [doc = "Field `AD0` writer - 8:8\\]
Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a\"start\" or\"stop\" condition is detected. - (RW )"]
pub type Ad0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AAS` reader - 9:9\\]
Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )"]
pub type AasR = crate :: BitReader ; # [doc = "Field `AAS` writer - 9:9\\]
Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )"]
pub type AasW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `XSMT` reader - 10:10\\]
Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_ is cleared when underflow has occurred. XSMT_ is set to\"1\" as a result of writing to ICDXR. In repeat mode if the I2C in master transmitter mode is holding transfer with XSMT_=0 (i.e. waiting for further action) and the STT or STP bit is set XSMT_ is set to\"1\" by hardware."]
pub type XsmtR = crate :: BitReader ; # [doc = "Field `XSMT` writer - 10:10\\]
Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_ is cleared when underflow has occurred. XSMT_ is set to\"1\" as a result of writing to ICDXR. In repeat mode if the I2C in master transmitter mode is holding transfer with XSMT_=0 (i.e. waiting for further action) and the STT or STP bit is set XSMT_ is set to\"1\" by hardware."]
pub type XsmtW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RSFULL` reader - 11:11\\]
Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR read access. RSFULL is clear when reading the ICDRR. RSFULL is set to\"1\" when the I2C has recognized an overrun. The contents of ICDRR are NOT lost in this case. In repeat mode since double buffer (ICRSR and ICDRR) behaves like a single buffer RSFULL is set to\"1\" every time the data is received. RSFULL is clear as a result of reading the ICDRR. - (RW )"]
pub type RsfullR = crate :: BitReader ; # [doc = "Field `RSFULL` writer - 11:11\\]
Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR read access. RSFULL is clear when reading the ICDRR. RSFULL is set to\"1\" when the I2C has recognized an overrun. The contents of ICDRR are NOT lost in this case. In repeat mode since double buffer (ICRSR and ICDRR) behaves like a single buffer RSFULL is set to\"1\" every time the data is received. RSFULL is clear as a result of reading the ICDRR. - (RW )"]
pub type RsfullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BB` reader - 12:12\\]
Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a\"start\" condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after reception of a\"stop\" condition. BB is kept to\"0\" regardless SCL state when the I2C is in reset (IRS_=0). If the IRS_ is set to\"1\" during transaction between other I2C devices the BB bit is set at the first falling edge of SCL or START condition. - (RW )"]
pub type BbR = crate :: BitReader ; # [doc = "Field `BB` writer - 12:12\\]
Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a\"start\" condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after reception of a\"stop\" condition. BB is kept to\"0\" regardless SCL state when the I2C is in reset (IRS_=0). If the IRS_ is set to\"1\" during transaction between other I2C devices the BB bit is set at the first falling edge of SCL or START condition. - (RW )"]
pub type BbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NACKSNT` reader - 13:13\\]
A No Acknowledge is sent due to NACKMOD is set to a\"1\". NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a\"1\" to this bit to clear it."]
pub type NacksntR = crate :: BitReader ; # [doc = "Field `NACKSNT` writer - 13:13\\]
A No Acknowledge is sent due to NACKMOD is set to a\"1\". NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a\"1\" to this bit to clear it."]
pub type NacksntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SDIR` reader - 14:14\\]
Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode (which the configuration should be master-transmitter slave-receiver) this bit is clear to '0'. Writing a\"1\" to this bit to clear it."]
pub type SdirR = crate :: BitReader ; # [doc = "Field `SDIR` writer - 14:14\\]
Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode (which the configuration should be master-transmitter slave-receiver) this bit is clear to '0'. Writing a\"1\" to this bit to clear it."]
pub type SdirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 31:15\\]
Reserved"]
pub type Nu2R = crate :: FieldReader < u32 > ; # [doc = "Field `NU2` writer - 31:15\\]
Reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 17 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the \"master\" mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a transfer while BB (bus busy) is 1. When this is set to 1 due to arbitration lost the MST/STT/STP bits are clear the I2C becomes a slave. Write '1' or Read the ICIVR (as 001) will clear it."]
# [inline (always)]
pub fn al (& self) -> AlR { AlR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in \"master\" mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010) will clear it."]
# [inline (always)]
pub fn nack (& self) -> NackR { NackR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let it knows that the I2C registers are ready to be accessed again. When RM=0 ARDY is set when the internal data count is passed 0 if STP register bit has not been set. When RM=1 ARDY is set at each byte end. If the I2C is in FDF mode(FDF=1) ARDY is set just after Start condition. This bit is automatically cleared by hardware when writing data to ICDXR in transmit mode reading data from ICDRR in receive mode or setting STT or STP bit. Write '1' will clear it."]
# [inline (always)]
pub fn ardy (& self) -> ArdyR { ArdyR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Receive Data Ready interrupt flag bit. ICRRDY is set to\"1\" when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to\"0\" when the ICDRR is read. This bit can also be polled by the CPU to read the received data in the ICDRR. Write '1' or DRR Read will clear it."]
# [inline (always)]
pub fn icrrdy (& self) -> IcrrdyR { IcrrdyR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Transmit Data Ready interrupt flag bit. ICXRDY is set to\"1\" is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to\"0\" when the ICDXR is written. This bit can also be polled by the CPU to write a new transmitted data into the ICDXR. Write '1' to this bit will set it and DXR Write will clear it."]
# [inline (always)]
pub fn icxrdy (& self) -> IcxrdyR { IcxrdyR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself."]
# [inline (always)]
pub fn scd (& self) -> ScdR { ScdR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - 7:6\\]
Reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - 8:8\\]
Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a\"start\" or\"stop\" condition is detected. - (RW )"]
# [inline (always)]
pub fn ad0 (& self) -> Ad0R { Ad0R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )"]
# [inline (always)]
pub fn aas (& self) -> AasR { AasR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_ is cleared when underflow has occurred. XSMT_ is set to\"1\" as a result of writing to ICDXR. In repeat mode if the I2C in master transmitter mode is holding transfer with XSMT_=0 (i.e. waiting for further action) and the STT or STP bit is set XSMT_ is set to\"1\" by hardware."]
# [inline (always)]
pub fn xsmt (& self) -> XsmtR { XsmtR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR read access. RSFULL is clear when reading the ICDRR. RSFULL is set to\"1\" when the I2C has recognized an overrun. The contents of ICDRR are NOT lost in this case. In repeat mode since double buffer (ICRSR and ICDRR) behaves like a single buffer RSFULL is set to\"1\" every time the data is received. RSFULL is clear as a result of reading the ICDRR. - (RW )"]
# [inline (always)]
pub fn rsfull (& self) -> RsfullR { RsfullR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a\"start\" condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after reception of a\"stop\" condition. BB is kept to\"0\" regardless SCL state when the I2C is in reset (IRS_=0). If the IRS_ is set to\"1\" during transaction between other I2C devices the BB bit is set at the first falling edge of SCL or START condition. - (RW )"]
# [inline (always)]
pub fn bb (& self) -> BbR { BbR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
A No Acknowledge is sent due to NACKMOD is set to a\"1\". NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a\"1\" to this bit to clear it."]
# [inline (always)]
pub fn nacksnt (& self) -> NacksntR { NacksntR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode (which the configuration should be master-transmitter slave-receiver) this bit is clear to '0'. Writing a\"1\" to this bit to clear it."]
# [inline (always)]
pub fn sdir (& self) -> SdirR { SdirR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:31 - 31:15\\]
Reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new ((self . bits >> 15) & 0x0001_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the \"master\" mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a transfer while BB (bus busy) is 1. When this is set to 1 due to arbitration lost the MST/STT/STP bits are clear the I2C becomes a slave. Write '1' or Read the ICIVR (as 001) will clear it."]
# [inline (always)]
# [must_use]
pub fn al (& mut self) -> AlW < IcstrSpec > { AlW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in \"master\" mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010) will clear it."]
# [inline (always)]
# [must_use]
pub fn nack (& mut self) -> NackW < IcstrSpec > { NackW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let it knows that the I2C registers are ready to be accessed again. When RM=0 ARDY is set when the internal data count is passed 0 if STP register bit has not been set. When RM=1 ARDY is set at each byte end. If the I2C is in FDF mode(FDF=1) ARDY is set just after Start condition. This bit is automatically cleared by hardware when writing data to ICDXR in transmit mode reading data from ICDRR in receive mode or setting STT or STP bit. Write '1' will clear it."]
# [inline (always)]
# [must_use]
pub fn ardy (& mut self) -> ArdyW < IcstrSpec > { ArdyW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Receive Data Ready interrupt flag bit. ICRRDY is set to\"1\" when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to\"0\" when the ICDRR is read. This bit can also be polled by the CPU to read the received data in the ICDRR. Write '1' or DRR Read will clear it."]
# [inline (always)]
# [must_use]
pub fn icrrdy (& mut self) -> IcrrdyW < IcstrSpec > { IcrrdyW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Transmit Data Ready interrupt flag bit. ICXRDY is set to\"1\" is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to\"0\" when the ICDXR is written. This bit can also be polled by the CPU to write a new transmitted data into the ICDXR. Write '1' to this bit will set it and DXR Write will clear it."]
# [inline (always)]
# [must_use]
pub fn icxrdy (& mut self) -> IcxrdyW < IcstrSpec > { IcxrdyW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself."]
# [inline (always)]
# [must_use]
pub fn scd (& mut self) -> ScdW < IcstrSpec > { ScdW :: new (self , 5) } # [doc = "Bits 6:7 - 7:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IcstrSpec > { Nu1W :: new (self , 6) } # [doc = "Bit 8 - 8:8\\]
Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a\"start\" or\"stop\" condition is detected. - (RW )"]
# [inline (always)]
# [must_use]
pub fn ad0 (& mut self) -> Ad0W < IcstrSpec > { Ad0W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )"]
# [inline (always)]
# [must_use]
pub fn aas (& mut self) -> AasW < IcstrSpec > { AasW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_ is cleared when underflow has occurred. XSMT_ is set to\"1\" as a result of writing to ICDXR. In repeat mode if the I2C in master transmitter mode is holding transfer with XSMT_=0 (i.e. waiting for further action) and the STT or STP bit is set XSMT_ is set to\"1\" by hardware."]
# [inline (always)]
# [must_use]
pub fn xsmt (& mut self) -> XsmtW < IcstrSpec > { XsmtW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR read access. RSFULL is clear when reading the ICDRR. RSFULL is set to\"1\" when the I2C has recognized an overrun. The contents of ICDRR are NOT lost in this case. In repeat mode since double buffer (ICRSR and ICDRR) behaves like a single buffer RSFULL is set to\"1\" every time the data is received. RSFULL is clear as a result of reading the ICDRR. - (RW )"]
# [inline (always)]
# [must_use]
pub fn rsfull (& mut self) -> RsfullW < IcstrSpec > { RsfullW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a\"start\" condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after reception of a\"stop\" condition. BB is kept to\"0\" regardless SCL state when the I2C is in reset (IRS_=0). If the IRS_ is set to\"1\" during transaction between other I2C devices the BB bit is set at the first falling edge of SCL or START condition. - (RW )"]
# [inline (always)]
# [must_use]
pub fn bb (& mut self) -> BbW < IcstrSpec > { BbW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
A No Acknowledge is sent due to NACKMOD is set to a\"1\". NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a\"1\" to this bit to clear it."]
# [inline (always)]
# [must_use]
pub fn nacksnt (& mut self) -> NacksntW < IcstrSpec > { NacksntW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode (which the configuration should be master-transmitter slave-receiver) this bit is clear to '0'. Writing a\"1\" to this bit to clear it."]
# [inline (always)]
# [must_use]
pub fn sdir (& mut self) -> SdirW < IcstrSpec > { SdirW :: new (self , 14) } # [doc = "Bits 15:31 - 31:15\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < IcstrSpec > { Nu2W :: new (self , 15) } } # [doc = "I2C Interrupt Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`icstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcstrSpec ; impl crate :: RegisterSpec for IcstrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icstr::R`](R) reader structure"]
impl crate :: Readable for IcstrSpec { } # [doc = "`write(|w| ..)` method takes [`icstr::W`](W) writer structure"]
impl crate :: Writable for IcstrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICSTR to value 0"]
impl crate :: Resettable for IcstrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICCLKL (rw) register accessor: I2C Clock Divider Low register\n\nYou can [`read`](crate::Reg::read) this register and get [`icclkl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icclkl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icclkl`]
module"]
# [doc (alias = "ICCLKL")]
pub type Icclkl = crate :: Reg < icclkl :: IcclklSpec > ; # [doc = "I2C Clock Divider Low register"]
pub mod icclkl { # [doc = "Register `ICCLKL` reader"]
pub type R = crate :: R < IcclklSpec > ; # [doc = "Register `ICCLKL` writer"]
pub type W = crate :: W < IcclklSpec > ; # [doc = "Field `ICCL15_ICCL0` reader - 15:0\\]
Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
pub type Iccl15Iccl0R = crate :: FieldReader < u16 > ; # [doc = "Field `ICCL15_ICCL0` writer - 15:0\\]
Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
pub type Iccl15Iccl0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - 31:16\\]
Reserved"]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:16\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
# [inline (always)]
pub fn iccl15_iccl0 (& self) -> Iccl15Iccl0R { Iccl15Iccl0R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
# [inline (always)]
# [must_use]
pub fn iccl15_iccl0 (& mut self) -> Iccl15Iccl0W < IcclklSpec > { Iccl15Iccl0W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcclklSpec > { NuW :: new (self , 16) } } # [doc = "I2C Clock Divider Low register\n\nYou can [`read`](crate::Reg::read) this register and get [`icclkl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icclkl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcclklSpec ; impl crate :: RegisterSpec for IcclklSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icclkl::R`](R) reader structure"]
impl crate :: Readable for IcclklSpec { } # [doc = "`write(|w| ..)` method takes [`icclkl::W`](W) writer structure"]
impl crate :: Writable for IcclklSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICCLKL to value 0"]
impl crate :: Resettable for IcclklSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICCLKH (rw) register accessor: I2C Clock Divider High register\n\nYou can [`read`](crate::Reg::read) this register and get [`icclkh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icclkh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icclkh`]
module"]
# [doc (alias = "ICCLKH")]
pub type Icclkh = crate :: Reg < icclkh :: IcclkhSpec > ; # [doc = "I2C Clock Divider High register"]
pub mod icclkh { # [doc = "Register `ICCLKH` reader"]
pub type R = crate :: R < IcclkhSpec > ; # [doc = "Register `ICCLKH` writer"]
pub type W = crate :: W < IcclkhSpec > ; # [doc = "Field `ICCH15_ICCLH0` reader - 15:0\\]
High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
pub type Icch15Icclh0R = crate :: FieldReader < u16 > ; # [doc = "Field `ICCH15_ICCLH0` writer - 15:0\\]
High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
pub type Icch15Icclh0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - 31:16\\]
Reserved"]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:16\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
# [inline (always)]
pub fn icch15_icclh0 (& self) -> Icch15Icclh0R { Icch15Icclh0R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."]
# [inline (always)]
# [must_use]
pub fn icch15_icclh0 (& mut self) -> Icch15Icclh0W < IcclkhSpec > { Icch15Icclh0W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcclkhSpec > { NuW :: new (self , 16) } } # [doc = "I2C Clock Divider High register\n\nYou can [`read`](crate::Reg::read) this register and get [`icclkh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icclkh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcclkhSpec ; impl crate :: RegisterSpec for IcclkhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icclkh::R`](R) reader structure"]
impl crate :: Readable for IcclkhSpec { } # [doc = "`write(|w| ..)` method takes [`icclkh::W`](W) writer structure"]
impl crate :: Writable for IcclkhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICCLKH to value 0"]
impl crate :: Resettable for IcclkhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICCNT (rw) register accessor: I2C Data Count register\n\nYou can [`read`](crate::Reg::read) this register and get [`iccnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iccnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iccnt`]
module"]
# [doc (alias = "ICCNT")]
pub type Iccnt = crate :: Reg < iccnt :: IccntSpec > ; # [doc = "I2C Data Count register"]
pub mod iccnt { # [doc = "Register `ICCNT` reader"]
pub type R = crate :: R < IccntSpec > ; # [doc = "Register `ICCNT` writer"]
pub type W = crate :: W < IccntSpec > ; # [doc = "Field `ICDC15_ICDC0` reader - 15:0\\]
Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: :::::::::::::::::::::::::::::::::::::::::::: ICCNT=0FFFFh data count is 65535 ICCNT=0data counter is 65536 Note that ICCNT is a don\"t care when RM is set to 1."]
pub type Icdc15Icdc0R = crate :: FieldReader < u16 > ; # [doc = "Field `ICDC15_ICDC0` writer - 15:0\\]
Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: :::::::::::::::::::::::::::::::::::::::::::: ICCNT=0FFFFh data count is 65535 ICCNT=0data counter is 65536 Note that ICCNT is a don\"t care when RM is set to 1."]
pub type Icdc15Icdc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `NU` reader - 31:16\\]
Reserved"]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:16\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: :::::::::::::::::::::::::::::::::::::::::::: ICCNT=0FFFFh data count is 65535 ICCNT=0data counter is 65536 Note that ICCNT is a don\"t care when RM is set to 1."]
# [inline (always)]
pub fn icdc15_icdc0 (& self) -> Icdc15Icdc0R { Icdc15Icdc0R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: :::::::::::::::::::::::::::::::::::::::::::: ICCNT=0FFFFh data count is 65535 ICCNT=0data counter is 65536 Note that ICCNT is a don\"t care when RM is set to 1."]
# [inline (always)]
# [must_use]
pub fn icdc15_icdc0 (& mut self) -> Icdc15Icdc0W < IccntSpec > { Icdc15Icdc0W :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IccntSpec > { NuW :: new (self , 16) } } # [doc = "I2C Data Count register\n\nYou can [`read`](crate::Reg::read) this register and get [`iccnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iccnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IccntSpec ; impl crate :: RegisterSpec for IccntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`iccnt::R`](R) reader structure"]
impl crate :: Readable for IccntSpec { } # [doc = "`write(|w| ..)` method takes [`iccnt::W`](W) writer structure"]
impl crate :: Writable for IccntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICCNT to value 0"]
impl crate :: Resettable for IccntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICDRR (rw) register accessor: I2C Data Receive register\n\nYou can [`read`](crate::Reg::read) this register and get [`icdrr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icdrr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icdrr`]
module"]
# [doc (alias = "ICDRR")]
pub type Icdrr = crate :: Reg < icdrr :: IcdrrSpec > ; # [doc = "I2C Data Receive register"]
pub mod icdrr { # [doc = "Register `ICDRR` reader"]
pub type R = crate :: R < IcdrrSpec > ; # [doc = "Register `ICDRR` writer"]
pub type W = crate :: W < IcdrrSpec > ; # [doc = "Field `D7_D0` reader - 7:0\\]
Receive data"]
pub type D7D0R = crate :: FieldReader ; # [doc = "Field `D7_D0` writer - 7:0\\]
Receive data"]
pub type D7D0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU` reader - 31:8\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:8\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Receive data"]
# [inline (always)]
pub fn d7_d0 (& self) -> D7D0R { D7D0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Receive data"]
# [inline (always)]
# [must_use]
pub fn d7_d0 (& mut self) -> D7D0W < IcdrrSpec > { D7D0W :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcdrrSpec > { NuW :: new (self , 8) } } # [doc = "I2C Data Receive register\n\nYou can [`read`](crate::Reg::read) this register and get [`icdrr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icdrr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcdrrSpec ; impl crate :: RegisterSpec for IcdrrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icdrr::R`](R) reader structure"]
impl crate :: Readable for IcdrrSpec { } # [doc = "`write(|w| ..)` method takes [`icdrr::W`](W) writer structure"]
impl crate :: Writable for IcdrrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICDRR to value 0"]
impl crate :: Resettable for IcdrrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICSAR (rw) register accessor: I2C Slave Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`icsar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icsar`]
module"]
# [doc (alias = "ICSAR")]
pub type Icsar = crate :: Reg < icsar :: IcsarSpec > ; # [doc = "I2C Slave Address register"]
pub mod icsar { # [doc = "Register `ICSAR` reader"]
pub type R = crate :: R < IcsarSpec > ; # [doc = "Register `ICSAR` writer"]
pub type W = crate :: W < IcsarSpec > ; # [doc = "Field `A9_A0` reader - 9:0\\]
Slave address. Use in both 7- and 10-bit address mode."]
pub type A9A0R = crate :: FieldReader < u16 > ; # [doc = "Field `A9_A0` writer - 9:0\\]
Slave address. Use in both 7- and 10-bit address mode."]
pub type A9A0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `NU` reader - 31:10\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:10\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 22 , u32 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
Slave address. Use in both 7- and 10-bit address mode."]
# [inline (always)]
pub fn a9_a0 (& self) -> A9A0R { A9A0R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:31 - 31:10\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 10) & 0x003f_ffff) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
Slave address. Use in both 7- and 10-bit address mode."]
# [inline (always)]
# [must_use]
pub fn a9_a0 (& mut self) -> A9A0W < IcsarSpec > { A9A0W :: new (self , 0) } # [doc = "Bits 10:31 - 31:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcsarSpec > { NuW :: new (self , 10) } } # [doc = "I2C Slave Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`icsar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcsarSpec ; impl crate :: RegisterSpec for IcsarSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icsar::R`](R) reader structure"]
impl crate :: Readable for IcsarSpec { } # [doc = "`write(|w| ..)` method takes [`icsar::W`](W) writer structure"]
impl crate :: Writable for IcsarSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICSAR to value 0"]
impl crate :: Resettable for IcsarSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICDXR (rw) register accessor: I2C Data Transmit register\n\nYou can [`read`](crate::Reg::read) this register and get [`icdxr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icdxr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icdxr`]
module"]
# [doc (alias = "ICDXR")]
pub type Icdxr = crate :: Reg < icdxr :: IcdxrSpec > ; # [doc = "I2C Data Transmit register"]
pub mod icdxr { # [doc = "Register `ICDXR` reader"]
pub type R = crate :: R < IcdxrSpec > ; # [doc = "Register `ICDXR` writer"]
pub type W = crate :: W < IcdxrSpec > ; # [doc = "Field `D7_D0` reader - 7:0\\]
Transmit data"]
pub type D7D0R = crate :: FieldReader ; # [doc = "Field `D7_D0` writer - 7:0\\]
Transmit data"]
pub type D7D0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU` reader - 31:8\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:8\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Transmit data"]
# [inline (always)]
pub fn d7_d0 (& self) -> D7D0R { D7D0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Transmit data"]
# [inline (always)]
# [must_use]
pub fn d7_d0 (& mut self) -> D7D0W < IcdxrSpec > { D7D0W :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcdxrSpec > { NuW :: new (self , 8) } } # [doc = "I2C Data Transmit register\n\nYou can [`read`](crate::Reg::read) this register and get [`icdxr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icdxr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcdxrSpec ; impl crate :: RegisterSpec for IcdxrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icdxr::R`](R) reader structure"]
impl crate :: Readable for IcdxrSpec { } # [doc = "`write(|w| ..)` method takes [`icdxr::W`](W) writer structure"]
impl crate :: Writable for IcdxrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICDXR to value 0"]
impl crate :: Resettable for IcdxrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICMDR (rw) register accessor: I2C Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`icmdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icmdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icmdr`]
module"]
# [doc (alias = "ICMDR")]
pub type Icmdr = crate :: Reg < icmdr :: IcmdrSpec > ; # [doc = "I2C Mode register"]
pub mod icmdr { # [doc = "Register `ICMDR` reader"]
pub type R = crate :: R < IcmdrSpec > ; # [doc = "Register `ICMDR` writer"]
pub type W = crate :: W < IcmdrSpec > ; # [doc = "Field `BC2_BC1_BC0` reader - 2:0\\]
Bit Count : Bit Count 2, Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted. __________________________________________ BC2_BC1_BC0__Bits/byte in FDF__Bits/byte w/ ACK _0___0___1_____NA (reserved)____ NA (reserved) _0___1___0________2______________3_______ _0___1___1________3______________4_______ _1___0___0________4______________5_______ _1___0___1________5______________6_______ _1___1___0________6______________7_______ _1___1___1________7______________8_______ _0___0___0________8______________9_______ __________________________________________"]
pub type Bc2Bc1Bc0R = crate :: FieldReader ; # [doc = "Field `BC2_BC1_BC0` writer - 2:0\\]
Bit Count : Bit Count 2, Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted. __________________________________________ BC2_BC1_BC0__Bits/byte in FDF__Bits/byte w/ ACK _0___0___1_____NA (reserved)____ NA (reserved) _0___1___0________2______________3_______ _0___1___1________3______________4_______ _1___0___0________4______________5_______ _1___0___1________5______________6_______ _1___1___0________6______________7_______ _1___1___1________7______________8_______ _0___0___0________8______________9_______ __________________________________________"]
pub type Bc2Bc1Bc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `FDF` reader - 3:3\\]
Free Data Format. This bit can be set to\"1\" by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode _0______1_____0____Master receive in non FDF mode _0______1_____1____Master transmit in non FDF mode _1______0_____0____Slave receiver in FDF mode _1______0_____1____Slave transmitter in FDF mode _1______1_____0____Master receiver in FDF mode _1______1_____1____Master transmitter in FDF mode ______________________________________________"]
pub type FdfR = crate :: BitReader ; # [doc = "Field `FDF` writer - 3:3\\]
Free Data Format. This bit can be set to\"1\" by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode _0______1_____0____Master receive in non FDF mode _0______1_____1____Master transmit in non FDF mode _1______0_____0____Slave receiver in FDF mode _1______0_____1____Slave transmitter in FDF mode _1______1_____0____Master receiver in FDF mode _1______1_____1____Master transmitter in FDF mode ______________________________________________"]
pub type FdfW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STB` reader - 4:4\\]
Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends \"00000001\"� regardless ICSAR value. Refer to the Philip I2C spec for more details."]
pub type StbR = crate :: BitReader ; # [doc = "Field `STB` writer - 4:4\\]
Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends \"00000001\"� regardless ICSAR value. Refer to the Philip I2C spec for more details."]
pub type StbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IRS` reader - 5:5\\]
I2C Reset Not. This can be set to a\"0\" by the CPU to put the I2C in reset or to a\"1\" to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during a transfer it can cause the I2C bus hang (SDA and SCL are tri-stated)."]
pub type IrsR = crate :: BitReader ; # [doc = "Field `IRS` writer - 5:5\\]
I2C Reset Not. This can be set to a\"0\" by the CPU to put the I2C in reset or to a\"1\" to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during a transfer it can cause the I2C bus hang (SDA and SCL are tri-stated)."]
pub type IrsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DLB` reader - 6:6\\]
Digital Loop Back (in master transmit mode only). This bit is set to a\"1\" by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via an internal path. The address of the ICOAR is output on SDA."]
pub type DlbR = crate :: BitReader ; # [doc = "Field `DLB` writer - 6:6\\]
Digital Loop Back (in master transmit mode only). This bit is set to a\"1\" by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via an internal path. The address of the ICOAR is output on SDA."]
pub type DlbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RM` reader - 7:7\\]
Repeat Mode. This bit is set to a\"1\" by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to\"1\" regardless of ICCNT value. This bit is don\"t care if the I2C is configured in slave mode. _________________________________________________________ RM___STT___STP___Conditions_____Bus Activities_______Mode _0_____0_____0_______Idle___________None___________NA _0_____0_____1_______Stop____________P____________NA _0_____1_____0_____(Re)Start_______S-A-D..(n)..D____Repeat n _0_____1_____1_____(Re)Start-Stop___S-A-D..(n)..D-P__Repeat n _1_____0_____0_______Idle___________none___________NA _1_____0_____1_______Stop____________P ___________NA _1_____1_____0_____(Re)Start_______S-A-D-D-D.._____Continuous _1_____1_____1_____Reserved________None___________NA _________________________________________________________"]
pub type RmR = crate :: BitReader ; # [doc = "Field `RM` writer - 7:7\\]
Repeat Mode. This bit is set to a\"1\" by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to\"1\" regardless of ICCNT value. This bit is don\"t care if the I2C is configured in slave mode. _________________________________________________________ RM___STT___STP___Conditions_____Bus Activities_______Mode _0_____0_____0_______Idle___________None___________NA _0_____0_____1_______Stop____________P____________NA _0_____1_____0_____(Re)Start_______S-A-D..(n)..D____Repeat n _0_____1_____1_____(Re)Start-Stop___S-A-D..(n)..D-P__Repeat n _1_____0_____0_______Idle___________none___________NA _1_____0_____1_______Stop____________P ___________NA _1_____1_____0_____(Re)Start_______S-A-D-D-D.._____Continuous _1_____1_____1_____Reserved________None___________NA _________________________________________________________"]
pub type RmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `XA` reader - 8:8\\]
Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode."]
pub type XaR = crate :: BitReader ; # [doc = "Field `XA` writer - 8:8\\]
Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode."]
pub type XaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRX` reader - 9:9\\]
Transmitter. TRX=0: The I 2 C is in the\"receiver\" mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the\"transmitter\" mode and the data in ICDXR is shifted out on data line SDA. The operating modes (not in FDF mode) are defined as follows. In FDF mode TRX must be configured even if the I2C is in slave mode because there is no address/direction byte in FDF mode. ______________________________ MST___TRX___Operating Modes _0______x_____\"slave receiver\" _0______x_____\"slave transmitter\" _1______0_____\"master receiver\" _1______1_____\"master transmitter\" ______________________________"]
pub type TrxR = crate :: BitReader ; # [doc = "Field `TRX` writer - 9:9\\]
Transmitter. TRX=0: The I 2 C is in the\"receiver\" mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the\"transmitter\" mode and the data in ICDXR is shifted out on data line SDA. The operating modes (not in FDF mode) are defined as follows. In FDF mode TRX must be configured even if the I2C is in slave mode because there is no address/direction byte in FDF mode. ______________________________ MST___TRX___Operating Modes _0______x_____\"slave receiver\" _0______x_____\"slave transmitter\" _1______0_____\"master receiver\" _1______1_____\"master transmitter\" ______________________________"]
pub type TrxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MST` reader - 10:10\\]
Master. MST=0: The I 2 C peripheral is in the\"slave\" mode and clock is received from the\"master\" device. MST=1: The I 2 C peripheral is in the\"master\" mode and it generates the clock. This bit is clear when the transfer completed."]
pub type MstR = crate :: BitReader ; # [doc = "Field `MST` writer - 10:10\\]
Master. MST=0: The I 2 C peripheral is in the\"slave\" mode and clock is received from the\"master\" device. MST=1: The I 2 C peripheral is in the\"master\" mode and it generates the clock. This bit is clear when the transfer completed."]
pub type MstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STP` reader - 11:11\\]
Stop Condition (Master mode only). This bit can be set to a\"1\" by the CPU to generate a Stop condition. It is reset to \"0\" by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when the I2C is in non-repeat mode(RM=0)."]
pub type StpR = crate :: BitReader ; # [doc = "Field `STP` writer - 11:11\\]
Stop Condition (Master mode only). This bit can be set to a\"1\" by the CPU to generate a Stop condition. It is reset to \"0\" by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when the I2C is in non-repeat mode(RM=0)."]
pub type StpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU1` reader - 12:12\\]
Reserved for IDLEEN (IDLE Enable on 5509). - (RW )"]
pub type Nu1R = crate :: BitReader ; # [doc = "Field `NU1` writer - 12:12\\]
Reserved for IDLEEN (IDLE Enable on 5509). - (RW )"]
pub type Nu1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STT` reader - 13:13\\]
Start Condition (Master only mode). This bit can be set to a\"1\" by the CPU to generate a Start condition. In master mode when setting Start to\"1\" generates a Start condition. It is reset to \"0\" by the hardware after the Start condition has been generated. The Start/Stop bits can be configured to generate different transfer formats. Note that the STT and STP can be used to terminate the repeat mode. ____________________________________________________ STT___STP____Conditions_______________Bus Activities _1_____0________Start___________________S-A-D _0_____1________Stop_____________________P _1_____1________Start-Stop (ICCNT= n)______S-A-D..(n)..D-P _1_____0________Start (ICCNT= n)__________S-A-D..(n)..D ____________________________________________________"]
pub type SttR = crate :: BitReader ; # [doc = "Field `STT` writer - 13:13\\]
Start Condition (Master only mode). This bit can be set to a\"1\" by the CPU to generate a Start condition. In master mode when setting Start to\"1\" generates a Start condition. It is reset to \"0\" by the hardware after the Start condition has been generated. The Start/Stop bits can be configured to generate different transfer formats. Note that the STT and STP can be used to terminate the repeat mode. ____________________________________________________ STT___STP____Conditions_______________Bus Activities _1_____0________Start___________________S-A-D _0_____1________Stop_____________________P _1_____1________Start-Stop (ICCNT= n)______S-A-D..(n)..D-P _1_____0________Start (ICCNT= n)__________S-A-D..(n)..D ____________________________________________________"]
pub type SttW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FREE` reader - 14:14\\]
Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL is high I2C waits until SCL becomes low and then stops. If the I2C is a slave it will stop when the transmission/receiving completes. FREE=1: The I2C runs free."]
pub type FreeR = crate :: BitReader ; # [doc = "Field `FREE` writer - 14:14\\]
Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL is high I2C waits until SCL becomes low and then stops. If the I2C is a slave it will stop when the transmission/receiving completes. FREE=1: The I2C runs free."]
pub type FreeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NACKMOD` reader - 15:15\\]
No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count counter decrements to zero the I2C sends a NACK. The master receiver I2C finishes a transfer when it sends a NACK. The I2C ignores ICCNT when NACKMOD is '1'. The NACKMOD bit should be set before the rising edge of the last data bit (bit 8) if a NACK must be sent and this bit is cleared once a NACK has been sent. NACKMOD=0 the I2C sends an ACK to the transmitter during the acknowledge cycle. NACKMOD=1 the I2C sends a NACK to the transmitter during the acknowledge cycle."]
pub type NackmodR = crate :: BitReader ; # [doc = "Field `NACKMOD` writer - 15:15\\]
No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count counter decrements to zero the I2C sends a NACK. The master receiver I2C finishes a transfer when it sends a NACK. The I2C ignores ICCNT when NACKMOD is '1'. The NACKMOD bit should be set before the rising edge of the last data bit (bit 8) if a NACK must be sent and this bit is cleared once a NACK has been sent. NACKMOD=0 the I2C sends an ACK to the transmitter during the acknowledge cycle. NACKMOD=1 the I2C sends a NACK to the transmitter during the acknowledge cycle."]
pub type NackmodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU2` reader - 31:16\\]
Reserved"]
pub type Nu2R = crate :: FieldReader < u16 > ; # [doc = "Field `NU2` writer - 31:16\\]
Reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Bit Count : Bit Count 2, Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted. __________________________________________ BC2_BC1_BC0__Bits/byte in FDF__Bits/byte w/ ACK _0___0___1_____NA (reserved)____ NA (reserved) _0___1___0________2______________3_______ _0___1___1________3______________4_______ _1___0___0________4______________5_______ _1___0___1________5______________6_______ _1___1___0________6______________7_______ _1___1___1________7______________8_______ _0___0___0________8______________9_______ __________________________________________"]
# [inline (always)]
pub fn bc2_bc1_bc0 (& self) -> Bc2Bc1Bc0R { Bc2Bc1Bc0R :: new ((self . bits & 7) as u8) } # [doc = "Bit 3 - 3:3\\]
Free Data Format. This bit can be set to\"1\" by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode _0______1_____0____Master receive in non FDF mode _0______1_____1____Master transmit in non FDF mode _1______0_____0____Slave receiver in FDF mode _1______0_____1____Slave transmitter in FDF mode _1______1_____0____Master receiver in FDF mode _1______1_____1____Master transmitter in FDF mode ______________________________________________"]
# [inline (always)]
pub fn fdf (& self) -> FdfR { FdfR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends \"00000001\"� regardless ICSAR value. Refer to the Philip I2C spec for more details."]
# [inline (always)]
pub fn stb (& self) -> StbR { StbR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
I2C Reset Not. This can be set to a\"0\" by the CPU to put the I2C in reset or to a\"1\" to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during a transfer it can cause the I2C bus hang (SDA and SCL are tri-stated)."]
# [inline (always)]
pub fn irs (& self) -> IrsR { IrsR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Digital Loop Back (in master transmit mode only). This bit is set to a\"1\" by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via an internal path. The address of the ICOAR is output on SDA."]
# [inline (always)]
pub fn dlb (& self) -> DlbR { DlbR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Repeat Mode. This bit is set to a\"1\" by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to\"1\" regardless of ICCNT value. This bit is don\"t care if the I2C is configured in slave mode. _________________________________________________________ RM___STT___STP___Conditions_____Bus Activities_______Mode _0_____0_____0_______Idle___________None___________NA _0_____0_____1_______Stop____________P____________NA _0_____1_____0_____(Re)Start_______S-A-D..(n)..D____Repeat n _0_____1_____1_____(Re)Start-Stop___S-A-D..(n)..D-P__Repeat n _1_____0_____0_______Idle___________none___________NA _1_____0_____1_______Stop____________P ___________NA _1_____1_____0_____(Re)Start_______S-A-D-D-D.._____Continuous _1_____1_____1_____Reserved________None___________NA _________________________________________________________"]
# [inline (always)]
pub fn rm (& self) -> RmR { RmR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode."]
# [inline (always)]
pub fn xa (& self) -> XaR { XaR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Transmitter. TRX=0: The I 2 C is in the\"receiver\" mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the\"transmitter\" mode and the data in ICDXR is shifted out on data line SDA. The operating modes (not in FDF mode) are defined as follows. In FDF mode TRX must be configured even if the I2C is in slave mode because there is no address/direction byte in FDF mode. ______________________________ MST___TRX___Operating Modes _0______x_____\"slave receiver\" _0______x_____\"slave transmitter\" _1______0_____\"master receiver\" _1______1_____\"master transmitter\" ______________________________"]
# [inline (always)]
pub fn trx (& self) -> TrxR { TrxR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Master. MST=0: The I 2 C peripheral is in the\"slave\" mode and clock is received from the\"master\" device. MST=1: The I 2 C peripheral is in the\"master\" mode and it generates the clock. This bit is clear when the transfer completed."]
# [inline (always)]
pub fn mst (& self) -> MstR { MstR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Stop Condition (Master mode only). This bit can be set to a\"1\" by the CPU to generate a Stop condition. It is reset to \"0\" by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when the I2C is in non-repeat mode(RM=0)."]
# [inline (always)]
pub fn stp (& self) -> StpR { StpR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Reserved for IDLEEN (IDLE Enable on 5509). - (RW )"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Start Condition (Master only mode). This bit can be set to a\"1\" by the CPU to generate a Start condition. In master mode when setting Start to\"1\" generates a Start condition. It is reset to \"0\" by the hardware after the Start condition has been generated. The Start/Stop bits can be configured to generate different transfer formats. Note that the STT and STP can be used to terminate the repeat mode. ____________________________________________________ STT___STP____Conditions_______________Bus Activities _1_____0________Start___________________S-A-D _0_____1________Stop_____________________P _1_____1________Start-Stop (ICCNT= n)______S-A-D..(n)..D-P _1_____0________Start (ICCNT= n)__________S-A-D..(n)..D ____________________________________________________"]
# [inline (always)]
pub fn stt (& self) -> SttR { SttR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL is high I2C waits until SCL becomes low and then stops. If the I2C is a slave it will stop when the transmission/receiving completes. FREE=1: The I2C runs free."]
# [inline (always)]
pub fn free (& self) -> FreeR { FreeR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count counter decrements to zero the I2C sends a NACK. The master receiver I2C finishes a transfer when it sends a NACK. The I2C ignores ICCNT when NACKMOD is '1'. The NACKMOD bit should be set before the rising edge of the last data bit (bit 8) if a NACK must be sent and this bit is cleared once a NACK has been sent. NACKMOD=0 the I2C sends an ACK to the transmitter during the acknowledge cycle. NACKMOD=1 the I2C sends a NACK to the transmitter during the acknowledge cycle."]
# [inline (always)]
pub fn nackmod (& self) -> NackmodR { NackmodR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Bit Count : Bit Count 2, Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted. __________________________________________ BC2_BC1_BC0__Bits/byte in FDF__Bits/byte w/ ACK _0___0___1_____NA (reserved)____ NA (reserved) _0___1___0________2______________3_______ _0___1___1________3______________4_______ _1___0___0________4______________5_______ _1___0___1________5______________6_______ _1___1___0________6______________7_______ _1___1___1________7______________8_______ _0___0___0________8______________9_______ __________________________________________"]
# [inline (always)]
# [must_use]
pub fn bc2_bc1_bc0 (& mut self) -> Bc2Bc1Bc0W < IcmdrSpec > { Bc2Bc1Bc0W :: new (self , 0) } # [doc = "Bit 3 - 3:3\\]
Free Data Format. This bit can be set to\"1\" by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode _0______1_____0____Master receive in non FDF mode _0______1_____1____Master transmit in non FDF mode _1______0_____0____Slave receiver in FDF mode _1______0_____1____Slave transmitter in FDF mode _1______1_____0____Master receiver in FDF mode _1______1_____1____Master transmitter in FDF mode ______________________________________________"]
# [inline (always)]
# [must_use]
pub fn fdf (& mut self) -> FdfW < IcmdrSpec > { FdfW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends \"00000001\"� regardless ICSAR value. Refer to the Philip I2C spec for more details."]
# [inline (always)]
# [must_use]
pub fn stb (& mut self) -> StbW < IcmdrSpec > { StbW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
I2C Reset Not. This can be set to a\"0\" by the CPU to put the I2C in reset or to a\"1\" to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during a transfer it can cause the I2C bus hang (SDA and SCL are tri-stated)."]
# [inline (always)]
# [must_use]
pub fn irs (& mut self) -> IrsW < IcmdrSpec > { IrsW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Digital Loop Back (in master transmit mode only). This bit is set to a\"1\" by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via an internal path. The address of the ICOAR is output on SDA."]
# [inline (always)]
# [must_use]
pub fn dlb (& mut self) -> DlbW < IcmdrSpec > { DlbW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Repeat Mode. This bit is set to a\"1\" by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to\"1\" regardless of ICCNT value. This bit is don\"t care if the I2C is configured in slave mode. _________________________________________________________ RM___STT___STP___Conditions_____Bus Activities_______Mode _0_____0_____0_______Idle___________None___________NA _0_____0_____1_______Stop____________P____________NA _0_____1_____0_____(Re)Start_______S-A-D..(n)..D____Repeat n _0_____1_____1_____(Re)Start-Stop___S-A-D..(n)..D-P__Repeat n _1_____0_____0_______Idle___________none___________NA _1_____0_____1_______Stop____________P ___________NA _1_____1_____0_____(Re)Start_______S-A-D-D-D.._____Continuous _1_____1_____1_____Reserved________None___________NA _________________________________________________________"]
# [inline (always)]
# [must_use]
pub fn rm (& mut self) -> RmW < IcmdrSpec > { RmW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode."]
# [inline (always)]
# [must_use]
pub fn xa (& mut self) -> XaW < IcmdrSpec > { XaW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Transmitter. TRX=0: The I 2 C is in the\"receiver\" mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the\"transmitter\" mode and the data in ICDXR is shifted out on data line SDA. The operating modes (not in FDF mode) are defined as follows. In FDF mode TRX must be configured even if the I2C is in slave mode because there is no address/direction byte in FDF mode. ______________________________ MST___TRX___Operating Modes _0______x_____\"slave receiver\" _0______x_____\"slave transmitter\" _1______0_____\"master receiver\" _1______1_____\"master transmitter\" ______________________________"]
# [inline (always)]
# [must_use]
pub fn trx (& mut self) -> TrxW < IcmdrSpec > { TrxW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Master. MST=0: The I 2 C peripheral is in the\"slave\" mode and clock is received from the\"master\" device. MST=1: The I 2 C peripheral is in the\"master\" mode and it generates the clock. This bit is clear when the transfer completed."]
# [inline (always)]
# [must_use]
pub fn mst (& mut self) -> MstW < IcmdrSpec > { MstW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Stop Condition (Master mode only). This bit can be set to a\"1\" by the CPU to generate a Stop condition. It is reset to \"0\" by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when the I2C is in non-repeat mode(RM=0)."]
# [inline (always)]
# [must_use]
pub fn stp (& mut self) -> StpW < IcmdrSpec > { StpW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Reserved for IDLEEN (IDLE Enable on 5509). - (RW )"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IcmdrSpec > { Nu1W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Start Condition (Master only mode). This bit can be set to a\"1\" by the CPU to generate a Start condition. In master mode when setting Start to\"1\" generates a Start condition. It is reset to \"0\" by the hardware after the Start condition has been generated. The Start/Stop bits can be configured to generate different transfer formats. Note that the STT and STP can be used to terminate the repeat mode. ____________________________________________________ STT___STP____Conditions_______________Bus Activities _1_____0________Start___________________S-A-D _0_____1________Stop_____________________P _1_____1________Start-Stop (ICCNT= n)______S-A-D..(n)..D-P _1_____0________Start (ICCNT= n)__________S-A-D..(n)..D ____________________________________________________"]
# [inline (always)]
# [must_use]
pub fn stt (& mut self) -> SttW < IcmdrSpec > { SttW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL is high I2C waits until SCL becomes low and then stops. If the I2C is a slave it will stop when the transmission/receiving completes. FREE=1: The I2C runs free."]
# [inline (always)]
# [must_use]
pub fn free (& mut self) -> FreeW < IcmdrSpec > { FreeW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count counter decrements to zero the I2C sends a NACK. The master receiver I2C finishes a transfer when it sends a NACK. The I2C ignores ICCNT when NACKMOD is '1'. The NACKMOD bit should be set before the rising edge of the last data bit (bit 8) if a NACK must be sent and this bit is cleared once a NACK has been sent. NACKMOD=0 the I2C sends an ACK to the transmitter during the acknowledge cycle. NACKMOD=1 the I2C sends a NACK to the transmitter during the acknowledge cycle."]
# [inline (always)]
# [must_use]
pub fn nackmod (& mut self) -> NackmodW < IcmdrSpec > { NackmodW :: new (self , 15) } # [doc = "Bits 16:31 - 31:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < IcmdrSpec > { Nu2W :: new (self , 16) } } # [doc = "I2C Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`icmdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icmdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcmdrSpec ; impl crate :: RegisterSpec for IcmdrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icmdr::R`](R) reader structure"]
impl crate :: Readable for IcmdrSpec { } # [doc = "`write(|w| ..)` method takes [`icmdr::W`](W) writer structure"]
impl crate :: Writable for IcmdrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICMDR to value 0"]
impl crate :: Resettable for IcmdrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICIVR (rw) register accessor: I2C Interrupt Vector register\n\nYou can [`read`](crate::Reg::read) this register and get [`icivr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icivr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icivr`]
module"]
# [doc (alias = "ICIVR")]
pub type Icivr = crate :: Reg < icivr :: IcivrSpec > ; # [doc = "I2C Interrupt Vector register"]
pub mod icivr { # [doc = "Register `ICIVR` reader"]
pub type R = crate :: R < IcivrSpec > ; # [doc = "Register `ICIVR` writer"]
pub type W = crate :: W < IcivrSpec > ; # [doc = "Field `INTCODE` reader - 2:0\\]
Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY and ICXRDY bits in the ICSTR is cleared to default value respectively. If other interrupts are pending a new interrupt is generated. If there are more than one interrupt flag reading the ICIVR clears the highest priority interrupt code. Reading the ICIVR also clears corresponding status bit in the ICSTR except ARDY ICRRDY ICXRDY and AAS. Note that users must read (clear) the ICIVR before doing another start otherwise the ICIVR could contain incorrect (old interrupt flags) value. ________________________________________________ Interrupt Code____________Interrupt Occurred__________ _000_(default)_________________None _001_(highest priority)____Arbitration Lost interrupt _010__________________No Acknowledgement interrupt _011__________________Register Access Ready interrupt _100__________________Receive Data Ready interrupt _101__________________Transmit Data Ready interrupt _110__________________Stop Condition Detection _111_(lowest priority)_____Address As Slave - (RW) ________________________________________________"]
pub type IntcodeR = crate :: FieldReader ; # [doc = "Field `INTCODE` writer - 2:0\\]
Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY and ICXRDY bits in the ICSTR is cleared to default value respectively. If other interrupts are pending a new interrupt is generated. If there are more than one interrupt flag reading the ICIVR clears the highest priority interrupt code. Reading the ICIVR also clears corresponding status bit in the ICSTR except ARDY ICRRDY ICXRDY and AAS. Note that users must read (clear) the ICIVR before doing another start otherwise the ICIVR could contain incorrect (old interrupt flags) value. ________________________________________________ Interrupt Code____________Interrupt Occurred__________ _000_(default)_________________None _001_(highest priority)____Arbitration Lost interrupt _010__________________No Acknowledgement interrupt _011__________________Register Access Ready interrupt _100__________________Receive Data Ready interrupt _101__________________Transmit Data Ready interrupt _110__________________Stop Condition Detection _111_(lowest priority)_____Address As Slave - (RW) ________________________________________________"]
pub type IntcodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `NU1` reader - 7:3\\]
Reserved."]
pub type Nu1R = crate :: FieldReader ; # [doc = "Field `NU1` writer - 7:3\\]
Reserved."]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `TESTMD` reader - 11:8\\]
Reserved for internal testing."]
pub type TestmdR = crate :: FieldReader ; # [doc = "Field `TESTMD` writer - 11:8\\]
Reserved for internal testing."]
pub type TestmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `NU2` reader - 31:12\\]
Reserved."]
pub type Nu2R = crate :: FieldReader < u32 > ; # [doc = "Field `NU2` writer - 31:12\\]
Reserved."]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY and ICXRDY bits in the ICSTR is cleared to default value respectively. If other interrupts are pending a new interrupt is generated. If there are more than one interrupt flag reading the ICIVR clears the highest priority interrupt code. Reading the ICIVR also clears corresponding status bit in the ICSTR except ARDY ICRRDY ICXRDY and AAS. Note that users must read (clear) the ICIVR before doing another start otherwise the ICIVR could contain incorrect (old interrupt flags) value. ________________________________________________ Interrupt Code____________Interrupt Occurred__________ _000_(default)_________________None _001_(highest priority)____Arbitration Lost interrupt _010__________________No Acknowledgement interrupt _011__________________Register Access Ready interrupt _100__________________Receive Data Ready interrupt _101__________________Transmit Data Ready interrupt _110__________________Stop Condition Detection _111_(lowest priority)_____Address As Slave - (RW) ________________________________________________"]
# [inline (always)]
pub fn intcode (& self) -> IntcodeR { IntcodeR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:7 - 7:3\\]
Reserved."]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Reserved for internal testing."]
# [inline (always)]
pub fn testmd (& self) -> TestmdR { TestmdR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:31 - 31:12\\]
Reserved."]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY and ICXRDY bits in the ICSTR is cleared to default value respectively. If other interrupts are pending a new interrupt is generated. If there are more than one interrupt flag reading the ICIVR clears the highest priority interrupt code. Reading the ICIVR also clears corresponding status bit in the ICSTR except ARDY ICRRDY ICXRDY and AAS. Note that users must read (clear) the ICIVR before doing another start otherwise the ICIVR could contain incorrect (old interrupt flags) value. ________________________________________________ Interrupt Code____________Interrupt Occurred__________ _000_(default)_________________None _001_(highest priority)____Arbitration Lost interrupt _010__________________No Acknowledgement interrupt _011__________________Register Access Ready interrupt _100__________________Receive Data Ready interrupt _101__________________Transmit Data Ready interrupt _110__________________Stop Condition Detection _111_(lowest priority)_____Address As Slave - (RW) ________________________________________________"]
# [inline (always)]
# [must_use]
pub fn intcode (& mut self) -> IntcodeW < IcivrSpec > { IntcodeW :: new (self , 0) } # [doc = "Bits 3:7 - 7:3\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < IcivrSpec > { Nu1W :: new (self , 3) } # [doc = "Bits 8:11 - 11:8\\]
Reserved for internal testing."]
# [inline (always)]
# [must_use]
pub fn testmd (& mut self) -> TestmdW < IcivrSpec > { TestmdW :: new (self , 8) } # [doc = "Bits 12:31 - 31:12\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < IcivrSpec > { Nu2W :: new (self , 12) } } # [doc = "I2C Interrupt Vector register\n\nYou can [`read`](crate::Reg::read) this register and get [`icivr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icivr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcivrSpec ; impl crate :: RegisterSpec for IcivrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icivr::R`](R) reader structure"]
impl crate :: Readable for IcivrSpec { } # [doc = "`write(|w| ..)` method takes [`icivr::W`](W) writer structure"]
impl crate :: Writable for IcivrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICIVR to value 0"]
impl crate :: Resettable for IcivrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICEMDR (rw) register accessor: I2C Extended Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`icemdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icemdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icemdr`]
module"]
# [doc (alias = "ICEMDR")]
pub type Icemdr = crate :: Reg < icemdr :: IcemdrSpec > ; # [doc = "I2C Extended Mode register"]
pub mod icemdr { # [doc = "Register `ICEMDR` reader"]
pub type R = crate :: R < IcemdrSpec > ; # [doc = "Register `ICEMDR` writer"]
pub type W = crate :: W < IcemdrSpec > ; # [doc = "Field `BCM` reader - 0:0\\]
Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details."]
pub type BcmR = crate :: BitReader ; # [doc = "Field `BCM` writer - 0:0\\]
Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details."]
pub type BcmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IGNACK` reader - 1:1\\]
Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK received from the slave."]
pub type IgnackR = crate :: BitReader ; # [doc = "Field `IGNACK` writer - 1:1\\]
Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK received from the slave."]
pub type IgnackW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved. - (RW )"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved. - (RW )"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details."]
# [inline (always)]
pub fn bcm (& self) -> BcmR { BcmR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK received from the slave."]
# [inline (always)]
pub fn ignack (& self) -> IgnackR { IgnackR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. - (RW )"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details."]
# [inline (always)]
# [must_use]
pub fn bcm (& mut self) -> BcmW < IcemdrSpec > { BcmW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK received from the slave."]
# [inline (always)]
# [must_use]
pub fn ignack (& mut self) -> IgnackW < IcemdrSpec > { IgnackW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. - (RW )"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcemdrSpec > { NuW :: new (self , 2) } } # [doc = "I2C Extended Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`icemdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icemdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcemdrSpec ; impl crate :: RegisterSpec for IcemdrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icemdr::R`](R) reader structure"]
impl crate :: Readable for IcemdrSpec { } # [doc = "`write(|w| ..)` method takes [`icemdr::W`](W) writer structure"]
impl crate :: Writable for IcemdrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICEMDR to value 0"]
impl crate :: Resettable for IcemdrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPSC (rw) register accessor: I2C Prescaler register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpsc`]
module"]
# [doc (alias = "ICPSC")]
pub type Icpsc = crate :: Reg < icpsc :: IcpscSpec > ; # [doc = "I2C Prescaler register"]
pub mod icpsc { # [doc = "Register `ICPSC` reader"]
pub type R = crate :: R < IcpscSpec > ; # [doc = "Register `ICPSC` writer"]
pub type W = crate :: W < IcpscSpec > ; # [doc = "Field `IPSC7_IPSC0` reader - 7:0\\]
8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_."]
pub type Ipsc7Ipsc0R = crate :: FieldReader ; # [doc = "Field `IPSC7_IPSC0` writer - 7:0\\]
8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_."]
pub type Ipsc7Ipsc0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU` reader - 31:8\\]
Reserved."]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:8\\]
Reserved."]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_."]
# [inline (always)]
pub fn ipsc7_ipsc0 (& self) -> Ipsc7Ipsc0R { Ipsc7Ipsc0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved."]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_."]
# [inline (always)]
# [must_use]
pub fn ipsc7_ipsc0 (& mut self) -> Ipsc7Ipsc0W < IcpscSpec > { Ipsc7Ipsc0W :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpscSpec > { NuW :: new (self , 8) } } # [doc = "I2C Prescaler register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpscSpec ; impl crate :: RegisterSpec for IcpscSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpsc::R`](R) reader structure"]
impl crate :: Readable for IcpscSpec { } # [doc = "`write(|w| ..)` method takes [`icpsc::W`](W) writer structure"]
impl crate :: Writable for IcpscSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPSC to value 0"]
impl crate :: Resettable for IcpscSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPID1 (rw) register accessor: I2C Peripheral ID register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`icpid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpid1`]
module"]
# [doc (alias = "ICPID1")]
pub type Icpid1 = crate :: Reg < icpid1 :: Icpid1Spec > ; # [doc = "I2C Peripheral ID register 1"]
pub mod icpid1 { # [doc = "Register `ICPID1` reader"]
pub type R = crate :: R < Icpid1Spec > ; # [doc = "Register `ICPID1` writer"]
pub type W = crate :: W < Icpid1Spec > ; # [doc = "Field `REVISION` reader - 7:0\\]
Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )"]
pub type RevisionR = crate :: FieldReader ; # [doc = "Field `REVISION` writer - 7:0\\]
Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )"]
pub type RevisionW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `CLASS` reader - 15:8\\]
Identifies the class of peripheral. This value should be 0x01 - (RW )"]
pub type ClassR = crate :: FieldReader ; # [doc = "Field `CLASS` writer - 15:8\\]
Identifies the class of peripheral. This value should be 0x01 - (RW )"]
pub type ClassW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU` reader - 31:16\\]
Reserved."]
pub type NuR = crate :: FieldReader < u16 > ; # [doc = "Field `NU` writer - 31:16\\]
Reserved."]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )"]
# [inline (always)]
pub fn revision (& self) -> RevisionR { RevisionR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Identifies the class of peripheral. This value should be 0x01 - (RW )"]
# [inline (always)]
pub fn class (& self) -> ClassR { ClassR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved."]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )"]
# [inline (always)]
# [must_use]
pub fn revision (& mut self) -> RevisionW < Icpid1Spec > { RevisionW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Identifies the class of peripheral. This value should be 0x01 - (RW )"]
# [inline (always)]
# [must_use]
pub fn class (& mut self) -> ClassW < Icpid1Spec > { ClassW :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Icpid1Spec > { NuW :: new (self , 16) } } # [doc = "I2C Peripheral ID register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`icpid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Icpid1Spec ; impl crate :: RegisterSpec for Icpid1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpid1::R`](R) reader structure"]
impl crate :: Readable for Icpid1Spec { } # [doc = "`write(|w| ..)` method takes [`icpid1::W`](W) writer structure"]
impl crate :: Writable for Icpid1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPID1 to value 0"]
impl crate :: Resettable for Icpid1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPID2 (rw) register accessor: I2C Peripheral ID register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`icpid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpid2`]
module"]
# [doc (alias = "ICPID2")]
pub type Icpid2 = crate :: Reg < icpid2 :: Icpid2Spec > ; # [doc = "I2C Peripheral ID register 2"]
pub mod icpid2 { # [doc = "Register `ICPID2` reader"]
pub type R = crate :: R < Icpid2Spec > ; # [doc = "Register `ICPID2` writer"]
pub type W = crate :: W < Icpid2Spec > ; # [doc = "Field `TYPE` reader - 7:0\\]
Identifies the type of peripheral. This value should be 0x05 - (RW )"]
pub type TypeR = crate :: FieldReader ; # [doc = "Field `TYPE` writer - 7:0\\]
Identifies the type of peripheral. This value should be 0x05 - (RW )"]
pub type TypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU` reader - 31:8\\]
Reserved."]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:8\\]
Reserved."]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Identifies the type of peripheral. This value should be 0x05 - (RW )"]
# [inline (always)]
pub fn type_ (& self) -> TypeR { TypeR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved."]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Identifies the type of peripheral. This value should be 0x05 - (RW )"]
# [inline (always)]
# [must_use]
pub fn type_ (& mut self) -> TypeW < Icpid2Spec > { TypeW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < Icpid2Spec > { NuW :: new (self , 8) } } # [doc = "I2C Peripheral ID register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`icpid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Icpid2Spec ; impl crate :: RegisterSpec for Icpid2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpid2::R`](R) reader structure"]
impl crate :: Readable for Icpid2Spec { } # [doc = "`write(|w| ..)` method takes [`icpid2::W`](W) writer structure"]
impl crate :: Writable for Icpid2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPID2 to value 0"]
impl crate :: Resettable for Icpid2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICDMAC (rw) register accessor: I2C DMA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icdmac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icdmac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icdmac`]
module"]
# [doc (alias = "ICDMAC")]
pub type Icdmac = crate :: Reg < icdmac :: IcdmacSpec > ; # [doc = "I2C DMA Control Register"]
pub mod icdmac { # [doc = "Register `ICDMAC` reader"]
pub type R = crate :: R < IcdmacSpec > ; # [doc = "Register `ICDMAC` writer"]
pub type W = crate :: W < IcdmacSpec > ; # [doc = "Field `RXDMAEN` reader - 0:0\\]
Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never asserted. RXDMAEN=0: DMA receive event is disabled. RXDMAEN=1: DMA receive event is enabled. (Default)"]
pub type RxdmaenR = crate :: BitReader ; # [doc = "Field `RXDMAEN` writer - 0:0\\]
Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never asserted. RXDMAEN=0: DMA receive event is disabled. RXDMAEN=1: DMA receive event is enabled. (Default)"]
pub type RxdmaenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXDMAEN` reader - 1:1\\]
Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never asserted. RXDMAEN=0: DMA transmit event is disabled. RXDMAEN=1: DMA transmit event is enabled. (Default)"]
pub type TxdmaenR = crate :: BitReader ; # [doc = "Field `TXDMAEN` writer - 1:1\\]
Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never asserted. RXDMAEN=0: DMA transmit event is disabled. RXDMAEN=1: DMA transmit event is enabled. (Default)"]
pub type TxdmaenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved. - (RW )"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved. - (RW )"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never asserted. RXDMAEN=0: DMA receive event is disabled. RXDMAEN=1: DMA receive event is enabled. (Default)"]
# [inline (always)]
pub fn rxdmaen (& self) -> RxdmaenR { RxdmaenR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never asserted. RXDMAEN=0: DMA transmit event is disabled. RXDMAEN=1: DMA transmit event is enabled. (Default)"]
# [inline (always)]
pub fn txdmaen (& self) -> TxdmaenR { TxdmaenR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. - (RW )"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never asserted. RXDMAEN=0: DMA receive event is disabled. RXDMAEN=1: DMA receive event is enabled. (Default)"]
# [inline (always)]
# [must_use]
pub fn rxdmaen (& mut self) -> RxdmaenW < IcdmacSpec > { RxdmaenW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never asserted. RXDMAEN=0: DMA transmit event is disabled. RXDMAEN=1: DMA transmit event is enabled. (Default)"]
# [inline (always)]
# [must_use]
pub fn txdmaen (& mut self) -> TxdmaenW < IcdmacSpec > { TxdmaenW :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved. - (RW )"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcdmacSpec > { NuW :: new (self , 2) } } # [doc = "I2C DMA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icdmac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icdmac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcdmacSpec ; impl crate :: RegisterSpec for IcdmacSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icdmac::R`](R) reader structure"]
impl crate :: Readable for IcdmacSpec { } # [doc = "`write(|w| ..)` method takes [`icdmac::W`](W) writer structure"]
impl crate :: Writable for IcdmacSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICDMAC to value 0"]
impl crate :: Resettable for IcdmacSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "I2C_RESERVED1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_reserved1`]
module"]
# [doc (alias = "I2C_RESERVED1")]
pub type I2cReserved1 = crate :: Reg < i2c_reserved1 :: I2cReserved1Spec > ; # [doc = "Reserved"]
pub mod i2c_reserved1 { # [doc = "Register `I2C_RESERVED1` reader"]
pub type R = crate :: R < I2cReserved1Spec > ; # [doc = "Register `I2C_RESERVED1` writer"]
pub type W = crate :: W < I2cReserved1Spec > ; # [doc = "Field `NU` reader - 31:0\\]
Reserved."]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:0\\]
Reserved."]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved."]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < I2cReserved1Spec > { NuW :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2cReserved1Spec ; impl crate :: RegisterSpec for I2cReserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`i2c_reserved1::R`](R) reader structure"]
impl crate :: Readable for I2cReserved1Spec { } # [doc = "`write(|w| ..)` method takes [`i2c_reserved1::W`](W) writer structure"]
impl crate :: Writable for I2cReserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets I2C_RESERVED1 to value 0"]
impl crate :: Resettable for I2cReserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "I2C_RESERVED2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_reserved2`]
module"]
# [doc (alias = "I2C_RESERVED2")]
pub type I2cReserved2 = crate :: Reg < i2c_reserved2 :: I2cReserved2Spec > ; # [doc = "Reserved"]
pub mod i2c_reserved2 { # [doc = "Register `I2C_RESERVED2` reader"]
pub type R = crate :: R < I2cReserved2Spec > ; # [doc = "Register `I2C_RESERVED2` writer"]
pub type W = crate :: W < I2cReserved2Spec > ; # [doc = "Field `NU` reader - 31:0\\]
Reserved."]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:0\\]
Reserved."]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved."]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < I2cReserved2Spec > { NuW :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2cReserved2Spec ; impl crate :: RegisterSpec for I2cReserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`i2c_reserved2::R`](R) reader structure"]
impl crate :: Readable for I2cReserved2Spec { } # [doc = "`write(|w| ..)` method takes [`i2c_reserved2::W`](W) writer structure"]
impl crate :: Writable for I2cReserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets I2C_RESERVED2 to value 0"]
impl crate :: Resettable for I2cReserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPFUNC (rw) register accessor: I2C Pin Function register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpfunc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpfunc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpfunc`]
module"]
# [doc (alias = "ICPFUNC")]
pub type Icpfunc = crate :: Reg < icpfunc :: IcpfuncSpec > ; # [doc = "I2C Pin Function register"]
pub mod icpfunc { # [doc = "Register `ICPFUNC` reader"]
pub type R = crate :: R < IcpfuncSpec > ; # [doc = "Register `ICPFUNC` writer"]
pub type W = crate :: W < IcpfuncSpec > ; # [doc = "Field `PFUNC0` reader - 0:0\\]
Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC\\[0\\]
and IRS_ bits are both set to one. When PFUNC\\[0\\]
is\"1\" (GPIO mode) the sub-module which controls the I2C function receives the value\"1\" for SCL and SDA. IRS_ can be set to\"1\" regardless of PFUNC\\[0\\]
and the I2C function works whenever the IRS_ bit is\"1\". The user is expected to hold I2C in reset via IRS_ bit when changing to/from GPIO mode via the PFUNC\\[0\\]
bit."]
pub type Pfunc0R = crate :: BitReader ; # [doc = "Field `PFUNC0` writer - 0:0\\]
Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC\\[0\\]
and IRS_ bits are both set to one. When PFUNC\\[0\\]
is\"1\" (GPIO mode) the sub-module which controls the I2C function receives the value\"1\" for SCL and SDA. IRS_ can be set to\"1\" regardless of PFUNC\\[0\\]
and the I2C function works whenever the IRS_ bit is\"1\". The user is expected to hold I2C in reset via IRS_ bit when changing to/from GPIO mode via the PFUNC\\[0\\]
bit."]
pub type Pfunc0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:1\\]
Reserved."]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:1\\]
Reserved."]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC\\[0\\]
and IRS_ bits are both set to one. When PFUNC\\[0\\]
is\"1\" (GPIO mode) the sub-module which controls the I2C function receives the value\"1\" for SCL and SDA. IRS_ can be set to\"1\" regardless of PFUNC\\[0\\]
and the I2C function works whenever the IRS_ bit is\"1\". The user is expected to hold I2C in reset via IRS_ bit when changing to/from GPIO mode via the PFUNC\\[0\\]
bit."]
# [inline (always)]
pub fn pfunc0 (& self) -> Pfunc0R { Pfunc0R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved."]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC\\[0\\]
and IRS_ bits are both set to one. When PFUNC\\[0\\]
is\"1\" (GPIO mode) the sub-module which controls the I2C function receives the value\"1\" for SCL and SDA. IRS_ can be set to\"1\" regardless of PFUNC\\[0\\]
and the I2C function works whenever the IRS_ bit is\"1\". The user is expected to hold I2C in reset via IRS_ bit when changing to/from GPIO mode via the PFUNC\\[0\\]
bit."]
# [inline (always)]
# [must_use]
pub fn pfunc0 (& mut self) -> Pfunc0W < IcpfuncSpec > { Pfunc0W :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved."]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpfuncSpec > { NuW :: new (self , 1) } } # [doc = "I2C Pin Function register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpfunc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpfunc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpfuncSpec ; impl crate :: RegisterSpec for IcpfuncSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpfunc::R`](R) reader structure"]
impl crate :: Readable for IcpfuncSpec { } # [doc = "`write(|w| ..)` method takes [`icpfunc::W`](W) writer structure"]
impl crate :: Writable for IcpfuncSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPFUNC to value 0"]
impl crate :: Resettable for IcpfuncSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPDIR (rw) register accessor: I2C Pin Direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpdir`]
module"]
# [doc (alias = "ICPDIR")]
pub type Icpdir = crate :: Reg < icpdir :: IcpdirSpec > ; # [doc = "I2C Pin Direction register"]
pub mod icpdir { # [doc = "Register `ICPDIR` reader"]
pub type R = crate :: R < IcpdirSpec > ; # [doc = "Register `ICPDIR` writer"]
pub type W = crate :: W < IcpdirSpec > ; # [doc = "Field `PDIR0` reader - 0:0\\]
Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output"]
pub type Pdir0R = crate :: BitReader ; # [doc = "Field `PDIR0` writer - 0:0\\]
Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output"]
pub type Pdir0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDIR1` reader - 1:1\\]
Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output"]
pub type Pdir1R = crate :: BitReader ; # [doc = "Field `PDIR1` writer - 1:1\\]
Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output"]
pub type Pdir1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output"]
# [inline (always)]
pub fn pdir0 (& self) -> Pdir0R { Pdir0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output"]
# [inline (always)]
pub fn pdir1 (& self) -> Pdir1R { Pdir1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output"]
# [inline (always)]
# [must_use]
pub fn pdir0 (& mut self) -> Pdir0W < IcpdirSpec > { Pdir0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output"]
# [inline (always)]
# [must_use]
pub fn pdir1 (& mut self) -> Pdir1W < IcpdirSpec > { Pdir1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpdirSpec > { NuW :: new (self , 2) } } # [doc = "I2C Pin Direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpdirSpec ; impl crate :: RegisterSpec for IcpdirSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpdir::R`](R) reader structure"]
impl crate :: Readable for IcpdirSpec { } # [doc = "`write(|w| ..)` method takes [`icpdir::W`](W) writer structure"]
impl crate :: Writable for IcpdirSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPDIR to value 0"]
impl crate :: Resettable for IcpdirSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPDIN (rw) register accessor: I2C Pin Data In register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpdin`]
module"]
# [doc (alias = "ICPDIN")]
pub type Icpdin = crate :: Reg < icpdin :: IcpdinSpec > ; # [doc = "I2C Pin Data In register"]
pub mod icpdin { # [doc = "Register `ICPDIN` reader"]
pub type R = crate :: R < IcpdinSpec > ; # [doc = "Register `ICPDIN` writer"]
pub type W = crate :: W < IcpdinSpec > ; # [doc = "Field `PDIN0` reader - 0:0\\]
Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )"]
pub type Pdin0R = crate :: BitReader ; # [doc = "Field `PDIN0` writer - 0:0\\]
Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )"]
pub type Pdin0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDIN1` reader - 1:1\\]
Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )"]
pub type Pdin1R = crate :: BitReader ; # [doc = "Field `PDIN1` writer - 1:1\\]
Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )"]
pub type Pdin1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )"]
# [inline (always)]
pub fn pdin0 (& self) -> Pdin0R { Pdin0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )"]
# [inline (always)]
pub fn pdin1 (& self) -> Pdin1R { Pdin1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )"]
# [inline (always)]
# [must_use]
pub fn pdin0 (& mut self) -> Pdin0W < IcpdinSpec > { Pdin0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )"]
# [inline (always)]
# [must_use]
pub fn pdin1 (& mut self) -> Pdin1W < IcpdinSpec > { Pdin1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpdinSpec > { NuW :: new (self , 2) } } # [doc = "I2C Pin Data In register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpdinSpec ; impl crate :: RegisterSpec for IcpdinSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpdin::R`](R) reader structure"]
impl crate :: Readable for IcpdinSpec { } # [doc = "`write(|w| ..)` method takes [`icpdin::W`](W) writer structure"]
impl crate :: Writable for IcpdinSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPDIN to value 0"]
impl crate :: Resettable for IcpdinSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPDOUT (rw) register accessor: I2C Pin Data Out register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpdout`]
module"]
# [doc (alias = "ICPDOUT")]
pub type Icpdout = crate :: Reg < icpdout :: IcpdoutSpec > ; # [doc = "I2C Pin Data Out register"]
pub mod icpdout { # [doc = "Register `ICPDOUT` reader"]
pub type R = crate :: R < IcpdoutSpec > ; # [doc = "Register `ICPDOUT` writer"]
pub type W = crate :: W < IcpdoutSpec > ; # [doc = "Field `PDOUT0` reader - 0:0\\]
Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at the chiplevel the I2C cannot drive SCL to high."]
pub type Pdout0R = crate :: BitReader ; # [doc = "Field `PDOUT0` writer - 0:0\\]
Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at the chiplevel the I2C cannot drive SCL to high."]
pub type Pdout0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDOUT1` reader - 1:1\\]
Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at the chiplevel the I2C cannot drive SDA to high."]
pub type Pdout1R = crate :: BitReader ; # [doc = "Field `PDOUT1` writer - 1:1\\]
Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at the chiplevel the I2C cannot drive SDA to high."]
pub type Pdout1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at the chiplevel the I2C cannot drive SCL to high."]
# [inline (always)]
pub fn pdout0 (& self) -> Pdout0R { Pdout0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at the chiplevel the I2C cannot drive SDA to high."]
# [inline (always)]
pub fn pdout1 (& self) -> Pdout1R { Pdout1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at the chiplevel the I2C cannot drive SCL to high."]
# [inline (always)]
# [must_use]
pub fn pdout0 (& mut self) -> Pdout0W < IcpdoutSpec > { Pdout0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at the chiplevel the I2C cannot drive SDA to high."]
# [inline (always)]
# [must_use]
pub fn pdout1 (& mut self) -> Pdout1W < IcpdoutSpec > { Pdout1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpdoutSpec > { NuW :: new (self , 2) } } # [doc = "I2C Pin Data Out register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpdoutSpec ; impl crate :: RegisterSpec for IcpdoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpdout::R`](R) reader structure"]
impl crate :: Readable for IcpdoutSpec { } # [doc = "`write(|w| ..)` method takes [`icpdout::W`](W) writer structure"]
impl crate :: Writable for IcpdoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPDOUT to value 0"]
impl crate :: Resettable for IcpdoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPDSET (rw) register accessor: I2C Pin Data Set register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpdset`]
module"]
# [doc (alias = "ICPDSET")]
pub type Icpdset = crate :: Reg < icpdset :: IcpdsetSpec > ; # [doc = "I2C Pin Data Set register"]
pub mod icpdset { # [doc = "Register `ICPDSET` reader"]
pub type R = crate :: R < IcpdsetSpec > ; # [doc = "Register `ICPDSET` writer"]
pub type W = crate :: W < IcpdsetSpec > ; # [doc = "Field `PDSET0` reader - 0:0\\]
Used to set PDOUT\\[0\\]
bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is set to logic high."]
pub type Pdset0R = crate :: BitReader ; # [doc = "Field `PDSET0` writer - 0:0\\]
Used to set PDOUT\\[0\\]
bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is set to logic high."]
pub type Pdset0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDSET1` reader - 1:1\\]
Used to set PDOUT\\[1\\]
bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is set to logic high."]
pub type Pdset1R = crate :: BitReader ; # [doc = "Field `PDSET1` writer - 1:1\\]
Used to set PDOUT\\[1\\]
bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is set to logic high."]
pub type Pdset1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Used to set PDOUT\\[0\\]
bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is set to logic high."]
# [inline (always)]
pub fn pdset0 (& self) -> Pdset0R { Pdset0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Used to set PDOUT\\[1\\]
bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is set to logic high."]
# [inline (always)]
pub fn pdset1 (& self) -> Pdset1R { Pdset1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Used to set PDOUT\\[0\\]
bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is set to logic high."]
# [inline (always)]
# [must_use]
pub fn pdset0 (& mut self) -> Pdset0W < IcpdsetSpec > { Pdset0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Used to set PDOUT\\[1\\]
bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is set to logic high."]
# [inline (always)]
# [must_use]
pub fn pdset1 (& mut self) -> Pdset1W < IcpdsetSpec > { Pdset1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpdsetSpec > { NuW :: new (self , 2) } } # [doc = "I2C Pin Data Set register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpdsetSpec ; impl crate :: RegisterSpec for IcpdsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpdset::R`](R) reader structure"]
impl crate :: Readable for IcpdsetSpec { } # [doc = "`write(|w| ..)` method takes [`icpdset::W`](W) writer structure"]
impl crate :: Writable for IcpdsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPDSET to value 0"]
impl crate :: Resettable for IcpdsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPDCLR (rw) register accessor: I2C Pin Data Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpdclr`]
module"]
# [doc (alias = "ICPDCLR")]
pub type Icpdclr = crate :: Reg < icpdclr :: IcpdclrSpec > ; # [doc = "I2C Pin Data Clear register"]
pub mod icpdclr { # [doc = "Register `ICPDCLR` reader"]
pub type R = crate :: R < IcpdclrSpec > ; # [doc = "Register `ICPDCLR` writer"]
pub type W = crate :: W < IcpdclrSpec > ; # [doc = "Field `PDCLR0` reader - 0:0\\]
Used to clear PDOUT\\[0\\]
bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is cleared to logic low."]
pub type Pdclr0R = crate :: BitReader ; # [doc = "Field `PDCLR0` writer - 0:0\\]
Used to clear PDOUT\\[0\\]
bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is cleared to logic low."]
pub type Pdclr0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDCLR1` reader - 1:1\\]
Used to clear PDOUT\\[1\\]
bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is cleared to logic low."]
pub type Pdclr1R = crate :: BitReader ; # [doc = "Field `PDCLR1` writer - 1:1\\]
Used to clear PDOUT\\[1\\]
bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is cleared to logic low."]
pub type Pdclr1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Used to clear PDOUT\\[0\\]
bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is cleared to logic low."]
# [inline (always)]
pub fn pdclr0 (& self) -> Pdclr0R { Pdclr0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Used to clear PDOUT\\[1\\]
bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is cleared to logic low."]
# [inline (always)]
pub fn pdclr1 (& self) -> Pdclr1R { Pdclr1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Used to clear PDOUT\\[0\\]
bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[0\\]
bit is cleared to logic low."]
# [inline (always)]
# [must_use]
pub fn pdclr0 (& mut self) -> Pdclr0W < IcpdclrSpec > { Pdclr0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Used to clear PDOUT\\[1\\]
bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT\\[1\\]
bit is cleared to logic low."]
# [inline (always)]
# [must_use]
pub fn pdclr1 (& mut self) -> Pdclr1W < IcpdclrSpec > { Pdclr1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpdclrSpec > { NuW :: new (self , 2) } } # [doc = "I2C Pin Data Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpdclrSpec ; impl crate :: RegisterSpec for IcpdclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpdclr::R`](R) reader structure"]
impl crate :: Readable for IcpdclrSpec { } # [doc = "`write(|w| ..)` method takes [`icpdclr::W`](W) writer structure"]
impl crate :: Writable for IcpdclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPDCLR to value 0"]
impl crate :: Resettable for IcpdclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ICPDRV (rw) register accessor: I2C Pin Driver Mode Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdrv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdrv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icpdrv`]
module"]
# [doc (alias = "ICPDRV")]
pub type Icpdrv = crate :: Reg < icpdrv :: IcpdrvSpec > ; # [doc = "I2C Pin Driver Mode Register"]
pub mod icpdrv { # [doc = "Register `ICPDRV` reader"]
pub type R = crate :: R < IcpdrvSpec > ; # [doc = "Register `ICPDRV` writer"]
pub type W = crate :: W < IcpdrvSpec > ; # [doc = "Field `PDRV0` reader - 0:0\\]
Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation."]
pub type Pdrv0R = crate :: BitReader ; # [doc = "Field `PDRV0` writer - 0:0\\]
Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation."]
pub type Pdrv0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDRV1` reader - 1:1\\]
Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation."]
pub type Pdrv1R = crate :: BitReader ; # [doc = "Field `PDRV1` writer - 1:1\\]
Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation."]
pub type Pdrv1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:2\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:2\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation."]
# [inline (always)]
pub fn pdrv0 (& self) -> Pdrv0R { Pdrv0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation."]
# [inline (always)]
pub fn pdrv1 (& self) -> Pdrv1R { Pdrv1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation."]
# [inline (always)]
# [must_use]
pub fn pdrv0 (& mut self) -> Pdrv0W < IcpdrvSpec > { Pdrv0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation."]
# [inline (always)]
# [must_use]
pub fn pdrv1 (& mut self) -> Pdrv1W < IcpdrvSpec > { Pdrv1W :: new (self , 1) } # [doc = "Bits 2:31 - 31:2\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < IcpdrvSpec > { NuW :: new (self , 2) } } # [doc = "I2C Pin Driver Mode Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icpdrv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icpdrv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcpdrvSpec ; impl crate :: RegisterSpec for IcpdrvSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`icpdrv::R`](R) reader structure"]
impl crate :: Readable for IcpdrvSpec { } # [doc = "`write(|w| ..)` method takes [`icpdrv::W`](W) writer structure"]
impl crate :: Writable for IcpdrvSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ICPDRV to value 0"]
impl crate :: Resettable for IcpdrvSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_PWM"]
pub struct AppPwm { _marker : PhantomData < * const () > } unsafe impl Send for AppPwm { } impl AppPwm { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_pwm :: RegisterBlock = 0x57f7_fc00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_pwm :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppPwm { type Target = app_pwm :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppPwm { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppPwm") . finish () } } # [doc = "APP_PWM"]
pub mod app_pwm { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { tbctl_tbsts : TbctlTbsts , tbphs : Tbphs , tbctr_tbprd : TbctrTbprd , cmpctl : Cmpctl , cmpa : Cmpa , cmpb_aqctla : CmpbAqctla , aqctlb_aqsfrc : AqctlbAqsfrc , aqcsfrc_dbctl : AqcsfrcDbctl , dbred_dbfed : DbredDbfed , tzsel_tzdcsel : TzselTzdcsel , tzctl_tzeint : TzctlTzeint , tzflg_tzclr : TzflgTzclr , tzfrc_etsel : TzfrcEtsel , etps_etflg : EtpsEtflg , etclr_etfrc : EtclrEtfrc , pcctl : Pcctl , reserved1 : Reserved1 , reserved2 : Reserved2 , reserved3 : Reserved3 , reserved4 : Reserved4 , reserved5 : Reserved5 , reserved6 : Reserved6 , reserved7 : Reserved7 , reserved8 : Reserved8 , dctripsel_dcactl : DctripselDcactl , dcbctl_dcfctl : DcbctlDcfctl , dccapctl_dcfoffset : DccapctlDcfoffset , dcfoffsetcnt_dcfwindow : DcfoffsetcntDcfwindow , dcfwindowcnt_dccap : DcfwindowcntDccap , } impl RegisterBlock { # [doc = "0x00 - Time-Base Control Register/ Status Register"]
# [inline (always)]
pub const fn tbctl_tbsts (& self) -> & TbctlTbsts { & self . tbctl_tbsts } # [doc = "0x04 - Time-Base Phase Register"]
# [inline (always)]
pub const fn tbphs (& self) -> & Tbphs { & self . tbphs } # [doc = "0x08 - Time-Base Counter Register/ Period Register"]
# [inline (always)]
pub const fn tbctr_tbprd (& self) -> & TbctrTbprd { & self . tbctr_tbprd } # [doc = "0x0c - Counter-Compare Control Register"]
# [inline (always)]
pub const fn cmpctl (& self) -> & Cmpctl { & self . cmpctl } # [doc = "0x10 - Counter-Compare A Register"]
# [inline (always)]
pub const fn cmpa (& self) -> & Cmpa { & self . cmpa } # [doc = "0x14 - Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"]
# [inline (always)]
pub const fn cmpb_aqctla (& self) -> & CmpbAqctla { & self . cmpb_aqctla } # [doc = "0x18 - Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"]
# [inline (always)]
pub const fn aqctlb_aqsfrc (& self) -> & AqctlbAqsfrc { & self . aqctlb_aqsfrc } # [doc = "0x1c - Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"]
# [inline (always)]
pub const fn aqcsfrc_dbctl (& self) -> & AqcsfrcDbctl { & self . aqcsfrc_dbctl } # [doc = "0x20 - Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"]
# [inline (always)]
pub const fn dbred_dbfed (& self) -> & DbredDbfed { & self . dbred_dbfed } # [doc = "0x24 - Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"]
# [inline (always)]
pub const fn tzsel_tzdcsel (& self) -> & TzselTzdcsel { & self . tzsel_tzdcsel } # [doc = "0x28 - Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"]
# [inline (always)]
pub const fn tzctl_tzeint (& self) -> & TzctlTzeint { & self . tzctl_tzeint } # [doc = "0x2c - Trip-Zone Flag Register/ Trip-Zone Clear Register"]
# [inline (always)]
pub const fn tzflg_tzclr (& self) -> & TzflgTzclr { & self . tzflg_tzclr } # [doc = "0x30 - Trip-Zone Force Register / Event-Trigger Selection Register"]
# [inline (always)]
pub const fn tzfrc_etsel (& self) -> & TzfrcEtsel { & self . tzfrc_etsel } # [doc = "0x34 - Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"]
# [inline (always)]
pub const fn etps_etflg (& self) -> & EtpsEtflg { & self . etps_etflg } # [doc = "0x38 - Event-Trigger Clear Register/ Event-Trigger Force Register"]
# [inline (always)]
pub const fn etclr_etfrc (& self) -> & EtclrEtfrc { & self . etclr_etfrc } # [doc = "0x3c - PWM-Chopper Control Register"]
# [inline (always)]
pub const fn pcctl (& self) -> & Pcctl { & self . pcctl } # [doc = "0x40 - Reserved"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0x44 - Reserved"]
# [inline (always)]
pub const fn reserved2 (& self) -> & Reserved2 { & self . reserved2 } # [doc = "0x48 - Reserved"]
# [inline (always)]
pub const fn reserved3 (& self) -> & Reserved3 { & self . reserved3 } # [doc = "0x4c - Reserved"]
# [inline (always)]
pub const fn reserved4 (& self) -> & Reserved4 { & self . reserved4 } # [doc = "0x50 - Reserved"]
# [inline (always)]
pub const fn reserved5 (& self) -> & Reserved5 { & self . reserved5 } # [doc = "0x54 - Reserved"]
# [inline (always)]
pub const fn reserved6 (& self) -> & Reserved6 { & self . reserved6 } # [doc = "0x58 - Reserved"]
# [inline (always)]
pub const fn reserved7 (& self) -> & Reserved7 { & self . reserved7 } # [doc = "0x5c - Reserved"]
# [inline (always)]
pub const fn reserved8 (& self) -> & Reserved8 { & self . reserved8 } # [doc = "0x60 - Digital Compare Trip Select Register/ Digital Compare A Control Register"]
# [inline (always)]
pub const fn dctripsel_dcactl (& self) -> & DctripselDcactl { & self . dctripsel_dcactl } # [doc = "0x64 - Digital Compare B Control Register/ Digital Compare Filter Control Register"]
# [inline (always)]
pub const fn dcbctl_dcfctl (& self) -> & DcbctlDcfctl { & self . dcbctl_dcfctl } # [doc = "0x68 - Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"]
# [inline (always)]
pub const fn dccapctl_dcfoffset (& self) -> & DccapctlDcfoffset { & self . dccapctl_dcfoffset } # [doc = "0x6c - Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"]
# [inline (always)]
pub const fn dcfoffsetcnt_dcfwindow (& self) -> & DcfoffsetcntDcfwindow { & self . dcfoffsetcnt_dcfwindow } # [doc = "0x70 - Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"]
# [inline (always)]
pub const fn dcfwindowcnt_dccap (& self) -> & DcfwindowcntDccap { & self . dcfwindowcnt_dccap } } # [doc = "TBCTL_TBSTS (rw) register accessor: Time-Base Control Register/ Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbctl_tbsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbctl_tbsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tbctl_tbsts`]
module"]
# [doc (alias = "TBCTL_TBSTS")]
pub type TbctlTbsts = crate :: Reg < tbctl_tbsts :: TbctlTbstsSpec > ; # [doc = "Time-Base Control Register/ Status Register"]
pub mod tbctl_tbsts { # [doc = "Register `TBCTL_TBSTS` reader"]
pub type R = crate :: R < TbctlTbstsSpec > ; # [doc = "Register `TBCTL_TBSTS` writer"]
pub type W = crate :: W < TbctlTbstsSpec > ; # [doc = "Field `TBCTL_CTRMODE` reader - 1:0\\]
Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0 Up-count mode 1h Down-count mode 2h Up-down-count mode 3h Stop-freeze counter operation (default on reset)"]
pub type TbctlCtrmodeR = crate :: FieldReader ; # [doc = "Field `TBCTL_CTRMODE` writer - 1:0\\]
Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0 Up-count mode 1h Down-count mode 2h Up-down-count mode 3h Stop-freeze counter operation (default on reset)"]
pub type TbctlCtrmodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TBCTL_PHSEN` reader - 2:2\\]
Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit, or when a digital compare sync event occurs."]
pub type TbctlPhsenR = crate :: BitReader ; # [doc = "Field `TBCTL_PHSEN` writer - 2:2\\]
Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit, or when a digital compare sync event occurs."]
pub type TbctlPhsenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TBCTL_PRDLD` reader - 3:3\\]
Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero. A write or read to the TBPRD register accesses the shadow register. 1 Load the TBPRD register immediately without using a shadow register. A write or read to the TBPRD register directly accesses the active register."]
pub type TbctlPrdldR = crate :: BitReader ; # [doc = "Field `TBCTL_PRDLD` writer - 3:3\\]
Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero. A write or read to the TBPRD register accesses the shadow register. 1 Load the TBPRD register immediately without using a shadow register. A write or read to the TBPRD register directly accesses the active register."]
pub type TbctlPrdldW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TBCTL_SYNCOSEL` reader - 5:4\\]
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) 3h Disable EPWMxSYNCO signal"]
pub type TbctlSyncoselR = crate :: FieldReader ; # [doc = "Field `TBCTL_SYNCOSEL` writer - 5:4\\]
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) 3h Disable EPWMxSYNCO signal"]
pub type TbctlSyncoselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TBCTL_SWFSYNC` reader - 6:6\\]
Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00."]
pub type TbctlSwfsyncR = crate :: BitReader ; # [doc = "Field `TBCTL_SWFSYNC` writer - 6:6\\]
Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00."]
pub type TbctlSwfsyncW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TBCTL_HSPCLKDIV` reader - 9:7\\]
High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14"]
pub type TbctlHspclkdivR = crate :: FieldReader ; # [doc = "Field `TBCTL_HSPCLKDIV` writer - 9:7\\]
High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14"]
pub type TbctlHspclkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TBCTL_CLKDIV` reader - 12:10\\]
Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128"]
pub type TbctlClkdivR = crate :: FieldReader ; # [doc = "Field `TBCTL_CLKDIV` writer - 12:10\\]
Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128"]
pub type TbctlClkdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TBCTL_PHSDIR` reader - 13:13\\]
Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register. This is irrespective of the direction of the counter before the synchronization event.. In the up-count and down-count modes this bit is ignored. 0 Count down after the synchronization event. 1 Count up after the synchronization event"]
pub type TbctlPhsdirR = crate :: BitReader ; # [doc = "Field `TBCTL_PHSDIR` writer - 13:13\\]
Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register. This is irrespective of the direction of the counter before the synchronization event.. In the up-count and down-count modes this bit is ignored. 0 Count down after the synchronization event. 1 Count up after the synchronization event"]
pub type TbctlPhsdirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TBCTL_FREE_SOFT` reader - 15:14\\]
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: ΓÇó Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD) ΓÇó Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) ΓÇó Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) 2h-3h Free run"]
pub type TbctlFreeSoftR = crate :: FieldReader ; # [doc = "Field `TBCTL_FREE_SOFT` writer - 15:14\\]
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: ΓÇó Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD) ΓÇó Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) ΓÇó Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) 2h-3h Free run"]
pub type TbctlFreeSoftW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TBSTS_CTRDIR` reader - 16:16\\]
Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL\\[CTRMODE\\]. 0 Time-Base Counter is currently counting down. 1 Time-Base Counter is currently counting up."]
pub type TbstsCtrdirR = crate :: BitReader ; # [doc = "Field `TBSTS_CTRDIR` writer - 16:16\\]
Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL\\[CTRMODE\\]. 0 Time-Base Counter is currently counting down. 1 Time-Base Counter is currently counting up."]
pub type TbstsCtrdirW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TBSTS_SYNCI` reader - 17:17\\]
Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event."]
pub type TbstsSynciR = crate :: BitReader ; # [doc = "Field `TBSTS_SYNCI` writer - 17:17\\]
Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event."]
pub type TbstsSynciW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TBSTS_CTRMAX` reader - 18:18\\]
Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event."]
pub type TbstsCtrmaxR = crate :: BitReader ; # [doc = "Field `TBSTS_CTRMAX` writer - 18:18\\]
Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event."]
pub type TbstsCtrmaxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0 Up-count mode 1h Down-count mode 2h Up-down-count mode 3h Stop-freeze counter operation (default on reset)"]
# [inline (always)]
pub fn tbctl_ctrmode (& self) -> TbctlCtrmodeR { TbctlCtrmodeR :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - 2:2\\]
Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit, or when a digital compare sync event occurs."]
# [inline (always)]
pub fn tbctl_phsen (& self) -> TbctlPhsenR { TbctlPhsenR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero. A write or read to the TBPRD register accesses the shadow register. 1 Load the TBPRD register immediately without using a shadow register. A write or read to the TBPRD register directly accesses the active register."]
# [inline (always)]
pub fn tbctl_prdld (& self) -> TbctlPrdldR { TbctlPrdldR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - 5:4\\]
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) 3h Disable EPWMxSYNCO signal"]
# [inline (always)]
pub fn tbctl_syncosel (& self) -> TbctlSyncoselR { TbctlSyncoselR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - 6:6\\]
Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00."]
# [inline (always)]
pub fn tbctl_swfsync (& self) -> TbctlSwfsyncR { TbctlSwfsyncR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:9 - 9:7\\]
High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14"]
# [inline (always)]
pub fn tbctl_hspclkdiv (& self) -> TbctlHspclkdivR { TbctlHspclkdivR :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - 12:10\\]
Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128"]
# [inline (always)]
pub fn tbctl_clkdiv (& self) -> TbctlClkdivR { TbctlClkdivR :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bit 13 - 13:13\\]
Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register. This is irrespective of the direction of the counter before the synchronization event.. In the up-count and down-count modes this bit is ignored. 0 Count down after the synchronization event. 1 Count up after the synchronization event"]
# [inline (always)]
pub fn tbctl_phsdir (& self) -> TbctlPhsdirR { TbctlPhsdirR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:15 - 15:14\\]
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: ΓÇó Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD) ΓÇó Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) ΓÇó Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) 2h-3h Free run"]
# [inline (always)]
pub fn tbctl_free_soft (& self) -> TbctlFreeSoftR { TbctlFreeSoftR :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - 16:16\\]
Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL\\[CTRMODE\\]. 0 Time-Base Counter is currently counting down. 1 Time-Base Counter is currently counting up."]
# [inline (always)]
pub fn tbsts_ctrdir (& self) -> TbstsCtrdirR { TbstsCtrdirR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event."]
# [inline (always)]
pub fn tbsts_synci (& self) -> TbstsSynciR { TbstsSynciR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event."]
# [inline (always)]
pub fn tbsts_ctrmax (& self) -> TbstsCtrmaxR { TbstsCtrmaxR :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0 Up-count mode 1h Down-count mode 2h Up-down-count mode 3h Stop-freeze counter operation (default on reset)"]
# [inline (always)]
# [must_use]
pub fn tbctl_ctrmode (& mut self) -> TbctlCtrmodeW < TbctlTbstsSpec > { TbctlCtrmodeW :: new (self , 0) } # [doc = "Bit 2 - 2:2\\]
Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit, or when a digital compare sync event occurs."]
# [inline (always)]
# [must_use]
pub fn tbctl_phsen (& mut self) -> TbctlPhsenW < TbctlTbstsSpec > { TbctlPhsenW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero. A write or read to the TBPRD register accesses the shadow register. 1 Load the TBPRD register immediately without using a shadow register. A write or read to the TBPRD register directly accesses the active register."]
# [inline (always)]
# [must_use]
pub fn tbctl_prdld (& mut self) -> TbctlPrdldW < TbctlTbstsSpec > { TbctlPrdldW :: new (self , 3) } # [doc = "Bits 4:5 - 5:4\\]
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) 3h Disable EPWMxSYNCO signal"]
# [inline (always)]
# [must_use]
pub fn tbctl_syncosel (& mut self) -> TbctlSyncoselW < TbctlTbstsSpec > { TbctlSyncoselW :: new (self , 4) } # [doc = "Bit 6 - 6:6\\]
Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00."]
# [inline (always)]
# [must_use]
pub fn tbctl_swfsync (& mut self) -> TbctlSwfsyncW < TbctlTbstsSpec > { TbctlSwfsyncW :: new (self , 6) } # [doc = "Bits 7:9 - 9:7\\]
High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14"]
# [inline (always)]
# [must_use]
pub fn tbctl_hspclkdiv (& mut self) -> TbctlHspclkdivW < TbctlTbstsSpec > { TbctlHspclkdivW :: new (self , 7) } # [doc = "Bits 10:12 - 12:10\\]
Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128"]
# [inline (always)]
# [must_use]
pub fn tbctl_clkdiv (& mut self) -> TbctlClkdivW < TbctlTbstsSpec > { TbctlClkdivW :: new (self , 10) } # [doc = "Bit 13 - 13:13\\]
Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register. This is irrespective of the direction of the counter before the synchronization event.. In the up-count and down-count modes this bit is ignored. 0 Count down after the synchronization event. 1 Count up after the synchronization event"]
# [inline (always)]
# [must_use]
pub fn tbctl_phsdir (& mut self) -> TbctlPhsdirW < TbctlTbstsSpec > { TbctlPhsdirW :: new (self , 13) } # [doc = "Bits 14:15 - 15:14\\]
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: ΓÇó Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD) ΓÇó Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) ΓÇó Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) 2h-3h Free run"]
# [inline (always)]
# [must_use]
pub fn tbctl_free_soft (& mut self) -> TbctlFreeSoftW < TbctlTbstsSpec > { TbctlFreeSoftW :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL\\[CTRMODE\\]. 0 Time-Base Counter is currently counting down. 1 Time-Base Counter is currently counting up."]
# [inline (always)]
# [must_use]
pub fn tbsts_ctrdir (& mut self) -> TbstsCtrdirW < TbctlTbstsSpec > { TbstsCtrdirW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event."]
# [inline (always)]
# [must_use]
pub fn tbsts_synci (& mut self) -> TbstsSynciW < TbctlTbstsSpec > { TbstsSynciW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event."]
# [inline (always)]
# [must_use]
pub fn tbsts_ctrmax (& mut self) -> TbstsCtrmaxW < TbctlTbstsSpec > { TbstsCtrmaxW :: new (self , 18) } } # [doc = "Time-Base Control Register/ Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbctl_tbsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbctl_tbsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TbctlTbstsSpec ; impl crate :: RegisterSpec for TbctlTbstsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tbctl_tbsts::R`](R) reader structure"]
impl crate :: Readable for TbctlTbstsSpec { } # [doc = "`write(|w| ..)` method takes [`tbctl_tbsts::W`](W) writer structure"]
impl crate :: Writable for TbctlTbstsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TBCTL_TBSTS to value 0"]
impl crate :: Resettable for TbctlTbstsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TBPHS (rw) register accessor: Time-Base Phase Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbphs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbphs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tbphs`]
module"]
# [doc (alias = "TBPHS")]
pub type Tbphs = crate :: Reg < tbphs :: TbphsSpec > ; # [doc = "Time-Base Phase Register"]
pub mod tbphs { # [doc = "Register `TBPHS` reader"]
pub type R = crate :: R < TbphsSpec > ; # [doc = "Register `TBPHS` writer"]
pub type W = crate :: W < TbphsSpec > ; # [doc = "Field `TBPHS` reader - 31:16\\]
Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. ΓÇó If TBCTL\\[PHSEN\\]
= 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase. ΓÇó If TBCTL\\[PHSEN\\]
= 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization."]
pub type TbphsR = crate :: FieldReader < u16 > ; # [doc = "Field `TBPHS` writer - 31:16\\]
Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. ΓÇó If TBCTL\\[PHSEN\\]
= 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase. ΓÇó If TBCTL\\[PHSEN\\]
= 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization."]
pub type TbphsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 16:31 - 31:16\\]
Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. ΓÇó If TBCTL\\[PHSEN\\]
= 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase. ΓÇó If TBCTL\\[PHSEN\\]
= 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization."]
# [inline (always)]
pub fn tbphs (& self) -> TbphsR { TbphsR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 16:31 - 31:16\\]
Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. ΓÇó If TBCTL\\[PHSEN\\]
= 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase. ΓÇó If TBCTL\\[PHSEN\\]
= 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization."]
# [inline (always)]
# [must_use]
pub fn tbphs (& mut self) -> TbphsW < TbphsSpec > { TbphsW :: new (self , 16) } } # [doc = "Time-Base Phase Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbphs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbphs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TbphsSpec ; impl crate :: RegisterSpec for TbphsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tbphs::R`](R) reader structure"]
impl crate :: Readable for TbphsSpec { } # [doc = "`write(|w| ..)` method takes [`tbphs::W`](W) writer structure"]
impl crate :: Writable for TbphsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TBPHS to value 0"]
impl crate :: Resettable for TbphsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TBCTR_TBPRD (rw) register accessor: Time-Base Counter Register/ Period Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbctr_tbprd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbctr_tbprd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tbctr_tbprd`]
module"]
# [doc (alias = "TBCTR_TBPRD")]
pub type TbctrTbprd = crate :: Reg < tbctr_tbprd :: TbctrTbprdSpec > ; # [doc = "Time-Base Counter Register/ Period Register"]
pub mod tbctr_tbprd { # [doc = "Register `TBCTR_TBPRD` reader"]
pub type R = crate :: R < TbctrTbprdSpec > ; # [doc = "Register `TBCTR_TBPRD` writer"]
pub type W = crate :: W < TbctrTbprdSpec > ; # [doc = "Field `TBCTR` reader - 15:0\\]
Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed."]
pub type TbctrR = crate :: FieldReader < u16 > ; # [doc = "Field `TBCTR` writer - 15:0\\]
Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed."]
pub type TbctrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `TBPRD` reader - 31:16\\]
Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL\\[PRDLD\\]
bit. By default this register is shadowed. ΓÇó If TBCTL\\[PRDLD\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the active register will be loaded from the shadow register when the timebase counter equals zero. ΓÇó If TBCTL\\[PRDLD\\]
= 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó The active and shadow registers share the same memory map address."]
pub type TbprdR = crate :: FieldReader < u16 > ; # [doc = "Field `TBPRD` writer - 31:16\\]
Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL\\[PRDLD\\]
bit. By default this register is shadowed. ΓÇó If TBCTL\\[PRDLD\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the active register will be loaded from the shadow register when the timebase counter equals zero. ΓÇó If TBCTL\\[PRDLD\\]
= 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó The active and shadow registers share the same memory map address."]
pub type TbprdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed."]
# [inline (always)]
pub fn tbctr (& self) -> TbctrR { TbctrR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL\\[PRDLD\\]
bit. By default this register is shadowed. ΓÇó If TBCTL\\[PRDLD\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the active register will be loaded from the shadow register when the timebase counter equals zero. ΓÇó If TBCTL\\[PRDLD\\]
= 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó The active and shadow registers share the same memory map address."]
# [inline (always)]
pub fn tbprd (& self) -> TbprdR { TbprdR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed."]
# [inline (always)]
# [must_use]
pub fn tbctr (& mut self) -> TbctrW < TbctrTbprdSpec > { TbctrW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL\\[PRDLD\\]
bit. By default this register is shadowed. ΓÇó If TBCTL\\[PRDLD\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the active register will be loaded from the shadow register when the timebase counter equals zero. ΓÇó If TBCTL\\[PRDLD\\]
= 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó The active and shadow registers share the same memory map address."]
# [inline (always)]
# [must_use]
pub fn tbprd (& mut self) -> TbprdW < TbctrTbprdSpec > { TbprdW :: new (self , 16) } } # [doc = "Time-Base Counter Register/ Period Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbctr_tbprd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbctr_tbprd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TbctrTbprdSpec ; impl crate :: RegisterSpec for TbctrTbprdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tbctr_tbprd::R`](R) reader structure"]
impl crate :: Readable for TbctrTbprdSpec { } # [doc = "`write(|w| ..)` method takes [`tbctr_tbprd::W`](W) writer structure"]
impl crate :: Writable for TbctrTbprdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TBCTR_TBPRD to value 0"]
impl crate :: Resettable for TbctrTbprdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMPCTL (rw) register accessor: Counter-Compare Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpctl`]
module"]
# [doc (alias = "CMPCTL")]
pub type Cmpctl = crate :: Reg < cmpctl :: CmpctlSpec > ; # [doc = "Counter-Compare Control Register"]
pub mod cmpctl { # [doc = "Register `CMPCTL` reader"]
pub type R = crate :: R < CmpctlSpec > ; # [doc = "Register `CMPCTL` writer"]
pub type W = crate :: W < CmpctlSpec > ; # [doc = "Field `Reserved1` reader - 15:0\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 15:0\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `LOADAMODE` reader - 17:16\\]
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL\\[SHDWAMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
pub type LoadamodeR = crate :: FieldReader ; # [doc = "Field `LOADAMODE` writer - 17:16\\]
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL\\[SHDWAMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
pub type LoadamodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `LOADBMODE` reader - 19:18\\]
Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL\\[SHDWBMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
pub type LoadbmodeR = crate :: FieldReader ; # [doc = "Field `LOADBMODE` writer - 19:18\\]
Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL\\[SHDWBMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
pub type LoadbmodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SHDWAMODE` reader - 20:20\\]
Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action"]
pub type ShdwamodeR = crate :: BitReader ; # [doc = "Field `SHDWAMODE` writer - 20:20\\]
Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action"]
pub type ShdwamodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 21:21\\]
Reserved"]
pub type Reserved2R = crate :: BitReader ; # [doc = "Field `Reserved2` writer - 21:21\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHDWBMODE` reader - 22:22\\]
Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action."]
pub type ShdwbmodeR = crate :: BitReader ; # [doc = "Field `SHDWBMODE` writer - 22:22\\]
Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action."]
pub type ShdwbmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 23:23\\]
Reserved"]
pub type Reserved3R = crate :: BitReader ; # [doc = "Field `Reserved3` writer - 23:23\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHDWAFULL` reader - 24:24\\]
Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs. 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value"]
pub type ShdwafullR = crate :: BitReader ; # [doc = "Field `SHDWAFULL` writer - 24:24\\]
Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs. 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value"]
pub type ShdwafullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SHDWBFULL` reader - 25:25\\]
Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value."]
pub type ShdwbfullR = crate :: BitReader ; # [doc = "Field `SHDWBFULL` writer - 25:25\\]
Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value."]
pub type ShdwbfullW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 31:26\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 31:26\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:17 - 17:16\\]
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL\\[SHDWAMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
# [inline (always)]
pub fn loadamode (& self) -> LoadamodeR { LoadamodeR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - 19:18\\]
Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL\\[SHDWBMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
# [inline (always)]
pub fn loadbmode (& self) -> LoadbmodeR { LoadbmodeR :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bit 20 - 20:20\\]
Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action"]
# [inline (always)]
pub fn shdwamode (& self) -> ShdwamodeR { ShdwamodeR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action."]
# [inline (always)]
pub fn shdwbmode (& self) -> ShdwbmodeR { ShdwbmodeR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs. 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value"]
# [inline (always)]
pub fn shdwafull (& self) -> ShdwafullR { ShdwafullR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value."]
# [inline (always)]
pub fn shdwbfull (& self) -> ShdwbfullR { ShdwbfullR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < CmpctlSpec > { Reserved1W :: new (self , 0) } # [doc = "Bits 16:17 - 17:16\\]
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL\\[SHDWAMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
# [inline (always)]
# [must_use]
pub fn loadamode (& mut self) -> LoadamodeW < CmpctlSpec > { LoadamodeW :: new (self , 16) } # [doc = "Bits 18:19 - 19:18\\]
Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL\\[SHDWBMODE\\]
= 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible)"]
# [inline (always)]
# [must_use]
pub fn loadbmode (& mut self) -> LoadbmodeW < CmpctlSpec > { LoadbmodeW :: new (self , 18) } # [doc = "Bit 20 - 20:20\\]
Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action"]
# [inline (always)]
# [must_use]
pub fn shdwamode (& mut self) -> ShdwamodeW < CmpctlSpec > { ShdwamodeW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < CmpctlSpec > { Reserved2W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action."]
# [inline (always)]
# [must_use]
pub fn shdwbmode (& mut self) -> ShdwbmodeW < CmpctlSpec > { ShdwbmodeW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < CmpctlSpec > { Reserved3W :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs. 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value"]
# [inline (always)]
# [must_use]
pub fn shdwafull (& mut self) -> ShdwafullW < CmpctlSpec > { ShdwafullW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value."]
# [inline (always)]
# [must_use]
pub fn shdwbfull (& mut self) -> ShdwbfullW < CmpctlSpec > { ShdwbfullW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < CmpctlSpec > { Reserved4W :: new (self , 26) } } # [doc = "Counter-Compare Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpctlSpec ; impl crate :: RegisterSpec for CmpctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmpctl::R`](R) reader structure"]
impl crate :: Readable for CmpctlSpec { } # [doc = "`write(|w| ..)` method takes [`cmpctl::W`](W) writer structure"]
impl crate :: Writable for CmpctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMPCTL to value 0"]
impl crate :: Resettable for CmpctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMPA (rw) register accessor: Counter-Compare A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpa`]
module"]
# [doc (alias = "CMPA")]
pub type Cmpa = crate :: Reg < cmpa :: CmpaSpec > ; # [doc = "Counter-Compare A Register"]
pub mod cmpa { # [doc = "Register `CMPA` reader"]
pub type R = crate :: R < CmpaSpec > ; # [doc = "Register `CMPA` writer"]
pub type W = crate :: W < CmpaSpec > ; # [doc = "Field `CMPA` reader - 31:16\\]
Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare A\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing; the event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWAMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADAMODE\\]
bit field determines which event will load the active register from the shadow register. ΓÇó Before a write, the CMPCTL\\[SHDWAFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address."]
pub type CmpaR = crate :: FieldReader < u16 > ; # [doc = "Field `CMPA` writer - 31:16\\]
Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare A\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing; the event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWAMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADAMODE\\]
bit field determines which event will load the active register from the shadow register. ΓÇó Before a write, the CMPCTL\\[SHDWAFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address."]
pub type CmpaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 16:31 - 31:16\\]
Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare A\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing; the event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWAMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADAMODE\\]
bit field determines which event will load the active register from the shadow register. ΓÇó Before a write, the CMPCTL\\[SHDWAFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address."]
# [inline (always)]
pub fn cmpa (& self) -> CmpaR { CmpaR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 16:31 - 31:16\\]
Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare A\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing; the event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWAMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADAMODE\\]
bit field determines which event will load the active register from the shadow register. ΓÇó Before a write, the CMPCTL\\[SHDWAFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWAMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address."]
# [inline (always)]
# [must_use]
pub fn cmpa (& mut self) -> CmpaW < CmpaSpec > { CmpaW :: new (self , 16) } } # [doc = "Counter-Compare A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpaSpec ; impl crate :: RegisterSpec for CmpaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmpa::R`](R) reader structure"]
impl crate :: Readable for CmpaSpec { } # [doc = "`write(|w| ..)` method takes [`cmpa::W`](W) writer structure"]
impl crate :: Writable for CmpaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMPA to value 0"]
impl crate :: Resettable for CmpaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CMPB_AQCTLA (rw) register accessor: Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpb_aqctla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpb_aqctla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpb_aqctla`]
module"]
# [doc (alias = "CMPB_AQCTLA")]
pub type CmpbAqctla = crate :: Reg < cmpb_aqctla :: CmpbAqctlaSpec > ; # [doc = "Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"]
pub mod cmpb_aqctla { # [doc = "Register `CMPB_AQCTLA` reader"]
pub type R = crate :: R < CmpbAqctlaSpec > ; # [doc = "Register `CMPB_AQCTLA` writer"]
pub type W = crate :: W < CmpbAqctlaSpec > ; # [doc = "Field `CMPB` reader - 15:0\\]
The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare B\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing. event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWBMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADBMODE\\]
bit field determines which event will load the active register from the shadow register: ΓÇó Before a write, the CMPCTL\\[SHDWBFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address"]
pub type CmpbR = crate :: FieldReader < u16 > ; # [doc = "Field `CMPB` writer - 15:0\\]
The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare B\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing. event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWBMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADBMODE\\]
bit field determines which event will load the active register from the shadow register: ΓÇó Before a write, the CMPCTL\\[SHDWBFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address"]
pub type CmpbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `AQCTLA_ZRO` reader - 17:16\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaZroR = crate :: FieldReader ; # [doc = "Field `AQCTLA_ZRO` writer - 17:16\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaZroW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLA_PRD` reader - 19:18\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaPrdR = crate :: FieldReader ; # [doc = "Field `AQCTLA_PRD` writer - 19:18\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaPrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLA_CAU` reader - 21:20\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCauR = crate :: FieldReader ; # [doc = "Field `AQCTLA_CAU` writer - 21:20\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCauW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLA_CAD` reader - 23:22\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCadR = crate :: FieldReader ; # [doc = "Field `AQCTLA_CAD` writer - 23:22\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCadW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLA_CBU` reader - 25:24\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCbuR = crate :: FieldReader ; # [doc = "Field `AQCTLA_CBU` writer - 25:24\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCbuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLA_CBD` reader - 27:26\\]
Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCbdR = crate :: FieldReader ; # [doc = "Field `AQCTLA_CBD` writer - 27:26\\]
Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlaCbdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare B\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing. event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWBMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADBMODE\\]
bit field determines which event will load the active register from the shadow register: ΓÇó Before a write, the CMPCTL\\[SHDWBFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address"]
# [inline (always)]
pub fn cmpb (& self) -> CmpbR { CmpbR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:17 - 17:16\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctla_zro (& self) -> AqctlaZroR { AqctlaZroR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - 19:18\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctla_prd (& self) -> AqctlaPrdR { AqctlaPrdR :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - 21:20\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctla_cau (& self) -> AqctlaCauR { AqctlaCauR :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - 23:22\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctla_cad (& self) -> AqctlaCadR { AqctlaCadR :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - 25:24\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctla_cbu (& self) -> AqctlaCbuR { AqctlaCbuR :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - 27:26\\]
Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctla_cbd (& self) -> AqctlaCbdR { AqctlaCbdR :: new (((self . bits >> 26) & 3) as u8) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a \"time-base counter equal to counter compare B\" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: ΓÇó Do nothing. event is ignored. ΓÇó Clear: Pull the EPWMxA and/or EPWMxB signal low ΓÇó Set: Pull the EPWMxA and/or EPWMxB signal high ΓÇó Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL\\[SHDWBMODE\\]
bit. By default this register is shadowed. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL\\[LOADBMODE\\]
bit field determines which event will load the active register from the shadow register: ΓÇó Before a write, the CMPCTL\\[SHDWBFULL\\]
bit can be read to determine if the shadow register is currently full. ΓÇó If CMPCTL\\[SHDWBMODE\\]
= 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. ΓÇó In either mode, the active and shadow registers share the same memory map address"]
# [inline (always)]
# [must_use]
pub fn cmpb (& mut self) -> CmpbW < CmpbAqctlaSpec > { CmpbW :: new (self , 0) } # [doc = "Bits 16:17 - 17:16\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctla_zro (& mut self) -> AqctlaZroW < CmpbAqctlaSpec > { AqctlaZroW :: new (self , 16) } # [doc = "Bits 18:19 - 19:18\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctla_prd (& mut self) -> AqctlaPrdW < CmpbAqctlaSpec > { AqctlaPrdW :: new (self , 18) } # [doc = "Bits 20:21 - 21:20\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctla_cau (& mut self) -> AqctlaCauW < CmpbAqctlaSpec > { AqctlaCauW :: new (self , 20) } # [doc = "Bits 22:23 - 23:22\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctla_cad (& mut self) -> AqctlaCadW < CmpbAqctlaSpec > { AqctlaCadW :: new (self , 22) } # [doc = "Bits 24:25 - 25:24\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctla_cbu (& mut self) -> AqctlaCbuW < CmpbAqctlaSpec > { AqctlaCbuW :: new (self , 24) } # [doc = "Bits 26:27 - 27:26\\]
Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctla_cbd (& mut self) -> AqctlaCbdW < CmpbAqctlaSpec > { AqctlaCbdW :: new (self , 26) } } # [doc = "Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpb_aqctla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpb_aqctla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpbAqctlaSpec ; impl crate :: RegisterSpec for CmpbAqctlaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cmpb_aqctla::R`](R) reader structure"]
impl crate :: Readable for CmpbAqctlaSpec { } # [doc = "`write(|w| ..)` method takes [`cmpb_aqctla::W`](W) writer structure"]
impl crate :: Writable for CmpbAqctlaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CMPB_AQCTLA to value 0"]
impl crate :: Resettable for CmpbAqctlaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AQCTLB_AQSFRC (rw) register accessor: Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aqctlb_aqsfrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aqctlb_aqsfrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aqctlb_aqsfrc`]
module"]
# [doc (alias = "AQCTLB_AQSFRC")]
pub type AqctlbAqsfrc = crate :: Reg < aqctlb_aqsfrc :: AqctlbAqsfrcSpec > ; # [doc = "Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"]
pub mod aqctlb_aqsfrc { # [doc = "Register `AQCTLB_AQSFRC` reader"]
pub type R = crate :: R < AqctlbAqsfrcSpec > ; # [doc = "Register `AQCTLB_AQSFRC` writer"]
pub type W = crate :: W < AqctlbAqsfrcSpec > ; # [doc = "Field `AQCTLB_ZRO` reader - 1:0\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low."]
pub type AqctlbZroR = crate :: FieldReader ; # [doc = "Field `AQCTLB_ZRO` writer - 1:0\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low."]
pub type AqctlbZroW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLB_PRD` reader - 3:2\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbPrdR = crate :: FieldReader ; # [doc = "Field `AQCTLB_PRD` writer - 3:2\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbPrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLB_CAU` reader - 5:4\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCauR = crate :: FieldReader ; # [doc = "Field `AQCTLB_CAU` writer - 5:4\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCauW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLB_CAD` reader - 7:6\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCadR = crate :: FieldReader ; # [doc = "Field `AQCTLB_CAD` writer - 7:6\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCadW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLB_CBU` reader - 9:8\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCbuR = crate :: FieldReader ; # [doc = "Field `AQCTLB_CBU` writer - 9:8\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCbuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCTLB_CBD` reader - 11:10\\]
Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCbdR = crate :: FieldReader ; # [doc = "Field `AQCTLB_CBD` writer - 11:10\\]
Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
pub type AqctlbCbdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved2` reader - 15:12\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 15:12\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `AQSFRC_ACTSFA` reader - 17:16\\]
Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir)"]
pub type AqsfrcActsfaR = crate :: FieldReader ; # [doc = "Field `AQSFRC_ACTSFA` writer - 17:16\\]
Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir)"]
pub type AqsfrcActsfaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQSFRC_OTSFA` reader - 18:18\\]
One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 1 Initiates a single software forced event"]
pub type AqsfrcOtsfaR = crate :: BitReader ; # [doc = "Field `AQSFRC_OTSFA` writer - 18:18\\]
One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 1 Initiates a single software forced event"]
pub type AqsfrcOtsfaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AQSFRC_ACTSFB` reader - 20:19\\]
Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir)"]
pub type AqsfrcActsfbR = crate :: FieldReader ; # [doc = "Field `AQSFRC_ACTSFB` writer - 20:19\\]
Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir)"]
pub type AqsfrcActsfbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQSFRC_OTSFB` reader - 21:21\\]
One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated.) This is a one-shot forced event. It can be overridden by another subsequent event on output B. 1 Initiates a single s/w forced event"]
pub type AqsfrcOtsfbR = crate :: BitReader ; # [doc = "Field `AQSFRC_OTSFB` writer - 21:21\\]
One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated.) This is a one-shot forced event. It can be overridden by another subsequent event on output B. 1 Initiates a single s/w forced event"]
pub type AqsfrcOtsfbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AQSFRC_RLDCSF` reader - 23:22\\]
AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)."]
pub type AqsfrcRldcsfR = crate :: FieldReader ; # [doc = "Field `AQSFRC_RLDCSF` writer - 23:22\\]
AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)."]
pub type AqsfrcRldcsfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low."]
# [inline (always)]
pub fn aqctlb_zro (& self) -> AqctlbZroR { AqctlbZroR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctlb_prd (& self) -> AqctlbPrdR { AqctlbPrdR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctlb_cau (& self) -> AqctlbCauR { AqctlbCauR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctlb_cad (& self) -> AqctlbCadR { AqctlbCadR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctlb_cbu (& self) -> AqctlbCbuR { AqctlbCbuR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
pub fn aqctlb_cbd (& self) -> AqctlbCbdR { AqctlbCbdR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:17 - 17:16\\]
Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir)"]
# [inline (always)]
pub fn aqsfrc_actsfa (& self) -> AqsfrcActsfaR { AqsfrcActsfaR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 1 Initiates a single software forced event"]
# [inline (always)]
pub fn aqsfrc_otsfa (& self) -> AqsfrcOtsfaR { AqsfrcOtsfaR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:20 - 20:19\\]
Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir)"]
# [inline (always)]
pub fn aqsfrc_actsfb (& self) -> AqsfrcActsfbR { AqsfrcActsfbR :: new (((self . bits >> 19) & 3) as u8) } # [doc = "Bit 21 - 21:21\\]
One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated.) This is a one-shot forced event. It can be overridden by another subsequent event on output B. 1 Initiates a single s/w forced event"]
# [inline (always)]
pub fn aqsfrc_otsfb (& self) -> AqsfrcOtsfbR { AqsfrcOtsfbR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bits 22:23 - 23:22\\]
AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)."]
# [inline (always)]
pub fn aqsfrc_rldcsf (& self) -> AqsfrcRldcsfR { AqsfrcRldcsfR :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low."]
# [inline (always)]
# [must_use]
pub fn aqctlb_zro (& mut self) -> AqctlbZroW < AqctlbAqsfrcSpec > { AqctlbZroW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctlb_prd (& mut self) -> AqctlbPrdW < AqctlbAqsfrcSpec > { AqctlbPrdW :: new (self , 2) } # [doc = "Bits 4:5 - 5:4\\]
Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctlb_cau (& mut self) -> AqctlbCauW < AqctlbAqsfrcSpec > { AqctlbCauW :: new (self , 4) } # [doc = "Bits 6:7 - 7:6\\]
Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctlb_cad (& mut self) -> AqctlbCadW < AqctlbAqsfrcSpec > { AqctlbCadW :: new (self , 6) } # [doc = "Bits 8:9 - 9:8\\]
Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctlb_cbu (& mut self) -> AqctlbCbuW < AqctlbAqsfrcSpec > { AqctlbCbuW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low"]
# [inline (always)]
# [must_use]
pub fn aqctlb_cbd (& mut self) -> AqctlbCbdW < AqctlbAqsfrcSpec > { AqctlbCbdW :: new (self , 10) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < AqctlbAqsfrcSpec > { Reserved2W :: new (self , 12) } # [doc = "Bits 16:17 - 17:16\\]
Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir)"]
# [inline (always)]
# [must_use]
pub fn aqsfrc_actsfa (& mut self) -> AqsfrcActsfaW < AqctlbAqsfrcSpec > { AqsfrcActsfaW :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 1 Initiates a single software forced event"]
# [inline (always)]
# [must_use]
pub fn aqsfrc_otsfa (& mut self) -> AqsfrcOtsfaW < AqctlbAqsfrcSpec > { AqsfrcOtsfaW :: new (self , 18) } # [doc = "Bits 19:20 - 20:19\\]
Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir)"]
# [inline (always)]
# [must_use]
pub fn aqsfrc_actsfb (& mut self) -> AqsfrcActsfbW < AqctlbAqsfrcSpec > { AqsfrcActsfbW :: new (self , 19) } # [doc = "Bit 21 - 21:21\\]
One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated.) This is a one-shot forced event. It can be overridden by another subsequent event on output B. 1 Initiates a single s/w forced event"]
# [inline (always)]
# [must_use]
pub fn aqsfrc_otsfb (& mut self) -> AqsfrcOtsfbW < AqctlbAqsfrcSpec > { AqsfrcOtsfbW :: new (self , 21) } # [doc = "Bits 22:23 - 23:22\\]
AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)."]
# [inline (always)]
# [must_use]
pub fn aqsfrc_rldcsf (& mut self) -> AqsfrcRldcsfW < AqctlbAqsfrcSpec > { AqsfrcRldcsfW :: new (self , 22) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < AqctlbAqsfrcSpec > { Reserved1W :: new (self , 24) } } # [doc = "Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register\n\nYou can [`read`](crate::Reg::read) this register and get [`aqctlb_aqsfrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aqctlb_aqsfrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AqctlbAqsfrcSpec ; impl crate :: RegisterSpec for AqctlbAqsfrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aqctlb_aqsfrc::R`](R) reader structure"]
impl crate :: Readable for AqctlbAqsfrcSpec { } # [doc = "`write(|w| ..)` method takes [`aqctlb_aqsfrc::W`](W) writer structure"]
impl crate :: Writable for AqctlbAqsfrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AQCTLB_AQSFRC to value 0"]
impl crate :: Resettable for AqctlbAqsfrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "AQCSFRC_DBCTL (rw) register accessor: Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set\n\nYou can [`read`](crate::Reg::read) this register and get [`aqcsfrc_dbctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aqcsfrc_dbctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aqcsfrc_dbctl`]
module"]
# [doc (alias = "AQCSFRC_DBCTL")]
pub type AqcsfrcDbctl = crate :: Reg < aqcsfrc_dbctl :: AqcsfrcDbctlSpec > ; # [doc = "Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"]
pub mod aqcsfrc_dbctl { # [doc = "Register `AQCSFRC_DBCTL` reader"]
pub type R = crate :: R < AqcsfrcDbctlSpec > ; # [doc = "Register `AQCSFRC_DBCTL` writer"]
pub type W = crate :: W < AqcsfrcDbctlSpec > ; # [doc = "Field `AQCSFRC_CSFA` reader - 1:0\\]
Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output A 2h Forces a continuous high on output A 3h Software forcing is disabled and has no effect"]
pub type AqcsfrcCsfaR = crate :: FieldReader ; # [doc = "Field `AQCSFRC_CSFA` writer - 1:0\\]
Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output A 2h Forces a continuous high on output A 3h Software forcing is disabled and has no effect"]
pub type AqcsfrcCsfaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `AQCSFRC_CSFB` reader - 3:2\\]
Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC\\[RLDCSF\\]. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect"]
pub type AqcsfrcCsfbR = crate :: FieldReader ; # [doc = "Field `AQCSFRC_CSFB` writer - 3:2\\]
Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC\\[RLDCSF\\]. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect"]
pub type AqcsfrcCsfbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved2` reader - 15:4\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved2` writer - 15:4\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `DBCTL_OUT_MODE` reader - 17:16\\]
Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 1h Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. 2h The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. 3h Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]."]
pub type DbctlOutModeR = crate :: FieldReader ; # [doc = "Field `DBCTL_OUT_MODE` writer - 17:16\\]
Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 1h Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. 2h The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. 3h Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]."]
pub type DbctlOutModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBCTL_POLSEL` reader - 19:18\\]
Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL\\[OUT_MODE\\]
= 1,1 and DBCTL\\[IN_MODE\\]
= 0,0. Other enhanced modes are also possible, but not regarded as typical usage modes. 0 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 1h Active low complementary (ALC) mode. EPWMxA is inverted. 2h Active high complementary (AHC). EPWMxB is inverted. 3h Active low (AL) mode. Both EPWMxA and EPWMxB are inverted"]
pub type DbctlPolselR = crate :: FieldReader ; # [doc = "Field `DBCTL_POLSEL` writer - 19:18\\]
Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL\\[OUT_MODE\\]
= 1,1 and DBCTL\\[IN_MODE\\]
= 0,0. Other enhanced modes are also possible, but not regarded as typical usage modes. 0 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 1h Active low complementary (ALC) mode. EPWMxA is inverted. 2h Active high complementary (AHC). EPWMxB is inverted. 3h Active low (AL) mode. Both EPWMxA and EPWMxB are inverted"]
pub type DbctlPolselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBCTL_IN_MODE` reader - 21:20\\]
Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays. 0 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 1h EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 2h EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 3h EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal."]
pub type DbctlInModeR = crate :: FieldReader ; # [doc = "Field `DBCTL_IN_MODE` writer - 21:20\\]
Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays. 0 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 1h EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 2h EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 3h EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal."]
pub type DbctlInModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 30:22\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 30:22\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `DBCTL_HALFCYCLE` reader - 31:31\\]
Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK � 2."]
pub type DbctlHalfcycleR = crate :: BitReader ; # [doc = "Field `DBCTL_HALFCYCLE` writer - 31:31\\]
Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK � 2."]
pub type DbctlHalfcycleW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output A 2h Forces a continuous high on output A 3h Software forcing is disabled and has no effect"]
# [inline (always)]
pub fn aqcsfrc_csfa (& self) -> AqcsfrcCsfaR { AqcsfrcCsfaR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC\\[RLDCSF\\]. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect"]
# [inline (always)]
pub fn aqcsfrc_csfb (& self) -> AqcsfrcCsfbR { AqcsfrcCsfbR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:15 - 15:4\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bits 16:17 - 17:16\\]
Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 1h Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. 2h The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. 3h Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]."]
# [inline (always)]
pub fn dbctl_out_mode (& self) -> DbctlOutModeR { DbctlOutModeR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - 19:18\\]
Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL\\[OUT_MODE\\]
= 1,1 and DBCTL\\[IN_MODE\\]
= 0,0. Other enhanced modes are also possible, but not regarded as typical usage modes. 0 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 1h Active low complementary (ALC) mode. EPWMxA is inverted. 2h Active high complementary (AHC). EPWMxB is inverted. 3h Active low (AL) mode. Both EPWMxA and EPWMxB are inverted"]
# [inline (always)]
pub fn dbctl_polsel (& self) -> DbctlPolselR { DbctlPolselR :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - 21:20\\]
Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays. 0 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 1h EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 2h EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 3h EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal."]
# [inline (always)]
pub fn dbctl_in_mode (& self) -> DbctlInModeR { DbctlInModeR :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:30 - 30:22\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 22) & 0x01ff) as u16) } # [doc = "Bit 31 - 31:31\\]
Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK � 2."]
# [inline (always)]
pub fn dbctl_halfcycle (& self) -> DbctlHalfcycleR { DbctlHalfcycleR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output A 2h Forces a continuous high on output A 3h Software forcing is disabled and has no effect"]
# [inline (always)]
# [must_use]
pub fn aqcsfrc_csfa (& mut self) -> AqcsfrcCsfaW < AqcsfrcDbctlSpec > { AqcsfrcCsfaW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC\\[RLDCSF\\]. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect"]
# [inline (always)]
# [must_use]
pub fn aqcsfrc_csfb (& mut self) -> AqcsfrcCsfbW < AqcsfrcDbctlSpec > { AqcsfrcCsfbW :: new (self , 2) } # [doc = "Bits 4:15 - 15:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < AqcsfrcDbctlSpec > { Reserved2W :: new (self , 4) } # [doc = "Bits 16:17 - 17:16\\]
Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 1h Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. 2h The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]. Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. 3h Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL\\[IN_MODE\\]."]
# [inline (always)]
# [must_use]
pub fn dbctl_out_mode (& mut self) -> DbctlOutModeW < AqcsfrcDbctlSpec > { DbctlOutModeW :: new (self , 16) } # [doc = "Bits 18:19 - 19:18\\]
Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL\\[OUT_MODE\\]
= 1,1 and DBCTL\\[IN_MODE\\]
= 0,0. Other enhanced modes are also possible, but not regarded as typical usage modes. 0 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 1h Active low complementary (ALC) mode. EPWMxA is inverted. 2h Active high complementary (AHC). EPWMxB is inverted. 3h Active low (AL) mode. Both EPWMxA and EPWMxB are inverted"]
# [inline (always)]
# [must_use]
pub fn dbctl_polsel (& mut self) -> DbctlPolselW < AqcsfrcDbctlSpec > { DbctlPolselW :: new (self , 18) } # [doc = "Bits 20:21 - 21:20\\]
Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays. 0 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 1h EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 2h EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 3h EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal."]
# [inline (always)]
# [must_use]
pub fn dbctl_in_mode (& mut self) -> DbctlInModeW < AqcsfrcDbctlSpec > { DbctlInModeW :: new (self , 20) } # [doc = "Bits 22:30 - 30:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < AqcsfrcDbctlSpec > { Reserved1W :: new (self , 22) } # [doc = "Bit 31 - 31:31\\]
Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK � 2."]
# [inline (always)]
# [must_use]
pub fn dbctl_halfcycle (& mut self) -> DbctlHalfcycleW < AqcsfrcDbctlSpec > { DbctlHalfcycleW :: new (self , 31) } } # [doc = "Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set\n\nYou can [`read`](crate::Reg::read) this register and get [`aqcsfrc_dbctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aqcsfrc_dbctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AqcsfrcDbctlSpec ; impl crate :: RegisterSpec for AqcsfrcDbctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`aqcsfrc_dbctl::R`](R) reader structure"]
impl crate :: Readable for AqcsfrcDbctlSpec { } # [doc = "`write(|w| ..)` method takes [`aqcsfrc_dbctl::W`](W) writer structure"]
impl crate :: Writable for AqcsfrcDbctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AQCSFRC_DBCTL to value 0"]
impl crate :: Resettable for AqcsfrcDbctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DBRED_DBFED (rw) register accessor: Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dbred_dbfed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbred_dbfed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbred_dbfed`]
module"]
# [doc (alias = "DBRED_DBFED")]
pub type DbredDbfed = crate :: Reg < dbred_dbfed :: DbredDbfedSpec > ; # [doc = "Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"]
pub mod dbred_dbfed { # [doc = "Register `DBRED_DBFED` reader"]
pub type R = crate :: R < DbredDbfedSpec > ; # [doc = "Register `DBRED_DBFED` writer"]
pub type W = crate :: W < DbredDbfedSpec > ; # [doc = "Field `DBRED_DEL` reader - 9:0\\]
Rising Edge Delay Count. 10-bit counter"]
pub type DbredDelR = crate :: FieldReader < u16 > ; # [doc = "Field `DBRED_DEL` writer - 9:0\\]
Rising Edge Delay Count. 10-bit counter"]
pub type DbredDelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `Reserved2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `DBFED_DEL` reader - 25:16\\]
Falling Edge Delay Count. 10-bit counter"]
pub type DbfedDelR = crate :: FieldReader < u16 > ; # [doc = "Field `DBFED_DEL` writer - 25:16\\]
Falling Edge Delay Count. 10-bit counter"]
pub type DbfedDelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; # [doc = "Field `Reserved1` reader - 31:26\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:26\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:9 - 9:0\\]
Rising Edge Delay Count. 10-bit counter"]
# [inline (always)]
pub fn dbred_del (& self) -> DbredDelR { DbredDelR :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bits 16:25 - 25:16\\]
Falling Edge Delay Count. 10-bit counter"]
# [inline (always)]
pub fn dbfed_del (& self) -> DbfedDelR { DbfedDelR :: new (((self . bits >> 16) & 0x03ff) as u16) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:9 - 9:0\\]
Rising Edge Delay Count. 10-bit counter"]
# [inline (always)]
# [must_use]
pub fn dbred_del (& mut self) -> DbredDelW < DbredDbfedSpec > { DbredDelW :: new (self , 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < DbredDbfedSpec > { Reserved2W :: new (self , 10) } # [doc = "Bits 16:25 - 25:16\\]
Falling Edge Delay Count. 10-bit counter"]
# [inline (always)]
# [must_use]
pub fn dbfed_del (& mut self) -> DbfedDelW < DbredDbfedSpec > { DbfedDelW :: new (self , 16) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < DbredDbfedSpec > { Reserved1W :: new (self , 26) } } # [doc = "Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dbred_dbfed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbred_dbfed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbredDbfedSpec ; impl crate :: RegisterSpec for DbredDbfedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dbred_dbfed::R`](R) reader structure"]
impl crate :: Readable for DbredDbfedSpec { } # [doc = "`write(|w| ..)` method takes [`dbred_dbfed::W`](W) writer structure"]
impl crate :: Writable for DbredDbfedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DBRED_DBFED to value 0"]
impl crate :: Resettable for DbredDbfedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TZSEL_TZDCSEL (rw) register accessor: Trip Zone Digital Compare Select Register/ Trip-Zone Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzsel_tzdcsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzsel_tzdcsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tzsel_tzdcsel`]
module"]
# [doc (alias = "TZSEL_TZDCSEL")]
pub type TzselTzdcsel = crate :: Reg < tzsel_tzdcsel :: TzselTzdcselSpec > ; # [doc = "Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"]
pub mod tzsel_tzdcsel { # [doc = "Register `TZSEL_TZDCSEL` reader"]
pub type R = crate :: R < TzselTzdcselSpec > ; # [doc = "Register `TZSEL_TZDCSEL` writer"]
pub type W = crate :: W < TzselTzdcselSpec > ; # [doc = "Field `TZSEL_CBC1` reader - 0:0\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module"]
pub type TzselCbc1R = crate :: BitReader ; # [doc = "Field `TZSEL_CBC1` writer - 0:0\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module"]
pub type TzselCbc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_CBC2` reader - 1:1\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module"]
pub type TzselCbc2R = crate :: BitReader ; # [doc = "Field `TZSEL_CBC2` writer - 1:1\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module"]
pub type TzselCbc2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_CBC3` reader - 2:2\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module"]
pub type TzselCbc3R = crate :: BitReader ; # [doc = "Field `TZSEL_CBC3` writer - 2:2\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module"]
pub type TzselCbc3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_CBC4` reader - 3:3\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module"]
pub type TzselCbc4R = crate :: BitReader ; # [doc = "Field `TZSEL_CBC4` writer - 3:3\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module"]
pub type TzselCbc4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_CBC5` reader - 4:4\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module"]
pub type TzselCbc5R = crate :: BitReader ; # [doc = "Field `TZSEL_CBC5` writer - 4:4\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module"]
pub type TzselCbc5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_CBC6` reader - 5:5\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module"]
pub type TzselCbc6R = crate :: BitReader ; # [doc = "Field `TZSEL_CBC6` writer - 5:5\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module"]
pub type TzselCbc6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_DCAEVT2` reader - 6:6\\]
Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module"]
pub type TzselDcaevt2R = crate :: BitReader ; # [doc = "Field `TZSEL_DCAEVT2` writer - 6:6\\]
Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module"]
pub type TzselDcaevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_DCBEVT2` reader - 7:7\\]
Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module"]
pub type TzselDcbevt2R = crate :: BitReader ; # [doc = "Field `TZSEL_DCBEVT2` writer - 7:7\\]
Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module"]
pub type TzselDcbevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_OSHT1` reader - 8:8\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module"]
pub type TzselOsht1R = crate :: BitReader ; # [doc = "Field `TZSEL_OSHT1` writer - 8:8\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module"]
pub type TzselOsht1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_OSHT2` reader - 9:9\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module"]
pub type TzselOsht2R = crate :: BitReader ; # [doc = "Field `TZSEL_OSHT2` writer - 9:9\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module"]
pub type TzselOsht2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_OSHT3` reader - 10:10\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module"]
pub type TzselOsht3R = crate :: BitReader ; # [doc = "Field `TZSEL_OSHT3` writer - 10:10\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module"]
pub type TzselOsht3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_OSHT4` reader - 11:11\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module"]
pub type TzselOsht4R = crate :: BitReader ; # [doc = "Field `TZSEL_OSHT4` writer - 11:11\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module"]
pub type TzselOsht4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_OSHT5` reader - 12:12\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module"]
pub type TzselOsht5R = crate :: BitReader ; # [doc = "Field `TZSEL_OSHT5` writer - 12:12\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module"]
pub type TzselOsht5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_OSHT6` reader - 13:13\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module"]
pub type TzselOsht6R = crate :: BitReader ; # [doc = "Field `TZSEL_OSHT6` writer - 13:13\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module"]
pub type TzselOsht6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_DCAEVT1` reader - 14:14\\]
Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module"]
pub type TzselDcaevt1R = crate :: BitReader ; # [doc = "Field `TZSEL_DCAEVT1` writer - 14:14\\]
Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module"]
pub type TzselDcaevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZSEL_DCBEVT1` reader - 15:15\\]
Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module"]
pub type TzselDcbevt1R = crate :: BitReader ; # [doc = "Field `TZSEL_DCBEVT1` writer - 15:15\\]
Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module"]
pub type TzselDcbevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZDCSEL_DCAEVT1` reader - 18:16\\]
Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
pub type TzdcselDcaevt1R = crate :: FieldReader ; # [doc = "Field `TZDCSEL_DCAEVT1` writer - 18:16\\]
Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
pub type TzdcselDcaevt1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TZDCSEL_DCAEVT2` reader - 21:19\\]
Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
pub type TzdcselDcaevt2R = crate :: FieldReader ; # [doc = "Field `TZDCSEL_DCAEVT2` writer - 21:19\\]
Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
pub type TzdcselDcaevt2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TZDCSEL_DCBEVT1` reader - 24:22\\]
Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
pub type TzdcselDcbevt1R = crate :: FieldReader ; # [doc = "Field `TZDCSEL_DCBEVT1` writer - 24:22\\]
Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
pub type TzdcselDcbevt1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TZDCSEL_DCBEVT2` reader - 27:25\\]
Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
pub type TzdcselDcbevt2R = crate :: FieldReader ; # [doc = "Field `TZDCSEL_DCBEVT2` writer - 27:25\\]
Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
pub type TzdcselDcbevt2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `Reserved1` reader - 31:28\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:28\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_cbc1 (& self) -> TzselCbc1R { TzselCbc1R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_cbc2 (& self) -> TzselCbc2R { TzselCbc2R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_cbc3 (& self) -> TzselCbc3R { TzselCbc3R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_cbc4 (& self) -> TzselCbc4R { TzselCbc4R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_cbc5 (& self) -> TzselCbc5R { TzselCbc5R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_cbc6 (& self) -> TzselCbc6R { TzselCbc6R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_dcaevt2 (& self) -> TzselDcaevt2R { TzselDcaevt2R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_dcbevt2 (& self) -> TzselDcbevt2R { TzselDcbevt2R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_osht1 (& self) -> TzselOsht1R { TzselOsht1R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_osht2 (& self) -> TzselOsht2R { TzselOsht2R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_osht3 (& self) -> TzselOsht3R { TzselOsht3R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_osht4 (& self) -> TzselOsht4R { TzselOsht4R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_osht5 (& self) -> TzselOsht5R { TzselOsht5R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_osht6 (& self) -> TzselOsht6R { TzselOsht6R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_dcaevt1 (& self) -> TzselDcaevt1R { TzselDcaevt1R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module"]
# [inline (always)]
pub fn tzsel_dcbevt1 (& self) -> TzselDcbevt1R { TzselDcbevt1R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
# [inline (always)]
pub fn tzdcsel_dcaevt1 (& self) -> TzdcselDcaevt1R { TzdcselDcaevt1R :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bits 19:21 - 21:19\\]
Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
# [inline (always)]
pub fn tzdcsel_dcaevt2 (& self) -> TzdcselDcaevt2R { TzdcselDcaevt2R :: new (((self . bits >> 19) & 7) as u8) } # [doc = "Bits 22:24 - 24:22\\]
Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
# [inline (always)]
pub fn tzdcsel_dcbevt1 (& self) -> TzdcselDcbevt1R { TzdcselDcbevt1R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 25:27 - 27:25\\]
Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
# [inline (always)]
pub fn tzdcsel_dcbevt2 (& self) -> TzdcselDcbevt2R { TzdcselDcbevt2R :: new (((self . bits >> 25) & 7) as u8) } # [doc = "Bits 28:31 - 31:28\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_cbc1 (& mut self) -> TzselCbc1W < TzselTzdcselSpec > { TzselCbc1W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_cbc2 (& mut self) -> TzselCbc2W < TzselTzdcselSpec > { TzselCbc2W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_cbc3 (& mut self) -> TzselCbc3W < TzselTzdcselSpec > { TzselCbc3W :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_cbc4 (& mut self) -> TzselCbc4W < TzselTzdcselSpec > { TzselCbc4W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_cbc5 (& mut self) -> TzselCbc5W < TzselTzdcselSpec > { TzselCbc5W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_cbc6 (& mut self) -> TzselCbc6W < TzselTzdcselSpec > { TzselCbc6W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_dcaevt2 (& mut self) -> TzselDcaevt2W < TzselTzdcselSpec > { TzselDcaevt2W :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_dcbevt2 (& mut self) -> TzselDcbevt2W < TzselTzdcselSpec > { TzselDcbevt2W :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_osht1 (& mut self) -> TzselOsht1W < TzselTzdcselSpec > { TzselOsht1W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_osht2 (& mut self) -> TzselOsht2W < TzselTzdcselSpec > { TzselOsht2W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_osht3 (& mut self) -> TzselOsht3W < TzselTzdcselSpec > { TzselOsht3W :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_osht4 (& mut self) -> TzselOsht4W < TzselTzdcselSpec > { TzselOsht4W :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_osht5 (& mut self) -> TzselOsht5W < TzselTzdcselSpec > { TzselOsht5W :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_osht6 (& mut self) -> TzselOsht6W < TzselTzdcselSpec > { TzselOsht6W :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_dcaevt1 (& mut self) -> TzselDcaevt1W < TzselTzdcselSpec > { TzselDcaevt1W :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module"]
# [inline (always)]
# [must_use]
pub fn tzsel_dcbevt1 (& mut self) -> TzselDcbevt1W < TzselTzdcselSpec > { TzselDcbevt1W :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
# [inline (always)]
# [must_use]
pub fn tzdcsel_dcaevt1 (& mut self) -> TzdcselDcaevt1W < TzselTzdcselSpec > { TzdcselDcaevt1W :: new (self , 16) } # [doc = "Bits 19:21 - 21:19\\]
Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved"]
# [inline (always)]
# [must_use]
pub fn tzdcsel_dcaevt2 (& mut self) -> TzdcselDcaevt2W < TzselTzdcselSpec > { TzdcselDcaevt2W :: new (self , 19) } # [doc = "Bits 22:24 - 24:22\\]
Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
# [inline (always)]
# [must_use]
pub fn tzdcsel_dcbevt1 (& mut self) -> TzdcselDcbevt1W < TzselTzdcselSpec > { TzdcselDcbevt1W :: new (self , 22) } # [doc = "Bits 25:27 - 27:25\\]
Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved"]
# [inline (always)]
# [must_use]
pub fn tzdcsel_dcbevt2 (& mut self) -> TzdcselDcbevt2W < TzselTzdcselSpec > { TzdcselDcbevt2W :: new (self , 25) } # [doc = "Bits 28:31 - 31:28\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < TzselTzdcselSpec > { Reserved1W :: new (self , 28) } } # [doc = "Trip Zone Digital Compare Select Register/ Trip-Zone Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzsel_tzdcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzsel_tzdcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TzselTzdcselSpec ; impl crate :: RegisterSpec for TzselTzdcselSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tzsel_tzdcsel::R`](R) reader structure"]
impl crate :: Readable for TzselTzdcselSpec { } # [doc = "`write(|w| ..)` method takes [`tzsel_tzdcsel::W`](W) writer structure"]
impl crate :: Writable for TzselTzdcselSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TZSEL_TZDCSEL to value 0"]
impl crate :: Resettable for TzselTzdcselSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TZCTL_TZEINT (rw) register accessor: Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzctl_tzeint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzctl_tzeint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tzctl_tzeint`]
module"]
# [doc (alias = "TZCTL_TZEINT")]
pub type TzctlTzeint = crate :: Reg < tzctl_tzeint :: TzctlTzeintSpec > ; # [doc = "Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"]
pub mod tzctl_tzeint { # [doc = "Register `TZCTL_TZEINT` reader"]
pub type R = crate :: R < TzctlTzeintSpec > ; # [doc = "Register `TZCTL_TZEINT` writer"]
pub type W = crate :: W < TzctlTzeintSpec > ; # [doc = "Field `TZCTL_TZA` reader - 1:0\\]
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing, no action is taken on EPWMxA"]
pub type TzctlTzaR = crate :: FieldReader ; # [doc = "Field `TZCTL_TZA` writer - 1:0\\]
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing, no action is taken on EPWMxA"]
pub type TzctlTzaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TZCTL_TZB` reader - 3:2\\]
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB to a low state 3h Do nothing, no action is taken on EPWMxB."]
pub type TzctlTzbR = crate :: FieldReader ; # [doc = "Field `TZCTL_TZB` writer - 3:2\\]
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB to a low state 3h Do nothing, no action is taken on EPWMxB."]
pub type TzctlTzbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TZCTL_DCAEVT1` reader - 5:4\\]
Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcaevt1R = crate :: FieldReader ; # [doc = "Field `TZCTL_DCAEVT1` writer - 5:4\\]
Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcaevt1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TZCTL_DCAEVT2` reader - 7:6\\]
Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcaevt2R = crate :: FieldReader ; # [doc = "Field `TZCTL_DCAEVT2` writer - 7:6\\]
Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcaevt2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TZCTL_DCBEVT1` reader - 9:8\\]
Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcbevt1R = crate :: FieldReader ; # [doc = "Field `TZCTL_DCBEVT1` writer - 9:8\\]
Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcbevt1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TZCTL_DCBEVT2` reader - 11:10\\]
Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcbevt2R = crate :: FieldReader ; # [doc = "Field `TZCTL_DCBEVT2` writer - 11:10\\]
Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
pub type TzctlDcbevt2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 15:12\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:12\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `Reserved2` reader - 16:16\\]
Reserved"]
pub type Reserved2R = crate :: BitReader ; # [doc = "Field `Reserved2` writer - 16:16\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZEINT_CBC` reader - 17:17\\]
Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt"]
pub type TzeintCbcR = crate :: BitReader ; # [doc = "Field `TZEINT_CBC` writer - 17:17\\]
Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt"]
pub type TzeintCbcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZEINT_OST` reader - 18:18\\]
Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt"]
pub type TzeintOstR = crate :: BitReader ; # [doc = "Field `TZEINT_OST` writer - 18:18\\]
Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt"]
pub type TzeintOstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZEINT_DCAEVT1` reader - 19:19\\]
Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcaevt1R = crate :: BitReader ; # [doc = "Field `TZEINT_DCAEVT1` writer - 19:19\\]
Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcaevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZEINT_DCAEVT2` reader - 20:20\\]
Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcaevt2R = crate :: BitReader ; # [doc = "Field `TZEINT_DCAEVT2` writer - 20:20\\]
Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcaevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZEINT_DCBEVT1` reader - 21:21\\]
Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcbevt1R = crate :: BitReader ; # [doc = "Field `TZEINT_DCBEVT1` writer - 21:21\\]
Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcbevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZEINT_DCBEVT2` reader - 22:22\\]
Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcbevt2R = crate :: BitReader ; # [doc = "Field `TZEINT_DCBEVT2` writer - 22:22\\]
Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
pub type TzeintDcbevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 31:23\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved3` writer - 31:23\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing, no action is taken on EPWMxA"]
# [inline (always)]
pub fn tzctl_tza (& self) -> TzctlTzaR { TzctlTzaR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB to a low state 3h Do nothing, no action is taken on EPWMxB."]
# [inline (always)]
pub fn tzctl_tzb (& self) -> TzctlTzbR { TzctlTzbR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
pub fn tzctl_dcaevt1 (& self) -> TzctlDcaevt1R { TzctlDcaevt1R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
pub fn tzctl_dcaevt2 (& self) -> TzctlDcaevt2R { TzctlDcaevt2R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
pub fn tzctl_dcbevt1 (& self) -> TzctlDcbevt1R { TzctlDcbevt1R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
pub fn tzctl_dcbevt2 (& self) -> TzctlDcbevt2R { TzctlDcbevt2R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt"]
# [inline (always)]
pub fn tzeint_cbc (& self) -> TzeintCbcR { TzeintCbcR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt"]
# [inline (always)]
pub fn tzeint_ost (& self) -> TzeintOstR { TzeintOstR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
pub fn tzeint_dcaevt1 (& self) -> TzeintDcaevt1R { TzeintDcaevt1R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
pub fn tzeint_dcaevt2 (& self) -> TzeintDcaevt2R { TzeintDcaevt2R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
pub fn tzeint_dcbevt1 (& self) -> TzeintDcbevt1R { TzeintDcbevt1R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
pub fn tzeint_dcbevt2 (& self) -> TzeintDcbevt2R { TzeintDcbevt2R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 23) & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing, no action is taken on EPWMxA"]
# [inline (always)]
# [must_use]
pub fn tzctl_tza (& mut self) -> TzctlTzaW < TzctlTzeintSpec > { TzctlTzaW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB to a low state 3h Do nothing, no action is taken on EPWMxB."]
# [inline (always)]
# [must_use]
pub fn tzctl_tzb (& mut self) -> TzctlTzbW < TzctlTzeintSpec > { TzctlTzbW :: new (self , 2) } # [doc = "Bits 4:5 - 5:4\\]
Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
# [must_use]
pub fn tzctl_dcaevt1 (& mut self) -> TzctlDcaevt1W < TzctlTzeintSpec > { TzctlDcaevt1W :: new (self , 4) } # [doc = "Bits 6:7 - 7:6\\]
Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
# [must_use]
pub fn tzctl_dcaevt2 (& mut self) -> TzctlDcaevt2W < TzctlTzeintSpec > { TzctlDcaevt2W :: new (self , 6) } # [doc = "Bits 8:9 - 9:8\\]
Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
# [must_use]
pub fn tzctl_dcbevt1 (& mut self) -> TzctlDcbevt1W < TzctlTzeintSpec > { TzctlDcbevt1W :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled"]
# [inline (always)]
# [must_use]
pub fn tzctl_dcbevt2 (& mut self) -> TzctlDcbevt2W < TzctlTzeintSpec > { TzctlDcbevt2W :: new (self , 10) } # [doc = "Bits 12:15 - 15:12\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < TzctlTzeintSpec > { Reserved1W :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < TzctlTzeintSpec > { Reserved2W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt"]
# [inline (always)]
# [must_use]
pub fn tzeint_cbc (& mut self) -> TzeintCbcW < TzctlTzeintSpec > { TzeintCbcW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt"]
# [inline (always)]
# [must_use]
pub fn tzeint_ost (& mut self) -> TzeintOstW < TzctlTzeintSpec > { TzeintOstW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
# [must_use]
pub fn tzeint_dcaevt1 (& mut self) -> TzeintDcaevt1W < TzctlTzeintSpec > { TzeintDcaevt1W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
# [must_use]
pub fn tzeint_dcaevt2 (& mut self) -> TzeintDcaevt2W < TzctlTzeintSpec > { TzeintDcaevt2W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
# [must_use]
pub fn tzeint_dcbevt1 (& mut self) -> TzeintDcbevt1W < TzctlTzeintSpec > { TzeintDcbevt1W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled"]
# [inline (always)]
# [must_use]
pub fn tzeint_dcbevt2 (& mut self) -> TzeintDcbevt2W < TzctlTzeintSpec > { TzeintDcbevt2W :: new (self , 22) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < TzctlTzeintSpec > { Reserved3W :: new (self , 23) } } # [doc = "Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzctl_tzeint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzctl_tzeint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TzctlTzeintSpec ; impl crate :: RegisterSpec for TzctlTzeintSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tzctl_tzeint::R`](R) reader structure"]
impl crate :: Readable for TzctlTzeintSpec { } # [doc = "`write(|w| ..)` method takes [`tzctl_tzeint::W`](W) writer structure"]
impl crate :: Writable for TzctlTzeintSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TZCTL_TZEINT to value 0"]
impl crate :: Resettable for TzctlTzeintSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TZFLG_TZCLR (rw) register accessor: Trip-Zone Flag Register/ Trip-Zone Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzflg_tzclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzflg_tzclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tzflg_tzclr`]
module"]
# [doc (alias = "TZFLG_TZCLR")]
pub type TzflgTzclr = crate :: Reg < tzflg_tzclr :: TzflgTzclrSpec > ; # [doc = "Trip-Zone Flag Register/ Trip-Zone Clear Register"]
pub mod tzflg_tzclr { # [doc = "Register `TZFLG_TZCLR` reader"]
pub type R = crate :: R < TzflgTzclrSpec > ; # [doc = "Register `TZFLG_TZCLR` writer"]
pub type W = crate :: W < TzflgTzclrSpec > ; # [doc = "Field `TZFLG_INT` reader - 0:0\\]
Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register"]
pub type TzflgIntR = crate :: BitReader ; # [doc = "Field `TZFLG_INT` writer - 0:0\\]
Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register"]
pub type TzflgIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFLG_CBC` reader - 1:1\\]
Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG\\[CBC\\]
bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the TZCLR register"]
pub type TzflgCbcR = crate :: BitReader ; # [doc = "Field `TZFLG_CBC` writer - 1:1\\]
Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG\\[CBC\\]
bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the TZCLR register"]
pub type TzflgCbcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFLG_OST` reader - 2:2\\]
Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register"]
pub type TzflgOstR = crate :: BitReader ; # [doc = "Field `TZFLG_OST` writer - 2:2\\]
Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register"]
pub type TzflgOstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFLG_DCAEVT1` reader - 3:3\\]
Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1"]
pub type TzflgDcaevt1R = crate :: BitReader ; # [doc = "Field `TZFLG_DCAEVT1` writer - 3:3\\]
Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1"]
pub type TzflgDcaevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFLG_DCAEVT2` reader - 4:4\\]
Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2"]
pub type TzflgDcaevt2R = crate :: BitReader ; # [doc = "Field `TZFLG_DCAEVT2` writer - 4:4\\]
Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2"]
pub type TzflgDcaevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFLG_DCBEVT1` reader - 5:5\\]
Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1"]
pub type TzflgDcbevt1R = crate :: BitReader ; # [doc = "Field `TZFLG_DCBEVT1` writer - 5:5\\]
Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1"]
pub type TzflgDcbevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFLG_DCBEVT2` reader - 6:6\\]
Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2"]
pub type TzflgDcbevt2R = crate :: BitReader ; # [doc = "Field `TZFLG_DCBEVT2` writer - 6:6\\]
Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2"]
pub type TzflgDcbevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 15:7\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved2` writer - 15:7\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `TZCLR_INT` reader - 16:16\\]
Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG\\[INT\\]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG\\[INT\\]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts."]
pub type TzclrIntR = crate :: BitReader ; # [doc = "Field `TZCLR_INT` writer - 16:16\\]
Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG\\[INT\\]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG\\[INT\\]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts."]
pub type TzclrIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZCLR_CBC` reader - 17:17\\]
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
pub type TzclrCbcR = crate :: BitReader ; # [doc = "Field `TZCLR_CBC` writer - 17:17\\]
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
pub type TzclrCbcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZCLR_OST` reader - 18:18\\]
Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
pub type TzclrOstR = crate :: BitReader ; # [doc = "Field `TZCLR_OST` writer - 18:18\\]
Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
pub type TzclrOstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZCLR_DCAEVT1` reader - 19:19\\]
Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition."]
pub type TzclrDcaevt1R = crate :: BitReader ; # [doc = "Field `TZCLR_DCAEVT1` writer - 19:19\\]
Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition."]
pub type TzclrDcaevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZCLR_DCAEVT2` reader - 20:20\\]
Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition"]
pub type TzclrDcaevt2R = crate :: BitReader ; # [doc = "Field `TZCLR_DCAEVT2` writer - 20:20\\]
Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition"]
pub type TzclrDcaevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZCLR_DCBEVT1` reader - 21:21\\]
Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition"]
pub type TzclrDcbevt1R = crate :: BitReader ; # [doc = "Field `TZCLR_DCBEVT1` writer - 21:21\\]
Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition"]
pub type TzclrDcbevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZCLR_DCBEVT2` reader - 22:22\\]
Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition."]
pub type TzclrDcbevt2R = crate :: BitReader ; # [doc = "Field `TZCLR_DCBEVT2` writer - 22:22\\]
Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition."]
pub type TzclrDcbevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 31:23\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 31:23\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register"]
# [inline (always)]
pub fn tzflg_int (& self) -> TzflgIntR { TzflgIntR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG\\[CBC\\]
bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the TZCLR register"]
# [inline (always)]
pub fn tzflg_cbc (& self) -> TzflgCbcR { TzflgCbcR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register"]
# [inline (always)]
pub fn tzflg_ost (& self) -> TzflgOstR { TzflgOstR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1"]
# [inline (always)]
pub fn tzflg_dcaevt1 (& self) -> TzflgDcaevt1R { TzflgDcaevt1R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2"]
# [inline (always)]
pub fn tzflg_dcaevt2 (& self) -> TzflgDcaevt2R { TzflgDcaevt2R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1"]
# [inline (always)]
pub fn tzflg_dcbevt1 (& self) -> TzflgDcbevt1R { TzflgDcbevt1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2"]
# [inline (always)]
pub fn tzflg_dcbevt2 (& self) -> TzflgDcbevt2R { TzflgDcbevt2R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:15 - 15:7\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 7) & 0x01ff) as u16) } # [doc = "Bit 16 - 16:16\\]
Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG\\[INT\\]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG\\[INT\\]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts."]
# [inline (always)]
pub fn tzclr_int (& self) -> TzclrIntR { TzclrIntR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
# [inline (always)]
pub fn tzclr_cbc (& self) -> TzclrCbcR { TzclrCbcR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
# [inline (always)]
pub fn tzclr_ost (& self) -> TzclrOstR { TzclrOstR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition."]
# [inline (always)]
pub fn tzclr_dcaevt1 (& self) -> TzclrDcaevt1R { TzclrDcaevt1R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition"]
# [inline (always)]
pub fn tzclr_dcaevt2 (& self) -> TzclrDcaevt2R { TzclrDcaevt2R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition"]
# [inline (always)]
pub fn tzclr_dcbevt1 (& self) -> TzclrDcbevt1R { TzclrDcbevt1R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition."]
# [inline (always)]
pub fn tzclr_dcbevt2 (& self) -> TzclrDcbevt2R { TzclrDcbevt2R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 23) & 0x01ff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register"]
# [inline (always)]
# [must_use]
pub fn tzflg_int (& mut self) -> TzflgIntW < TzflgTzclrSpec > { TzflgIntW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG\\[CBC\\]
bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the TZCLR register"]
# [inline (always)]
# [must_use]
pub fn tzflg_cbc (& mut self) -> TzflgCbcW < TzflgTzclrSpec > { TzflgCbcW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register"]
# [inline (always)]
# [must_use]
pub fn tzflg_ost (& mut self) -> TzflgOstW < TzflgTzclrSpec > { TzflgOstW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1"]
# [inline (always)]
# [must_use]
pub fn tzflg_dcaevt1 (& mut self) -> TzflgDcaevt1W < TzflgTzclrSpec > { TzflgDcaevt1W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2"]
# [inline (always)]
# [must_use]
pub fn tzflg_dcaevt2 (& mut self) -> TzflgDcaevt2W < TzflgTzclrSpec > { TzflgDcaevt2W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1"]
# [inline (always)]
# [must_use]
pub fn tzflg_dcbevt1 (& mut self) -> TzflgDcbevt1W < TzflgTzclrSpec > { TzflgDcbevt1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2"]
# [inline (always)]
# [must_use]
pub fn tzflg_dcbevt2 (& mut self) -> TzflgDcbevt2W < TzflgTzclrSpec > { TzflgDcbevt2W :: new (self , 6) } # [doc = "Bits 7:15 - 15:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < TzflgTzclrSpec > { Reserved2W :: new (self , 7) } # [doc = "Bit 16 - 16:16\\]
Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG\\[INT\\]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG\\[INT\\]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts."]
# [inline (always)]
# [must_use]
pub fn tzclr_int (& mut self) -> TzclrIntW < TzflgTzclrSpec > { TzclrIntW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
# [inline (always)]
# [must_use]
pub fn tzclr_cbc (& mut self) -> TzclrCbcW < TzflgTzclrSpec > { TzclrCbcW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition."]
# [inline (always)]
# [must_use]
pub fn tzclr_ost (& mut self) -> TzclrOstW < TzflgTzclrSpec > { TzclrOstW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition."]
# [inline (always)]
# [must_use]
pub fn tzclr_dcaevt1 (& mut self) -> TzclrDcaevt1W < TzflgTzclrSpec > { TzclrDcaevt1W :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition"]
# [inline (always)]
# [must_use]
pub fn tzclr_dcaevt2 (& mut self) -> TzclrDcaevt2W < TzflgTzclrSpec > { TzclrDcaevt2W :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition"]
# [inline (always)]
# [must_use]
pub fn tzclr_dcbevt1 (& mut self) -> TzclrDcbevt1W < TzflgTzclrSpec > { TzclrDcbevt1W :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition."]
# [inline (always)]
# [must_use]
pub fn tzclr_dcbevt2 (& mut self) -> TzclrDcbevt2W < TzflgTzclrSpec > { TzclrDcbevt2W :: new (self , 22) } # [doc = "Bits 23:31 - 31:23\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < TzflgTzclrSpec > { Reserved1W :: new (self , 23) } } # [doc = "Trip-Zone Flag Register/ Trip-Zone Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzflg_tzclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzflg_tzclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TzflgTzclrSpec ; impl crate :: RegisterSpec for TzflgTzclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tzflg_tzclr::R`](R) reader structure"]
impl crate :: Readable for TzflgTzclrSpec { } # [doc = "`write(|w| ..)` method takes [`tzflg_tzclr::W`](W) writer structure"]
impl crate :: Writable for TzflgTzclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TZFLG_TZCLR to value 0"]
impl crate :: Resettable for TzflgTzclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TZFRC_ETSEL (rw) register accessor: Trip-Zone Force Register / Event-Trigger Selection Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzfrc_etsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzfrc_etsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tzfrc_etsel`]
module"]
# [doc (alias = "TZFRC_ETSEL")]
pub type TzfrcEtsel = crate :: Reg < tzfrc_etsel :: TzfrcEtselSpec > ; # [doc = "Trip-Zone Force Register / Event-Trigger Selection Register"]
pub mod tzfrc_etsel { # [doc = "Register `TZFRC_ETSEL` reader"]
pub type R = crate :: R < TzfrcEtselSpec > ; # [doc = "Register `TZFRC_ETSEL` writer"]
pub type W = crate :: W < TzfrcEtselSpec > ; # [doc = "Field `Reserved2` reader - 0:0\\]
Reserved"]
pub type Reserved2R = crate :: BitReader ; # [doc = "Field `Reserved2` writer - 0:0\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFRC_CBC` reader - 1:1\\]
Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG\\[CBC\\]
bit."]
pub type TzfrcCbcR = crate :: BitReader ; # [doc = "Field `TZFRC_CBC` writer - 1:1\\]
Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG\\[CBC\\]
bit."]
pub type TzfrcCbcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFRC_OST` reader - 2:2\\]
Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG\\[OST\\]
bit"]
pub type TzfrcOstR = crate :: BitReader ; # [doc = "Field `TZFRC_OST` writer - 2:2\\]
Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG\\[OST\\]
bit"]
pub type TzfrcOstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFRC_DCAEVT1` reader - 3:3\\]
Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG\\[DCAEVT1\\]
bit"]
pub type TzfrcDcaevt1R = crate :: BitReader ; # [doc = "Field `TZFRC_DCAEVT1` writer - 3:3\\]
Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG\\[DCAEVT1\\]
bit"]
pub type TzfrcDcaevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFRC_DCAEVT2` reader - 4:4\\]
Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG\\[DCAEVT2\\]
bit"]
pub type TzfrcDcaevt2R = crate :: BitReader ; # [doc = "Field `TZFRC_DCAEVT2` writer - 4:4\\]
Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG\\[DCAEVT2\\]
bit"]
pub type TzfrcDcaevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFRC_DCBEVT1` reader - 5:5\\]
Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG\\[DCBEVT1\\]
bit"]
pub type TzfrcDcbevt1R = crate :: BitReader ; # [doc = "Field `TZFRC_DCBEVT1` writer - 5:5\\]
Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG\\[DCBEVT1\\]
bit"]
pub type TzfrcDcbevt1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TZFRC_DCBEVT2` reader - 6:6\\]
Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG\\[DCBEVT2\\]
bit."]
pub type TzfrcDcbevt2R = crate :: BitReader ; # [doc = "Field `TZFRC_DCBEVT2` writer - 6:6\\]
Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG\\[DCBEVT2\\]
bit."]
pub type TzfrcDcbevt2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 15:7\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved3` writer - 15:7\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `ETSEL_INTSEL` reader - 18:16\\]
ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing."]
pub type EtselIntselR = crate :: FieldReader ; # [doc = "Field `ETSEL_INTSEL` writer - 18:16\\]
ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing."]
pub type EtselIntselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ETSEL_INTEN` reader - 19:19\\]
Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation"]
pub type EtselIntenR = crate :: BitReader ; # [doc = "Field `ETSEL_INTEN` writer - 19:19\\]
Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation"]
pub type EtselIntenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 23:20\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 23:20\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ETSEL_SOCASEL` reader - 26:24\\]
EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
pub type EtselSocaselR = crate :: FieldReader ; # [doc = "Field `ETSEL_SOCASEL` writer - 26:24\\]
EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
pub type EtselSocaselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ETSEL_SOCAEN` reader - 27:27\\]
Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse."]
pub type EtselSocaenR = crate :: BitReader ; # [doc = "Field `ETSEL_SOCAEN` writer - 27:27\\]
Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse."]
pub type EtselSocaenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETSEL_SOCBSEL` reader - 30:28\\]
EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
pub type EtselSocbselR = crate :: FieldReader ; # [doc = "Field `ETSEL_SOCBSEL` writer - 30:28\\]
EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
pub type EtselSocbselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ETSEL_SOCBEN` reader - 31:31\\]
Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse"]
pub type EtselSocbenR = crate :: BitReader ; # [doc = "Field `ETSEL_SOCBEN` writer - 31:31\\]
Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse"]
pub type EtselSocbenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG\\[CBC\\]
bit."]
# [inline (always)]
pub fn tzfrc_cbc (& self) -> TzfrcCbcR { TzfrcCbcR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG\\[OST\\]
bit"]
# [inline (always)]
pub fn tzfrc_ost (& self) -> TzfrcOstR { TzfrcOstR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG\\[DCAEVT1\\]
bit"]
# [inline (always)]
pub fn tzfrc_dcaevt1 (& self) -> TzfrcDcaevt1R { TzfrcDcaevt1R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG\\[DCAEVT2\\]
bit"]
# [inline (always)]
pub fn tzfrc_dcaevt2 (& self) -> TzfrcDcaevt2R { TzfrcDcaevt2R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG\\[DCBEVT1\\]
bit"]
# [inline (always)]
pub fn tzfrc_dcbevt1 (& self) -> TzfrcDcbevt1R { TzfrcDcbevt1R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG\\[DCBEVT2\\]
bit."]
# [inline (always)]
pub fn tzfrc_dcbevt2 (& self) -> TzfrcDcbevt2R { TzfrcDcbevt2R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:15 - 15:7\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 7) & 0x01ff) as u16) } # [doc = "Bits 16:18 - 18:16\\]
ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing."]
# [inline (always)]
pub fn etsel_intsel (& self) -> EtselIntselR { EtselIntselR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 19 - 19:19\\]
Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation"]
# [inline (always)]
pub fn etsel_inten (& self) -> EtselIntenR { EtselIntenR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:23 - 23:20\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:26 - 26:24\\]
EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
# [inline (always)]
pub fn etsel_socasel (& self) -> EtselSocaselR { EtselSocaselR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bit 27 - 27:27\\]
Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse."]
# [inline (always)]
pub fn etsel_socaen (& self) -> EtselSocaenR { EtselSocaenR :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bits 28:30 - 30:28\\]
EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
# [inline (always)]
pub fn etsel_socbsel (& self) -> EtselSocbselR { EtselSocbselR :: new (((self . bits >> 28) & 7) as u8) } # [doc = "Bit 31 - 31:31\\]
Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse"]
# [inline (always)]
pub fn etsel_socben (& self) -> EtselSocbenR { EtselSocbenR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < TzfrcEtselSpec > { Reserved2W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG\\[CBC\\]
bit."]
# [inline (always)]
# [must_use]
pub fn tzfrc_cbc (& mut self) -> TzfrcCbcW < TzfrcEtselSpec > { TzfrcCbcW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG\\[OST\\]
bit"]
# [inline (always)]
# [must_use]
pub fn tzfrc_ost (& mut self) -> TzfrcOstW < TzfrcEtselSpec > { TzfrcOstW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG\\[DCAEVT1\\]
bit"]
# [inline (always)]
# [must_use]
pub fn tzfrc_dcaevt1 (& mut self) -> TzfrcDcaevt1W < TzfrcEtselSpec > { TzfrcDcaevt1W :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG\\[DCAEVT2\\]
bit"]
# [inline (always)]
# [must_use]
pub fn tzfrc_dcaevt2 (& mut self) -> TzfrcDcaevt2W < TzfrcEtselSpec > { TzfrcDcaevt2W :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG\\[DCBEVT1\\]
bit"]
# [inline (always)]
# [must_use]
pub fn tzfrc_dcbevt1 (& mut self) -> TzfrcDcbevt1W < TzfrcEtselSpec > { TzfrcDcbevt1W :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG\\[DCBEVT2\\]
bit."]
# [inline (always)]
# [must_use]
pub fn tzfrc_dcbevt2 (& mut self) -> TzfrcDcbevt2W < TzfrcEtselSpec > { TzfrcDcbevt2W :: new (self , 6) } # [doc = "Bits 7:15 - 15:7\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < TzfrcEtselSpec > { Reserved3W :: new (self , 7) } # [doc = "Bits 16:18 - 18:16\\]
ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing."]
# [inline (always)]
# [must_use]
pub fn etsel_intsel (& mut self) -> EtselIntselW < TzfrcEtselSpec > { EtselIntselW :: new (self , 16) } # [doc = "Bit 19 - 19:19\\]
Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation"]
# [inline (always)]
# [must_use]
pub fn etsel_inten (& mut self) -> EtselIntenW < TzfrcEtselSpec > { EtselIntenW :: new (self , 19) } # [doc = "Bits 20:23 - 23:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < TzfrcEtselSpec > { Reserved1W :: new (self , 20) } # [doc = "Bits 24:26 - 26:24\\]
EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
# [inline (always)]
# [must_use]
pub fn etsel_socasel (& mut self) -> EtselSocaselW < TzfrcEtselSpec > { EtselSocaselW :: new (self , 24) } # [doc = "Bit 27 - 27:27\\]
Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse."]
# [inline (always)]
# [must_use]
pub fn etsel_socaen (& mut self) -> EtselSocaenW < TzfrcEtselSpec > { EtselSocaenW :: new (self , 27) } # [doc = "Bits 28:30 - 30:28\\]
EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing"]
# [inline (always)]
# [must_use]
pub fn etsel_socbsel (& mut self) -> EtselSocbselW < TzfrcEtselSpec > { EtselSocbselW :: new (self , 28) } # [doc = "Bit 31 - 31:31\\]
Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse"]
# [inline (always)]
# [must_use]
pub fn etsel_socben (& mut self) -> EtselSocbenW < TzfrcEtselSpec > { EtselSocbenW :: new (self , 31) } } # [doc = "Trip-Zone Force Register / Event-Trigger Selection Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tzfrc_etsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tzfrc_etsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TzfrcEtselSpec ; impl crate :: RegisterSpec for TzfrcEtselSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`tzfrc_etsel::R`](R) reader structure"]
impl crate :: Readable for TzfrcEtselSpec { } # [doc = "`write(|w| ..)` method takes [`tzfrc_etsel::W`](W) writer structure"]
impl crate :: Writable for TzfrcEtselSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TZFRC_ETSEL to value 0"]
impl crate :: Resettable for TzfrcEtselSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ETPS_ETFLG (rw) register accessor: Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register\n\nYou can [`read`](crate::Reg::read) this register and get [`etps_etflg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etps_etflg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etps_etflg`]
module"]
# [doc (alias = "ETPS_ETFLG")]
pub type EtpsEtflg = crate :: Reg < etps_etflg :: EtpsEtflgSpec > ; # [doc = "Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"]
pub mod etps_etflg { # [doc = "Register `ETPS_ETFLG` reader"]
pub type R = crate :: R < EtpsEtflgSpec > ; # [doc = "Register `ETPS_ETFLG` writer"]
pub type W = crate :: W < EtpsEtflgSpec > ; # [doc = "Field `ETPS_INTPRD` reader - 1:0\\]
ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL\\[INTSEL\\]
events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (ETSEL\\[INT\\]
= 1). If the interrupt status flag is set from a previous interrupt (ETFLG\\[INT\\]
= 1) then no interrupt will be generated until the flag is cleared via the ETCLR\\[INT\\]
bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS\\[INTCNT\\]
bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 0 Disable the interrupt event counter. No interrupt will be generated and ETFRC\\[INT\\]
is ignored. 1h Generate an interrupt on the first event INTCNT = 01 (first event) 2h Generate interrupt on ETPS\\[INTCNT\\]
= 1,0 (second event) 3h Generate interrupt on ETPS\\[INTCNT\\]
= 1,1 (third event)"]
pub type EtpsIntprdR = crate :: FieldReader ; # [doc = "Field `ETPS_INTPRD` writer - 1:0\\]
ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL\\[INTSEL\\]
events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (ETSEL\\[INT\\]
= 1). If the interrupt status flag is set from a previous interrupt (ETFLG\\[INT\\]
= 1) then no interrupt will be generated until the flag is cleared via the ETCLR\\[INT\\]
bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS\\[INTCNT\\]
bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 0 Disable the interrupt event counter. No interrupt will be generated and ETFRC\\[INT\\]
is ignored. 1h Generate an interrupt on the first event INTCNT = 01 (first event) 2h Generate interrupt on ETPS\\[INTCNT\\]
= 1,0 (second event) 3h Generate interrupt on ETPS\\[INTCNT\\]
= 1,1 (third event)"]
pub type EtpsIntprdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ETPS_INTCNT` reader - 3:2\\]
ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL\\[INTSEL\\]
events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL\\[INT\\]
= 0 or the interrupt flag is set, ETFLG\\[INT\\]
= 1, the counter will stop counting events when it reaches the period value ETPS\\[INTCNT\\]
= ETPS\\[INTPRD\\]. 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
pub type EtpsIntcntR = crate :: FieldReader ; # [doc = "Field `ETPS_INTCNT` writer - 3:2\\]
ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL\\[INTSEL\\]
events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL\\[INT\\]
= 0 or the interrupt flag is set, ETFLG\\[INT\\]
= 1, the counter will stop counting events when it reaches the period value ETPS\\[INTCNT\\]
= ETPS\\[INTPRD\\]. 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
pub type EtpsIntcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved3` reader - 7:4\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 7:4\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ETPS_SOCAPRD` reader - 9:8\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL\\[SOCASEL\\]
events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCAEN\\]
= 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCA\\]
= 1). Once the SOCA pulse is generated, the ETPS\\[SOCACNT\\]
bits will automatically be cleared. 0 Disable the SOCA event counter. No EPWMxSOCA pulse will be generated 1h Generate the EPWMxSOCA pulse on the first event: ETPS\\[SOCACNT\\]
= 0,1 2h Generate the EPWMxSOCA pulse on the second event: ETPS\\[SOCACNT\\]
= 1,0 3h Generate the EPWMxSOCA pulse on the third event: ETPS\\[SOCACNT\\]
= 1,1"]
pub type EtpsSocaprdR = crate :: FieldReader ; # [doc = "Field `ETPS_SOCAPRD` writer - 9:8\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL\\[SOCASEL\\]
events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCAEN\\]
= 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCA\\]
= 1). Once the SOCA pulse is generated, the ETPS\\[SOCACNT\\]
bits will automatically be cleared. 0 Disable the SOCA event counter. No EPWMxSOCA pulse will be generated 1h Generate the EPWMxSOCA pulse on the first event: ETPS\\[SOCACNT\\]
= 0,1 2h Generate the EPWMxSOCA pulse on the second event: ETPS\\[SOCACNT\\]
= 1,0 3h Generate the EPWMxSOCA pulse on the third event: ETPS\\[SOCACNT\\]
= 1,1"]
pub type EtpsSocaprdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ETPS_SOCACNT` reader - 11:10\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL\\[SOCASEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
pub type EtpsSocacntR = crate :: FieldReader ; # [doc = "Field `ETPS_SOCACNT` writer - 11:10\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL\\[SOCASEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
pub type EtpsSocacntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ETPS_SOCBPRD` reader - 13:12\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL\\[SOCBSEL\\]
events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCBEN\\]
= 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCB\\]
= 1). Once the SOCB pulse is generated, the ETPS\\[SOCBCNT\\]
bits will automatically be cleared. 0 Disable the SOCB event counter. No EPWMxSOCB pulse will be generated 1h Generate the EPWMxSOCB pulse on the first event: ETPS\\[SOCBCNT\\]
= 0,1 2h Generate the EPWMxSOCB pulse on the second event: ETPS\\[SOCBCNT\\]
= 1,0 3h Generate the EPWMxSOCB pulse on the third event: ETPS\\[SOCBCNT\\]
= 1,1"]
pub type EtpsSocbprdR = crate :: FieldReader ; # [doc = "Field `ETPS_SOCBPRD` writer - 13:12\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL\\[SOCBSEL\\]
events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCBEN\\]
= 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCB\\]
= 1). Once the SOCB pulse is generated, the ETPS\\[SOCBCNT\\]
bits will automatically be cleared. 0 Disable the SOCB event counter. No EPWMxSOCB pulse will be generated 1h Generate the EPWMxSOCB pulse on the first event: ETPS\\[SOCBCNT\\]
= 0,1 2h Generate the EPWMxSOCB pulse on the second event: ETPS\\[SOCBCNT\\]
= 1,0 3h Generate the EPWMxSOCB pulse on the third event: ETPS\\[SOCBCNT\\]
= 1,1"]
pub type EtpsSocbprdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ETPS_SOCBCNT` reader - 15:14\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL\\[SOCBSEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred"]
pub type EtpsSocbcntR = crate :: FieldReader ; # [doc = "Field `ETPS_SOCBCNT` writer - 15:14\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL\\[SOCBSEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred"]
pub type EtpsSocbcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ETFLG_INT` reader - 16:16\\]
Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG\\[INT\\]
bit is still set. If an interrupt is pending, it will not be generated until after the ETFLG\\[INT\\]
bit is cleared"]
pub type EtflgIntR = crate :: BitReader ; # [doc = "Field `ETFLG_INT` writer - 16:16\\]
Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG\\[INT\\]
bit is still set. If an interrupt is pending, it will not be generated until after the ETFLG\\[INT\\]
bit is cleared"]
pub type EtflgIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 17:17\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 17:17\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETFLG_SOCA` reader - 18:18\\]
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG\\[INT\\]
flag, the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA output will continue to be generated even if the flag bit is set"]
pub type EtflgSocaR = crate :: BitReader ; # [doc = "Field `ETFLG_SOCA` writer - 18:18\\]
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG\\[INT\\]
flag, the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA output will continue to be generated even if the flag bit is set"]
pub type EtflgSocaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETFLG_SOCB` reader - 19:19\\]
Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag bit is set."]
pub type EtflgSocbR = crate :: BitReader ; # [doc = "Field `ETFLG_SOCB` writer - 19:19\\]
Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag bit is set."]
pub type EtflgSocbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 31:20\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved2` writer - 31:20\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL\\[INTSEL\\]
events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (ETSEL\\[INT\\]
= 1). If the interrupt status flag is set from a previous interrupt (ETFLG\\[INT\\]
= 1) then no interrupt will be generated until the flag is cleared via the ETCLR\\[INT\\]
bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS\\[INTCNT\\]
bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 0 Disable the interrupt event counter. No interrupt will be generated and ETFRC\\[INT\\]
is ignored. 1h Generate an interrupt on the first event INTCNT = 01 (first event) 2h Generate interrupt on ETPS\\[INTCNT\\]
= 1,0 (second event) 3h Generate interrupt on ETPS\\[INTCNT\\]
= 1,1 (third event)"]
# [inline (always)]
pub fn etps_intprd (& self) -> EtpsIntprdR { EtpsIntprdR :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL\\[INTSEL\\]
events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL\\[INT\\]
= 0 or the interrupt flag is set, ETFLG\\[INT\\]
= 1, the counter will stop counting events when it reaches the period value ETPS\\[INTCNT\\]
= ETPS\\[INTPRD\\]. 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
# [inline (always)]
pub fn etps_intcnt (& self) -> EtpsIntcntR { EtpsIntcntR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:9 - 9:8\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL\\[SOCASEL\\]
events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCAEN\\]
= 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCA\\]
= 1). Once the SOCA pulse is generated, the ETPS\\[SOCACNT\\]
bits will automatically be cleared. 0 Disable the SOCA event counter. No EPWMxSOCA pulse will be generated 1h Generate the EPWMxSOCA pulse on the first event: ETPS\\[SOCACNT\\]
= 0,1 2h Generate the EPWMxSOCA pulse on the second event: ETPS\\[SOCACNT\\]
= 1,0 3h Generate the EPWMxSOCA pulse on the third event: ETPS\\[SOCACNT\\]
= 1,1"]
# [inline (always)]
pub fn etps_socaprd (& self) -> EtpsSocaprdR { EtpsSocaprdR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL\\[SOCASEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
# [inline (always)]
pub fn etps_socacnt (& self) -> EtpsSocacntR { EtpsSocacntR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - 13:12\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL\\[SOCBSEL\\]
events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCBEN\\]
= 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCB\\]
= 1). Once the SOCB pulse is generated, the ETPS\\[SOCBCNT\\]
bits will automatically be cleared. 0 Disable the SOCB event counter. No EPWMxSOCB pulse will be generated 1h Generate the EPWMxSOCB pulse on the first event: ETPS\\[SOCBCNT\\]
= 0,1 2h Generate the EPWMxSOCB pulse on the second event: ETPS\\[SOCBCNT\\]
= 1,0 3h Generate the EPWMxSOCB pulse on the third event: ETPS\\[SOCBCNT\\]
= 1,1"]
# [inline (always)]
pub fn etps_socbprd (& self) -> EtpsSocbprdR { EtpsSocbprdR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - 15:14\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL\\[SOCBSEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred"]
# [inline (always)]
pub fn etps_socbcnt (& self) -> EtpsSocbcntR { EtpsSocbcntR :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - 16:16\\]
Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG\\[INT\\]
bit is still set. If an interrupt is pending, it will not be generated until after the ETFLG\\[INT\\]
bit is cleared"]
# [inline (always)]
pub fn etflg_int (& self) -> EtflgIntR { EtflgIntR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG\\[INT\\]
flag, the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA output will continue to be generated even if the flag bit is set"]
# [inline (always)]
pub fn etflg_soca (& self) -> EtflgSocaR { EtflgSocaR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag bit is set."]
# [inline (always)]
pub fn etflg_socb (& self) -> EtflgSocbR { EtflgSocbR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL\\[INTSEL\\]
events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (ETSEL\\[INT\\]
= 1). If the interrupt status flag is set from a previous interrupt (ETFLG\\[INT\\]
= 1) then no interrupt will be generated until the flag is cleared via the ETCLR\\[INT\\]
bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS\\[INTCNT\\]
bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 0 Disable the interrupt event counter. No interrupt will be generated and ETFRC\\[INT\\]
is ignored. 1h Generate an interrupt on the first event INTCNT = 01 (first event) 2h Generate interrupt on ETPS\\[INTCNT\\]
= 1,0 (second event) 3h Generate interrupt on ETPS\\[INTCNT\\]
= 1,1 (third event)"]
# [inline (always)]
# [must_use]
pub fn etps_intprd (& mut self) -> EtpsIntprdW < EtpsEtflgSpec > { EtpsIntprdW :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL\\[INTSEL\\]
events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL\\[INT\\]
= 0 or the interrupt flag is set, ETFLG\\[INT\\]
= 1, the counter will stop counting events when it reaches the period value ETPS\\[INTCNT\\]
= ETPS\\[INTPRD\\]. 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
# [inline (always)]
# [must_use]
pub fn etps_intcnt (& mut self) -> EtpsIntcntW < EtpsEtflgSpec > { EtpsIntcntW :: new (self , 2) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < EtpsEtflgSpec > { Reserved3W :: new (self , 4) } # [doc = "Bits 8:9 - 9:8\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL\\[SOCASEL\\]
events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCAEN\\]
= 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCA\\]
= 1). Once the SOCA pulse is generated, the ETPS\\[SOCACNT\\]
bits will automatically be cleared. 0 Disable the SOCA event counter. No EPWMxSOCA pulse will be generated 1h Generate the EPWMxSOCA pulse on the first event: ETPS\\[SOCACNT\\]
= 0,1 2h Generate the EPWMxSOCA pulse on the second event: ETPS\\[SOCACNT\\]
= 1,0 3h Generate the EPWMxSOCA pulse on the third event: ETPS\\[SOCACNT\\]
= 1,1"]
# [inline (always)]
# [must_use]
pub fn etps_socaprd (& mut self) -> EtpsSocaprdW < EtpsEtflgSpec > { EtpsSocaprdW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL\\[SOCASEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred."]
# [inline (always)]
# [must_use]
pub fn etps_socacnt (& mut self) -> EtpsSocacntW < EtpsEtflgSpec > { EtpsSocacntW :: new (self , 10) } # [doc = "Bits 12:13 - 13:12\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL\\[SOCBSEL\\]
events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled (ETSEL\\[SOCBEN\\]
= 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG\\[SOCB\\]
= 1). Once the SOCB pulse is generated, the ETPS\\[SOCBCNT\\]
bits will automatically be cleared. 0 Disable the SOCB event counter. No EPWMxSOCB pulse will be generated 1h Generate the EPWMxSOCB pulse on the first event: ETPS\\[SOCBCNT\\]
= 0,1 2h Generate the EPWMxSOCB pulse on the second event: ETPS\\[SOCBCNT\\]
= 1,0 3h Generate the EPWMxSOCB pulse on the third event: ETPS\\[SOCBCNT\\]
= 1,1"]
# [inline (always)]
# [must_use]
pub fn etps_socbprd (& mut self) -> EtpsSocbprdW < EtpsEtflgSpec > { EtpsSocbprdW :: new (self , 12) } # [doc = "Bits 14:15 - 15:14\\]
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL\\[SOCBSEL\\]
events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred"]
# [inline (always)]
# [must_use]
pub fn etps_socbcnt (& mut self) -> EtpsSocbcntW < EtpsEtflgSpec > { EtpsSocbcntW :: new (self , 14) } # [doc = "Bit 16 - 16:16\\]
Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG\\[INT\\]
bit is still set. If an interrupt is pending, it will not be generated until after the ETFLG\\[INT\\]
bit is cleared"]
# [inline (always)]
# [must_use]
pub fn etflg_int (& mut self) -> EtflgIntW < EtpsEtflgSpec > { EtflgIntW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < EtpsEtflgSpec > { Reserved1W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG\\[INT\\]
flag, the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA output will continue to be generated even if the flag bit is set"]
# [inline (always)]
# [must_use]
pub fn etflg_soca (& mut self) -> EtflgSocaW < EtpsEtflgSpec > { EtflgSocaW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag bit is set."]
# [inline (always)]
# [must_use]
pub fn etflg_socb (& mut self) -> EtflgSocbW < EtpsEtflgSpec > { EtflgSocbW :: new (self , 19) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < EtpsEtflgSpec > { Reserved2W :: new (self , 20) } } # [doc = "Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register\n\nYou can [`read`](crate::Reg::read) this register and get [`etps_etflg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etps_etflg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EtpsEtflgSpec ; impl crate :: RegisterSpec for EtpsEtflgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`etps_etflg::R`](R) reader structure"]
impl crate :: Readable for EtpsEtflgSpec { } # [doc = "`write(|w| ..)` method takes [`etps_etflg::W`](W) writer structure"]
impl crate :: Writable for EtpsEtflgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ETPS_ETFLG to value 0"]
impl crate :: Resettable for EtpsEtflgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ETCLR_ETFRC (rw) register accessor: Event-Trigger Clear Register/ Event-Trigger Force Register\n\nYou can [`read`](crate::Reg::read) this register and get [`etclr_etfrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etclr_etfrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etclr_etfrc`]
module"]
# [doc (alias = "ETCLR_ETFRC")]
pub type EtclrEtfrc = crate :: Reg < etclr_etfrc :: EtclrEtfrcSpec > ; # [doc = "Event-Trigger Clear Register/ Event-Trigger Force Register"]
pub mod etclr_etfrc { # [doc = "Register `ETCLR_ETFRC` reader"]
pub type R = crate :: R < EtclrEtfrcSpec > ; # [doc = "Register `ETCLR_ETFRC` writer"]
pub type W = crate :: W < EtclrEtfrcSpec > ; # [doc = "Field `ETCLR_INT` reader - 0:0\\]
ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[INT\\]
flag bit and enable further interrupts pulses to be generated"]
pub type EtclrIntR = crate :: BitReader ; # [doc = "Field `ETCLR_INT` writer - 0:0\\]
ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[INT\\]
flag bit and enable further interrupts pulses to be generated"]
pub type EtclrIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 1:1\\]
Reserved"]
pub type Reserved1R = crate :: BitReader ; # [doc = "Field `Reserved1` writer - 1:1\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETCLR_SOCA` reader - 2:2\\]
ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCA\\]
flag bit"]
pub type EtclrSocaR = crate :: BitReader ; # [doc = "Field `ETCLR_SOCA` writer - 2:2\\]
ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCA\\]
flag bit"]
pub type EtclrSocaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETCLR_SOCB` reader - 3:3\\]
ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCB\\]
flag bit"]
pub type EtclrSocbR = crate :: BitReader ; # [doc = "Field `ETCLR_SOCB` writer - 3:3\\]
ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCB\\]
flag bit"]
pub type EtclrSocbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 15:4\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved2` writer - 15:4\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `ETFRC_INT` reader - 16:16\\]
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes"]
pub type EtfrcIntR = crate :: BitReader ; # [doc = "Field `ETFRC_INT` writer - 16:16\\]
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes"]
pub type EtfrcIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved3` reader - 17:17\\]
Reserved"]
pub type Reserved3R = crate :: BitReader ; # [doc = "Field `Reserved3` writer - 17:17\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETFRC_SOCA` reader - 18:18\\]
SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCA\\]
flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes"]
pub type EtfrcSocaR = crate :: BitReader ; # [doc = "Field `ETFRC_SOCA` writer - 18:18\\]
SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCA\\]
flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes"]
pub type EtfrcSocaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETFRC_SOCB` reader - 19:19\\]
SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCB\\]
flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes"]
pub type EtfrcSocbR = crate :: BitReader ; # [doc = "Field `ETFRC_SOCB` writer - 19:19\\]
SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCB\\]
flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes"]
pub type EtfrcSocbW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved4` reader - 31:20\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved4` writer - 31:20\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[INT\\]
flag bit and enable further interrupts pulses to be generated"]
# [inline (always)]
pub fn etclr_int (& self) -> EtclrIntR { EtclrIntR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCA\\]
flag bit"]
# [inline (always)]
pub fn etclr_soca (& self) -> EtclrSocaR { EtclrSocaR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCB\\]
flag bit"]
# [inline (always)]
pub fn etclr_socb (& self) -> EtclrSocbR { EtclrSocbR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:15 - 15:4\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 4) & 0x0fff) as u16) } # [doc = "Bit 16 - 16:16\\]
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes"]
# [inline (always)]
pub fn etfrc_int (& self) -> EtfrcIntR { EtfrcIntR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCA\\]
flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes"]
# [inline (always)]
pub fn etfrc_soca (& self) -> EtfrcSocaR { EtfrcSocaR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCB\\]
flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes"]
# [inline (always)]
pub fn etfrc_socb (& self) -> EtfrcSocbR { EtfrcSocbR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[INT\\]
flag bit and enable further interrupts pulses to be generated"]
# [inline (always)]
# [must_use]
pub fn etclr_int (& mut self) -> EtclrIntW < EtclrEtfrcSpec > { EtclrIntW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < EtclrEtfrcSpec > { Reserved1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCA\\]
flag bit"]
# [inline (always)]
# [must_use]
pub fn etclr_soca (& mut self) -> EtclrSocaW < EtclrEtfrcSpec > { EtclrSocaW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG\\[SOCB\\]
flag bit"]
# [inline (always)]
# [must_use]
pub fn etclr_socb (& mut self) -> EtclrSocbW < EtclrEtfrcSpec > { EtclrSocbW :: new (self , 3) } # [doc = "Bits 4:15 - 15:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < EtclrEtfrcSpec > { Reserved2W :: new (self , 4) } # [doc = "Bit 16 - 16:16\\]
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes"]
# [inline (always)]
# [must_use]
pub fn etfrc_int (& mut self) -> EtfrcIntW < EtclrEtfrcSpec > { EtfrcIntW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < EtclrEtfrcSpec > { Reserved3W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCA\\]
flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes"]
# [inline (always)]
# [must_use]
pub fn etfrc_soca (& mut self) -> EtfrcSocaW < EtclrEtfrcSpec > { EtfrcSocaW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG\\[SOCB\\]
flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes"]
# [inline (always)]
# [must_use]
pub fn etfrc_socb (& mut self) -> EtfrcSocbW < EtclrEtfrcSpec > { EtfrcSocbW :: new (self , 19) } # [doc = "Bits 20:31 - 31:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < EtclrEtfrcSpec > { Reserved4W :: new (self , 20) } } # [doc = "Event-Trigger Clear Register/ Event-Trigger Force Register\n\nYou can [`read`](crate::Reg::read) this register and get [`etclr_etfrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etclr_etfrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EtclrEtfrcSpec ; impl crate :: RegisterSpec for EtclrEtfrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`etclr_etfrc::R`](R) reader structure"]
impl crate :: Readable for EtclrEtfrcSpec { } # [doc = "`write(|w| ..)` method takes [`etclr_etfrc::W`](W) writer structure"]
impl crate :: Writable for EtclrEtfrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ETCLR_ETFRC to value 0"]
impl crate :: Resettable for EtclrEtfrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCCTL (rw) register accessor: PWM-Chopper Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pcctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcctl`]
module"]
# [doc (alias = "PCCTL")]
pub type Pcctl = crate :: Reg < pcctl :: PcctlSpec > ; # [doc = "PWM-Chopper Control Register"]
pub mod pcctl { # [doc = "Register `PCCTL` reader"]
pub type R = crate :: R < PcctlSpec > ; # [doc = "Register `PCCTL` writer"]
pub type W = crate :: W < PcctlSpec > ; # [doc = "Field `CHPEN` reader - 0:0\\]
PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function"]
pub type ChpenR = crate :: BitReader ; # [doc = "Field `CHPEN` writer - 0:0\\]
PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function"]
pub type ChpenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OSHTWTH` reader - 4:1\\]
One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide ( = 400 nS at 100 MHz VCLK3) 5h 6 x VCLK3 / 8 wide ( = 480 nS at 100 MHz VCLK3) 6h 7 x VCLK3 / 8 wide ( = 560 nS at 100 MHz VCLK3) 7h 8 x VCLK3 / 8 wide ( = 640 nS at 100 MHz VCLK3) 8h 9 x VCLK3 / 8 wide ( = 720 nS at 100 MHz VCLK3) 9h 10 x VCLK3 / 8 wide ( = 800 nS at 100 MHz VCLK3) Ah 11 x VCLK3 / 8 wide ( = 880 nS at 100 MHz VCLK3) Bh 12 x VCLK3 / 8 wide ( = 960 nS at 100 MHz VCLK3) Ch 13 x VCLK3 / 8 wide ( = 1040 nS at 100 MHz VCLK3) Dh 14 x VCLK3 / 8 wide ( = 1120 nS at 100 MHz VCLK3) Eh 15 x VCLK3 / 8 wide ( = 1200 nS at 100 MHz VCLK3) Fh 16 x VCLK3 / 8 wide ( = 1280 nS at 100 MHz VCLK3)"]
pub type OshtwthR = crate :: FieldReader ; # [doc = "Field `OSHTWTH` writer - 4:1\\]
One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide ( = 400 nS at 100 MHz VCLK3) 5h 6 x VCLK3 / 8 wide ( = 480 nS at 100 MHz VCLK3) 6h 7 x VCLK3 / 8 wide ( = 560 nS at 100 MHz VCLK3) 7h 8 x VCLK3 / 8 wide ( = 640 nS at 100 MHz VCLK3) 8h 9 x VCLK3 / 8 wide ( = 720 nS at 100 MHz VCLK3) 9h 10 x VCLK3 / 8 wide ( = 800 nS at 100 MHz VCLK3) Ah 11 x VCLK3 / 8 wide ( = 880 nS at 100 MHz VCLK3) Bh 12 x VCLK3 / 8 wide ( = 960 nS at 100 MHz VCLK3) Ch 13 x VCLK3 / 8 wide ( = 1040 nS at 100 MHz VCLK3) Dh 14 x VCLK3 / 8 wide ( = 1120 nS at 100 MHz VCLK3) Eh 15 x VCLK3 / 8 wide ( = 1200 nS at 100 MHz VCLK3) Fh 16 x VCLK3 / 8 wide ( = 1280 nS at 100 MHz VCLK3)"]
pub type OshtwthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CHPFREQ` reader - 7:5\\]
Chopping Clock Frequency 0 Divide by 1 (no prescale, = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz VCLK3) 5h Divide by 6 (2.08 MHz at 100 MHz VCLK3) 6h Divide by 7 (1.78 MHz at 100 MHz VCLK3) 7h Divide by 8 (1.56 MHz at 100 MHz VCLK3)"]
pub type ChpfreqR = crate :: FieldReader ; # [doc = "Field `CHPFREQ` writer - 7:5\\]
Chopping Clock Frequency 0 Divide by 1 (no prescale, = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz VCLK3) 5h Divide by 6 (2.08 MHz at 100 MHz VCLK3) 6h Divide by 7 (1.78 MHz at 100 MHz VCLK3) 7h Divide by 8 (1.56 MHz at 100 MHz VCLK3)"]
pub type ChpfreqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CHPDUTY` reader - 10:8\\]
Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved"]
pub type ChpdutyR = crate :: FieldReader ; # [doc = "Field `CHPDUTY` writer - 10:8\\]
Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved"]
pub type ChpdutyW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bit 0 - 0:0\\]
PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function"]
# [inline (always)]
pub fn chpen (& self) -> ChpenR { ChpenR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:4 - 4:1\\]
One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide ( = 400 nS at 100 MHz VCLK3) 5h 6 x VCLK3 / 8 wide ( = 480 nS at 100 MHz VCLK3) 6h 7 x VCLK3 / 8 wide ( = 560 nS at 100 MHz VCLK3) 7h 8 x VCLK3 / 8 wide ( = 640 nS at 100 MHz VCLK3) 8h 9 x VCLK3 / 8 wide ( = 720 nS at 100 MHz VCLK3) 9h 10 x VCLK3 / 8 wide ( = 800 nS at 100 MHz VCLK3) Ah 11 x VCLK3 / 8 wide ( = 880 nS at 100 MHz VCLK3) Bh 12 x VCLK3 / 8 wide ( = 960 nS at 100 MHz VCLK3) Ch 13 x VCLK3 / 8 wide ( = 1040 nS at 100 MHz VCLK3) Dh 14 x VCLK3 / 8 wide ( = 1120 nS at 100 MHz VCLK3) Eh 15 x VCLK3 / 8 wide ( = 1200 nS at 100 MHz VCLK3) Fh 16 x VCLK3 / 8 wide ( = 1280 nS at 100 MHz VCLK3)"]
# [inline (always)]
pub fn oshtwth (& self) -> OshtwthR { OshtwthR :: new (((self . bits >> 1) & 0x0f) as u8) } # [doc = "Bits 5:7 - 7:5\\]
Chopping Clock Frequency 0 Divide by 1 (no prescale, = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz VCLK3) 5h Divide by 6 (2.08 MHz at 100 MHz VCLK3) 6h Divide by 7 (1.78 MHz at 100 MHz VCLK3) 7h Divide by 8 (1.56 MHz at 100 MHz VCLK3)"]
# [inline (always)]
pub fn chpfreq (& self) -> ChpfreqR { ChpfreqR :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved"]
# [inline (always)]
pub fn chpduty (& self) -> ChpdutyR { ChpdutyR :: new (((self . bits >> 8) & 7) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function"]
# [inline (always)]
# [must_use]
pub fn chpen (& mut self) -> ChpenW < PcctlSpec > { ChpenW :: new (self , 0) } # [doc = "Bits 1:4 - 4:1\\]
One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide ( = 400 nS at 100 MHz VCLK3) 5h 6 x VCLK3 / 8 wide ( = 480 nS at 100 MHz VCLK3) 6h 7 x VCLK3 / 8 wide ( = 560 nS at 100 MHz VCLK3) 7h 8 x VCLK3 / 8 wide ( = 640 nS at 100 MHz VCLK3) 8h 9 x VCLK3 / 8 wide ( = 720 nS at 100 MHz VCLK3) 9h 10 x VCLK3 / 8 wide ( = 800 nS at 100 MHz VCLK3) Ah 11 x VCLK3 / 8 wide ( = 880 nS at 100 MHz VCLK3) Bh 12 x VCLK3 / 8 wide ( = 960 nS at 100 MHz VCLK3) Ch 13 x VCLK3 / 8 wide ( = 1040 nS at 100 MHz VCLK3) Dh 14 x VCLK3 / 8 wide ( = 1120 nS at 100 MHz VCLK3) Eh 15 x VCLK3 / 8 wide ( = 1200 nS at 100 MHz VCLK3) Fh 16 x VCLK3 / 8 wide ( = 1280 nS at 100 MHz VCLK3)"]
# [inline (always)]
# [must_use]
pub fn oshtwth (& mut self) -> OshtwthW < PcctlSpec > { OshtwthW :: new (self , 1) } # [doc = "Bits 5:7 - 7:5\\]
Chopping Clock Frequency 0 Divide by 1 (no prescale, = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz VCLK3) 5h Divide by 6 (2.08 MHz at 100 MHz VCLK3) 6h Divide by 7 (1.78 MHz at 100 MHz VCLK3) 7h Divide by 8 (1.56 MHz at 100 MHz VCLK3)"]
# [inline (always)]
# [must_use]
pub fn chpfreq (& mut self) -> ChpfreqW < PcctlSpec > { ChpfreqW :: new (self , 5) } # [doc = "Bits 8:10 - 10:8\\]
Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved"]
# [inline (always)]
# [must_use]
pub fn chpduty (& mut self) -> ChpdutyW < PcctlSpec > { ChpdutyW :: new (self , 8) } } # [doc = "PWM-Chopper Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pcctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcctlSpec ; impl crate :: RegisterSpec for PcctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pcctl::R`](R) reader structure"]
impl crate :: Readable for PcctlSpec { } # [doc = "`write(|w| ..)` method takes [`pcctl::W`](W) writer structure"]
impl crate :: Writable for PcctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCCTL to value 0"]
impl crate :: Resettable for PcctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "Reserved"]
pub mod reserved1 { # [doc = "Register `Reserved1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `Reserved1` writer"]
pub type W = crate :: W < Reserved1Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved2`]
module"]
pub type Reserved2 = crate :: Reg < reserved2 :: Reserved2Spec > ; # [doc = "Reserved"]
pub mod reserved2 { # [doc = "Register `Reserved2` reader"]
pub type R = crate :: R < Reserved2Spec > ; # [doc = "Register `Reserved2` writer"]
pub type W = crate :: W < Reserved2Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved2Spec ; impl crate :: RegisterSpec for Reserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved2::R`](R) reader structure"]
impl crate :: Readable for Reserved2Spec { } # [doc = "`write(|w| ..)` method takes [`reserved2::W`](W) writer structure"]
impl crate :: Writable for Reserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved2 to value 0"]
impl crate :: Resettable for Reserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved3`]
module"]
pub type Reserved3 = crate :: Reg < reserved3 :: Reserved3Spec > ; # [doc = "Reserved"]
pub mod reserved3 { # [doc = "Register `Reserved3` reader"]
pub type R = crate :: R < Reserved3Spec > ; # [doc = "Register `Reserved3` writer"]
pub type W = crate :: W < Reserved3Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved3Spec ; impl crate :: RegisterSpec for Reserved3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved3::R`](R) reader structure"]
impl crate :: Readable for Reserved3Spec { } # [doc = "`write(|w| ..)` method takes [`reserved3::W`](W) writer structure"]
impl crate :: Writable for Reserved3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved3 to value 0"]
impl crate :: Resettable for Reserved3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved4 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved4`]
module"]
pub type Reserved4 = crate :: Reg < reserved4 :: Reserved4Spec > ; # [doc = "Reserved"]
pub mod reserved4 { # [doc = "Register `Reserved4` reader"]
pub type R = crate :: R < Reserved4Spec > ; # [doc = "Register `Reserved4` writer"]
pub type W = crate :: W < Reserved4Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved4Spec ; impl crate :: RegisterSpec for Reserved4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved4::R`](R) reader structure"]
impl crate :: Readable for Reserved4Spec { } # [doc = "`write(|w| ..)` method takes [`reserved4::W`](W) writer structure"]
impl crate :: Writable for Reserved4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved4 to value 0"]
impl crate :: Resettable for Reserved4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved5 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved5`]
module"]
pub type Reserved5 = crate :: Reg < reserved5 :: Reserved5Spec > ; # [doc = "Reserved"]
pub mod reserved5 { # [doc = "Register `Reserved5` reader"]
pub type R = crate :: R < Reserved5Spec > ; # [doc = "Register `Reserved5` writer"]
pub type W = crate :: W < Reserved5Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved5Spec ; impl crate :: RegisterSpec for Reserved5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved5::R`](R) reader structure"]
impl crate :: Readable for Reserved5Spec { } # [doc = "`write(|w| ..)` method takes [`reserved5::W`](W) writer structure"]
impl crate :: Writable for Reserved5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved5 to value 0"]
impl crate :: Resettable for Reserved5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved6 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved6`]
module"]
pub type Reserved6 = crate :: Reg < reserved6 :: Reserved6Spec > ; # [doc = "Reserved"]
pub mod reserved6 { # [doc = "Register `Reserved6` reader"]
pub type R = crate :: R < Reserved6Spec > ; # [doc = "Register `Reserved6` writer"]
pub type W = crate :: W < Reserved6Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved6Spec ; impl crate :: RegisterSpec for Reserved6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved6::R`](R) reader structure"]
impl crate :: Readable for Reserved6Spec { } # [doc = "`write(|w| ..)` method takes [`reserved6::W`](W) writer structure"]
impl crate :: Writable for Reserved6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved6 to value 0"]
impl crate :: Resettable for Reserved6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved7 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved7`]
module"]
pub type Reserved7 = crate :: Reg < reserved7 :: Reserved7Spec > ; # [doc = "Reserved"]
pub mod reserved7 { # [doc = "Register `Reserved7` reader"]
pub type R = crate :: R < Reserved7Spec > ; # [doc = "Register `Reserved7` writer"]
pub type W = crate :: W < Reserved7Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved7Spec ; impl crate :: RegisterSpec for Reserved7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved7::R`](R) reader structure"]
impl crate :: Readable for Reserved7Spec { } # [doc = "`write(|w| ..)` method takes [`reserved7::W`](W) writer structure"]
impl crate :: Writable for Reserved7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved7 to value 0"]
impl crate :: Resettable for Reserved7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "Reserved8 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved8`]
module"]
pub type Reserved8 = crate :: Reg < reserved8 :: Reserved8Spec > ; # [doc = "Reserved"]
pub mod reserved8 { # [doc = "Register `Reserved8` reader"]
pub type R = crate :: R < Reserved8Spec > ; # [doc = "Register `Reserved8` writer"]
pub type W = crate :: W < Reserved8Spec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved8Spec ; impl crate :: RegisterSpec for Reserved8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved8::R`](R) reader structure"]
impl crate :: Readable for Reserved8Spec { } # [doc = "`write(|w| ..)` method takes [`reserved8::W`](W) writer structure"]
impl crate :: Writable for Reserved8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets Reserved8 to value 0"]
impl crate :: Resettable for Reserved8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCTRIPSEL_DCACTL (rw) register accessor: Digital Compare Trip Select Register/ Digital Compare A Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dctripsel_dcactl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctripsel_dcactl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dctripsel_dcactl`]
module"]
# [doc (alias = "DCTRIPSEL_DCACTL")]
pub type DctripselDcactl = crate :: Reg < dctripsel_dcactl :: DctripselDcactlSpec > ; # [doc = "Digital Compare Trip Select Register/ Digital Compare A Control Register"]
pub mod dctripsel_dcactl { # [doc = "Register `DCTRIPSEL_DCACTL` reader"]
pub type R = crate :: R < DctripselDcactlSpec > ; # [doc = "Register `DCTRIPSEL_DCACTL` writer"]
pub type W = crate :: W < DctripselDcactlSpec > ; # [doc = "Field `DCTRIPSEL_DCAHCOMPSEL` reader - 3:0\\]
Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcahcompselR = crate :: FieldReader ; # [doc = "Field `DCTRIPSEL_DCAHCOMPSEL` writer - 3:0\\]
Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcahcompselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DCTRIPSEL_DCALCOMPSEL` reader - 7:4\\]
Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcalcompselR = crate :: FieldReader ; # [doc = "Field `DCTRIPSEL_DCALCOMPSEL` writer - 7:4\\]
Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcalcompselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DCTRIPSEL_DCBHCOMPSEL` reader - 11:8\\]
Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcbhcompselR = crate :: FieldReader ; # [doc = "Field `DCTRIPSEL_DCBHCOMPSEL` writer - 11:8\\]
Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcbhcompselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DCTRIPSEL_DCBLCOMPSEL` reader - 15:12\\]
Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcblcompselR = crate :: FieldReader ; # [doc = "Field `DCTRIPSEL_DCBLCOMPSEL` writer - 15:12\\]
Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
pub type DctripselDcblcompselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DCACTL_EVT1SRCSEL` reader - 16:16\\]
DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcactlEvt1srcselR = crate :: BitReader ; # [doc = "Field `DCACTL_EVT1SRCSEL` writer - 16:16\\]
DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcactlEvt1srcselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCACTL_EVT1FRC_SYNCSEL` reader - 17:17\\]
DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcactlEvt1frcSyncselR = crate :: BitReader ; # [doc = "Field `DCACTL_EVT1FRC_SYNCSEL` writer - 17:17\\]
DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcactlEvt1frcSyncselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCACTL_EVT1SOCE` reader - 18:18\\]
DCAEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
pub type DcactlEvt1soceR = crate :: BitReader ; # [doc = "Field `DCACTL_EVT1SOCE` writer - 18:18\\]
DCAEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
pub type DcactlEvt1soceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCACTL_EVT1SYNCE` reader - 19:19\\]
DCAEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
pub type DcactlEvt1synceR = crate :: BitReader ; # [doc = "Field `DCACTL_EVT1SYNCE` writer - 19:19\\]
DCAEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
pub type DcactlEvt1synceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 23:20\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 23:20\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DCACTL_EVT2SRCSEL` reader - 24:24\\]
DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcactlEvt2srcselR = crate :: BitReader ; # [doc = "Field `DCACTL_EVT2SRCSEL` writer - 24:24\\]
DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcactlEvt2srcselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCACTL_EVT2FRC_SYNCSEL` reader - 25:25\\]
DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcactlEvt2frcSyncselR = crate :: BitReader ; # [doc = "Field `DCACTL_EVT2FRC_SYNCSEL` writer - 25:25\\]
DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcactlEvt2frcSyncselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 31:26\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:26\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
pub fn dctripsel_dcahcompsel (& self) -> DctripselDcahcompselR { DctripselDcahcompselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
pub fn dctripsel_dcalcompsel (& self) -> DctripselDcalcompselR { DctripselDcalcompselR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
pub fn dctripsel_dcbhcompsel (& self) -> DctripselDcbhcompselR { DctripselDcbhcompselR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
pub fn dctripsel_dcblcompsel (& self) -> DctripselDcblcompselR { DctripselDcblcompselR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bit 16 - 16:16\\]
DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
pub fn dcactl_evt1srcsel (& self) -> DcactlEvt1srcselR { DcactlEvt1srcselR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
pub fn dcactl_evt1frc_syncsel (& self) -> DcactlEvt1frcSyncselR { DcactlEvt1frcSyncselR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
DCAEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
# [inline (always)]
pub fn dcactl_evt1soce (& self) -> DcactlEvt1soceR { DcactlEvt1soceR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
DCAEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
# [inline (always)]
pub fn dcactl_evt1synce (& self) -> DcactlEvt1synceR { DcactlEvt1synceR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:23 - 23:20\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bit 24 - 24:24\\]
DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
pub fn dcactl_evt2srcsel (& self) -> DcactlEvt2srcselR { DcactlEvt2srcselR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
pub fn dcactl_evt2frc_syncsel (& self) -> DcactlEvt2frcSyncselR { DcactlEvt2frcSyncselR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 26) & 0x3f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
# [must_use]
pub fn dctripsel_dcahcompsel (& mut self) -> DctripselDcahcompselW < DctripselDcactlSpec > { DctripselDcahcompselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
# [must_use]
pub fn dctripsel_dcalcompsel (& mut self) -> DctripselDcalcompselW < DctripselDcactlSpec > { DctripselDcalcompselW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
# [must_use]
pub fn dctripsel_dcbhcompsel (& mut self) -> DctripselDcbhcompselW < DctripselDcactlSpec > { DctripselDcbhcompselW :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved."]
# [inline (always)]
# [must_use]
pub fn dctripsel_dcblcompsel (& mut self) -> DctripselDcblcompselW < DctripselDcactlSpec > { DctripselDcblcompselW :: new (self , 12) } # [doc = "Bit 16 - 16:16\\]
DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
# [must_use]
pub fn dcactl_evt1srcsel (& mut self) -> DcactlEvt1srcselW < DctripselDcactlSpec > { DcactlEvt1srcselW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
# [must_use]
pub fn dcactl_evt1frc_syncsel (& mut self) -> DcactlEvt1frcSyncselW < DctripselDcactlSpec > { DcactlEvt1frcSyncselW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
DCAEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
# [inline (always)]
# [must_use]
pub fn dcactl_evt1soce (& mut self) -> DcactlEvt1soceW < DctripselDcactlSpec > { DcactlEvt1soceW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
DCAEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
# [inline (always)]
# [must_use]
pub fn dcactl_evt1synce (& mut self) -> DcactlEvt1synceW < DctripselDcactlSpec > { DcactlEvt1synceW :: new (self , 19) } # [doc = "Bits 20:23 - 23:20\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < DctripselDcactlSpec > { Reserved1W :: new (self , 20) } # [doc = "Bit 24 - 24:24\\]
DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
# [must_use]
pub fn dcactl_evt2srcsel (& mut self) -> DcactlEvt2srcselW < DctripselDcactlSpec > { DcactlEvt2srcselW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
# [must_use]
pub fn dcactl_evt2frc_syncsel (& mut self) -> DcactlEvt2frcSyncselW < DctripselDcactlSpec > { DcactlEvt2frcSyncselW :: new (self , 25) } # [doc = "Bits 26:31 - 31:26\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < DctripselDcactlSpec > { Reserved2W :: new (self , 26) } } # [doc = "Digital Compare Trip Select Register/ Digital Compare A Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dctripsel_dcactl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctripsel_dcactl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DctripselDcactlSpec ; impl crate :: RegisterSpec for DctripselDcactlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dctripsel_dcactl::R`](R) reader structure"]
impl crate :: Readable for DctripselDcactlSpec { } # [doc = "`write(|w| ..)` method takes [`dctripsel_dcactl::W`](W) writer structure"]
impl crate :: Writable for DctripselDcactlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCTRIPSEL_DCACTL to value 0"]
impl crate :: Resettable for DctripselDcactlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCBCTL_DCFCTL (rw) register accessor: Digital Compare B Control Register/ Digital Compare Filter Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcbctl_dcfctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcbctl_dcfctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcbctl_dcfctl`]
module"]
# [doc (alias = "DCBCTL_DCFCTL")]
pub type DcbctlDcfctl = crate :: Reg < dcbctl_dcfctl :: DcbctlDcfctlSpec > ; # [doc = "Digital Compare B Control Register/ Digital Compare Filter Control Register"]
pub mod dcbctl_dcfctl { # [doc = "Register `DCBCTL_DCFCTL` reader"]
pub type R = crate :: R < DcbctlDcfctlSpec > ; # [doc = "Register `DCBCTL_DCFCTL` writer"]
pub type W = crate :: W < DcbctlDcfctlSpec > ; # [doc = "Field `DCBCTL_EVT1SRCSEL` reader - 0:0\\]
DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcbctlEvt1srcselR = crate :: BitReader ; # [doc = "Field `DCBCTL_EVT1SRCSEL` writer - 0:0\\]
DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcbctlEvt1srcselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCBCTL_EVT1FRC_SYNCSEL` reader - 1:1\\]
DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcbctlEvt1frcSyncselR = crate :: BitReader ; # [doc = "Field `DCBCTL_EVT1FRC_SYNCSEL` writer - 1:1\\]
DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcbctlEvt1frcSyncselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCBCTL_EVT1SOCE` reader - 2:2\\]
DCBEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
pub type DcbctlEvt1soceR = crate :: BitReader ; # [doc = "Field `DCBCTL_EVT1SOCE` writer - 2:2\\]
DCBEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
pub type DcbctlEvt1soceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCBCTL_EVT1SYNCE` reader - 3:3\\]
DCBEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
pub type DcbctlEvt1synceR = crate :: BitReader ; # [doc = "Field `DCBCTL_EVT1SYNCE` writer - 3:3\\]
DCBEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
pub type DcbctlEvt1synceW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 7:4\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 7:4\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DCBCTL_EVT2SRCSEL` reader - 8:8\\]
DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcbctlEvt2srcselR = crate :: BitReader ; # [doc = "Field `DCBCTL_EVT2SRCSEL` writer - 8:8\\]
DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal"]
pub type DcbctlEvt2srcselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCBCTL_EVT2FRC_SYNCSEL` reader - 9:9\\]
DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcbctlEvt2frcSyncselR = crate :: BitReader ; # [doc = "Field `DCBCTL_EVT2FRC_SYNCSEL` writer - 9:9\\]
DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
pub type DcbctlEvt2frcSyncselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved2` reader - 15:10\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 15:10\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `DCFCTL_SRCSEL` reader - 17:16\\]
Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal"]
pub type DcfctlSrcselR = crate :: FieldReader ; # [doc = "Field `DCFCTL_SRCSEL` writer - 17:16\\]
Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal"]
pub type DcfctlSrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DCFCTL_BLANKE` reader - 18:18\\]
Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled"]
pub type DcfctlBlankeR = crate :: BitReader ; # [doc = "Field `DCFCTL_BLANKE` writer - 18:18\\]
Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled"]
pub type DcfctlBlankeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCFCTL_BLANKINV` reader - 19:19\\]
Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted"]
pub type DcfctlBlankinvR = crate :: BitReader ; # [doc = "Field `DCFCTL_BLANKINV` writer - 19:19\\]
Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted"]
pub type DcfctlBlankinvW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCFCTL_PULSESEL` reader - 21:20\\]
Pulse Select For Blanking &amp; Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved"]
pub type DcfctlPulseselR = crate :: FieldReader ; # [doc = "Field `DCFCTL_PULSESEL` writer - 21:20\\]
Pulse Select For Blanking &amp; Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved"]
pub type DcfctlPulseselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved3` reader - 31:22\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved3` writer - 31:22\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
pub fn dcbctl_evt1srcsel (& self) -> DcbctlEvt1srcselR { DcbctlEvt1srcselR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
pub fn dcbctl_evt1frc_syncsel (& self) -> DcbctlEvt1frcSyncselR { DcbctlEvt1frcSyncselR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
DCBEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
# [inline (always)]
pub fn dcbctl_evt1soce (& self) -> DcbctlEvt1soceR { DcbctlEvt1soceR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
DCBEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
# [inline (always)]
pub fn dcbctl_evt1synce (& self) -> DcbctlEvt1synceR { DcbctlEvt1synceR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bit 8 - 8:8\\]
DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
pub fn dcbctl_evt2srcsel (& self) -> DcbctlEvt2srcselR { DcbctlEvt2srcselR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
pub fn dcbctl_evt2frc_syncsel (& self) -> DcbctlEvt2frcSyncselR { DcbctlEvt2frcSyncselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 10) & 0x3f) as u8) } # [doc = "Bits 16:17 - 17:16\\]
Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal"]
# [inline (always)]
pub fn dcfctl_srcsel (& self) -> DcfctlSrcselR { DcfctlSrcselR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 18 - 18:18\\]
Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled"]
# [inline (always)]
pub fn dcfctl_blanke (& self) -> DcfctlBlankeR { DcfctlBlankeR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted"]
# [inline (always)]
pub fn dcfctl_blankinv (& self) -> DcfctlBlankinvR { DcfctlBlankinvR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bits 20:21 - 21:20\\]
Pulse Select For Blanking &amp; Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved"]
# [inline (always)]
pub fn dcfctl_pulsesel (& self) -> DcfctlPulseselR { DcfctlPulseselR :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:31 - 31:22\\]
Reserved"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 22) & 0x03ff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
# [must_use]
pub fn dcbctl_evt1srcsel (& mut self) -> DcbctlEvt1srcselW < DcbctlDcfctlSpec > { DcbctlEvt1srcselW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
# [must_use]
pub fn dcbctl_evt1frc_syncsel (& mut self) -> DcbctlEvt1frcSyncselW < DcbctlDcfctlSpec > { DcbctlEvt1frcSyncselW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
DCBEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled"]
# [inline (always)]
# [must_use]
pub fn dcbctl_evt1soce (& mut self) -> DcbctlEvt1soceW < DcbctlDcfctlSpec > { DcbctlEvt1soceW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
DCBEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled"]
# [inline (always)]
# [must_use]
pub fn dcbctl_evt1synce (& mut self) -> DcbctlEvt1synceW < DcbctlDcfctlSpec > { DcbctlEvt1synceW :: new (self , 3) } # [doc = "Bits 4:7 - 7:4\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < DcbctlDcfctlSpec > { Reserved1W :: new (self , 4) } # [doc = "Bit 8 - 8:8\\]
DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal"]
# [inline (always)]
# [must_use]
pub fn dcbctl_evt2srcsel (& mut self) -> DcbctlEvt2srcselW < DcbctlDcfctlSpec > { DcbctlEvt2srcselW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal"]
# [inline (always)]
# [must_use]
pub fn dcbctl_evt2frc_syncsel (& mut self) -> DcbctlEvt2frcSyncselW < DcbctlDcfctlSpec > { DcbctlEvt2frcSyncselW :: new (self , 9) } # [doc = "Bits 10:15 - 15:10\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < DcbctlDcfctlSpec > { Reserved2W :: new (self , 10) } # [doc = "Bits 16:17 - 17:16\\]
Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal"]
# [inline (always)]
# [must_use]
pub fn dcfctl_srcsel (& mut self) -> DcfctlSrcselW < DcbctlDcfctlSpec > { DcfctlSrcselW :: new (self , 16) } # [doc = "Bit 18 - 18:18\\]
Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled"]
# [inline (always)]
# [must_use]
pub fn dcfctl_blanke (& mut self) -> DcfctlBlankeW < DcbctlDcfctlSpec > { DcfctlBlankeW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted"]
# [inline (always)]
# [must_use]
pub fn dcfctl_blankinv (& mut self) -> DcfctlBlankinvW < DcbctlDcfctlSpec > { DcfctlBlankinvW :: new (self , 19) } # [doc = "Bits 20:21 - 21:20\\]
Pulse Select For Blanking &amp; Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved"]
# [inline (always)]
# [must_use]
pub fn dcfctl_pulsesel (& mut self) -> DcfctlPulseselW < DcbctlDcfctlSpec > { DcfctlPulseselW :: new (self , 20) } # [doc = "Bits 22:31 - 31:22\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < DcbctlDcfctlSpec > { Reserved3W :: new (self , 22) } } # [doc = "Digital Compare B Control Register/ Digital Compare Filter Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcbctl_dcfctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcbctl_dcfctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcbctlDcfctlSpec ; impl crate :: RegisterSpec for DcbctlDcfctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcbctl_dcfctl::R`](R) reader structure"]
impl crate :: Readable for DcbctlDcfctlSpec { } # [doc = "`write(|w| ..)` method takes [`dcbctl_dcfctl::W`](W) writer structure"]
impl crate :: Writable for DcbctlDcfctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCBCTL_DCFCTL to value 0"]
impl crate :: Resettable for DcbctlDcfctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCCAPCTL_DCFOFFSET (rw) register accessor: Digital Compare Capture Control Register/ Digital Compare Filter Offset Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dccapctl_dcfoffset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccapctl_dcfoffset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dccapctl_dcfoffset`]
module"]
# [doc (alias = "DCCAPCTL_DCFOFFSET")]
pub type DccapctlDcfoffset = crate :: Reg < dccapctl_dcfoffset :: DccapctlDcfoffsetSpec > ; # [doc = "Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"]
pub mod dccapctl_dcfoffset { # [doc = "Register `DCCAPCTL_DCFOFFSET` reader"]
pub type R = crate :: R < DccapctlDcfoffsetSpec > ; # [doc = "Register `DCCAPCTL_DCFOFFSET` writer"]
pub type W = crate :: W < DccapctlDcfoffsetSpec > ; # [doc = "Field `DCCAPCTL_CAPE` reader - 0:0\\]
TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture."]
pub type DccapctlCapeR = crate :: BitReader ; # [doc = "Field `DCCAPCTL_CAPE` writer - 0:0\\]
TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture."]
pub type DccapctlCapeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCCAPCTL_SHDWMODE` reader - 1:1\\]
TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of the DCCAP register will return the shadow register contents. 1 Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will always return the active register contents"]
pub type DccapctlShdwmodeR = crate :: BitReader ; # [doc = "Field `DCCAPCTL_SHDWMODE` writer - 1:1\\]
TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of the DCCAP register will return the shadow register contents. 1 Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will always return the active register contents"]
pub type DccapctlShdwmodeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DCFOFFSET_OFFSET` reader - 31:16\\]
Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the DCFCTL\\[PULSESEL\\]
bit. This offset register is shadowed and the active register is loaded at the reference point defined by DCFCTL\\[PULSESEL\\]. The offset counter is also initialized and begins to count down when the active register is loaded. When the counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is restarted."]
pub type DcfoffsetOffsetR = crate :: FieldReader < u16 > ; # [doc = "Field `DCFOFFSET_OFFSET` writer - 31:16\\]
Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the DCFCTL\\[PULSESEL\\]
bit. This offset register is shadowed and the active register is loaded at the reference point defined by DCFCTL\\[PULSESEL\\]. The offset counter is also initialized and begins to count down when the active register is loaded. When the counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is restarted."]
pub type DcfoffsetOffsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - 0:0\\]
TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture."]
# [inline (always)]
pub fn dccapctl_cape (& self) -> DccapctlCapeR { DccapctlCapeR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of the DCCAP register will return the shadow register contents. 1 Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will always return the active register contents"]
# [inline (always)]
pub fn dccapctl_shdwmode (& self) -> DccapctlShdwmodeR { DccapctlShdwmodeR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 16:31 - 31:16\\]
Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the DCFCTL\\[PULSESEL\\]
bit. This offset register is shadowed and the active register is loaded at the reference point defined by DCFCTL\\[PULSESEL\\]. The offset counter is also initialized and begins to count down when the active register is loaded. When the counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is restarted."]
# [inline (always)]
pub fn dcfoffset_offset (& self) -> DcfoffsetOffsetR { DcfoffsetOffsetR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bit 0 - 0:0\\]
TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture."]
# [inline (always)]
# [must_use]
pub fn dccapctl_cape (& mut self) -> DccapctlCapeW < DccapctlDcfoffsetSpec > { DccapctlCapeW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of the DCCAP register will return the shadow register contents. 1 Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will always return the active register contents"]
# [inline (always)]
# [must_use]
pub fn dccapctl_shdwmode (& mut self) -> DccapctlShdwmodeW < DccapctlDcfoffsetSpec > { DccapctlShdwmodeW :: new (self , 1) } # [doc = "Bits 16:31 - 31:16\\]
Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the DCFCTL\\[PULSESEL\\]
bit. This offset register is shadowed and the active register is loaded at the reference point defined by DCFCTL\\[PULSESEL\\]. The offset counter is also initialized and begins to count down when the active register is loaded. When the counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is restarted."]
# [inline (always)]
# [must_use]
pub fn dcfoffset_offset (& mut self) -> DcfoffsetOffsetW < DccapctlDcfoffsetSpec > { DcfoffsetOffsetW :: new (self , 16) } } # [doc = "Digital Compare Capture Control Register/ Digital Compare Filter Offset Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dccapctl_dcfoffset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dccapctl_dcfoffset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DccapctlDcfoffsetSpec ; impl crate :: RegisterSpec for DccapctlDcfoffsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dccapctl_dcfoffset::R`](R) reader structure"]
impl crate :: Readable for DccapctlDcfoffsetSpec { } # [doc = "`write(|w| ..)` method takes [`dccapctl_dcfoffset::W`](W) writer structure"]
impl crate :: Writable for DccapctlDcfoffsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCCAPCTL_DCFOFFSET to value 0"]
impl crate :: Resettable for DccapctlDcfoffsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCFOFFSETCNT_DCFWINDOW (rw) register accessor: Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfoffsetcnt_dcfwindow::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfoffsetcnt_dcfwindow::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfoffsetcnt_dcfwindow`]
module"]
# [doc (alias = "DCFOFFSETCNT_DCFWINDOW")]
pub type DcfoffsetcntDcfwindow = crate :: Reg < dcfoffsetcnt_dcfwindow :: DcfoffsetcntDcfwindowSpec > ; # [doc = "Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"]
pub mod dcfoffsetcnt_dcfwindow { # [doc = "Register `DCFOFFSETCNT_DCFWINDOW` reader"]
pub type R = crate :: R < DcfoffsetcntDcfwindowSpec > ; # [doc = "Register `DCFOFFSETCNT_DCFWINDOW` writer"]
pub type W = crate :: W < DcfoffsetcntDcfwindowSpec > ; # [doc = "Field `DCFOFFSETCNT_OFFSETCNT` reader - 15:0\\]
Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop."]
pub type DcfoffsetcntOffsetcntR = crate :: FieldReader < u16 > ; # [doc = "Field `DCFOFFSETCNT_OFFSETCNT` writer - 15:0\\]
Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop."]
pub type DcfoffsetcntOffsetcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `DCFWINDOW_WINDOW` reader - 23:16\\]
Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs, the window counter is loaded and begins to count down. If the blanking window is currently active and the offset counter expires, the blanking window counter is restarted. The blanking window can cross a PWM period boundary."]
pub type DcfwindowWindowR = crate :: FieldReader ; # [doc = "Field `DCFWINDOW_WINDOW` writer - 23:16\\]
Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs, the window counter is loaded and begins to count down. If the blanking window is currently active and the offset counter expires, the blanking window counter is restarted. The blanking window can cross a PWM period boundary."]
pub type DcfwindowWindowW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop."]
# [inline (always)]
pub fn dcfoffsetcnt_offsetcnt (& self) -> DcfoffsetcntOffsetcntR { DcfoffsetcntOffsetcntR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:23 - 23:16\\]
Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs, the window counter is loaded and begins to count down. If the blanking window is currently active and the offset counter expires, the blanking window counter is restarted. The blanking window can cross a PWM period boundary."]
# [inline (always)]
pub fn dcfwindow_window (& self) -> DcfwindowWindowR { DcfwindowWindowR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the DCFCTL\\[PULSESEL\\]
bit. The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop."]
# [inline (always)]
# [must_use]
pub fn dcfoffsetcnt_offsetcnt (& mut self) -> DcfoffsetcntOffsetcntW < DcfoffsetcntDcfwindowSpec > { DcfoffsetcntOffsetcntW :: new (self , 0) } # [doc = "Bits 16:23 - 23:16\\]
Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs, the window counter is loaded and begins to count down. If the blanking window is currently active and the offset counter expires, the blanking window counter is restarted. The blanking window can cross a PWM period boundary."]
# [inline (always)]
# [must_use]
pub fn dcfwindow_window (& mut self) -> DcfwindowWindowW < DcfoffsetcntDcfwindowSpec > { DcfwindowWindowW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < DcfoffsetcntDcfwindowSpec > { Reserved1W :: new (self , 24) } } # [doc = "Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfoffsetcnt_dcfwindow::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfoffsetcnt_dcfwindow::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcfoffsetcntDcfwindowSpec ; impl crate :: RegisterSpec for DcfoffsetcntDcfwindowSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcfoffsetcnt_dcfwindow::R`](R) reader structure"]
impl crate :: Readable for DcfoffsetcntDcfwindowSpec { } # [doc = "`write(|w| ..)` method takes [`dcfoffsetcnt_dcfwindow::W`](W) writer structure"]
impl crate :: Writable for DcfoffsetcntDcfwindowSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCFOFFSETCNT_DCFWINDOW to value 0"]
impl crate :: Resettable for DcfoffsetcntDcfwindowSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DCFWINDOWCNT_DCCAP (rw) register accessor: Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfwindowcnt_dccap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfwindowcnt_dccap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfwindowcnt_dccap`]
module"]
# [doc (alias = "DCFWINDOWCNT_DCCAP")]
pub type DcfwindowcntDccap = crate :: Reg < dcfwindowcnt_dccap :: DcfwindowcntDccapSpec > ; # [doc = "Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"]
pub mod dcfwindowcnt_dccap { # [doc = "Register `DCFWINDOWCNT_DCCAP` reader"]
pub type R = crate :: R < DcfwindowcntDccapSpec > ; # [doc = "Register `DCFWINDOWCNT_DCCAP` writer"]
pub type W = crate :: W < DcfwindowcntDccapSpec > ; # [doc = "Field `DCFWINDOWCNT` reader - 7:0\\]
0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."]
pub type DcfwindowcntR = crate :: FieldReader ; # [doc = "Field `DCFWINDOWCNT` writer - 7:0\\]
0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."]
pub type DcfwindowcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `Reserved1` reader - 15:8\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:8\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `DCCAP` reader - 31:16\\]
Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCCAPCLT\\[CAPE\\]
bit to 1. If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by the DCFCTL\\[PULSESEL\\]
bit. Shadowing of DCCAP is enabled and disabled by the DCCAPCTL\\[SHDWMODE\\]
bit. By default this register is shadowed. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of this register will return the shadow register value. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address."]
pub type DccapR = crate :: FieldReader < u16 > ; # [doc = "Field `DCCAP` writer - 31:16\\]
Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCCAPCLT\\[CAPE\\]
bit to 1. If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by the DCFCTL\\[PULSESEL\\]
bit. Shadowing of DCCAP is enabled and disabled by the DCCAPCTL\\[SHDWMODE\\]
bit. By default this register is shadowed. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of this register will return the shadow register value. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address."]
pub type DccapW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."]
# [inline (always)]
pub fn dcfwindowcnt (& self) -> DcfwindowcntR { DcfwindowcntR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:31 - 31:16\\]
Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCCAPCLT\\[CAPE\\]
bit to 1. If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by the DCFCTL\\[PULSESEL\\]
bit. Shadowing of DCCAP is enabled and disabled by the DCCAPCTL\\[SHDWMODE\\]
bit. By default this register is shadowed. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of this register will return the shadow register value. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address."]
# [inline (always)]
pub fn dccap (& self) -> DccapR { DccapR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."]
# [inline (always)]
# [must_use]
pub fn dcfwindowcnt (& mut self) -> DcfwindowcntW < DcfwindowcntDccapSpec > { DcfwindowcntW :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < DcfwindowcntDccapSpec > { Reserved1W :: new (self , 8) } # [doc = "Bits 16:31 - 31:16\\]
Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCCAPCLT\\[CAPE\\]
bit to 1. If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by the DCFCTL\\[PULSESEL\\]
bit. Shadowing of DCCAP is enabled and disabled by the DCCAPCTL\\[SHDWMODE\\]
bit. By default this register is shadowed. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL\\[PULSESEL\\]
bit. CPU reads of this register will return the shadow register value. ΓÇó If DCCAPCTL\\[SHDWMODE\\]
= 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address."]
# [inline (always)]
# [must_use]
pub fn dccap (& mut self) -> DccapW < DcfwindowcntDccapSpec > { DccapW :: new (self , 16) } } # [doc = "Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfwindowcnt_dccap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfwindowcnt_dccap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcfwindowcntDccapSpec ; impl crate :: RegisterSpec for DcfwindowcntDccapSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dcfwindowcnt_dccap::R`](R) reader structure"]
impl crate :: Readable for DcfwindowcntDccapSpec { } # [doc = "`write(|w| ..)` method takes [`dcfwindowcnt_dccap::W`](W) writer structure"]
impl crate :: Writable for DcfwindowcntDccapSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DCFWINDOWCNT_DCCAP to value 0"]
impl crate :: Resettable for DcfwindowcntDccapSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "TOP_IO_MUX"]
pub struct TopIoMux { _marker : PhantomData < * const () > } unsafe impl Send for TopIoMux { } impl TopIoMux { # [doc = r"Pointer to the register block"]
pub const PTR : * const top_io_mux :: RegisterBlock = 0x5a00_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const top_io_mux :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TopIoMux { type Target = top_io_mux :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TopIoMux { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TopIoMux") . finish () } } # [doc = "TOP_IO_MUX"]
pub mod top_io_mux { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { padaa_cfg_reg : PadaaCfgReg , padab_cfg_reg : PadabCfgReg , padac_cfg_reg : PadacCfgReg , padad_cfg_reg : PadadCfgReg , padae_cfg_reg : PadaeCfgReg , padaf_cfg_reg : PadafCfgReg , padag_cfg_reg : PadagCfgReg , padah_cfg_reg : PadahCfgReg , padai_cfg_reg : PadaiCfgReg , padaj_cfg_reg : PadajCfgReg , padak_cfg_reg : PadakCfgReg , padal_cfg_reg : PadalCfgReg , padam_cfg_reg : PadamCfgReg , padan_cfg_reg : PadanCfgReg , padao_cfg_reg : PadaoCfgReg , padap_cfg_reg : PadapCfgReg , padaq_cfg_reg : PadaqCfgReg , padar_cfg_reg : PadarCfgReg , padas_cfg_reg : PadasCfgReg , padat_cfg_reg : PadatCfgReg , padau_cfg_reg : PadauCfgReg , padav_cfg_reg : PadavCfgReg , padaw_cfg_reg : PadawCfgReg , padax_cfg_reg : PadaxCfgReg , usermodeen : Usermodeen , padglblcfgreg : Padglblcfgreg , iocfgkick0 : Iocfgkick0 , iocfgkick1 : Iocfgkick1 , } impl RegisterBlock { # [doc = "0x00 - PADAA_cfg_reg"]
# [inline (always)]
pub const fn padaa_cfg_reg (& self) -> & PadaaCfgReg { & self . padaa_cfg_reg } # [doc = "0x04 - PADAB_cfg_reg"]
# [inline (always)]
pub const fn padab_cfg_reg (& self) -> & PadabCfgReg { & self . padab_cfg_reg } # [doc = "0x08 - PADAC_cfg_reg"]
# [inline (always)]
pub const fn padac_cfg_reg (& self) -> & PadacCfgReg { & self . padac_cfg_reg } # [doc = "0x0c - PADAD_cfg_reg"]
# [inline (always)]
pub const fn padad_cfg_reg (& self) -> & PadadCfgReg { & self . padad_cfg_reg } # [doc = "0x10 - PADAE_cfg_reg"]
# [inline (always)]
pub const fn padae_cfg_reg (& self) -> & PadaeCfgReg { & self . padae_cfg_reg } # [doc = "0x14 - PADAF_cfg_reg"]
# [inline (always)]
pub const fn padaf_cfg_reg (& self) -> & PadafCfgReg { & self . padaf_cfg_reg } # [doc = "0x18 - PADAG_cfg_reg"]
# [inline (always)]
pub const fn padag_cfg_reg (& self) -> & PadagCfgReg { & self . padag_cfg_reg } # [doc = "0x1c - PADAH_cfg_reg"]
# [inline (always)]
pub const fn padah_cfg_reg (& self) -> & PadahCfgReg { & self . padah_cfg_reg } # [doc = "0x20 - PADAI_cfg_reg"]
# [inline (always)]
pub const fn padai_cfg_reg (& self) -> & PadaiCfgReg { & self . padai_cfg_reg } # [doc = "0x24 - PADAJ_cfg_reg"]
# [inline (always)]
pub const fn padaj_cfg_reg (& self) -> & PadajCfgReg { & self . padaj_cfg_reg } # [doc = "0x28 - PADAK_cfg_reg"]
# [inline (always)]
pub const fn padak_cfg_reg (& self) -> & PadakCfgReg { & self . padak_cfg_reg } # [doc = "0x2c - PADAL_cfg_reg"]
# [inline (always)]
pub const fn padal_cfg_reg (& self) -> & PadalCfgReg { & self . padal_cfg_reg } # [doc = "0x30 - PADAM_cfg_reg"]
# [inline (always)]
pub const fn padam_cfg_reg (& self) -> & PadamCfgReg { & self . padam_cfg_reg } # [doc = "0x34 - PADAN_cfg_reg"]
# [inline (always)]
pub const fn padan_cfg_reg (& self) -> & PadanCfgReg { & self . padan_cfg_reg } # [doc = "0x38 - PADAO_cfg_reg"]
# [inline (always)]
pub const fn padao_cfg_reg (& self) -> & PadaoCfgReg { & self . padao_cfg_reg } # [doc = "0x3c - PADAP_cfg_reg"]
# [inline (always)]
pub const fn padap_cfg_reg (& self) -> & PadapCfgReg { & self . padap_cfg_reg } # [doc = "0x40 - PADAQ_cfg_reg"]
# [inline (always)]
pub const fn padaq_cfg_reg (& self) -> & PadaqCfgReg { & self . padaq_cfg_reg } # [doc = "0x44 - PADAR_cfg_reg"]
# [inline (always)]
pub const fn padar_cfg_reg (& self) -> & PadarCfgReg { & self . padar_cfg_reg } # [doc = "0x48 - PADAS_cfg_reg"]
# [inline (always)]
pub const fn padas_cfg_reg (& self) -> & PadasCfgReg { & self . padas_cfg_reg } # [doc = "0x4c - PADAT_cfg_reg"]
# [inline (always)]
pub const fn padat_cfg_reg (& self) -> & PadatCfgReg { & self . padat_cfg_reg } # [doc = "0x50 - PADAU_cfg_reg"]
# [inline (always)]
pub const fn padau_cfg_reg (& self) -> & PadauCfgReg { & self . padau_cfg_reg } # [doc = "0x54 - PADAV_cfg_reg"]
# [inline (always)]
pub const fn padav_cfg_reg (& self) -> & PadavCfgReg { & self . padav_cfg_reg } # [doc = "0x58 - PADAW_cfg_reg"]
# [inline (always)]
pub const fn padaw_cfg_reg (& self) -> & PadawCfgReg { & self . padaw_cfg_reg } # [doc = "0x5c - PADAX_cfg_reg"]
# [inline (always)]
pub const fn padax_cfg_reg (& self) -> & PadaxCfgReg { & self . padax_cfg_reg } # [doc = "0x60 - USERMODEEN"]
# [inline (always)]
pub const fn usermodeen (& self) -> & Usermodeen { & self . usermodeen } # [doc = "0x64 - PADGLBLCFGREG"]
# [inline (always)]
pub const fn padglblcfgreg (& self) -> & Padglblcfgreg { & self . padglblcfgreg } # [doc = "0x68 - IOCFGKICK0"]
# [inline (always)]
pub const fn iocfgkick0 (& self) -> & Iocfgkick0 { & self . iocfgkick0 } # [doc = "0x6c - IOCFGKICK1"]
# [inline (always)]
pub const fn iocfgkick1 (& self) -> & Iocfgkick1 { & self . iocfgkick1 } } # [doc = "PADAA_cfg_reg (rw) register accessor: PADAA_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaa_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaa_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padaa_cfg_reg`]
module"]
# [doc (alias = "PADAA_cfg_reg")]
pub type PadaaCfgReg = crate :: Reg < padaa_cfg_reg :: PadaaCfgRegSpec > ; # [doc = "PADAA_cfg_reg"]
pub mod padaa_cfg_reg { # [doc = "Register `PADAA_cfg_reg` reader"]
pub type R = crate :: R < PadaaCfgRegSpec > ; # [doc = "Register `PADAA_cfg_reg` writer"]
pub type W = crate :: W < PadaaCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadaaCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadaaCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadaaCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadaaCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadaaCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadaaCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadaaCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadaaCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadaaCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAA_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaa_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaa_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadaaCfgRegSpec ; impl crate :: RegisterSpec for PadaaCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padaa_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadaaCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padaa_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadaaCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAA_cfg_reg to value 0"]
impl crate :: Resettable for PadaaCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAB_cfg_reg (rw) register accessor: PADAB_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padab_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padab_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padab_cfg_reg`]
module"]
# [doc (alias = "PADAB_cfg_reg")]
pub type PadabCfgReg = crate :: Reg < padab_cfg_reg :: PadabCfgRegSpec > ; # [doc = "PADAB_cfg_reg"]
pub mod padab_cfg_reg { # [doc = "Register `PADAB_cfg_reg` reader"]
pub type R = crate :: R < PadabCfgRegSpec > ; # [doc = "Register `PADAB_cfg_reg` writer"]
pub type W = crate :: W < PadabCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadabCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadabCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadabCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadabCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadabCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadabCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadabCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadabCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadabCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAB_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padab_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padab_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadabCfgRegSpec ; impl crate :: RegisterSpec for PadabCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padab_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadabCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padab_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadabCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAB_cfg_reg to value 0"]
impl crate :: Resettable for PadabCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAC_cfg_reg (rw) register accessor: PADAC_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padac_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padac_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padac_cfg_reg`]
module"]
# [doc (alias = "PADAC_cfg_reg")]
pub type PadacCfgReg = crate :: Reg < padac_cfg_reg :: PadacCfgRegSpec > ; # [doc = "PADAC_cfg_reg"]
pub mod padac_cfg_reg { # [doc = "Register `PADAC_cfg_reg` reader"]
pub type R = crate :: R < PadacCfgRegSpec > ; # [doc = "Register `PADAC_cfg_reg` writer"]
pub type W = crate :: W < PadacCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadacCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadacCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadacCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadacCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadacCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadacCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadacCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadacCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadacCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAC_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padac_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padac_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadacCfgRegSpec ; impl crate :: RegisterSpec for PadacCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padac_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadacCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padac_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadacCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAC_cfg_reg to value 0"]
impl crate :: Resettable for PadacCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAD_cfg_reg (rw) register accessor: PADAD_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padad_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padad_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padad_cfg_reg`]
module"]
# [doc (alias = "PADAD_cfg_reg")]
pub type PadadCfgReg = crate :: Reg < padad_cfg_reg :: PadadCfgRegSpec > ; # [doc = "PADAD_cfg_reg"]
pub mod padad_cfg_reg { # [doc = "Register `PADAD_cfg_reg` reader"]
pub type R = crate :: R < PadadCfgRegSpec > ; # [doc = "Register `PADAD_cfg_reg` writer"]
pub type W = crate :: W < PadadCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadadCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadadCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadadCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadadCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadadCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadadCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadadCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadadCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadadCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAD_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padad_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padad_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadadCfgRegSpec ; impl crate :: RegisterSpec for PadadCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padad_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadadCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padad_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadadCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAD_cfg_reg to value 0"]
impl crate :: Resettable for PadadCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAE_cfg_reg (rw) register accessor: PADAE_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padae_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padae_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padae_cfg_reg`]
module"]
# [doc (alias = "PADAE_cfg_reg")]
pub type PadaeCfgReg = crate :: Reg < padae_cfg_reg :: PadaeCfgRegSpec > ; # [doc = "PADAE_cfg_reg"]
pub mod padae_cfg_reg { # [doc = "Register `PADAE_cfg_reg` reader"]
pub type R = crate :: R < PadaeCfgRegSpec > ; # [doc = "Register `PADAE_cfg_reg` writer"]
pub type W = crate :: W < PadaeCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadaeCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadaeCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadaeCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadaeCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadaeCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadaeCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadaeCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadaeCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadaeCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAE_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padae_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padae_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadaeCfgRegSpec ; impl crate :: RegisterSpec for PadaeCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padae_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadaeCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padae_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadaeCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAE_cfg_reg to value 0"]
impl crate :: Resettable for PadaeCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAF_cfg_reg (rw) register accessor: PADAF_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaf_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaf_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padaf_cfg_reg`]
module"]
# [doc (alias = "PADAF_cfg_reg")]
pub type PadafCfgReg = crate :: Reg < padaf_cfg_reg :: PadafCfgRegSpec > ; # [doc = "PADAF_cfg_reg"]
pub mod padaf_cfg_reg { # [doc = "Register `PADAF_cfg_reg` reader"]
pub type R = crate :: R < PadafCfgRegSpec > ; # [doc = "Register `PADAF_cfg_reg` writer"]
pub type W = crate :: W < PadafCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadafCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadafCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadafCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadafCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadafCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadafCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadafCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadafCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadafCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAF_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaf_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaf_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadafCfgRegSpec ; impl crate :: RegisterSpec for PadafCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padaf_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadafCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padaf_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadafCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAF_cfg_reg to value 0"]
impl crate :: Resettable for PadafCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAG_cfg_reg (rw) register accessor: PADAG_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padag_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padag_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padag_cfg_reg`]
module"]
# [doc (alias = "PADAG_cfg_reg")]
pub type PadagCfgReg = crate :: Reg < padag_cfg_reg :: PadagCfgRegSpec > ; # [doc = "PADAG_cfg_reg"]
pub mod padag_cfg_reg { # [doc = "Register `PADAG_cfg_reg` reader"]
pub type R = crate :: R < PadagCfgRegSpec > ; # [doc = "Register `PADAG_cfg_reg` writer"]
pub type W = crate :: W < PadagCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadagCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadagCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadagCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadagCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadagCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadagCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadagCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadagCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadagCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAG_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padag_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padag_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadagCfgRegSpec ; impl crate :: RegisterSpec for PadagCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padag_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadagCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padag_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadagCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAG_cfg_reg to value 0"]
impl crate :: Resettable for PadagCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAH_cfg_reg (rw) register accessor: PADAH_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padah_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padah_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padah_cfg_reg`]
module"]
# [doc (alias = "PADAH_cfg_reg")]
pub type PadahCfgReg = crate :: Reg < padah_cfg_reg :: PadahCfgRegSpec > ; # [doc = "PADAH_cfg_reg"]
pub mod padah_cfg_reg { # [doc = "Register `PADAH_cfg_reg` reader"]
pub type R = crate :: R < PadahCfgRegSpec > ; # [doc = "Register `PADAH_cfg_reg` writer"]
pub type W = crate :: W < PadahCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadahCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadahCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadahCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadahCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadahCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadahCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadahCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadahCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadahCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAH_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padah_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padah_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadahCfgRegSpec ; impl crate :: RegisterSpec for PadahCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padah_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadahCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padah_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadahCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAH_cfg_reg to value 0"]
impl crate :: Resettable for PadahCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAI_cfg_reg (rw) register accessor: PADAI_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padai_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padai_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padai_cfg_reg`]
module"]
# [doc (alias = "PADAI_cfg_reg")]
pub type PadaiCfgReg = crate :: Reg < padai_cfg_reg :: PadaiCfgRegSpec > ; # [doc = "PADAI_cfg_reg"]
pub mod padai_cfg_reg { # [doc = "Register `PADAI_cfg_reg` reader"]
pub type R = crate :: R < PadaiCfgRegSpec > ; # [doc = "Register `PADAI_cfg_reg` writer"]
pub type W = crate :: W < PadaiCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadaiCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadaiCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadaiCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadaiCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadaiCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadaiCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadaiCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadaiCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadaiCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAI_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padai_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padai_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadaiCfgRegSpec ; impl crate :: RegisterSpec for PadaiCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padai_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadaiCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padai_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadaiCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAI_cfg_reg to value 0"]
impl crate :: Resettable for PadaiCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAJ_cfg_reg (rw) register accessor: PADAJ_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaj_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaj_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padaj_cfg_reg`]
module"]
# [doc (alias = "PADAJ_cfg_reg")]
pub type PadajCfgReg = crate :: Reg < padaj_cfg_reg :: PadajCfgRegSpec > ; # [doc = "PADAJ_cfg_reg"]
pub mod padaj_cfg_reg { # [doc = "Register `PADAJ_cfg_reg` reader"]
pub type R = crate :: R < PadajCfgRegSpec > ; # [doc = "Register `PADAJ_cfg_reg` writer"]
pub type W = crate :: W < PadajCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadajCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadajCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadajCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadajCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadajCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadajCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadajCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadajCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadajCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAJ_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaj_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaj_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadajCfgRegSpec ; impl crate :: RegisterSpec for PadajCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padaj_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadajCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padaj_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadajCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAJ_cfg_reg to value 0"]
impl crate :: Resettable for PadajCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAK_cfg_reg (rw) register accessor: PADAK_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padak_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padak_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padak_cfg_reg`]
module"]
# [doc (alias = "PADAK_cfg_reg")]
pub type PadakCfgReg = crate :: Reg < padak_cfg_reg :: PadakCfgRegSpec > ; # [doc = "PADAK_cfg_reg"]
pub mod padak_cfg_reg { # [doc = "Register `PADAK_cfg_reg` reader"]
pub type R = crate :: R < PadakCfgRegSpec > ; # [doc = "Register `PADAK_cfg_reg` writer"]
pub type W = crate :: W < PadakCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadakCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadakCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadakCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadakCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadakCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadakCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadakCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadakCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadakCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAK_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padak_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padak_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadakCfgRegSpec ; impl crate :: RegisterSpec for PadakCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padak_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadakCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padak_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadakCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAK_cfg_reg to value 0"]
impl crate :: Resettable for PadakCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAL_cfg_reg (rw) register accessor: PADAL_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padal_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padal_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padal_cfg_reg`]
module"]
# [doc (alias = "PADAL_cfg_reg")]
pub type PadalCfgReg = crate :: Reg < padal_cfg_reg :: PadalCfgRegSpec > ; # [doc = "PADAL_cfg_reg"]
pub mod padal_cfg_reg { # [doc = "Register `PADAL_cfg_reg` reader"]
pub type R = crate :: R < PadalCfgRegSpec > ; # [doc = "Register `PADAL_cfg_reg` writer"]
pub type W = crate :: W < PadalCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadalCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadalCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadalCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadalCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadalCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadalCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadalCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadalCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadalCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAL_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padal_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padal_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadalCfgRegSpec ; impl crate :: RegisterSpec for PadalCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padal_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadalCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padal_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadalCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAL_cfg_reg to value 0"]
impl crate :: Resettable for PadalCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAM_cfg_reg (rw) register accessor: PADAM_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padam_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padam_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padam_cfg_reg`]
module"]
# [doc (alias = "PADAM_cfg_reg")]
pub type PadamCfgReg = crate :: Reg < padam_cfg_reg :: PadamCfgRegSpec > ; # [doc = "PADAM_cfg_reg"]
pub mod padam_cfg_reg { # [doc = "Register `PADAM_cfg_reg` reader"]
pub type R = crate :: R < PadamCfgRegSpec > ; # [doc = "Register `PADAM_cfg_reg` writer"]
pub type W = crate :: W < PadamCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadamCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadamCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadamCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadamCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadamCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadamCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadamCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadamCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadamCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAM_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padam_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padam_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadamCfgRegSpec ; impl crate :: RegisterSpec for PadamCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padam_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadamCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padam_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadamCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAM_cfg_reg to value 0"]
impl crate :: Resettable for PadamCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAN_cfg_reg (rw) register accessor: PADAN_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padan_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padan_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padan_cfg_reg`]
module"]
# [doc (alias = "PADAN_cfg_reg")]
pub type PadanCfgReg = crate :: Reg < padan_cfg_reg :: PadanCfgRegSpec > ; # [doc = "PADAN_cfg_reg"]
pub mod padan_cfg_reg { # [doc = "Register `PADAN_cfg_reg` reader"]
pub type R = crate :: R < PadanCfgRegSpec > ; # [doc = "Register `PADAN_cfg_reg` writer"]
pub type W = crate :: W < PadanCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadanCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadanCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadanCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadanCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadanCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadanCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadanCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadanCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadanCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAN_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padan_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padan_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadanCfgRegSpec ; impl crate :: RegisterSpec for PadanCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padan_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadanCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padan_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadanCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAN_cfg_reg to value 0"]
impl crate :: Resettable for PadanCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAO_cfg_reg (rw) register accessor: PADAO_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padao_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padao_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padao_cfg_reg`]
module"]
# [doc (alias = "PADAO_cfg_reg")]
pub type PadaoCfgReg = crate :: Reg < padao_cfg_reg :: PadaoCfgRegSpec > ; # [doc = "PADAO_cfg_reg"]
pub mod padao_cfg_reg { # [doc = "Register `PADAO_cfg_reg` reader"]
pub type R = crate :: R < PadaoCfgRegSpec > ; # [doc = "Register `PADAO_cfg_reg` writer"]
pub type W = crate :: W < PadaoCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadaoCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadaoCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadaoCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadaoCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadaoCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadaoCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadaoCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadaoCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadaoCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAO_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padao_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padao_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadaoCfgRegSpec ; impl crate :: RegisterSpec for PadaoCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padao_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadaoCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padao_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadaoCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAO_cfg_reg to value 0"]
impl crate :: Resettable for PadaoCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAP_cfg_reg (rw) register accessor: PADAP_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padap_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padap_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padap_cfg_reg`]
module"]
# [doc (alias = "PADAP_cfg_reg")]
pub type PadapCfgReg = crate :: Reg < padap_cfg_reg :: PadapCfgRegSpec > ; # [doc = "PADAP_cfg_reg"]
pub mod padap_cfg_reg { # [doc = "Register `PADAP_cfg_reg` reader"]
pub type R = crate :: R < PadapCfgRegSpec > ; # [doc = "Register `PADAP_cfg_reg` writer"]
pub type W = crate :: W < PadapCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadapCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadapCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadapCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadapCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadapCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadapCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadapCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadapCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadapCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAP_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padap_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padap_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadapCfgRegSpec ; impl crate :: RegisterSpec for PadapCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padap_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadapCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padap_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadapCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAP_cfg_reg to value 0"]
impl crate :: Resettable for PadapCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAQ_cfg_reg (rw) register accessor: PADAQ_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaq_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaq_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padaq_cfg_reg`]
module"]
# [doc (alias = "PADAQ_cfg_reg")]
pub type PadaqCfgReg = crate :: Reg < padaq_cfg_reg :: PadaqCfgRegSpec > ; # [doc = "PADAQ_cfg_reg"]
pub mod padaq_cfg_reg { # [doc = "Register `PADAQ_cfg_reg` reader"]
pub type R = crate :: R < PadaqCfgRegSpec > ; # [doc = "Register `PADAQ_cfg_reg` writer"]
pub type W = crate :: W < PadaqCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadaqCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadaqCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadaqCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadaqCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadaqCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadaqCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadaqCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadaqCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadaqCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAQ_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaq_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaq_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadaqCfgRegSpec ; impl crate :: RegisterSpec for PadaqCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padaq_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadaqCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padaq_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadaqCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAQ_cfg_reg to value 0"]
impl crate :: Resettable for PadaqCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAR_cfg_reg (rw) register accessor: PADAR_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padar_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padar_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padar_cfg_reg`]
module"]
# [doc (alias = "PADAR_cfg_reg")]
pub type PadarCfgReg = crate :: Reg < padar_cfg_reg :: PadarCfgRegSpec > ; # [doc = "PADAR_cfg_reg"]
pub mod padar_cfg_reg { # [doc = "Register `PADAR_cfg_reg` reader"]
pub type R = crate :: R < PadarCfgRegSpec > ; # [doc = "Register `PADAR_cfg_reg` writer"]
pub type W = crate :: W < PadarCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadarCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadarCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadarCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadarCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadarCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadarCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadarCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadarCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadarCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAR_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padar_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padar_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadarCfgRegSpec ; impl crate :: RegisterSpec for PadarCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padar_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadarCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padar_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadarCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAR_cfg_reg to value 0"]
impl crate :: Resettable for PadarCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAS_cfg_reg (rw) register accessor: PADAS_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padas_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padas_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padas_cfg_reg`]
module"]
# [doc (alias = "PADAS_cfg_reg")]
pub type PadasCfgReg = crate :: Reg < padas_cfg_reg :: PadasCfgRegSpec > ; # [doc = "PADAS_cfg_reg"]
pub mod padas_cfg_reg { # [doc = "Register `PADAS_cfg_reg` reader"]
pub type R = crate :: R < PadasCfgRegSpec > ; # [doc = "Register `PADAS_cfg_reg` writer"]
pub type W = crate :: W < PadasCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadasCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadasCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadasCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadasCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadasCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadasCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadasCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadasCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadasCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAS_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padas_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padas_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadasCfgRegSpec ; impl crate :: RegisterSpec for PadasCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padas_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadasCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padas_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadasCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAS_cfg_reg to value 0"]
impl crate :: Resettable for PadasCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAT_cfg_reg (rw) register accessor: PADAT_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padat_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padat_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padat_cfg_reg`]
module"]
# [doc (alias = "PADAT_cfg_reg")]
pub type PadatCfgReg = crate :: Reg < padat_cfg_reg :: PadatCfgRegSpec > ; # [doc = "PADAT_cfg_reg"]
pub mod padat_cfg_reg { # [doc = "Register `PADAT_cfg_reg` reader"]
pub type R = crate :: R < PadatCfgRegSpec > ; # [doc = "Register `PADAT_cfg_reg` writer"]
pub type W = crate :: W < PadatCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadatCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadatCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadatCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadatCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadatCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadatCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadatCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadatCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadatCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAT_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padat_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padat_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadatCfgRegSpec ; impl crate :: RegisterSpec for PadatCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padat_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadatCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padat_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadatCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAT_cfg_reg to value 0"]
impl crate :: Resettable for PadatCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAU_cfg_reg (rw) register accessor: PADAU_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padau_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padau_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padau_cfg_reg`]
module"]
# [doc (alias = "PADAU_cfg_reg")]
pub type PadauCfgReg = crate :: Reg < padau_cfg_reg :: PadauCfgRegSpec > ; # [doc = "PADAU_cfg_reg"]
pub mod padau_cfg_reg { # [doc = "Register `PADAU_cfg_reg` reader"]
pub type R = crate :: R < PadauCfgRegSpec > ; # [doc = "Register `PADAU_cfg_reg` writer"]
pub type W = crate :: W < PadauCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadauCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadauCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadauCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadauCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadauCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadauCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadauCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadauCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadauCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAU_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padau_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padau_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadauCfgRegSpec ; impl crate :: RegisterSpec for PadauCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padau_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadauCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padau_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadauCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAU_cfg_reg to value 0"]
impl crate :: Resettable for PadauCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAV_cfg_reg (rw) register accessor: PADAV_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padav_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padav_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padav_cfg_reg`]
module"]
# [doc (alias = "PADAV_cfg_reg")]
pub type PadavCfgReg = crate :: Reg < padav_cfg_reg :: PadavCfgRegSpec > ; # [doc = "PADAV_cfg_reg"]
pub mod padav_cfg_reg { # [doc = "Register `PADAV_cfg_reg` reader"]
pub type R = crate :: R < PadavCfgRegSpec > ; # [doc = "Register `PADAV_cfg_reg` writer"]
pub type W = crate :: W < PadavCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadavCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadavCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadavCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadavCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadavCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadavCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadavCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadavCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadavCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAV_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padav_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padav_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadavCfgRegSpec ; impl crate :: RegisterSpec for PadavCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padav_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadavCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padav_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadavCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAV_cfg_reg to value 0"]
impl crate :: Resettable for PadavCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAW_cfg_reg (rw) register accessor: PADAW_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaw_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaw_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padaw_cfg_reg`]
module"]
# [doc (alias = "PADAW_cfg_reg")]
pub type PadawCfgReg = crate :: Reg < padaw_cfg_reg :: PadawCfgRegSpec > ; # [doc = "PADAW_cfg_reg"]
pub mod padaw_cfg_reg { # [doc = "Register `PADAW_cfg_reg` reader"]
pub type R = crate :: R < PadawCfgRegSpec > ; # [doc = "Register `PADAW_cfg_reg` writer"]
pub type W = crate :: W < PadawCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadawCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadawCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadawCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadawCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadawCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadawCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadawCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadawCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadawCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAW_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padaw_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padaw_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadawCfgRegSpec ; impl crate :: RegisterSpec for PadawCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padaw_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadawCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padaw_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadawCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAW_cfg_reg to value 0"]
impl crate :: Resettable for PadawCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADAX_cfg_reg (rw) register accessor: PADAX_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padax_cfg_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padax_cfg_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padax_cfg_reg`]
module"]
# [doc (alias = "PADAX_cfg_reg")]
pub type PadaxCfgReg = crate :: Reg < padax_cfg_reg :: PadaxCfgRegSpec > ; # [doc = "PADAX_cfg_reg"]
pub mod padax_cfg_reg { # [doc = "Register `PADAX_cfg_reg` reader"]
pub type R = crate :: R < PadaxCfgRegSpec > ; # [doc = "Register `PADAX_cfg_reg` writer"]
pub type W = crate :: W < PadaxCfgRegSpec > ; # [doc = "Field `func_sel` reader - 3:0\\]
Function select"]
pub type FuncSelR = crate :: FieldReader ; # [doc = "Field `func_sel` writer - 3:0\\]
Function select"]
pub type FuncSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ie_override_ctrl` reader - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `ie_override_ctrl` writer - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
pub type IeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ie_override` reader - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideR = crate :: BitReader ; # [doc = "Field `ie_override` writer - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
pub type IeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override_ctrl` reader - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlR = crate :: BitReader ; # [doc = "Field `oe_override_ctrl` writer - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
pub type OeOverrideCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `oe_override` reader - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideR = crate :: BitReader ; # [doc = "Field `oe_override` writer - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
pub type OeOverrideW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pi` reader - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiR = crate :: BitReader ; # [doc = "Field `pi` writer - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
pub type PiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `pupdsel` reader - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselR = crate :: BitReader ; # [doc = "Field `pupdsel` writer - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
pub type PupdselW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sc1` reader - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1R = crate :: BitReader ; # [doc = "Field `sc1` writer - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
pub type Sc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:11\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:11\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 21 , u32 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
pub fn func_sel (& self) -> FuncSelR { FuncSelR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
pub fn ie_override_ctrl (& self) -> IeOverrideCtrlR { IeOverrideCtrlR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
pub fn ie_override (& self) -> IeOverrideR { IeOverrideR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
pub fn oe_override_ctrl (& self) -> OeOverrideCtrlR { OeOverrideCtrlR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
pub fn oe_override (& self) -> OeOverrideR { OeOverrideR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
pub fn pi (& self) -> PiR { PiR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
pub fn pupdsel (& self) -> PupdselR { PupdselR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
pub fn sc1 (& self) -> Sc1R { Sc1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 11) & 0x001f_ffff) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Function select"]
# [inline (always)]
# [must_use]
pub fn func_sel (& mut self) -> FuncSelW < PadaxCfgRegSpec > { FuncSelW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn ie_override_ctrl (& mut self) -> IeOverrideCtrlW < PadaxCfgRegSpec > { IeOverrideCtrlW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core)"]
# [inline (always)]
# [must_use]
pub fn ie_override (& mut self) -> IeOverrideW < PadaxCfgRegSpec > { IeOverrideW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware"]
# [inline (always)]
# [must_use]
pub fn oe_override_ctrl (& mut self) -> OeOverrideCtrlW < PadaxCfgRegSpec > { OeOverrideCtrlW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
Active Low Output Override, 0: Output is enabled 1: Output disabled"]
# [inline (always)]
# [must_use]
pub fn oe_override (& mut self) -> OeOverrideW < PadaxCfgRegSpec > { OeOverrideW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
Pull Inhibit/Pull Disable 0 -- Enable"]
# [inline (always)]
# [must_use]
pub fn pi (& mut self) -> PiW < PadaxCfgRegSpec > { PiW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Pullup/PullDown Selection 0 -- Pull Down"]
# [inline (always)]
# [must_use]
pub fn pupdsel (& mut self) -> PupdselW < PadaxCfgRegSpec > { PupdselW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate."]
# [inline (always)]
# [must_use]
pub fn sc1 (& mut self) -> Sc1W < PadaxCfgRegSpec > { Sc1W :: new (self , 10) } # [doc = "Bits 11:31 - 31:11\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < PadaxCfgRegSpec > { NuW :: new (self , 11) } } # [doc = "PADAX_cfg_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`padax_cfg_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padax_cfg_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadaxCfgRegSpec ; impl crate :: RegisterSpec for PadaxCfgRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padax_cfg_reg::R`](R) reader structure"]
impl crate :: Readable for PadaxCfgRegSpec { } # [doc = "`write(|w| ..)` method takes [`padax_cfg_reg::W`](W) writer structure"]
impl crate :: Writable for PadaxCfgRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADAX_cfg_reg to value 0"]
impl crate :: Resettable for PadaxCfgRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "USERMODEEN (rw) register accessor: USERMODEEN\n\nYou can [`read`](crate::Reg::read) this register and get [`usermodeen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usermodeen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usermodeen`]
module"]
# [doc (alias = "USERMODEEN")]
pub type Usermodeen = crate :: Reg < usermodeen :: UsermodeenSpec > ; # [doc = "USERMODEEN"]
pub mod usermodeen { # [doc = "Register `USERMODEEN` reader"]
pub type R = crate :: R < UsermodeenSpec > ; # [doc = "Register `USERMODEEN` writer"]
pub type W = crate :: W < UsermodeenSpec > ; # [doc = "Field `USERMODEEN` reader - 31:0\\]
Write 0XADADADAD to enable user mode write access to IO CFG space"]
pub type UsermodeenR = crate :: FieldReader < u32 > ; # [doc = "Field `USERMODEEN` writer - 31:0\\]
Write 0XADADADAD to enable user mode write access to IO CFG space"]
pub type UsermodeenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Write 0XADADADAD to enable user mode write access to IO CFG space"]
# [inline (always)]
pub fn usermodeen (& self) -> UsermodeenR { UsermodeenR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Write 0XADADADAD to enable user mode write access to IO CFG space"]
# [inline (always)]
# [must_use]
pub fn usermodeen (& mut self) -> UsermodeenW < UsermodeenSpec > { UsermodeenW :: new (self , 0) } } # [doc = "USERMODEEN\n\nYou can [`read`](crate::Reg::read) this register and get [`usermodeen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usermodeen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UsermodeenSpec ; impl crate :: RegisterSpec for UsermodeenSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`usermodeen::R`](R) reader structure"]
impl crate :: Readable for UsermodeenSpec { } # [doc = "`write(|w| ..)` method takes [`usermodeen::W`](W) writer structure"]
impl crate :: Writable for UsermodeenSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets USERMODEEN to value 0"]
impl crate :: Resettable for UsermodeenSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADGLBLCFGREG (rw) register accessor: PADGLBLCFGREG\n\nYou can [`read`](crate::Reg::read) this register and get [`padglblcfgreg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padglblcfgreg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padglblcfgreg`]
module"]
# [doc (alias = "PADGLBLCFGREG")]
pub type Padglblcfgreg = crate :: Reg < padglblcfgreg :: PadglblcfgregSpec > ; # [doc = "PADGLBLCFGREG"]
pub mod padglblcfgreg { # [doc = "Register `PADGLBLCFGREG` reader"]
pub type R = crate :: R < PadglblcfgregSpec > ; # [doc = "Register `PADGLBLCFGREG` writer"]
pub type W = crate :: W < PadglblcfgregSpec > ; # [doc = "Field `PADGLBLCFGREG` reader - 31:0\\]
2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs. 3 : global_ie_n_val - Active low 10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs. 11 : global_oe_n_val - Active low 18:16 : global_pi_ctl - Write 3'b111 to pass global_pi_val and global_pu_val to all the IOs 19 : global_pi_val 20 : global_pu_val"]
pub type PadglblcfgregR = crate :: FieldReader < u32 > ; # [doc = "Field `PADGLBLCFGREG` writer - 31:0\\]
2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs. 3 : global_ie_n_val - Active low 10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs. 11 : global_oe_n_val - Active low 18:16 : global_pi_ctl - Write 3'b111 to pass global_pi_val and global_pu_val to all the IOs 19 : global_pi_val 20 : global_pu_val"]
pub type PadglblcfgregW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs. 3 : global_ie_n_val - Active low 10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs. 11 : global_oe_n_val - Active low 18:16 : global_pi_ctl - Write 3'b111 to pass global_pi_val and global_pu_val to all the IOs 19 : global_pi_val 20 : global_pu_val"]
# [inline (always)]
pub fn padglblcfgreg (& self) -> PadglblcfgregR { PadglblcfgregR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs. 3 : global_ie_n_val - Active low 10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs. 11 : global_oe_n_val - Active low 18:16 : global_pi_ctl - Write 3'b111 to pass global_pi_val and global_pu_val to all the IOs 19 : global_pi_val 20 : global_pu_val"]
# [inline (always)]
# [must_use]
pub fn padglblcfgreg (& mut self) -> PadglblcfgregW < PadglblcfgregSpec > { PadglblcfgregW :: new (self , 0) } } # [doc = "PADGLBLCFGREG\n\nYou can [`read`](crate::Reg::read) this register and get [`padglblcfgreg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`padglblcfgreg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PadglblcfgregSpec ; impl crate :: RegisterSpec for PadglblcfgregSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`padglblcfgreg::R`](R) reader structure"]
impl crate :: Readable for PadglblcfgregSpec { } # [doc = "`write(|w| ..)` method takes [`padglblcfgreg::W`](W) writer structure"]
impl crate :: Writable for PadglblcfgregSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADGLBLCFGREG to value 0"]
impl crate :: Resettable for PadglblcfgregSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IOCFGKICK0 (rw) register accessor: IOCFGKICK0\n\nYou can [`read`](crate::Reg::read) this register and get [`iocfgkick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocfgkick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iocfgkick0`]
module"]
# [doc (alias = "IOCFGKICK0")]
pub type Iocfgkick0 = crate :: Reg < iocfgkick0 :: Iocfgkick0Spec > ; # [doc = "IOCFGKICK0"]
pub mod iocfgkick0 { # [doc = "Register `IOCFGKICK0` reader"]
pub type R = crate :: R < Iocfgkick0Spec > ; # [doc = "Register `IOCFGKICK0` writer"]
pub type W = crate :: W < Iocfgkick0Spec > ; # [doc = "Field `IOCFGKICK0` reader - 31:0\\]
Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the above PIN MUX registers (including IOCFGKICK1)"]
pub type Iocfgkick0R = crate :: FieldReader < u32 > ; # [doc = "Field `IOCFGKICK0` writer - 31:0\\]
Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the above PIN MUX registers (including IOCFGKICK1)"]
pub type Iocfgkick0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the above PIN MUX registers (including IOCFGKICK1)"]
# [inline (always)]
pub fn iocfgkick0 (& self) -> Iocfgkick0R { Iocfgkick0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the above PIN MUX registers (including IOCFGKICK1)"]
# [inline (always)]
# [must_use]
pub fn iocfgkick0 (& mut self) -> Iocfgkick0W < Iocfgkick0Spec > { Iocfgkick0W :: new (self , 0) } } # [doc = "IOCFGKICK0\n\nYou can [`read`](crate::Reg::read) this register and get [`iocfgkick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocfgkick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iocfgkick0Spec ; impl crate :: RegisterSpec for Iocfgkick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`iocfgkick0::R`](R) reader structure"]
impl crate :: Readable for Iocfgkick0Spec { } # [doc = "`write(|w| ..)` method takes [`iocfgkick0::W`](W) writer structure"]
impl crate :: Writable for Iocfgkick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IOCFGKICK0 to value 0"]
impl crate :: Resettable for Iocfgkick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "IOCFGKICK1 (rw) register accessor: IOCFGKICK1\n\nYou can [`read`](crate::Reg::read) this register and get [`iocfgkick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocfgkick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iocfgkick1`]
module"]
# [doc (alias = "IOCFGKICK1")]
pub type Iocfgkick1 = crate :: Reg < iocfgkick1 :: Iocfgkick1Spec > ; # [doc = "IOCFGKICK1"]
pub mod iocfgkick1 { # [doc = "Register `IOCFGKICK1` reader"]
pub type R = crate :: R < Iocfgkick1Spec > ; # [doc = "Register `IOCFGKICK1` writer"]
pub type W = crate :: W < Iocfgkick1Spec > ; # [doc = "Field `IOCFGKICK1` reader - 31:0\\]
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to IOCFGKICK1."]
pub type Iocfgkick1R = crate :: FieldReader < u32 > ; # [doc = "Field `IOCFGKICK1` writer - 31:0\\]
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to IOCFGKICK1."]
pub type Iocfgkick1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to IOCFGKICK1."]
# [inline (always)]
pub fn iocfgkick1 (& self) -> Iocfgkick1R { Iocfgkick1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to IOCFGKICK1."]
# [inline (always)]
# [must_use]
pub fn iocfgkick1 (& mut self) -> Iocfgkick1W < Iocfgkick1Spec > { Iocfgkick1W :: new (self , 0) } } # [doc = "IOCFGKICK1\n\nYou can [`read`](crate::Reg::read) this register and get [`iocfgkick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocfgkick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iocfgkick1Spec ; impl crate :: RegisterSpec for Iocfgkick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`iocfgkick1::R`](R) reader structure"]
impl crate :: Readable for Iocfgkick1Spec { } # [doc = "`write(|w| ..)` method takes [`iocfgkick1::W`](W) writer structure"]
impl crate :: Writable for Iocfgkick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IOCFGKICK1 to value 0"]
impl crate :: Resettable for Iocfgkick1Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_PRCM"]
pub struct AppPrcm { _marker : PhantomData < * const () > } unsafe impl Send for AppPrcm { } impl AppPrcm { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_prcm :: RegisterBlock = 0x5a04_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_prcm :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppPrcm { type Target = app_prcm :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppPrcm { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppPrcm") . finish () } } # [doc = "APP_PRCM"]
pub mod app_prcm { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , cpuclkctl : Cpuclkctl , canclkctl : Canclkctl , spiclkctl : Spiclkctl , qspiclkctl : Qspiclkctl , topssclkctl : Topssclkctl , rticlkctl : Rticlkctl , wdtclkctl : Wdtclkctl , uart1clkctl : Uart1clkctl , uart2clkctl : Uart2clkctl , i2cclkctl : I2cclkctl , linclkctl : Linclkctl , reserved0 : Reserved0 , reserved1 : Reserved1 , reserved2 : Reserved2 , reserved3 : Reserved3 , vbusclkgate0 : Vbusclkgate0 , vbusclkgate1 : Vbusclkgate1 , vbusclkgate2 : Vbusclkgate2 , blockreset0 : Blockreset0 , blockreset1 : Blockreset1 , _reserved21 : [u8 ; 0x0fb4]
, lock0_kick0 : Lock0Kick0 , lock0_kick1 : Lock0Kick1 , intr_raw_status : IntrRawStatus , intr_enabled_status_clear : IntrEnabledStatusClear , intr_enable : IntrEnable , intr_enable_clear : IntrEnableClear , eoi : Eoi , fault_address : FaultAddress , fault_type_status : FaultTypeStatus , fault_attr_status : FaultAttrStatus , fault_clear : FaultClear , } impl RegisterBlock { # [doc = "0x00 - PID register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - CPUCLKCTL"]
# [inline (always)]
pub const fn cpuclkctl (& self) -> & Cpuclkctl { & self . cpuclkctl } # [doc = "0x08 - CANCLKCTL"]
# [inline (always)]
pub const fn canclkctl (& self) -> & Canclkctl { & self . canclkctl } # [doc = "0x0c - SPICLKCTL"]
# [inline (always)]
pub const fn spiclkctl (& self) -> & Spiclkctl { & self . spiclkctl } # [doc = "0x10 - QSPICLKCTL"]
# [inline (always)]
pub const fn qspiclkctl (& self) -> & Qspiclkctl { & self . qspiclkctl } # [doc = "0x14 - TOPSSCLKCTL"]
# [inline (always)]
pub const fn topssclkctl (& self) -> & Topssclkctl { & self . topssclkctl } # [doc = "0x18 - RTICLKCTL"]
# [inline (always)]
pub const fn rticlkctl (& self) -> & Rticlkctl { & self . rticlkctl } # [doc = "0x1c - WDTCLKCTL"]
# [inline (always)]
pub const fn wdtclkctl (& self) -> & Wdtclkctl { & self . wdtclkctl } # [doc = "0x20 - UART1CLKCTL"]
# [inline (always)]
pub const fn uart1clkctl (& self) -> & Uart1clkctl { & self . uart1clkctl } # [doc = "0x24 - UART2CLKCTL"]
# [inline (always)]
pub const fn uart2clkctl (& self) -> & Uart2clkctl { & self . uart2clkctl } # [doc = "0x28 - I2CCLKCTL"]
# [inline (always)]
pub const fn i2cclkctl (& self) -> & I2cclkctl { & self . i2cclkctl } # [doc = "0x2c - LINCLKCTL"]
# [inline (always)]
pub const fn linclkctl (& self) -> & Linclkctl { & self . linclkctl } # [doc = "0x30 - RESERVED0"]
# [inline (always)]
pub const fn reserved0 (& self) -> & Reserved0 { & self . reserved0 } # [doc = "0x34 - RESERVED1"]
# [inline (always)]
pub const fn reserved1 (& self) -> & Reserved1 { & self . reserved1 } # [doc = "0x38 - RESERVED2"]
# [inline (always)]
pub const fn reserved2 (& self) -> & Reserved2 { & self . reserved2 } # [doc = "0x3c - RESERVED3"]
# [inline (always)]
pub const fn reserved3 (& self) -> & Reserved3 { & self . reserved3 } # [doc = "0x40 - VBUSCLKGATE0"]
# [inline (always)]
pub const fn vbusclkgate0 (& self) -> & Vbusclkgate0 { & self . vbusclkgate0 } # [doc = "0x44 - VBUSCLKGATE1"]
# [inline (always)]
pub const fn vbusclkgate1 (& self) -> & Vbusclkgate1 { & self . vbusclkgate1 } # [doc = "0x48 - VBUSCLKGATE2"]
# [inline (always)]
pub const fn vbusclkgate2 (& self) -> & Vbusclkgate2 { & self . vbusclkgate2 } # [doc = "0x4c - BLOCKRESET0"]
# [inline (always)]
pub const fn blockreset0 (& self) -> & Blockreset0 { & self . blockreset0 } # [doc = "0x50 - BLOCKRESET1"]
# [inline (always)]
pub const fn blockreset1 (& self) -> & Blockreset1 { & self . blockreset1 } # [doc = "0x1008 - - KICK0 component"]
# [inline (always)]
pub const fn lock0_kick0 (& self) -> & Lock0Kick0 { & self . lock0_kick0 } # [doc = "0x100c - - KICK1 component"]
# [inline (always)]
pub const fn lock0_kick1 (& self) -> & Lock0Kick1 { & self . lock0_kick1 } # [doc = "0x1010 - Interrupt Raw Status/Set Register"]
# [inline (always)]
pub const fn intr_raw_status (& self) -> & IntrRawStatus { & self . intr_raw_status } # [doc = "0x1014 - Interrupt Enabled Status/Clear register"]
# [inline (always)]
pub const fn intr_enabled_status_clear (& self) -> & IntrEnabledStatusClear { & self . intr_enabled_status_clear } # [doc = "0x1018 - Interrupt Enable register"]
# [inline (always)]
pub const fn intr_enable (& self) -> & IntrEnable { & self . intr_enable } # [doc = "0x101c - Interrupt Enable Clear register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x1020 - EOI register"]
# [inline (always)]
pub const fn eoi (& self) -> & Eoi { & self . eoi } # [doc = "0x1024 - Fault Address register"]
# [inline (always)]
pub const fn fault_address (& self) -> & FaultAddress { & self . fault_address } # [doc = "0x1028 - Fault Type Status register"]
# [inline (always)]
pub const fn fault_type_status (& self) -> & FaultTypeStatus { & self . fault_type_status } # [doc = "0x102c - Fault Attribute Status register"]
# [inline (always)]
pub const fn fault_attr_status (& self) -> & FaultAttrStatus { & self . fault_attr_status } # [doc = "0x1030 - Fault Clear register"]
# [inline (always)]
pub const fn fault_clear (& self) -> & FaultClear { & self . fault_clear } } # [doc = "PID (rw) register accessor: PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `PID_W6_O0` reader - "]
pub type PidW6O0R = crate :: FieldReader ; # [doc = "Field `PID_W6_O0` writer - "]
pub type PidW6O0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PID_W2_O6` reader - "]
pub type PidW2O6R = crate :: FieldReader ; # [doc = "Field `PID_W2_O6` writer - "]
pub type PidW2O6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PID_W3_O8` reader - "]
pub type PidW3O8R = crate :: FieldReader ; # [doc = "Field `PID_W3_O8` writer - "]
pub type PidW3O8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PID_W5_O11` reader - "]
pub type PidW5O11R = crate :: FieldReader ; # [doc = "Field `PID_W5_O11` writer - "]
pub type PidW5O11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PID_W16_O16` reader - "]
pub type PidW16O16R = crate :: FieldReader < u16 > ; # [doc = "Field `PID_W16_O16` writer - "]
pub type PidW16O16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5"]
# [inline (always)]
pub fn pid_w6_o0 (& self) -> PidW6O0R { PidW6O0R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7"]
# [inline (always)]
pub fn pid_w2_o6 (& self) -> PidW2O6R { PidW2O6R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10"]
# [inline (always)]
pub fn pid_w3_o8 (& self) -> PidW3O8R { PidW3O8R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15"]
# [inline (always)]
pub fn pid_w5_o11 (& self) -> PidW5O11R { PidW5O11R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn pid_w16_o16 (& self) -> PidW16O16R { PidW16O16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5"]
# [inline (always)]
# [must_use]
pub fn pid_w6_o0 (& mut self) -> PidW6O0W < PidSpec > { PidW6O0W :: new (self , 0) } # [doc = "Bits 6:7"]
# [inline (always)]
# [must_use]
pub fn pid_w2_o6 (& mut self) -> PidW2O6W < PidSpec > { PidW2O6W :: new (self , 6) } # [doc = "Bits 8:10"]
# [inline (always)]
# [must_use]
pub fn pid_w3_o8 (& mut self) -> PidW3O8W < PidSpec > { PidW3O8W :: new (self , 8) } # [doc = "Bits 11:15"]
# [inline (always)]
# [must_use]
pub fn pid_w5_o11 (& mut self) -> PidW5O11W < PidSpec > { PidW5O11W :: new (self , 11) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn pid_w16_o16 (& mut self) -> PidW16O16W < PidSpec > { PidW16O16W :: new (self , 16) } } # [doc = "PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CPUCLKCTL (rw) register accessor: CPUCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`cpuclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpuclkctl`]
module"]
# [doc (alias = "CPUCLKCTL")]
pub type Cpuclkctl = crate :: Reg < cpuclkctl :: CpuclkctlSpec > ; # [doc = "CPUCLKCTL"]
pub mod cpuclkctl { # [doc = "Register `CPUCLKCTL` reader"]
pub type R = crate :: R < CpuclkctlSpec > ; # [doc = "Register `CPUCLKCTL` writer"]
pub type W = crate :: W < CpuclkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
Slect the source clock:#br#0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
Slect the source clock:#br#0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Slect the source clock:#br#0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Slect the source clock:#br#0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < CpuclkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < CpuclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < CpuclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < CpuclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < CpuclkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < CpuclkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "CPUCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`cpuclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CpuclkctlSpec ; impl crate :: RegisterSpec for CpuclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cpuclkctl::R`](R) reader structure"]
impl crate :: Readable for CpuclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`cpuclkctl::W`](W) writer structure"]
impl crate :: Writable for CpuclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CPUCLKCTL to value 0"]
impl crate :: Resettable for CpuclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CANCLKCTL (rw) register accessor: CANCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`canclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`canclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@canclkctl`]
module"]
# [doc (alias = "CANCLKCTL")]
pub type Canclkctl = crate :: Reg < canclkctl :: CanclkctlSpec > ; # [doc = "CANCLKCTL"]
pub mod canclkctl { # [doc = "Register `CANCLKCTL` reader"]
pub type R = crate :: R < CanclkctlSpec > ; # [doc = "Register `CANCLKCTL` writer"]
pub type W = crate :: W < CanclkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < CanclkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < CanclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < CanclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < CanclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < CanclkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < CanclkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "CANCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`canclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`canclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CanclkctlSpec ; impl crate :: RegisterSpec for CanclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`canclkctl::R`](R) reader structure"]
impl crate :: Readable for CanclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`canclkctl::W`](W) writer structure"]
impl crate :: Writable for CanclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CANCLKCTL to value 0"]
impl crate :: Resettable for CanclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPICLKCTL (rw) register accessor: SPICLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`spiclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spiclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spiclkctl`]
module"]
# [doc (alias = "SPICLKCTL")]
pub type Spiclkctl = crate :: Reg < spiclkctl :: SpiclkctlSpec > ; # [doc = "SPICLKCTL"]
pub mod spiclkctl { # [doc = "Register `SPICLKCTL` reader"]
pub type R = crate :: R < SpiclkctlSpec > ; # [doc = "Register `SPICLKCTL` writer"]
pub type W = crate :: W < SpiclkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < SpiclkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < SpiclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < SpiclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < SpiclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < SpiclkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < SpiclkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "SPICLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`spiclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spiclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiclkctlSpec ; impl crate :: RegisterSpec for SpiclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spiclkctl::R`](R) reader structure"]
impl crate :: Readable for SpiclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`spiclkctl::W`](W) writer structure"]
impl crate :: Writable for SpiclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPICLKCTL to value 0"]
impl crate :: Resettable for SpiclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "QSPICLKCTL (rw) register accessor: QSPICLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`qspiclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qspiclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qspiclkctl`]
module"]
# [doc (alias = "QSPICLKCTL")]
pub type Qspiclkctl = crate :: Reg < qspiclkctl :: QspiclkctlSpec > ; # [doc = "QSPICLKCTL"]
pub mod qspiclkctl { # [doc = "Register `QSPICLKCTL` reader"]
pub type R = crate :: R < QspiclkctlSpec > ; # [doc = "Register `QSPICLKCTL` writer"]
pub type W = crate :: W < QspiclkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < QspiclkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < QspiclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < QspiclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < QspiclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < QspiclkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < QspiclkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "QSPICLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`qspiclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qspiclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct QspiclkctlSpec ; impl crate :: RegisterSpec for QspiclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`qspiclkctl::R`](R) reader structure"]
impl crate :: Readable for QspiclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`qspiclkctl::W`](W) writer structure"]
impl crate :: Writable for QspiclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets QSPICLKCTL to value 0"]
impl crate :: Resettable for QspiclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TOPSSCLKCTL (rw) register accessor: TOPSSCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`topssclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`topssclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@topssclkctl`]
module"]
# [doc (alias = "TOPSSCLKCTL")]
pub type Topssclkctl = crate :: Reg < topssclkctl :: TopssclkctlSpec > ; # [doc = "TOPSSCLKCTL"]
pub mod topssclkctl { # [doc = "Register `TOPSSCLKCTL` reader"]
pub type R = crate :: R < TopssclkctlSpec > ; # [doc = "Register `TOPSSCLKCTL` writer"]
pub type W = crate :: W < TopssclkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < TopssclkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < TopssclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < TopssclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < TopssclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < TopssclkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < TopssclkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "TOPSSCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`topssclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`topssclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TopssclkctlSpec ; impl crate :: RegisterSpec for TopssclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`topssclkctl::R`](R) reader structure"]
impl crate :: Readable for TopssclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`topssclkctl::W`](W) writer structure"]
impl crate :: Writable for TopssclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TOPSSCLKCTL to value 0"]
impl crate :: Resettable for TopssclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTICLKCTL (rw) register accessor: RTICLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`rticlkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticlkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rticlkctl`]
module"]
# [doc (alias = "RTICLKCTL")]
pub type Rticlkctl = crate :: Reg < rticlkctl :: RticlkctlSpec > ; # [doc = "RTICLKCTL"]
pub mod rticlkctl { # [doc = "Register `RTICLKCTL` reader"]
pub type R = crate :: R < RticlkctlSpec > ; # [doc = "Register `RTICLKCTL` writer"]
pub type W = crate :: W < RticlkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
0x0 : XTALCLK#br#0x1 : REFCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
0x0 : XTALCLK#br#0x1 : REFCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : REFCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : REFCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < RticlkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < RticlkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < RticlkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < RticlkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < RticlkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < RticlkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "RTICLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`rticlkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rticlkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RticlkctlSpec ; impl crate :: RegisterSpec for RticlkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`rticlkctl::R`](R) reader structure"]
impl crate :: Readable for RticlkctlSpec { } # [doc = "`write(|w| ..)` method takes [`rticlkctl::W`](W) writer structure"]
impl crate :: Writable for RticlkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTICLKCTL to value 0"]
impl crate :: Resettable for RticlkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "WDTCLKCTL (rw) register accessor: WDTCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtclkctl`]
module"]
# [doc (alias = "WDTCLKCTL")]
pub type Wdtclkctl = crate :: Reg < wdtclkctl :: WdtclkctlSpec > ; # [doc = "WDTCLKCTL"]
pub mod wdtclkctl { # [doc = "Register `WDTCLKCTL` reader"]
pub type R = crate :: R < WdtclkctlSpec > ; # [doc = "Register `WDTCLKCTL` writer"]
pub type W = crate :: W < WdtclkctlSpec > ; # [doc = "Field `srcsel` reader - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselR = crate :: FieldReader ; # [doc = "Field `srcsel` writer - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
pub type SrcselW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `currclk` reader - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
pub fn srcsel (& self) -> SrcselR { SrcselR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected."]
# [inline (always)]
# [must_use]
pub fn srcsel (& mut self) -> SrcselW < WdtclkctlSpec > { SrcselW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < WdtclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < WdtclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < WdtclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < WdtclkctlSpec > { CurrdivrW :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < WdtclkctlSpec > { CurrclkW :: new (self , 24) } } # [doc = "WDTCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtclkctlSpec ; impl crate :: RegisterSpec for WdtclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`wdtclkctl::R`](R) reader structure"]
impl crate :: Readable for WdtclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`wdtclkctl::W`](W) writer structure"]
impl crate :: Writable for WdtclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WDTCLKCTL to value 0"]
impl crate :: Resettable for WdtclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "UART1CLKCTL (rw) register accessor: UART1CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1clkctl`]
module"]
# [doc (alias = "UART1CLKCTL")]
pub type Uart1clkctl = crate :: Reg < uart1clkctl :: Uart1clkctlSpec > ; # [doc = "UART1CLKCTL"]
pub mod uart1clkctl { # [doc = "Register `UART1CLKCTL` reader"]
pub type R = crate :: R < Uart1clkctlSpec > ; # [doc = "Register `UART1CLKCTL` writer"]
pub type W = crate :: W < Uart1clkctlSpec > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < Uart1clkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < Uart1clkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < Uart1clkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < Uart1clkctlSpec > { CurrdivrW :: new (self , 16) } } # [doc = "UART1CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart1clkctlSpec ; impl crate :: RegisterSpec for Uart1clkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`uart1clkctl::R`](R) reader structure"]
impl crate :: Readable for Uart1clkctlSpec { } # [doc = "`write(|w| ..)` method takes [`uart1clkctl::W`](W) writer structure"]
impl crate :: Writable for Uart1clkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets UART1CLKCTL to value 0"]
impl crate :: Resettable for Uart1clkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "UART2CLKCTL (rw) register accessor: UART2CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`uart2clkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart2clkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart2clkctl`]
module"]
# [doc (alias = "UART2CLKCTL")]
pub type Uart2clkctl = crate :: Reg < uart2clkctl :: Uart2clkctlSpec > ; # [doc = "UART2CLKCTL"]
pub mod uart2clkctl { # [doc = "Register `UART2CLKCTL` reader"]
pub type R = crate :: R < Uart2clkctlSpec > ; # [doc = "Register `UART2CLKCTL` writer"]
pub type W = crate :: W < Uart2clkctlSpec > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < Uart2clkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < Uart2clkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < Uart2clkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < Uart2clkctlSpec > { CurrdivrW :: new (self , 16) } } # [doc = "UART2CLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`uart2clkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart2clkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart2clkctlSpec ; impl crate :: RegisterSpec for Uart2clkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`uart2clkctl::R`](R) reader structure"]
impl crate :: Readable for Uart2clkctlSpec { } # [doc = "`write(|w| ..)` method takes [`uart2clkctl::W`](W) writer structure"]
impl crate :: Writable for Uart2clkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets UART2CLKCTL to value 0"]
impl crate :: Resettable for Uart2clkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "I2CCLKCTL (rw) register accessor: I2CCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cclkctl`]
module"]
# [doc (alias = "I2CCLKCTL")]
pub type I2cclkctl = crate :: Reg < i2cclkctl :: I2cclkctlSpec > ; # [doc = "I2CCLKCTL"]
pub mod i2cclkctl { # [doc = "Register `I2CCLKCTL` reader"]
pub type R = crate :: R < I2cclkctlSpec > ; # [doc = "Register `I2CCLKCTL` writer"]
pub type W = crate :: W < I2cclkctlSpec > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < I2cclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < I2cclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < I2cclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < I2cclkctlSpec > { CurrdivrW :: new (self , 16) } } # [doc = "I2CCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2cclkctlSpec ; impl crate :: RegisterSpec for I2cclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`i2cclkctl::R`](R) reader structure"]
impl crate :: Readable for I2cclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`i2cclkctl::W`](W) writer structure"]
impl crate :: Writable for I2cclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets I2CCLKCTL to value 0"]
impl crate :: Resettable for I2cclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LINCLKCTL (rw) register accessor: LINCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`linclkctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linclkctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linclkctl`]
module"]
# [doc (alias = "LINCLKCTL")]
pub type Linclkctl = crate :: Reg < linclkctl :: LinclkctlSpec > ; # [doc = "LINCLKCTL"]
pub mod linclkctl { # [doc = "Register `LINCLKCTL` reader"]
pub type R = crate :: R < LinclkctlSpec > ; # [doc = "Register `LINCLKCTL` writer"]
pub type W = crate :: W < LinclkctlSpec > ; # [doc = "Field `gate` reader - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateR = crate :: FieldReader ; # [doc = "Field `gate` writer - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type GateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrR = crate :: FieldReader ; # [doc = "Field `divr` writer - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `switchen` reader - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenR = crate :: BitReader ; # [doc = "Field `switchen` writer - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
pub type SwitchenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `currdivr` reader - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 19:16\\]
Gives the current divr setting used by the clock divider."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn gate (& self) -> GateR { GateR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
pub fn switchen (& self) -> SwitchenR { SwitchenR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bits 4:7 - 7:4\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn gate (& mut self) -> GateW < LinclkctlSpec > { GateW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16"]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < LinclkctlSpec > { DivrW :: new (self , 8) } # [doc = "Bit 12 - 12:12\\]
1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1,"]
# [inline (always)]
# [must_use]
pub fn switchen (& mut self) -> SwitchenW < LinclkctlSpec > { SwitchenW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
Gives the current divr setting used by the clock divider."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < LinclkctlSpec > { CurrdivrW :: new (self , 16) } } # [doc = "LINCLKCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`linclkctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linclkctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LinclkctlSpec ; impl crate :: RegisterSpec for LinclkctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`linclkctl::R`](R) reader structure"]
impl crate :: Readable for LinclkctlSpec { } # [doc = "`write(|w| ..)` method takes [`linclkctl::W`](W) writer structure"]
impl crate :: Writable for LinclkctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LINCLKCTL to value 0"]
impl crate :: Resettable for LinclkctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED0 (rw) register accessor: RESERVED0\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved0`]
module"]
# [doc (alias = "RESERVED0")]
pub type Reserved0 = crate :: Reg < reserved0 :: Reserved0Spec > ; # [doc = "RESERVED0"]
pub mod reserved0 { # [doc = "Register `RESERVED0` reader"]
pub type R = crate :: R < Reserved0Spec > ; # [doc = "Register `RESERVED0` writer"]
pub type W = crate :: W < Reserved0Spec > ; # [doc = "Field `rwres` reader - "]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - "]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - "]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - "]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - "]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - "]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved0Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved0Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved0Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED0\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved0Spec ; impl crate :: RegisterSpec for Reserved0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved0::R`](R) reader structure"]
impl crate :: Readable for Reserved0Spec { } # [doc = "`write(|w| ..)` method takes [`reserved0::W`](W) writer structure"]
impl crate :: Writable for Reserved0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED0 to value 0"]
impl crate :: Resettable for Reserved0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED1 (rw) register accessor: RESERVED1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved1`]
module"]
# [doc (alias = "RESERVED1")]
pub type Reserved1 = crate :: Reg < reserved1 :: Reserved1Spec > ; # [doc = "RESERVED1"]
pub mod reserved1 { # [doc = "Register `RESERVED1` reader"]
pub type R = crate :: R < Reserved1Spec > ; # [doc = "Register `RESERVED1` writer"]
pub type W = crate :: W < Reserved1Spec > ; # [doc = "Field `rwres` reader - "]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - "]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - "]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - "]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - "]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - "]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved1Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved1Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved1Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED1\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved1Spec ; impl crate :: RegisterSpec for Reserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved1::R`](R) reader structure"]
impl crate :: Readable for Reserved1Spec { } # [doc = "`write(|w| ..)` method takes [`reserved1::W`](W) writer structure"]
impl crate :: Writable for Reserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED1 to value 0"]
impl crate :: Resettable for Reserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED2 (rw) register accessor: RESERVED2\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved2`]
module"]
# [doc (alias = "RESERVED2")]
pub type Reserved2 = crate :: Reg < reserved2 :: Reserved2Spec > ; # [doc = "RESERVED2"]
pub mod reserved2 { # [doc = "Register `RESERVED2` reader"]
pub type R = crate :: R < Reserved2Spec > ; # [doc = "Register `RESERVED2` writer"]
pub type W = crate :: W < Reserved2Spec > ; # [doc = "Field `rwres` reader - "]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - "]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - "]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - "]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - "]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - "]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved2Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved2Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved2Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED2\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved2Spec ; impl crate :: RegisterSpec for Reserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved2::R`](R) reader structure"]
impl crate :: Readable for Reserved2Spec { } # [doc = "`write(|w| ..)` method takes [`reserved2::W`](W) writer structure"]
impl crate :: Writable for Reserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED2 to value 0"]
impl crate :: Resettable for Reserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RESERVED3 (rw) register accessor: RESERVED3\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved3`]
module"]
# [doc (alias = "RESERVED3")]
pub type Reserved3 = crate :: Reg < reserved3 :: Reserved3Spec > ; # [doc = "RESERVED3"]
pub mod reserved3 { # [doc = "Register `RESERVED3` reader"]
pub type R = crate :: R < Reserved3Spec > ; # [doc = "Register `RESERVED3` writer"]
pub type W = crate :: W < Reserved3Spec > ; # [doc = "Field `rwres` reader - "]
pub type RwresR = crate :: FieldReader ; # [doc = "Field `rwres` writer - "]
pub type RwresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `rores` reader - "]
pub type RoresR = crate :: FieldReader ; # [doc = "Field `rores` writer - "]
pub type RoresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `wphres` reader - "]
pub type WphresR = crate :: FieldReader ; # [doc = "Field `wphres` writer - "]
pub type WphresW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7"]
# [inline (always)]
pub fn rwres (& self) -> RwresR { RwresR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15"]
# [inline (always)]
pub fn rores (& self) -> RoresR { RoresR :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 24:31"]
# [inline (always)]
pub fn wphres (& self) -> WphresR { WphresR :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7"]
# [inline (always)]
# [must_use]
pub fn rwres (& mut self) -> RwresW < Reserved3Spec > { RwresW :: new (self , 0) } # [doc = "Bits 8:15"]
# [inline (always)]
# [must_use]
pub fn rores (& mut self) -> RoresW < Reserved3Spec > { RoresW :: new (self , 8) } # [doc = "Bits 24:31"]
# [inline (always)]
# [must_use]
pub fn wphres (& mut self) -> WphresW < Reserved3Spec > { WphresW :: new (self , 24) } } # [doc = "RESERVED3\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserved3Spec ; impl crate :: RegisterSpec for Reserved3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved3::R`](R) reader structure"]
impl crate :: Readable for Reserved3Spec { } # [doc = "`write(|w| ..)` method takes [`reserved3::W`](W) writer structure"]
impl crate :: Writable for Reserved3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED3 to value 0"]
impl crate :: Resettable for Reserved3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "VBUSCLKGATE0 (rw) register accessor: VBUSCLKGATE0\n\nYou can [`read`](crate::Reg::read) this register and get [`vbusclkgate0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vbusclkgate0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vbusclkgate0`]
module"]
# [doc (alias = "VBUSCLKGATE0")]
pub type Vbusclkgate0 = crate :: Reg < vbusclkgate0 :: Vbusclkgate0Spec > ; # [doc = "VBUSCLKGATE0"]
pub mod vbusclkgate0 { # [doc = "Register `VBUSCLKGATE0` reader"]
pub type R = crate :: R < Vbusclkgate0Spec > ; # [doc = "Register `VBUSCLKGATE0` writer"]
pub type W = crate :: W < Vbusclkgate0Spec > ; # [doc = "Field `xbara` reader - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type XbaraR = crate :: FieldReader ; # [doc = "Field `xbara` writer - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type XbaraW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `qspi` reader - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type QspiR = crate :: FieldReader ; # [doc = "Field `qspi` writer - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type QspiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc1` reader - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Tptc1R = crate :: FieldReader ; # [doc = "Field `tptc1` writer - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Tptc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc2` reader - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Tptc2R = crate :: FieldReader ; # [doc = "Field `tptc2` writer - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Tptc2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tpcc` reader - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type TpccR = crate :: FieldReader ; # [doc = "Field `tpcc` writer - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type TpccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `esm` reader - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type EsmR = crate :: FieldReader ; # [doc = "Field `esm` writer - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type EsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `rti` reader - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type RtiR = crate :: FieldReader ; # [doc = "Field `rti` writer - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type RtiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `wdt` reader - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type WdtR = crate :: FieldReader ; # [doc = "Field `wdt` writer - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type WdtW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `dcc` reader - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type DccR = crate :: FieldReader ; # [doc = "Field `dcc` writer - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type DccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `i2c` reader - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type I2cR = crate :: FieldReader ; # [doc = "Field `i2c` writer - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type I2cW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn xbara (& self) -> XbaraR { XbaraR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn qspi (& self) -> QspiR { QspiR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn tptc1 (& self) -> Tptc1R { Tptc1R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn tptc2 (& self) -> Tptc2R { Tptc2R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn tpcc (& self) -> TpccR { TpccR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn esm (& self) -> EsmR { EsmR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn rti (& self) -> RtiR { RtiR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn wdt (& self) -> WdtR { WdtR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn dcc (& self) -> DccR { DccR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn i2c (& self) -> I2cR { I2cR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn xbara (& mut self) -> XbaraW < Vbusclkgate0Spec > { XbaraW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn qspi (& mut self) -> QspiW < Vbusclkgate0Spec > { QspiW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn tptc1 (& mut self) -> Tptc1W < Vbusclkgate0Spec > { Tptc1W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn tptc2 (& mut self) -> Tptc2W < Vbusclkgate0Spec > { Tptc2W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn tpcc (& mut self) -> TpccW < Vbusclkgate0Spec > { TpccW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn esm (& mut self) -> EsmW < Vbusclkgate0Spec > { EsmW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn rti (& mut self) -> RtiW < Vbusclkgate0Spec > { RtiW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn wdt (& mut self) -> WdtW < Vbusclkgate0Spec > { WdtW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn dcc (& mut self) -> DccW < Vbusclkgate0Spec > { DccW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn i2c (& mut self) -> I2cW < Vbusclkgate0Spec > { I2cW :: new (self , 27) } } # [doc = "VBUSCLKGATE0\n\nYou can [`read`](crate::Reg::read) this register and get [`vbusclkgate0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vbusclkgate0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Vbusclkgate0Spec ; impl crate :: RegisterSpec for Vbusclkgate0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`vbusclkgate0::R`](R) reader structure"]
impl crate :: Readable for Vbusclkgate0Spec { } # [doc = "`write(|w| ..)` method takes [`vbusclkgate0::W`](W) writer structure"]
impl crate :: Writable for Vbusclkgate0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets VBUSCLKGATE0 to value 0"]
impl crate :: Resettable for Vbusclkgate0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "VBUSCLKGATE1 (rw) register accessor: VBUSCLKGATE1\n\nYou can [`read`](crate::Reg::read) this register and get [`vbusclkgate1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vbusclkgate1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vbusclkgate1`]
module"]
# [doc (alias = "VBUSCLKGATE1")]
pub type Vbusclkgate1 = crate :: Reg < vbusclkgate1 :: Vbusclkgate1Spec > ; # [doc = "VBUSCLKGATE1"]
pub mod vbusclkgate1 { # [doc = "Register `VBUSCLKGATE1` reader"]
pub type R = crate :: R < Vbusclkgate1Spec > ; # [doc = "Register `VBUSCLKGATE1` writer"]
pub type W = crate :: W < Vbusclkgate1Spec > ; # [doc = "Field `uart1` reader - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Uart1R = crate :: FieldReader ; # [doc = "Field `uart1` writer - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Uart1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `uart2` reader - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Uart2R = crate :: FieldReader ; # [doc = "Field `uart2` writer - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Uart2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `spi1` reader - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Spi1R = crate :: FieldReader ; # [doc = "Field `spi1` writer - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Spi1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `spi2` reader - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Spi2R = crate :: FieldReader ; # [doc = "Field `spi2` writer - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Spi2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `can` reader - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type CanR = crate :: FieldReader ; # [doc = "Field `can` writer - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type CanW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `lin` reader - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type LinR = crate :: FieldReader ; # [doc = "Field `lin` writer - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type LinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pwm` reader - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type PwmR = crate :: FieldReader ; # [doc = "Field `pwm` writer - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type PwmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `crc` reader - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type CrcR = crate :: FieldReader ; # [doc = "Field `crc` writer - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type CrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ctrl_reg` reader - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type CtrlRegR = crate :: FieldReader ; # [doc = "Field `ctrl_reg` writer - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type CtrlRegW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res` reader - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type ResR = crate :: FieldReader ; # [doc = "Field `res` writer - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type ResW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn uart1 (& self) -> Uart1R { Uart1R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn uart2 (& self) -> Uart2R { Uart2R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn spi1 (& self) -> Spi1R { Spi1R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn spi2 (& self) -> Spi2R { Spi2R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn can (& self) -> CanR { CanR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn lin (& self) -> LinR { LinR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn pwm (& self) -> PwmR { PwmR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn crc (& self) -> CrcR { CrcR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn ctrl_reg (& self) -> CtrlRegR { CtrlRegR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res (& self) -> ResR { ResR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn uart1 (& mut self) -> Uart1W < Vbusclkgate1Spec > { Uart1W :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn uart2 (& mut self) -> Uart2W < Vbusclkgate1Spec > { Uart2W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn spi1 (& mut self) -> Spi1W < Vbusclkgate1Spec > { Spi1W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn spi2 (& mut self) -> Spi2W < Vbusclkgate1Spec > { Spi2W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn can (& mut self) -> CanW < Vbusclkgate1Spec > { CanW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn lin (& mut self) -> LinW < Vbusclkgate1Spec > { LinW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pwm (& mut self) -> PwmW < Vbusclkgate1Spec > { PwmW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn crc (& mut self) -> CrcW < Vbusclkgate1Spec > { CrcW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn ctrl_reg (& mut self) -> CtrlRegW < Vbusclkgate1Spec > { CtrlRegW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res (& mut self) -> ResW < Vbusclkgate1Spec > { ResW :: new (self , 27) } } # [doc = "VBUSCLKGATE1\n\nYou can [`read`](crate::Reg::read) this register and get [`vbusclkgate1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vbusclkgate1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Vbusclkgate1Spec ; impl crate :: RegisterSpec for Vbusclkgate1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`vbusclkgate1::R`](R) reader structure"]
impl crate :: Readable for Vbusclkgate1Spec { } # [doc = "`write(|w| ..)` method takes [`vbusclkgate1::W`](W) writer structure"]
impl crate :: Writable for Vbusclkgate1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets VBUSCLKGATE1 to value 0"]
impl crate :: Resettable for Vbusclkgate1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "VBUSCLKGATE2 (rw) register accessor: VBUSCLKGATE2\n\nYou can [`read`](crate::Reg::read) this register and get [`vbusclkgate2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vbusclkgate2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vbusclkgate2`]
module"]
# [doc (alias = "VBUSCLKGATE2")]
pub type Vbusclkgate2 = crate :: Reg < vbusclkgate2 :: Vbusclkgate2Spec > ; # [doc = "VBUSCLKGATE2"]
pub mod vbusclkgate2 { # [doc = "Register `VBUSCLKGATE2` reader"]
pub type R = crate :: R < Vbusclkgate2Spec > ; # [doc = "Register `VBUSCLKGATE2` writer"]
pub type W = crate :: W < Vbusclkgate2Spec > ; # [doc = "Field `pcr3` reader - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr3R = crate :: FieldReader ; # [doc = "Field `pcr3` writer - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pcr4` reader - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr4R = crate :: FieldReader ; # [doc = "Field `pcr4` writer - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pcr5` reader - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr5R = crate :: FieldReader ; # [doc = "Field `pcr5` writer - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pcr6` reader - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr6R = crate :: FieldReader ; # [doc = "Field `pcr6` writer - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Pcr6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res0` reader - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res0R = crate :: FieldReader ; # [doc = "Field `res0` writer - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res1` reader - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res1R = crate :: FieldReader ; # [doc = "Field `res1` writer - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res2` reader - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res2R = crate :: FieldReader ; # [doc = "Field `res2` writer - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res3` reader - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res3R = crate :: FieldReader ; # [doc = "Field `res3` writer - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res4` reader - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res4R = crate :: FieldReader ; # [doc = "Field `res4` writer - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res5` reader - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res5R = crate :: FieldReader ; # [doc = "Field `res5` writer - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
pub type Res5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn pcr3 (& self) -> Pcr3R { Pcr3R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn pcr4 (& self) -> Pcr4R { Pcr4R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn pcr5 (& self) -> Pcr5R { Pcr5R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn pcr6 (& self) -> Pcr6R { Pcr6R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res0 (& self) -> Res0R { Res0R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res1 (& self) -> Res1R { Res1R :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res2 (& self) -> Res2R { Res2R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res3 (& self) -> Res3R { Res3R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res4 (& self) -> Res4R { Res4R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
pub fn res5 (& self) -> Res5R { Res5R :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pcr3 (& mut self) -> Pcr3W < Vbusclkgate2Spec > { Pcr3W :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pcr4 (& mut self) -> Pcr4W < Vbusclkgate2Spec > { Pcr4W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pcr5 (& mut self) -> Pcr5W < Vbusclkgate2Spec > { Pcr5W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn pcr6 (& mut self) -> Pcr6W < Vbusclkgate2Spec > { Pcr6W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res0 (& mut self) -> Res0W < Vbusclkgate2Spec > { Res0W :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res1 (& mut self) -> Res1W < Vbusclkgate2Spec > { Res1W :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res2 (& mut self) -> Res2W < Vbusclkgate2Spec > { Res2W :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res3 (& mut self) -> Res3W < Vbusclkgate2Spec > { Res3W :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res4 (& mut self) -> Res4W < Vbusclkgate2Spec > { Res4W :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Enable the Clock#br#0x7 : Gate the clock"]
# [inline (always)]
# [must_use]
pub fn res5 (& mut self) -> Res5W < Vbusclkgate2Spec > { Res5W :: new (self , 27) } } # [doc = "VBUSCLKGATE2\n\nYou can [`read`](crate::Reg::read) this register and get [`vbusclkgate2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vbusclkgate2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Vbusclkgate2Spec ; impl crate :: RegisterSpec for Vbusclkgate2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`vbusclkgate2::R`](R) reader structure"]
impl crate :: Readable for Vbusclkgate2Spec { } # [doc = "`write(|w| ..)` method takes [`vbusclkgate2::W`](W) writer structure"]
impl crate :: Writable for Vbusclkgate2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets VBUSCLKGATE2 to value 0"]
impl crate :: Resettable for Vbusclkgate2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BLOCKRESET0 (rw) register accessor: BLOCKRESET0\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blockreset0`]
module"]
# [doc (alias = "BLOCKRESET0")]
pub type Blockreset0 = crate :: Reg < blockreset0 :: Blockreset0Spec > ; # [doc = "BLOCKRESET0"]
pub mod blockreset0 { # [doc = "Register `BLOCKRESET0` reader"]
pub type R = crate :: R < Blockreset0Spec > ; # [doc = "Register `BLOCKRESET0` writer"]
pub type W = crate :: W < Blockreset0Spec > ; # [doc = "Field `res` reader - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type ResR = crate :: FieldReader ; # [doc = "Field `res` writer - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type ResW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `qspi` reader - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type QspiR = crate :: FieldReader ; # [doc = "Field `qspi` writer - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type QspiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc1` reader - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Tptc1R = crate :: FieldReader ; # [doc = "Field `tptc1` writer - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Tptc1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tptc2` reader - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Tptc2R = crate :: FieldReader ; # [doc = "Field `tptc2` writer - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Tptc2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `tpcc` reader - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type TpccR = crate :: FieldReader ; # [doc = "Field `tpcc` writer - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type TpccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `esm` reader - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type EsmR = crate :: FieldReader ; # [doc = "Field `esm` writer - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type EsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `rti` reader - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type RtiR = crate :: FieldReader ; # [doc = "Field `rti` writer - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type RtiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `wdt` reader - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type WdtR = crate :: FieldReader ; # [doc = "Field `wdt` writer - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type WdtW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `dcc` reader - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type DccR = crate :: FieldReader ; # [doc = "Field `dcc` writer - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type DccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `i2c` reader - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type I2cR = crate :: FieldReader ; # [doc = "Field `i2c` writer - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type I2cW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn res (& self) -> ResR { ResR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn qspi (& self) -> QspiR { QspiR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn tptc1 (& self) -> Tptc1R { Tptc1R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn tptc2 (& self) -> Tptc2R { Tptc2R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn tpcc (& self) -> TpccR { TpccR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn esm (& self) -> EsmR { EsmR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn rti (& self) -> RtiR { RtiR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn wdt (& self) -> WdtR { WdtR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn dcc (& self) -> DccR { DccR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn i2c (& self) -> I2cR { I2cR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn res (& mut self) -> ResW < Blockreset0Spec > { ResW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn qspi (& mut self) -> QspiW < Blockreset0Spec > { QspiW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn tptc1 (& mut self) -> Tptc1W < Blockreset0Spec > { Tptc1W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn tptc2 (& mut self) -> Tptc2W < Blockreset0Spec > { Tptc2W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn tpcc (& mut self) -> TpccW < Blockreset0Spec > { TpccW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn esm (& mut self) -> EsmW < Blockreset0Spec > { EsmW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn rti (& mut self) -> RtiW < Blockreset0Spec > { RtiW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn wdt (& mut self) -> WdtW < Blockreset0Spec > { WdtW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn dcc (& mut self) -> DccW < Blockreset0Spec > { DccW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn i2c (& mut self) -> I2cW < Blockreset0Spec > { I2cW :: new (self , 27) } } # [doc = "BLOCKRESET0\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Blockreset0Spec ; impl crate :: RegisterSpec for Blockreset0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`blockreset0::R`](R) reader structure"]
impl crate :: Readable for Blockreset0Spec { } # [doc = "`write(|w| ..)` method takes [`blockreset0::W`](W) writer structure"]
impl crate :: Writable for Blockreset0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BLOCKRESET0 to value 0"]
impl crate :: Resettable for Blockreset0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "BLOCKRESET1 (rw) register accessor: BLOCKRESET1\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blockreset1`]
module"]
# [doc (alias = "BLOCKRESET1")]
pub type Blockreset1 = crate :: Reg < blockreset1 :: Blockreset1Spec > ; # [doc = "BLOCKRESET1"]
pub mod blockreset1 { # [doc = "Register `BLOCKRESET1` reader"]
pub type R = crate :: R < Blockreset1Spec > ; # [doc = "Register `BLOCKRESET1` writer"]
pub type W = crate :: W < Blockreset1Spec > ; # [doc = "Field `uart1` reader - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Uart1R = crate :: FieldReader ; # [doc = "Field `uart1` writer - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Uart1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `uart2` reader - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Uart2R = crate :: FieldReader ; # [doc = "Field `uart2` writer - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Uart2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `spi1` reader - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Spi1R = crate :: FieldReader ; # [doc = "Field `spi1` writer - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Spi1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `spi2` reader - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Spi2R = crate :: FieldReader ; # [doc = "Field `spi2` writer - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type Spi2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `can` reader - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type CanR = crate :: FieldReader ; # [doc = "Field `can` writer - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type CanW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `lin` reader - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type LinR = crate :: FieldReader ; # [doc = "Field `lin` writer - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type LinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `pwm` reader - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type PwmR = crate :: FieldReader ; # [doc = "Field `pwm` writer - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type PwmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `crc` reader - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type CrcR = crate :: FieldReader ; # [doc = "Field `crc` writer - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type CrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ctrl_reg` reader - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type CtrlRegR = crate :: FieldReader ; # [doc = "Field `ctrl_reg` writer - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type CtrlRegW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `res` reader - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type ResR = crate :: FieldReader ; # [doc = "Field `res` writer - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
pub type ResW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn uart1 (& self) -> Uart1R { Uart1R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn uart2 (& self) -> Uart2R { Uart2R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn spi1 (& self) -> Spi1R { Spi1R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn spi2 (& self) -> Spi2R { Spi2R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn can (& self) -> CanR { CanR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn lin (& self) -> LinR { LinR :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn pwm (& self) -> PwmR { PwmR :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn crc (& self) -> CrcR { CrcR :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn ctrl_reg (& self) -> CtrlRegR { CtrlRegR :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
pub fn res (& self) -> ResR { ResR :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn uart1 (& mut self) -> Uart1W < Blockreset1Spec > { Uart1W :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn uart2 (& mut self) -> Uart2W < Blockreset1Spec > { Uart2W :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn spi1 (& mut self) -> Spi1W < Blockreset1Spec > { Spi1W :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn spi2 (& mut self) -> Spi2W < Blockreset1Spec > { Spi2W :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn can (& mut self) -> CanW < Blockreset1Spec > { CanW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn lin (& mut self) -> LinW < Blockreset1Spec > { LinW :: new (self , 15) } # [doc = "Bits 18:20 - 20:18\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn pwm (& mut self) -> PwmW < Blockreset1Spec > { PwmW :: new (self , 18) } # [doc = "Bits 21:23 - 23:21\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn crc (& mut self) -> CrcW < Blockreset1Spec > { CrcW :: new (self , 21) } # [doc = "Bits 24:26 - 26:24\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn ctrl_reg (& mut self) -> CtrlRegW < Blockreset1Spec > { CtrlRegW :: new (self , 24) } # [doc = "Bits 27:29 - 29:27\\]
0x0 : Release the reset#br#0x7 : Assert the reset"]
# [inline (always)]
# [must_use]
pub fn res (& mut self) -> ResW < Blockreset1Spec > { ResW :: new (self , 27) } } # [doc = "BLOCKRESET1\n\nYou can [`read`](crate::Reg::read) this register and get [`blockreset1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blockreset1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Blockreset1Spec ; impl crate :: RegisterSpec for Blockreset1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`blockreset1::R`](R) reader structure"]
impl crate :: Readable for Blockreset1Spec { } # [doc = "`write(|w| ..)` method takes [`blockreset1::W`](W) writer structure"]
impl crate :: Writable for Blockreset1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BLOCKRESET1 to value 0"]
impl crate :: Resettable for Blockreset1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK0 (rw) register accessor: - KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick0`]
module"]
# [doc (alias = "LOCK0_KICK0")]
pub type Lock0Kick0 = crate :: Reg < lock0_kick0 :: Lock0Kick0Spec > ; # [doc = "- KICK0 component"]
pub mod lock0_kick0 { # [doc = "Register `LOCK0_KICK0` reader"]
pub type R = crate :: R < Lock0Kick0Spec > ; # [doc = "Register `LOCK0_KICK0` writer"]
pub type W = crate :: W < Lock0Kick0Spec > ; # [doc = "Field `KICK0_COMPONENT` reader - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK0_COMPONENT` writer - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
pub fn kick0_component (& self) -> Kick0ComponentR { Kick0ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
# [must_use]
pub fn kick0_component (& mut self) -> Kick0ComponentW < Lock0Kick0Spec > { Kick0ComponentW :: new (self , 0) } } # [doc = "- KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick0Spec ; impl crate :: RegisterSpec for Lock0Kick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick0::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick0Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick0::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK0 to value 0"]
impl crate :: Resettable for Lock0Kick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK1 (rw) register accessor: - KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick1`]
module"]
# [doc (alias = "LOCK0_KICK1")]
pub type Lock0Kick1 = crate :: Reg < lock0_kick1 :: Lock0Kick1Spec > ; # [doc = "- KICK1 component"]
pub mod lock0_kick1 { # [doc = "Register `LOCK0_KICK1` reader"]
pub type R = crate :: R < Lock0Kick1Spec > ; # [doc = "Register `LOCK0_KICK1` writer"]
pub type W = crate :: W < Lock0Kick1Spec > ; # [doc = "Field `KICK1_COMPONENT` reader - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK1_COMPONENT` writer - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
pub fn kick1_component (& self) -> Kick1ComponentR { Kick1ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
# [must_use]
pub fn kick1_component (& mut self) -> Kick1ComponentW < Lock0Kick1Spec > { Kick1ComponentW :: new (self , 0) } } # [doc = "- KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick1Spec ; impl crate :: RegisterSpec for Lock0Kick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick1::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick1Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick1::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK1 to value 0"]
impl crate :: Resettable for Lock0Kick1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_raw_status (rw) register accessor: Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw_status`]
module"]
# [doc (alias = "intr_raw_status")]
pub type IntrRawStatus = crate :: Reg < intr_raw_status :: IntrRawStatusSpec > ; # [doc = "Interrupt Raw Status/Set Register"]
pub mod intr_raw_status { # [doc = "Register `intr_raw_status` reader"]
pub type R = crate :: R < IntrRawStatusSpec > ; # [doc = "Register `intr_raw_status` writer"]
pub type W = crate :: W < IntrRawStatusSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrRawStatusSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrRawStatusSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrRawStatusSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrRawStatusSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrRawStatusSpec ; impl crate :: RegisterSpec for IntrRawStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_raw_status::R`](R) reader structure"]
impl crate :: Readable for IntrRawStatusSpec { } # [doc = "`write(|w| ..)` method takes [`intr_raw_status::W`](W) writer structure"]
impl crate :: Writable for IntrRawStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_raw_status to value 0"]
impl crate :: Resettable for IntrRawStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enabled_status_clear (rw) register accessor: Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enabled_status_clear`]
module"]
# [doc (alias = "intr_enabled_status_clear")]
pub type IntrEnabledStatusClear = crate :: Reg < intr_enabled_status_clear :: IntrEnabledStatusClearSpec > ; # [doc = "Interrupt Enabled Status/Clear register"]
pub mod intr_enabled_status_clear { # [doc = "Register `intr_enabled_status_clear` reader"]
pub type R = crate :: R < IntrEnabledStatusClearSpec > ; # [doc = "Register `intr_enabled_status_clear` writer"]
pub type W = crate :: W < IntrEnabledStatusClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrEnabledStatusClearSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrEnabledStatusClearSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnabledStatusClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnabledStatusClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnabledStatusClearSpec ; impl crate :: RegisterSpec for IntrEnabledStatusClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enabled_status_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnabledStatusClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enabled_status_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnabledStatusClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enabled_status_clear to value 0"]
impl crate :: Resettable for IntrEnabledStatusClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable`]
module"]
# [doc (alias = "intr_enable")]
pub type IntrEnable = crate :: Reg < intr_enable :: IntrEnableSpec > ; # [doc = "Interrupt Enable register"]
pub mod intr_enable { # [doc = "Register `intr_enable` reader"]
pub type R = crate :: R < IntrEnableSpec > ; # [doc = "Register `intr_enable` writer"]
pub type W = crate :: W < IntrEnableSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSpec ; impl crate :: RegisterSpec for IntrEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable to value 0"]
impl crate :: Resettable for IntrEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable_clear (rw) register accessor: Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "intr_enable_clear")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "Interrupt Enable Clear register"]
pub mod intr_enable_clear { # [doc = "Register `intr_enable_clear` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `intr_enable_clear` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableClearSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableClearSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable_clear to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "eoi (rw) register accessor: EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi`]
module"]
# [doc (alias = "eoi")]
pub type Eoi = crate :: Reg < eoi :: EoiSpec > ; # [doc = "EOI register"]
pub mod eoi { # [doc = "Register `eoi` reader"]
pub type R = crate :: R < EoiSpec > ; # [doc = "Register `eoi` writer"]
pub type W = crate :: W < EoiSpec > ; # [doc = "Field `EOI_VECTOR_VALUE_` reader - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_R = crate :: FieldReader ; # [doc = "Field `EOI_VECTOR_VALUE_` writer - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
pub fn eoi_vector_value_ (& self) -> EoiVectorValue_R { EoiVectorValue_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
# [must_use]
pub fn eoi_vector_value_ (& mut self) -> EoiVectorValue_W < EoiSpec > { EoiVectorValue_W :: new (self , 0) } } # [doc = "EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EoiSpec ; impl crate :: RegisterSpec for EoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eoi::R`](R) reader structure"]
impl crate :: Readable for EoiSpec { } # [doc = "`write(|w| ..)` method takes [`eoi::W`](W) writer structure"]
impl crate :: Writable for EoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets eoi to value 0"]
impl crate :: Resettable for EoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_address (rw) register accessor: Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_address`]
module"]
# [doc (alias = "fault_address")]
pub type FaultAddress = crate :: Reg < fault_address :: FaultAddressSpec > ; # [doc = "Fault Address register"]
pub mod fault_address { # [doc = "Register `fault_address` reader"]
pub type R = crate :: R < FaultAddressSpec > ; # [doc = "Register `fault_address` writer"]
pub type W = crate :: W < FaultAddressSpec > ; # [doc = "Field `FAULT_ADDRESS_` reader - 31:0\\]
Fault Address."]
pub type FaultAddress_R = crate :: FieldReader < u32 > ; # [doc = "Field `FAULT_ADDRESS_` writer - 31:0\\]
Fault Address."]
pub type FaultAddress_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
pub fn fault_address_ (& self) -> FaultAddress_R { FaultAddress_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
# [must_use]
pub fn fault_address_ (& mut self) -> FaultAddress_W < FaultAddressSpec > { FaultAddress_W :: new (self , 0) } } # [doc = "Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAddressSpec ; impl crate :: RegisterSpec for FaultAddressSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_address::R`](R) reader structure"]
impl crate :: Readable for FaultAddressSpec { } # [doc = "`write(|w| ..)` method takes [`fault_address::W`](W) writer structure"]
impl crate :: Writable for FaultAddressSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_address to value 0"]
impl crate :: Resettable for FaultAddressSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_type_status (rw) register accessor: Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_type_status`]
module"]
# [doc (alias = "fault_type_status")]
pub type FaultTypeStatus = crate :: Reg < fault_type_status :: FaultTypeStatusSpec > ; # [doc = "Fault Type Status register"]
pub mod fault_type_status { # [doc = "Register `fault_type_status` reader"]
pub type R = crate :: R < FaultTypeStatusSpec > ; # [doc = "Register `fault_type_status` writer"]
pub type W = crate :: W < FaultTypeStatusSpec > ; # [doc = "Field `FAULT_TYPE_` reader - 5:0\\]
Fault Type #br# 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 #br# 01_0000 = Supervisor write fault - priv = 1 dir = 0 #br# 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 #br# 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 #br# 00_0010 = User write fault - priv = 0 dir = 0 #br# 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 #br# 00_0000 = No fault"]
pub type FaultType_R = crate :: FieldReader ; # [doc = "Field `FAULT_TYPE_` writer - 5:0\\]
Fault Type #br# 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 #br# 01_0000 = Supervisor write fault - priv = 1 dir = 0 #br# 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 #br# 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 #br# 00_0010 = User write fault - priv = 0 dir = 0 #br# 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 #br# 00_0000 = No fault"]
pub type FaultType_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NONSECURE_ACCESS_` reader - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_R = crate :: BitReader ; # [doc = "Field `NONSECURE_ACCESS_` writer - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Fault Type #br# 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 #br# 01_0000 = Supervisor write fault - priv = 1 dir = 0 #br# 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 #br# 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 #br# 00_0010 = User write fault - priv = 0 dir = 0 #br# 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 #br# 00_0000 = No fault"]
# [inline (always)]
pub fn fault_type_ (& self) -> FaultType_R { FaultType_R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
pub fn nonsecure_access_ (& self) -> NonsecureAccess_R { NonsecureAccess_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Fault Type #br# 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 #br# 01_0000 = Supervisor write fault - priv = 1 dir = 0 #br# 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 #br# 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 #br# 00_0010 = User write fault - priv = 0 dir = 0 #br# 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 #br# 00_0000 = No fault"]
# [inline (always)]
# [must_use]
pub fn fault_type_ (& mut self) -> FaultType_W < FaultTypeStatusSpec > { FaultType_W :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
# [must_use]
pub fn nonsecure_access_ (& mut self) -> NonsecureAccess_W < FaultTypeStatusSpec > { NonsecureAccess_W :: new (self , 6) } } # [doc = "Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultTypeStatusSpec ; impl crate :: RegisterSpec for FaultTypeStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_type_status::R`](R) reader structure"]
impl crate :: Readable for FaultTypeStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_type_status::W`](W) writer structure"]
impl crate :: Writable for FaultTypeStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_type_status to value 0"]
impl crate :: Resettable for FaultTypeStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_attr_status (rw) register accessor: Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_attr_status`]
module"]
# [doc (alias = "fault_attr_status")]
pub type FaultAttrStatus = crate :: Reg < fault_attr_status :: FaultAttrStatusSpec > ; # [doc = "Fault Attribute Status register"]
pub mod fault_attr_status { # [doc = "Register `fault_attr_status` reader"]
pub type R = crate :: R < FaultAttrStatusSpec > ; # [doc = "Register `fault_attr_status` writer"]
pub type W = crate :: W < FaultAttrStatusSpec > ; # [doc = "Field `PRIVILEGE_ID_` reader - 7:0\\]
Privilege ID."]
pub type PrivilegeId_R = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID_` writer - 7:0\\]
Privilege ID."]
pub type PrivilegeId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ROUTE_ID_` reader - 19:8\\]
Route ID."]
pub type RouteId_R = crate :: FieldReader < u16 > ; # [doc = "Field `ROUTE_ID_` writer - 19:8\\]
Route ID."]
pub type RouteId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `XID_` reader - 31:20\\]
XID."]
pub type Xid_R = crate :: FieldReader < u16 > ; # [doc = "Field `XID_` writer - 31:20\\]
XID."]
pub type Xid_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
pub fn privilege_id_ (& self) -> PrivilegeId_R { PrivilegeId_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
pub fn route_id_ (& self) -> RouteId_R { RouteId_R :: new (((self . bits >> 8) & 0x0fff) as u16) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
pub fn xid_ (& self) -> Xid_R { Xid_R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
# [must_use]
pub fn privilege_id_ (& mut self) -> PrivilegeId_W < FaultAttrStatusSpec > { PrivilegeId_W :: new (self , 0) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
# [must_use]
pub fn route_id_ (& mut self) -> RouteId_W < FaultAttrStatusSpec > { RouteId_W :: new (self , 8) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
# [must_use]
pub fn xid_ (& mut self) -> Xid_W < FaultAttrStatusSpec > { Xid_W :: new (self , 20) } } # [doc = "Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAttrStatusSpec ; impl crate :: RegisterSpec for FaultAttrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_attr_status::R`](R) reader structure"]
impl crate :: Readable for FaultAttrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_attr_status::W`](W) writer structure"]
impl crate :: Writable for FaultAttrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_attr_status to value 0"]
impl crate :: Resettable for FaultAttrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_clear (rw) register accessor: Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_clear`]
module"]
# [doc (alias = "fault_clear")]
pub type FaultClear = crate :: Reg < fault_clear :: FaultClearSpec > ; # [doc = "Fault Clear register"]
pub mod fault_clear { # [doc = "Register `fault_clear` reader"]
pub type R = crate :: R < FaultClearSpec > ; # [doc = "Register `fault_clear` writer"]
pub type W = crate :: W < FaultClearSpec > ; # [doc = "Field `FAULT_CLEAR__WRITING` reader - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingR = crate :: BitReader ; # [doc = "Field `FAULT_CLEAR__WRITING` writer - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
pub fn fault_clear__writing (& self) -> FaultClear_WritingR { FaultClear_WritingR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn fault_clear__writing (& mut self) -> FaultClear_WritingW < FaultClearSpec > { FaultClear_WritingW :: new (self , 0) } } # [doc = "Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultClearSpec ; impl crate :: RegisterSpec for FaultClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_clear::R`](R) reader structure"]
impl crate :: Readable for FaultClearSpec { } # [doc = "`write(|w| ..)` method takes [`fault_clear::W`](W) writer structure"]
impl crate :: Writable for FaultClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_clear to value 0"]
impl crate :: Resettable for FaultClearSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "TOP_GIO"]
pub struct TopGio { _marker : PhantomData < * const () > } unsafe impl Send for TopGio { } impl TopGio { # [doc = r"Pointer to the register block"]
pub const PTR : * const top_gio :: RegisterBlock = 0x5af7_fc00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const top_gio :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TopGio { type Target = top_gio :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TopGio { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TopGio") . finish () } } # [doc = "TOP_GIO"]
pub mod top_gio { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { giogcr : Giogcr , giopwdn : Giopwdn , giointdet : Giointdet , giopol : Giopol , gioenaset : Gioenaset , gioenaclr : Gioenaclr , giolvlset : Giolvlset , giolvlclr : Giolvlclr , gioflg : Gioflg , giooffa : Giooffa , giooffb : Giooffb , gioemua : Gioemua , gioemub : Gioemub , giodira : Giodira , giodina : Giodina , giodouta : Giodouta , gioseta : Gioseta , gioclra : Gioclra , giopdra : Giopdra , giopuldisa : Giopuldisa , giopsla : Giopsla , giodirb : Giodirb , giodinb : Giodinb , giodoutb : Giodoutb , giosetb : Giosetb , gioclrb : Gioclrb , giopdrb : Giopdrb , giopuldisb : Giopuldisb , giopslb : Giopslb , giodirc : Giodirc , giodinc : Giodinc , giodoutc : Giodoutc , giosetc : Giosetc , gioclrc : Gioclrc , giopdrc : Giopdrc , giopuldisc : Giopuldisc , giopslc : Giopslc , giodird : Giodird , giodind : Giodind , giodoutd : Giodoutd , giosetd : Giosetd , gioclrd : Gioclrd , giopdrd : Giopdrd , giopuldisd : Giopuldisd , giopsld : Giopsld , giodire : Giodire , giodine : Giodine , giodoute : Giodoute , giosete : Giosete , gioclre : Gioclre , giopdre : Giopdre , giopuldise : Giopuldise , giopsle : Giopsle , giodirf : Giodirf , giodinf : Giodinf , giodoutf : Giodoutf , giosetf : Giosetf , gioclrf : Gioclrf , giopdrf : Giopdrf , giopuldisf : Giopuldisf , giopslf : Giopslf , giodirg : Giodirg , gioding : Gioding , giodoutg : Giodoutg , giosetg : Giosetg , gioclrg : Gioclrg , giopdrg : Giopdrg , giopuldisg : Giopuldisg , giopslg : Giopslg , giodirh : Giodirh , giodinh : Giodinh , giodouth : Giodouth , gioseth : Gioseth , gioclrh : Gioclrh , giopdrh : Giopdrh , giopuldish : Giopuldish , giopslh : Giopslh , giosrca : Giosrca , giosrcb : Giosrcb , giosrcc : Giosrcc , giosrcd : Giosrcd , giosrce : Giosrce , giosrcf : Giosrcf , giosrcg : Giosrcg , giosrch : Giosrch , } impl RegisterBlock { # [doc = "0x00 - GIO reset"]
# [inline (always)]
pub const fn giogcr (& self) -> & Giogcr { & self . giogcr } # [doc = "0x04 - GIO power down mode register"]
# [inline (always)]
pub const fn giopwdn (& self) -> & Giopwdn { & self . giopwdn } # [doc = "0x08 - Interrupt detection select for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn giointdet (& self) -> & Giointdet { & self . giointdet } # [doc = "0x0c - Interrupt polarity select for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn giopol (& self) -> & Giopol { & self . giopol } # [doc = "0x10 - Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn gioenaset (& self) -> & Gioenaset { & self . gioenaset } # [doc = "0x14 - Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn gioenaclr (& self) -> & Gioenaclr { & self . gioenaclr } # [doc = "0x18 - GIO high priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn giolvlset (& self) -> & Giolvlset { & self . giolvlset } # [doc = "0x1c - GIO low priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn giolvlclr (& self) -> & Giolvlclr { & self . giolvlclr } # [doc = "0x20 - GIO flag for pins \\[0:1\\]
GIO\\[7:0\\]."]
# [inline (always)]
pub const fn gioflg (& self) -> & Gioflg { & self . gioflg } # [doc = "0x24 - Index bits for currently pending high-priority interrupt Register A"]
# [inline (always)]
pub const fn giooffa (& self) -> & Giooffa { & self . giooffa } # [doc = "0x28 - Index bits for currently pending high-priority interrupt Register B"]
# [inline (always)]
pub const fn giooffb (& self) -> & Giooffb { & self . giooffb } # [doc = "0x2c - GIO emulation register A"]
# [inline (always)]
pub const fn gioemua (& self) -> & Gioemua { & self . gioemua } # [doc = "0x30 - GIO emulation register B"]
# [inline (always)]
pub const fn gioemub (& self) -> & Gioemub { & self . gioemub } # [doc = "0x34 - GIO data direction of pins in Port A"]
# [inline (always)]
pub const fn giodira (& self) -> & Giodira { & self . giodira } # [doc = "0x38 - GIO data input for pins in port A"]
# [inline (always)]
pub const fn giodina (& self) -> & Giodina { & self . giodina } # [doc = "0x3c - GIO data output for pins in port A"]
# [inline (always)]
pub const fn giodouta (& self) -> & Giodouta { & self . giodouta } # [doc = "0x40 - GIO data set for port A"]
# [inline (always)]
pub const fn gioseta (& self) -> & Gioseta { & self . gioseta } # [doc = "0x44 - GIO data clear for port A"]
# [inline (always)]
pub const fn gioclra (& self) -> & Gioclra { & self . gioclra } # [doc = "0x48 - GIO open drain for port A"]
# [inline (always)]
pub const fn giopdra (& self) -> & Giopdra { & self . giopdra } # [doc = "0x4c - GIO pul disable for port A"]
# [inline (always)]
pub const fn giopuldisa (& self) -> & Giopuldisa { & self . giopuldisa } # [doc = "0x50 - GIO pul select for port A"]
# [inline (always)]
pub const fn giopsla (& self) -> & Giopsla { & self . giopsla } # [doc = "0x54 - GIO data direction of pins in Port B"]
# [inline (always)]
pub const fn giodirb (& self) -> & Giodirb { & self . giodirb } # [doc = "0x58 - GIO data input for pins in port B"]
# [inline (always)]
pub const fn giodinb (& self) -> & Giodinb { & self . giodinb } # [doc = "0x5c - GIO data output for pins in port B"]
# [inline (always)]
pub const fn giodoutb (& self) -> & Giodoutb { & self . giodoutb } # [doc = "0x60 - GIO data set for port B"]
# [inline (always)]
pub const fn giosetb (& self) -> & Giosetb { & self . giosetb } # [doc = "0x64 - GIO data clear for port B"]
# [inline (always)]
pub const fn gioclrb (& self) -> & Gioclrb { & self . gioclrb } # [doc = "0x68 - GIO open drain for port B"]
# [inline (always)]
pub const fn giopdrb (& self) -> & Giopdrb { & self . giopdrb } # [doc = "0x6c - GIO pul disable for port B"]
# [inline (always)]
pub const fn giopuldisb (& self) -> & Giopuldisb { & self . giopuldisb } # [doc = "0x70 - GIO pul select for port B"]
# [inline (always)]
pub const fn giopslb (& self) -> & Giopslb { & self . giopslb } # [doc = "0x74 - GIO data direction of pins in Port C"]
# [inline (always)]
pub const fn giodirc (& self) -> & Giodirc { & self . giodirc } # [doc = "0x78 - GIO data input for pins in port C"]
# [inline (always)]
pub const fn giodinc (& self) -> & Giodinc { & self . giodinc } # [doc = "0x7c - GIO data output for pins in port C"]
# [inline (always)]
pub const fn giodoutc (& self) -> & Giodoutc { & self . giodoutc } # [doc = "0x80 - GIO data set for port C"]
# [inline (always)]
pub const fn giosetc (& self) -> & Giosetc { & self . giosetc } # [doc = "0x84 - GIO data clear for port C"]
# [inline (always)]
pub const fn gioclrc (& self) -> & Gioclrc { & self . gioclrc } # [doc = "0x88 - GIO open drain for port C"]
# [inline (always)]
pub const fn giopdrc (& self) -> & Giopdrc { & self . giopdrc } # [doc = "0x8c - GIO pul disable for port C"]
# [inline (always)]
pub const fn giopuldisc (& self) -> & Giopuldisc { & self . giopuldisc } # [doc = "0x90 - GIO pul select for port C"]
# [inline (always)]
pub const fn giopslc (& self) -> & Giopslc { & self . giopslc } # [doc = "0x94 - GIO data direction of pins in Port D"]
# [inline (always)]
pub const fn giodird (& self) -> & Giodird { & self . giodird } # [doc = "0x98 - GIO data input for pins in port D"]
# [inline (always)]
pub const fn giodind (& self) -> & Giodind { & self . giodind } # [doc = "0x9c - GIO data output for pins in port D"]
# [inline (always)]
pub const fn giodoutd (& self) -> & Giodoutd { & self . giodoutd } # [doc = "0xa0 - GIO data set for port D"]
# [inline (always)]
pub const fn giosetd (& self) -> & Giosetd { & self . giosetd } # [doc = "0xa4 - GIO data clear for port D"]
# [inline (always)]
pub const fn gioclrd (& self) -> & Gioclrd { & self . gioclrd } # [doc = "0xa8 - GIO open drain for port D"]
# [inline (always)]
pub const fn giopdrd (& self) -> & Giopdrd { & self . giopdrd } # [doc = "0xac - GIO pul disable for port D"]
# [inline (always)]
pub const fn giopuldisd (& self) -> & Giopuldisd { & self . giopuldisd } # [doc = "0xb0 - GIO pul select for port D"]
# [inline (always)]
pub const fn giopsld (& self) -> & Giopsld { & self . giopsld } # [doc = "0xb4 - GIO data direction of pins in Port E"]
# [inline (always)]
pub const fn giodire (& self) -> & Giodire { & self . giodire } # [doc = "0xb8 - GIO data input for pins in port E"]
# [inline (always)]
pub const fn giodine (& self) -> & Giodine { & self . giodine } # [doc = "0xbc - GIO data output for pins in port E"]
# [inline (always)]
pub const fn giodoute (& self) -> & Giodoute { & self . giodoute } # [doc = "0xc0 - GIO data set for port E"]
# [inline (always)]
pub const fn giosete (& self) -> & Giosete { & self . giosete } # [doc = "0xc4 - GIO data clear for port E"]
# [inline (always)]
pub const fn gioclre (& self) -> & Gioclre { & self . gioclre } # [doc = "0xc8 - GIO open drain for port E"]
# [inline (always)]
pub const fn giopdre (& self) -> & Giopdre { & self . giopdre } # [doc = "0xcc - GIO pul disable for port E"]
# [inline (always)]
pub const fn giopuldise (& self) -> & Giopuldise { & self . giopuldise } # [doc = "0xd0 - GIO pul select for port E"]
# [inline (always)]
pub const fn giopsle (& self) -> & Giopsle { & self . giopsle } # [doc = "0xd4 - GIO data direction of pins in Port F"]
# [inline (always)]
pub const fn giodirf (& self) -> & Giodirf { & self . giodirf } # [doc = "0xd8 - GIO data input for pins in Port F"]
# [inline (always)]
pub const fn giodinf (& self) -> & Giodinf { & self . giodinf } # [doc = "0xdc - GIO data output for pins in Port F"]
# [inline (always)]
pub const fn giodoutf (& self) -> & Giodoutf { & self . giodoutf } # [doc = "0xe0 - GIO data set for Port F"]
# [inline (always)]
pub const fn giosetf (& self) -> & Giosetf { & self . giosetf } # [doc = "0xe4 - GIO data clear for Port F"]
# [inline (always)]
pub const fn gioclrf (& self) -> & Gioclrf { & self . gioclrf } # [doc = "0xe8 - GIO open drain for Port F"]
# [inline (always)]
pub const fn giopdrf (& self) -> & Giopdrf { & self . giopdrf } # [doc = "0xec - GIO pul disable for port F"]
# [inline (always)]
pub const fn giopuldisf (& self) -> & Giopuldisf { & self . giopuldisf } # [doc = "0xf0 - GIO pul select for port F"]
# [inline (always)]
pub const fn giopslf (& self) -> & Giopslf { & self . giopslf } # [doc = "0xf4 - GIO data direction of pins in Port G"]
# [inline (always)]
pub const fn giodirg (& self) -> & Giodirg { & self . giodirg } # [doc = "0xf8 - GIO data input for pins in port G"]
# [inline (always)]
pub const fn gioding (& self) -> & Gioding { & self . gioding } # [doc = "0xfc - GIO data output for pins in port G"]
# [inline (always)]
pub const fn giodoutg (& self) -> & Giodoutg { & self . giodoutg } # [doc = "0x100 - GIO data set for port G"]
# [inline (always)]
pub const fn giosetg (& self) -> & Giosetg { & self . giosetg } # [doc = "0x104 - GIO data clear for port G"]
# [inline (always)]
pub const fn gioclrg (& self) -> & Gioclrg { & self . gioclrg } # [doc = "0x108 - GIO open drain for port G"]
# [inline (always)]
pub const fn giopdrg (& self) -> & Giopdrg { & self . giopdrg } # [doc = "0x10c - GIO pul disable for port G"]
# [inline (always)]
pub const fn giopuldisg (& self) -> & Giopuldisg { & self . giopuldisg } # [doc = "0x110 - GIO pul select for port G"]
# [inline (always)]
pub const fn giopslg (& self) -> & Giopslg { & self . giopslg } # [doc = "0x114 - GIO data direction of pins in Port H"]
# [inline (always)]
pub const fn giodirh (& self) -> & Giodirh { & self . giodirh } # [doc = "0x118 - GIO data input for pins in Port H"]
# [inline (always)]
pub const fn giodinh (& self) -> & Giodinh { & self . giodinh } # [doc = "0x11c - GIO data output for pins in Port H"]
# [inline (always)]
pub const fn giodouth (& self) -> & Giodouth { & self . giodouth } # [doc = "0x120 - GIO data set for Port H"]
# [inline (always)]
pub const fn gioseth (& self) -> & Gioseth { & self . gioseth } # [doc = "0x124 - GIO data clear for Port H"]
# [inline (always)]
pub const fn gioclrh (& self) -> & Gioclrh { & self . gioclrh } # [doc = "0x128 - GIO open drain for Port H"]
# [inline (always)]
pub const fn giopdrh (& self) -> & Giopdrh { & self . giopdrh } # [doc = "0x12c - GIO pul disable for port H"]
# [inline (always)]
pub const fn giopuldish (& self) -> & Giopuldish { & self . giopuldish } # [doc = "0x130 - GIO pul select for port H"]
# [inline (always)]
pub const fn giopslh (& self) -> & Giopslh { & self . giopslh } # [doc = "0x134 - GIO slew rate select for port A"]
# [inline (always)]
pub const fn giosrca (& self) -> & Giosrca { & self . giosrca } # [doc = "0x138 - GIO slew rate select for port B"]
# [inline (always)]
pub const fn giosrcb (& self) -> & Giosrcb { & self . giosrcb } # [doc = "0x13c - GIO slew rate select for port C"]
# [inline (always)]
pub const fn giosrcc (& self) -> & Giosrcc { & self . giosrcc } # [doc = "0x140 - GIO slew rate select for port D"]
# [inline (always)]
pub const fn giosrcd (& self) -> & Giosrcd { & self . giosrcd } # [doc = "0x144 - GIO slew rate select for port E"]
# [inline (always)]
pub const fn giosrce (& self) -> & Giosrce { & self . giosrce } # [doc = "0x148 - GIO slew rate select for port F"]
# [inline (always)]
pub const fn giosrcf (& self) -> & Giosrcf { & self . giosrcf } # [doc = "0x14c - GIO slew rate select for port G"]
# [inline (always)]
pub const fn giosrcg (& self) -> & Giosrcg { & self . giosrcg } # [doc = "0x150 - GIO slew rate select for port H"]
# [inline (always)]
pub const fn giosrch (& self) -> & Giosrch { & self . giosrch } } # [doc = "GIOGCR (rw) register accessor: GIO reset\n\nYou can [`read`](crate::Reg::read) this register and get [`giogcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giogcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giogcr`]
module"]
# [doc (alias = "GIOGCR")]
pub type Giogcr = crate :: Reg < giogcr :: GiogcrSpec > ; # [doc = "GIO reset"]
pub mod giogcr { # [doc = "Register `GIOGCR` reader"]
pub type R = crate :: R < GiogcrSpec > ; # [doc = "Register `GIOGCR` writer"]
pub type W = crate :: W < GiogcrSpec > ; # [doc = "Field `RESET` reader - 0:0\\]
GIO reset"]
pub type ResetR = crate :: BitReader ; # [doc = "Field `RESET` writer - 0:0\\]
GIO reset"]
pub type ResetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU0` reader - 31:1\\]
Reserved"]
pub type Nu0R = crate :: FieldReader < u32 > ; # [doc = "Field `NU0` writer - 31:1\\]
Reserved"]
pub type Nu0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
GIO reset"]
# [inline (always)]
pub fn reset (& self) -> ResetR { ResetR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu0 (& self) -> Nu0R { Nu0R :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
GIO reset"]
# [inline (always)]
# [must_use]
pub fn reset (& mut self) -> ResetW < GiogcrSpec > { ResetW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu0 (& mut self) -> Nu0W < GiogcrSpec > { Nu0W :: new (self , 1) } } # [doc = "GIO reset\n\nYou can [`read`](crate::Reg::read) this register and get [`giogcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giogcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiogcrSpec ; impl crate :: RegisterSpec for GiogcrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giogcr::R`](R) reader structure"]
impl crate :: Readable for GiogcrSpec { } # [doc = "`write(|w| ..)` method takes [`giogcr::W`](W) writer structure"]
impl crate :: Writable for GiogcrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOGCR to value 0"]
impl crate :: Resettable for GiogcrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPWDN (rw) register accessor: GIO power down mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`giopwdn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopwdn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopwdn`]
module"]
# [doc (alias = "GIOPWDN")]
pub type Giopwdn = crate :: Reg < giopwdn :: GiopwdnSpec > ; # [doc = "GIO power down mode register"]
pub mod giopwdn { # [doc = "Register `GIOPWDN` reader"]
pub type R = crate :: R < GiopwdnSpec > ; # [doc = "Register `GIOPWDN` writer"]
pub type W = crate :: W < GiopwdnSpec > ; # [doc = "Field `GIOPWDN` reader - 0:0\\]
Writing to the GIOPWDN bit is only allowed in privilege mode. Reading of the GIOPWDN bit is allowed in all modes. Privilege mode (write): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode User mode (write): Writes have no effect in user mode. User or privilege mode (read): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode"]
pub type GiopwdnR = crate :: BitReader ; # [doc = "Field `GIOPWDN` writer - 0:0\\]
Writing to the GIOPWDN bit is only allowed in privilege mode. Reading of the GIOPWDN bit is allowed in all modes. Privilege mode (write): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode User mode (write): Writes have no effect in user mode. User or privilege mode (read): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode"]
pub type GiopwdnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NU` reader - 31:1\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:1\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Writing to the GIOPWDN bit is only allowed in privilege mode. Reading of the GIOPWDN bit is allowed in all modes. Privilege mode (write): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode User mode (write): Writes have no effect in user mode. User or privilege mode (read): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode"]
# [inline (always)]
pub fn giopwdn (& self) -> GiopwdnR { GiopwdnR :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 1) & 0x7fff_ffff) } } impl W { # [doc = "Bit 0 - 0:0\\]
Writing to the GIOPWDN bit is only allowed in privilege mode. Reading of the GIOPWDN bit is allowed in all modes. Privilege mode (write): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode User mode (write): Writes have no effect in user mode. User or privilege mode (read): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode"]
# [inline (always)]
# [must_use]
pub fn giopwdn (& mut self) -> GiopwdnW < GiopwdnSpec > { GiopwdnW :: new (self , 0) } # [doc = "Bits 1:31 - 31:1\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < GiopwdnSpec > { NuW :: new (self , 1) } } # [doc = "GIO power down mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`giopwdn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopwdn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopwdnSpec ; impl crate :: RegisterSpec for GiopwdnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopwdn::R`](R) reader structure"]
impl crate :: Readable for GiopwdnSpec { } # [doc = "`write(|w| ..)` method takes [`giopwdn::W`](W) writer structure"]
impl crate :: Writable for GiopwdnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPWDN to value 0"]
impl crate :: Resettable for GiopwdnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOINTDET (rw) register accessor: Interrupt detection select for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giointdet::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giointdet::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giointdet`]
module"]
# [doc (alias = "GIOINTDET")]
pub type Giointdet = crate :: Reg < giointdet :: GiointdetSpec > ; # [doc = "Interrupt detection select for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod giointdet { # [doc = "Register `GIOINTDET` reader"]
pub type R = crate :: R < GiointdetSpec > ; # [doc = "Register `GIOINTDET` writer"]
pub type W = crate :: W < GiointdetSpec > ; # [doc = "Field `GIOINTDET_0` reader - 7:0\\]
Interrupt detection select for pins GIOA\\[7:0\\]."]
pub type Giointdet0R = crate :: FieldReader ; # [doc = "Field `GIOINTDET_0` writer - 7:0\\]
Interrupt detection select for pins GIOA\\[7:0\\]."]
pub type Giointdet0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOINTDET_1` reader - 15:8\\]
Interrupt detection select for pins GIOB\\[7:0\\]."]
pub type Giointdet1R = crate :: FieldReader ; # [doc = "Field `GIOINTDET_1` writer - 15:8\\]
Interrupt detection select for pins GIOB\\[7:0\\]."]
pub type Giointdet1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOINTDET_2` reader - 23:16\\]
Interrupt detection select for pins GIOC\\[7:0\\]."]
pub type Giointdet2R = crate :: FieldReader ; # [doc = "Field `GIOINTDET_2` writer - 23:16\\]
Interrupt detection select for pins GIOC\\[7:0\\]."]
pub type Giointdet2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOINTDET_3` reader - 31:24\\]
Interrupt detection select for pins GIOD\\[7:0\\]."]
pub type Giointdet3R = crate :: FieldReader ; # [doc = "Field `GIOINTDET_3` writer - 31:24\\]
Interrupt detection select for pins GIOD\\[7:0\\]."]
pub type Giointdet3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Interrupt detection select for pins GIOA\\[7:0\\]."]
# [inline (always)]
pub fn giointdet_0 (& self) -> Giointdet0R { Giointdet0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt detection select for pins GIOB\\[7:0\\]."]
# [inline (always)]
pub fn giointdet_1 (& self) -> Giointdet1R { Giointdet1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt detection select for pins GIOC\\[7:0\\]."]
# [inline (always)]
pub fn giointdet_2 (& self) -> Giointdet2R { Giointdet2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt detection select for pins GIOD\\[7:0\\]."]
# [inline (always)]
pub fn giointdet_3 (& self) -> Giointdet3R { Giointdet3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Interrupt detection select for pins GIOA\\[7:0\\]."]
# [inline (always)]
# [must_use]
pub fn giointdet_0 (& mut self) -> Giointdet0W < GiointdetSpec > { Giointdet0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt detection select for pins GIOB\\[7:0\\]."]
# [inline (always)]
# [must_use]
pub fn giointdet_1 (& mut self) -> Giointdet1W < GiointdetSpec > { Giointdet1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt detection select for pins GIOC\\[7:0\\]."]
# [inline (always)]
# [must_use]
pub fn giointdet_2 (& mut self) -> Giointdet2W < GiointdetSpec > { Giointdet2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt detection select for pins GIOD\\[7:0\\]."]
# [inline (always)]
# [must_use]
pub fn giointdet_3 (& mut self) -> Giointdet3W < GiointdetSpec > { Giointdet3W :: new (self , 24) } } # [doc = "Interrupt detection select for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giointdet::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giointdet::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiointdetSpec ; impl crate :: RegisterSpec for GiointdetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giointdet::R`](R) reader structure"]
impl crate :: Readable for GiointdetSpec { } # [doc = "`write(|w| ..)` method takes [`giointdet::W`](W) writer structure"]
impl crate :: Writable for GiointdetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOINTDET to value 0"]
impl crate :: Resettable for GiointdetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPOL (rw) register accessor: Interrupt polarity select for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giopol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopol`]
module"]
# [doc (alias = "GIOPOL")]
pub type Giopol = crate :: Reg < giopol :: GiopolSpec > ; # [doc = "Interrupt polarity select for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod giopol { # [doc = "Register `GIOPOL` reader"]
pub type R = crate :: R < GiopolSpec > ; # [doc = "Register `GIOPOL` writer"]
pub type W = crate :: W < GiopolSpec > ; # [doc = "Field `GIOPOL_0` reader - 7:0\\]
Interrupt polarity select for pins GIOA\\[7:0\\]"]
pub type Giopol0R = crate :: FieldReader ; # [doc = "Field `GIOPOL_0` writer - 7:0\\]
Interrupt polarity select for pins GIOA\\[7:0\\]"]
pub type Giopol0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOPOL_1` reader - 15:8\\]
Interrupt polarity select for pins GIOB\\[7:0\\]"]
pub type Giopol1R = crate :: FieldReader ; # [doc = "Field `GIOPOL_1` writer - 15:8\\]
Interrupt polarity select for pins GIOB\\[7:0\\]"]
pub type Giopol1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOPOL_2` reader - 23:16\\]
Interrupt polarity select for pins GIOC\\[7:0\\]"]
pub type Giopol2R = crate :: FieldReader ; # [doc = "Field `GIOPOL_2` writer - 23:16\\]
Interrupt polarity select for pins GIOC\\[7:0\\]"]
pub type Giopol2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOPOL_3` reader - 31:24\\]
Interrupt polarity select for pins GIOD\\[7:0\\]"]
pub type Giopol3R = crate :: FieldReader ; # [doc = "Field `GIOPOL_3` writer - 31:24\\]
Interrupt polarity select for pins GIOD\\[7:0\\]"]
pub type Giopol3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Interrupt polarity select for pins GIOA\\[7:0\\]"]
# [inline (always)]
pub fn giopol_0 (& self) -> Giopol0R { Giopol0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt polarity select for pins GIOB\\[7:0\\]"]
# [inline (always)]
pub fn giopol_1 (& self) -> Giopol1R { Giopol1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt polarity select for pins GIOC\\[7:0\\]"]
# [inline (always)]
pub fn giopol_2 (& self) -> Giopol2R { Giopol2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt polarity select for pins GIOD\\[7:0\\]"]
# [inline (always)]
pub fn giopol_3 (& self) -> Giopol3R { Giopol3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Interrupt polarity select for pins GIOA\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giopol_0 (& mut self) -> Giopol0W < GiopolSpec > { Giopol0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt polarity select for pins GIOB\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giopol_1 (& mut self) -> Giopol1W < GiopolSpec > { Giopol1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt polarity select for pins GIOC\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giopol_2 (& mut self) -> Giopol2W < GiopolSpec > { Giopol2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt polarity select for pins GIOD\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giopol_3 (& mut self) -> Giopol3W < GiopolSpec > { Giopol3W :: new (self , 24) } } # [doc = "Interrupt polarity select for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giopol::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopol::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopolSpec ; impl crate :: RegisterSpec for GiopolSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopol::R`](R) reader structure"]
impl crate :: Readable for GiopolSpec { } # [doc = "`write(|w| ..)` method takes [`giopol::W`](W) writer structure"]
impl crate :: Writable for GiopolSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPOL to value 0"]
impl crate :: Resettable for GiopolSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOENASET (rw) register accessor: Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`gioenaset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioenaset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioenaset`]
module"]
# [doc (alias = "GIOENASET")]
pub type Gioenaset = crate :: Reg < gioenaset :: GioenasetSpec > ; # [doc = "Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod gioenaset { # [doc = "Register `GIOENASET` reader"]
pub type R = crate :: R < GioenasetSpec > ; # [doc = "Register `GIOENASET` writer"]
pub type W = crate :: W < GioenasetSpec > ; # [doc = "Field `GIOENASET_0` reader - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
pub type Gioenaset0R = crate :: FieldReader ; # [doc = "Field `GIOENASET_0` writer - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
pub type Gioenaset0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOENASET_1` reader - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
pub type Gioenaset1R = crate :: FieldReader ; # [doc = "Field `GIOENASET_1` writer - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
pub type Gioenaset1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOENASET_2` reader - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
pub type Gioenaset2R = crate :: FieldReader ; # [doc = "Field `GIOENASET_2` writer - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
pub type Gioenaset2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOENASET_3` reader - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
pub type Gioenaset3R = crate :: FieldReader ; # [doc = "Field `GIOENASET_3` writer - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
pub type Gioenaset3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
# [inline (always)]
pub fn gioenaset_0 (& self) -> Gioenaset0R { Gioenaset0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
# [inline (always)]
pub fn gioenaset_1 (& self) -> Gioenaset1R { Gioenaset1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
# [inline (always)]
pub fn gioenaset_2 (& self) -> Gioenaset2R { Gioenaset2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
# [inline (always)]
pub fn gioenaset_3 (& self) -> Gioenaset3R { Gioenaset3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaset_0 (& mut self) -> Gioenaset0W < GioenasetSpec > { Gioenaset0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaset_1 (& mut self) -> Gioenaset1W < GioenasetSpec > { Gioenaset1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaset_2 (& mut self) -> Gioenaset2W < GioenasetSpec > { Gioenaset2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaset_3 (& mut self) -> Gioenaset3W < GioenasetSpec > { Gioenaset3W :: new (self , 24) } } # [doc = "Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`gioenaset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioenaset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioenasetSpec ; impl crate :: RegisterSpec for GioenasetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioenaset::R`](R) reader structure"]
impl crate :: Readable for GioenasetSpec { } # [doc = "`write(|w| ..)` method takes [`gioenaset::W`](W) writer structure"]
impl crate :: Writable for GioenasetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOENASET to value 0"]
impl crate :: Resettable for GioenasetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOENACLR (rw) register accessor: Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`gioenaclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioenaclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioenaclr`]
module"]
# [doc (alias = "GIOENACLR")]
pub type Gioenaclr = crate :: Reg < gioenaclr :: GioenaclrSpec > ; # [doc = "Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod gioenaclr { # [doc = "Register `GIOENACLR` reader"]
pub type R = crate :: R < GioenaclrSpec > ; # [doc = "Register `GIOENACLR` writer"]
pub type W = crate :: W < GioenaclrSpec > ; # [doc = "Field `GIOENACLR_0` reader - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
pub type Gioenaclr0R = crate :: FieldReader ; # [doc = "Field `GIOENACLR_0` writer - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
pub type Gioenaclr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOENACLR_1` reader - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
pub type Gioenaclr1R = crate :: FieldReader ; # [doc = "Field `GIOENACLR_1` writer - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
pub type Gioenaclr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOENACLR_2` reader - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
pub type Gioenaclr2R = crate :: FieldReader ; # [doc = "Field `GIOENACLR_2` writer - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
pub type Gioenaclr2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOENACLR_3` reader - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
pub type Gioenaclr3R = crate :: FieldReader ; # [doc = "Field `GIOENACLR_3` writer - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
pub type Gioenaclr3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
# [inline (always)]
pub fn gioenaclr_0 (& self) -> Gioenaclr0R { Gioenaclr0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
# [inline (always)]
pub fn gioenaclr_1 (& self) -> Gioenaclr1R { Gioenaclr1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
# [inline (always)]
pub fn gioenaclr_2 (& self) -> Gioenaclr2R { Gioenaclr2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
# [inline (always)]
pub fn gioenaclr_3 (& self) -> Gioenaclr3R { Gioenaclr3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Interrupt enable for pins GIOA \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaclr_0 (& mut self) -> Gioenaclr0W < GioenaclrSpec > { Gioenaclr0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Interrupt enable for pins GIOB \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaclr_1 (& mut self) -> Gioenaclr1W < GioenaclrSpec > { Gioenaclr1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
Interrupt enable for pins GIOC \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaclr_2 (& mut self) -> Gioenaclr2W < GioenaclrSpec > { Gioenaclr2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
Interrupt enable for pins GIOD \\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioenaclr_3 (& mut self) -> Gioenaclr3W < GioenaclrSpec > { Gioenaclr3W :: new (self , 24) } } # [doc = "Interrupt enable for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`gioenaclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioenaclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioenaclrSpec ; impl crate :: RegisterSpec for GioenaclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioenaclr::R`](R) reader structure"]
impl crate :: Readable for GioenaclrSpec { } # [doc = "`write(|w| ..)` method takes [`gioenaclr::W`](W) writer structure"]
impl crate :: Writable for GioenaclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOENACLR to value 0"]
impl crate :: Resettable for GioenaclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOLVLSET (rw) register accessor: GIO high priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giolvlset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giolvlset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giolvlset`]
module"]
# [doc (alias = "GIOLVLSET")]
pub type Giolvlset = crate :: Reg < giolvlset :: GiolvlsetSpec > ; # [doc = "GIO high priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod giolvlset { # [doc = "Register `GIOLVLSET` reader"]
pub type R = crate :: R < GiolvlsetSpec > ; # [doc = "Register `GIOLVLSET` writer"]
pub type W = crate :: W < GiolvlsetSpec > ; # [doc = "Field `GIOLVLSET_0` reader - 7:0\\]
GIO high priority interrupt for pins GIOA\\[7:0\\]"]
pub type Giolvlset0R = crate :: FieldReader ; # [doc = "Field `GIOLVLSET_0` writer - 7:0\\]
GIO high priority interrupt for pins GIOA\\[7:0\\]"]
pub type Giolvlset0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOLVLSET_1` reader - 15:8\\]
GIO high priority interrupt for pins GIOB\\[7:0\\]"]
pub type Giolvlset1R = crate :: FieldReader ; # [doc = "Field `GIOLVLSET_1` writer - 15:8\\]
GIO high priority interrupt for pins GIOB\\[7:0\\]"]
pub type Giolvlset1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOLVLSET_2` reader - 23:16\\]
GIO high priority interrupt for pins GIOC\\[7:0\\]"]
pub type Giolvlset2R = crate :: FieldReader ; # [doc = "Field `GIOLVLSET_2` writer - 23:16\\]
GIO high priority interrupt for pins GIOC\\[7:0\\]"]
pub type Giolvlset2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOLVLSET_3` reader - 31:24\\]
GIO high priority interrupt for pins GIOD\\[7:0\\]"]
pub type Giolvlset3R = crate :: FieldReader ; # [doc = "Field `GIOLVLSET_3` writer - 31:24\\]
GIO high priority interrupt for pins GIOD\\[7:0\\]"]
pub type Giolvlset3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO high priority interrupt for pins GIOA\\[7:0\\]"]
# [inline (always)]
pub fn giolvlset_0 (& self) -> Giolvlset0R { Giolvlset0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
GIO high priority interrupt for pins GIOB\\[7:0\\]"]
# [inline (always)]
pub fn giolvlset_1 (& self) -> Giolvlset1R { Giolvlset1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
GIO high priority interrupt for pins GIOC\\[7:0\\]"]
# [inline (always)]
pub fn giolvlset_2 (& self) -> Giolvlset2R { Giolvlset2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
GIO high priority interrupt for pins GIOD\\[7:0\\]"]
# [inline (always)]
pub fn giolvlset_3 (& self) -> Giolvlset3R { Giolvlset3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO high priority interrupt for pins GIOA\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlset_0 (& mut self) -> Giolvlset0W < GiolvlsetSpec > { Giolvlset0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
GIO high priority interrupt for pins GIOB\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlset_1 (& mut self) -> Giolvlset1W < GiolvlsetSpec > { Giolvlset1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
GIO high priority interrupt for pins GIOC\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlset_2 (& mut self) -> Giolvlset2W < GiolvlsetSpec > { Giolvlset2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
GIO high priority interrupt for pins GIOD\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlset_3 (& mut self) -> Giolvlset3W < GiolvlsetSpec > { Giolvlset3W :: new (self , 24) } } # [doc = "GIO high priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giolvlset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giolvlset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiolvlsetSpec ; impl crate :: RegisterSpec for GiolvlsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giolvlset::R`](R) reader structure"]
impl crate :: Readable for GiolvlsetSpec { } # [doc = "`write(|w| ..)` method takes [`giolvlset::W`](W) writer structure"]
impl crate :: Writable for GiolvlsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOLVLSET to value 0"]
impl crate :: Resettable for GiolvlsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOLVLCLR (rw) register accessor: GIO low priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giolvlclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giolvlclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giolvlclr`]
module"]
# [doc (alias = "GIOLVLCLR")]
pub type Giolvlclr = crate :: Reg < giolvlclr :: GiolvlclrSpec > ; # [doc = "GIO low priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod giolvlclr { # [doc = "Register `GIOLVLCLR` reader"]
pub type R = crate :: R < GiolvlclrSpec > ; # [doc = "Register `GIOLVLCLR` writer"]
pub type W = crate :: W < GiolvlclrSpec > ; # [doc = "Field `GIOLVLCLR_0` reader - 7:0\\]
GIO low priority interrupt for pins GIOA\\[7:0\\]"]
pub type Giolvlclr0R = crate :: FieldReader ; # [doc = "Field `GIOLVLCLR_0` writer - 7:0\\]
GIO low priority interrupt for pins GIOA\\[7:0\\]"]
pub type Giolvlclr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOLVLCLR_1` reader - 15:8\\]
GIO low priority interrupt for pins GIOB\\[7:0\\]"]
pub type Giolvlclr1R = crate :: FieldReader ; # [doc = "Field `GIOLVLCLR_1` writer - 15:8\\]
GIO low priority interrupt for pins GIOB\\[7:0\\]"]
pub type Giolvlclr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOLVLCLR_2` reader - 23:16\\]
GIO low priority interrupt for pins GIOC\\[7:0\\]"]
pub type Giolvlclr2R = crate :: FieldReader ; # [doc = "Field `GIOLVLCLR_2` writer - 23:16\\]
GIO low priority interrupt for pins GIOC\\[7:0\\]"]
pub type Giolvlclr2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOLVLCLR_3` reader - 31:24\\]
GIO low priority interrupt for pins GIOD\\[7:0\\]"]
pub type Giolvlclr3R = crate :: FieldReader ; # [doc = "Field `GIOLVLCLR_3` writer - 31:24\\]
GIO low priority interrupt for pins GIOD\\[7:0\\]"]
pub type Giolvlclr3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO low priority interrupt for pins GIOA\\[7:0\\]"]
# [inline (always)]
pub fn giolvlclr_0 (& self) -> Giolvlclr0R { Giolvlclr0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
GIO low priority interrupt for pins GIOB\\[7:0\\]"]
# [inline (always)]
pub fn giolvlclr_1 (& self) -> Giolvlclr1R { Giolvlclr1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
GIO low priority interrupt for pins GIOC\\[7:0\\]"]
# [inline (always)]
pub fn giolvlclr_2 (& self) -> Giolvlclr2R { Giolvlclr2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
GIO low priority interrupt for pins GIOD\\[7:0\\]"]
# [inline (always)]
pub fn giolvlclr_3 (& self) -> Giolvlclr3R { Giolvlclr3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO low priority interrupt for pins GIOA\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlclr_0 (& mut self) -> Giolvlclr0W < GiolvlclrSpec > { Giolvlclr0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
GIO low priority interrupt for pins GIOB\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlclr_1 (& mut self) -> Giolvlclr1W < GiolvlclrSpec > { Giolvlclr1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
GIO low priority interrupt for pins GIOC\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlclr_2 (& mut self) -> Giolvlclr2W < GiolvlclrSpec > { Giolvlclr2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
GIO low priority interrupt for pins GIOD\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn giolvlclr_3 (& mut self) -> Giolvlclr3W < GiolvlclrSpec > { Giolvlclr3W :: new (self , 24) } } # [doc = "GIO low priority interrupt for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`giolvlclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giolvlclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiolvlclrSpec ; impl crate :: RegisterSpec for GiolvlclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giolvlclr::R`](R) reader structure"]
impl crate :: Readable for GiolvlclrSpec { } # [doc = "`write(|w| ..)` method takes [`giolvlclr::W`](W) writer structure"]
impl crate :: Writable for GiolvlclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOLVLCLR to value 0"]
impl crate :: Resettable for GiolvlclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOFLG (rw) register accessor: GIO flag for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`gioflg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioflg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioflg`]
module"]
# [doc (alias = "GIOFLG")]
pub type Gioflg = crate :: Reg < gioflg :: GioflgSpec > ; # [doc = "GIO flag for pins \\[0:1\\]
GIO\\[7:0\\]."]
pub mod gioflg { # [doc = "Register `GIOFLG` reader"]
pub type R = crate :: R < GioflgSpec > ; # [doc = "Register `GIOFLG` writer"]
pub type W = crate :: W < GioflgSpec > ; # [doc = "Field `GIOFLG_0` reader - 7:0\\]
GIO flag for pins GIOA\\[7:0\\]"]
pub type Gioflg0R = crate :: FieldReader ; # [doc = "Field `GIOFLG_0` writer - 7:0\\]
GIO flag for pins GIOA\\[7:0\\]"]
pub type Gioflg0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOFLG_1` reader - 15:8\\]
GIO flag for pins GIOB\\[7:0\\]"]
pub type Gioflg1R = crate :: FieldReader ; # [doc = "Field `GIOFLG_1` writer - 15:8\\]
GIO flag for pins GIOB\\[7:0\\]"]
pub type Gioflg1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOFLG_2` reader - 23:16\\]
GIO flag for pins GIOC\\[7:0\\]"]
pub type Gioflg2R = crate :: FieldReader ; # [doc = "Field `GIOFLG_2` writer - 23:16\\]
GIO flag for pins GIOC\\[7:0\\]"]
pub type Gioflg2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GIOFLG_3` reader - 31:24\\]
GIO flag for pins GIOD\\[7:0\\]"]
pub type Gioflg3R = crate :: FieldReader ; # [doc = "Field `GIOFLG_3` writer - 31:24\\]
GIO flag for pins GIOD\\[7:0\\]"]
pub type Gioflg3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO flag for pins GIOA\\[7:0\\]"]
# [inline (always)]
pub fn gioflg_0 (& self) -> Gioflg0R { Gioflg0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
GIO flag for pins GIOB\\[7:0\\]"]
# [inline (always)]
pub fn gioflg_1 (& self) -> Gioflg1R { Gioflg1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
GIO flag for pins GIOC\\[7:0\\]"]
# [inline (always)]
pub fn gioflg_2 (& self) -> Gioflg2R { Gioflg2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
GIO flag for pins GIOD\\[7:0\\]"]
# [inline (always)]
pub fn gioflg_3 (& self) -> Gioflg3R { Gioflg3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO flag for pins GIOA\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioflg_0 (& mut self) -> Gioflg0W < GioflgSpec > { Gioflg0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
GIO flag for pins GIOB\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioflg_1 (& mut self) -> Gioflg1W < GioflgSpec > { Gioflg1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
GIO flag for pins GIOC\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioflg_2 (& mut self) -> Gioflg2W < GioflgSpec > { Gioflg2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
GIO flag for pins GIOD\\[7:0\\]"]
# [inline (always)]
# [must_use]
pub fn gioflg_3 (& mut self) -> Gioflg3W < GioflgSpec > { Gioflg3W :: new (self , 24) } } # [doc = "GIO flag for pins \\[0:1\\]
GIO\\[7:0\\].\n\nYou can [`read`](crate::Reg::read) this register and get [`gioflg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioflg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioflgSpec ; impl crate :: RegisterSpec for GioflgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioflg::R`](R) reader structure"]
impl crate :: Readable for GioflgSpec { } # [doc = "`write(|w| ..)` method takes [`gioflg::W`](W) writer structure"]
impl crate :: Writable for GioflgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOFLG to value 0"]
impl crate :: Resettable for GioflgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOOFFA (rw) register accessor: Index bits for currently pending high-priority interrupt Register A\n\nYou can [`read`](crate::Reg::read) this register and get [`giooffa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giooffa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giooffa`]
module"]
# [doc (alias = "GIOOFFA")]
pub type Giooffa = crate :: Reg < giooffa :: GiooffaSpec > ; # [doc = "Index bits for currently pending high-priority interrupt Register A"]
pub mod giooffa { # [doc = "Register `GIOOFFA` reader"]
pub type R = crate :: R < GiooffaSpec > ; # [doc = "Register `GIOOFFA` writer"]
pub type W = crate :: W < GiooffaSpec > ; # [doc = "Field `GIOOFFA` reader - 5:0\\]
Index bits for currently pending high-priority interrupt Register A"]
pub type GiooffaR = crate :: FieldReader ; # [doc = "Field `GIOOFFA` writer - 5:0\\]
Index bits for currently pending high-priority interrupt Register A"]
pub type GiooffaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU1` reader - 31:6\\]
Reserved"]
pub type Nu1R = crate :: FieldReader < u32 > ; # [doc = "Field `NU1` writer - 31:6\\]
Reserved"]
pub type Nu1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Index bits for currently pending high-priority interrupt Register A"]
# [inline (always)]
pub fn giooffa (& self) -> GiooffaR { GiooffaR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu1 (& self) -> Nu1R { Nu1R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Index bits for currently pending high-priority interrupt Register A"]
# [inline (always)]
# [must_use]
pub fn giooffa (& mut self) -> GiooffaW < GiooffaSpec > { GiooffaW :: new (self , 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu1 (& mut self) -> Nu1W < GiooffaSpec > { Nu1W :: new (self , 6) } } # [doc = "Index bits for currently pending high-priority interrupt Register A\n\nYou can [`read`](crate::Reg::read) this register and get [`giooffa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giooffa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiooffaSpec ; impl crate :: RegisterSpec for GiooffaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giooffa::R`](R) reader structure"]
impl crate :: Readable for GiooffaSpec { } # [doc = "`write(|w| ..)` method takes [`giooffa::W`](W) writer structure"]
impl crate :: Writable for GiooffaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOOFFA to value 0"]
impl crate :: Resettable for GiooffaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOOFFB (rw) register accessor: Index bits for currently pending high-priority interrupt Register B\n\nYou can [`read`](crate::Reg::read) this register and get [`giooffb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giooffb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giooffb`]
module"]
# [doc (alias = "GIOOFFB")]
pub type Giooffb = crate :: Reg < giooffb :: GiooffbSpec > ; # [doc = "Index bits for currently pending high-priority interrupt Register B"]
pub mod giooffb { # [doc = "Register `GIOOFFB` reader"]
pub type R = crate :: R < GiooffbSpec > ; # [doc = "Register `GIOOFFB` writer"]
pub type W = crate :: W < GiooffbSpec > ; # [doc = "Field `GIOOFFB` reader - 5:0\\]
Index bits for currently pending high-priority interrupt Register B"]
pub type GiooffbR = crate :: FieldReader ; # [doc = "Field `GIOOFFB` writer - 5:0\\]
Index bits for currently pending high-priority interrupt Register B"]
pub type GiooffbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU2` reader - 31:6\\]
Reserved"]
pub type Nu2R = crate :: FieldReader < u32 > ; # [doc = "Field `NU2` writer - 31:6\\]
Reserved"]
pub type Nu2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Index bits for currently pending high-priority interrupt Register B"]
# [inline (always)]
pub fn giooffb (& self) -> GiooffbR { GiooffbR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu2 (& self) -> Nu2R { Nu2R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Index bits for currently pending high-priority interrupt Register B"]
# [inline (always)]
# [must_use]
pub fn giooffb (& mut self) -> GiooffbW < GiooffbSpec > { GiooffbW :: new (self , 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu2 (& mut self) -> Nu2W < GiooffbSpec > { Nu2W :: new (self , 6) } } # [doc = "Index bits for currently pending high-priority interrupt Register B\n\nYou can [`read`](crate::Reg::read) this register and get [`giooffb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giooffb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiooffbSpec ; impl crate :: RegisterSpec for GiooffbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giooffb::R`](R) reader structure"]
impl crate :: Readable for GiooffbSpec { } # [doc = "`write(|w| ..)` method takes [`giooffb::W`](W) writer structure"]
impl crate :: Writable for GiooffbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOOFFB to value 0"]
impl crate :: Resettable for GiooffbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOEMUA (rw) register accessor: GIO emulation register A\n\nYou can [`read`](crate::Reg::read) this register and get [`gioemua::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioemua::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioemua`]
module"]
# [doc (alias = "GIOEMUA")]
pub type Gioemua = crate :: Reg < gioemua :: GioemuaSpec > ; # [doc = "GIO emulation register A"]
pub mod gioemua { # [doc = "Register `GIOEMUA` reader"]
pub type R = crate :: R < GioemuaSpec > ; # [doc = "Register `GIOEMUA` writer"]
pub type W = crate :: W < GioemuaSpec > ; # [doc = "Field `GIOEMUA` reader - 5:0\\]
GIO emulation register A"]
pub type GioemuaR = crate :: FieldReader ; # [doc = "Field `GIOEMUA` writer - 5:0\\]
GIO emulation register A"]
pub type GioemuaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU3` reader - 31:6\\]
Reserved"]
pub type Nu3R = crate :: FieldReader < u32 > ; # [doc = "Field `NU3` writer - 31:6\\]
Reserved"]
pub type Nu3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
GIO emulation register A"]
# [inline (always)]
pub fn gioemua (& self) -> GioemuaR { GioemuaR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu3 (& self) -> Nu3R { Nu3R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
GIO emulation register A"]
# [inline (always)]
# [must_use]
pub fn gioemua (& mut self) -> GioemuaW < GioemuaSpec > { GioemuaW :: new (self , 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu3 (& mut self) -> Nu3W < GioemuaSpec > { Nu3W :: new (self , 6) } } # [doc = "GIO emulation register A\n\nYou can [`read`](crate::Reg::read) this register and get [`gioemua::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioemua::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioemuaSpec ; impl crate :: RegisterSpec for GioemuaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioemua::R`](R) reader structure"]
impl crate :: Readable for GioemuaSpec { } # [doc = "`write(|w| ..)` method takes [`gioemua::W`](W) writer structure"]
impl crate :: Writable for GioemuaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOEMUA to value 0"]
impl crate :: Resettable for GioemuaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOEMUB (rw) register accessor: GIO emulation register B\n\nYou can [`read`](crate::Reg::read) this register and get [`gioemub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioemub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioemub`]
module"]
# [doc (alias = "GIOEMUB")]
pub type Gioemub = crate :: Reg < gioemub :: GioemubSpec > ; # [doc = "GIO emulation register B"]
pub mod gioemub { # [doc = "Register `GIOEMUB` reader"]
pub type R = crate :: R < GioemubSpec > ; # [doc = "Register `GIOEMUB` writer"]
pub type W = crate :: W < GioemubSpec > ; # [doc = "Field `GIOEMUB` reader - 5:0\\]
GIO emulation register B"]
pub type GioemubR = crate :: FieldReader ; # [doc = "Field `GIOEMUB` writer - 5:0\\]
GIO emulation register B"]
pub type GioemubW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NU4` reader - 31:6\\]
Reserved"]
pub type Nu4R = crate :: FieldReader < u32 > ; # [doc = "Field `NU4` writer - 31:6\\]
Reserved"]
pub type Nu4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
GIO emulation register B"]
# [inline (always)]
pub fn gioemub (& self) -> GioemubR { GioemubR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
pub fn nu4 (& self) -> Nu4R { Nu4R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
GIO emulation register B"]
# [inline (always)]
# [must_use]
pub fn gioemub (& mut self) -> GioemubW < GioemubSpec > { GioemubW :: new (self , 0) } # [doc = "Bits 6:31 - 31:6\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu4 (& mut self) -> Nu4W < GioemubSpec > { Nu4W :: new (self , 6) } } # [doc = "GIO emulation register B\n\nYou can [`read`](crate::Reg::read) this register and get [`gioemub::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioemub::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioemubSpec ; impl crate :: RegisterSpec for GioemubSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioemub::R`](R) reader structure"]
impl crate :: Readable for GioemubSpec { } # [doc = "`write(|w| ..)` method takes [`gioemub::W`](W) writer structure"]
impl crate :: Writable for GioemubSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOEMUB to value 0"]
impl crate :: Resettable for GioemubSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRA (rw) register accessor: GIO data direction of pins in Port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giodira::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodira::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodira`]
module"]
# [doc (alias = "GIODIRA")]
pub type Giodira = crate :: Reg < giodira :: GiodiraSpec > ; # [doc = "GIO data direction of pins in Port A"]
pub mod giodira { # [doc = "Register `GIODIRA` reader"]
pub type R = crate :: R < GiodiraSpec > ; # [doc = "Register `GIODIRA` writer"]
pub type W = crate :: W < GiodiraSpec > ; # [doc = "Field `GIODIRA` reader - 7:0\\]
GIO data direction of pins in Port A"]
pub type GiodiraR = crate :: FieldReader ; # [doc = "Field `GIODIRA` writer - 7:0\\]
GIO data direction of pins in Port A"]
pub type GiodiraW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU5` reader - 31:8\\]
Reserved"]
pub type Nu5R = crate :: FieldReader < u32 > ; # [doc = "Field `NU5` writer - 31:8\\]
Reserved"]
pub type Nu5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port A"]
# [inline (always)]
pub fn giodira (& self) -> GiodiraR { GiodiraR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu5 (& self) -> Nu5R { Nu5R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port A"]
# [inline (always)]
# [must_use]
pub fn giodira (& mut self) -> GiodiraW < GiodiraSpec > { GiodiraW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu5 (& mut self) -> Nu5W < GiodiraSpec > { Nu5W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giodira::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodira::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodiraSpec ; impl crate :: RegisterSpec for GiodiraSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodira::R`](R) reader structure"]
impl crate :: Readable for GiodiraSpec { } # [doc = "`write(|w| ..)` method takes [`giodira::W`](W) writer structure"]
impl crate :: Writable for GiodiraSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRA to value 0"]
impl crate :: Resettable for GiodiraSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODINA (rw) register accessor: GIO data input for pins in port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giodina::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodina::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodina`]
module"]
# [doc (alias = "GIODINA")]
pub type Giodina = crate :: Reg < giodina :: GiodinaSpec > ; # [doc = "GIO data input for pins in port A"]
pub mod giodina { # [doc = "Register `GIODINA` reader"]
pub type R = crate :: R < GiodinaSpec > ; # [doc = "Register `GIODINA` writer"]
pub type W = crate :: W < GiodinaSpec > ; # [doc = "Field `GIODINA` reader - 7:0\\]
GIO data input for pins in port A"]
pub type GiodinaR = crate :: FieldReader ; # [doc = "Field `GIODINA` writer - 7:0\\]
GIO data input for pins in port A"]
pub type GiodinaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU11` reader - 31:8\\]
Reserved"]
pub type Nu11R = crate :: FieldReader < u32 > ; # [doc = "Field `NU11` writer - 31:8\\]
Reserved"]
pub type Nu11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port A"]
# [inline (always)]
pub fn giodina (& self) -> GiodinaR { GiodinaR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu11 (& self) -> Nu11R { Nu11R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port A"]
# [inline (always)]
# [must_use]
pub fn giodina (& mut self) -> GiodinaW < GiodinaSpec > { GiodinaW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu11 (& mut self) -> Nu11W < GiodinaSpec > { Nu11W :: new (self , 8) } } # [doc = "GIO data input for pins in port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giodina::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodina::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodinaSpec ; impl crate :: RegisterSpec for GiodinaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodina::R`](R) reader structure"]
impl crate :: Readable for GiodinaSpec { } # [doc = "`write(|w| ..)` method takes [`giodina::W`](W) writer structure"]
impl crate :: Writable for GiodinaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODINA to value 0"]
impl crate :: Resettable for GiodinaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTA (rw) register accessor: GIO data output for pins in port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giodouta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodouta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodouta`]
module"]
# [doc (alias = "GIODOUTA")]
pub type Giodouta = crate :: Reg < giodouta :: GiodoutaSpec > ; # [doc = "GIO data output for pins in port A"]
pub mod giodouta { # [doc = "Register `GIODOUTA` reader"]
pub type R = crate :: R < GiodoutaSpec > ; # [doc = "Register `GIODOUTA` writer"]
pub type W = crate :: W < GiodoutaSpec > ; # [doc = "Field `GIODOUTA` reader - 7:0\\]
GIO data output for pins in port A"]
pub type GiodoutaR = crate :: FieldReader ; # [doc = "Field `GIODOUTA` writer - 7:0\\]
GIO data output for pins in port A"]
pub type GiodoutaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU17` reader - 31:8\\]
Reserved"]
pub type Nu17R = crate :: FieldReader < u32 > ; # [doc = "Field `NU17` writer - 31:8\\]
Reserved"]
pub type Nu17W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port A"]
# [inline (always)]
pub fn giodouta (& self) -> GiodoutaR { GiodoutaR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu17 (& self) -> Nu17R { Nu17R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port A"]
# [inline (always)]
# [must_use]
pub fn giodouta (& mut self) -> GiodoutaW < GiodoutaSpec > { GiodoutaW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu17 (& mut self) -> Nu17W < GiodoutaSpec > { Nu17W :: new (self , 8) } } # [doc = "GIO data output for pins in port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giodouta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodouta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodoutaSpec ; impl crate :: RegisterSpec for GiodoutaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodouta::R`](R) reader structure"]
impl crate :: Readable for GiodoutaSpec { } # [doc = "`write(|w| ..)` method takes [`giodouta::W`](W) writer structure"]
impl crate :: Writable for GiodoutaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTA to value 0"]
impl crate :: Resettable for GiodoutaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETA (rw) register accessor: GIO data set for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`gioseta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioseta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioseta`]
module"]
# [doc (alias = "GIOSETA")]
pub type Gioseta = crate :: Reg < gioseta :: GiosetaSpec > ; # [doc = "GIO data set for port A"]
pub mod gioseta { # [doc = "Register `GIOSETA` reader"]
pub type R = crate :: R < GiosetaSpec > ; # [doc = "Register `GIOSETA` writer"]
pub type W = crate :: W < GiosetaSpec > ; # [doc = "Field `GIODSETA` reader - 7:0\\]
GIO data set for port A"]
pub type GiodsetaR = crate :: FieldReader ; # [doc = "Field `GIODSETA` writer - 7:0\\]
GIO data set for port A"]
pub type GiodsetaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU23` reader - 31:8\\]
Reserved"]
pub type Nu23R = crate :: FieldReader < u32 > ; # [doc = "Field `NU23` writer - 31:8\\]
Reserved"]
pub type Nu23W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port A"]
# [inline (always)]
pub fn giodseta (& self) -> GiodsetaR { GiodsetaR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu23 (& self) -> Nu23R { Nu23R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port A"]
# [inline (always)]
# [must_use]
pub fn giodseta (& mut self) -> GiodsetaW < GiosetaSpec > { GiodsetaW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu23 (& mut self) -> Nu23W < GiosetaSpec > { Nu23W :: new (self , 8) } } # [doc = "GIO data set for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`gioseta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioseta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosetaSpec ; impl crate :: RegisterSpec for GiosetaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioseta::R`](R) reader structure"]
impl crate :: Readable for GiosetaSpec { } # [doc = "`write(|w| ..)` method takes [`gioseta::W`](W) writer structure"]
impl crate :: Writable for GiosetaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETA to value 0"]
impl crate :: Resettable for GiosetaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRA (rw) register accessor: GIO data clear for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclra`]
module"]
# [doc (alias = "GIOCLRA")]
pub type Gioclra = crate :: Reg < gioclra :: GioclraSpec > ; # [doc = "GIO data clear for port A"]
pub mod gioclra { # [doc = "Register `GIOCLRA` reader"]
pub type R = crate :: R < GioclraSpec > ; # [doc = "Register `GIOCLRA` writer"]
pub type W = crate :: W < GioclraSpec > ; # [doc = "Field `GIODCLRA` reader - 7:0\\]
GIO data clear for port A"]
pub type GiodclraR = crate :: FieldReader ; # [doc = "Field `GIODCLRA` writer - 7:0\\]
GIO data clear for port A"]
pub type GiodclraW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU29` reader - 31:8\\]
Reserved"]
pub type Nu29R = crate :: FieldReader < u32 > ; # [doc = "Field `NU29` writer - 31:8\\]
Reserved"]
pub type Nu29W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port A"]
# [inline (always)]
pub fn giodclra (& self) -> GiodclraR { GiodclraR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu29 (& self) -> Nu29R { Nu29R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port A"]
# [inline (always)]
# [must_use]
pub fn giodclra (& mut self) -> GiodclraW < GioclraSpec > { GiodclraW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu29 (& mut self) -> Nu29W < GioclraSpec > { Nu29W :: new (self , 8) } } # [doc = "GIO data clear for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclraSpec ; impl crate :: RegisterSpec for GioclraSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclra::R`](R) reader structure"]
impl crate :: Readable for GioclraSpec { } # [doc = "`write(|w| ..)` method takes [`gioclra::W`](W) writer structure"]
impl crate :: Writable for GioclraSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRA to value 0"]
impl crate :: Resettable for GioclraSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRA (rw) register accessor: GIO open drain for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdra`]
module"]
# [doc (alias = "GIOPDRA")]
pub type Giopdra = crate :: Reg < giopdra :: GiopdraSpec > ; # [doc = "GIO open drain for port A"]
pub mod giopdra { # [doc = "Register `GIOPDRA` reader"]
pub type R = crate :: R < GiopdraSpec > ; # [doc = "Register `GIOPDRA` writer"]
pub type W = crate :: W < GiopdraSpec > ; # [doc = "Field `GIOPDRA` reader - 7:0\\]
GIO open drain for port A"]
pub type GiopdraR = crate :: FieldReader ; # [doc = "Field `GIOPDRA` writer - 7:0\\]
GIO open drain for port A"]
pub type GiopdraW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU35` reader - 31:8\\]
Reserved"]
pub type Nu35R = crate :: FieldReader < u32 > ; # [doc = "Field `NU35` writer - 31:8\\]
Reserved"]
pub type Nu35W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port A"]
# [inline (always)]
pub fn giopdra (& self) -> GiopdraR { GiopdraR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu35 (& self) -> Nu35R { Nu35R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port A"]
# [inline (always)]
# [must_use]
pub fn giopdra (& mut self) -> GiopdraW < GiopdraSpec > { GiopdraW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu35 (& mut self) -> Nu35W < GiopdraSpec > { Nu35W :: new (self , 8) } } # [doc = "GIO open drain for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdraSpec ; impl crate :: RegisterSpec for GiopdraSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdra::R`](R) reader structure"]
impl crate :: Readable for GiopdraSpec { } # [doc = "`write(|w| ..)` method takes [`giopdra::W`](W) writer structure"]
impl crate :: Writable for GiopdraSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRA to value 0"]
impl crate :: Resettable for GiopdraSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISA (rw) register accessor: GIO pul disable for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldisa`]
module"]
# [doc (alias = "GIOPULDISA")]
pub type Giopuldisa = crate :: Reg < giopuldisa :: GiopuldisaSpec > ; # [doc = "GIO pul disable for port A"]
pub mod giopuldisa { # [doc = "Register `GIOPULDISA` reader"]
pub type R = crate :: R < GiopuldisaSpec > ; # [doc = "Register `GIOPULDISA` writer"]
pub type W = crate :: W < GiopuldisaSpec > ; # [doc = "Field `GIOPULDISA` reader - 7:0\\]
GIO pull disable for port A"]
pub type GiopuldisaR = crate :: FieldReader ; # [doc = "Field `GIOPULDISA` writer - 7:0\\]
GIO pull disable for port A"]
pub type GiopuldisaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU` reader - 31:8\\]
Reserved"]
pub type NuR = crate :: FieldReader < u32 > ; # [doc = "Field `NU` writer - 31:8\\]
Reserved"]
pub type NuW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port A"]
# [inline (always)]
pub fn giopuldisa (& self) -> GiopuldisaR { GiopuldisaR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu (& self) -> NuR { NuR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port A"]
# [inline (always)]
# [must_use]
pub fn giopuldisa (& mut self) -> GiopuldisaW < GiopuldisaSpec > { GiopuldisaW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu (& mut self) -> NuW < GiopuldisaSpec > { NuW :: new (self , 8) } } # [doc = "GIO pul disable for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldisaSpec ; impl crate :: RegisterSpec for GiopuldisaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldisa::R`](R) reader structure"]
impl crate :: Readable for GiopuldisaSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldisa::W`](W) writer structure"]
impl crate :: Writable for GiopuldisaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISA to value 0"]
impl crate :: Resettable for GiopuldisaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLA (rw) register accessor: GIO pul select for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giopsla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopsla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopsla`]
module"]
# [doc (alias = "GIOPSLA")]
pub type Giopsla = crate :: Reg < giopsla :: GiopslaSpec > ; # [doc = "GIO pul select for port A"]
pub mod giopsla { # [doc = "Register `GIOPSLA` reader"]
pub type R = crate :: R < GiopslaSpec > ; # [doc = "Register `GIOPSLA` writer"]
pub type W = crate :: W < GiopslaSpec > ; # [doc = "Field `GIOPSLA` reader - 7:0\\]
GIO pull select for port A"]
pub type GiopslaR = crate :: FieldReader ; # [doc = "Field `GIOPSLA` writer - 7:0\\]
GIO pull select for port A"]
pub type GiopslaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU35` reader - 31:8\\]
Reserved"]
pub type Nu35R = crate :: FieldReader < u32 > ; # [doc = "Field `NU35` writer - 31:8\\]
Reserved"]
pub type Nu35W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port A"]
# [inline (always)]
pub fn giopsla (& self) -> GiopslaR { GiopslaR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu35 (& self) -> Nu35R { Nu35R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port A"]
# [inline (always)]
# [must_use]
pub fn giopsla (& mut self) -> GiopslaW < GiopslaSpec > { GiopslaW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu35 (& mut self) -> Nu35W < GiopslaSpec > { Nu35W :: new (self , 8) } } # [doc = "GIO pul select for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giopsla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopsla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopslaSpec ; impl crate :: RegisterSpec for GiopslaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopsla::R`](R) reader structure"]
impl crate :: Readable for GiopslaSpec { } # [doc = "`write(|w| ..)` method takes [`giopsla::W`](W) writer structure"]
impl crate :: Writable for GiopslaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLA to value 0"]
impl crate :: Resettable for GiopslaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRB (rw) register accessor: GIO data direction of pins in Port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodirb`]
module"]
# [doc (alias = "GIODIRB")]
pub type Giodirb = crate :: Reg < giodirb :: GiodirbSpec > ; # [doc = "GIO data direction of pins in Port B"]
pub mod giodirb { # [doc = "Register `GIODIRB` reader"]
pub type R = crate :: R < GiodirbSpec > ; # [doc = "Register `GIODIRB` writer"]
pub type W = crate :: W < GiodirbSpec > ; # [doc = "Field `GIODIRB` reader - 7:0\\]
GIO data direction of pins in Port B"]
pub type GiodirbR = crate :: FieldReader ; # [doc = "Field `GIODIRB` writer - 7:0\\]
GIO data direction of pins in Port B"]
pub type GiodirbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU6` reader - 31:8\\]
Reserved"]
pub type Nu6R = crate :: FieldReader < u32 > ; # [doc = "Field `NU6` writer - 31:8\\]
Reserved"]
pub type Nu6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port B"]
# [inline (always)]
pub fn giodirb (& self) -> GiodirbR { GiodirbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu6 (& self) -> Nu6R { Nu6R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port B"]
# [inline (always)]
# [must_use]
pub fn giodirb (& mut self) -> GiodirbW < GiodirbSpec > { GiodirbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu6 (& mut self) -> Nu6W < GiodirbSpec > { Nu6W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodirbSpec ; impl crate :: RegisterSpec for GiodirbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodirb::R`](R) reader structure"]
impl crate :: Readable for GiodirbSpec { } # [doc = "`write(|w| ..)` method takes [`giodirb::W`](W) writer structure"]
impl crate :: Writable for GiodirbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRB to value 0"]
impl crate :: Resettable for GiodirbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODINB (rw) register accessor: GIO data input for pins in port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodinb`]
module"]
# [doc (alias = "GIODINB")]
pub type Giodinb = crate :: Reg < giodinb :: GiodinbSpec > ; # [doc = "GIO data input for pins in port B"]
pub mod giodinb { # [doc = "Register `GIODINB` reader"]
pub type R = crate :: R < GiodinbSpec > ; # [doc = "Register `GIODINB` writer"]
pub type W = crate :: W < GiodinbSpec > ; # [doc = "Field `GIODINB` reader - 7:0\\]
GIO data input for pins in port B"]
pub type GiodinbR = crate :: FieldReader ; # [doc = "Field `GIODINB` writer - 7:0\\]
GIO data input for pins in port B"]
pub type GiodinbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU12` reader - 31:8\\]
Reserved"]
pub type Nu12R = crate :: FieldReader < u32 > ; # [doc = "Field `NU12` writer - 31:8\\]
Reserved"]
pub type Nu12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port B"]
# [inline (always)]
pub fn giodinb (& self) -> GiodinbR { GiodinbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu12 (& self) -> Nu12R { Nu12R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port B"]
# [inline (always)]
# [must_use]
pub fn giodinb (& mut self) -> GiodinbW < GiodinbSpec > { GiodinbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu12 (& mut self) -> Nu12W < GiodinbSpec > { Nu12W :: new (self , 8) } } # [doc = "GIO data input for pins in port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodinbSpec ; impl crate :: RegisterSpec for GiodinbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodinb::R`](R) reader structure"]
impl crate :: Readable for GiodinbSpec { } # [doc = "`write(|w| ..)` method takes [`giodinb::W`](W) writer structure"]
impl crate :: Writable for GiodinbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODINB to value 0"]
impl crate :: Resettable for GiodinbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTB (rw) register accessor: GIO data output for pins in port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodoutb`]
module"]
# [doc (alias = "GIODOUTB")]
pub type Giodoutb = crate :: Reg < giodoutb :: GiodoutbSpec > ; # [doc = "GIO data output for pins in port B"]
pub mod giodoutb { # [doc = "Register `GIODOUTB` reader"]
pub type R = crate :: R < GiodoutbSpec > ; # [doc = "Register `GIODOUTB` writer"]
pub type W = crate :: W < GiodoutbSpec > ; # [doc = "Field `GIODOUTB` reader - 7:0\\]
GIO data output for pins in port B"]
pub type GiodoutbR = crate :: FieldReader ; # [doc = "Field `GIODOUTB` writer - 7:0\\]
GIO data output for pins in port B"]
pub type GiodoutbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU18` reader - 31:8\\]
Reserved"]
pub type Nu18R = crate :: FieldReader < u32 > ; # [doc = "Field `NU18` writer - 31:8\\]
Reserved"]
pub type Nu18W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port B"]
# [inline (always)]
pub fn giodoutb (& self) -> GiodoutbR { GiodoutbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu18 (& self) -> Nu18R { Nu18R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port B"]
# [inline (always)]
# [must_use]
pub fn giodoutb (& mut self) -> GiodoutbW < GiodoutbSpec > { GiodoutbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu18 (& mut self) -> Nu18W < GiodoutbSpec > { Nu18W :: new (self , 8) } } # [doc = "GIO data output for pins in port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodoutbSpec ; impl crate :: RegisterSpec for GiodoutbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodoutb::R`](R) reader structure"]
impl crate :: Readable for GiodoutbSpec { } # [doc = "`write(|w| ..)` method takes [`giodoutb::W`](W) writer structure"]
impl crate :: Writable for GiodoutbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTB to value 0"]
impl crate :: Resettable for GiodoutbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETB (rw) register accessor: GIO data set for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosetb`]
module"]
# [doc (alias = "GIOSETB")]
pub type Giosetb = crate :: Reg < giosetb :: GiosetbSpec > ; # [doc = "GIO data set for port B"]
pub mod giosetb { # [doc = "Register `GIOSETB` reader"]
pub type R = crate :: R < GiosetbSpec > ; # [doc = "Register `GIOSETB` writer"]
pub type W = crate :: W < GiosetbSpec > ; # [doc = "Field `GIODSETB` reader - 7:0\\]
GIO data set for port B"]
pub type GiodsetbR = crate :: FieldReader ; # [doc = "Field `GIODSETB` writer - 7:0\\]
GIO data set for port B"]
pub type GiodsetbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU24` reader - 31:8\\]
Reserved"]
pub type Nu24R = crate :: FieldReader < u32 > ; # [doc = "Field `NU24` writer - 31:8\\]
Reserved"]
pub type Nu24W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port B"]
# [inline (always)]
pub fn giodsetb (& self) -> GiodsetbR { GiodsetbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu24 (& self) -> Nu24R { Nu24R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port B"]
# [inline (always)]
# [must_use]
pub fn giodsetb (& mut self) -> GiodsetbW < GiosetbSpec > { GiodsetbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu24 (& mut self) -> Nu24W < GiosetbSpec > { Nu24W :: new (self , 8) } } # [doc = "GIO data set for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosetbSpec ; impl crate :: RegisterSpec for GiosetbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosetb::R`](R) reader structure"]
impl crate :: Readable for GiosetbSpec { } # [doc = "`write(|w| ..)` method takes [`giosetb::W`](W) writer structure"]
impl crate :: Writable for GiosetbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETB to value 0"]
impl crate :: Resettable for GiosetbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRB (rw) register accessor: GIO data clear for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclrb`]
module"]
# [doc (alias = "GIOCLRB")]
pub type Gioclrb = crate :: Reg < gioclrb :: GioclrbSpec > ; # [doc = "GIO data clear for port B"]
pub mod gioclrb { # [doc = "Register `GIOCLRB` reader"]
pub type R = crate :: R < GioclrbSpec > ; # [doc = "Register `GIOCLRB` writer"]
pub type W = crate :: W < GioclrbSpec > ; # [doc = "Field `GIODCLRB` reader - 7:0\\]
GIO data clear for port B"]
pub type GiodclrbR = crate :: FieldReader ; # [doc = "Field `GIODCLRB` writer - 7:0\\]
GIO data clear for port B"]
pub type GiodclrbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU30` reader - 31:8\\]
Reserved"]
pub type Nu30R = crate :: FieldReader < u32 > ; # [doc = "Field `NU30` writer - 31:8\\]
Reserved"]
pub type Nu30W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port B"]
# [inline (always)]
pub fn giodclrb (& self) -> GiodclrbR { GiodclrbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu30 (& self) -> Nu30R { Nu30R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port B"]
# [inline (always)]
# [must_use]
pub fn giodclrb (& mut self) -> GiodclrbW < GioclrbSpec > { GiodclrbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu30 (& mut self) -> Nu30W < GioclrbSpec > { Nu30W :: new (self , 8) } } # [doc = "GIO data clear for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclrbSpec ; impl crate :: RegisterSpec for GioclrbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclrb::R`](R) reader structure"]
impl crate :: Readable for GioclrbSpec { } # [doc = "`write(|w| ..)` method takes [`gioclrb::W`](W) writer structure"]
impl crate :: Writable for GioclrbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRB to value 0"]
impl crate :: Resettable for GioclrbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRB (rw) register accessor: GIO open drain for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdrb`]
module"]
# [doc (alias = "GIOPDRB")]
pub type Giopdrb = crate :: Reg < giopdrb :: GiopdrbSpec > ; # [doc = "GIO open drain for port B"]
pub mod giopdrb { # [doc = "Register `GIOPDRB` reader"]
pub type R = crate :: R < GiopdrbSpec > ; # [doc = "Register `GIOPDRB` writer"]
pub type W = crate :: W < GiopdrbSpec > ; # [doc = "Field `GIOPDRB` reader - 7:0\\]
GIO open drain for port B"]
pub type GiopdrbR = crate :: FieldReader ; # [doc = "Field `GIOPDRB` writer - 7:0\\]
GIO open drain for port B"]
pub type GiopdrbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU36` reader - 31:8\\]
Reserved"]
pub type Nu36R = crate :: FieldReader < u32 > ; # [doc = "Field `NU36` writer - 31:8\\]
Reserved"]
pub type Nu36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port B"]
# [inline (always)]
pub fn giopdrb (& self) -> GiopdrbR { GiopdrbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu36 (& self) -> Nu36R { Nu36R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port B"]
# [inline (always)]
# [must_use]
pub fn giopdrb (& mut self) -> GiopdrbW < GiopdrbSpec > { GiopdrbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu36 (& mut self) -> Nu36W < GiopdrbSpec > { Nu36W :: new (self , 8) } } # [doc = "GIO open drain for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdrbSpec ; impl crate :: RegisterSpec for GiopdrbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdrb::R`](R) reader structure"]
impl crate :: Readable for GiopdrbSpec { } # [doc = "`write(|w| ..)` method takes [`giopdrb::W`](W) writer structure"]
impl crate :: Writable for GiopdrbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRB to value 0"]
impl crate :: Resettable for GiopdrbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISB (rw) register accessor: GIO pul disable for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldisb`]
module"]
# [doc (alias = "GIOPULDISB")]
pub type Giopuldisb = crate :: Reg < giopuldisb :: GiopuldisbSpec > ; # [doc = "GIO pul disable for port B"]
pub mod giopuldisb { # [doc = "Register `GIOPULDISB` reader"]
pub type R = crate :: R < GiopuldisbSpec > ; # [doc = "Register `GIOPULDISB` writer"]
pub type W = crate :: W < GiopuldisbSpec > ; # [doc = "Field `GIOPULDISB` reader - 7:0\\]
GIO pull disable for port B"]
pub type GiopuldisbR = crate :: FieldReader ; # [doc = "Field `GIOPULDISB` writer - 7:0\\]
GIO pull disable for port B"]
pub type GiopuldisbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU36` reader - 31:8\\]
Reserved"]
pub type Nu36R = crate :: FieldReader < u32 > ; # [doc = "Field `NU36` writer - 31:8\\]
Reserved"]
pub type Nu36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port B"]
# [inline (always)]
pub fn giopuldisb (& self) -> GiopuldisbR { GiopuldisbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu36 (& self) -> Nu36R { Nu36R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port B"]
# [inline (always)]
# [must_use]
pub fn giopuldisb (& mut self) -> GiopuldisbW < GiopuldisbSpec > { GiopuldisbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu36 (& mut self) -> Nu36W < GiopuldisbSpec > { Nu36W :: new (self , 8) } } # [doc = "GIO pul disable for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldisbSpec ; impl crate :: RegisterSpec for GiopuldisbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldisb::R`](R) reader structure"]
impl crate :: Readable for GiopuldisbSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldisb::W`](W) writer structure"]
impl crate :: Writable for GiopuldisbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISB to value 0"]
impl crate :: Resettable for GiopuldisbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLB (rw) register accessor: GIO pul select for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopslb`]
module"]
# [doc (alias = "GIOPSLB")]
pub type Giopslb = crate :: Reg < giopslb :: GiopslbSpec > ; # [doc = "GIO pul select for port B"]
pub mod giopslb { # [doc = "Register `GIOPSLB` reader"]
pub type R = crate :: R < GiopslbSpec > ; # [doc = "Register `GIOPSLB` writer"]
pub type W = crate :: W < GiopslbSpec > ; # [doc = "Field `GIOPSLB` reader - 7:0\\]
GIO pull select for port B"]
pub type GiopslbR = crate :: FieldReader ; # [doc = "Field `GIOPSLB` writer - 7:0\\]
GIO pull select for port B"]
pub type GiopslbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU36` reader - 31:8\\]
Reserved"]
pub type Nu36R = crate :: FieldReader < u32 > ; # [doc = "Field `NU36` writer - 31:8\\]
Reserved"]
pub type Nu36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port B"]
# [inline (always)]
pub fn giopslb (& self) -> GiopslbR { GiopslbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu36 (& self) -> Nu36R { Nu36R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port B"]
# [inline (always)]
# [must_use]
pub fn giopslb (& mut self) -> GiopslbW < GiopslbSpec > { GiopslbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu36 (& mut self) -> Nu36W < GiopslbSpec > { Nu36W :: new (self , 8) } } # [doc = "GIO pul select for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopslbSpec ; impl crate :: RegisterSpec for GiopslbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopslb::R`](R) reader structure"]
impl crate :: Readable for GiopslbSpec { } # [doc = "`write(|w| ..)` method takes [`giopslb::W`](W) writer structure"]
impl crate :: Writable for GiopslbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLB to value 0"]
impl crate :: Resettable for GiopslbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRC (rw) register accessor: GIO data direction of pins in Port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodirc`]
module"]
# [doc (alias = "GIODIRC")]
pub type Giodirc = crate :: Reg < giodirc :: GiodircSpec > ; # [doc = "GIO data direction of pins in Port C"]
pub mod giodirc { # [doc = "Register `GIODIRC` reader"]
pub type R = crate :: R < GiodircSpec > ; # [doc = "Register `GIODIRC` writer"]
pub type W = crate :: W < GiodircSpec > ; # [doc = "Field `GIODIRC` reader - 7:0\\]
GIO data direction of pins in Port C"]
pub type GiodircR = crate :: FieldReader ; # [doc = "Field `GIODIRC` writer - 7:0\\]
GIO data direction of pins in Port C"]
pub type GiodircW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU7` reader - 31:8\\]
Reserved"]
pub type Nu7R = crate :: FieldReader < u32 > ; # [doc = "Field `NU7` writer - 31:8\\]
Reserved"]
pub type Nu7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port C"]
# [inline (always)]
pub fn giodirc (& self) -> GiodircR { GiodircR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu7 (& self) -> Nu7R { Nu7R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port C"]
# [inline (always)]
# [must_use]
pub fn giodirc (& mut self) -> GiodircW < GiodircSpec > { GiodircW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu7 (& mut self) -> Nu7W < GiodircSpec > { Nu7W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodircSpec ; impl crate :: RegisterSpec for GiodircSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodirc::R`](R) reader structure"]
impl crate :: Readable for GiodircSpec { } # [doc = "`write(|w| ..)` method takes [`giodirc::W`](W) writer structure"]
impl crate :: Writable for GiodircSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRC to value 0"]
impl crate :: Resettable for GiodircSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODINC (rw) register accessor: GIO data input for pins in port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodinc`]
module"]
# [doc (alias = "GIODINC")]
pub type Giodinc = crate :: Reg < giodinc :: GiodincSpec > ; # [doc = "GIO data input for pins in port C"]
pub mod giodinc { # [doc = "Register `GIODINC` reader"]
pub type R = crate :: R < GiodincSpec > ; # [doc = "Register `GIODINC` writer"]
pub type W = crate :: W < GiodincSpec > ; # [doc = "Field `GIODINC` reader - 7:0\\]
GIO data input for pins in port C"]
pub type GiodincR = crate :: FieldReader ; # [doc = "Field `GIODINC` writer - 7:0\\]
GIO data input for pins in port C"]
pub type GiodincW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU13` reader - 31:8\\]
Reserved"]
pub type Nu13R = crate :: FieldReader < u32 > ; # [doc = "Field `NU13` writer - 31:8\\]
Reserved"]
pub type Nu13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port C"]
# [inline (always)]
pub fn giodinc (& self) -> GiodincR { GiodincR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu13 (& self) -> Nu13R { Nu13R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port C"]
# [inline (always)]
# [must_use]
pub fn giodinc (& mut self) -> GiodincW < GiodincSpec > { GiodincW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu13 (& mut self) -> Nu13W < GiodincSpec > { Nu13W :: new (self , 8) } } # [doc = "GIO data input for pins in port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodincSpec ; impl crate :: RegisterSpec for GiodincSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodinc::R`](R) reader structure"]
impl crate :: Readable for GiodincSpec { } # [doc = "`write(|w| ..)` method takes [`giodinc::W`](W) writer structure"]
impl crate :: Writable for GiodincSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODINC to value 0"]
impl crate :: Resettable for GiodincSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTC (rw) register accessor: GIO data output for pins in port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodoutc`]
module"]
# [doc (alias = "GIODOUTC")]
pub type Giodoutc = crate :: Reg < giodoutc :: GiodoutcSpec > ; # [doc = "GIO data output for pins in port C"]
pub mod giodoutc { # [doc = "Register `GIODOUTC` reader"]
pub type R = crate :: R < GiodoutcSpec > ; # [doc = "Register `GIODOUTC` writer"]
pub type W = crate :: W < GiodoutcSpec > ; # [doc = "Field `GIODOUTC` reader - 7:0\\]
GIO data output for pins in port C"]
pub type GiodoutcR = crate :: FieldReader ; # [doc = "Field `GIODOUTC` writer - 7:0\\]
GIO data output for pins in port C"]
pub type GiodoutcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU19` reader - 31:8\\]
Reserved"]
pub type Nu19R = crate :: FieldReader < u32 > ; # [doc = "Field `NU19` writer - 31:8\\]
Reserved"]
pub type Nu19W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port C"]
# [inline (always)]
pub fn giodoutc (& self) -> GiodoutcR { GiodoutcR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu19 (& self) -> Nu19R { Nu19R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port C"]
# [inline (always)]
# [must_use]
pub fn giodoutc (& mut self) -> GiodoutcW < GiodoutcSpec > { GiodoutcW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu19 (& mut self) -> Nu19W < GiodoutcSpec > { Nu19W :: new (self , 8) } } # [doc = "GIO data output for pins in port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodoutcSpec ; impl crate :: RegisterSpec for GiodoutcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodoutc::R`](R) reader structure"]
impl crate :: Readable for GiodoutcSpec { } # [doc = "`write(|w| ..)` method takes [`giodoutc::W`](W) writer structure"]
impl crate :: Writable for GiodoutcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTC to value 0"]
impl crate :: Resettable for GiodoutcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETC (rw) register accessor: GIO data set for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosetc`]
module"]
# [doc (alias = "GIOSETC")]
pub type Giosetc = crate :: Reg < giosetc :: GiosetcSpec > ; # [doc = "GIO data set for port C"]
pub mod giosetc { # [doc = "Register `GIOSETC` reader"]
pub type R = crate :: R < GiosetcSpec > ; # [doc = "Register `GIOSETC` writer"]
pub type W = crate :: W < GiosetcSpec > ; # [doc = "Field `GIODSETC` reader - 7:0\\]
GIO data set for port C"]
pub type GiodsetcR = crate :: FieldReader ; # [doc = "Field `GIODSETC` writer - 7:0\\]
GIO data set for port C"]
pub type GiodsetcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU25` reader - 31:8\\]
Reserved"]
pub type Nu25R = crate :: FieldReader < u32 > ; # [doc = "Field `NU25` writer - 31:8\\]
Reserved"]
pub type Nu25W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port C"]
# [inline (always)]
pub fn giodsetc (& self) -> GiodsetcR { GiodsetcR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu25 (& self) -> Nu25R { Nu25R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port C"]
# [inline (always)]
# [must_use]
pub fn giodsetc (& mut self) -> GiodsetcW < GiosetcSpec > { GiodsetcW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu25 (& mut self) -> Nu25W < GiosetcSpec > { Nu25W :: new (self , 8) } } # [doc = "GIO data set for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosetcSpec ; impl crate :: RegisterSpec for GiosetcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosetc::R`](R) reader structure"]
impl crate :: Readable for GiosetcSpec { } # [doc = "`write(|w| ..)` method takes [`giosetc::W`](W) writer structure"]
impl crate :: Writable for GiosetcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETC to value 0"]
impl crate :: Resettable for GiosetcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRC (rw) register accessor: GIO data clear for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclrc`]
module"]
# [doc (alias = "GIOCLRC")]
pub type Gioclrc = crate :: Reg < gioclrc :: GioclrcSpec > ; # [doc = "GIO data clear for port C"]
pub mod gioclrc { # [doc = "Register `GIOCLRC` reader"]
pub type R = crate :: R < GioclrcSpec > ; # [doc = "Register `GIOCLRC` writer"]
pub type W = crate :: W < GioclrcSpec > ; # [doc = "Field `GIODCLRC` reader - 7:0\\]
GIO data clear for port C"]
pub type GiodclrcR = crate :: FieldReader ; # [doc = "Field `GIODCLRC` writer - 7:0\\]
GIO data clear for port C"]
pub type GiodclrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU31` reader - 31:8\\]
Reserved"]
pub type Nu31R = crate :: FieldReader < u32 > ; # [doc = "Field `NU31` writer - 31:8\\]
Reserved"]
pub type Nu31W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port C"]
# [inline (always)]
pub fn giodclrc (& self) -> GiodclrcR { GiodclrcR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu31 (& self) -> Nu31R { Nu31R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port C"]
# [inline (always)]
# [must_use]
pub fn giodclrc (& mut self) -> GiodclrcW < GioclrcSpec > { GiodclrcW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu31 (& mut self) -> Nu31W < GioclrcSpec > { Nu31W :: new (self , 8) } } # [doc = "GIO data clear for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclrcSpec ; impl crate :: RegisterSpec for GioclrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclrc::R`](R) reader structure"]
impl crate :: Readable for GioclrcSpec { } # [doc = "`write(|w| ..)` method takes [`gioclrc::W`](W) writer structure"]
impl crate :: Writable for GioclrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRC to value 0"]
impl crate :: Resettable for GioclrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRC (rw) register accessor: GIO open drain for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdrc`]
module"]
# [doc (alias = "GIOPDRC")]
pub type Giopdrc = crate :: Reg < giopdrc :: GiopdrcSpec > ; # [doc = "GIO open drain for port C"]
pub mod giopdrc { # [doc = "Register `GIOPDRC` reader"]
pub type R = crate :: R < GiopdrcSpec > ; # [doc = "Register `GIOPDRC` writer"]
pub type W = crate :: W < GiopdrcSpec > ; # [doc = "Field `GIOPDRC` reader - 7:0\\]
GIO open drain for port C"]
pub type GiopdrcR = crate :: FieldReader ; # [doc = "Field `GIOPDRC` writer - 7:0\\]
GIO open drain for port C"]
pub type GiopdrcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU37` reader - 31:8\\]
Reserved"]
pub type Nu37R = crate :: FieldReader < u32 > ; # [doc = "Field `NU37` writer - 31:8\\]
Reserved"]
pub type Nu37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port C"]
# [inline (always)]
pub fn giopdrc (& self) -> GiopdrcR { GiopdrcR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu37 (& self) -> Nu37R { Nu37R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port C"]
# [inline (always)]
# [must_use]
pub fn giopdrc (& mut self) -> GiopdrcW < GiopdrcSpec > { GiopdrcW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu37 (& mut self) -> Nu37W < GiopdrcSpec > { Nu37W :: new (self , 8) } } # [doc = "GIO open drain for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdrcSpec ; impl crate :: RegisterSpec for GiopdrcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdrc::R`](R) reader structure"]
impl crate :: Readable for GiopdrcSpec { } # [doc = "`write(|w| ..)` method takes [`giopdrc::W`](W) writer structure"]
impl crate :: Writable for GiopdrcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRC to value 0"]
impl crate :: Resettable for GiopdrcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISC (rw) register accessor: GIO pul disable for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldisc`]
module"]
# [doc (alias = "GIOPULDISC")]
pub type Giopuldisc = crate :: Reg < giopuldisc :: GiopuldiscSpec > ; # [doc = "GIO pul disable for port C"]
pub mod giopuldisc { # [doc = "Register `GIOPULDISC` reader"]
pub type R = crate :: R < GiopuldiscSpec > ; # [doc = "Register `GIOPULDISC` writer"]
pub type W = crate :: W < GiopuldiscSpec > ; # [doc = "Field `GIOPULDISC` reader - 7:0\\]
GIO pull disable for port C"]
pub type GiopuldiscR = crate :: FieldReader ; # [doc = "Field `GIOPULDISC` writer - 7:0\\]
GIO pull disable for port C"]
pub type GiopuldiscW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU37` reader - 31:8\\]
Reserved"]
pub type Nu37R = crate :: FieldReader < u32 > ; # [doc = "Field `NU37` writer - 31:8\\]
Reserved"]
pub type Nu37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port C"]
# [inline (always)]
pub fn giopuldisc (& self) -> GiopuldiscR { GiopuldiscR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu37 (& self) -> Nu37R { Nu37R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port C"]
# [inline (always)]
# [must_use]
pub fn giopuldisc (& mut self) -> GiopuldiscW < GiopuldiscSpec > { GiopuldiscW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu37 (& mut self) -> Nu37W < GiopuldiscSpec > { Nu37W :: new (self , 8) } } # [doc = "GIO pul disable for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldiscSpec ; impl crate :: RegisterSpec for GiopuldiscSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldisc::R`](R) reader structure"]
impl crate :: Readable for GiopuldiscSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldisc::W`](W) writer structure"]
impl crate :: Writable for GiopuldiscSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISC to value 0"]
impl crate :: Resettable for GiopuldiscSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLC (rw) register accessor: GIO pul select for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopslc`]
module"]
# [doc (alias = "GIOPSLC")]
pub type Giopslc = crate :: Reg < giopslc :: GiopslcSpec > ; # [doc = "GIO pul select for port C"]
pub mod giopslc { # [doc = "Register `GIOPSLC` reader"]
pub type R = crate :: R < GiopslcSpec > ; # [doc = "Register `GIOPSLC` writer"]
pub type W = crate :: W < GiopslcSpec > ; # [doc = "Field `GIOPSLC` reader - 7:0\\]
GIO pull select for port C"]
pub type GiopslcR = crate :: FieldReader ; # [doc = "Field `GIOPSLC` writer - 7:0\\]
GIO pull select for port C"]
pub type GiopslcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU37` reader - 31:8\\]
Reserved"]
pub type Nu37R = crate :: FieldReader < u32 > ; # [doc = "Field `NU37` writer - 31:8\\]
Reserved"]
pub type Nu37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port C"]
# [inline (always)]
pub fn giopslc (& self) -> GiopslcR { GiopslcR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu37 (& self) -> Nu37R { Nu37R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port C"]
# [inline (always)]
# [must_use]
pub fn giopslc (& mut self) -> GiopslcW < GiopslcSpec > { GiopslcW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu37 (& mut self) -> Nu37W < GiopslcSpec > { Nu37W :: new (self , 8) } } # [doc = "GIO pul select for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopslcSpec ; impl crate :: RegisterSpec for GiopslcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopslc::R`](R) reader structure"]
impl crate :: Readable for GiopslcSpec { } # [doc = "`write(|w| ..)` method takes [`giopslc::W`](W) writer structure"]
impl crate :: Writable for GiopslcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLC to value 0"]
impl crate :: Resettable for GiopslcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRD (rw) register accessor: GIO data direction of pins in Port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giodird::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodird::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodird`]
module"]
# [doc (alias = "GIODIRD")]
pub type Giodird = crate :: Reg < giodird :: GiodirdSpec > ; # [doc = "GIO data direction of pins in Port D"]
pub mod giodird { # [doc = "Register `GIODIRD` reader"]
pub type R = crate :: R < GiodirdSpec > ; # [doc = "Register `GIODIRD` writer"]
pub type W = crate :: W < GiodirdSpec > ; # [doc = "Field `GIODIRD` reader - 7:0\\]
GIO data direction of pins in Port D"]
pub type GiodirdR = crate :: FieldReader ; # [doc = "Field `GIODIRD` writer - 7:0\\]
GIO data direction of pins in Port D"]
pub type GiodirdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU8` reader - 31:8\\]
Reserved"]
pub type Nu8R = crate :: FieldReader < u32 > ; # [doc = "Field `NU8` writer - 31:8\\]
Reserved"]
pub type Nu8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port D"]
# [inline (always)]
pub fn giodird (& self) -> GiodirdR { GiodirdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu8 (& self) -> Nu8R { Nu8R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port D"]
# [inline (always)]
# [must_use]
pub fn giodird (& mut self) -> GiodirdW < GiodirdSpec > { GiodirdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu8 (& mut self) -> Nu8W < GiodirdSpec > { Nu8W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giodird::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodird::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodirdSpec ; impl crate :: RegisterSpec for GiodirdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodird::R`](R) reader structure"]
impl crate :: Readable for GiodirdSpec { } # [doc = "`write(|w| ..)` method takes [`giodird::W`](W) writer structure"]
impl crate :: Writable for GiodirdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRD to value 0"]
impl crate :: Resettable for GiodirdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIND (rw) register accessor: GIO data input for pins in port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giodind::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodind::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodind`]
module"]
# [doc (alias = "GIODIND")]
pub type Giodind = crate :: Reg < giodind :: GiodindSpec > ; # [doc = "GIO data input for pins in port D"]
pub mod giodind { # [doc = "Register `GIODIND` reader"]
pub type R = crate :: R < GiodindSpec > ; # [doc = "Register `GIODIND` writer"]
pub type W = crate :: W < GiodindSpec > ; # [doc = "Field `GIODIND` reader - 7:0\\]
GIO data input for pins in port D"]
pub type GiodindR = crate :: FieldReader ; # [doc = "Field `GIODIND` writer - 7:0\\]
GIO data input for pins in port D"]
pub type GiodindW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU14` reader - 31:8\\]
Reserved"]
pub type Nu14R = crate :: FieldReader < u32 > ; # [doc = "Field `NU14` writer - 31:8\\]
Reserved"]
pub type Nu14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port D"]
# [inline (always)]
pub fn giodind (& self) -> GiodindR { GiodindR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu14 (& self) -> Nu14R { Nu14R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port D"]
# [inline (always)]
# [must_use]
pub fn giodind (& mut self) -> GiodindW < GiodindSpec > { GiodindW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu14 (& mut self) -> Nu14W < GiodindSpec > { Nu14W :: new (self , 8) } } # [doc = "GIO data input for pins in port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giodind::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodind::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodindSpec ; impl crate :: RegisterSpec for GiodindSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodind::R`](R) reader structure"]
impl crate :: Readable for GiodindSpec { } # [doc = "`write(|w| ..)` method takes [`giodind::W`](W) writer structure"]
impl crate :: Writable for GiodindSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIND to value 0"]
impl crate :: Resettable for GiodindSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTD (rw) register accessor: GIO data output for pins in port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodoutd`]
module"]
# [doc (alias = "GIODOUTD")]
pub type Giodoutd = crate :: Reg < giodoutd :: GiodoutdSpec > ; # [doc = "GIO data output for pins in port D"]
pub mod giodoutd { # [doc = "Register `GIODOUTD` reader"]
pub type R = crate :: R < GiodoutdSpec > ; # [doc = "Register `GIODOUTD` writer"]
pub type W = crate :: W < GiodoutdSpec > ; # [doc = "Field `GIODOUTD` reader - 7:0\\]
GIO data output for pins in port D"]
pub type GiodoutdR = crate :: FieldReader ; # [doc = "Field `GIODOUTD` writer - 7:0\\]
GIO data output for pins in port D"]
pub type GiodoutdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU20` reader - 31:8\\]
Reserved"]
pub type Nu20R = crate :: FieldReader < u32 > ; # [doc = "Field `NU20` writer - 31:8\\]
Reserved"]
pub type Nu20W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port D"]
# [inline (always)]
pub fn giodoutd (& self) -> GiodoutdR { GiodoutdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu20 (& self) -> Nu20R { Nu20R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port D"]
# [inline (always)]
# [must_use]
pub fn giodoutd (& mut self) -> GiodoutdW < GiodoutdSpec > { GiodoutdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu20 (& mut self) -> Nu20W < GiodoutdSpec > { Nu20W :: new (self , 8) } } # [doc = "GIO data output for pins in port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodoutdSpec ; impl crate :: RegisterSpec for GiodoutdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodoutd::R`](R) reader structure"]
impl crate :: Readable for GiodoutdSpec { } # [doc = "`write(|w| ..)` method takes [`giodoutd::W`](W) writer structure"]
impl crate :: Writable for GiodoutdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTD to value 0"]
impl crate :: Resettable for GiodoutdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETD (rw) register accessor: GIO data set for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosetd`]
module"]
# [doc (alias = "GIOSETD")]
pub type Giosetd = crate :: Reg < giosetd :: GiosetdSpec > ; # [doc = "GIO data set for port D"]
pub mod giosetd { # [doc = "Register `GIOSETD` reader"]
pub type R = crate :: R < GiosetdSpec > ; # [doc = "Register `GIOSETD` writer"]
pub type W = crate :: W < GiosetdSpec > ; # [doc = "Field `GIODSETD` reader - 7:0\\]
GIO data set for port D"]
pub type GiodsetdR = crate :: FieldReader ; # [doc = "Field `GIODSETD` writer - 7:0\\]
GIO data set for port D"]
pub type GiodsetdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU26` reader - 31:8\\]
Reserved"]
pub type Nu26R = crate :: FieldReader < u32 > ; # [doc = "Field `NU26` writer - 31:8\\]
Reserved"]
pub type Nu26W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port D"]
# [inline (always)]
pub fn giodsetd (& self) -> GiodsetdR { GiodsetdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu26 (& self) -> Nu26R { Nu26R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port D"]
# [inline (always)]
# [must_use]
pub fn giodsetd (& mut self) -> GiodsetdW < GiosetdSpec > { GiodsetdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu26 (& mut self) -> Nu26W < GiosetdSpec > { Nu26W :: new (self , 8) } } # [doc = "GIO data set for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosetdSpec ; impl crate :: RegisterSpec for GiosetdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosetd::R`](R) reader structure"]
impl crate :: Readable for GiosetdSpec { } # [doc = "`write(|w| ..)` method takes [`giosetd::W`](W) writer structure"]
impl crate :: Writable for GiosetdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETD to value 0"]
impl crate :: Resettable for GiosetdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRD (rw) register accessor: GIO data clear for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclrd`]
module"]
# [doc (alias = "GIOCLRD")]
pub type Gioclrd = crate :: Reg < gioclrd :: GioclrdSpec > ; # [doc = "GIO data clear for port D"]
pub mod gioclrd { # [doc = "Register `GIOCLRD` reader"]
pub type R = crate :: R < GioclrdSpec > ; # [doc = "Register `GIOCLRD` writer"]
pub type W = crate :: W < GioclrdSpec > ; # [doc = "Field `GIODCLRD` reader - 7:0\\]
GIO data clear for port D"]
pub type GiodclrdR = crate :: FieldReader ; # [doc = "Field `GIODCLRD` writer - 7:0\\]
GIO data clear for port D"]
pub type GiodclrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU32` reader - 31:8\\]
Reserved"]
pub type Nu32R = crate :: FieldReader < u32 > ; # [doc = "Field `NU32` writer - 31:8\\]
Reserved"]
pub type Nu32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port D"]
# [inline (always)]
pub fn giodclrd (& self) -> GiodclrdR { GiodclrdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu32 (& self) -> Nu32R { Nu32R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port D"]
# [inline (always)]
# [must_use]
pub fn giodclrd (& mut self) -> GiodclrdW < GioclrdSpec > { GiodclrdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu32 (& mut self) -> Nu32W < GioclrdSpec > { Nu32W :: new (self , 8) } } # [doc = "GIO data clear for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclrdSpec ; impl crate :: RegisterSpec for GioclrdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclrd::R`](R) reader structure"]
impl crate :: Readable for GioclrdSpec { } # [doc = "`write(|w| ..)` method takes [`gioclrd::W`](W) writer structure"]
impl crate :: Writable for GioclrdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRD to value 0"]
impl crate :: Resettable for GioclrdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRD (rw) register accessor: GIO open drain for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdrd`]
module"]
# [doc (alias = "GIOPDRD")]
pub type Giopdrd = crate :: Reg < giopdrd :: GiopdrdSpec > ; # [doc = "GIO open drain for port D"]
pub mod giopdrd { # [doc = "Register `GIOPDRD` reader"]
pub type R = crate :: R < GiopdrdSpec > ; # [doc = "Register `GIOPDRD` writer"]
pub type W = crate :: W < GiopdrdSpec > ; # [doc = "Field `GIOPDRD` reader - 7:0\\]
GIO open drain for port D"]
pub type GiopdrdR = crate :: FieldReader ; # [doc = "Field `GIOPDRD` writer - 7:0\\]
GIO open drain for port D"]
pub type GiopdrdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU38` reader - 31:8\\]
Reserved"]
pub type Nu38R = crate :: FieldReader < u32 > ; # [doc = "Field `NU38` writer - 31:8\\]
Reserved"]
pub type Nu38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port D"]
# [inline (always)]
pub fn giopdrd (& self) -> GiopdrdR { GiopdrdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu38 (& self) -> Nu38R { Nu38R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port D"]
# [inline (always)]
# [must_use]
pub fn giopdrd (& mut self) -> GiopdrdW < GiopdrdSpec > { GiopdrdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu38 (& mut self) -> Nu38W < GiopdrdSpec > { Nu38W :: new (self , 8) } } # [doc = "GIO open drain for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdrdSpec ; impl crate :: RegisterSpec for GiopdrdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdrd::R`](R) reader structure"]
impl crate :: Readable for GiopdrdSpec { } # [doc = "`write(|w| ..)` method takes [`giopdrd::W`](W) writer structure"]
impl crate :: Writable for GiopdrdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRD to value 0"]
impl crate :: Resettable for GiopdrdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISD (rw) register accessor: GIO pul disable for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldisd`]
module"]
# [doc (alias = "GIOPULDISD")]
pub type Giopuldisd = crate :: Reg < giopuldisd :: GiopuldisdSpec > ; # [doc = "GIO pul disable for port D"]
pub mod giopuldisd { # [doc = "Register `GIOPULDISD` reader"]
pub type R = crate :: R < GiopuldisdSpec > ; # [doc = "Register `GIOPULDISD` writer"]
pub type W = crate :: W < GiopuldisdSpec > ; # [doc = "Field `GIOPULDISD` reader - 7:0\\]
GIO pull disable for port D"]
pub type GiopuldisdR = crate :: FieldReader ; # [doc = "Field `GIOPULDISD` writer - 7:0\\]
GIO pull disable for port D"]
pub type GiopuldisdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU38` reader - 31:8\\]
Reserved"]
pub type Nu38R = crate :: FieldReader < u32 > ; # [doc = "Field `NU38` writer - 31:8\\]
Reserved"]
pub type Nu38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port D"]
# [inline (always)]
pub fn giopuldisd (& self) -> GiopuldisdR { GiopuldisdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu38 (& self) -> Nu38R { Nu38R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port D"]
# [inline (always)]
# [must_use]
pub fn giopuldisd (& mut self) -> GiopuldisdW < GiopuldisdSpec > { GiopuldisdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu38 (& mut self) -> Nu38W < GiopuldisdSpec > { Nu38W :: new (self , 8) } } # [doc = "GIO pul disable for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldisdSpec ; impl crate :: RegisterSpec for GiopuldisdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldisd::R`](R) reader structure"]
impl crate :: Readable for GiopuldisdSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldisd::W`](W) writer structure"]
impl crate :: Writable for GiopuldisdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISD to value 0"]
impl crate :: Resettable for GiopuldisdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLD (rw) register accessor: GIO pul select for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giopsld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopsld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopsld`]
module"]
# [doc (alias = "GIOPSLD")]
pub type Giopsld = crate :: Reg < giopsld :: GiopsldSpec > ; # [doc = "GIO pul select for port D"]
pub mod giopsld { # [doc = "Register `GIOPSLD` reader"]
pub type R = crate :: R < GiopsldSpec > ; # [doc = "Register `GIOPSLD` writer"]
pub type W = crate :: W < GiopsldSpec > ; # [doc = "Field `GIOPSLD` reader - 7:0\\]
GIO pull select for port D"]
pub type GiopsldR = crate :: FieldReader ; # [doc = "Field `GIOPSLD` writer - 7:0\\]
GIO pull select for port D"]
pub type GiopsldW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU38` reader - 31:8\\]
Reserved"]
pub type Nu38R = crate :: FieldReader < u32 > ; # [doc = "Field `NU38` writer - 31:8\\]
Reserved"]
pub type Nu38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port D"]
# [inline (always)]
pub fn giopsld (& self) -> GiopsldR { GiopsldR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu38 (& self) -> Nu38R { Nu38R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port D"]
# [inline (always)]
# [must_use]
pub fn giopsld (& mut self) -> GiopsldW < GiopsldSpec > { GiopsldW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu38 (& mut self) -> Nu38W < GiopsldSpec > { Nu38W :: new (self , 8) } } # [doc = "GIO pul select for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giopsld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopsld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopsldSpec ; impl crate :: RegisterSpec for GiopsldSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopsld::R`](R) reader structure"]
impl crate :: Readable for GiopsldSpec { } # [doc = "`write(|w| ..)` method takes [`giopsld::W`](W) writer structure"]
impl crate :: Writable for GiopsldSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLD to value 0"]
impl crate :: Resettable for GiopsldSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRE (rw) register accessor: GIO data direction of pins in Port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giodire::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodire::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodire`]
module"]
# [doc (alias = "GIODIRE")]
pub type Giodire = crate :: Reg < giodire :: GiodireSpec > ; # [doc = "GIO data direction of pins in Port E"]
pub mod giodire { # [doc = "Register `GIODIRE` reader"]
pub type R = crate :: R < GiodireSpec > ; # [doc = "Register `GIODIRE` writer"]
pub type W = crate :: W < GiodireSpec > ; # [doc = "Field `GIODIRE` reader - 7:0\\]
GIO data direction of pins in Port E"]
pub type GiodireR = crate :: FieldReader ; # [doc = "Field `GIODIRE` writer - 7:0\\]
GIO data direction of pins in Port E"]
pub type GiodireW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU9` reader - 31:8\\]
Reserved"]
pub type Nu9R = crate :: FieldReader < u32 > ; # [doc = "Field `NU9` writer - 31:8\\]
Reserved"]
pub type Nu9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port E"]
# [inline (always)]
pub fn giodire (& self) -> GiodireR { GiodireR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu9 (& self) -> Nu9R { Nu9R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port E"]
# [inline (always)]
# [must_use]
pub fn giodire (& mut self) -> GiodireW < GiodireSpec > { GiodireW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu9 (& mut self) -> Nu9W < GiodireSpec > { Nu9W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giodire::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodire::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodireSpec ; impl crate :: RegisterSpec for GiodireSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodire::R`](R) reader structure"]
impl crate :: Readable for GiodireSpec { } # [doc = "`write(|w| ..)` method takes [`giodire::W`](W) writer structure"]
impl crate :: Writable for GiodireSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRE to value 0"]
impl crate :: Resettable for GiodireSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODINE (rw) register accessor: GIO data input for pins in port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giodine::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodine::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodine`]
module"]
# [doc (alias = "GIODINE")]
pub type Giodine = crate :: Reg < giodine :: GiodineSpec > ; # [doc = "GIO data input for pins in port E"]
pub mod giodine { # [doc = "Register `GIODINE` reader"]
pub type R = crate :: R < GiodineSpec > ; # [doc = "Register `GIODINE` writer"]
pub type W = crate :: W < GiodineSpec > ; # [doc = "Field `GIODINE` reader - 7:0\\]
GIO data input for pins in port E"]
pub type GiodineR = crate :: FieldReader ; # [doc = "Field `GIODINE` writer - 7:0\\]
GIO data input for pins in port E"]
pub type GiodineW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU15` reader - 31:8\\]
Reserved"]
pub type Nu15R = crate :: FieldReader < u32 > ; # [doc = "Field `NU15` writer - 31:8\\]
Reserved"]
pub type Nu15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port E"]
# [inline (always)]
pub fn giodine (& self) -> GiodineR { GiodineR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu15 (& self) -> Nu15R { Nu15R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port E"]
# [inline (always)]
# [must_use]
pub fn giodine (& mut self) -> GiodineW < GiodineSpec > { GiodineW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu15 (& mut self) -> Nu15W < GiodineSpec > { Nu15W :: new (self , 8) } } # [doc = "GIO data input for pins in port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giodine::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodine::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodineSpec ; impl crate :: RegisterSpec for GiodineSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodine::R`](R) reader structure"]
impl crate :: Readable for GiodineSpec { } # [doc = "`write(|w| ..)` method takes [`giodine::W`](W) writer structure"]
impl crate :: Writable for GiodineSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODINE to value 0"]
impl crate :: Resettable for GiodineSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTE (rw) register accessor: GIO data output for pins in port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoute::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoute::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodoute`]
module"]
# [doc (alias = "GIODOUTE")]
pub type Giodoute = crate :: Reg < giodoute :: GiodouteSpec > ; # [doc = "GIO data output for pins in port E"]
pub mod giodoute { # [doc = "Register `GIODOUTE` reader"]
pub type R = crate :: R < GiodouteSpec > ; # [doc = "Register `GIODOUTE` writer"]
pub type W = crate :: W < GiodouteSpec > ; # [doc = "Field `GIODOUTE` reader - 7:0\\]
GIO data output for pins in port E"]
pub type GiodouteR = crate :: FieldReader ; # [doc = "Field `GIODOUTE` writer - 7:0\\]
GIO data output for pins in port E"]
pub type GiodouteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU21` reader - 31:8\\]
Reserved"]
pub type Nu21R = crate :: FieldReader < u32 > ; # [doc = "Field `NU21` writer - 31:8\\]
Reserved"]
pub type Nu21W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port E"]
# [inline (always)]
pub fn giodoute (& self) -> GiodouteR { GiodouteR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu21 (& self) -> Nu21R { Nu21R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port E"]
# [inline (always)]
# [must_use]
pub fn giodoute (& mut self) -> GiodouteW < GiodouteSpec > { GiodouteW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu21 (& mut self) -> Nu21W < GiodouteSpec > { Nu21W :: new (self , 8) } } # [doc = "GIO data output for pins in port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoute::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoute::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodouteSpec ; impl crate :: RegisterSpec for GiodouteSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodoute::R`](R) reader structure"]
impl crate :: Readable for GiodouteSpec { } # [doc = "`write(|w| ..)` method takes [`giodoute::W`](W) writer structure"]
impl crate :: Writable for GiodouteSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTE to value 0"]
impl crate :: Resettable for GiodouteSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETE (rw) register accessor: GIO data set for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giosete::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosete::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosete`]
module"]
# [doc (alias = "GIOSETE")]
pub type Giosete = crate :: Reg < giosete :: GioseteSpec > ; # [doc = "GIO data set for port E"]
pub mod giosete { # [doc = "Register `GIOSETE` reader"]
pub type R = crate :: R < GioseteSpec > ; # [doc = "Register `GIOSETE` writer"]
pub type W = crate :: W < GioseteSpec > ; # [doc = "Field `GIODSETE` reader - 7:0\\]
GIO data set for port E"]
pub type GiodseteR = crate :: FieldReader ; # [doc = "Field `GIODSETE` writer - 7:0\\]
GIO data set for port E"]
pub type GiodseteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU27` reader - 31:8\\]
Reserved"]
pub type Nu27R = crate :: FieldReader < u32 > ; # [doc = "Field `NU27` writer - 31:8\\]
Reserved"]
pub type Nu27W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port E"]
# [inline (always)]
pub fn giodsete (& self) -> GiodseteR { GiodseteR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu27 (& self) -> Nu27R { Nu27R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port E"]
# [inline (always)]
# [must_use]
pub fn giodsete (& mut self) -> GiodseteW < GioseteSpec > { GiodseteW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu27 (& mut self) -> Nu27W < GioseteSpec > { Nu27W :: new (self , 8) } } # [doc = "GIO data set for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giosete::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosete::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioseteSpec ; impl crate :: RegisterSpec for GioseteSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosete::R`](R) reader structure"]
impl crate :: Readable for GioseteSpec { } # [doc = "`write(|w| ..)` method takes [`giosete::W`](W) writer structure"]
impl crate :: Writable for GioseteSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETE to value 0"]
impl crate :: Resettable for GioseteSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRE (rw) register accessor: GIO data clear for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclre::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclre::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclre`]
module"]
# [doc (alias = "GIOCLRE")]
pub type Gioclre = crate :: Reg < gioclre :: GioclreSpec > ; # [doc = "GIO data clear for port E"]
pub mod gioclre { # [doc = "Register `GIOCLRE` reader"]
pub type R = crate :: R < GioclreSpec > ; # [doc = "Register `GIOCLRE` writer"]
pub type W = crate :: W < GioclreSpec > ; # [doc = "Field `GIODCLRE` reader - 7:0\\]
GIO data clear for port E"]
pub type GiodclreR = crate :: FieldReader ; # [doc = "Field `GIODCLRE` writer - 7:0\\]
GIO data clear for port E"]
pub type GiodclreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU33` reader - 31:8\\]
Reserved"]
pub type Nu33R = crate :: FieldReader < u32 > ; # [doc = "Field `NU33` writer - 31:8\\]
Reserved"]
pub type Nu33W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port E"]
# [inline (always)]
pub fn giodclre (& self) -> GiodclreR { GiodclreR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu33 (& self) -> Nu33R { Nu33R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port E"]
# [inline (always)]
# [must_use]
pub fn giodclre (& mut self) -> GiodclreW < GioclreSpec > { GiodclreW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu33 (& mut self) -> Nu33W < GioclreSpec > { Nu33W :: new (self , 8) } } # [doc = "GIO data clear for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclre::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclre::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclreSpec ; impl crate :: RegisterSpec for GioclreSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclre::R`](R) reader structure"]
impl crate :: Readable for GioclreSpec { } # [doc = "`write(|w| ..)` method takes [`gioclre::W`](W) writer structure"]
impl crate :: Writable for GioclreSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRE to value 0"]
impl crate :: Resettable for GioclreSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRE (rw) register accessor: GIO open drain for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdre::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdre::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdre`]
module"]
# [doc (alias = "GIOPDRE")]
pub type Giopdre = crate :: Reg < giopdre :: GiopdreSpec > ; # [doc = "GIO open drain for port E"]
pub mod giopdre { # [doc = "Register `GIOPDRE` reader"]
pub type R = crate :: R < GiopdreSpec > ; # [doc = "Register `GIOPDRE` writer"]
pub type W = crate :: W < GiopdreSpec > ; # [doc = "Field `GIOPDRE` reader - 7:0\\]
GIO open drain for port E"]
pub type GiopdreR = crate :: FieldReader ; # [doc = "Field `GIOPDRE` writer - 7:0\\]
GIO open drain for port E"]
pub type GiopdreW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port E"]
# [inline (always)]
pub fn giopdre (& self) -> GiopdreR { GiopdreR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port E"]
# [inline (always)]
# [must_use]
pub fn giopdre (& mut self) -> GiopdreW < GiopdreSpec > { GiopdreW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiopdreSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO open drain for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdre::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdre::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdreSpec ; impl crate :: RegisterSpec for GiopdreSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdre::R`](R) reader structure"]
impl crate :: Readable for GiopdreSpec { } # [doc = "`write(|w| ..)` method takes [`giopdre::W`](W) writer structure"]
impl crate :: Writable for GiopdreSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRE to value 0"]
impl crate :: Resettable for GiopdreSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISE (rw) register accessor: GIO pul disable for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldise::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldise::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldise`]
module"]
# [doc (alias = "GIOPULDISE")]
pub type Giopuldise = crate :: Reg < giopuldise :: GiopuldiseSpec > ; # [doc = "GIO pul disable for port E"]
pub mod giopuldise { # [doc = "Register `GIOPULDISE` reader"]
pub type R = crate :: R < GiopuldiseSpec > ; # [doc = "Register `GIOPULDISE` writer"]
pub type W = crate :: W < GiopuldiseSpec > ; # [doc = "Field `GIOPULDISE` reader - 7:0\\]
GIO pull disable for port E"]
pub type GiopuldiseR = crate :: FieldReader ; # [doc = "Field `GIOPULDISE` writer - 7:0\\]
GIO pull disable for port E"]
pub type GiopuldiseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port E"]
# [inline (always)]
pub fn giopuldise (& self) -> GiopuldiseR { GiopuldiseR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port E"]
# [inline (always)]
# [must_use]
pub fn giopuldise (& mut self) -> GiopuldiseW < GiopuldiseSpec > { GiopuldiseW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiopuldiseSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO pul disable for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldise::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldise::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldiseSpec ; impl crate :: RegisterSpec for GiopuldiseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldise::R`](R) reader structure"]
impl crate :: Readable for GiopuldiseSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldise::W`](W) writer structure"]
impl crate :: Writable for GiopuldiseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISE to value 0"]
impl crate :: Resettable for GiopuldiseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLE (rw) register accessor: GIO pul select for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giopsle::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopsle::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopsle`]
module"]
# [doc (alias = "GIOPSLE")]
pub type Giopsle = crate :: Reg < giopsle :: GiopsleSpec > ; # [doc = "GIO pul select for port E"]
pub mod giopsle { # [doc = "Register `GIOPSLE` reader"]
pub type R = crate :: R < GiopsleSpec > ; # [doc = "Register `GIOPSLE` writer"]
pub type W = crate :: W < GiopsleSpec > ; # [doc = "Field `GIOPSLE` reader - 7:0\\]
GIO pull select for port E"]
pub type GiopsleR = crate :: FieldReader ; # [doc = "Field `GIOPSLE` writer - 7:0\\]
GIO pull select for port E"]
pub type GiopsleW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port E"]
# [inline (always)]
pub fn giopsle (& self) -> GiopsleR { GiopsleR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port E"]
# [inline (always)]
# [must_use]
pub fn giopsle (& mut self) -> GiopsleW < GiopsleSpec > { GiopsleW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiopsleSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO pul select for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giopsle::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopsle::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopsleSpec ; impl crate :: RegisterSpec for GiopsleSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopsle::R`](R) reader structure"]
impl crate :: Readable for GiopsleSpec { } # [doc = "`write(|w| ..)` method takes [`giopsle::W`](W) writer structure"]
impl crate :: Writable for GiopsleSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLE to value 0"]
impl crate :: Resettable for GiopsleSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRF (rw) register accessor: GIO data direction of pins in Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodirf`]
module"]
# [doc (alias = "GIODIRF")]
pub type Giodirf = crate :: Reg < giodirf :: GiodirfSpec > ; # [doc = "GIO data direction of pins in Port F"]
pub mod giodirf { # [doc = "Register `GIODIRF` reader"]
pub type R = crate :: R < GiodirfSpec > ; # [doc = "Register `GIODIRF` writer"]
pub type W = crate :: W < GiodirfSpec > ; # [doc = "Field `GIODIRF` reader - 7:0\\]
GIO data direction of pins in Port F"]
pub type GiodirfR = crate :: FieldReader ; # [doc = "Field `GIODIRF` writer - 7:0\\]
GIO data direction of pins in Port F"]
pub type GiodirfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU10` reader - 31:8\\]
Reserved"]
pub type Nu10R = crate :: FieldReader < u32 > ; # [doc = "Field `NU10` writer - 31:8\\]
Reserved"]
pub type Nu10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port F"]
# [inline (always)]
pub fn giodirf (& self) -> GiodirfR { GiodirfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu10 (& self) -> Nu10R { Nu10R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port F"]
# [inline (always)]
# [must_use]
pub fn giodirf (& mut self) -> GiodirfW < GiodirfSpec > { GiodirfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu10 (& mut self) -> Nu10W < GiodirfSpec > { Nu10W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodirfSpec ; impl crate :: RegisterSpec for GiodirfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodirf::R`](R) reader structure"]
impl crate :: Readable for GiodirfSpec { } # [doc = "`write(|w| ..)` method takes [`giodirf::W`](W) writer structure"]
impl crate :: Writable for GiodirfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRF to value 0"]
impl crate :: Resettable for GiodirfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODINF (rw) register accessor: GIO data input for pins in Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodinf`]
module"]
# [doc (alias = "GIODINF")]
pub type Giodinf = crate :: Reg < giodinf :: GiodinfSpec > ; # [doc = "GIO data input for pins in Port F"]
pub mod giodinf { # [doc = "Register `GIODINF` reader"]
pub type R = crate :: R < GiodinfSpec > ; # [doc = "Register `GIODINF` writer"]
pub type W = crate :: W < GiodinfSpec > ; # [doc = "Field `GIODINF` reader - 7:0\\]
GIO data input for pins in port F"]
pub type GiodinfR = crate :: FieldReader ; # [doc = "Field `GIODINF` writer - 7:0\\]
GIO data input for pins in port F"]
pub type GiodinfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU16` reader - 31:8\\]
Reserved"]
pub type Nu16R = crate :: FieldReader < u32 > ; # [doc = "Field `NU16` writer - 31:8\\]
Reserved"]
pub type Nu16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port F"]
# [inline (always)]
pub fn giodinf (& self) -> GiodinfR { GiodinfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu16 (& self) -> Nu16R { Nu16R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port F"]
# [inline (always)]
# [must_use]
pub fn giodinf (& mut self) -> GiodinfW < GiodinfSpec > { GiodinfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu16 (& mut self) -> Nu16W < GiodinfSpec > { Nu16W :: new (self , 8) } } # [doc = "GIO data input for pins in Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodinfSpec ; impl crate :: RegisterSpec for GiodinfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodinf::R`](R) reader structure"]
impl crate :: Readable for GiodinfSpec { } # [doc = "`write(|w| ..)` method takes [`giodinf::W`](W) writer structure"]
impl crate :: Writable for GiodinfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODINF to value 0"]
impl crate :: Resettable for GiodinfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTF (rw) register accessor: GIO data output for pins in Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodoutf`]
module"]
# [doc (alias = "GIODOUTF")]
pub type Giodoutf = crate :: Reg < giodoutf :: GiodoutfSpec > ; # [doc = "GIO data output for pins in Port F"]
pub mod giodoutf { # [doc = "Register `GIODOUTF` reader"]
pub type R = crate :: R < GiodoutfSpec > ; # [doc = "Register `GIODOUTF` writer"]
pub type W = crate :: W < GiodoutfSpec > ; # [doc = "Field `GIODOUTF` reader - 7:0\\]
GIO data output for pins in port F"]
pub type GiodoutfR = crate :: FieldReader ; # [doc = "Field `GIODOUTF` writer - 7:0\\]
GIO data output for pins in port F"]
pub type GiodoutfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU22` reader - 31:8\\]
Reserved"]
pub type Nu22R = crate :: FieldReader < u32 > ; # [doc = "Field `NU22` writer - 31:8\\]
Reserved"]
pub type Nu22W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port F"]
# [inline (always)]
pub fn giodoutf (& self) -> GiodoutfR { GiodoutfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu22 (& self) -> Nu22R { Nu22R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port F"]
# [inline (always)]
# [must_use]
pub fn giodoutf (& mut self) -> GiodoutfW < GiodoutfSpec > { GiodoutfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu22 (& mut self) -> Nu22W < GiodoutfSpec > { Nu22W :: new (self , 8) } } # [doc = "GIO data output for pins in Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodoutfSpec ; impl crate :: RegisterSpec for GiodoutfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodoutf::R`](R) reader structure"]
impl crate :: Readable for GiodoutfSpec { } # [doc = "`write(|w| ..)` method takes [`giodoutf::W`](W) writer structure"]
impl crate :: Writable for GiodoutfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTF to value 0"]
impl crate :: Resettable for GiodoutfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETF (rw) register accessor: GIO data set for Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosetf`]
module"]
# [doc (alias = "GIOSETF")]
pub type Giosetf = crate :: Reg < giosetf :: GiosetfSpec > ; # [doc = "GIO data set for Port F"]
pub mod giosetf { # [doc = "Register `GIOSETF` reader"]
pub type R = crate :: R < GiosetfSpec > ; # [doc = "Register `GIOSETF` writer"]
pub type W = crate :: W < GiosetfSpec > ; # [doc = "Field `GIODSETF` reader - 7:0\\]
GIO data set for port F"]
pub type GiodsetfR = crate :: FieldReader ; # [doc = "Field `GIODSETF` writer - 7:0\\]
GIO data set for port F"]
pub type GiodsetfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU28` reader - 31:8\\]
Reserved"]
pub type Nu28R = crate :: FieldReader < u32 > ; # [doc = "Field `NU28` writer - 31:8\\]
Reserved"]
pub type Nu28W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port F"]
# [inline (always)]
pub fn giodsetf (& self) -> GiodsetfR { GiodsetfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu28 (& self) -> Nu28R { Nu28R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port F"]
# [inline (always)]
# [must_use]
pub fn giodsetf (& mut self) -> GiodsetfW < GiosetfSpec > { GiodsetfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu28 (& mut self) -> Nu28W < GiosetfSpec > { Nu28W :: new (self , 8) } } # [doc = "GIO data set for Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosetfSpec ; impl crate :: RegisterSpec for GiosetfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosetf::R`](R) reader structure"]
impl crate :: Readable for GiosetfSpec { } # [doc = "`write(|w| ..)` method takes [`giosetf::W`](W) writer structure"]
impl crate :: Writable for GiosetfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETF to value 0"]
impl crate :: Resettable for GiosetfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRF (rw) register accessor: GIO data clear for Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclrf`]
module"]
# [doc (alias = "GIOCLRF")]
pub type Gioclrf = crate :: Reg < gioclrf :: GioclrfSpec > ; # [doc = "GIO data clear for Port F"]
pub mod gioclrf { # [doc = "Register `GIOCLRF` reader"]
pub type R = crate :: R < GioclrfSpec > ; # [doc = "Register `GIOCLRF` writer"]
pub type W = crate :: W < GioclrfSpec > ; # [doc = "Field `GIODCLRF` reader - 7:0\\]
GIO data clear for port F"]
pub type GiodclrfR = crate :: FieldReader ; # [doc = "Field `GIODCLRF` writer - 7:0\\]
GIO data clear for port F"]
pub type GiodclrfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU34` reader - 31:8\\]
Reserved"]
pub type Nu34R = crate :: FieldReader < u32 > ; # [doc = "Field `NU34` writer - 31:8\\]
Reserved"]
pub type Nu34W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port F"]
# [inline (always)]
pub fn giodclrf (& self) -> GiodclrfR { GiodclrfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu34 (& self) -> Nu34R { Nu34R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port F"]
# [inline (always)]
# [must_use]
pub fn giodclrf (& mut self) -> GiodclrfW < GioclrfSpec > { GiodclrfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu34 (& mut self) -> Nu34W < GioclrfSpec > { Nu34W :: new (self , 8) } } # [doc = "GIO data clear for Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclrfSpec ; impl crate :: RegisterSpec for GioclrfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclrf::R`](R) reader structure"]
impl crate :: Readable for GioclrfSpec { } # [doc = "`write(|w| ..)` method takes [`gioclrf::W`](W) writer structure"]
impl crate :: Writable for GioclrfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRF to value 0"]
impl crate :: Resettable for GioclrfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRF (rw) register accessor: GIO open drain for Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdrf`]
module"]
# [doc (alias = "GIOPDRF")]
pub type Giopdrf = crate :: Reg < giopdrf :: GiopdrfSpec > ; # [doc = "GIO open drain for Port F"]
pub mod giopdrf { # [doc = "Register `GIOPDRF` reader"]
pub type R = crate :: R < GiopdrfSpec > ; # [doc = "Register `GIOPDRF` writer"]
pub type W = crate :: W < GiopdrfSpec > ; # [doc = "Field `GIOPDRF` reader - 7:0\\]
GIO open drain for port F"]
pub type GiopdrfR = crate :: FieldReader ; # [doc = "Field `GIOPDRF` writer - 7:0\\]
GIO open drain for port F"]
pub type GiopdrfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port F"]
# [inline (always)]
pub fn giopdrf (& self) -> GiopdrfR { GiopdrfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port F"]
# [inline (always)]
# [must_use]
pub fn giopdrf (& mut self) -> GiopdrfW < GiopdrfSpec > { GiopdrfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiopdrfSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO open drain for Port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdrfSpec ; impl crate :: RegisterSpec for GiopdrfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdrf::R`](R) reader structure"]
impl crate :: Readable for GiopdrfSpec { } # [doc = "`write(|w| ..)` method takes [`giopdrf::W`](W) writer structure"]
impl crate :: Writable for GiopdrfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRF to value 0"]
impl crate :: Resettable for GiopdrfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISF (rw) register accessor: GIO pul disable for port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldisf`]
module"]
# [doc (alias = "GIOPULDISF")]
pub type Giopuldisf = crate :: Reg < giopuldisf :: GiopuldisfSpec > ; # [doc = "GIO pul disable for port F"]
pub mod giopuldisf { # [doc = "Register `GIOPULDISF` reader"]
pub type R = crate :: R < GiopuldisfSpec > ; # [doc = "Register `GIOPULDISF` writer"]
pub type W = crate :: W < GiopuldisfSpec > ; # [doc = "Field `GIOPULDISF` reader - 7:0\\]
GIO pull disable for port F"]
pub type GiopuldisfR = crate :: FieldReader ; # [doc = "Field `GIOPULDISF` writer - 7:0\\]
GIO pull disable for port F"]
pub type GiopuldisfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port F"]
# [inline (always)]
pub fn giopuldisf (& self) -> GiopuldisfR { GiopuldisfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port F"]
# [inline (always)]
# [must_use]
pub fn giopuldisf (& mut self) -> GiopuldisfW < GiopuldisfSpec > { GiopuldisfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiopuldisfSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO pul disable for port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldisfSpec ; impl crate :: RegisterSpec for GiopuldisfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldisf::R`](R) reader structure"]
impl crate :: Readable for GiopuldisfSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldisf::W`](W) writer structure"]
impl crate :: Writable for GiopuldisfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISF to value 0"]
impl crate :: Resettable for GiopuldisfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLF (rw) register accessor: GIO pul select for port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopslf`]
module"]
# [doc (alias = "GIOPSLF")]
pub type Giopslf = crate :: Reg < giopslf :: GiopslfSpec > ; # [doc = "GIO pul select for port F"]
pub mod giopslf { # [doc = "Register `GIOPSLF` reader"]
pub type R = crate :: R < GiopslfSpec > ; # [doc = "Register `GIOPSLF` writer"]
pub type W = crate :: W < GiopslfSpec > ; # [doc = "Field `GIOPSLF` reader - 7:0\\]
GIO pull select for port F"]
pub type GiopslfR = crate :: FieldReader ; # [doc = "Field `GIOPSLF` writer - 7:0\\]
GIO pull select for port F"]
pub type GiopslfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port F"]
# [inline (always)]
pub fn giopslf (& self) -> GiopslfR { GiopslfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port F"]
# [inline (always)]
# [must_use]
pub fn giopslf (& mut self) -> GiopslfW < GiopslfSpec > { GiopslfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiopslfSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO pul select for port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopslfSpec ; impl crate :: RegisterSpec for GiopslfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopslf::R`](R) reader structure"]
impl crate :: Readable for GiopslfSpec { } # [doc = "`write(|w| ..)` method takes [`giopslf::W`](W) writer structure"]
impl crate :: Writable for GiopslfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLF to value 0"]
impl crate :: Resettable for GiopslfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRG (rw) register accessor: GIO data direction of pins in Port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodirg`]
module"]
# [doc (alias = "GIODIRG")]
pub type Giodirg = crate :: Reg < giodirg :: GiodirgSpec > ; # [doc = "GIO data direction of pins in Port G"]
pub mod giodirg { # [doc = "Register `GIODIRG` reader"]
pub type R = crate :: R < GiodirgSpec > ; # [doc = "Register `GIODIRG` writer"]
pub type W = crate :: W < GiodirgSpec > ; # [doc = "Field `GIODIRG` reader - 7:0\\]
GIO data direction of pins in Port G"]
pub type GiodirgR = crate :: FieldReader ; # [doc = "Field `GIODIRG` writer - 7:0\\]
GIO data direction of pins in Port G"]
pub type GiodirgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU9` reader - 31:8\\]
Reserved"]
pub type Nu9R = crate :: FieldReader < u32 > ; # [doc = "Field `NU9` writer - 31:8\\]
Reserved"]
pub type Nu9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port G"]
# [inline (always)]
pub fn giodirg (& self) -> GiodirgR { GiodirgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu9 (& self) -> Nu9R { Nu9R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port G"]
# [inline (always)]
# [must_use]
pub fn giodirg (& mut self) -> GiodirgW < GiodirgSpec > { GiodirgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu9 (& mut self) -> Nu9W < GiodirgSpec > { Nu9W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodirgSpec ; impl crate :: RegisterSpec for GiodirgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodirg::R`](R) reader structure"]
impl crate :: Readable for GiodirgSpec { } # [doc = "`write(|w| ..)` method takes [`giodirg::W`](W) writer structure"]
impl crate :: Writable for GiodirgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRG to value 0"]
impl crate :: Resettable for GiodirgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODING (rw) register accessor: GIO data input for pins in port G\n\nYou can [`read`](crate::Reg::read) this register and get [`gioding::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioding::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioding`]
module"]
# [doc (alias = "GIODING")]
pub type Gioding = crate :: Reg < gioding :: GiodingSpec > ; # [doc = "GIO data input for pins in port G"]
pub mod gioding { # [doc = "Register `GIODING` reader"]
pub type R = crate :: R < GiodingSpec > ; # [doc = "Register `GIODING` writer"]
pub type W = crate :: W < GiodingSpec > ; # [doc = "Field `GIODING` reader - 7:0\\]
GIO data input for pins in port G"]
pub type GiodingR = crate :: FieldReader ; # [doc = "Field `GIODING` writer - 7:0\\]
GIO data input for pins in port G"]
pub type GiodingW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU15` reader - 31:8\\]
Reserved"]
pub type Nu15R = crate :: FieldReader < u32 > ; # [doc = "Field `NU15` writer - 31:8\\]
Reserved"]
pub type Nu15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port G"]
# [inline (always)]
pub fn gioding (& self) -> GiodingR { GiodingR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu15 (& self) -> Nu15R { Nu15R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port G"]
# [inline (always)]
# [must_use]
pub fn gioding (& mut self) -> GiodingW < GiodingSpec > { GiodingW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu15 (& mut self) -> Nu15W < GiodingSpec > { Nu15W :: new (self , 8) } } # [doc = "GIO data input for pins in port G\n\nYou can [`read`](crate::Reg::read) this register and get [`gioding::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioding::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodingSpec ; impl crate :: RegisterSpec for GiodingSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioding::R`](R) reader structure"]
impl crate :: Readable for GiodingSpec { } # [doc = "`write(|w| ..)` method takes [`gioding::W`](W) writer structure"]
impl crate :: Writable for GiodingSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODING to value 0"]
impl crate :: Resettable for GiodingSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTG (rw) register accessor: GIO data output for pins in port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodoutg`]
module"]
# [doc (alias = "GIODOUTG")]
pub type Giodoutg = crate :: Reg < giodoutg :: GiodoutgSpec > ; # [doc = "GIO data output for pins in port G"]
pub mod giodoutg { # [doc = "Register `GIODOUTG` reader"]
pub type R = crate :: R < GiodoutgSpec > ; # [doc = "Register `GIODOUTG` writer"]
pub type W = crate :: W < GiodoutgSpec > ; # [doc = "Field `GIODOUTG` reader - 7:0\\]
GIO data output for pins in port G"]
pub type GiodoutgR = crate :: FieldReader ; # [doc = "Field `GIODOUTG` writer - 7:0\\]
GIO data output for pins in port G"]
pub type GiodoutgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU21` reader - 31:8\\]
Reserved"]
pub type Nu21R = crate :: FieldReader < u32 > ; # [doc = "Field `NU21` writer - 31:8\\]
Reserved"]
pub type Nu21W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port G"]
# [inline (always)]
pub fn giodoutg (& self) -> GiodoutgR { GiodoutgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu21 (& self) -> Nu21R { Nu21R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port G"]
# [inline (always)]
# [must_use]
pub fn giodoutg (& mut self) -> GiodoutgW < GiodoutgSpec > { GiodoutgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu21 (& mut self) -> Nu21W < GiodoutgSpec > { Nu21W :: new (self , 8) } } # [doc = "GIO data output for pins in port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giodoutg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodoutg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodoutgSpec ; impl crate :: RegisterSpec for GiodoutgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodoutg::R`](R) reader structure"]
impl crate :: Readable for GiodoutgSpec { } # [doc = "`write(|w| ..)` method takes [`giodoutg::W`](W) writer structure"]
impl crate :: Writable for GiodoutgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTG to value 0"]
impl crate :: Resettable for GiodoutgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETG (rw) register accessor: GIO data set for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosetg`]
module"]
# [doc (alias = "GIOSETG")]
pub type Giosetg = crate :: Reg < giosetg :: GiosetgSpec > ; # [doc = "GIO data set for port G"]
pub mod giosetg { # [doc = "Register `GIOSETG` reader"]
pub type R = crate :: R < GiosetgSpec > ; # [doc = "Register `GIOSETG` writer"]
pub type W = crate :: W < GiosetgSpec > ; # [doc = "Field `GIODSETG` reader - 7:0\\]
GIO data set for port G"]
pub type GiodsetgR = crate :: FieldReader ; # [doc = "Field `GIODSETG` writer - 7:0\\]
GIO data set for port G"]
pub type GiodsetgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU27` reader - 31:8\\]
Reserved"]
pub type Nu27R = crate :: FieldReader < u32 > ; # [doc = "Field `NU27` writer - 31:8\\]
Reserved"]
pub type Nu27W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port G"]
# [inline (always)]
pub fn giodsetg (& self) -> GiodsetgR { GiodsetgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu27 (& self) -> Nu27R { Nu27R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port G"]
# [inline (always)]
# [must_use]
pub fn giodsetg (& mut self) -> GiodsetgW < GiosetgSpec > { GiodsetgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu27 (& mut self) -> Nu27W < GiosetgSpec > { Nu27W :: new (self , 8) } } # [doc = "GIO data set for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giosetg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosetg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosetgSpec ; impl crate :: RegisterSpec for GiosetgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosetg::R`](R) reader structure"]
impl crate :: Readable for GiosetgSpec { } # [doc = "`write(|w| ..)` method takes [`giosetg::W`](W) writer structure"]
impl crate :: Writable for GiosetgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETG to value 0"]
impl crate :: Resettable for GiosetgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRG (rw) register accessor: GIO data clear for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclrg`]
module"]
# [doc (alias = "GIOCLRG")]
pub type Gioclrg = crate :: Reg < gioclrg :: GioclrgSpec > ; # [doc = "GIO data clear for port G"]
pub mod gioclrg { # [doc = "Register `GIOCLRG` reader"]
pub type R = crate :: R < GioclrgSpec > ; # [doc = "Register `GIOCLRG` writer"]
pub type W = crate :: W < GioclrgSpec > ; # [doc = "Field `GIODCLRG` reader - 7:0\\]
GIO data clear for port G"]
pub type GiodclrgR = crate :: FieldReader ; # [doc = "Field `GIODCLRG` writer - 7:0\\]
GIO data clear for port G"]
pub type GiodclrgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU33` reader - 31:8\\]
Reserved"]
pub type Nu33R = crate :: FieldReader < u32 > ; # [doc = "Field `NU33` writer - 31:8\\]
Reserved"]
pub type Nu33W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port G"]
# [inline (always)]
pub fn giodclrg (& self) -> GiodclrgR { GiodclrgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu33 (& self) -> Nu33R { Nu33R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port G"]
# [inline (always)]
# [must_use]
pub fn giodclrg (& mut self) -> GiodclrgW < GioclrgSpec > { GiodclrgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu33 (& mut self) -> Nu33W < GioclrgSpec > { Nu33W :: new (self , 8) } } # [doc = "GIO data clear for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclrgSpec ; impl crate :: RegisterSpec for GioclrgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclrg::R`](R) reader structure"]
impl crate :: Readable for GioclrgSpec { } # [doc = "`write(|w| ..)` method takes [`gioclrg::W`](W) writer structure"]
impl crate :: Writable for GioclrgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRG to value 0"]
impl crate :: Resettable for GioclrgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRG (rw) register accessor: GIO open drain for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdrg`]
module"]
# [doc (alias = "GIOPDRG")]
pub type Giopdrg = crate :: Reg < giopdrg :: GiopdrgSpec > ; # [doc = "GIO open drain for port G"]
pub mod giopdrg { # [doc = "Register `GIOPDRG` reader"]
pub type R = crate :: R < GiopdrgSpec > ; # [doc = "Register `GIOPDRG` writer"]
pub type W = crate :: W < GiopdrgSpec > ; # [doc = "Field `GIOPDRG` reader - 7:0\\]
GIO open drain for port G"]
pub type GiopdrgR = crate :: FieldReader ; # [doc = "Field `GIOPDRG` writer - 7:0\\]
GIO open drain for port G"]
pub type GiopdrgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port G"]
# [inline (always)]
pub fn giopdrg (& self) -> GiopdrgR { GiopdrgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port G"]
# [inline (always)]
# [must_use]
pub fn giopdrg (& mut self) -> GiopdrgW < GiopdrgSpec > { GiopdrgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiopdrgSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO open drain for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdrgSpec ; impl crate :: RegisterSpec for GiopdrgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdrg::R`](R) reader structure"]
impl crate :: Readable for GiopdrgSpec { } # [doc = "`write(|w| ..)` method takes [`giopdrg::W`](W) writer structure"]
impl crate :: Writable for GiopdrgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRG to value 0"]
impl crate :: Resettable for GiopdrgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISG (rw) register accessor: GIO pul disable for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldisg`]
module"]
# [doc (alias = "GIOPULDISG")]
pub type Giopuldisg = crate :: Reg < giopuldisg :: GiopuldisgSpec > ; # [doc = "GIO pul disable for port G"]
pub mod giopuldisg { # [doc = "Register `GIOPULDISG` reader"]
pub type R = crate :: R < GiopuldisgSpec > ; # [doc = "Register `GIOPULDISG` writer"]
pub type W = crate :: W < GiopuldisgSpec > ; # [doc = "Field `GIOPULDISG` reader - 7:0\\]
GIO pull disable for port G"]
pub type GiopuldisgR = crate :: FieldReader ; # [doc = "Field `GIOPULDISG` writer - 7:0\\]
GIO pull disable for port G"]
pub type GiopuldisgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port G"]
# [inline (always)]
pub fn giopuldisg (& self) -> GiopuldisgR { GiopuldisgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port G"]
# [inline (always)]
# [must_use]
pub fn giopuldisg (& mut self) -> GiopuldisgW < GiopuldisgSpec > { GiopuldisgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiopuldisgSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO pul disable for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldisg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldisg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldisgSpec ; impl crate :: RegisterSpec for GiopuldisgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldisg::R`](R) reader structure"]
impl crate :: Readable for GiopuldisgSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldisg::W`](W) writer structure"]
impl crate :: Writable for GiopuldisgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISG to value 0"]
impl crate :: Resettable for GiopuldisgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLG (rw) register accessor: GIO pul select for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopslg`]
module"]
# [doc (alias = "GIOPSLG")]
pub type Giopslg = crate :: Reg < giopslg :: GiopslgSpec > ; # [doc = "GIO pul select for port G"]
pub mod giopslg { # [doc = "Register `GIOPSLG` reader"]
pub type R = crate :: R < GiopslgSpec > ; # [doc = "Register `GIOPSLG` writer"]
pub type W = crate :: W < GiopslgSpec > ; # [doc = "Field `GIOPSLG` reader - 7:0\\]
GIO pull select for port G"]
pub type GiopslgR = crate :: FieldReader ; # [doc = "Field `GIOPSLG` writer - 7:0\\]
GIO pull select for port G"]
pub type GiopslgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port G"]
# [inline (always)]
pub fn giopslg (& self) -> GiopslgR { GiopslgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port G"]
# [inline (always)]
# [must_use]
pub fn giopslg (& mut self) -> GiopslgW < GiopslgSpec > { GiopslgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiopslgSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO pul select for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopslgSpec ; impl crate :: RegisterSpec for GiopslgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopslg::R`](R) reader structure"]
impl crate :: Readable for GiopslgSpec { } # [doc = "`write(|w| ..)` method takes [`giopslg::W`](W) writer structure"]
impl crate :: Writable for GiopslgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLG to value 0"]
impl crate :: Resettable for GiopslgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODIRH (rw) register accessor: GIO data direction of pins in Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodirh`]
module"]
# [doc (alias = "GIODIRH")]
pub type Giodirh = crate :: Reg < giodirh :: GiodirhSpec > ; # [doc = "GIO data direction of pins in Port H"]
pub mod giodirh { # [doc = "Register `GIODIRH` reader"]
pub type R = crate :: R < GiodirhSpec > ; # [doc = "Register `GIODIRH` writer"]
pub type W = crate :: W < GiodirhSpec > ; # [doc = "Field `GIODIRH` reader - 7:0\\]
GIO data direction of pins in Port H"]
pub type GiodirhR = crate :: FieldReader ; # [doc = "Field `GIODIRH` writer - 7:0\\]
GIO data direction of pins in Port H"]
pub type GiodirhW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU10` reader - 31:8\\]
Reserved"]
pub type Nu10R = crate :: FieldReader < u32 > ; # [doc = "Field `NU10` writer - 31:8\\]
Reserved"]
pub type Nu10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port H"]
# [inline (always)]
pub fn giodirh (& self) -> GiodirhR { GiodirhR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu10 (& self) -> Nu10R { Nu10R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data direction of pins in Port H"]
# [inline (always)]
# [must_use]
pub fn giodirh (& mut self) -> GiodirhW < GiodirhSpec > { GiodirhW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu10 (& mut self) -> Nu10W < GiodirhSpec > { Nu10W :: new (self , 8) } } # [doc = "GIO data direction of pins in Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giodirh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodirh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodirhSpec ; impl crate :: RegisterSpec for GiodirhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodirh::R`](R) reader structure"]
impl crate :: Readable for GiodirhSpec { } # [doc = "`write(|w| ..)` method takes [`giodirh::W`](W) writer structure"]
impl crate :: Writable for GiodirhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODIRH to value 0"]
impl crate :: Resettable for GiodirhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODINH (rw) register accessor: GIO data input for pins in Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodinh`]
module"]
# [doc (alias = "GIODINH")]
pub type Giodinh = crate :: Reg < giodinh :: GiodinhSpec > ; # [doc = "GIO data input for pins in Port H"]
pub mod giodinh { # [doc = "Register `GIODINH` reader"]
pub type R = crate :: R < GiodinhSpec > ; # [doc = "Register `GIODINH` writer"]
pub type W = crate :: W < GiodinhSpec > ; # [doc = "Field `GIODINH` reader - 7:0\\]
GIO data input for pins in port H"]
pub type GiodinhR = crate :: FieldReader ; # [doc = "Field `GIODINH` writer - 7:0\\]
GIO data input for pins in port H"]
pub type GiodinhW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU16` reader - 31:8\\]
Reserved"]
pub type Nu16R = crate :: FieldReader < u32 > ; # [doc = "Field `NU16` writer - 31:8\\]
Reserved"]
pub type Nu16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port H"]
# [inline (always)]
pub fn giodinh (& self) -> GiodinhR { GiodinhR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu16 (& self) -> Nu16R { Nu16R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data input for pins in port H"]
# [inline (always)]
# [must_use]
pub fn giodinh (& mut self) -> GiodinhW < GiodinhSpec > { GiodinhW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu16 (& mut self) -> Nu16W < GiodinhSpec > { Nu16W :: new (self , 8) } } # [doc = "GIO data input for pins in Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giodinh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodinh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodinhSpec ; impl crate :: RegisterSpec for GiodinhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodinh::R`](R) reader structure"]
impl crate :: Readable for GiodinhSpec { } # [doc = "`write(|w| ..)` method takes [`giodinh::W`](W) writer structure"]
impl crate :: Writable for GiodinhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODINH to value 0"]
impl crate :: Resettable for GiodinhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIODOUTH (rw) register accessor: GIO data output for pins in Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giodouth::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodouth::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giodouth`]
module"]
# [doc (alias = "GIODOUTH")]
pub type Giodouth = crate :: Reg < giodouth :: GiodouthSpec > ; # [doc = "GIO data output for pins in Port H"]
pub mod giodouth { # [doc = "Register `GIODOUTH` reader"]
pub type R = crate :: R < GiodouthSpec > ; # [doc = "Register `GIODOUTH` writer"]
pub type W = crate :: W < GiodouthSpec > ; # [doc = "Field `GIODOUTH` reader - 7:0\\]
GIO data output for pins in port H"]
pub type GiodouthR = crate :: FieldReader ; # [doc = "Field `GIODOUTH` writer - 7:0\\]
GIO data output for pins in port H"]
pub type GiodouthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU22` reader - 31:8\\]
Reserved"]
pub type Nu22R = crate :: FieldReader < u32 > ; # [doc = "Field `NU22` writer - 31:8\\]
Reserved"]
pub type Nu22W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port H"]
# [inline (always)]
pub fn giodouth (& self) -> GiodouthR { GiodouthR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu22 (& self) -> Nu22R { Nu22R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data output for pins in port H"]
# [inline (always)]
# [must_use]
pub fn giodouth (& mut self) -> GiodouthW < GiodouthSpec > { GiodouthW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu22 (& mut self) -> Nu22W < GiodouthSpec > { Nu22W :: new (self , 8) } } # [doc = "GIO data output for pins in Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giodouth::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giodouth::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiodouthSpec ; impl crate :: RegisterSpec for GiodouthSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giodouth::R`](R) reader structure"]
impl crate :: Readable for GiodouthSpec { } # [doc = "`write(|w| ..)` method takes [`giodouth::W`](W) writer structure"]
impl crate :: Writable for GiodouthSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIODOUTH to value 0"]
impl crate :: Resettable for GiodouthSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSETH (rw) register accessor: GIO data set for Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`gioseth::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioseth::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioseth`]
module"]
# [doc (alias = "GIOSETH")]
pub type Gioseth = crate :: Reg < gioseth :: GiosethSpec > ; # [doc = "GIO data set for Port H"]
pub mod gioseth { # [doc = "Register `GIOSETH` reader"]
pub type R = crate :: R < GiosethSpec > ; # [doc = "Register `GIOSETH` writer"]
pub type W = crate :: W < GiosethSpec > ; # [doc = "Field `GIODSETH` reader - 7:0\\]
GIO data set for port H"]
pub type GiodsethR = crate :: FieldReader ; # [doc = "Field `GIODSETH` writer - 7:0\\]
GIO data set for port H"]
pub type GiodsethW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU28` reader - 31:8\\]
Reserved"]
pub type Nu28R = crate :: FieldReader < u32 > ; # [doc = "Field `NU28` writer - 31:8\\]
Reserved"]
pub type Nu28W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port H"]
# [inline (always)]
pub fn giodseth (& self) -> GiodsethR { GiodsethR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu28 (& self) -> Nu28R { Nu28R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data set for port H"]
# [inline (always)]
# [must_use]
pub fn giodseth (& mut self) -> GiodsethW < GiosethSpec > { GiodsethW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu28 (& mut self) -> Nu28W < GiosethSpec > { Nu28W :: new (self , 8) } } # [doc = "GIO data set for Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`gioseth::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioseth::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosethSpec ; impl crate :: RegisterSpec for GiosethSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioseth::R`](R) reader structure"]
impl crate :: Readable for GiosethSpec { } # [doc = "`write(|w| ..)` method takes [`gioseth::W`](W) writer structure"]
impl crate :: Writable for GiosethSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSETH to value 0"]
impl crate :: Resettable for GiosethSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOCLRH (rw) register accessor: GIO data clear for Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gioclrh`]
module"]
# [doc (alias = "GIOCLRH")]
pub type Gioclrh = crate :: Reg < gioclrh :: GioclrhSpec > ; # [doc = "GIO data clear for Port H"]
pub mod gioclrh { # [doc = "Register `GIOCLRH` reader"]
pub type R = crate :: R < GioclrhSpec > ; # [doc = "Register `GIOCLRH` writer"]
pub type W = crate :: W < GioclrhSpec > ; # [doc = "Field `GIODCLRH` reader - 7:0\\]
GIO data clear for port H"]
pub type GiodclrhR = crate :: FieldReader ; # [doc = "Field `GIODCLRH` writer - 7:0\\]
GIO data clear for port H"]
pub type GiodclrhW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU34` reader - 31:8\\]
Reserved"]
pub type Nu34R = crate :: FieldReader < u32 > ; # [doc = "Field `NU34` writer - 31:8\\]
Reserved"]
pub type Nu34W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port H"]
# [inline (always)]
pub fn giodclrh (& self) -> GiodclrhR { GiodclrhR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu34 (& self) -> Nu34R { Nu34R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO data clear for port H"]
# [inline (always)]
# [must_use]
pub fn giodclrh (& mut self) -> GiodclrhW < GioclrhSpec > { GiodclrhW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu34 (& mut self) -> Nu34W < GioclrhSpec > { Nu34W :: new (self , 8) } } # [doc = "GIO data clear for Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`gioclrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gioclrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GioclrhSpec ; impl crate :: RegisterSpec for GioclrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`gioclrh::R`](R) reader structure"]
impl crate :: Readable for GioclrhSpec { } # [doc = "`write(|w| ..)` method takes [`gioclrh::W`](W) writer structure"]
impl crate :: Writable for GioclrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOCLRH to value 0"]
impl crate :: Resettable for GioclrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPDRH (rw) register accessor: GIO open drain for Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopdrh`]
module"]
# [doc (alias = "GIOPDRH")]
pub type Giopdrh = crate :: Reg < giopdrh :: GiopdrhSpec > ; # [doc = "GIO open drain for Port H"]
pub mod giopdrh { # [doc = "Register `GIOPDRH` reader"]
pub type R = crate :: R < GiopdrhSpec > ; # [doc = "Register `GIOPDRH` writer"]
pub type W = crate :: W < GiopdrhSpec > ; # [doc = "Field `GIOPDRH` reader - 7:0\\]
GIO open drain for port H"]
pub type GiopdrhR = crate :: FieldReader ; # [doc = "Field `GIOPDRH` writer - 7:0\\]
GIO open drain for port H"]
pub type GiopdrhW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port H"]
# [inline (always)]
pub fn giopdrh (& self) -> GiopdrhR { GiopdrhR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO open drain for port H"]
# [inline (always)]
# [must_use]
pub fn giopdrh (& mut self) -> GiopdrhW < GiopdrhSpec > { GiopdrhW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiopdrhSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO open drain for Port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giopdrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopdrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopdrhSpec ; impl crate :: RegisterSpec for GiopdrhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopdrh::R`](R) reader structure"]
impl crate :: Readable for GiopdrhSpec { } # [doc = "`write(|w| ..)` method takes [`giopdrh::W`](W) writer structure"]
impl crate :: Writable for GiopdrhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPDRH to value 0"]
impl crate :: Resettable for GiopdrhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPULDISH (rw) register accessor: GIO pul disable for port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldish::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldish::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopuldish`]
module"]
# [doc (alias = "GIOPULDISH")]
pub type Giopuldish = crate :: Reg < giopuldish :: GiopuldishSpec > ; # [doc = "GIO pul disable for port H"]
pub mod giopuldish { # [doc = "Register `GIOPULDISH` reader"]
pub type R = crate :: R < GiopuldishSpec > ; # [doc = "Register `GIOPULDISH` writer"]
pub type W = crate :: W < GiopuldishSpec > ; # [doc = "Field `GIOPULDISH` reader - 7:0\\]
GIO pull disable for port H"]
pub type GiopuldishR = crate :: FieldReader ; # [doc = "Field `GIOPULDISH` writer - 7:0\\]
GIO pull disable for port H"]
pub type GiopuldishW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port H"]
# [inline (always)]
pub fn giopuldish (& self) -> GiopuldishR { GiopuldishR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull disable for port H"]
# [inline (always)]
# [must_use]
pub fn giopuldish (& mut self) -> GiopuldishW < GiopuldishSpec > { GiopuldishW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiopuldishSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO pul disable for port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giopuldish::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopuldish::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopuldishSpec ; impl crate :: RegisterSpec for GiopuldishSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopuldish::R`](R) reader structure"]
impl crate :: Readable for GiopuldishSpec { } # [doc = "`write(|w| ..)` method takes [`giopuldish::W`](W) writer structure"]
impl crate :: Writable for GiopuldishSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPULDISH to value 0"]
impl crate :: Resettable for GiopuldishSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOPSLH (rw) register accessor: GIO pul select for port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giopslh`]
module"]
# [doc (alias = "GIOPSLH")]
pub type Giopslh = crate :: Reg < giopslh :: GiopslhSpec > ; # [doc = "GIO pul select for port H"]
pub mod giopslh { # [doc = "Register `GIOPSLH` reader"]
pub type R = crate :: R < GiopslhSpec > ; # [doc = "Register `GIOPSLH` writer"]
pub type W = crate :: W < GiopslhSpec > ; # [doc = "Field `GIOPSLH` reader - 7:0\\]
GIO pull select for port H"]
pub type GiopslhR = crate :: FieldReader ; # [doc = "Field `GIOPSLH` writer - 7:0\\]
GIO pull select for port H"]
pub type GiopslhW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port H"]
# [inline (always)]
pub fn giopslh (& self) -> GiopslhR { GiopslhR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO pull select for port H"]
# [inline (always)]
# [must_use]
pub fn giopslh (& mut self) -> GiopslhW < GiopslhSpec > { GiopslhW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiopslhSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO pul select for port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giopslh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giopslh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiopslhSpec ; impl crate :: RegisterSpec for GiopslhSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giopslh::R`](R) reader structure"]
impl crate :: Readable for GiopslhSpec { } # [doc = "`write(|w| ..)` method takes [`giopslh::W`](W) writer structure"]
impl crate :: Writable for GiopslhSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOPSLH to value 0"]
impl crate :: Resettable for GiopslhSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCA (rw) register accessor: GIO slew rate select for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrca::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrca::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrca`]
module"]
# [doc (alias = "GIOSRCA")]
pub type Giosrca = crate :: Reg < giosrca :: GiosrcaSpec > ; # [doc = "GIO slew rate select for port A"]
pub mod giosrca { # [doc = "Register `GIOSRCA` reader"]
pub type R = crate :: R < GiosrcaSpec > ; # [doc = "Register `GIOSRCA` writer"]
pub type W = crate :: W < GiosrcaSpec > ; # [doc = "Field `GIOSRCA` reader - 7:0\\]
GIO slew rate control for port A"]
pub type GiosrcaR = crate :: FieldReader ; # [doc = "Field `GIOSRCA` writer - 7:0\\]
GIO slew rate control for port A"]
pub type GiosrcaW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU35` reader - 31:8\\]
Reserved"]
pub type Nu35R = crate :: FieldReader < u32 > ; # [doc = "Field `NU35` writer - 31:8\\]
Reserved"]
pub type Nu35W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port A"]
# [inline (always)]
pub fn giosrca (& self) -> GiosrcaR { GiosrcaR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu35 (& self) -> Nu35R { Nu35R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port A"]
# [inline (always)]
# [must_use]
pub fn giosrca (& mut self) -> GiosrcaW < GiosrcaSpec > { GiosrcaW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu35 (& mut self) -> Nu35W < GiosrcaSpec > { Nu35W :: new (self , 8) } } # [doc = "GIO slew rate select for port A\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrca::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrca::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrcaSpec ; impl crate :: RegisterSpec for GiosrcaSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrca::R`](R) reader structure"]
impl crate :: Readable for GiosrcaSpec { } # [doc = "`write(|w| ..)` method takes [`giosrca::W`](W) writer structure"]
impl crate :: Writable for GiosrcaSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCA to value 0"]
impl crate :: Resettable for GiosrcaSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCB (rw) register accessor: GIO slew rate select for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrcb`]
module"]
# [doc (alias = "GIOSRCB")]
pub type Giosrcb = crate :: Reg < giosrcb :: GiosrcbSpec > ; # [doc = "GIO slew rate select for port B"]
pub mod giosrcb { # [doc = "Register `GIOSRCB` reader"]
pub type R = crate :: R < GiosrcbSpec > ; # [doc = "Register `GIOSRCB` writer"]
pub type W = crate :: W < GiosrcbSpec > ; # [doc = "Field `GIOSRCB` reader - 7:0\\]
GIO slew rate control for port B"]
pub type GiosrcbR = crate :: FieldReader ; # [doc = "Field `GIOSRCB` writer - 7:0\\]
GIO slew rate control for port B"]
pub type GiosrcbW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU36` reader - 31:8\\]
Reserved"]
pub type Nu36R = crate :: FieldReader < u32 > ; # [doc = "Field `NU36` writer - 31:8\\]
Reserved"]
pub type Nu36W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port B"]
# [inline (always)]
pub fn giosrcb (& self) -> GiosrcbR { GiosrcbR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu36 (& self) -> Nu36R { Nu36R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port B"]
# [inline (always)]
# [must_use]
pub fn giosrcb (& mut self) -> GiosrcbW < GiosrcbSpec > { GiosrcbW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu36 (& mut self) -> Nu36W < GiosrcbSpec > { Nu36W :: new (self , 8) } } # [doc = "GIO slew rate select for port B\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrcbSpec ; impl crate :: RegisterSpec for GiosrcbSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrcb::R`](R) reader structure"]
impl crate :: Readable for GiosrcbSpec { } # [doc = "`write(|w| ..)` method takes [`giosrcb::W`](W) writer structure"]
impl crate :: Writable for GiosrcbSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCB to value 0"]
impl crate :: Resettable for GiosrcbSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCC (rw) register accessor: GIO slew rate select for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrcc`]
module"]
# [doc (alias = "GIOSRCC")]
pub type Giosrcc = crate :: Reg < giosrcc :: GiosrccSpec > ; # [doc = "GIO slew rate select for port C"]
pub mod giosrcc { # [doc = "Register `GIOSRCC` reader"]
pub type R = crate :: R < GiosrccSpec > ; # [doc = "Register `GIOSRCC` writer"]
pub type W = crate :: W < GiosrccSpec > ; # [doc = "Field `GIOSRCC` reader - 7:0\\]
GIO slew rate control for port C"]
pub type GiosrccR = crate :: FieldReader ; # [doc = "Field `GIOSRCC` writer - 7:0\\]
GIO slew rate control for port C"]
pub type GiosrccW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU37` reader - 31:8\\]
Reserved"]
pub type Nu37R = crate :: FieldReader < u32 > ; # [doc = "Field `NU37` writer - 31:8\\]
Reserved"]
pub type Nu37W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port C"]
# [inline (always)]
pub fn giosrcc (& self) -> GiosrccR { GiosrccR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu37 (& self) -> Nu37R { Nu37R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port C"]
# [inline (always)]
# [must_use]
pub fn giosrcc (& mut self) -> GiosrccW < GiosrccSpec > { GiosrccW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu37 (& mut self) -> Nu37W < GiosrccSpec > { Nu37W :: new (self , 8) } } # [doc = "GIO slew rate select for port C\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrccSpec ; impl crate :: RegisterSpec for GiosrccSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrcc::R`](R) reader structure"]
impl crate :: Readable for GiosrccSpec { } # [doc = "`write(|w| ..)` method takes [`giosrcc::W`](W) writer structure"]
impl crate :: Writable for GiosrccSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCC to value 0"]
impl crate :: Resettable for GiosrccSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCD (rw) register accessor: GIO slew rate select for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrcd`]
module"]
# [doc (alias = "GIOSRCD")]
pub type Giosrcd = crate :: Reg < giosrcd :: GiosrcdSpec > ; # [doc = "GIO slew rate select for port D"]
pub mod giosrcd { # [doc = "Register `GIOSRCD` reader"]
pub type R = crate :: R < GiosrcdSpec > ; # [doc = "Register `GIOSRCD` writer"]
pub type W = crate :: W < GiosrcdSpec > ; # [doc = "Field `GIOSRCD` reader - 7:0\\]
GIO slew rate control for port D"]
pub type GiosrcdR = crate :: FieldReader ; # [doc = "Field `GIOSRCD` writer - 7:0\\]
GIO slew rate control for port D"]
pub type GiosrcdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU38` reader - 31:8\\]
Reserved"]
pub type Nu38R = crate :: FieldReader < u32 > ; # [doc = "Field `NU38` writer - 31:8\\]
Reserved"]
pub type Nu38W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port D"]
# [inline (always)]
pub fn giosrcd (& self) -> GiosrcdR { GiosrcdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu38 (& self) -> Nu38R { Nu38R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port D"]
# [inline (always)]
# [must_use]
pub fn giosrcd (& mut self) -> GiosrcdW < GiosrcdSpec > { GiosrcdW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu38 (& mut self) -> Nu38W < GiosrcdSpec > { Nu38W :: new (self , 8) } } # [doc = "GIO slew rate select for port D\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrcdSpec ; impl crate :: RegisterSpec for GiosrcdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrcd::R`](R) reader structure"]
impl crate :: Readable for GiosrcdSpec { } # [doc = "`write(|w| ..)` method takes [`giosrcd::W`](W) writer structure"]
impl crate :: Writable for GiosrcdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCD to value 0"]
impl crate :: Resettable for GiosrcdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCE (rw) register accessor: GIO slew rate select for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrce`]
module"]
# [doc (alias = "GIOSRCE")]
pub type Giosrce = crate :: Reg < giosrce :: GiosrceSpec > ; # [doc = "GIO slew rate select for port E"]
pub mod giosrce { # [doc = "Register `GIOSRCE` reader"]
pub type R = crate :: R < GiosrceSpec > ; # [doc = "Register `GIOSRCE` writer"]
pub type W = crate :: W < GiosrceSpec > ; # [doc = "Field `GIOSRCE` reader - 7:0\\]
GIO slew rate control for port E"]
pub type GiosrceR = crate :: FieldReader ; # [doc = "Field `GIOSRCE` writer - 7:0\\]
GIO slew rate control for port E"]
pub type GiosrceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port E"]
# [inline (always)]
pub fn giosrce (& self) -> GiosrceR { GiosrceR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port E"]
# [inline (always)]
# [must_use]
pub fn giosrce (& mut self) -> GiosrceW < GiosrceSpec > { GiosrceW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiosrceSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO slew rate select for port E\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrceSpec ; impl crate :: RegisterSpec for GiosrceSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrce::R`](R) reader structure"]
impl crate :: Readable for GiosrceSpec { } # [doc = "`write(|w| ..)` method takes [`giosrce::W`](W) writer structure"]
impl crate :: Writable for GiosrceSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCE to value 0"]
impl crate :: Resettable for GiosrceSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCF (rw) register accessor: GIO slew rate select for port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrcf`]
module"]
# [doc (alias = "GIOSRCF")]
pub type Giosrcf = crate :: Reg < giosrcf :: GiosrcfSpec > ; # [doc = "GIO slew rate select for port F"]
pub mod giosrcf { # [doc = "Register `GIOSRCF` reader"]
pub type R = crate :: R < GiosrcfSpec > ; # [doc = "Register `GIOSRCF` writer"]
pub type W = crate :: W < GiosrcfSpec > ; # [doc = "Field `GIOSRCF` reader - 7:0\\]
GIO slew rate control for port F"]
pub type GiosrcfR = crate :: FieldReader ; # [doc = "Field `GIOSRCF` writer - 7:0\\]
GIO slew rate control for port F"]
pub type GiosrcfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port F"]
# [inline (always)]
pub fn giosrcf (& self) -> GiosrcfR { GiosrcfR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port F"]
# [inline (always)]
# [must_use]
pub fn giosrcf (& mut self) -> GiosrcfW < GiosrcfSpec > { GiosrcfW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiosrcfSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO slew rate select for port F\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrcfSpec ; impl crate :: RegisterSpec for GiosrcfSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrcf::R`](R) reader structure"]
impl crate :: Readable for GiosrcfSpec { } # [doc = "`write(|w| ..)` method takes [`giosrcf::W`](W) writer structure"]
impl crate :: Writable for GiosrcfSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCF to value 0"]
impl crate :: Resettable for GiosrcfSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCG (rw) register accessor: GIO slew rate select for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrcg`]
module"]
# [doc (alias = "GIOSRCG")]
pub type Giosrcg = crate :: Reg < giosrcg :: GiosrcgSpec > ; # [doc = "GIO slew rate select for port G"]
pub mod giosrcg { # [doc = "Register `GIOSRCG` reader"]
pub type R = crate :: R < GiosrcgSpec > ; # [doc = "Register `GIOSRCG` writer"]
pub type W = crate :: W < GiosrcgSpec > ; # [doc = "Field `GIOSRCG` reader - 7:0\\]
GIO slew rate control for port G"]
pub type GiosrcgR = crate :: FieldReader ; # [doc = "Field `GIOSRCG` writer - 7:0\\]
GIO slew rate control for port G"]
pub type GiosrcgW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU39` reader - 31:8\\]
Reserved"]
pub type Nu39R = crate :: FieldReader < u32 > ; # [doc = "Field `NU39` writer - 31:8\\]
Reserved"]
pub type Nu39W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port G"]
# [inline (always)]
pub fn giosrcg (& self) -> GiosrcgR { GiosrcgR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu39 (& self) -> Nu39R { Nu39R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port G"]
# [inline (always)]
# [must_use]
pub fn giosrcg (& mut self) -> GiosrcgW < GiosrcgSpec > { GiosrcgW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu39 (& mut self) -> Nu39W < GiosrcgSpec > { Nu39W :: new (self , 8) } } # [doc = "GIO slew rate select for port G\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrcg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrcg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrcgSpec ; impl crate :: RegisterSpec for GiosrcgSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrcg::R`](R) reader structure"]
impl crate :: Readable for GiosrcgSpec { } # [doc = "`write(|w| ..)` method takes [`giosrcg::W`](W) writer structure"]
impl crate :: Writable for GiosrcgSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCG to value 0"]
impl crate :: Resettable for GiosrcgSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "GIOSRCH (rw) register accessor: GIO slew rate select for port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giosrch`]
module"]
# [doc (alias = "GIOSRCH")]
pub type Giosrch = crate :: Reg < giosrch :: GiosrchSpec > ; # [doc = "GIO slew rate select for port H"]
pub mod giosrch { # [doc = "Register `GIOSRCH` reader"]
pub type R = crate :: R < GiosrchSpec > ; # [doc = "Register `GIOSRCH` writer"]
pub type W = crate :: W < GiosrchSpec > ; # [doc = "Field `GIOSRCH` reader - 7:0\\]
GIO slew rate control for port H"]
pub type GiosrchR = crate :: FieldReader ; # [doc = "Field `GIOSRCH` writer - 7:0\\]
GIO slew rate control for port H"]
pub type GiosrchW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NU40` reader - 31:8\\]
Reserved"]
pub type Nu40R = crate :: FieldReader < u32 > ; # [doc = "Field `NU40` writer - 31:8\\]
Reserved"]
pub type Nu40W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port H"]
# [inline (always)]
pub fn giosrch (& self) -> GiosrchR { GiosrchR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
pub fn nu40 (& self) -> Nu40R { Nu40R :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
GIO slew rate control for port H"]
# [inline (always)]
# [must_use]
pub fn giosrch (& mut self) -> GiosrchW < GiosrchSpec > { GiosrchW :: new (self , 0) } # [doc = "Bits 8:31 - 31:8\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn nu40 (& mut self) -> Nu40W < GiosrchSpec > { Nu40W :: new (self , 8) } } # [doc = "GIO slew rate select for port H\n\nYou can [`read`](crate::Reg::read) this register and get [`giosrch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giosrch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GiosrchSpec ; impl crate :: RegisterSpec for GiosrchSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`giosrch::R`](R) reader structure"]
impl crate :: Readable for GiosrchSpec { } # [doc = "`write(|w| ..)` method takes [`giosrch::W`](W) writer structure"]
impl crate :: Writable for GiosrchSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GIOSRCH to value 0"]
impl crate :: Resettable for GiosrchSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "TOPSS_CTRL"]
pub struct TopssCtrl { _marker : PhantomData < * const () > } unsafe impl Send for TopssCtrl { } impl TopssCtrl { # [doc = r"Pointer to the register block"]
pub const PTR : * const topss_ctrl :: RegisterBlock = 0x5b02_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const topss_ctrl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TopssCtrl { type Target = topss_ctrl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TopssCtrl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TopssCtrl") . finish () } } # [doc = "TOPSS_CTRL"]
pub mod topss_ctrl { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , xtal_freq : XtalFreq , sop_mode : SopMode , rs232_bitinterval_0_1 : Rs232Bitinterval0_1 , rs232_bitinterval_2_3 : Rs232Bitinterval2_3 , dig_sync_select : DigSyncSelect , limp_mode_gen_en : LimpModeGenEn , cti_intr_mux_sel : CtiIntrMuxSel , secap_tx_data : SecapTxData , secap_tx_control : SecapTxControl , secap_rx_data : SecapRxData , secap_rx_control : SecapRxControl , dft_proc_dmled_exec : DftProcDmledExec , dft_proc_dmled_status : DftProcDmledStatus , dft_config_reg : DftConfigReg , dft_pbist_st_key : DftPbistStKey , dft_pbist_st_rst : DftPbistStRst , top_intmask : TopIntmask , debug_status_aon_1 : DebugStatusAon1 , debug_status_aon_2 : DebugStatusAon2 , debug_status_aon_3 : DebugStatusAon3 , debug_status_aon_4 : DebugStatusAon4 , debug_status_aon_5 : DebugStatusAon5 , debug_status_aon_6 : DebugStatusAon6 , debug_status_aon_7 : DebugStatusAon7 , debug_status_aon_8 : DebugStatusAon8 , debug_status_aon_9 : DebugStatusAon9 , debug_status_aon_10 : DebugStatusAon10 , debug_status_aon_11 : DebugStatusAon11 , debug_status_aon_12 : DebugStatusAon12 , debug_status_aon_13 : DebugStatusAon13 , debug_status_aon_14 : DebugStatusAon14 , debug_status_aon_15 : DebugStatusAon15 , debug_status_aon_16 : DebugStatusAon16 , appss_dynamic_clk_gate_status : AppssDynamicClkGateStatus , _reserved35 : [u8 ; 0x0f7c]
, lock0_kick0 : Lock0Kick0 , lock0_kick1 : Lock0Kick1 , intr_raw_status : IntrRawStatus , intr_enabled_status_clear : IntrEnabledStatusClear , intr_enable : IntrEnable , intr_enable_clear : IntrEnableClear , eoi : Eoi , fault_address : FaultAddress , fault_type_status : FaultTypeStatus , fault_attr_status : FaultAttrStatus , fault_clear : FaultClear , } impl RegisterBlock { # [doc = "0x00 - PID register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - XTAL_FREQ"]
# [inline (always)]
pub const fn xtal_freq (& self) -> & XtalFreq { & self . xtal_freq } # [doc = "0x08 - SOP_MODE"]
# [inline (always)]
pub const fn sop_mode (& self) -> & SopMode { & self . sop_mode } # [doc = "0x0c - RS232_BITINTERVAL_0_1"]
# [inline (always)]
pub const fn rs232_bitinterval_0_1 (& self) -> & Rs232Bitinterval0_1 { & self . rs232_bitinterval_0_1 } # [doc = "0x10 - RS232_BITINTERVAL_2_3"]
# [inline (always)]
pub const fn rs232_bitinterval_2_3 (& self) -> & Rs232Bitinterval2_3 { & self . rs232_bitinterval_2_3 } # [doc = "0x14 - DIG_SYNC_SELECT"]
# [inline (always)]
pub const fn dig_sync_select (& self) -> & DigSyncSelect { & self . dig_sync_select } # [doc = "0x18 - LIMP_MODE_GEN_EN"]
# [inline (always)]
pub const fn limp_mode_gen_en (& self) -> & LimpModeGenEn { & self . limp_mode_gen_en } # [doc = "0x1c - CTI_INTR_MUX_SEL"]
# [inline (always)]
pub const fn cti_intr_mux_sel (& self) -> & CtiIntrMuxSel { & self . cti_intr_mux_sel } # [doc = "0x20 - SECAP_TX_DATA"]
# [inline (always)]
pub const fn secap_tx_data (& self) -> & SecapTxData { & self . secap_tx_data } # [doc = "0x24 - SECAP_TX_CONTROL"]
# [inline (always)]
pub const fn secap_tx_control (& self) -> & SecapTxControl { & self . secap_tx_control } # [doc = "0x28 - SECAP_RX_DATA"]
# [inline (always)]
pub const fn secap_rx_data (& self) -> & SecapRxData { & self . secap_rx_data } # [doc = "0x2c - SECAP_RX_CONTROL"]
# [inline (always)]
pub const fn secap_rx_control (& self) -> & SecapRxControl { & self . secap_rx_control } # [doc = "0x30 - dft_proc_dmled_exec"]
# [inline (always)]
pub const fn dft_proc_dmled_exec (& self) -> & DftProcDmledExec { & self . dft_proc_dmled_exec } # [doc = "0x34 - dft_proc_dmled_status"]
# [inline (always)]
pub const fn dft_proc_dmled_status (& self) -> & DftProcDmledStatus { & self . dft_proc_dmled_status } # [doc = "0x38 - dft_config_reg"]
# [inline (always)]
pub const fn dft_config_reg (& self) -> & DftConfigReg { & self . dft_config_reg } # [doc = "0x3c - dft_pbist_st_key"]
# [inline (always)]
pub const fn dft_pbist_st_key (& self) -> & DftPbistStKey { & self . dft_pbist_st_key } # [doc = "0x40 - dft_pbist_st_rst"]
# [inline (always)]
pub const fn dft_pbist_st_rst (& self) -> & DftPbistStRst { & self . dft_pbist_st_rst } # [doc = "0x44 - TOP_INTMASK"]
# [inline (always)]
pub const fn top_intmask (& self) -> & TopIntmask { & self . top_intmask } # [doc = "0x48 - DEBUG_STATUS_AON_1"]
# [inline (always)]
pub const fn debug_status_aon_1 (& self) -> & DebugStatusAon1 { & self . debug_status_aon_1 } # [doc = "0x4c - DEBUG_STATUS_AON_2"]
# [inline (always)]
pub const fn debug_status_aon_2 (& self) -> & DebugStatusAon2 { & self . debug_status_aon_2 } # [doc = "0x50 - DEBUG_STATUS_AON_3"]
# [inline (always)]
pub const fn debug_status_aon_3 (& self) -> & DebugStatusAon3 { & self . debug_status_aon_3 } # [doc = "0x54 - DEBUG_STATUS_AON_4"]
# [inline (always)]
pub const fn debug_status_aon_4 (& self) -> & DebugStatusAon4 { & self . debug_status_aon_4 } # [doc = "0x58 - DEBUG_STATUS_AON_5"]
# [inline (always)]
pub const fn debug_status_aon_5 (& self) -> & DebugStatusAon5 { & self . debug_status_aon_5 } # [doc = "0x5c - DEBUG_STATUS_AON_6"]
# [inline (always)]
pub const fn debug_status_aon_6 (& self) -> & DebugStatusAon6 { & self . debug_status_aon_6 } # [doc = "0x60 - DEBUG_STATUS_AON_7"]
# [inline (always)]
pub const fn debug_status_aon_7 (& self) -> & DebugStatusAon7 { & self . debug_status_aon_7 } # [doc = "0x64 - DEBUG_STATUS_AON_8"]
# [inline (always)]
pub const fn debug_status_aon_8 (& self) -> & DebugStatusAon8 { & self . debug_status_aon_8 } # [doc = "0x68 - DEBUG_STATUS_AON_9"]
# [inline (always)]
pub const fn debug_status_aon_9 (& self) -> & DebugStatusAon9 { & self . debug_status_aon_9 } # [doc = "0x6c - DEBUG_STATUS_AON_10"]
# [inline (always)]
pub const fn debug_status_aon_10 (& self) -> & DebugStatusAon10 { & self . debug_status_aon_10 } # [doc = "0x70 - DEBUG_STATUS_AON_11"]
# [inline (always)]
pub const fn debug_status_aon_11 (& self) -> & DebugStatusAon11 { & self . debug_status_aon_11 } # [doc = "0x74 - DEBUG_STATUS_AON_12"]
# [inline (always)]
pub const fn debug_status_aon_12 (& self) -> & DebugStatusAon12 { & self . debug_status_aon_12 } # [doc = "0x78 - DEBUG_STATUS_AON_13"]
# [inline (always)]
pub const fn debug_status_aon_13 (& self) -> & DebugStatusAon13 { & self . debug_status_aon_13 } # [doc = "0x7c - DEBUG_STATUS_AON_14"]
# [inline (always)]
pub const fn debug_status_aon_14 (& self) -> & DebugStatusAon14 { & self . debug_status_aon_14 } # [doc = "0x80 - DEBUG_STATUS_AON_15"]
# [inline (always)]
pub const fn debug_status_aon_15 (& self) -> & DebugStatusAon15 { & self . debug_status_aon_15 } # [doc = "0x84 - DEBUG_STATUS_AON_16"]
# [inline (always)]
pub const fn debug_status_aon_16 (& self) -> & DebugStatusAon16 { & self . debug_status_aon_16 } # [doc = "0x88 - APPSS_DYNAMIC_CLK_GATE_STATUS"]
# [inline (always)]
pub const fn appss_dynamic_clk_gate_status (& self) -> & AppssDynamicClkGateStatus { & self . appss_dynamic_clk_gate_status } # [doc = "0x1008 - - KICK0 component"]
# [inline (always)]
pub const fn lock0_kick0 (& self) -> & Lock0Kick0 { & self . lock0_kick0 } # [doc = "0x100c - - KICK1 component"]
# [inline (always)]
pub const fn lock0_kick1 (& self) -> & Lock0Kick1 { & self . lock0_kick1 } # [doc = "0x1010 - Interrupt Raw Status/Set Register"]
# [inline (always)]
pub const fn intr_raw_status (& self) -> & IntrRawStatus { & self . intr_raw_status } # [doc = "0x1014 - Interrupt Enabled Status/Clear register"]
# [inline (always)]
pub const fn intr_enabled_status_clear (& self) -> & IntrEnabledStatusClear { & self . intr_enabled_status_clear } # [doc = "0x1018 - Interrupt Enable register"]
# [inline (always)]
pub const fn intr_enable (& self) -> & IntrEnable { & self . intr_enable } # [doc = "0x101c - Interrupt Enable Clear register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x1020 - EOI register"]
# [inline (always)]
pub const fn eoi (& self) -> & Eoi { & self . eoi } # [doc = "0x1024 - Fault Address register"]
# [inline (always)]
pub const fn fault_address (& self) -> & FaultAddress { & self . fault_address } # [doc = "0x1028 - Fault Type Status register"]
# [inline (always)]
pub const fn fault_type_status (& self) -> & FaultTypeStatus { & self . fault_type_status } # [doc = "0x102c - Fault Attribute Status register"]
# [inline (always)]
pub const fn fault_attr_status (& self) -> & FaultAttrStatus { & self . fault_attr_status } # [doc = "0x1030 - Fault Clear register"]
# [inline (always)]
pub const fn fault_clear (& self) -> & FaultClear { & self . fault_clear } } # [doc = "PID (rw) register accessor: PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `PID_W6_O0` reader - "]
pub type PidW6O0R = crate :: FieldReader ; # [doc = "Field `PID_W6_O0` writer - "]
pub type PidW6O0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PID_W2_O6` reader - "]
pub type PidW2O6R = crate :: FieldReader ; # [doc = "Field `PID_W2_O6` writer - "]
pub type PidW2O6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PID_W3_O8` reader - "]
pub type PidW3O8R = crate :: FieldReader ; # [doc = "Field `PID_W3_O8` writer - "]
pub type PidW3O8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PID_W5_O11` reader - "]
pub type PidW5O11R = crate :: FieldReader ; # [doc = "Field `PID_W5_O11` writer - "]
pub type PidW5O11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PID_W16_O16` reader - "]
pub type PidW16O16R = crate :: FieldReader < u16 > ; # [doc = "Field `PID_W16_O16` writer - "]
pub type PidW16O16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5"]
# [inline (always)]
pub fn pid_w6_o0 (& self) -> PidW6O0R { PidW6O0R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7"]
# [inline (always)]
pub fn pid_w2_o6 (& self) -> PidW2O6R { PidW2O6R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10"]
# [inline (always)]
pub fn pid_w3_o8 (& self) -> PidW3O8R { PidW3O8R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15"]
# [inline (always)]
pub fn pid_w5_o11 (& self) -> PidW5O11R { PidW5O11R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn pid_w16_o16 (& self) -> PidW16O16R { PidW16O16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5"]
# [inline (always)]
# [must_use]
pub fn pid_w6_o0 (& mut self) -> PidW6O0W < PidSpec > { PidW6O0W :: new (self , 0) } # [doc = "Bits 6:7"]
# [inline (always)]
# [must_use]
pub fn pid_w2_o6 (& mut self) -> PidW2O6W < PidSpec > { PidW2O6W :: new (self , 6) } # [doc = "Bits 8:10"]
# [inline (always)]
# [must_use]
pub fn pid_w3_o8 (& mut self) -> PidW3O8W < PidSpec > { PidW3O8W :: new (self , 8) } # [doc = "Bits 11:15"]
# [inline (always)]
# [must_use]
pub fn pid_w5_o11 (& mut self) -> PidW5O11W < PidSpec > { PidW5O11W :: new (self , 11) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn pid_w16_o16 (& mut self) -> PidW16O16W < PidSpec > { PidW16O16W :: new (self , 16) } } # [doc = "PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "XTAL_FREQ (rw) register accessor: XTAL_FREQ\n\nYou can [`read`](crate::Reg::read) this register and get [`xtal_freq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtal_freq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xtal_freq`]
module"]
# [doc (alias = "XTAL_FREQ")]
pub type XtalFreq = crate :: Reg < xtal_freq :: XtalFreqSpec > ; # [doc = "XTAL_FREQ"]
pub mod xtal_freq { # [doc = "Register `XTAL_FREQ` reader"]
pub type R = crate :: R < XtalFreqSpec > ; # [doc = "Register `XTAL_FREQ` writer"]
pub type W = crate :: W < XtalFreqSpec > ; # [doc = "Field `clkm_xtal_freq` reader - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
pub type ClkmXtalFreqR = crate :: FieldReader ; # [doc = "Field `clkm_xtal_freq` writer - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
pub type ClkmXtalFreqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
# [inline (always)]
pub fn clkm_xtal_freq (& self) -> ClkmXtalFreqR { ClkmXtalFreqR :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_freq (& mut self) -> ClkmXtalFreqW < XtalFreqSpec > { ClkmXtalFreqW :: new (self , 0) } } # [doc = "XTAL_FREQ\n\nYou can [`read`](crate::Reg::read) this register and get [`xtal_freq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtal_freq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XtalFreqSpec ; impl crate :: RegisterSpec for XtalFreqSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`xtal_freq::R`](R) reader structure"]
impl crate :: Readable for XtalFreqSpec { } # [doc = "`write(|w| ..)` method takes [`xtal_freq::W`](W) writer structure"]
impl crate :: Writable for XtalFreqSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets XTAL_FREQ to value 0"]
impl crate :: Resettable for XtalFreqSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SOP_MODE (rw) register accessor: SOP_MODE\n\nYou can [`read`](crate::Reg::read) this register and get [`sop_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sop_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sop_mode`]
module"]
# [doc (alias = "SOP_MODE")]
pub type SopMode = crate :: Reg < sop_mode :: SopModeSpec > ; # [doc = "SOP_MODE"]
pub mod sop_mode { # [doc = "Register `SOP_MODE` reader"]
pub type R = crate :: R < SopModeSpec > ; # [doc = "Register `SOP_MODE` writer"]
pub type W = crate :: W < SopModeSpec > ; # [doc = "Field `sop_mode` reader - 1:0\\]
SOP MODE, 0x0 = Device Management Mode 0x1 = Application Mode 0x2 = Test mode 0x3 = Debug Mode"]
pub type SopModeR = crate :: FieldReader ; # [doc = "Field `sop_mode` writer - 1:0\\]
SOP MODE, 0x0 = Device Management Mode 0x1 = Application Mode 0x2 = Test mode 0x3 = Debug Mode"]
pub type SopModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
SOP MODE, 0x0 = Device Management Mode 0x1 = Application Mode 0x2 = Test mode 0x3 = Debug Mode"]
# [inline (always)]
pub fn sop_mode (& self) -> SopModeR { SopModeR :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
SOP MODE, 0x0 = Device Management Mode 0x1 = Application Mode 0x2 = Test mode 0x3 = Debug Mode"]
# [inline (always)]
# [must_use]
pub fn sop_mode (& mut self) -> SopModeW < SopModeSpec > { SopModeW :: new (self , 0) } } # [doc = "SOP_MODE\n\nYou can [`read`](crate::Reg::read) this register and get [`sop_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sop_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SopModeSpec ; impl crate :: RegisterSpec for SopModeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sop_mode::R`](R) reader structure"]
impl crate :: Readable for SopModeSpec { } # [doc = "`write(|w| ..)` method takes [`sop_mode::W`](W) writer structure"]
impl crate :: Writable for SopModeSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SOP_MODE to value 0"]
impl crate :: Resettable for SopModeSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RS232_BITINTERVAL_0_1 (rw) register accessor: RS232_BITINTERVAL_0_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rs232_bitinterval_0_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rs232_bitinterval_0_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs232_bitinterval_0_1`]
module"]
# [doc (alias = "RS232_BITINTERVAL_0_1")]
pub type Rs232Bitinterval0_1 = crate :: Reg < rs232_bitinterval_0_1 :: Rs232Bitinterval0_1Spec > ; # [doc = "RS232_BITINTERVAL_0_1"]
pub mod rs232_bitinterval_0_1 { # [doc = "Register `RS232_BITINTERVAL_0_1` reader"]
pub type R = crate :: R < Rs232Bitinterval0_1Spec > ; # [doc = "Register `RS232_BITINTERVAL_0_1` writer"]
pub type W = crate :: W < Rs232Bitinterval0_1Spec > ; # [doc = "Field `rs232_bitinterval_0` reader - 11:0\\]
BIT Interval value for 25MHz XTAL"]
pub type Rs232Bitinterval0R = crate :: FieldReader < u16 > ; # [doc = "Field `rs232_bitinterval_0` writer - 11:0\\]
BIT Interval value for 25MHz XTAL"]
pub type Rs232Bitinterval0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `rs232_bitinterval_1` reader - 27:16\\]
BIT Interval value for 40MHz XTAL"]
pub type Rs232Bitinterval1R = crate :: FieldReader < u16 > ; # [doc = "Field `rs232_bitinterval_1` writer - 27:16\\]
BIT Interval value for 40MHz XTAL"]
pub type Rs232Bitinterval1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
BIT Interval value for 25MHz XTAL"]
# [inline (always)]
pub fn rs232_bitinterval_0 (& self) -> Rs232Bitinterval0R { Rs232Bitinterval0R :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
BIT Interval value for 40MHz XTAL"]
# [inline (always)]
pub fn rs232_bitinterval_1 (& self) -> Rs232Bitinterval1R { Rs232Bitinterval1R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
BIT Interval value for 25MHz XTAL"]
# [inline (always)]
# [must_use]
pub fn rs232_bitinterval_0 (& mut self) -> Rs232Bitinterval0W < Rs232Bitinterval0_1Spec > { Rs232Bitinterval0W :: new (self , 0) } # [doc = "Bits 16:27 - 27:16\\]
BIT Interval value for 40MHz XTAL"]
# [inline (always)]
# [must_use]
pub fn rs232_bitinterval_1 (& mut self) -> Rs232Bitinterval1W < Rs232Bitinterval0_1Spec > { Rs232Bitinterval1W :: new (self , 16) } } # [doc = "RS232_BITINTERVAL_0_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rs232_bitinterval_0_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rs232_bitinterval_0_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rs232Bitinterval0_1Spec ; impl crate :: RegisterSpec for Rs232Bitinterval0_1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rs232_bitinterval_0_1::R`](R) reader structure"]
impl crate :: Readable for Rs232Bitinterval0_1Spec { } # [doc = "`write(|w| ..)` method takes [`rs232_bitinterval_0_1::W`](W) writer structure"]
impl crate :: Writable for Rs232Bitinterval0_1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RS232_BITINTERVAL_0_1 to value 0"]
impl crate :: Resettable for Rs232Bitinterval0_1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "RS232_BITINTERVAL_2_3 (rw) register accessor: RS232_BITINTERVAL_2_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rs232_bitinterval_2_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rs232_bitinterval_2_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs232_bitinterval_2_3`]
module"]
# [doc (alias = "RS232_BITINTERVAL_2_3")]
pub type Rs232Bitinterval2_3 = crate :: Reg < rs232_bitinterval_2_3 :: Rs232Bitinterval2_3Spec > ; # [doc = "RS232_BITINTERVAL_2_3"]
pub mod rs232_bitinterval_2_3 { # [doc = "Register `RS232_BITINTERVAL_2_3` reader"]
pub type R = crate :: R < Rs232Bitinterval2_3Spec > ; # [doc = "Register `RS232_BITINTERVAL_2_3` writer"]
pub type W = crate :: W < Rs232Bitinterval2_3Spec > ; # [doc = "Field `rs232_bitinterval_2` reader - 11:0\\]
BIT Interval value for 26MHz XTAL"]
pub type Rs232Bitinterval2R = crate :: FieldReader < u16 > ; # [doc = "Field `rs232_bitinterval_2` writer - 11:0\\]
BIT Interval value for 26MHz XTAL"]
pub type Rs232Bitinterval2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `rs232_bitinterval_3` reader - 27:16\\]
BIT Interval value for 38.4MHz XTAL"]
pub type Rs232Bitinterval3R = crate :: FieldReader < u16 > ; # [doc = "Field `rs232_bitinterval_3` writer - 27:16\\]
BIT Interval value for 38.4MHz XTAL"]
pub type Rs232Bitinterval3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
BIT Interval value for 26MHz XTAL"]
# [inline (always)]
pub fn rs232_bitinterval_2 (& self) -> Rs232Bitinterval2R { Rs232Bitinterval2R :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
BIT Interval value for 38.4MHz XTAL"]
# [inline (always)]
pub fn rs232_bitinterval_3 (& self) -> Rs232Bitinterval3R { Rs232Bitinterval3R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
BIT Interval value for 26MHz XTAL"]
# [inline (always)]
# [must_use]
pub fn rs232_bitinterval_2 (& mut self) -> Rs232Bitinterval2W < Rs232Bitinterval2_3Spec > { Rs232Bitinterval2W :: new (self , 0) } # [doc = "Bits 16:27 - 27:16\\]
BIT Interval value for 38.4MHz XTAL"]
# [inline (always)]
# [must_use]
pub fn rs232_bitinterval_3 (& mut self) -> Rs232Bitinterval3W < Rs232Bitinterval2_3Spec > { Rs232Bitinterval3W :: new (self , 16) } } # [doc = "RS232_BITINTERVAL_2_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rs232_bitinterval_2_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rs232_bitinterval_2_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rs232Bitinterval2_3Spec ; impl crate :: RegisterSpec for Rs232Bitinterval2_3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`rs232_bitinterval_2_3::R`](R) reader structure"]
impl crate :: Readable for Rs232Bitinterval2_3Spec { } # [doc = "`write(|w| ..)` method takes [`rs232_bitinterval_2_3::W`](W) writer structure"]
impl crate :: Writable for Rs232Bitinterval2_3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RS232_BITINTERVAL_2_3 to value 0"]
impl crate :: Resettable for Rs232Bitinterval2_3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DIG_SYNC_SELECT (rw) register accessor: DIG_SYNC_SELECT\n\nYou can [`read`](crate::Reg::read) this register and get [`dig_sync_select::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dig_sync_select::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dig_sync_select`]
module"]
# [doc (alias = "DIG_SYNC_SELECT")]
pub type DigSyncSelect = crate :: Reg < dig_sync_select :: DigSyncSelectSpec > ; # [doc = "DIG_SYNC_SELECT"]
pub mod dig_sync_select { # [doc = "Register `DIG_SYNC_SELECT` reader"]
pub type R = crate :: R < DigSyncSelectSpec > ; # [doc = "Register `DIG_SYNC_SELECT` writer"]
pub type W = crate :: W < DigSyncSelectSpec > ; # [doc = "Field `dig_sync_select` reader - 1:0\\]
Selects dig_sync_in for FRC 2'b00: dig_sync_in 2'b01: mcan_intr 2'b10: lin_intr"]
pub type DigSyncSelectR = crate :: FieldReader ; # [doc = "Field `dig_sync_select` writer - 1:0\\]
Selects dig_sync_in for FRC 2'b00: dig_sync_in 2'b01: mcan_intr 2'b10: lin_intr"]
pub type DigSyncSelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Selects dig_sync_in for FRC 2'b00: dig_sync_in 2'b01: mcan_intr 2'b10: lin_intr"]
# [inline (always)]
pub fn dig_sync_select (& self) -> DigSyncSelectR { DigSyncSelectR :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Selects dig_sync_in for FRC 2'b00: dig_sync_in 2'b01: mcan_intr 2'b10: lin_intr"]
# [inline (always)]
# [must_use]
pub fn dig_sync_select (& mut self) -> DigSyncSelectW < DigSyncSelectSpec > { DigSyncSelectW :: new (self , 0) } } # [doc = "DIG_SYNC_SELECT\n\nYou can [`read`](crate::Reg::read) this register and get [`dig_sync_select::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dig_sync_select::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DigSyncSelectSpec ; impl crate :: RegisterSpec for DigSyncSelectSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dig_sync_select::R`](R) reader structure"]
impl crate :: Readable for DigSyncSelectSpec { } # [doc = "`write(|w| ..)` method takes [`dig_sync_select::W`](W) writer structure"]
impl crate :: Writable for DigSyncSelectSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DIG_SYNC_SELECT to value 0"]
impl crate :: Resettable for DigSyncSelectSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LIMP_MODE_GEN_EN (rw) register accessor: LIMP_MODE_GEN_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`limp_mode_gen_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`limp_mode_gen_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@limp_mode_gen_en`]
module"]
# [doc (alias = "LIMP_MODE_GEN_EN")]
pub type LimpModeGenEn = crate :: Reg < limp_mode_gen_en :: LimpModeGenEnSpec > ; # [doc = "LIMP_MODE_GEN_EN"]
pub mod limp_mode_gen_en { # [doc = "Register `LIMP_MODE_GEN_EN` reader"]
pub type R = crate :: R < LimpModeGenEnSpec > ; # [doc = "Register `LIMP_MODE_GEN_EN` writer"]
pub type W = crate :: W < LimpModeGenEnSpec > ; # [doc = "Field `dcc_error_limp_gen_enable` reader - 2:0\\]
Enable EDCC Error to generate Limp mode 3'b000: EDCC Error will not generate Limp mode (multibit 000) 3'b111 : EDCC Error will generate Limp mode (multibit 111)"]
pub type DccErrorLimpGenEnableR = crate :: FieldReader ; # [doc = "Field `dcc_error_limp_gen_enable` writer - 2:0\\]
Enable EDCC Error to generate Limp mode 3'b000: EDCC Error will not generate Limp mode (multibit 000) 3'b111 : EDCC Error will generate Limp mode (multibit 111)"]
pub type DccErrorLimpGenEnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `plldig_lockmon_limp_gen_enable` reader - 10:8\\]
Enable PLLDIG lockmon to generate Limp mode 3'b000: PLLDIG lockmon will not generate Limp mode (multibit 000) 3'b111 : PLLDIG lockmon will generate Limp mode (multibit 111)"]
pub type PlldigLockmonLimpGenEnableR = crate :: FieldReader ; # [doc = "Field `plldig_lockmon_limp_gen_enable` writer - 10:8\\]
Enable PLLDIG lockmon to generate Limp mode 3'b000: PLLDIG lockmon will not generate Limp mode (multibit 000) 3'b111 : PLLDIG lockmon will generate Limp mode (multibit 111)"]
pub type PlldigLockmonLimpGenEnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PLLDIG_LOCKMON_ESM_ERR_GEN_ENABLE` reader - 13:11\\]
Enable PLLDIG lockmon to generate esm error 3'b000: PLLDIG lockmon will not generate esm error (multibit 000) 3'b111 : PLLDIG lockmon will generate esm error (multibit 111)"]
pub type PlldigLockmonEsmErrGenEnableR = crate :: FieldReader ; # [doc = "Field `PLLDIG_LOCKMON_ESM_ERR_GEN_ENABLE` writer - 13:11\\]
Enable PLLDIG lockmon to generate esm error 3'b000: PLLDIG lockmon will not generate esm error (multibit 000) 3'b111 : PLLDIG lockmon will generate esm error (multibit 111)"]
pub type PlldigLockmonEsmErrGenEnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `limp_mode_dcc` reader - 16:16\\]
status reg for limp_mode_dcc"]
pub type LimpModeDccR = crate :: BitReader ; # [doc = "Field `limp_mode_dcc` writer - 16:16\\]
status reg for limp_mode_dcc"]
pub type LimpModeDccW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `limp_mode_plldig_lockmon` reader - 24:24\\]
status reg for limp_mode_plldig_lockmon"]
pub type LimpModePlldigLockmonR = crate :: BitReader ; # [doc = "Field `limp_mode_plldig_lockmon` writer - 24:24\\]
status reg for limp_mode_plldig_lockmon"]
pub type LimpModePlldigLockmonW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Enable EDCC Error to generate Limp mode 3'b000: EDCC Error will not generate Limp mode (multibit 000) 3'b111 : EDCC Error will generate Limp mode (multibit 111)"]
# [inline (always)]
pub fn dcc_error_limp_gen_enable (& self) -> DccErrorLimpGenEnableR { DccErrorLimpGenEnableR :: new ((self . bits & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Enable PLLDIG lockmon to generate Limp mode 3'b000: PLLDIG lockmon will not generate Limp mode (multibit 000) 3'b111 : PLLDIG lockmon will generate Limp mode (multibit 111)"]
# [inline (always)]
pub fn plldig_lockmon_limp_gen_enable (& self) -> PlldigLockmonLimpGenEnableR { PlldigLockmonLimpGenEnableR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:13 - 13:11\\]
Enable PLLDIG lockmon to generate esm error 3'b000: PLLDIG lockmon will not generate esm error (multibit 000) 3'b111 : PLLDIG lockmon will generate esm error (multibit 111)"]
# [inline (always)]
pub fn plldig_lockmon_esm_err_gen_enable (& self) -> PlldigLockmonEsmErrGenEnableR { PlldigLockmonEsmErrGenEnableR :: new (((self . bits >> 11) & 7) as u8) } # [doc = "Bit 16 - 16:16\\]
status reg for limp_mode_dcc"]
# [inline (always)]
pub fn limp_mode_dcc (& self) -> LimpModeDccR { LimpModeDccR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
status reg for limp_mode_plldig_lockmon"]
# [inline (always)]
pub fn limp_mode_plldig_lockmon (& self) -> LimpModePlldigLockmonR { LimpModePlldigLockmonR :: new (((self . bits >> 24) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Enable EDCC Error to generate Limp mode 3'b000: EDCC Error will not generate Limp mode (multibit 000) 3'b111 : EDCC Error will generate Limp mode (multibit 111)"]
# [inline (always)]
# [must_use]
pub fn dcc_error_limp_gen_enable (& mut self) -> DccErrorLimpGenEnableW < LimpModeGenEnSpec > { DccErrorLimpGenEnableW :: new (self , 0) } # [doc = "Bits 8:10 - 10:8\\]
Enable PLLDIG lockmon to generate Limp mode 3'b000: PLLDIG lockmon will not generate Limp mode (multibit 000) 3'b111 : PLLDIG lockmon will generate Limp mode (multibit 111)"]
# [inline (always)]
# [must_use]
pub fn plldig_lockmon_limp_gen_enable (& mut self) -> PlldigLockmonLimpGenEnableW < LimpModeGenEnSpec > { PlldigLockmonLimpGenEnableW :: new (self , 8) } # [doc = "Bits 11:13 - 13:11\\]
Enable PLLDIG lockmon to generate esm error 3'b000: PLLDIG lockmon will not generate esm error (multibit 000) 3'b111 : PLLDIG lockmon will generate esm error (multibit 111)"]
# [inline (always)]
# [must_use]
pub fn plldig_lockmon_esm_err_gen_enable (& mut self) -> PlldigLockmonEsmErrGenEnableW < LimpModeGenEnSpec > { PlldigLockmonEsmErrGenEnableW :: new (self , 11) } # [doc = "Bit 16 - 16:16\\]
status reg for limp_mode_dcc"]
# [inline (always)]
# [must_use]
pub fn limp_mode_dcc (& mut self) -> LimpModeDccW < LimpModeGenEnSpec > { LimpModeDccW :: new (self , 16) } # [doc = "Bit 24 - 24:24\\]
status reg for limp_mode_plldig_lockmon"]
# [inline (always)]
# [must_use]
pub fn limp_mode_plldig_lockmon (& mut self) -> LimpModePlldigLockmonW < LimpModeGenEnSpec > { LimpModePlldigLockmonW :: new (self , 24) } } # [doc = "LIMP_MODE_GEN_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`limp_mode_gen_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`limp_mode_gen_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LimpModeGenEnSpec ; impl crate :: RegisterSpec for LimpModeGenEnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`limp_mode_gen_en::R`](R) reader structure"]
impl crate :: Readable for LimpModeGenEnSpec { } # [doc = "`write(|w| ..)` method takes [`limp_mode_gen_en::W`](W) writer structure"]
impl crate :: Writable for LimpModeGenEnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LIMP_MODE_GEN_EN to value 0"]
impl crate :: Resettable for LimpModeGenEnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTI_INTR_MUX_SEL (rw) register accessor: CTI_INTR_MUX_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`cti_intr_mux_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cti_intr_mux_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cti_intr_mux_sel`]
module"]
# [doc (alias = "CTI_INTR_MUX_SEL")]
pub type CtiIntrMuxSel = crate :: Reg < cti_intr_mux_sel :: CtiIntrMuxSelSpec > ; # [doc = "CTI_INTR_MUX_SEL"]
pub mod cti_intr_mux_sel { # [doc = "Register `CTI_INTR_MUX_SEL` reader"]
pub type R = crate :: R < CtiIntrMuxSelSpec > ; # [doc = "Register `CTI_INTR_MUX_SEL` writer"]
pub type W = crate :: W < CtiIntrMuxSelSpec > ; # [doc = "Field `CTI0_intr_mux_select` reader - 1:0\\]
CTI0 mux select 2'b00: ESM_LO_IRQ 2'b01: FEC_INTRundefined 2'b10: FEC_INTRundefined"]
pub type Cti0IntrMuxSelectR = crate :: FieldReader ; # [doc = "Field `CTI0_intr_mux_select` writer - 1:0\\]
CTI0 mux select 2'b00: ESM_LO_IRQ 2'b01: FEC_INTRundefined 2'b10: FEC_INTRundefined"]
pub type Cti0IntrMuxSelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CTI1_intr_mux_select` reader - 10:8\\]
CTI1 mux select 3'b000: app_rti_int_req0 3'b001: app_rti_int_req1 3'b010: tpcc_1_intagg 3'b011: tpcc_2_intagg 3'b100: hwa_loop_int 3'b101: hwa_paramdone_int"]
pub type Cti1IntrMuxSelectR = crate :: FieldReader ; # [doc = "Field `CTI1_intr_mux_select` writer - 10:8\\]
CTI1 mux select 3'b000: app_rti_int_req0 3'b001: app_rti_int_req1 3'b010: tpcc_1_intagg 3'b011: tpcc_2_intagg 3'b100: hwa_loop_int 3'b101: hwa_paramdone_int"]
pub type Cti1IntrMuxSelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CTI2_intr_mux_select` reader - 17:16\\]
CTI2 mux select 2'b00: CHIRP_AVAIL_IRQ 2'b01: ADC_VALID_START 2'b10: CHIRPTIMER_CHIRP_START 2'b11: CHIRPTIMER_CHIRP_END"]
pub type Cti2IntrMuxSelectR = crate :: FieldReader ; # [doc = "Field `CTI2_intr_mux_select` writer - 17:16\\]
CTI2 mux select 2'b00: CHIRP_AVAIL_IRQ 2'b01: ADC_VALID_START 2'b10: CHIRPTIMER_CHIRP_START 2'b11: CHIRPTIMER_CHIRP_END"]
pub type Cti2IntrMuxSelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CTI3_intr_mux_select` reader - 26:24\\]
CTI3 mux select 3'b000: FRAMETIMER_FRAME_START 3'b001: FRAME_START_OFFSET_INTR_TIME1 3'b010: BURST_START_OFFSET_TIME 3'b011: CHIRPTIMER_BURST_START 3'b100: CHIRPTIMER_BURST_END"]
pub type Cti3IntrMuxSelectR = crate :: FieldReader ; # [doc = "Field `CTI3_intr_mux_select` writer - 26:24\\]
CTI3 mux select 3'b000: FRAMETIMER_FRAME_START 3'b001: FRAME_START_OFFSET_INTR_TIME1 3'b010: BURST_START_OFFSET_TIME 3'b011: CHIRPTIMER_BURST_START 3'b100: CHIRPTIMER_BURST_END"]
pub type Cti3IntrMuxSelectW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
CTI0 mux select 2'b00: ESM_LO_IRQ 2'b01: FEC_INTRundefined 2'b10: FEC_INTRundefined"]
# [inline (always)]
pub fn cti0_intr_mux_select (& self) -> Cti0IntrMuxSelectR { Cti0IntrMuxSelectR :: new ((self . bits & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
CTI1 mux select 3'b000: app_rti_int_req0 3'b001: app_rti_int_req1 3'b010: tpcc_1_intagg 3'b011: tpcc_2_intagg 3'b100: hwa_loop_int 3'b101: hwa_paramdone_int"]
# [inline (always)]
pub fn cti1_intr_mux_select (& self) -> Cti1IntrMuxSelectR { Cti1IntrMuxSelectR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 16:17 - 17:16\\]
CTI2 mux select 2'b00: CHIRP_AVAIL_IRQ 2'b01: ADC_VALID_START 2'b10: CHIRPTIMER_CHIRP_START 2'b11: CHIRPTIMER_CHIRP_END"]
# [inline (always)]
pub fn cti2_intr_mux_select (& self) -> Cti2IntrMuxSelectR { Cti2IntrMuxSelectR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 24:26 - 26:24\\]
CTI3 mux select 3'b000: FRAMETIMER_FRAME_START 3'b001: FRAME_START_OFFSET_INTR_TIME1 3'b010: BURST_START_OFFSET_TIME 3'b011: CHIRPTIMER_BURST_START 3'b100: CHIRPTIMER_BURST_END"]
# [inline (always)]
pub fn cti3_intr_mux_select (& self) -> Cti3IntrMuxSelectR { Cti3IntrMuxSelectR :: new (((self . bits >> 24) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
CTI0 mux select 2'b00: ESM_LO_IRQ 2'b01: FEC_INTRundefined 2'b10: FEC_INTRundefined"]
# [inline (always)]
# [must_use]
pub fn cti0_intr_mux_select (& mut self) -> Cti0IntrMuxSelectW < CtiIntrMuxSelSpec > { Cti0IntrMuxSelectW :: new (self , 0) } # [doc = "Bits 8:10 - 10:8\\]
CTI1 mux select 3'b000: app_rti_int_req0 3'b001: app_rti_int_req1 3'b010: tpcc_1_intagg 3'b011: tpcc_2_intagg 3'b100: hwa_loop_int 3'b101: hwa_paramdone_int"]
# [inline (always)]
# [must_use]
pub fn cti1_intr_mux_select (& mut self) -> Cti1IntrMuxSelectW < CtiIntrMuxSelSpec > { Cti1IntrMuxSelectW :: new (self , 8) } # [doc = "Bits 16:17 - 17:16\\]
CTI2 mux select 2'b00: CHIRP_AVAIL_IRQ 2'b01: ADC_VALID_START 2'b10: CHIRPTIMER_CHIRP_START 2'b11: CHIRPTIMER_CHIRP_END"]
# [inline (always)]
# [must_use]
pub fn cti2_intr_mux_select (& mut self) -> Cti2IntrMuxSelectW < CtiIntrMuxSelSpec > { Cti2IntrMuxSelectW :: new (self , 16) } # [doc = "Bits 24:26 - 26:24\\]
CTI3 mux select 3'b000: FRAMETIMER_FRAME_START 3'b001: FRAME_START_OFFSET_INTR_TIME1 3'b010: BURST_START_OFFSET_TIME 3'b011: CHIRPTIMER_BURST_START 3'b100: CHIRPTIMER_BURST_END"]
# [inline (always)]
# [must_use]
pub fn cti3_intr_mux_select (& mut self) -> Cti3IntrMuxSelectW < CtiIntrMuxSelSpec > { Cti3IntrMuxSelectW :: new (self , 24) } } # [doc = "CTI_INTR_MUX_SEL\n\nYou can [`read`](crate::Reg::read) this register and get [`cti_intr_mux_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cti_intr_mux_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtiIntrMuxSelSpec ; impl crate :: RegisterSpec for CtiIntrMuxSelSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`cti_intr_mux_sel::R`](R) reader structure"]
impl crate :: Readable for CtiIntrMuxSelSpec { } # [doc = "`write(|w| ..)` method takes [`cti_intr_mux_sel::W`](W) writer structure"]
impl crate :: Writable for CtiIntrMuxSelSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTI_INTR_MUX_SEL to value 0"]
impl crate :: Resettable for CtiIntrMuxSelSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECAP_TX_DATA (rw) register accessor: SECAP_TX_DATA\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_tx_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_tx_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secap_tx_data`]
module"]
# [doc (alias = "SECAP_TX_DATA")]
pub type SecapTxData = crate :: Reg < secap_tx_data :: SecapTxDataSpec > ; # [doc = "SECAP_TX_DATA"]
pub mod secap_tx_data { # [doc = "Register `SECAP_TX_DATA` reader"]
pub type R = crate :: R < SecapTxDataSpec > ; # [doc = "Register `SECAP_TX_DATA` writer"]
pub type W = crate :: W < SecapTxDataSpec > ; # [doc = "Field `JTAGTXDATA` reader - 31:0\\]
This register is used to pass data to the system security logic. The data is transmit from the external JTAG interface and hence is the Rx path for the SECAP interface."]
pub type JtagtxdataR = crate :: FieldReader < u32 > ; # [doc = "Field `JTAGTXDATA` writer - 31:0\\]
This register is used to pass data to the system security logic. The data is transmit from the external JTAG interface and hence is the Rx path for the SECAP interface."]
pub type JtagtxdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register is used to pass data to the system security logic. The data is transmit from the external JTAG interface and hence is the Rx path for the SECAP interface."]
# [inline (always)]
pub fn jtagtxdata (& self) -> JtagtxdataR { JtagtxdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register is used to pass data to the system security logic. The data is transmit from the external JTAG interface and hence is the Rx path for the SECAP interface."]
# [inline (always)]
# [must_use]
pub fn jtagtxdata (& mut self) -> JtagtxdataW < SecapTxDataSpec > { JtagtxdataW :: new (self , 0) } } # [doc = "SECAP_TX_DATA\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_tx_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_tx_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecapTxDataSpec ; impl crate :: RegisterSpec for SecapTxDataSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secap_tx_data::R`](R) reader structure"]
impl crate :: Readable for SecapTxDataSpec { } # [doc = "`write(|w| ..)` method takes [`secap_tx_data::W`](W) writer structure"]
impl crate :: Writable for SecapTxDataSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECAP_TX_DATA to value 0"]
impl crate :: Resettable for SecapTxDataSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECAP_TX_CONTROL (rw) register accessor: SECAP_TX_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_tx_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_tx_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secap_tx_control`]
module"]
# [doc (alias = "SECAP_TX_CONTROL")]
pub type SecapTxControl = crate :: Reg < secap_tx_control :: SecapTxControlSpec > ; # [doc = "SECAP_TX_CONTROL"]
pub mod secap_tx_control { # [doc = "Register `SECAP_TX_CONTROL` reader"]
pub type R = crate :: R < SecapTxControlSpec > ; # [doc = "Register `SECAP_TX_CONTROL` writer"]
pub type W = crate :: W < SecapTxControlSpec > ; # [doc = "Field `JTAGTXCONTROL` reader - 30:0\\]
This register is provides the handshake for the JTAGTXDATA Register and can also be used to pass control information to the system security logic."]
pub type JtagtxcontrolR = crate :: FieldReader < u32 > ; # [doc = "Field `JTAGTXCONTROL` writer - 30:0\\]
This register is provides the handshake for the JTAGTXDATA Register and can also be used to pass control information to the system security logic."]
pub type JtagtxcontrolW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; # [doc = "Field `TXDATA_AVAIL` reader - 31:31\\]
Tx Interrupt to indicate avaliablity of TXDATA . 1 - TXDATA available ; 0 - TXDATA not available"]
pub type TxdataAvailR = crate :: BitReader ; # [doc = "Field `TXDATA_AVAIL` writer - 31:31\\]
Tx Interrupt to indicate avaliablity of TXDATA . 1 - TXDATA available ; 0 - TXDATA not available"]
pub type TxdataAvailW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:30 - 30:0\\]
This register is provides the handshake for the JTAGTXDATA Register and can also be used to pass control information to the system security logic."]
# [inline (always)]
pub fn jtagtxcontrol (& self) -> JtagtxcontrolR { JtagtxcontrolR :: new (self . bits & 0x7fff_ffff) } # [doc = "Bit 31 - 31:31\\]
Tx Interrupt to indicate avaliablity of TXDATA . 1 - TXDATA available ; 0 - TXDATA not available"]
# [inline (always)]
pub fn txdata_avail (& self) -> TxdataAvailR { TxdataAvailR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:30 - 30:0\\]
This register is provides the handshake for the JTAGTXDATA Register and can also be used to pass control information to the system security logic."]
# [inline (always)]
# [must_use]
pub fn jtagtxcontrol (& mut self) -> JtagtxcontrolW < SecapTxControlSpec > { JtagtxcontrolW :: new (self , 0) } # [doc = "Bit 31 - 31:31\\]
Tx Interrupt to indicate avaliablity of TXDATA . 1 - TXDATA available ; 0 - TXDATA not available"]
# [inline (always)]
# [must_use]
pub fn txdata_avail (& mut self) -> TxdataAvailW < SecapTxControlSpec > { TxdataAvailW :: new (self , 31) } } # [doc = "SECAP_TX_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_tx_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_tx_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecapTxControlSpec ; impl crate :: RegisterSpec for SecapTxControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secap_tx_control::R`](R) reader structure"]
impl crate :: Readable for SecapTxControlSpec { } # [doc = "`write(|w| ..)` method takes [`secap_tx_control::W`](W) writer structure"]
impl crate :: Writable for SecapTxControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECAP_TX_CONTROL to value 0"]
impl crate :: Resettable for SecapTxControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECAP_RX_DATA (rw) register accessor: SECAP_RX_DATA\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_rx_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_rx_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secap_rx_data`]
module"]
# [doc (alias = "SECAP_RX_DATA")]
pub type SecapRxData = crate :: Reg < secap_rx_data :: SecapRxDataSpec > ; # [doc = "SECAP_RX_DATA"]
pub mod secap_rx_data { # [doc = "Register `SECAP_RX_DATA` reader"]
pub type R = crate :: R < SecapRxDataSpec > ; # [doc = "Register `SECAP_RX_DATA` writer"]
pub type W = crate :: W < SecapRxDataSpec > ; # [doc = "Field `JTAGRXDATA` reader - 31:0\\]
This register is used to pass data from the system security logic. The data is transmit from the SECAP interface to external JTAG interface and hence is the Tx path for the SECAP interface."]
pub type JtagrxdataR = crate :: FieldReader < u32 > ; # [doc = "Field `JTAGRXDATA` writer - 31:0\\]
This register is used to pass data from the system security logic. The data is transmit from the SECAP interface to external JTAG interface and hence is the Tx path for the SECAP interface."]
pub type JtagrxdataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
This register is used to pass data from the system security logic. The data is transmit from the SECAP interface to external JTAG interface and hence is the Tx path for the SECAP interface."]
# [inline (always)]
pub fn jtagrxdata (& self) -> JtagrxdataR { JtagrxdataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
This register is used to pass data from the system security logic. The data is transmit from the SECAP interface to external JTAG interface and hence is the Tx path for the SECAP interface."]
# [inline (always)]
# [must_use]
pub fn jtagrxdata (& mut self) -> JtagrxdataW < SecapRxDataSpec > { JtagrxdataW :: new (self , 0) } } # [doc = "SECAP_RX_DATA\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_rx_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_rx_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecapRxDataSpec ; impl crate :: RegisterSpec for SecapRxDataSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secap_rx_data::R`](R) reader structure"]
impl crate :: Readable for SecapRxDataSpec { } # [doc = "`write(|w| ..)` method takes [`secap_rx_data::W`](W) writer structure"]
impl crate :: Writable for SecapRxDataSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECAP_RX_DATA to value 0"]
impl crate :: Resettable for SecapRxDataSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SECAP_RX_CONTROL (rw) register accessor: SECAP_RX_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_rx_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_rx_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secap_rx_control`]
module"]
# [doc (alias = "SECAP_RX_CONTROL")]
pub type SecapRxControl = crate :: Reg < secap_rx_control :: SecapRxControlSpec > ; # [doc = "SECAP_RX_CONTROL"]
pub mod secap_rx_control { # [doc = "Register `SECAP_RX_CONTROL` reader"]
pub type R = crate :: R < SecapRxControlSpec > ; # [doc = "Register `SECAP_RX_CONTROL` writer"]
pub type W = crate :: W < SecapRxControlSpec > ; # [doc = "Field `JTAGRXCONTROL` reader - 30:0\\]
This register is provides the handshake for the JTAGRXDATA Register and can also be used to pass control information from the system security logic"]
pub type JtagrxcontrolR = crate :: FieldReader < u32 > ; # [doc = "Field `JTAGRXCONTROL` writer - 30:0\\]
This register is provides the handshake for the JTAGRXDATA Register and can also be used to pass control information from the system security logic"]
pub type JtagrxcontrolW < 'a , REG > = crate :: FieldWriter < 'a , REG , 31 , u32 > ; # [doc = "Field `RXDATA_AVAIL` reader - 31:31\\]
Tx Interrupt to indicate avaliablity of RXDATA . 1 - RXDATA available ; 0 - RXDATA not available"]
pub type RxdataAvailR = crate :: BitReader ; # [doc = "Field `RXDATA_AVAIL` writer - 31:31\\]
Tx Interrupt to indicate avaliablity of RXDATA . 1 - RXDATA available ; 0 - RXDATA not available"]
pub type RxdataAvailW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:30 - 30:0\\]
This register is provides the handshake for the JTAGRXDATA Register and can also be used to pass control information from the system security logic"]
# [inline (always)]
pub fn jtagrxcontrol (& self) -> JtagrxcontrolR { JtagrxcontrolR :: new (self . bits & 0x7fff_ffff) } # [doc = "Bit 31 - 31:31\\]
Tx Interrupt to indicate avaliablity of RXDATA . 1 - RXDATA available ; 0 - RXDATA not available"]
# [inline (always)]
pub fn rxdata_avail (& self) -> RxdataAvailR { RxdataAvailR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:30 - 30:0\\]
This register is provides the handshake for the JTAGRXDATA Register and can also be used to pass control information from the system security logic"]
# [inline (always)]
# [must_use]
pub fn jtagrxcontrol (& mut self) -> JtagrxcontrolW < SecapRxControlSpec > { JtagrxcontrolW :: new (self , 0) } # [doc = "Bit 31 - 31:31\\]
Tx Interrupt to indicate avaliablity of RXDATA . 1 - RXDATA available ; 0 - RXDATA not available"]
# [inline (always)]
# [must_use]
pub fn rxdata_avail (& mut self) -> RxdataAvailW < SecapRxControlSpec > { RxdataAvailW :: new (self , 31) } } # [doc = "SECAP_RX_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`secap_rx_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`secap_rx_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SecapRxControlSpec ; impl crate :: RegisterSpec for SecapRxControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`secap_rx_control::R`](R) reader structure"]
impl crate :: Readable for SecapRxControlSpec { } # [doc = "`write(|w| ..)` method takes [`secap_rx_control::W`](W) writer structure"]
impl crate :: Writable for SecapRxControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SECAP_RX_CONTROL to value 0"]
impl crate :: Resettable for SecapRxControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "dft_proc_dmled_exec (rw) register accessor: dft_proc_dmled_exec\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_proc_dmled_exec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_proc_dmled_exec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_proc_dmled_exec`]
module"]
# [doc (alias = "dft_proc_dmled_exec")]
pub type DftProcDmledExec = crate :: Reg < dft_proc_dmled_exec :: DftProcDmledExecSpec > ; # [doc = "dft_proc_dmled_exec"]
pub mod dft_proc_dmled_exec { # [doc = "Register `dft_proc_dmled_exec` reader"]
pub type R = crate :: R < DftProcDmledExecSpec > ; # [doc = "Register `dft_proc_dmled_exec` writer"]
pub type W = crate :: W < DftProcDmledExecSpec > ; # [doc = "Field `cm4_exec` reader - 2:0\\]
dft_proc_dmled_cm4_exec"]
pub type Cm4ExecR = crate :: FieldReader ; # [doc = "Field `cm4_exec` writer - 2:0\\]
dft_proc_dmled_cm4_exec"]
pub type Cm4ExecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cm3_exec` reader - 5:3\\]
dft_proc_dmled_cm3_exec"]
pub type Cm3ExecR = crate :: FieldReader ; # [doc = "Field `cm3_exec` writer - 5:3\\]
dft_proc_dmled_cm3_exec"]
pub type Cm3ExecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `obs_exec` reader - 8:6\\]
dft_proc_dmled_obs_exec"]
pub type ObsExecR = crate :: FieldReader ; # [doc = "Field `obs_exec` writer - 8:6\\]
dft_proc_dmled_obs_exec"]
pub type ObsExecW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cm4_status` reader - 11:9\\]
dft_proc_dmled_cm4_status"]
pub type Cm4StatusR = crate :: FieldReader ; # [doc = "Field `cm4_status` writer - 11:9\\]
dft_proc_dmled_cm4_status"]
pub type Cm4StatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cm3_status` reader - 14:12\\]
dft_proc_dmled_cm3_status"]
pub type Cm3StatusR = crate :: FieldReader ; # [doc = "Field `cm3_status` writer - 14:12\\]
dft_proc_dmled_cm3_status"]
pub type Cm3StatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `obs_status` reader - 17:15\\]
dft_proc_dmled_obs_status"]
pub type ObsStatusR = crate :: FieldReader ; # [doc = "Field `obs_status` writer - 17:15\\]
dft_proc_dmled_obs_status"]
pub type ObsStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
dft_proc_dmled_cm4_exec"]
# [inline (always)]
pub fn cm4_exec (& self) -> Cm4ExecR { Cm4ExecR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
dft_proc_dmled_cm3_exec"]
# [inline (always)]
pub fn cm3_exec (& self) -> Cm3ExecR { Cm3ExecR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
dft_proc_dmled_obs_exec"]
# [inline (always)]
pub fn obs_exec (& self) -> ObsExecR { ObsExecR :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
dft_proc_dmled_cm4_status"]
# [inline (always)]
pub fn cm4_status (& self) -> Cm4StatusR { Cm4StatusR :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
dft_proc_dmled_cm3_status"]
# [inline (always)]
pub fn cm3_status (& self) -> Cm3StatusR { Cm3StatusR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
dft_proc_dmled_obs_status"]
# [inline (always)]
pub fn obs_status (& self) -> ObsStatusR { ObsStatusR :: new (((self . bits >> 15) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
dft_proc_dmled_cm4_exec"]
# [inline (always)]
# [must_use]
pub fn cm4_exec (& mut self) -> Cm4ExecW < DftProcDmledExecSpec > { Cm4ExecW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
dft_proc_dmled_cm3_exec"]
# [inline (always)]
# [must_use]
pub fn cm3_exec (& mut self) -> Cm3ExecW < DftProcDmledExecSpec > { Cm3ExecW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
dft_proc_dmled_obs_exec"]
# [inline (always)]
# [must_use]
pub fn obs_exec (& mut self) -> ObsExecW < DftProcDmledExecSpec > { ObsExecW :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
dft_proc_dmled_cm4_status"]
# [inline (always)]
# [must_use]
pub fn cm4_status (& mut self) -> Cm4StatusW < DftProcDmledExecSpec > { Cm4StatusW :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
dft_proc_dmled_cm3_status"]
# [inline (always)]
# [must_use]
pub fn cm3_status (& mut self) -> Cm3StatusW < DftProcDmledExecSpec > { Cm3StatusW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
dft_proc_dmled_obs_status"]
# [inline (always)]
# [must_use]
pub fn obs_status (& mut self) -> ObsStatusW < DftProcDmledExecSpec > { ObsStatusW :: new (self , 15) } } # [doc = "dft_proc_dmled_exec\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_proc_dmled_exec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_proc_dmled_exec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftProcDmledExecSpec ; impl crate :: RegisterSpec for DftProcDmledExecSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_proc_dmled_exec::R`](R) reader structure"]
impl crate :: Readable for DftProcDmledExecSpec { } # [doc = "`write(|w| ..)` method takes [`dft_proc_dmled_exec::W`](W) writer structure"]
impl crate :: Writable for DftProcDmledExecSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets dft_proc_dmled_exec to value 0"]
impl crate :: Resettable for DftProcDmledExecSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "dft_proc_dmled_status (rw) register accessor: dft_proc_dmled_status\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_proc_dmled_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_proc_dmled_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_proc_dmled_status`]
module"]
# [doc (alias = "dft_proc_dmled_status")]
pub type DftProcDmledStatus = crate :: Reg < dft_proc_dmled_status :: DftProcDmledStatusSpec > ; # [doc = "dft_proc_dmled_status"]
pub mod dft_proc_dmled_status { # [doc = "Register `dft_proc_dmled_status` reader"]
pub type R = crate :: R < DftProcDmledStatusSpec > ; # [doc = "Register `dft_proc_dmled_status` writer"]
pub type W = crate :: W < DftProcDmledStatusSpec > ; impl W { } # [doc = "dft_proc_dmled_status\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_proc_dmled_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_proc_dmled_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftProcDmledStatusSpec ; impl crate :: RegisterSpec for DftProcDmledStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_proc_dmled_status::R`](R) reader structure"]
impl crate :: Readable for DftProcDmledStatusSpec { } # [doc = "`write(|w| ..)` method takes [`dft_proc_dmled_status::W`](W) writer structure"]
impl crate :: Writable for DftProcDmledStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets dft_proc_dmled_status to value 0"]
impl crate :: Resettable for DftProcDmledStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "dft_config_reg (rw) register accessor: dft_config_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_config_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_config_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_config_reg`]
module"]
# [doc (alias = "dft_config_reg")]
pub type DftConfigReg = crate :: Reg < dft_config_reg :: DftConfigRegSpec > ; # [doc = "dft_config_reg"]
pub mod dft_config_reg { # [doc = "Register `dft_config_reg` reader"]
pub type R = crate :: R < DftConfigRegSpec > ; # [doc = "Register `dft_config_reg` writer"]
pub type W = crate :: W < DftConfigRegSpec > ; # [doc = "Field `ctrl` reader - 31:0\\]
bitundefined: dft_dmled_status_obs_sel"]
pub type CtrlR = crate :: FieldReader < u32 > ; # [doc = "Field `ctrl` writer - 31:0\\]
bitundefined: dft_dmled_status_obs_sel"]
pub type CtrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
bitundefined: dft_dmled_status_obs_sel"]
# [inline (always)]
pub fn ctrl (& self) -> CtrlR { CtrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
bitundefined: dft_dmled_status_obs_sel"]
# [inline (always)]
# [must_use]
pub fn ctrl (& mut self) -> CtrlW < DftConfigRegSpec > { CtrlW :: new (self , 0) } } # [doc = "dft_config_reg\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_config_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_config_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftConfigRegSpec ; impl crate :: RegisterSpec for DftConfigRegSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_config_reg::R`](R) reader structure"]
impl crate :: Readable for DftConfigRegSpec { } # [doc = "`write(|w| ..)` method takes [`dft_config_reg::W`](W) writer structure"]
impl crate :: Writable for DftConfigRegSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets dft_config_reg to value 0"]
impl crate :: Resettable for DftConfigRegSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "dft_pbist_st_key (rw) register accessor: dft_pbist_st_key\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_pbist_st_key::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_pbist_st_key::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_pbist_st_key`]
module"]
# [doc (alias = "dft_pbist_st_key")]
pub type DftPbistStKey = crate :: Reg < dft_pbist_st_key :: DftPbistStKeySpec > ; # [doc = "dft_pbist_st_key"]
pub mod dft_pbist_st_key { # [doc = "Register `dft_pbist_st_key` reader"]
pub type R = crate :: R < DftPbistStKeySpec > ; # [doc = "Register `dft_pbist_st_key` writer"]
pub type W = crate :: W < DftPbistStKeySpec > ; # [doc = "Field `reg` reader - 31:0\\]
dft_pbist_st_key"]
pub type RegR = crate :: FieldReader < u32 > ; # [doc = "Field `reg` writer - 31:0\\]
dft_pbist_st_key"]
pub type RegW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
dft_pbist_st_key"]
# [inline (always)]
pub fn reg (& self) -> RegR { RegR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
dft_pbist_st_key"]
# [inline (always)]
# [must_use]
pub fn reg (& mut self) -> RegW < DftPbistStKeySpec > { RegW :: new (self , 0) } } # [doc = "dft_pbist_st_key\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_pbist_st_key::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_pbist_st_key::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftPbistStKeySpec ; impl crate :: RegisterSpec for DftPbistStKeySpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_pbist_st_key::R`](R) reader structure"]
impl crate :: Readable for DftPbistStKeySpec { } # [doc = "`write(|w| ..)` method takes [`dft_pbist_st_key::W`](W) writer structure"]
impl crate :: Writable for DftPbistStKeySpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets dft_pbist_st_key to value 0"]
impl crate :: Resettable for DftPbistStKeySpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "dft_pbist_st_rst (rw) register accessor: dft_pbist_st_rst\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_pbist_st_rst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_pbist_st_rst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dft_pbist_st_rst`]
module"]
# [doc (alias = "dft_pbist_st_rst")]
pub type DftPbistStRst = crate :: Reg < dft_pbist_st_rst :: DftPbistStRstSpec > ; # [doc = "dft_pbist_st_rst"]
pub mod dft_pbist_st_rst { # [doc = "Register `dft_pbist_st_rst` reader"]
pub type R = crate :: R < DftPbistStRstSpec > ; # [doc = "Register `dft_pbist_st_rst` writer"]
pub type W = crate :: W < DftPbistStRstSpec > ; # [doc = "Field `reg` reader - 31:0\\]
dft_pbist_st_rst"]
pub type RegR = crate :: FieldReader < u32 > ; # [doc = "Field `reg` writer - 31:0\\]
dft_pbist_st_rst"]
pub type RegW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
dft_pbist_st_rst"]
# [inline (always)]
pub fn reg (& self) -> RegR { RegR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
dft_pbist_st_rst"]
# [inline (always)]
# [must_use]
pub fn reg (& mut self) -> RegW < DftPbistStRstSpec > { RegW :: new (self , 0) } } # [doc = "dft_pbist_st_rst\n\nYou can [`read`](crate::Reg::read) this register and get [`dft_pbist_st_rst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dft_pbist_st_rst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DftPbistStRstSpec ; impl crate :: RegisterSpec for DftPbistStRstSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`dft_pbist_st_rst::R`](R) reader structure"]
impl crate :: Readable for DftPbistStRstSpec { } # [doc = "`write(|w| ..)` method takes [`dft_pbist_st_rst::W`](W) writer structure"]
impl crate :: Writable for DftPbistStRstSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets dft_pbist_st_rst to value 0"]
impl crate :: Resettable for DftPbistStRstSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "TOP_INTMASK (rw) register accessor: TOP_INTMASK\n\nYou can [`read`](crate::Reg::read) this register and get [`top_intmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`top_intmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@top_intmask`]
module"]
# [doc (alias = "TOP_INTMASK")]
pub type TopIntmask = crate :: Reg < top_intmask :: TopIntmaskSpec > ; # [doc = "TOP_INTMASK"]
pub mod top_intmask { # [doc = "Register `TOP_INTMASK` reader"]
pub type R = crate :: R < TopIntmaskSpec > ; # [doc = "Register `TOP_INTMASK` writer"]
pub type W = crate :: W < TopIntmaskSpec > ; # [doc = "Field `set` reader - 31:0\\]
Mask Interrupt from frame timer 1 : Interrupt is Masked 0 : Interrupt is Unmasked Bit 0 - Mask Interrupts from Frame Timer Bit 31:0 - Reserved"]
pub type SetR = crate :: FieldReader < u32 > ; # [doc = "Field `set` writer - 31:0\\]
Mask Interrupt from frame timer 1 : Interrupt is Masked 0 : Interrupt is Unmasked Bit 0 - Mask Interrupts from Frame Timer Bit 31:0 - Reserved"]
pub type SetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Mask Interrupt from frame timer 1 : Interrupt is Masked 0 : Interrupt is Unmasked Bit 0 - Mask Interrupts from Frame Timer Bit 31:0 - Reserved"]
# [inline (always)]
pub fn set_ (& self) -> SetR { SetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Mask Interrupt from frame timer 1 : Interrupt is Masked 0 : Interrupt is Unmasked Bit 0 - Mask Interrupts from Frame Timer Bit 31:0 - Reserved"]
# [inline (always)]
# [must_use]
pub fn set_ (& mut self) -> SetW < TopIntmaskSpec > { SetW :: new (self , 0) } } # [doc = "TOP_INTMASK\n\nYou can [`read`](crate::Reg::read) this register and get [`top_intmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`top_intmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TopIntmaskSpec ; impl crate :: RegisterSpec for TopIntmaskSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`top_intmask::R`](R) reader structure"]
impl crate :: Readable for TopIntmaskSpec { } # [doc = "`write(|w| ..)` method takes [`top_intmask::W`](W) writer structure"]
impl crate :: Writable for TopIntmaskSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TOP_INTMASK to value 0"]
impl crate :: Resettable for TopIntmaskSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_1 (rw) register accessor: DEBUG_STATUS_AON_1\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_1`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_1")]
pub type DebugStatusAon1 = crate :: Reg < debug_status_aon_1 :: DebugStatusAon1Spec > ; # [doc = "DEBUG_STATUS_AON_1"]
pub mod debug_status_aon_1 { # [doc = "Register `DEBUG_STATUS_AON_1` reader"]
pub type R = crate :: R < DebugStatusAon1Spec > ; # [doc = "Register `DEBUG_STATUS_AON_1` writer"]
pub type W = crate :: W < DebugStatusAon1Spec > ; # [doc = "Field `sram_ldo_state` reader - 4:0\\]
status reg for sram_ldo_state"]
pub type SramLdoStateR = crate :: FieldReader ; # [doc = "Field `sram_ldo_state` writer - 4:0\\]
status reg for sram_ldo_state"]
pub type SramLdoStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `sram_ldo_en` reader - 5:5\\]
status reg for sram_ldo_en"]
pub type SramLdoEnR = crate :: BitReader ; # [doc = "Field `sram_ldo_en` writer - 5:5\\]
status reg for sram_ldo_en"]
pub type SramLdoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `sram_ka_ldo_en` reader - 6:6\\]
status reg for sram_ka_ldo_en"]
pub type SramKaLdoEnR = crate :: BitReader ; # [doc = "Field `sram_ka_ldo_en` writer - 6:6\\]
status reg for sram_ka_ldo_en"]
pub type SramKaLdoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `dig_ldo_state` reader - 10:7\\]
status reg for dig_ldo_state"]
pub type DigLdoStateR = crate :: FieldReader ; # [doc = "Field `dig_ldo_state` writer - 10:7\\]
status reg for dig_ldo_state"]
pub type DigLdoStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `dig_ldo_en` reader - 11:11\\]
status reg for dig_ldo_en"]
pub type DigLdoEnR = crate :: BitReader ; # [doc = "Field `dig_ldo_en` writer - 11:11\\]
status reg for dig_ldo_en"]
pub type DigLdoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `dig_ka_ldo_en` reader - 12:12\\]
status reg for dig_ka_ldo_en"]
pub type DigKaLdoEnR = crate :: BitReader ; # [doc = "Field `dig_ka_ldo_en` writer - 12:12\\]
status reg for dig_ka_ldo_en"]
pub type DigKaLdoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `bgap_state` reader - 16:13\\]
status reg for bgap_state"]
pub type BgapStateR = crate :: FieldReader ; # [doc = "Field `bgap_state` writer - 16:13\\]
status reg for bgap_state"]
pub type BgapStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `bgap_en` reader - 17:17\\]
status reg for bgap_en"]
pub type BgapEnR = crate :: BitReader ; # [doc = "Field `bgap_en` writer - 17:17\\]
status reg for bgap_en"]
pub type BgapEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `bgap_cap_sw_enz` reader - 18:18\\]
status reg for bgap_cap_sw_enz"]
pub type BgapCapSwEnzR = crate :: BitReader ; # [doc = "Field `bgap_cap_sw_enz` writer - 18:18\\]
status reg for bgap_cap_sw_enz"]
pub type BgapCapSwEnzW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `bgap_cap_charge_en` reader - 19:19\\]
status reg for bgap_cap_charge_en"]
pub type BgapCapChargeEnR = crate :: BitReader ; # [doc = "Field `bgap_cap_charge_en` writer - 19:19\\]
status reg for bgap_cap_charge_en"]
pub type BgapCapChargeEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `bgap_hib_cap_sw_en` reader - 20:20\\]
status reg for bgap_hib_cap_sw_en"]
pub type BgapHibCapSwEnR = crate :: BitReader ; # [doc = "Field `bgap_hib_cap_sw_en` writer - 20:20\\]
status reg for bgap_hib_cap_sw_en"]
pub type BgapHibCapSwEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `bgap_hib_ref_cap_charge_en` reader - 21:21\\]
status reg for bgap_hib_ref_cap_charge_en"]
pub type BgapHibRefCapChargeEnR = crate :: BitReader ; # [doc = "Field `bgap_hib_ref_cap_charge_en` writer - 21:21\\]
status reg for bgap_hib_ref_cap_charge_en"]
pub type BgapHibRefCapChargeEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
status reg for sram_ldo_state"]
# [inline (always)]
pub fn sram_ldo_state (& self) -> SramLdoStateR { SramLdoStateR :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 5 - 5:5\\]
status reg for sram_ldo_en"]
# [inline (always)]
pub fn sram_ldo_en (& self) -> SramLdoEnR { SramLdoEnR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
status reg for sram_ka_ldo_en"]
# [inline (always)]
pub fn sram_ka_ldo_en (& self) -> SramKaLdoEnR { SramKaLdoEnR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 7:10 - 10:7\\]
status reg for dig_ldo_state"]
# [inline (always)]
pub fn dig_ldo_state (& self) -> DigLdoStateR { DigLdoStateR :: new (((self . bits >> 7) & 0x0f) as u8) } # [doc = "Bit 11 - 11:11\\]
status reg for dig_ldo_en"]
# [inline (always)]
pub fn dig_ldo_en (& self) -> DigLdoEnR { DigLdoEnR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
status reg for dig_ka_ldo_en"]
# [inline (always)]
pub fn dig_ka_ldo_en (& self) -> DigKaLdoEnR { DigKaLdoEnR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:16 - 16:13\\]
status reg for bgap_state"]
# [inline (always)]
pub fn bgap_state (& self) -> BgapStateR { BgapStateR :: new (((self . bits >> 13) & 0x0f) as u8) } # [doc = "Bit 17 - 17:17\\]
status reg for bgap_en"]
# [inline (always)]
pub fn bgap_en (& self) -> BgapEnR { BgapEnR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
status reg for bgap_cap_sw_enz"]
# [inline (always)]
pub fn bgap_cap_sw_enz (& self) -> BgapCapSwEnzR { BgapCapSwEnzR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
status reg for bgap_cap_charge_en"]
# [inline (always)]
pub fn bgap_cap_charge_en (& self) -> BgapCapChargeEnR { BgapCapChargeEnR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
status reg for bgap_hib_cap_sw_en"]
# [inline (always)]
pub fn bgap_hib_cap_sw_en (& self) -> BgapHibCapSwEnR { BgapHibCapSwEnR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
status reg for bgap_hib_ref_cap_charge_en"]
# [inline (always)]
pub fn bgap_hib_ref_cap_charge_en (& self) -> BgapHibRefCapChargeEnR { BgapHibRefCapChargeEnR :: new (((self . bits >> 21) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
status reg for sram_ldo_state"]
# [inline (always)]
# [must_use]
pub fn sram_ldo_state (& mut self) -> SramLdoStateW < DebugStatusAon1Spec > { SramLdoStateW :: new (self , 0) } # [doc = "Bit 5 - 5:5\\]
status reg for sram_ldo_en"]
# [inline (always)]
# [must_use]
pub fn sram_ldo_en (& mut self) -> SramLdoEnW < DebugStatusAon1Spec > { SramLdoEnW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
status reg for sram_ka_ldo_en"]
# [inline (always)]
# [must_use]
pub fn sram_ka_ldo_en (& mut self) -> SramKaLdoEnW < DebugStatusAon1Spec > { SramKaLdoEnW :: new (self , 6) } # [doc = "Bits 7:10 - 10:7\\]
status reg for dig_ldo_state"]
# [inline (always)]
# [must_use]
pub fn dig_ldo_state (& mut self) -> DigLdoStateW < DebugStatusAon1Spec > { DigLdoStateW :: new (self , 7) } # [doc = "Bit 11 - 11:11\\]
status reg for dig_ldo_en"]
# [inline (always)]
# [must_use]
pub fn dig_ldo_en (& mut self) -> DigLdoEnW < DebugStatusAon1Spec > { DigLdoEnW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
status reg for dig_ka_ldo_en"]
# [inline (always)]
# [must_use]
pub fn dig_ka_ldo_en (& mut self) -> DigKaLdoEnW < DebugStatusAon1Spec > { DigKaLdoEnW :: new (self , 12) } # [doc = "Bits 13:16 - 16:13\\]
status reg for bgap_state"]
# [inline (always)]
# [must_use]
pub fn bgap_state (& mut self) -> BgapStateW < DebugStatusAon1Spec > { BgapStateW :: new (self , 13) } # [doc = "Bit 17 - 17:17\\]
status reg for bgap_en"]
# [inline (always)]
# [must_use]
pub fn bgap_en (& mut self) -> BgapEnW < DebugStatusAon1Spec > { BgapEnW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
status reg for bgap_cap_sw_enz"]
# [inline (always)]
# [must_use]
pub fn bgap_cap_sw_enz (& mut self) -> BgapCapSwEnzW < DebugStatusAon1Spec > { BgapCapSwEnzW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
status reg for bgap_cap_charge_en"]
# [inline (always)]
# [must_use]
pub fn bgap_cap_charge_en (& mut self) -> BgapCapChargeEnW < DebugStatusAon1Spec > { BgapCapChargeEnW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
status reg for bgap_hib_cap_sw_en"]
# [inline (always)]
# [must_use]
pub fn bgap_hib_cap_sw_en (& mut self) -> BgapHibCapSwEnW < DebugStatusAon1Spec > { BgapHibCapSwEnW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
status reg for bgap_hib_ref_cap_charge_en"]
# [inline (always)]
# [must_use]
pub fn bgap_hib_ref_cap_charge_en (& mut self) -> BgapHibRefCapChargeEnW < DebugStatusAon1Spec > { BgapHibRefCapChargeEnW :: new (self , 21) } } # [doc = "DEBUG_STATUS_AON_1\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon1Spec ; impl crate :: RegisterSpec for DebugStatusAon1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_1::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon1Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_1::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_1 to value 0"]
impl crate :: Resettable for DebugStatusAon1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_2 (rw) register accessor: DEBUG_STATUS_AON_2\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_2`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_2")]
pub type DebugStatusAon2 = crate :: Reg < debug_status_aon_2 :: DebugStatusAon2Spec > ; # [doc = "DEBUG_STATUS_AON_2"]
pub mod debug_status_aon_2 { # [doc = "Register `DEBUG_STATUS_AON_2` reader"]
pub type R = crate :: R < DebugStatusAon2Spec > ; # [doc = "Register `DEBUG_STATUS_AON_2` writer"]
pub type W = crate :: W < DebugStatusAon2Spec > ; # [doc = "Field `clkm_state` reader - 5:0\\]
status reg for clkm_state"]
pub type ClkmStateR = crate :: FieldReader ; # [doc = "Field `clkm_state` writer - 5:0\\]
status reg for clkm_state"]
pub type ClkmStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `clkm_xtal_det_status_in` reader - 6:6\\]
status reg for clkm_xtal_det_status_in"]
pub type ClkmXtalDetStatusInR = crate :: BitReader ; # [doc = "Field `clkm_xtal_det_status_in` writer - 6:6\\]
status reg for clkm_xtal_det_status_in"]
pub type ClkmXtalDetStatusInW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_slicer_ldo_en` reader - 7:7\\]
status reg for clkm_slicer_ldo_en"]
pub type ClkmSlicerLdoEnR = crate :: BitReader ; # [doc = "Field `clkm_slicer_ldo_en` writer - 7:7\\]
status reg for clkm_slicer_ldo_en"]
pub type ClkmSlicerLdoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_slicer_bias_en` reader - 8:8\\]
status reg for clkm_slicer_bias_en"]
pub type ClkmSlicerBiasEnR = crate :: BitReader ; # [doc = "Field `clkm_slicer_bias_en` writer - 8:8\\]
status reg for clkm_slicer_bias_en"]
pub type ClkmSlicerBiasEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_xtal_en` reader - 9:9\\]
status reg for clkm_xtal_en"]
pub type ClkmXtalEnR = crate :: BitReader ; # [doc = "Field `clkm_xtal_en` writer - 9:9\\]
status reg for clkm_xtal_en"]
pub type ClkmXtalEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_slicer_en` reader - 10:10\\]
status reg for clkm_slicer_en"]
pub type ClkmSlicerEnR = crate :: BitReader ; # [doc = "Field `clkm_slicer_en` writer - 10:10\\]
status reg for clkm_slicer_en"]
pub type ClkmSlicerEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_xtal_det_en` reader - 11:11\\]
status reg for clkm_xtal_det_en"]
pub type ClkmXtalDetEnR = crate :: BitReader ; # [doc = "Field `clkm_xtal_det_en` writer - 11:11\\]
status reg for clkm_xtal_det_en"]
pub type ClkmXtalDetEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_xtal_det_status` reader - 12:12\\]
status reg for clkm_xtal_det_status"]
pub type ClkmXtalDetStatusR = crate :: BitReader ; # [doc = "Field `clkm_xtal_det_status` writer - 12:12\\]
status reg for clkm_xtal_det_status"]
pub type ClkmXtalDetStatusW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_oscillator_clk_valid` reader - 13:13\\]
status reg for clkm_oscillator_clk_valid"]
pub type ClkmOscillatorClkValidR = crate :: BitReader ; # [doc = "Field `clkm_oscillator_clk_valid` writer - 13:13\\]
status reg for clkm_oscillator_clk_valid"]
pub type ClkmOscillatorClkValidW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_first_wake_up` reader - 14:14\\]
status reg for clkm_first_wake_up"]
pub type ClkmFirstWakeUpR = crate :: BitReader ; # [doc = "Field `clkm_first_wake_up` writer - 14:14\\]
status reg for clkm_first_wake_up"]
pub type ClkmFirstWakeUpW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_host_clk_req` reader - 15:15\\]
status reg for clkm_host_clk_req"]
pub type ClkmHostClkReqR = crate :: BitReader ; # [doc = "Field `clkm_host_clk_req` writer - 15:15\\]
status reg for clkm_host_clk_req"]
pub type ClkmHostClkReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_host_clk_req_output_en` reader - 16:16\\]
status reg for clkm_host_clk_req_output_en"]
pub type ClkmHostClkReqOutputEnR = crate :: BitReader ; # [doc = "Field `clkm_host_clk_req_output_en` writer - 16:16\\]
status reg for clkm_host_clk_req_output_en"]
pub type ClkmHostClkReqOutputEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_limp_mode` reader - 17:17\\]
status reg for clkm_limp_mode"]
pub type ClkmLimpModeR = crate :: BitReader ; # [doc = "Field `clkm_limp_mode` writer - 17:17\\]
status reg for clkm_limp_mode"]
pub type ClkmLimpModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `clkm_xtal_freq` reader - 19:18\\]
status reg for clkm_xtal_freq"]
pub type ClkmXtalFreqR = crate :: FieldReader ; # [doc = "Field `clkm_xtal_freq` writer - 19:18\\]
status reg for clkm_xtal_freq"]
pub type ClkmXtalFreqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `clkm_xt_drive` reader - 24:20\\]
status reg for clkm_xt_drive"]
pub type ClkmXtDriveR = crate :: FieldReader ; # [doc = "Field `clkm_xt_drive` writer - 24:20\\]
status reg for clkm_xt_drive"]
pub type ClkmXtDriveW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
status reg for clkm_state"]
# [inline (always)]
pub fn clkm_state (& self) -> ClkmStateR { ClkmStateR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
status reg for clkm_xtal_det_status_in"]
# [inline (always)]
pub fn clkm_xtal_det_status_in (& self) -> ClkmXtalDetStatusInR { ClkmXtalDetStatusInR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
status reg for clkm_slicer_ldo_en"]
# [inline (always)]
pub fn clkm_slicer_ldo_en (& self) -> ClkmSlicerLdoEnR { ClkmSlicerLdoEnR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
status reg for clkm_slicer_bias_en"]
# [inline (always)]
pub fn clkm_slicer_bias_en (& self) -> ClkmSlicerBiasEnR { ClkmSlicerBiasEnR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
status reg for clkm_xtal_en"]
# [inline (always)]
pub fn clkm_xtal_en (& self) -> ClkmXtalEnR { ClkmXtalEnR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
status reg for clkm_slicer_en"]
# [inline (always)]
pub fn clkm_slicer_en (& self) -> ClkmSlicerEnR { ClkmSlicerEnR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
status reg for clkm_xtal_det_en"]
# [inline (always)]
pub fn clkm_xtal_det_en (& self) -> ClkmXtalDetEnR { ClkmXtalDetEnR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
status reg for clkm_xtal_det_status"]
# [inline (always)]
pub fn clkm_xtal_det_status (& self) -> ClkmXtalDetStatusR { ClkmXtalDetStatusR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
status reg for clkm_oscillator_clk_valid"]
# [inline (always)]
pub fn clkm_oscillator_clk_valid (& self) -> ClkmOscillatorClkValidR { ClkmOscillatorClkValidR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
status reg for clkm_first_wake_up"]
# [inline (always)]
pub fn clkm_first_wake_up (& self) -> ClkmFirstWakeUpR { ClkmFirstWakeUpR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
status reg for clkm_host_clk_req"]
# [inline (always)]
pub fn clkm_host_clk_req (& self) -> ClkmHostClkReqR { ClkmHostClkReqR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
status reg for clkm_host_clk_req_output_en"]
# [inline (always)]
pub fn clkm_host_clk_req_output_en (& self) -> ClkmHostClkReqOutputEnR { ClkmHostClkReqOutputEnR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
status reg for clkm_limp_mode"]
# [inline (always)]
pub fn clkm_limp_mode (& self) -> ClkmLimpModeR { ClkmLimpModeR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:19 - 19:18\\]
status reg for clkm_xtal_freq"]
# [inline (always)]
pub fn clkm_xtal_freq (& self) -> ClkmXtalFreqR { ClkmXtalFreqR :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:24 - 24:20\\]
status reg for clkm_xt_drive"]
# [inline (always)]
pub fn clkm_xt_drive (& self) -> ClkmXtDriveR { ClkmXtDriveR :: new (((self . bits >> 20) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
status reg for clkm_state"]
# [inline (always)]
# [must_use]
pub fn clkm_state (& mut self) -> ClkmStateW < DebugStatusAon2Spec > { ClkmStateW :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
status reg for clkm_xtal_det_status_in"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_det_status_in (& mut self) -> ClkmXtalDetStatusInW < DebugStatusAon2Spec > { ClkmXtalDetStatusInW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
status reg for clkm_slicer_ldo_en"]
# [inline (always)]
# [must_use]
pub fn clkm_slicer_ldo_en (& mut self) -> ClkmSlicerLdoEnW < DebugStatusAon2Spec > { ClkmSlicerLdoEnW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
status reg for clkm_slicer_bias_en"]
# [inline (always)]
# [must_use]
pub fn clkm_slicer_bias_en (& mut self) -> ClkmSlicerBiasEnW < DebugStatusAon2Spec > { ClkmSlicerBiasEnW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
status reg for clkm_xtal_en"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_en (& mut self) -> ClkmXtalEnW < DebugStatusAon2Spec > { ClkmXtalEnW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
status reg for clkm_slicer_en"]
# [inline (always)]
# [must_use]
pub fn clkm_slicer_en (& mut self) -> ClkmSlicerEnW < DebugStatusAon2Spec > { ClkmSlicerEnW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
status reg for clkm_xtal_det_en"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_det_en (& mut self) -> ClkmXtalDetEnW < DebugStatusAon2Spec > { ClkmXtalDetEnW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
status reg for clkm_xtal_det_status"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_det_status (& mut self) -> ClkmXtalDetStatusW < DebugStatusAon2Spec > { ClkmXtalDetStatusW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
status reg for clkm_oscillator_clk_valid"]
# [inline (always)]
# [must_use]
pub fn clkm_oscillator_clk_valid (& mut self) -> ClkmOscillatorClkValidW < DebugStatusAon2Spec > { ClkmOscillatorClkValidW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
status reg for clkm_first_wake_up"]
# [inline (always)]
# [must_use]
pub fn clkm_first_wake_up (& mut self) -> ClkmFirstWakeUpW < DebugStatusAon2Spec > { ClkmFirstWakeUpW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
status reg for clkm_host_clk_req"]
# [inline (always)]
# [must_use]
pub fn clkm_host_clk_req (& mut self) -> ClkmHostClkReqW < DebugStatusAon2Spec > { ClkmHostClkReqW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
status reg for clkm_host_clk_req_output_en"]
# [inline (always)]
# [must_use]
pub fn clkm_host_clk_req_output_en (& mut self) -> ClkmHostClkReqOutputEnW < DebugStatusAon2Spec > { ClkmHostClkReqOutputEnW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
status reg for clkm_limp_mode"]
# [inline (always)]
# [must_use]
pub fn clkm_limp_mode (& mut self) -> ClkmLimpModeW < DebugStatusAon2Spec > { ClkmLimpModeW :: new (self , 17) } # [doc = "Bits 18:19 - 19:18\\]
status reg for clkm_xtal_freq"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_freq (& mut self) -> ClkmXtalFreqW < DebugStatusAon2Spec > { ClkmXtalFreqW :: new (self , 18) } # [doc = "Bits 20:24 - 24:20\\]
status reg for clkm_xt_drive"]
# [inline (always)]
# [must_use]
pub fn clkm_xt_drive (& mut self) -> ClkmXtDriveW < DebugStatusAon2Spec > { ClkmXtDriveW :: new (self , 20) } } # [doc = "DEBUG_STATUS_AON_2\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon2Spec ; impl crate :: RegisterSpec for DebugStatusAon2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_2::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon2Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_2::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_2 to value 0"]
impl crate :: Resettable for DebugStatusAon2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_3 (rw) register accessor: DEBUG_STATUS_AON_3\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_3`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_3")]
pub type DebugStatusAon3 = crate :: Reg < debug_status_aon_3 :: DebugStatusAon3Spec > ; # [doc = "DEBUG_STATUS_AON_3"]
pub mod debug_status_aon_3 { # [doc = "Register `DEBUG_STATUS_AON_3` reader"]
pub type R = crate :: R < DebugStatusAon3Spec > ; # [doc = "Register `DEBUG_STATUS_AON_3` writer"]
pub type W = crate :: W < DebugStatusAon3Spec > ; # [doc = "Field `radar_state` reader - 3:0\\]
status reg for radar_state"]
pub type RadarStateR = crate :: FieldReader ; # [doc = "Field `radar_state` writer - 3:0\\]
status reg for radar_state"]
pub type RadarStateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `wakeup_source_sleep_counter` reader - 4:4\\]
status reg for wakeup_source_sleep_counter"]
pub type WakeupSourceSleepCounterR = crate :: BitReader ; # [doc = "Field `wakeup_source_sleep_counter` writer - 4:4\\]
status reg for wakeup_source_sleep_counter"]
pub type WakeupSourceSleepCounterW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_source_uart` reader - 5:5\\]
status reg for wakeup_source_uart"]
pub type WakeupSourceUartR = crate :: BitReader ; # [doc = "Field `wakeup_source_uart` writer - 5:5\\]
status reg for wakeup_source_uart"]
pub type WakeupSourceUartW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_source_spi` reader - 6:6\\]
status reg for wakeup_source_spi"]
pub type WakeupSourceSpiR = crate :: BitReader ; # [doc = "Field `wakeup_source_spi` writer - 6:6\\]
status reg for wakeup_source_spi"]
pub type WakeupSourceSpiW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_source_gpio` reader - 7:7\\]
status reg for wakeup_source_gpio"]
pub type WakeupSourceGpioR = crate :: BitReader ; # [doc = "Field `wakeup_source_gpio` writer - 7:7\\]
status reg for wakeup_source_gpio"]
pub type WakeupSourceGpioW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_source_rtc` reader - 8:8\\]
status reg for wakeup_source_rtc"]
pub type WakeupSourceRtcR = crate :: BitReader ; # [doc = "Field `wakeup_source_rtc` writer - 8:8\\]
status reg for wakeup_source_rtc"]
pub type WakeupSourceRtcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `wakeup_source_frc` reader - 9:9\\]
status reg for wakeup_source_frc"]
pub type WakeupSourceFrcR = crate :: BitReader ; # [doc = "Field `wakeup_source_frc` writer - 9:9\\]
status reg for wakeup_source_frc"]
pub type WakeupSourceFrcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
status reg for radar_state"]
# [inline (always)]
pub fn radar_state (& self) -> RadarStateR { RadarStateR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - 4:4\\]
status reg for wakeup_source_sleep_counter"]
# [inline (always)]
pub fn wakeup_source_sleep_counter (& self) -> WakeupSourceSleepCounterR { WakeupSourceSleepCounterR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
status reg for wakeup_source_uart"]
# [inline (always)]
pub fn wakeup_source_uart (& self) -> WakeupSourceUartR { WakeupSourceUartR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
status reg for wakeup_source_spi"]
# [inline (always)]
pub fn wakeup_source_spi (& self) -> WakeupSourceSpiR { WakeupSourceSpiR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
status reg for wakeup_source_gpio"]
# [inline (always)]
pub fn wakeup_source_gpio (& self) -> WakeupSourceGpioR { WakeupSourceGpioR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
status reg for wakeup_source_rtc"]
# [inline (always)]
pub fn wakeup_source_rtc (& self) -> WakeupSourceRtcR { WakeupSourceRtcR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
status reg for wakeup_source_frc"]
# [inline (always)]
pub fn wakeup_source_frc (& self) -> WakeupSourceFrcR { WakeupSourceFrcR :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
status reg for radar_state"]
# [inline (always)]
# [must_use]
pub fn radar_state (& mut self) -> RadarStateW < DebugStatusAon3Spec > { RadarStateW :: new (self , 0) } # [doc = "Bit 4 - 4:4\\]
status reg for wakeup_source_sleep_counter"]
# [inline (always)]
# [must_use]
pub fn wakeup_source_sleep_counter (& mut self) -> WakeupSourceSleepCounterW < DebugStatusAon3Spec > { WakeupSourceSleepCounterW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
status reg for wakeup_source_uart"]
# [inline (always)]
# [must_use]
pub fn wakeup_source_uart (& mut self) -> WakeupSourceUartW < DebugStatusAon3Spec > { WakeupSourceUartW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
status reg for wakeup_source_spi"]
# [inline (always)]
# [must_use]
pub fn wakeup_source_spi (& mut self) -> WakeupSourceSpiW < DebugStatusAon3Spec > { WakeupSourceSpiW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
status reg for wakeup_source_gpio"]
# [inline (always)]
# [must_use]
pub fn wakeup_source_gpio (& mut self) -> WakeupSourceGpioW < DebugStatusAon3Spec > { WakeupSourceGpioW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
status reg for wakeup_source_rtc"]
# [inline (always)]
# [must_use]
pub fn wakeup_source_rtc (& mut self) -> WakeupSourceRtcW < DebugStatusAon3Spec > { WakeupSourceRtcW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
status reg for wakeup_source_frc"]
# [inline (always)]
# [must_use]
pub fn wakeup_source_frc (& mut self) -> WakeupSourceFrcW < DebugStatusAon3Spec > { WakeupSourceFrcW :: new (self , 9) } } # [doc = "DEBUG_STATUS_AON_3\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon3Spec ; impl crate :: RegisterSpec for DebugStatusAon3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_3::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon3Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_3::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_3 to value 0"]
impl crate :: Resettable for DebugStatusAon3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_4 (rw) register accessor: DEBUG_STATUS_AON_4\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_4`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_4")]
pub type DebugStatusAon4 = crate :: Reg < debug_status_aon_4 :: DebugStatusAon4Spec > ; # [doc = "DEBUG_STATUS_AON_4"]
pub mod debug_status_aon_4 { # [doc = "Register `DEBUG_STATUS_AON_4` reader"]
pub type R = crate :: R < DebugStatusAon4Spec > ; # [doc = "Register `DEBUG_STATUS_AON_4` writer"]
pub type W = crate :: W < DebugStatusAon4Spec > ; # [doc = "Field `app_logic_pscon_fsm` reader - 4:0\\]
status reg for app_logic_pscon_fsm"]
pub type AppLogicPsconFsmR = crate :: FieldReader ; # [doc = "Field `app_logic_pscon_fsm` writer - 4:0\\]
status reg for app_logic_pscon_fsm"]
pub type AppLogicPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `fec_logic_pscon_fsm` reader - 9:5\\]
status reg for fec_logic_pscon_fsm"]
pub type FecLogicPsconFsmR = crate :: FieldReader ; # [doc = "Field `fec_logic_pscon_fsm` writer - 9:5\\]
status reg for fec_logic_pscon_fsm"]
pub type FecLogicPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `hwa_logic_pscon_fsm` reader - 14:10\\]
status reg for hwa_logic_pscon_fsm"]
pub type HwaLogicPsconFsmR = crate :: FieldReader ; # [doc = "Field `hwa_logic_pscon_fsm` writer - 14:10\\]
status reg for hwa_logic_pscon_fsm"]
pub type HwaLogicPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `testdbg_logic_pscon_fsm` reader - 19:15\\]
status reg for testdbg_logic_pscon_fsm"]
pub type TestdbgLogicPsconFsmR = crate :: FieldReader ; # [doc = "Field `testdbg_logic_pscon_fsm` writer - 19:15\\]
status reg for testdbg_logic_pscon_fsm"]
pub type TestdbgLogicPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
status reg for app_logic_pscon_fsm"]
# [inline (always)]
pub fn app_logic_pscon_fsm (& self) -> AppLogicPsconFsmR { AppLogicPsconFsmR :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:9 - 9:5\\]
status reg for fec_logic_pscon_fsm"]
# [inline (always)]
pub fn fec_logic_pscon_fsm (& self) -> FecLogicPsconFsmR { FecLogicPsconFsmR :: new (((self . bits >> 5) & 0x1f) as u8) } # [doc = "Bits 10:14 - 14:10\\]
status reg for hwa_logic_pscon_fsm"]
# [inline (always)]
pub fn hwa_logic_pscon_fsm (& self) -> HwaLogicPsconFsmR { HwaLogicPsconFsmR :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bits 15:19 - 19:15\\]
status reg for testdbg_logic_pscon_fsm"]
# [inline (always)]
pub fn testdbg_logic_pscon_fsm (& self) -> TestdbgLogicPsconFsmR { TestdbgLogicPsconFsmR :: new (((self . bits >> 15) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
status reg for app_logic_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn app_logic_pscon_fsm (& mut self) -> AppLogicPsconFsmW < DebugStatusAon4Spec > { AppLogicPsconFsmW :: new (self , 0) } # [doc = "Bits 5:9 - 9:5\\]
status reg for fec_logic_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn fec_logic_pscon_fsm (& mut self) -> FecLogicPsconFsmW < DebugStatusAon4Spec > { FecLogicPsconFsmW :: new (self , 5) } # [doc = "Bits 10:14 - 14:10\\]
status reg for hwa_logic_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn hwa_logic_pscon_fsm (& mut self) -> HwaLogicPsconFsmW < DebugStatusAon4Spec > { HwaLogicPsconFsmW :: new (self , 10) } # [doc = "Bits 15:19 - 19:15\\]
status reg for testdbg_logic_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn testdbg_logic_pscon_fsm (& mut self) -> TestdbgLogicPsconFsmW < DebugStatusAon4Spec > { TestdbgLogicPsconFsmW :: new (self , 15) } } # [doc = "DEBUG_STATUS_AON_4\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon4Spec ; impl crate :: RegisterSpec for DebugStatusAon4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_4::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon4Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_4::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_4 to value 0"]
impl crate :: Resettable for DebugStatusAon4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_5 (rw) register accessor: DEBUG_STATUS_AON_5\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_5`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_5")]
pub type DebugStatusAon5 = crate :: Reg < debug_status_aon_5 :: DebugStatusAon5Spec > ; # [doc = "DEBUG_STATUS_AON_5"]
pub mod debug_status_aon_5 { # [doc = "Register `DEBUG_STATUS_AON_5` reader"]
pub type R = crate :: R < DebugStatusAon5Spec > ; # [doc = "Register `DEBUG_STATUS_AON_5` writer"]
pub type W = crate :: W < DebugStatusAon5Spec > ; # [doc = "Field `app_mem_pscon_fsm` reader - 3:0\\]
status reg for app_mem_pscon_fsm"]
pub type AppMemPsconFsmR = crate :: FieldReader ; # [doc = "Field `app_mem_pscon_fsm` writer - 3:0\\]
status reg for app_mem_pscon_fsm"]
pub type AppMemPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `app_grp1_mem_pscon_fsm` reader - 7:4\\]
status reg for app_grp1_mem_pscon_fsm"]
pub type AppGrp1MemPsconFsmR = crate :: FieldReader ; # [doc = "Field `app_grp1_mem_pscon_fsm` writer - 7:4\\]
status reg for app_grp1_mem_pscon_fsm"]
pub type AppGrp1MemPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `app_grp2_mem_pscon_fsm` reader - 11:8\\]
status reg for app_grp2_mem_pscon_fsm"]
pub type AppGrp2MemPsconFsmR = crate :: FieldReader ; # [doc = "Field `app_grp2_mem_pscon_fsm` writer - 11:8\\]
status reg for app_grp2_mem_pscon_fsm"]
pub type AppGrp2MemPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `hwa_grp3_mem_pscon_fsm` reader - 15:12\\]
status reg for hwa_grp3_mem_pscon_fsm"]
pub type HwaGrp3MemPsconFsmR = crate :: FieldReader ; # [doc = "Field `hwa_grp3_mem_pscon_fsm` writer - 15:12\\]
status reg for hwa_grp3_mem_pscon_fsm"]
pub type HwaGrp3MemPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `fec_mem_pscon_fsm` reader - 19:16\\]
status reg for fec_mem_pscon_fsm"]
pub type FecMemPsconFsmR = crate :: FieldReader ; # [doc = "Field `fec_mem_pscon_fsm` writer - 19:16\\]
status reg for fec_mem_pscon_fsm"]
pub type FecMemPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `fec_grp4mem_pscon_fsm` reader - 23:20\\]
status reg for fec_grp4mem_pscon_fsm"]
pub type FecGrp4memPsconFsmR = crate :: FieldReader ; # [doc = "Field `fec_grp4mem_pscon_fsm` writer - 23:20\\]
status reg for fec_grp4mem_pscon_fsm"]
pub type FecGrp4memPsconFsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
status reg for app_mem_pscon_fsm"]
# [inline (always)]
pub fn app_mem_pscon_fsm (& self) -> AppMemPsconFsmR { AppMemPsconFsmR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - 7:4\\]
status reg for app_grp1_mem_pscon_fsm"]
# [inline (always)]
pub fn app_grp1_mem_pscon_fsm (& self) -> AppGrp1MemPsconFsmR { AppGrp1MemPsconFsmR :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - 11:8\\]
status reg for app_grp2_mem_pscon_fsm"]
# [inline (always)]
pub fn app_grp2_mem_pscon_fsm (& self) -> AppGrp2MemPsconFsmR { AppGrp2MemPsconFsmR :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - 15:12\\]
status reg for hwa_grp3_mem_pscon_fsm"]
# [inline (always)]
pub fn hwa_grp3_mem_pscon_fsm (& self) -> HwaGrp3MemPsconFsmR { HwaGrp3MemPsconFsmR :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:19 - 19:16\\]
status reg for fec_mem_pscon_fsm"]
# [inline (always)]
pub fn fec_mem_pscon_fsm (& self) -> FecMemPsconFsmR { FecMemPsconFsmR :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - 23:20\\]
status reg for fec_grp4mem_pscon_fsm"]
# [inline (always)]
pub fn fec_grp4mem_pscon_fsm (& self) -> FecGrp4memPsconFsmR { FecGrp4memPsconFsmR :: new (((self . bits >> 20) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
status reg for app_mem_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn app_mem_pscon_fsm (& mut self) -> AppMemPsconFsmW < DebugStatusAon5Spec > { AppMemPsconFsmW :: new (self , 0) } # [doc = "Bits 4:7 - 7:4\\]
status reg for app_grp1_mem_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn app_grp1_mem_pscon_fsm (& mut self) -> AppGrp1MemPsconFsmW < DebugStatusAon5Spec > { AppGrp1MemPsconFsmW :: new (self , 4) } # [doc = "Bits 8:11 - 11:8\\]
status reg for app_grp2_mem_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn app_grp2_mem_pscon_fsm (& mut self) -> AppGrp2MemPsconFsmW < DebugStatusAon5Spec > { AppGrp2MemPsconFsmW :: new (self , 8) } # [doc = "Bits 12:15 - 15:12\\]
status reg for hwa_grp3_mem_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn hwa_grp3_mem_pscon_fsm (& mut self) -> HwaGrp3MemPsconFsmW < DebugStatusAon5Spec > { HwaGrp3MemPsconFsmW :: new (self , 12) } # [doc = "Bits 16:19 - 19:16\\]
status reg for fec_mem_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn fec_mem_pscon_fsm (& mut self) -> FecMemPsconFsmW < DebugStatusAon5Spec > { FecMemPsconFsmW :: new (self , 16) } # [doc = "Bits 20:23 - 23:20\\]
status reg for fec_grp4mem_pscon_fsm"]
# [inline (always)]
# [must_use]
pub fn fec_grp4mem_pscon_fsm (& mut self) -> FecGrp4memPsconFsmW < DebugStatusAon5Spec > { FecGrp4memPsconFsmW :: new (self , 20) } } # [doc = "DEBUG_STATUS_AON_5\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon5Spec ; impl crate :: RegisterSpec for DebugStatusAon5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_5::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon5Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_5::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_5 to value 0"]
impl crate :: Resettable for DebugStatusAon5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_6 (rw) register accessor: DEBUG_STATUS_AON_6\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_6`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_6")]
pub type DebugStatusAon6 = crate :: Reg < debug_status_aon_6 :: DebugStatusAon6Spec > ; # [doc = "DEBUG_STATUS_AON_6"]
pub mod debug_status_aon_6 { # [doc = "Register `DEBUG_STATUS_AON_6` reader"]
pub type R = crate :: R < DebugStatusAon6Spec > ; # [doc = "Register `DEBUG_STATUS_AON_6` writer"]
pub type W = crate :: W < DebugStatusAon6Spec > ; # [doc = "Field `app_pd_is_sleep` reader - 0:0\\]
status reg for app_pd_is_sleep"]
pub type AppPdIsSleepR = crate :: BitReader ; # [doc = "Field `app_pd_is_sleep` writer - 0:0\\]
status reg for app_pd_is_sleep"]
pub type AppPdIsSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_is_sleep` reader - 1:1\\]
status reg for fec_pd_is_sleep"]
pub type FecPdIsSleepR = crate :: BitReader ; # [doc = "Field `fec_pd_is_sleep` writer - 1:1\\]
status reg for fec_pd_is_sleep"]
pub type FecPdIsSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_is_sleep` reader - 2:2\\]
status reg for hwa_pd_is_sleep"]
pub type HwaPdIsSleepR = crate :: BitReader ; # [doc = "Field `hwa_pd_is_sleep` writer - 2:2\\]
status reg for hwa_pd_is_sleep"]
pub type HwaPdIsSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_is_sleep` reader - 3:3\\]
status reg for test_dbg_pd_is_sleep"]
pub type TestDbgPdIsSleepR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_is_sleep` writer - 3:3\\]
status reg for test_dbg_pd_is_sleep"]
pub type TestDbgPdIsSleepW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_pwr_req` reader - 4:4\\]
status reg for app_pd_pwr_req"]
pub type AppPdPwrReqR = crate :: BitReader ; # [doc = "Field `app_pd_pwr_req` writer - 4:4\\]
status reg for app_pd_pwr_req"]
pub type AppPdPwrReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_pwr_req` reader - 5:5\\]
status reg for fec_pd_pwr_req"]
pub type FecPdPwrReqR = crate :: BitReader ; # [doc = "Field `fec_pd_pwr_req` writer - 5:5\\]
status reg for fec_pd_pwr_req"]
pub type FecPdPwrReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_pwr_req` reader - 6:6\\]
status reg for hwa_pd_pwr_req"]
pub type HwaPdPwrReqR = crate :: BitReader ; # [doc = "Field `hwa_pd_pwr_req` writer - 6:6\\]
status reg for hwa_pd_pwr_req"]
pub type HwaPdPwrReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_pwr_req` reader - 7:7\\]
status reg for test_dbg_pd_pwr_req"]
pub type TestDbgPdPwrReqR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_pwr_req` writer - 7:7\\]
status reg for test_dbg_pd_pwr_req"]
pub type TestDbgPdPwrReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_is_sleep"]
# [inline (always)]
pub fn app_pd_is_sleep (& self) -> AppPdIsSleepR { AppPdIsSleepR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_is_sleep"]
# [inline (always)]
pub fn fec_pd_is_sleep (& self) -> FecPdIsSleepR { FecPdIsSleepR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_is_sleep"]
# [inline (always)]
pub fn hwa_pd_is_sleep (& self) -> HwaPdIsSleepR { HwaPdIsSleepR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
status reg for test_dbg_pd_is_sleep"]
# [inline (always)]
pub fn test_dbg_pd_is_sleep (& self) -> TestDbgPdIsSleepR { TestDbgPdIsSleepR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_pwr_req"]
# [inline (always)]
pub fn app_pd_pwr_req (& self) -> AppPdPwrReqR { AppPdPwrReqR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
status reg for fec_pd_pwr_req"]
# [inline (always)]
pub fn fec_pd_pwr_req (& self) -> FecPdPwrReqR { FecPdPwrReqR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
status reg for hwa_pd_pwr_req"]
# [inline (always)]
pub fn hwa_pd_pwr_req (& self) -> HwaPdPwrReqR { HwaPdPwrReqR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
status reg for test_dbg_pd_pwr_req"]
# [inline (always)]
pub fn test_dbg_pd_pwr_req (& self) -> TestDbgPdPwrReqR { TestDbgPdPwrReqR :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_is_sleep"]
# [inline (always)]
# [must_use]
pub fn app_pd_is_sleep (& mut self) -> AppPdIsSleepW < DebugStatusAon6Spec > { AppPdIsSleepW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_is_sleep"]
# [inline (always)]
# [must_use]
pub fn fec_pd_is_sleep (& mut self) -> FecPdIsSleepW < DebugStatusAon6Spec > { FecPdIsSleepW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_is_sleep"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_is_sleep (& mut self) -> HwaPdIsSleepW < DebugStatusAon6Spec > { HwaPdIsSleepW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
status reg for test_dbg_pd_is_sleep"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_is_sleep (& mut self) -> TestDbgPdIsSleepW < DebugStatusAon6Spec > { TestDbgPdIsSleepW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_pwr_req"]
# [inline (always)]
# [must_use]
pub fn app_pd_pwr_req (& mut self) -> AppPdPwrReqW < DebugStatusAon6Spec > { AppPdPwrReqW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
status reg for fec_pd_pwr_req"]
# [inline (always)]
# [must_use]
pub fn fec_pd_pwr_req (& mut self) -> FecPdPwrReqW < DebugStatusAon6Spec > { FecPdPwrReqW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
status reg for hwa_pd_pwr_req"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_pwr_req (& mut self) -> HwaPdPwrReqW < DebugStatusAon6Spec > { HwaPdPwrReqW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
status reg for test_dbg_pd_pwr_req"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_pwr_req (& mut self) -> TestDbgPdPwrReqW < DebugStatusAon6Spec > { TestDbgPdPwrReqW :: new (self , 7) } } # [doc = "DEBUG_STATUS_AON_6\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon6Spec ; impl crate :: RegisterSpec for DebugStatusAon6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_6::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon6Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_6::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_6 to value 0"]
impl crate :: Resettable for DebugStatusAon6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_7 (rw) register accessor: DEBUG_STATUS_AON_7\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_7`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_7")]
pub type DebugStatusAon7 = crate :: Reg < debug_status_aon_7 :: DebugStatusAon7Spec > ; # [doc = "DEBUG_STATUS_AON_7"]
pub mod debug_status_aon_7 { # [doc = "Register `DEBUG_STATUS_AON_7` reader"]
pub type R = crate :: R < DebugStatusAon7Spec > ; # [doc = "Register `DEBUG_STATUS_AON_7` writer"]
pub type W = crate :: W < DebugStatusAon7Spec > ; # [doc = "Field `app_pd_iso` reader - 0:0\\]
status reg for app_pd_iso"]
pub type AppPdIsoR = crate :: BitReader ; # [doc = "Field `app_pd_iso` writer - 0:0\\]
status reg for app_pd_iso"]
pub type AppPdIsoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_iso_ram` reader - 1:1\\]
status reg for app_pd_iso_ram"]
pub type AppPdIsoRamR = crate :: BitReader ; # [doc = "Field `app_pd_iso_ram` writer - 1:1\\]
status reg for app_pd_iso_ram"]
pub type AppPdIsoRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_isoscan` reader - 2:2\\]
status reg for app_pd_isoscan"]
pub type AppPdIsoscanR = crate :: BitReader ; # [doc = "Field `app_pd_isoscan` writer - 2:2\\]
status reg for app_pd_isoscan"]
pub type AppPdIsoscanW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_ponin` reader - 3:3\\]
status reg for app_pd_ponin"]
pub type AppPdPoninR = crate :: BitReader ; # [doc = "Field `app_pd_ponin` writer - 3:3\\]
status reg for app_pd_ponin"]
pub type AppPdPoninW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_pgoodin` reader - 4:4\\]
status reg for app_pd_pgoodin"]
pub type AppPdPgoodinR = crate :: BitReader ; # [doc = "Field `app_pd_pgoodin` writer - 4:4\\]
status reg for app_pd_pgoodin"]
pub type AppPdPgoodinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_ponout` reader - 5:5\\]
status reg for app_pd_ponout"]
pub type AppPdPonoutR = crate :: BitReader ; # [doc = "Field `app_pd_ponout` writer - 5:5\\]
status reg for app_pd_ponout"]
pub type AppPdPonoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_pgoodout` reader - 6:6\\]
status reg for app_pd_pgoodout"]
pub type AppPdPgoodoutR = crate :: BitReader ; # [doc = "Field `app_pd_pgoodout` writer - 6:6\\]
status reg for app_pd_pgoodout"]
pub type AppPdPgoodoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_iso` reader - 7:7\\]
status reg for fec_pd_iso"]
pub type FecPdIsoR = crate :: BitReader ; # [doc = "Field `fec_pd_iso` writer - 7:7\\]
status reg for fec_pd_iso"]
pub type FecPdIsoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_iso_ram` reader - 8:8\\]
status reg for fec_pd_iso_ram"]
pub type FecPdIsoRamR = crate :: BitReader ; # [doc = "Field `fec_pd_iso_ram` writer - 8:8\\]
status reg for fec_pd_iso_ram"]
pub type FecPdIsoRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_isoscan` reader - 9:9\\]
status reg for fec_pd_isoscan"]
pub type FecPdIsoscanR = crate :: BitReader ; # [doc = "Field `fec_pd_isoscan` writer - 9:9\\]
status reg for fec_pd_isoscan"]
pub type FecPdIsoscanW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_ponin` reader - 10:10\\]
status reg for fec_pd_ponin"]
pub type FecPdPoninR = crate :: BitReader ; # [doc = "Field `fec_pd_ponin` writer - 10:10\\]
status reg for fec_pd_ponin"]
pub type FecPdPoninW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_pgoodin` reader - 11:11\\]
status reg for fec_pd_pgoodin"]
pub type FecPdPgoodinR = crate :: BitReader ; # [doc = "Field `fec_pd_pgoodin` writer - 11:11\\]
status reg for fec_pd_pgoodin"]
pub type FecPdPgoodinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_ponout` reader - 12:12\\]
status reg for fec_pd_ponout"]
pub type FecPdPonoutR = crate :: BitReader ; # [doc = "Field `fec_pd_ponout` writer - 12:12\\]
status reg for fec_pd_ponout"]
pub type FecPdPonoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_pgoodout` reader - 13:13\\]
status reg for fec_pd_pgoodout"]
pub type FecPdPgoodoutR = crate :: BitReader ; # [doc = "Field `fec_pd_pgoodout` writer - 13:13\\]
status reg for fec_pd_pgoodout"]
pub type FecPdPgoodoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_iso` reader - 14:14\\]
status reg for hwa_pd_iso"]
pub type HwaPdIsoR = crate :: BitReader ; # [doc = "Field `hwa_pd_iso` writer - 14:14\\]
status reg for hwa_pd_iso"]
pub type HwaPdIsoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_iso_ram` reader - 15:15\\]
status reg for hwa_pd_iso_ram"]
pub type HwaPdIsoRamR = crate :: BitReader ; # [doc = "Field `hwa_pd_iso_ram` writer - 15:15\\]
status reg for hwa_pd_iso_ram"]
pub type HwaPdIsoRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_isoscan` reader - 16:16\\]
status reg for hwa_pd_isoscan"]
pub type HwaPdIsoscanR = crate :: BitReader ; # [doc = "Field `hwa_pd_isoscan` writer - 16:16\\]
status reg for hwa_pd_isoscan"]
pub type HwaPdIsoscanW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_ponin` reader - 17:17\\]
status reg for hwa_pd_ponin"]
pub type HwaPdPoninR = crate :: BitReader ; # [doc = "Field `hwa_pd_ponin` writer - 17:17\\]
status reg for hwa_pd_ponin"]
pub type HwaPdPoninW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_pgoodin` reader - 18:18\\]
status reg for hwa_pd_pgoodin"]
pub type HwaPdPgoodinR = crate :: BitReader ; # [doc = "Field `hwa_pd_pgoodin` writer - 18:18\\]
status reg for hwa_pd_pgoodin"]
pub type HwaPdPgoodinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_ponout` reader - 19:19\\]
status reg for hwa_pd_ponout"]
pub type HwaPdPonoutR = crate :: BitReader ; # [doc = "Field `hwa_pd_ponout` writer - 19:19\\]
status reg for hwa_pd_ponout"]
pub type HwaPdPonoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_pgoodout` reader - 20:20\\]
status reg for hwa_pd_pgoodout"]
pub type HwaPdPgoodoutR = crate :: BitReader ; # [doc = "Field `hwa_pd_pgoodout` writer - 20:20\\]
status reg for hwa_pd_pgoodout"]
pub type HwaPdPgoodoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_iso` reader - 21:21\\]
status reg for test_dbg_pd_iso"]
pub type TestDbgPdIsoR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_iso` writer - 21:21\\]
status reg for test_dbg_pd_iso"]
pub type TestDbgPdIsoW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_iso_ram` reader - 22:22\\]
status reg for test_dbg_pd_iso_ram"]
pub type TestDbgPdIsoRamR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_iso_ram` writer - 22:22\\]
status reg for test_dbg_pd_iso_ram"]
pub type TestDbgPdIsoRamW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_isoscan` reader - 23:23\\]
status reg for test_dbg_pd_isoscan"]
pub type TestDbgPdIsoscanR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_isoscan` writer - 23:23\\]
status reg for test_dbg_pd_isoscan"]
pub type TestDbgPdIsoscanW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_ponin` reader - 24:24\\]
status reg for test_dbg_pd_ponin"]
pub type TestDbgPdPoninR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_ponin` writer - 24:24\\]
status reg for test_dbg_pd_ponin"]
pub type TestDbgPdPoninW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_pgoodin` reader - 25:25\\]
status reg for test_dbg_pd_pgoodin"]
pub type TestDbgPdPgoodinR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_pgoodin` writer - 25:25\\]
status reg for test_dbg_pd_pgoodin"]
pub type TestDbgPdPgoodinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_ponout` reader - 26:26\\]
status reg for test_dbg_pd_ponout"]
pub type TestDbgPdPonoutR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_ponout` writer - 26:26\\]
status reg for test_dbg_pd_ponout"]
pub type TestDbgPdPonoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_pgoodout` reader - 27:27\\]
status reg for test_dbg_pd_pgoodout"]
pub type TestDbgPdPgoodoutR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_pgoodout` writer - 27:27\\]
status reg for test_dbg_pd_pgoodout"]
pub type TestDbgPdPgoodoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_iso"]
# [inline (always)]
pub fn app_pd_iso (& self) -> AppPdIsoR { AppPdIsoR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for app_pd_iso_ram"]
# [inline (always)]
pub fn app_pd_iso_ram (& self) -> AppPdIsoRamR { AppPdIsoRamR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for app_pd_isoscan"]
# [inline (always)]
pub fn app_pd_isoscan (& self) -> AppPdIsoscanR { AppPdIsoscanR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
status reg for app_pd_ponin"]
# [inline (always)]
pub fn app_pd_ponin (& self) -> AppPdPoninR { AppPdPoninR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_pgoodin"]
# [inline (always)]
pub fn app_pd_pgoodin (& self) -> AppPdPgoodinR { AppPdPgoodinR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
status reg for app_pd_ponout"]
# [inline (always)]
pub fn app_pd_ponout (& self) -> AppPdPonoutR { AppPdPonoutR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
status reg for app_pd_pgoodout"]
# [inline (always)]
pub fn app_pd_pgoodout (& self) -> AppPdPgoodoutR { AppPdPgoodoutR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
status reg for fec_pd_iso"]
# [inline (always)]
pub fn fec_pd_iso (& self) -> FecPdIsoR { FecPdIsoR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
status reg for fec_pd_iso_ram"]
# [inline (always)]
pub fn fec_pd_iso_ram (& self) -> FecPdIsoRamR { FecPdIsoRamR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
status reg for fec_pd_isoscan"]
# [inline (always)]
pub fn fec_pd_isoscan (& self) -> FecPdIsoscanR { FecPdIsoscanR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
status reg for fec_pd_ponin"]
# [inline (always)]
pub fn fec_pd_ponin (& self) -> FecPdPoninR { FecPdPoninR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
status reg for fec_pd_pgoodin"]
# [inline (always)]
pub fn fec_pd_pgoodin (& self) -> FecPdPgoodinR { FecPdPgoodinR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
status reg for fec_pd_ponout"]
# [inline (always)]
pub fn fec_pd_ponout (& self) -> FecPdPonoutR { FecPdPonoutR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
status reg for fec_pd_pgoodout"]
# [inline (always)]
pub fn fec_pd_pgoodout (& self) -> FecPdPgoodoutR { FecPdPgoodoutR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - 14:14\\]
status reg for hwa_pd_iso"]
# [inline (always)]
pub fn hwa_pd_iso (& self) -> HwaPdIsoR { HwaPdIsoR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
status reg for hwa_pd_iso_ram"]
# [inline (always)]
pub fn hwa_pd_iso_ram (& self) -> HwaPdIsoRamR { HwaPdIsoRamR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
status reg for hwa_pd_isoscan"]
# [inline (always)]
pub fn hwa_pd_isoscan (& self) -> HwaPdIsoscanR { HwaPdIsoscanR :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
status reg for hwa_pd_ponin"]
# [inline (always)]
pub fn hwa_pd_ponin (& self) -> HwaPdPoninR { HwaPdPoninR :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
status reg for hwa_pd_pgoodin"]
# [inline (always)]
pub fn hwa_pd_pgoodin (& self) -> HwaPdPgoodinR { HwaPdPgoodinR :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - 19:19\\]
status reg for hwa_pd_ponout"]
# [inline (always)]
pub fn hwa_pd_ponout (& self) -> HwaPdPonoutR { HwaPdPonoutR :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - 20:20\\]
status reg for hwa_pd_pgoodout"]
# [inline (always)]
pub fn hwa_pd_pgoodout (& self) -> HwaPdPgoodoutR { HwaPdPgoodoutR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
status reg for test_dbg_pd_iso"]
# [inline (always)]
pub fn test_dbg_pd_iso (& self) -> TestDbgPdIsoR { TestDbgPdIsoR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
status reg for test_dbg_pd_iso_ram"]
# [inline (always)]
pub fn test_dbg_pd_iso_ram (& self) -> TestDbgPdIsoRamR { TestDbgPdIsoRamR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
status reg for test_dbg_pd_isoscan"]
# [inline (always)]
pub fn test_dbg_pd_isoscan (& self) -> TestDbgPdIsoscanR { TestDbgPdIsoscanR :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - 24:24\\]
status reg for test_dbg_pd_ponin"]
# [inline (always)]
pub fn test_dbg_pd_ponin (& self) -> TestDbgPdPoninR { TestDbgPdPoninR :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
status reg for test_dbg_pd_pgoodin"]
# [inline (always)]
pub fn test_dbg_pd_pgoodin (& self) -> TestDbgPdPgoodinR { TestDbgPdPgoodinR :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
status reg for test_dbg_pd_ponout"]
# [inline (always)]
pub fn test_dbg_pd_ponout (& self) -> TestDbgPdPonoutR { TestDbgPdPonoutR :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - 27:27\\]
status reg for test_dbg_pd_pgoodout"]
# [inline (always)]
pub fn test_dbg_pd_pgoodout (& self) -> TestDbgPdPgoodoutR { TestDbgPdPgoodoutR :: new (((self . bits >> 27) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_iso"]
# [inline (always)]
# [must_use]
pub fn app_pd_iso (& mut self) -> AppPdIsoW < DebugStatusAon7Spec > { AppPdIsoW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for app_pd_iso_ram"]
# [inline (always)]
# [must_use]
pub fn app_pd_iso_ram (& mut self) -> AppPdIsoRamW < DebugStatusAon7Spec > { AppPdIsoRamW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for app_pd_isoscan"]
# [inline (always)]
# [must_use]
pub fn app_pd_isoscan (& mut self) -> AppPdIsoscanW < DebugStatusAon7Spec > { AppPdIsoscanW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
status reg for app_pd_ponin"]
# [inline (always)]
# [must_use]
pub fn app_pd_ponin (& mut self) -> AppPdPoninW < DebugStatusAon7Spec > { AppPdPoninW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_pgoodin"]
# [inline (always)]
# [must_use]
pub fn app_pd_pgoodin (& mut self) -> AppPdPgoodinW < DebugStatusAon7Spec > { AppPdPgoodinW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
status reg for app_pd_ponout"]
# [inline (always)]
# [must_use]
pub fn app_pd_ponout (& mut self) -> AppPdPonoutW < DebugStatusAon7Spec > { AppPdPonoutW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
status reg for app_pd_pgoodout"]
# [inline (always)]
# [must_use]
pub fn app_pd_pgoodout (& mut self) -> AppPdPgoodoutW < DebugStatusAon7Spec > { AppPdPgoodoutW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
status reg for fec_pd_iso"]
# [inline (always)]
# [must_use]
pub fn fec_pd_iso (& mut self) -> FecPdIsoW < DebugStatusAon7Spec > { FecPdIsoW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
status reg for fec_pd_iso_ram"]
# [inline (always)]
# [must_use]
pub fn fec_pd_iso_ram (& mut self) -> FecPdIsoRamW < DebugStatusAon7Spec > { FecPdIsoRamW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
status reg for fec_pd_isoscan"]
# [inline (always)]
# [must_use]
pub fn fec_pd_isoscan (& mut self) -> FecPdIsoscanW < DebugStatusAon7Spec > { FecPdIsoscanW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
status reg for fec_pd_ponin"]
# [inline (always)]
# [must_use]
pub fn fec_pd_ponin (& mut self) -> FecPdPoninW < DebugStatusAon7Spec > { FecPdPoninW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
status reg for fec_pd_pgoodin"]
# [inline (always)]
# [must_use]
pub fn fec_pd_pgoodin (& mut self) -> FecPdPgoodinW < DebugStatusAon7Spec > { FecPdPgoodinW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
status reg for fec_pd_ponout"]
# [inline (always)]
# [must_use]
pub fn fec_pd_ponout (& mut self) -> FecPdPonoutW < DebugStatusAon7Spec > { FecPdPonoutW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
status reg for fec_pd_pgoodout"]
# [inline (always)]
# [must_use]
pub fn fec_pd_pgoodout (& mut self) -> FecPdPgoodoutW < DebugStatusAon7Spec > { FecPdPgoodoutW :: new (self , 13) } # [doc = "Bit 14 - 14:14\\]
status reg for hwa_pd_iso"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_iso (& mut self) -> HwaPdIsoW < DebugStatusAon7Spec > { HwaPdIsoW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
status reg for hwa_pd_iso_ram"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_iso_ram (& mut self) -> HwaPdIsoRamW < DebugStatusAon7Spec > { HwaPdIsoRamW :: new (self , 15) } # [doc = "Bit 16 - 16:16\\]
status reg for hwa_pd_isoscan"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_isoscan (& mut self) -> HwaPdIsoscanW < DebugStatusAon7Spec > { HwaPdIsoscanW :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
status reg for hwa_pd_ponin"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_ponin (& mut self) -> HwaPdPoninW < DebugStatusAon7Spec > { HwaPdPoninW :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
status reg for hwa_pd_pgoodin"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_pgoodin (& mut self) -> HwaPdPgoodinW < DebugStatusAon7Spec > { HwaPdPgoodinW :: new (self , 18) } # [doc = "Bit 19 - 19:19\\]
status reg for hwa_pd_ponout"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_ponout (& mut self) -> HwaPdPonoutW < DebugStatusAon7Spec > { HwaPdPonoutW :: new (self , 19) } # [doc = "Bit 20 - 20:20\\]
status reg for hwa_pd_pgoodout"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_pgoodout (& mut self) -> HwaPdPgoodoutW < DebugStatusAon7Spec > { HwaPdPgoodoutW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
status reg for test_dbg_pd_iso"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_iso (& mut self) -> TestDbgPdIsoW < DebugStatusAon7Spec > { TestDbgPdIsoW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
status reg for test_dbg_pd_iso_ram"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_iso_ram (& mut self) -> TestDbgPdIsoRamW < DebugStatusAon7Spec > { TestDbgPdIsoRamW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
status reg for test_dbg_pd_isoscan"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_isoscan (& mut self) -> TestDbgPdIsoscanW < DebugStatusAon7Spec > { TestDbgPdIsoscanW :: new (self , 23) } # [doc = "Bit 24 - 24:24\\]
status reg for test_dbg_pd_ponin"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_ponin (& mut self) -> TestDbgPdPoninW < DebugStatusAon7Spec > { TestDbgPdPoninW :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
status reg for test_dbg_pd_pgoodin"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_pgoodin (& mut self) -> TestDbgPdPgoodinW < DebugStatusAon7Spec > { TestDbgPdPgoodinW :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
status reg for test_dbg_pd_ponout"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_ponout (& mut self) -> TestDbgPdPonoutW < DebugStatusAon7Spec > { TestDbgPdPonoutW :: new (self , 26) } # [doc = "Bit 27 - 27:27\\]
status reg for test_dbg_pd_pgoodout"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_pgoodout (& mut self) -> TestDbgPdPgoodoutW < DebugStatusAon7Spec > { TestDbgPdPgoodoutW :: new (self , 27) } } # [doc = "DEBUG_STATUS_AON_7\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon7Spec ; impl crate :: RegisterSpec for DebugStatusAon7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_7::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon7Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_7::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_7 to value 0"]
impl crate :: Resettable for DebugStatusAon7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_8 (rw) register accessor: DEBUG_STATUS_AON_8\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_8`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_8")]
pub type DebugStatusAon8 = crate :: Reg < debug_status_aon_8 :: DebugStatusAon8Spec > ; # [doc = "DEBUG_STATUS_AON_8"]
pub mod debug_status_aon_8 { # [doc = "Register `DEBUG_STATUS_AON_8` reader"]
pub type R = crate :: R < DebugStatusAon8Spec > ; # [doc = "Register `DEBUG_STATUS_AON_8` writer"]
pub type W = crate :: W < DebugStatusAon8Spec > ; # [doc = "Field `app_pd_mem_aonout` reader - 2:0\\]
status reg for app_pd_mem_aonout"]
pub type AppPdMemAonoutR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_aonout` writer - 2:0\\]
status reg for app_pd_mem_aonout"]
pub type AppPdMemAonoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pd_mem_agoodout` reader - 5:3\\]
status reg for app_pd_mem_agoodout"]
pub type AppPdMemAgoodoutR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_agoodout` writer - 5:3\\]
status reg for app_pd_mem_agoodout"]
pub type AppPdMemAgoodoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pd_mem_aonin` reader - 8:6\\]
status reg for app_pd_mem_aonin"]
pub type AppPdMemAoninR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_aonin` writer - 8:6\\]
status reg for app_pd_mem_aonin"]
pub type AppPdMemAoninW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pd_mem_agoodin` reader - 11:9\\]
status reg for app_pd_mem_agoodin"]
pub type AppPdMemAgoodinR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_agoodin` writer - 11:9\\]
status reg for app_pd_mem_agoodin"]
pub type AppPdMemAgoodinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pd_mem_grp1_aonout` reader - 13:12\\]
status reg for app_pd_mem_grp1_aonout"]
pub type AppPdMemGrp1AonoutR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_grp1_aonout` writer - 13:12\\]
status reg for app_pd_mem_grp1_aonout"]
pub type AppPdMemGrp1AonoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `app_pd_mem_grp1_agoodout` reader - 15:14\\]
status reg for app_pd_mem_grp1_agoodout"]
pub type AppPdMemGrp1AgoodoutR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_grp1_agoodout` writer - 15:14\\]
status reg for app_pd_mem_grp1_agoodout"]
pub type AppPdMemGrp1AgoodoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `app_pd_mem_grp1_aonin` reader - 17:16\\]
status reg for app_pd_mem_grp1_aonin"]
pub type AppPdMemGrp1AoninR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_grp1_aonin` writer - 17:16\\]
status reg for app_pd_mem_grp1_aonin"]
pub type AppPdMemGrp1AoninW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `app_pd_mem_grp1_agoodin` reader - 19:18\\]
status reg for app_pd_mem_grp1_agoodin"]
pub type AppPdMemGrp1AgoodinR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_grp1_agoodin` writer - 19:18\\]
status reg for app_pd_mem_grp1_agoodin"]
pub type AppPdMemGrp1AgoodinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `app_pd_mem_grp2_aonout` reader - 20:20\\]
status reg for app_pd_mem_grp2_aonout"]
pub type AppPdMemGrp2AonoutR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_aonout` writer - 20:20\\]
status reg for app_pd_mem_grp2_aonout"]
pub type AppPdMemGrp2AonoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_agoodout` reader - 21:21\\]
status reg for app_pd_mem_grp2_agoodout"]
pub type AppPdMemGrp2AgoodoutR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_agoodout` writer - 21:21\\]
status reg for app_pd_mem_grp2_agoodout"]
pub type AppPdMemGrp2AgoodoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_aonin` reader - 22:22\\]
status reg for app_pd_mem_grp2_aonin"]
pub type AppPdMemGrp2AoninR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_aonin` writer - 22:22\\]
status reg for app_pd_mem_grp2_aonin"]
pub type AppPdMemGrp2AoninW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_agoodin` reader - 23:23\\]
status reg for app_pd_mem_grp2_agoodin"]
pub type AppPdMemGrp2AgoodinR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_agoodin` writer - 23:23\\]
status reg for app_pd_mem_grp2_agoodin"]
pub type AppPdMemGrp2AgoodinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
status reg for app_pd_mem_aonout"]
# [inline (always)]
pub fn app_pd_mem_aonout (& self) -> AppPdMemAonoutR { AppPdMemAonoutR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
status reg for app_pd_mem_agoodout"]
# [inline (always)]
pub fn app_pd_mem_agoodout (& self) -> AppPdMemAgoodoutR { AppPdMemAgoodoutR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
status reg for app_pd_mem_aonin"]
# [inline (always)]
pub fn app_pd_mem_aonin (& self) -> AppPdMemAoninR { AppPdMemAoninR :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
status reg for app_pd_mem_agoodin"]
# [inline (always)]
pub fn app_pd_mem_agoodin (& self) -> AppPdMemAgoodinR { AppPdMemAgoodinR :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:13 - 13:12\\]
status reg for app_pd_mem_grp1_aonout"]
# [inline (always)]
pub fn app_pd_mem_grp1_aonout (& self) -> AppPdMemGrp1AonoutR { AppPdMemGrp1AonoutR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - 15:14\\]
status reg for app_pd_mem_grp1_agoodout"]
# [inline (always)]
pub fn app_pd_mem_grp1_agoodout (& self) -> AppPdMemGrp1AgoodoutR { AppPdMemGrp1AgoodoutR :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - 17:16\\]
status reg for app_pd_mem_grp1_aonin"]
# [inline (always)]
pub fn app_pd_mem_grp1_aonin (& self) -> AppPdMemGrp1AoninR { AppPdMemGrp1AoninR :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - 19:18\\]
status reg for app_pd_mem_grp1_agoodin"]
# [inline (always)]
pub fn app_pd_mem_grp1_agoodin (& self) -> AppPdMemGrp1AgoodinR { AppPdMemGrp1AgoodinR :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bit 20 - 20:20\\]
status reg for app_pd_mem_grp2_aonout"]
# [inline (always)]
pub fn app_pd_mem_grp2_aonout (& self) -> AppPdMemGrp2AonoutR { AppPdMemGrp2AonoutR :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - 21:21\\]
status reg for app_pd_mem_grp2_agoodout"]
# [inline (always)]
pub fn app_pd_mem_grp2_agoodout (& self) -> AppPdMemGrp2AgoodoutR { AppPdMemGrp2AgoodoutR :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - 22:22\\]
status reg for app_pd_mem_grp2_aonin"]
# [inline (always)]
pub fn app_pd_mem_grp2_aonin (& self) -> AppPdMemGrp2AoninR { AppPdMemGrp2AoninR :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - 23:23\\]
status reg for app_pd_mem_grp2_agoodin"]
# [inline (always)]
pub fn app_pd_mem_grp2_agoodin (& self) -> AppPdMemGrp2AgoodinR { AppPdMemGrp2AgoodinR :: new (((self . bits >> 23) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
status reg for app_pd_mem_aonout"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_aonout (& mut self) -> AppPdMemAonoutW < DebugStatusAon8Spec > { AppPdMemAonoutW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
status reg for app_pd_mem_agoodout"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_agoodout (& mut self) -> AppPdMemAgoodoutW < DebugStatusAon8Spec > { AppPdMemAgoodoutW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
status reg for app_pd_mem_aonin"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_aonin (& mut self) -> AppPdMemAoninW < DebugStatusAon8Spec > { AppPdMemAoninW :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
status reg for app_pd_mem_agoodin"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_agoodin (& mut self) -> AppPdMemAgoodinW < DebugStatusAon8Spec > { AppPdMemAgoodinW :: new (self , 9) } # [doc = "Bits 12:13 - 13:12\\]
status reg for app_pd_mem_grp1_aonout"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_aonout (& mut self) -> AppPdMemGrp1AonoutW < DebugStatusAon8Spec > { AppPdMemGrp1AonoutW :: new (self , 12) } # [doc = "Bits 14:15 - 15:14\\]
status reg for app_pd_mem_grp1_agoodout"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_agoodout (& mut self) -> AppPdMemGrp1AgoodoutW < DebugStatusAon8Spec > { AppPdMemGrp1AgoodoutW :: new (self , 14) } # [doc = "Bits 16:17 - 17:16\\]
status reg for app_pd_mem_grp1_aonin"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_aonin (& mut self) -> AppPdMemGrp1AoninW < DebugStatusAon8Spec > { AppPdMemGrp1AoninW :: new (self , 16) } # [doc = "Bits 18:19 - 19:18\\]
status reg for app_pd_mem_grp1_agoodin"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_agoodin (& mut self) -> AppPdMemGrp1AgoodinW < DebugStatusAon8Spec > { AppPdMemGrp1AgoodinW :: new (self , 18) } # [doc = "Bit 20 - 20:20\\]
status reg for app_pd_mem_grp2_aonout"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_aonout (& mut self) -> AppPdMemGrp2AonoutW < DebugStatusAon8Spec > { AppPdMemGrp2AonoutW :: new (self , 20) } # [doc = "Bit 21 - 21:21\\]
status reg for app_pd_mem_grp2_agoodout"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_agoodout (& mut self) -> AppPdMemGrp2AgoodoutW < DebugStatusAon8Spec > { AppPdMemGrp2AgoodoutW :: new (self , 21) } # [doc = "Bit 22 - 22:22\\]
status reg for app_pd_mem_grp2_aonin"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_aonin (& mut self) -> AppPdMemGrp2AoninW < DebugStatusAon8Spec > { AppPdMemGrp2AoninW :: new (self , 22) } # [doc = "Bit 23 - 23:23\\]
status reg for app_pd_mem_grp2_agoodin"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_agoodin (& mut self) -> AppPdMemGrp2AgoodinW < DebugStatusAon8Spec > { AppPdMemGrp2AgoodinW :: new (self , 23) } } # [doc = "DEBUG_STATUS_AON_8\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon8Spec ; impl crate :: RegisterSpec for DebugStatusAon8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_8::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon8Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_8::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_8 to value 0"]
impl crate :: Resettable for DebugStatusAon8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_9 (rw) register accessor: DEBUG_STATUS_AON_9\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_9`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_9")]
pub type DebugStatusAon9 = crate :: Reg < debug_status_aon_9 :: DebugStatusAon9Spec > ; # [doc = "DEBUG_STATUS_AON_9"]
pub mod debug_status_aon_9 { # [doc = "Register `DEBUG_STATUS_AON_9` reader"]
pub type R = crate :: R < DebugStatusAon9Spec > ; # [doc = "Register `DEBUG_STATUS_AON_9` writer"]
pub type W = crate :: W < DebugStatusAon9Spec > ; # [doc = "Field `app_pd_mem_dftrtaon` reader - 2:0\\]
status reg for app_pd_mem_dftrtaon"]
pub type AppPdMemDftrtaonR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_dftrtaon` writer - 2:0\\]
status reg for app_pd_mem_dftrtaon"]
pub type AppPdMemDftrtaonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pd_mem_dftrtagood` reader - 5:3\\]
status reg for app_pd_mem_dftrtagood"]
pub type AppPdMemDftrtagoodR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_dftrtagood` writer - 5:3\\]
status reg for app_pd_mem_dftrtagood"]
pub type AppPdMemDftrtagoodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `app_pd_mem_grp1_dftrtaon` reader - 7:6\\]
status reg for app_pd_mem_grp1_dftrtaon"]
pub type AppPdMemGrp1DftrtaonR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_grp1_dftrtaon` writer - 7:6\\]
status reg for app_pd_mem_grp1_dftrtaon"]
pub type AppPdMemGrp1DftrtaonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `app_pd_mem_grp1_dftrtagood` reader - 9:8\\]
status reg for app_pd_mem_grp1_dftrtagood"]
pub type AppPdMemGrp1DftrtagoodR = crate :: FieldReader ; # [doc = "Field `app_pd_mem_grp1_dftrtagood` writer - 9:8\\]
status reg for app_pd_mem_grp1_dftrtagood"]
pub type AppPdMemGrp1DftrtagoodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `app_pd_mem_grp2_dftrtaon` reader - 10:10\\]
status reg for app_pd_mem_grp2_dftrtaon"]
pub type AppPdMemGrp2DftrtaonR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_dftrtaon` writer - 10:10\\]
status reg for app_pd_mem_grp2_dftrtaon"]
pub type AppPdMemGrp2DftrtaonW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_dftrtagood` reader - 11:11\\]
status reg for app_pd_mem_grp2_dftrtagood"]
pub type AppPdMemGrp2DftrtagoodR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_dftrtagood` writer - 11:11\\]
status reg for app_pd_mem_grp2_dftrtagood"]
pub type AppPdMemGrp2DftrtagoodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
status reg for app_pd_mem_dftrtaon"]
# [inline (always)]
pub fn app_pd_mem_dftrtaon (& self) -> AppPdMemDftrtaonR { AppPdMemDftrtaonR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
status reg for app_pd_mem_dftrtagood"]
# [inline (always)]
pub fn app_pd_mem_dftrtagood (& self) -> AppPdMemDftrtagoodR { AppPdMemDftrtagoodR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:7 - 7:6\\]
status reg for app_pd_mem_grp1_dftrtaon"]
# [inline (always)]
pub fn app_pd_mem_grp1_dftrtaon (& self) -> AppPdMemGrp1DftrtaonR { AppPdMemGrp1DftrtaonR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
status reg for app_pd_mem_grp1_dftrtagood"]
# [inline (always)]
pub fn app_pd_mem_grp1_dftrtagood (& self) -> AppPdMemGrp1DftrtagoodR { AppPdMemGrp1DftrtagoodR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - 10:10\\]
status reg for app_pd_mem_grp2_dftrtaon"]
# [inline (always)]
pub fn app_pd_mem_grp2_dftrtaon (& self) -> AppPdMemGrp2DftrtaonR { AppPdMemGrp2DftrtaonR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
status reg for app_pd_mem_grp2_dftrtagood"]
# [inline (always)]
pub fn app_pd_mem_grp2_dftrtagood (& self) -> AppPdMemGrp2DftrtagoodR { AppPdMemGrp2DftrtagoodR :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
status reg for app_pd_mem_dftrtaon"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_dftrtaon (& mut self) -> AppPdMemDftrtaonW < DebugStatusAon9Spec > { AppPdMemDftrtaonW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
status reg for app_pd_mem_dftrtagood"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_dftrtagood (& mut self) -> AppPdMemDftrtagoodW < DebugStatusAon9Spec > { AppPdMemDftrtagoodW :: new (self , 3) } # [doc = "Bits 6:7 - 7:6\\]
status reg for app_pd_mem_grp1_dftrtaon"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_dftrtaon (& mut self) -> AppPdMemGrp1DftrtaonW < DebugStatusAon9Spec > { AppPdMemGrp1DftrtaonW :: new (self , 6) } # [doc = "Bits 8:9 - 9:8\\]
status reg for app_pd_mem_grp1_dftrtagood"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_dftrtagood (& mut self) -> AppPdMemGrp1DftrtagoodW < DebugStatusAon9Spec > { AppPdMemGrp1DftrtagoodW :: new (self , 8) } # [doc = "Bit 10 - 10:10\\]
status reg for app_pd_mem_grp2_dftrtaon"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_dftrtaon (& mut self) -> AppPdMemGrp2DftrtaonW < DebugStatusAon9Spec > { AppPdMemGrp2DftrtaonW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
status reg for app_pd_mem_grp2_dftrtagood"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_dftrtagood (& mut self) -> AppPdMemGrp2DftrtagoodW < DebugStatusAon9Spec > { AppPdMemGrp2DftrtagoodW :: new (self , 11) } } # [doc = "DEBUG_STATUS_AON_9\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon9Spec ; impl crate :: RegisterSpec for DebugStatusAon9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_9::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon9Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_9::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_9 to value 0"]
impl crate :: Resettable for DebugStatusAon9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_10 (rw) register accessor: DEBUG_STATUS_AON_10\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_10`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_10")]
pub type DebugStatusAon10 = crate :: Reg < debug_status_aon_10 :: DebugStatusAon10Spec > ; # [doc = "DEBUG_STATUS_AON_10"]
pub mod debug_status_aon_10 { # [doc = "Register `DEBUG_STATUS_AON_10` reader"]
pub type R = crate :: R < DebugStatusAon10Spec > ; # [doc = "Register `DEBUG_STATUS_AON_10` writer"]
pub type W = crate :: W < DebugStatusAon10Spec > ; # [doc = "Field `hwa_pd_mem_grp3_aonout` reader - 2:0\\]
status reg for hwa_pd_mem_grp3_aonout"]
pub type HwaPdMemGrp3AonoutR = crate :: FieldReader ; # [doc = "Field `hwa_pd_mem_grp3_aonout` writer - 2:0\\]
status reg for hwa_pd_mem_grp3_aonout"]
pub type HwaPdMemGrp3AonoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `hwa_pd_mem_grp3_agoodout` reader - 5:3\\]
status reg for hwa_pd_mem_grp3_agoodout"]
pub type HwaPdMemGrp3AgoodoutR = crate :: FieldReader ; # [doc = "Field `hwa_pd_mem_grp3_agoodout` writer - 5:3\\]
status reg for hwa_pd_mem_grp3_agoodout"]
pub type HwaPdMemGrp3AgoodoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `hwa_pd_mem_grp3_aonin` reader - 8:6\\]
status reg for hwa_pd_mem_grp3_aonin"]
pub type HwaPdMemGrp3AoninR = crate :: FieldReader ; # [doc = "Field `hwa_pd_mem_grp3_aonin` writer - 8:6\\]
status reg for hwa_pd_mem_grp3_aonin"]
pub type HwaPdMemGrp3AoninW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `hwa_pd_mem_grp3_agoodin` reader - 11:9\\]
status reg for hwa_pd_mem_grp3_agoodin"]
pub type HwaPdMemGrp3AgoodinR = crate :: FieldReader ; # [doc = "Field `hwa_pd_mem_grp3_agoodin` writer - 11:9\\]
status reg for hwa_pd_mem_grp3_agoodin"]
pub type HwaPdMemGrp3AgoodinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `hwa_pd_mem_grp3_dftrtaon` reader - 14:12\\]
status reg for hwa_pd_mem_grp3_dftrtaon"]
pub type HwaPdMemGrp3DftrtaonR = crate :: FieldReader ; # [doc = "Field `hwa_pd_mem_grp3_dftrtaon` writer - 14:12\\]
status reg for hwa_pd_mem_grp3_dftrtaon"]
pub type HwaPdMemGrp3DftrtaonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `hwa_pd_mem_grp3_dftrtagood` reader - 17:15\\]
status reg for hwa_pd_mem_grp3_dftrtagood"]
pub type HwaPdMemGrp3DftrtagoodR = crate :: FieldReader ; # [doc = "Field `hwa_pd_mem_grp3_dftrtagood` writer - 17:15\\]
status reg for hwa_pd_mem_grp3_dftrtagood"]
pub type HwaPdMemGrp3DftrtagoodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
status reg for hwa_pd_mem_grp3_aonout"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_aonout (& self) -> HwaPdMemGrp3AonoutR { HwaPdMemGrp3AonoutR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
status reg for hwa_pd_mem_grp3_agoodout"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_agoodout (& self) -> HwaPdMemGrp3AgoodoutR { HwaPdMemGrp3AgoodoutR :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - 8:6\\]
status reg for hwa_pd_mem_grp3_aonin"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_aonin (& self) -> HwaPdMemGrp3AoninR { HwaPdMemGrp3AoninR :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - 11:9\\]
status reg for hwa_pd_mem_grp3_agoodin"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_agoodin (& self) -> HwaPdMemGrp3AgoodinR { HwaPdMemGrp3AgoodinR :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - 14:12\\]
status reg for hwa_pd_mem_grp3_dftrtaon"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_dftrtaon (& self) -> HwaPdMemGrp3DftrtaonR { HwaPdMemGrp3DftrtaonR :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - 17:15\\]
status reg for hwa_pd_mem_grp3_dftrtagood"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_dftrtagood (& self) -> HwaPdMemGrp3DftrtagoodR { HwaPdMemGrp3DftrtagoodR :: new (((self . bits >> 15) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
status reg for hwa_pd_mem_grp3_aonout"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_aonout (& mut self) -> HwaPdMemGrp3AonoutW < DebugStatusAon10Spec > { HwaPdMemGrp3AonoutW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
status reg for hwa_pd_mem_grp3_agoodout"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_agoodout (& mut self) -> HwaPdMemGrp3AgoodoutW < DebugStatusAon10Spec > { HwaPdMemGrp3AgoodoutW :: new (self , 3) } # [doc = "Bits 6:8 - 8:6\\]
status reg for hwa_pd_mem_grp3_aonin"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_aonin (& mut self) -> HwaPdMemGrp3AoninW < DebugStatusAon10Spec > { HwaPdMemGrp3AoninW :: new (self , 6) } # [doc = "Bits 9:11 - 11:9\\]
status reg for hwa_pd_mem_grp3_agoodin"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_agoodin (& mut self) -> HwaPdMemGrp3AgoodinW < DebugStatusAon10Spec > { HwaPdMemGrp3AgoodinW :: new (self , 9) } # [doc = "Bits 12:14 - 14:12\\]
status reg for hwa_pd_mem_grp3_dftrtaon"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_dftrtaon (& mut self) -> HwaPdMemGrp3DftrtaonW < DebugStatusAon10Spec > { HwaPdMemGrp3DftrtaonW :: new (self , 12) } # [doc = "Bits 15:17 - 17:15\\]
status reg for hwa_pd_mem_grp3_dftrtagood"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_dftrtagood (& mut self) -> HwaPdMemGrp3DftrtagoodW < DebugStatusAon10Spec > { HwaPdMemGrp3DftrtagoodW :: new (self , 15) } } # [doc = "DEBUG_STATUS_AON_10\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon10Spec ; impl crate :: RegisterSpec for DebugStatusAon10Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_10::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon10Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_10::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon10Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_10 to value 0"]
impl crate :: Resettable for DebugStatusAon10Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_11 (rw) register accessor: DEBUG_STATUS_AON_11\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_11`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_11")]
pub type DebugStatusAon11 = crate :: Reg < debug_status_aon_11 :: DebugStatusAon11Spec > ; # [doc = "DEBUG_STATUS_AON_11"]
pub mod debug_status_aon_11 { # [doc = "Register `DEBUG_STATUS_AON_11` reader"]
pub type R = crate :: R < DebugStatusAon11Spec > ; # [doc = "Register `DEBUG_STATUS_AON_11` writer"]
pub type W = crate :: W < DebugStatusAon11Spec > ; # [doc = "Field `fec_pd_mem_aonout` reader - 0:0\\]
status reg for fec_pd_mem_aonout"]
pub type FecPdMemAonoutR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_aonout` writer - 0:0\\]
status reg for fec_pd_mem_aonout"]
pub type FecPdMemAonoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_agoodout` reader - 1:1\\]
status reg for fec_pd_mem_agoodout"]
pub type FecPdMemAgoodoutR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_agoodout` writer - 1:1\\]
status reg for fec_pd_mem_agoodout"]
pub type FecPdMemAgoodoutW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_aonin` reader - 2:2\\]
status reg for fec_pd_mem_aonin"]
pub type FecPdMemAoninR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_aonin` writer - 2:2\\]
status reg for fec_pd_mem_aonin"]
pub type FecPdMemAoninW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_agoodin` reader - 3:3\\]
status reg for fec_pd_mem_agoodin"]
pub type FecPdMemAgoodinR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_agoodin` writer - 3:3\\]
status reg for fec_pd_mem_agoodin"]
pub type FecPdMemAgoodinW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_grp4_aonout` reader - 5:4\\]
status reg for fec_pd_mem_grp4_aonout"]
pub type FecPdMemGrp4AonoutR = crate :: FieldReader ; # [doc = "Field `fec_pd_mem_grp4_aonout` writer - 5:4\\]
status reg for fec_pd_mem_grp4_aonout"]
pub type FecPdMemGrp4AonoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `fec_pd_mem_grp4_agoodout` reader - 7:6\\]
status reg for fec_pd_mem_grp4_agoodout"]
pub type FecPdMemGrp4AgoodoutR = crate :: FieldReader ; # [doc = "Field `fec_pd_mem_grp4_agoodout` writer - 7:6\\]
status reg for fec_pd_mem_grp4_agoodout"]
pub type FecPdMemGrp4AgoodoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `fec_pd_mem_grp4_aonin` reader - 9:8\\]
status reg for fec_pd_mem_grp4_aonin"]
pub type FecPdMemGrp4AoninR = crate :: FieldReader ; # [doc = "Field `fec_pd_mem_grp4_aonin` writer - 9:8\\]
status reg for fec_pd_mem_grp4_aonin"]
pub type FecPdMemGrp4AoninW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `fec_pd_mem_grp4_agoodin` reader - 11:10\\]
status reg for fec_pd_mem_grp4_agoodin"]
pub type FecPdMemGrp4AgoodinR = crate :: FieldReader ; # [doc = "Field `fec_pd_mem_grp4_agoodin` writer - 11:10\\]
status reg for fec_pd_mem_grp4_agoodin"]
pub type FecPdMemGrp4AgoodinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `fec_pd_mem_dftrtaon` reader - 12:12\\]
status reg for fec_pd_mem_dftrtaon"]
pub type FecPdMemDftrtaonR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_dftrtaon` writer - 12:12\\]
status reg for fec_pd_mem_dftrtaon"]
pub type FecPdMemDftrtaonW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_dftrtagood` reader - 13:13\\]
status reg for fec_pd_mem_dftrtagood"]
pub type FecPdMemDftrtagoodR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_dftrtagood` writer - 13:13\\]
status reg for fec_pd_mem_dftrtagood"]
pub type FecPdMemDftrtagoodW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_grp4_dftrtaon` reader - 15:14\\]
status reg for fec_pd_mem_grp4_dftrtaon"]
pub type FecPdMemGrp4DftrtaonR = crate :: FieldReader ; # [doc = "Field `fec_pd_mem_grp4_dftrtaon` writer - 15:14\\]
status reg for fec_pd_mem_grp4_dftrtaon"]
pub type FecPdMemGrp4DftrtaonW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `fec_pd_mem_grp4_dftrtagood` reader - 17:16\\]
status reg for fec_pd_mem_grp4_dftrtagood"]
pub type FecPdMemGrp4DftrtagoodR = crate :: FieldReader ; # [doc = "Field `fec_pd_mem_grp4_dftrtagood` writer - 17:16\\]
status reg for fec_pd_mem_grp4_dftrtagood"]
pub type FecPdMemGrp4DftrtagoodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for fec_pd_mem_aonout"]
# [inline (always)]
pub fn fec_pd_mem_aonout (& self) -> FecPdMemAonoutR { FecPdMemAonoutR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_mem_agoodout"]
# [inline (always)]
pub fn fec_pd_mem_agoodout (& self) -> FecPdMemAgoodoutR { FecPdMemAgoodoutR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for fec_pd_mem_aonin"]
# [inline (always)]
pub fn fec_pd_mem_aonin (& self) -> FecPdMemAoninR { FecPdMemAoninR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
status reg for fec_pd_mem_agoodin"]
# [inline (always)]
pub fn fec_pd_mem_agoodin (& self) -> FecPdMemAgoodinR { FecPdMemAgoodinR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - 5:4\\]
status reg for fec_pd_mem_grp4_aonout"]
# [inline (always)]
pub fn fec_pd_mem_grp4_aonout (& self) -> FecPdMemGrp4AonoutR { FecPdMemGrp4AonoutR :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - 7:6\\]
status reg for fec_pd_mem_grp4_agoodout"]
# [inline (always)]
pub fn fec_pd_mem_grp4_agoodout (& self) -> FecPdMemGrp4AgoodoutR { FecPdMemGrp4AgoodoutR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - 9:8\\]
status reg for fec_pd_mem_grp4_aonin"]
# [inline (always)]
pub fn fec_pd_mem_grp4_aonin (& self) -> FecPdMemGrp4AoninR { FecPdMemGrp4AoninR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
status reg for fec_pd_mem_grp4_agoodin"]
# [inline (always)]
pub fn fec_pd_mem_grp4_agoodin (& self) -> FecPdMemGrp4AgoodinR { FecPdMemGrp4AgoodinR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - 12:12\\]
status reg for fec_pd_mem_dftrtaon"]
# [inline (always)]
pub fn fec_pd_mem_dftrtaon (& self) -> FecPdMemDftrtaonR { FecPdMemDftrtaonR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
status reg for fec_pd_mem_dftrtagood"]
# [inline (always)]
pub fn fec_pd_mem_dftrtagood (& self) -> FecPdMemDftrtagoodR { FecPdMemDftrtagoodR :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bits 14:15 - 15:14\\]
status reg for fec_pd_mem_grp4_dftrtaon"]
# [inline (always)]
pub fn fec_pd_mem_grp4_dftrtaon (& self) -> FecPdMemGrp4DftrtaonR { FecPdMemGrp4DftrtaonR :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - 17:16\\]
status reg for fec_pd_mem_grp4_dftrtagood"]
# [inline (always)]
pub fn fec_pd_mem_grp4_dftrtagood (& self) -> FecPdMemGrp4DftrtagoodR { FecPdMemGrp4DftrtagoodR :: new (((self . bits >> 16) & 3) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for fec_pd_mem_aonout"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_aonout (& mut self) -> FecPdMemAonoutW < DebugStatusAon11Spec > { FecPdMemAonoutW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_mem_agoodout"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_agoodout (& mut self) -> FecPdMemAgoodoutW < DebugStatusAon11Spec > { FecPdMemAgoodoutW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for fec_pd_mem_aonin"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_aonin (& mut self) -> FecPdMemAoninW < DebugStatusAon11Spec > { FecPdMemAoninW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
status reg for fec_pd_mem_agoodin"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_agoodin (& mut self) -> FecPdMemAgoodinW < DebugStatusAon11Spec > { FecPdMemAgoodinW :: new (self , 3) } # [doc = "Bits 4:5 - 5:4\\]
status reg for fec_pd_mem_grp4_aonout"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_aonout (& mut self) -> FecPdMemGrp4AonoutW < DebugStatusAon11Spec > { FecPdMemGrp4AonoutW :: new (self , 4) } # [doc = "Bits 6:7 - 7:6\\]
status reg for fec_pd_mem_grp4_agoodout"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_agoodout (& mut self) -> FecPdMemGrp4AgoodoutW < DebugStatusAon11Spec > { FecPdMemGrp4AgoodoutW :: new (self , 6) } # [doc = "Bits 8:9 - 9:8\\]
status reg for fec_pd_mem_grp4_aonin"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_aonin (& mut self) -> FecPdMemGrp4AoninW < DebugStatusAon11Spec > { FecPdMemGrp4AoninW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
status reg for fec_pd_mem_grp4_agoodin"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_agoodin (& mut self) -> FecPdMemGrp4AgoodinW < DebugStatusAon11Spec > { FecPdMemGrp4AgoodinW :: new (self , 10) } # [doc = "Bit 12 - 12:12\\]
status reg for fec_pd_mem_dftrtaon"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_dftrtaon (& mut self) -> FecPdMemDftrtaonW < DebugStatusAon11Spec > { FecPdMemDftrtaonW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
status reg for fec_pd_mem_dftrtagood"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_dftrtagood (& mut self) -> FecPdMemDftrtagoodW < DebugStatusAon11Spec > { FecPdMemDftrtagoodW :: new (self , 13) } # [doc = "Bits 14:15 - 15:14\\]
status reg for fec_pd_mem_grp4_dftrtaon"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_dftrtaon (& mut self) -> FecPdMemGrp4DftrtaonW < DebugStatusAon11Spec > { FecPdMemGrp4DftrtaonW :: new (self , 14) } # [doc = "Bits 16:17 - 17:16\\]
status reg for fec_pd_mem_grp4_dftrtagood"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_dftrtagood (& mut self) -> FecPdMemGrp4DftrtagoodW < DebugStatusAon11Spec > { FecPdMemGrp4DftrtagoodW :: new (self , 16) } } # [doc = "DEBUG_STATUS_AON_11\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon11Spec ; impl crate :: RegisterSpec for DebugStatusAon11Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_11::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon11Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_11::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon11Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_11 to value 0"]
impl crate :: Resettable for DebugStatusAon11Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_12 (rw) register accessor: DEBUG_STATUS_AON_12\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_12`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_12")]
pub type DebugStatusAon12 = crate :: Reg < debug_status_aon_12 :: DebugStatusAon12Spec > ; # [doc = "DEBUG_STATUS_AON_12"]
pub mod debug_status_aon_12 { # [doc = "Register `DEBUG_STATUS_AON_12` reader"]
pub type R = crate :: R < DebugStatusAon12Spec > ; # [doc = "Register `DEBUG_STATUS_AON_12` writer"]
pub type W = crate :: W < DebugStatusAon12Spec > ; # [doc = "Field `app_pd_mem_grp1_highres_switch_en` reader - 0:0\\]
status reg for app_pd_mem_grp1_highres_switch_en"]
pub type AppPdMemGrp1HighresSwitchEnR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp1_highres_switch_en` writer - 0:0\\]
status reg for app_pd_mem_grp1_highres_switch_en"]
pub type AppPdMemGrp1HighresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_highres_switch_en` reader - 1:1\\]
status reg for app_pd_mem_grp2_highres_switch_en"]
pub type AppPdMemGrp2HighresSwitchEnR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_highres_switch_en` writer - 1:1\\]
status reg for app_pd_mem_grp2_highres_switch_en"]
pub type AppPdMemGrp2HighresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_mem_grp3_highres_switch_en` reader - 2:2\\]
status reg for hwa_pd_mem_grp3_highres_switch_en"]
pub type HwaPdMemGrp3HighresSwitchEnR = crate :: BitReader ; # [doc = "Field `hwa_pd_mem_grp3_highres_switch_en` writer - 2:2\\]
status reg for hwa_pd_mem_grp3_highres_switch_en"]
pub type HwaPdMemGrp3HighresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_grp4_highres_switch_en` reader - 3:3\\]
status reg for fec_pd_mem_grp4_highres_switch_en"]
pub type FecPdMemGrp4HighresSwitchEnR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_grp4_highres_switch_en` writer - 3:3\\]
status reg for fec_pd_mem_grp4_highres_switch_en"]
pub type FecPdMemGrp4HighresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp1_lowres_switch_en` reader - 4:4\\]
status reg for app_pd_mem_grp1_lowres_switch_en"]
pub type AppPdMemGrp1LowresSwitchEnR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp1_lowres_switch_en` writer - 4:4\\]
status reg for app_pd_mem_grp1_lowres_switch_en"]
pub type AppPdMemGrp1LowresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_lowres_switch_en` reader - 5:5\\]
status reg for app_pd_mem_grp2_lowres_switch_en"]
pub type AppPdMemGrp2LowresSwitchEnR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_lowres_switch_en` writer - 5:5\\]
status reg for app_pd_mem_grp2_lowres_switch_en"]
pub type AppPdMemGrp2LowresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_mem_gpr3_lowres_switch_en` reader - 6:6\\]
status reg for hwa_pd_mem_gpr3_lowres_switch_en"]
pub type HwaPdMemGpr3LowresSwitchEnR = crate :: BitReader ; # [doc = "Field `hwa_pd_mem_gpr3_lowres_switch_en` writer - 6:6\\]
status reg for hwa_pd_mem_gpr3_lowres_switch_en"]
pub type HwaPdMemGpr3LowresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_gpr4_lowres_switch_en` reader - 7:7\\]
status reg for fec_pd_mem_gpr4_lowres_switch_en"]
pub type FecPdMemGpr4LowresSwitchEnR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_gpr4_lowres_switch_en` writer - 7:7\\]
status reg for fec_pd_mem_gpr4_lowres_switch_en"]
pub type FecPdMemGpr4LowresSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp1_vnwa_switch_en` reader - 8:8\\]
status reg for app_pd_mem_grp1_vnwa_switch_en"]
pub type AppPdMemGrp1VnwaSwitchEnR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp1_vnwa_switch_en` writer - 8:8\\]
status reg for app_pd_mem_grp1_vnwa_switch_en"]
pub type AppPdMemGrp1VnwaSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_mem_grp2_vnwa_switch_en` reader - 9:9\\]
status reg for app_pd_mem_grp2_vnwa_switch_en"]
pub type AppPdMemGrp2VnwaSwitchEnR = crate :: BitReader ; # [doc = "Field `app_pd_mem_grp2_vnwa_switch_en` writer - 9:9\\]
status reg for app_pd_mem_grp2_vnwa_switch_en"]
pub type AppPdMemGrp2VnwaSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_mem_grp3_vnwa_switch_en` reader - 10:10\\]
status reg for hwa_pd_mem_grp3_vnwa_switch_en"]
pub type HwaPdMemGrp3VnwaSwitchEnR = crate :: BitReader ; # [doc = "Field `hwa_pd_mem_grp3_vnwa_switch_en` writer - 10:10\\]
status reg for hwa_pd_mem_grp3_vnwa_switch_en"]
pub type HwaPdMemGrp3VnwaSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_mem_grp4_vnwa_switch_en` reader - 11:11\\]
status reg for fec_pd_mem_grp4_vnwa_switch_en"]
pub type FecPdMemGrp4VnwaSwitchEnR = crate :: BitReader ; # [doc = "Field `fec_pd_mem_grp4_vnwa_switch_en` writer - 11:11\\]
status reg for fec_pd_mem_grp4_vnwa_switch_en"]
pub type FecPdMemGrp4VnwaSwitchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `vnwa_switch_weak_process` reader - 12:12\\]
status reg for vnwa_switch_weak_process"]
pub type VnwaSwitchWeakProcessR = crate :: BitReader ; # [doc = "Field `vnwa_switch_weak_process` writer - 12:12\\]
status reg for vnwa_switch_weak_process"]
pub type VnwaSwitchWeakProcessW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `vnwa_switch_screen_en` reader - 13:13\\]
status reg for vnwa_switch_screen_en"]
pub type VnwaSwitchScreenEnR = crate :: BitReader ; # [doc = "Field `vnwa_switch_screen_en` writer - 13:13\\]
status reg for vnwa_switch_screen_en"]
pub type VnwaSwitchScreenEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_mem_grp1_highres_switch_en"]
# [inline (always)]
pub fn app_pd_mem_grp1_highres_switch_en (& self) -> AppPdMemGrp1HighresSwitchEnR { AppPdMemGrp1HighresSwitchEnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for app_pd_mem_grp2_highres_switch_en"]
# [inline (always)]
pub fn app_pd_mem_grp2_highres_switch_en (& self) -> AppPdMemGrp2HighresSwitchEnR { AppPdMemGrp2HighresSwitchEnR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_mem_grp3_highres_switch_en"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_highres_switch_en (& self) -> HwaPdMemGrp3HighresSwitchEnR { HwaPdMemGrp3HighresSwitchEnR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
status reg for fec_pd_mem_grp4_highres_switch_en"]
# [inline (always)]
pub fn fec_pd_mem_grp4_highres_switch_en (& self) -> FecPdMemGrp4HighresSwitchEnR { FecPdMemGrp4HighresSwitchEnR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_mem_grp1_lowres_switch_en"]
# [inline (always)]
pub fn app_pd_mem_grp1_lowres_switch_en (& self) -> AppPdMemGrp1LowresSwitchEnR { AppPdMemGrp1LowresSwitchEnR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
status reg for app_pd_mem_grp2_lowres_switch_en"]
# [inline (always)]
pub fn app_pd_mem_grp2_lowres_switch_en (& self) -> AppPdMemGrp2LowresSwitchEnR { AppPdMemGrp2LowresSwitchEnR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
status reg for hwa_pd_mem_gpr3_lowres_switch_en"]
# [inline (always)]
pub fn hwa_pd_mem_gpr3_lowres_switch_en (& self) -> HwaPdMemGpr3LowresSwitchEnR { HwaPdMemGpr3LowresSwitchEnR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
status reg for fec_pd_mem_gpr4_lowres_switch_en"]
# [inline (always)]
pub fn fec_pd_mem_gpr4_lowres_switch_en (& self) -> FecPdMemGpr4LowresSwitchEnR { FecPdMemGpr4LowresSwitchEnR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
status reg for app_pd_mem_grp1_vnwa_switch_en"]
# [inline (always)]
pub fn app_pd_mem_grp1_vnwa_switch_en (& self) -> AppPdMemGrp1VnwaSwitchEnR { AppPdMemGrp1VnwaSwitchEnR :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
status reg for app_pd_mem_grp2_vnwa_switch_en"]
# [inline (always)]
pub fn app_pd_mem_grp2_vnwa_switch_en (& self) -> AppPdMemGrp2VnwaSwitchEnR { AppPdMemGrp2VnwaSwitchEnR :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
status reg for hwa_pd_mem_grp3_vnwa_switch_en"]
# [inline (always)]
pub fn hwa_pd_mem_grp3_vnwa_switch_en (& self) -> HwaPdMemGrp3VnwaSwitchEnR { HwaPdMemGrp3VnwaSwitchEnR :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - 11:11\\]
status reg for fec_pd_mem_grp4_vnwa_switch_en"]
# [inline (always)]
pub fn fec_pd_mem_grp4_vnwa_switch_en (& self) -> FecPdMemGrp4VnwaSwitchEnR { FecPdMemGrp4VnwaSwitchEnR :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - 12:12\\]
status reg for vnwa_switch_weak_process"]
# [inline (always)]
pub fn vnwa_switch_weak_process (& self) -> VnwaSwitchWeakProcessR { VnwaSwitchWeakProcessR :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - 13:13\\]
status reg for vnwa_switch_screen_en"]
# [inline (always)]
pub fn vnwa_switch_screen_en (& self) -> VnwaSwitchScreenEnR { VnwaSwitchScreenEnR :: new (((self . bits >> 13) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_mem_grp1_highres_switch_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_highres_switch_en (& mut self) -> AppPdMemGrp1HighresSwitchEnW < DebugStatusAon12Spec > { AppPdMemGrp1HighresSwitchEnW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for app_pd_mem_grp2_highres_switch_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_highres_switch_en (& mut self) -> AppPdMemGrp2HighresSwitchEnW < DebugStatusAon12Spec > { AppPdMemGrp2HighresSwitchEnW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_mem_grp3_highres_switch_en"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_highres_switch_en (& mut self) -> HwaPdMemGrp3HighresSwitchEnW < DebugStatusAon12Spec > { HwaPdMemGrp3HighresSwitchEnW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
status reg for fec_pd_mem_grp4_highres_switch_en"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_highres_switch_en (& mut self) -> FecPdMemGrp4HighresSwitchEnW < DebugStatusAon12Spec > { FecPdMemGrp4HighresSwitchEnW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_mem_grp1_lowres_switch_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_lowres_switch_en (& mut self) -> AppPdMemGrp1LowresSwitchEnW < DebugStatusAon12Spec > { AppPdMemGrp1LowresSwitchEnW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
status reg for app_pd_mem_grp2_lowres_switch_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_lowres_switch_en (& mut self) -> AppPdMemGrp2LowresSwitchEnW < DebugStatusAon12Spec > { AppPdMemGrp2LowresSwitchEnW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
status reg for hwa_pd_mem_gpr3_lowres_switch_en"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_gpr3_lowres_switch_en (& mut self) -> HwaPdMemGpr3LowresSwitchEnW < DebugStatusAon12Spec > { HwaPdMemGpr3LowresSwitchEnW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
status reg for fec_pd_mem_gpr4_lowres_switch_en"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_gpr4_lowres_switch_en (& mut self) -> FecPdMemGpr4LowresSwitchEnW < DebugStatusAon12Spec > { FecPdMemGpr4LowresSwitchEnW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
status reg for app_pd_mem_grp1_vnwa_switch_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp1_vnwa_switch_en (& mut self) -> AppPdMemGrp1VnwaSwitchEnW < DebugStatusAon12Spec > { AppPdMemGrp1VnwaSwitchEnW :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
status reg for app_pd_mem_grp2_vnwa_switch_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_mem_grp2_vnwa_switch_en (& mut self) -> AppPdMemGrp2VnwaSwitchEnW < DebugStatusAon12Spec > { AppPdMemGrp2VnwaSwitchEnW :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
status reg for hwa_pd_mem_grp3_vnwa_switch_en"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_mem_grp3_vnwa_switch_en (& mut self) -> HwaPdMemGrp3VnwaSwitchEnW < DebugStatusAon12Spec > { HwaPdMemGrp3VnwaSwitchEnW :: new (self , 10) } # [doc = "Bit 11 - 11:11\\]
status reg for fec_pd_mem_grp4_vnwa_switch_en"]
# [inline (always)]
# [must_use]
pub fn fec_pd_mem_grp4_vnwa_switch_en (& mut self) -> FecPdMemGrp4VnwaSwitchEnW < DebugStatusAon12Spec > { FecPdMemGrp4VnwaSwitchEnW :: new (self , 11) } # [doc = "Bit 12 - 12:12\\]
status reg for vnwa_switch_weak_process"]
# [inline (always)]
# [must_use]
pub fn vnwa_switch_weak_process (& mut self) -> VnwaSwitchWeakProcessW < DebugStatusAon12Spec > { VnwaSwitchWeakProcessW :: new (self , 12) } # [doc = "Bit 13 - 13:13\\]
status reg for vnwa_switch_screen_en"]
# [inline (always)]
# [must_use]
pub fn vnwa_switch_screen_en (& mut self) -> VnwaSwitchScreenEnW < DebugStatusAon12Spec > { VnwaSwitchScreenEnW :: new (self , 13) } } # [doc = "DEBUG_STATUS_AON_12\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon12Spec ; impl crate :: RegisterSpec for DebugStatusAon12Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_12::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon12Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_12::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon12Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_12 to value 0"]
impl crate :: Resettable for DebugStatusAon12Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_13 (rw) register accessor: DEBUG_STATUS_AON_13\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_13`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_13")]
pub type DebugStatusAon13 = crate :: Reg < debug_status_aon_13 :: DebugStatusAon13Spec > ; # [doc = "DEBUG_STATUS_AON_13"]
pub mod debug_status_aon_13 { # [doc = "Register `DEBUG_STATUS_AON_13` reader"]
pub type R = crate :: R < DebugStatusAon13Spec > ; # [doc = "Register `DEBUG_STATUS_AON_13` writer"]
pub type W = crate :: W < DebugStatusAon13Spec > ; # [doc = "Field `app_pd_clkgate_en` reader - 0:0\\]
status reg for app_pd_clkgate_en"]
pub type AppPdClkgateEnR = crate :: BitReader ; # [doc = "Field `app_pd_clkgate_en` writer - 0:0\\]
status reg for app_pd_clkgate_en"]
pub type AppPdClkgateEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_clkgate_en` reader - 1:1\\]
status reg for fec_pd_clkgate_en"]
pub type FecPdClkgateEnR = crate :: BitReader ; # [doc = "Field `fec_pd_clkgate_en` writer - 1:1\\]
status reg for fec_pd_clkgate_en"]
pub type FecPdClkgateEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_clkgate_en` reader - 2:2\\]
status reg for hwa_pd_clkgate_en"]
pub type HwaPdClkgateEnR = crate :: BitReader ; # [doc = "Field `hwa_pd_clkgate_en` writer - 2:2\\]
status reg for hwa_pd_clkgate_en"]
pub type HwaPdClkgateEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_clkgate_en"]
# [inline (always)]
pub fn app_pd_clkgate_en (& self) -> AppPdClkgateEnR { AppPdClkgateEnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_clkgate_en"]
# [inline (always)]
pub fn fec_pd_clkgate_en (& self) -> FecPdClkgateEnR { FecPdClkgateEnR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_clkgate_en"]
# [inline (always)]
pub fn hwa_pd_clkgate_en (& self) -> HwaPdClkgateEnR { HwaPdClkgateEnR :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_clkgate_en"]
# [inline (always)]
# [must_use]
pub fn app_pd_clkgate_en (& mut self) -> AppPdClkgateEnW < DebugStatusAon13Spec > { AppPdClkgateEnW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_clkgate_en"]
# [inline (always)]
# [must_use]
pub fn fec_pd_clkgate_en (& mut self) -> FecPdClkgateEnW < DebugStatusAon13Spec > { FecPdClkgateEnW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_clkgate_en"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_clkgate_en (& mut self) -> HwaPdClkgateEnW < DebugStatusAon13Spec > { HwaPdClkgateEnW :: new (self , 2) } } # [doc = "DEBUG_STATUS_AON_13\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon13Spec ; impl crate :: RegisterSpec for DebugStatusAon13Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_13::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon13Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_13::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon13Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_13 to value 0"]
impl crate :: Resettable for DebugStatusAon13Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_14 (rw) register accessor: DEBUG_STATUS_AON_14\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_14`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_14")]
pub type DebugStatusAon14 = crate :: Reg < debug_status_aon_14 :: DebugStatusAon14Spec > ; # [doc = "DEBUG_STATUS_AON_14"]
pub mod debug_status_aon_14 { # [doc = "Register `DEBUG_STATUS_AON_14` reader"]
pub type R = crate :: R < DebugStatusAon14Spec > ; # [doc = "Register `DEBUG_STATUS_AON_14` writer"]
pub type W = crate :: W < DebugStatusAon14Spec > ; # [doc = "Field `app_pd_por_rstn` reader - 0:0\\]
status reg for app_pd_por_rstn"]
pub type AppPdPorRstnR = crate :: BitReader ; # [doc = "Field `app_pd_por_rstn` writer - 0:0\\]
status reg for app_pd_por_rstn"]
pub type AppPdPorRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_por_rstn` reader - 1:1\\]
status reg for fec_pd_por_rstn"]
pub type FecPdPorRstnR = crate :: BitReader ; # [doc = "Field `fec_pd_por_rstn` writer - 1:1\\]
status reg for fec_pd_por_rstn"]
pub type FecPdPorRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_por_rstn` reader - 2:2\\]
status reg for hwa_pd_por_rstn"]
pub type HwaPdPorRstnR = crate :: BitReader ; # [doc = "Field `hwa_pd_por_rstn` writer - 2:2\\]
status reg for hwa_pd_por_rstn"]
pub type HwaPdPorRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `test_dbg_pd_por_rstn` reader - 3:3\\]
status reg for test_dbg_pd_por_rstn"]
pub type TestDbgPdPorRstnR = crate :: BitReader ; # [doc = "Field `test_dbg_pd_por_rstn` writer - 3:3\\]
status reg for test_dbg_pd_por_rstn"]
pub type TestDbgPdPorRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_warm_rstn` reader - 4:4\\]
status reg for app_pd_warm_rstn"]
pub type AppPdWarmRstnR = crate :: BitReader ; # [doc = "Field `app_pd_warm_rstn` writer - 4:4\\]
status reg for app_pd_warm_rstn"]
pub type AppPdWarmRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_warm_rstn` reader - 5:5\\]
status reg for fec_pd_warm_rstn"]
pub type FecPdWarmRstnR = crate :: BitReader ; # [doc = "Field `fec_pd_warm_rstn` writer - 5:5\\]
status reg for fec_pd_warm_rstn"]
pub type FecPdWarmRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `hwa_pd_warm_rstn` reader - 6:6\\]
status reg for hwa_pd_warm_rstn"]
pub type HwaPdWarmRstnR = crate :: BitReader ; # [doc = "Field `hwa_pd_warm_rstn` writer - 6:6\\]
status reg for hwa_pd_warm_rstn"]
pub type HwaPdWarmRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `app_pd_core_rstn` reader - 7:7\\]
status reg for app_pd_core_rstn"]
pub type AppPdCoreRstnR = crate :: BitReader ; # [doc = "Field `app_pd_core_rstn` writer - 7:7\\]
status reg for app_pd_core_rstn"]
pub type AppPdCoreRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `fec_pd_core_rstn` reader - 8:8\\]
status reg for fec_pd_core_rstn"]
pub type FecPdCoreRstnR = crate :: BitReader ; # [doc = "Field `fec_pd_core_rstn` writer - 8:8\\]
status reg for fec_pd_core_rstn"]
pub type FecPdCoreRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_por_rstn"]
# [inline (always)]
pub fn app_pd_por_rstn (& self) -> AppPdPorRstnR { AppPdPorRstnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_por_rstn"]
# [inline (always)]
pub fn fec_pd_por_rstn (& self) -> FecPdPorRstnR { FecPdPorRstnR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_por_rstn"]
# [inline (always)]
pub fn hwa_pd_por_rstn (& self) -> HwaPdPorRstnR { HwaPdPorRstnR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
status reg for test_dbg_pd_por_rstn"]
# [inline (always)]
pub fn test_dbg_pd_por_rstn (& self) -> TestDbgPdPorRstnR { TestDbgPdPorRstnR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_warm_rstn"]
# [inline (always)]
pub fn app_pd_warm_rstn (& self) -> AppPdWarmRstnR { AppPdWarmRstnR :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - 5:5\\]
status reg for fec_pd_warm_rstn"]
# [inline (always)]
pub fn fec_pd_warm_rstn (& self) -> FecPdWarmRstnR { FecPdWarmRstnR :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - 6:6\\]
status reg for hwa_pd_warm_rstn"]
# [inline (always)]
pub fn hwa_pd_warm_rstn (& self) -> HwaPdWarmRstnR { HwaPdWarmRstnR :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - 7:7\\]
status reg for app_pd_core_rstn"]
# [inline (always)]
pub fn app_pd_core_rstn (& self) -> AppPdCoreRstnR { AppPdCoreRstnR :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - 8:8\\]
status reg for fec_pd_core_rstn"]
# [inline (always)]
pub fn fec_pd_core_rstn (& self) -> FecPdCoreRstnR { FecPdCoreRstnR :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for app_pd_por_rstn"]
# [inline (always)]
# [must_use]
pub fn app_pd_por_rstn (& mut self) -> AppPdPorRstnW < DebugStatusAon14Spec > { AppPdPorRstnW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for fec_pd_por_rstn"]
# [inline (always)]
# [must_use]
pub fn fec_pd_por_rstn (& mut self) -> FecPdPorRstnW < DebugStatusAon14Spec > { FecPdPorRstnW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for hwa_pd_por_rstn"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_por_rstn (& mut self) -> HwaPdPorRstnW < DebugStatusAon14Spec > { HwaPdPorRstnW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
status reg for test_dbg_pd_por_rstn"]
# [inline (always)]
# [must_use]
pub fn test_dbg_pd_por_rstn (& mut self) -> TestDbgPdPorRstnW < DebugStatusAon14Spec > { TestDbgPdPorRstnW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
status reg for app_pd_warm_rstn"]
# [inline (always)]
# [must_use]
pub fn app_pd_warm_rstn (& mut self) -> AppPdWarmRstnW < DebugStatusAon14Spec > { AppPdWarmRstnW :: new (self , 4) } # [doc = "Bit 5 - 5:5\\]
status reg for fec_pd_warm_rstn"]
# [inline (always)]
# [must_use]
pub fn fec_pd_warm_rstn (& mut self) -> FecPdWarmRstnW < DebugStatusAon14Spec > { FecPdWarmRstnW :: new (self , 5) } # [doc = "Bit 6 - 6:6\\]
status reg for hwa_pd_warm_rstn"]
# [inline (always)]
# [must_use]
pub fn hwa_pd_warm_rstn (& mut self) -> HwaPdWarmRstnW < DebugStatusAon14Spec > { HwaPdWarmRstnW :: new (self , 6) } # [doc = "Bit 7 - 7:7\\]
status reg for app_pd_core_rstn"]
# [inline (always)]
# [must_use]
pub fn app_pd_core_rstn (& mut self) -> AppPdCoreRstnW < DebugStatusAon14Spec > { AppPdCoreRstnW :: new (self , 7) } # [doc = "Bit 8 - 8:8\\]
status reg for fec_pd_core_rstn"]
# [inline (always)]
# [must_use]
pub fn fec_pd_core_rstn (& mut self) -> FecPdCoreRstnW < DebugStatusAon14Spec > { FecPdCoreRstnW :: new (self , 8) } } # [doc = "DEBUG_STATUS_AON_14\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon14Spec ; impl crate :: RegisterSpec for DebugStatusAon14Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_14::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon14Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_14::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon14Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_14 to value 0"]
impl crate :: Resettable for DebugStatusAon14Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_15 (rw) register accessor: DEBUG_STATUS_AON_15\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_15`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_15")]
pub type DebugStatusAon15 = crate :: Reg < debug_status_aon_15 :: DebugStatusAon15Spec > ; # [doc = "DEBUG_STATUS_AON_15"]
pub mod debug_status_aon_15 { # [doc = "Register `DEBUG_STATUS_AON_15` reader"]
pub type R = crate :: R < DebugStatusAon15Spec > ; # [doc = "Register `DEBUG_STATUS_AON_15` writer"]
pub type W = crate :: W < DebugStatusAon15Spec > ; # [doc = "Field `DIS_JTAG` reader - 0:0\\]
status reg for DIS_JTAG"]
pub type DisJtagR = crate :: BitReader ; # [doc = "Field `DIS_JTAG` writer - 0:0\\]
status reg for DIS_JTAG"]
pub type DisJtagW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JTAG_DIS` reader - 1:1\\]
status reg for JTAG_DIS"]
pub type JtagDisR = crate :: BitReader ; # [doc = "Field `JTAG_DIS` writer - 1:1\\]
status reg for JTAG_DIS"]
pub type JtagDisW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RS232_DIS` reader - 2:2\\]
status reg for RS232_DIS"]
pub type Rs232DisR = crate :: BitReader ; # [doc = "Field `RS232_DIS` writer - 2:2\\]
status reg for RS232_DIS"]
pub type Rs232DisW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEST_DIS` reader - 3:3\\]
status reg for TEST_DIS"]
pub type TestDisR = crate :: BitReader ; # [doc = "Field `TEST_DIS` writer - 3:3\\]
status reg for TEST_DIS"]
pub type TestDisW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LVDS_DIS` reader - 4:4\\]
status reg for LVDS_DIS"]
pub type LvdsDisR = crate :: BitReader ; # [doc = "Field `LVDS_DIS` writer - 4:4\\]
status reg for LVDS_DIS"]
pub type LvdsDisW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for DIS_JTAG"]
# [inline (always)]
pub fn dis_jtag (& self) -> DisJtagR { DisJtagR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
status reg for JTAG_DIS"]
# [inline (always)]
pub fn jtag_dis (& self) -> JtagDisR { JtagDisR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
status reg for RS232_DIS"]
# [inline (always)]
pub fn rs232_dis (& self) -> Rs232DisR { Rs232DisR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
status reg for TEST_DIS"]
# [inline (always)]
pub fn test_dis (& self) -> TestDisR { TestDisR :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - 4:4\\]
status reg for LVDS_DIS"]
# [inline (always)]
pub fn lvds_dis (& self) -> LvdsDisR { LvdsDisR :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for DIS_JTAG"]
# [inline (always)]
# [must_use]
pub fn dis_jtag (& mut self) -> DisJtagW < DebugStatusAon15Spec > { DisJtagW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
status reg for JTAG_DIS"]
# [inline (always)]
# [must_use]
pub fn jtag_dis (& mut self) -> JtagDisW < DebugStatusAon15Spec > { JtagDisW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
status reg for RS232_DIS"]
# [inline (always)]
# [must_use]
pub fn rs232_dis (& mut self) -> Rs232DisW < DebugStatusAon15Spec > { Rs232DisW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
status reg for TEST_DIS"]
# [inline (always)]
# [must_use]
pub fn test_dis (& mut self) -> TestDisW < DebugStatusAon15Spec > { TestDisW :: new (self , 3) } # [doc = "Bit 4 - 4:4\\]
status reg for LVDS_DIS"]
# [inline (always)]
# [must_use]
pub fn lvds_dis (& mut self) -> LvdsDisW < DebugStatusAon15Spec > { LvdsDisW :: new (self , 4) } } # [doc = "DEBUG_STATUS_AON_15\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon15Spec ; impl crate :: RegisterSpec for DebugStatusAon15Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_15::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon15Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_15::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon15Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_15 to value 0"]
impl crate :: Resettable for DebugStatusAon15Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "DEBUG_STATUS_AON_16 (rw) register accessor: DEBUG_STATUS_AON_16\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_status_aon_16`]
module"]
# [doc (alias = "DEBUG_STATUS_AON_16")]
pub type DebugStatusAon16 = crate :: Reg < debug_status_aon_16 :: DebugStatusAon16Spec > ; # [doc = "DEBUG_STATUS_AON_16"]
pub mod debug_status_aon_16 { # [doc = "Register `DEBUG_STATUS_AON_16` reader"]
pub type R = crate :: R < DebugStatusAon16Spec > ; # [doc = "Register `DEBUG_STATUS_AON_16` writer"]
pub type W = crate :: W < DebugStatusAon16Spec > ; # [doc = "Field `icemelter_powakeemu` reader - 0:0\\]
status reg for icemelter_powakeemu"]
pub type IcemelterPowakeemuR = crate :: BitReader ; # [doc = "Field `icemelter_powakeemu` writer - 0:0\\]
status reg for icemelter_powakeemu"]
pub type IcemelterPowakeemuW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
status reg for icemelter_powakeemu"]
# [inline (always)]
pub fn icemelter_powakeemu (& self) -> IcemelterPowakeemuR { IcemelterPowakeemuR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
status reg for icemelter_powakeemu"]
# [inline (always)]
# [must_use]
pub fn icemelter_powakeemu (& mut self) -> IcemelterPowakeemuW < DebugStatusAon16Spec > { IcemelterPowakeemuW :: new (self , 0) } } # [doc = "DEBUG_STATUS_AON_16\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status_aon_16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status_aon_16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugStatusAon16Spec ; impl crate :: RegisterSpec for DebugStatusAon16Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`debug_status_aon_16::R`](R) reader structure"]
impl crate :: Readable for DebugStatusAon16Spec { } # [doc = "`write(|w| ..)` method takes [`debug_status_aon_16::W`](W) writer structure"]
impl crate :: Writable for DebugStatusAon16Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DEBUG_STATUS_AON_16 to value 0"]
impl crate :: Resettable for DebugStatusAon16Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APPSS_DYNAMIC_CLK_GATE_STATUS (rw) register accessor: APPSS_DYNAMIC_CLK_GATE_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dynamic_clk_gate_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dynamic_clk_gate_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@appss_dynamic_clk_gate_status`]
module"]
# [doc (alias = "APPSS_DYNAMIC_CLK_GATE_STATUS")]
pub type AppssDynamicClkGateStatus = crate :: Reg < appss_dynamic_clk_gate_status :: AppssDynamicClkGateStatusSpec > ; # [doc = "APPSS_DYNAMIC_CLK_GATE_STATUS"]
pub mod appss_dynamic_clk_gate_status { # [doc = "Register `APPSS_DYNAMIC_CLK_GATE_STATUS` reader"]
pub type R = crate :: R < AppssDynamicClkGateStatusSpec > ; # [doc = "Register `APPSS_DYNAMIC_CLK_GATE_STATUS` writer"]
pub type W = crate :: W < AppssDynamicClkGateStatusSpec > ; # [doc = "Field `xbara` reader - 0:0\\]
Dynamic Clock gate Status of XBARA 1 - Clock is Enabled 0 - Clock is Gated."]
pub type XbaraR = crate :: BitReader ; # [doc = "Field `xbara` writer - 0:0\\]
Dynamic Clock gate Status of XBARA 1 - Clock is Enabled 0 - Clock is Gated."]
pub type XbaraW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc1` reader - 1:1\\]
Dynamic Clock gate Status of TPTC1 1 - Clock is Enabled 0 - Clock is Gated."]
pub type Tptc1R = crate :: BitReader ; # [doc = "Field `tptc1` writer - 1:1\\]
Dynamic Clock gate Status of TPTC1 1 - Clock is Enabled 0 - Clock is Gated."]
pub type Tptc1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `tptc2` reader - 2:2\\]
Dynamic Clock gate Status of TPTC2 1 - Clock is Enabled 0 - Clock is Gated."]
pub type Tptc2R = crate :: BitReader ; # [doc = "Field `tptc2` writer - 2:2\\]
Dynamic Clock gate Status of TPTC2 1 - Clock is Enabled 0 - Clock is Gated."]
pub type Tptc2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Dynamic Clock gate Status of XBARA 1 - Clock is Enabled 0 - Clock is Gated."]
# [inline (always)]
pub fn xbara (& self) -> XbaraR { XbaraR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Dynamic Clock gate Status of TPTC1 1 - Clock is Enabled 0 - Clock is Gated."]
# [inline (always)]
pub fn tptc1 (& self) -> Tptc1R { Tptc1R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Dynamic Clock gate Status of TPTC2 1 - Clock is Enabled 0 - Clock is Gated."]
# [inline (always)]
pub fn tptc2 (& self) -> Tptc2R { Tptc2R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Dynamic Clock gate Status of XBARA 1 - Clock is Enabled 0 - Clock is Gated."]
# [inline (always)]
# [must_use]
pub fn xbara (& mut self) -> XbaraW < AppssDynamicClkGateStatusSpec > { XbaraW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Dynamic Clock gate Status of TPTC1 1 - Clock is Enabled 0 - Clock is Gated."]
# [inline (always)]
# [must_use]
pub fn tptc1 (& mut self) -> Tptc1W < AppssDynamicClkGateStatusSpec > { Tptc1W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Dynamic Clock gate Status of TPTC2 1 - Clock is Enabled 0 - Clock is Gated."]
# [inline (always)]
# [must_use]
pub fn tptc2 (& mut self) -> Tptc2W < AppssDynamicClkGateStatusSpec > { Tptc2W :: new (self , 2) } } # [doc = "APPSS_DYNAMIC_CLK_GATE_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`appss_dynamic_clk_gate_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`appss_dynamic_clk_gate_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppssDynamicClkGateStatusSpec ; impl crate :: RegisterSpec for AppssDynamicClkGateStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`appss_dynamic_clk_gate_status::R`](R) reader structure"]
impl crate :: Readable for AppssDynamicClkGateStatusSpec { } # [doc = "`write(|w| ..)` method takes [`appss_dynamic_clk_gate_status::W`](W) writer structure"]
impl crate :: Writable for AppssDynamicClkGateStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APPSS_DYNAMIC_CLK_GATE_STATUS to value 0"]
impl crate :: Resettable for AppssDynamicClkGateStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK0 (rw) register accessor: - KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick0`]
module"]
# [doc (alias = "LOCK0_KICK0")]
pub type Lock0Kick0 = crate :: Reg < lock0_kick0 :: Lock0Kick0Spec > ; # [doc = "- KICK0 component"]
pub mod lock0_kick0 { # [doc = "Register `LOCK0_KICK0` reader"]
pub type R = crate :: R < Lock0Kick0Spec > ; # [doc = "Register `LOCK0_KICK0` writer"]
pub type W = crate :: W < Lock0Kick0Spec > ; # [doc = "Field `KICK0_COMPONENT` reader - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK0_COMPONENT` writer - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
pub fn kick0_component (& self) -> Kick0ComponentR { Kick0ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
# [must_use]
pub fn kick0_component (& mut self) -> Kick0ComponentW < Lock0Kick0Spec > { Kick0ComponentW :: new (self , 0) } } # [doc = "- KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick0Spec ; impl crate :: RegisterSpec for Lock0Kick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick0::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick0Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick0::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK0 to value 0"]
impl crate :: Resettable for Lock0Kick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK1 (rw) register accessor: - KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick1`]
module"]
# [doc (alias = "LOCK0_KICK1")]
pub type Lock0Kick1 = crate :: Reg < lock0_kick1 :: Lock0Kick1Spec > ; # [doc = "- KICK1 component"]
pub mod lock0_kick1 { # [doc = "Register `LOCK0_KICK1` reader"]
pub type R = crate :: R < Lock0Kick1Spec > ; # [doc = "Register `LOCK0_KICK1` writer"]
pub type W = crate :: W < Lock0Kick1Spec > ; # [doc = "Field `KICK1_COMPONENT` reader - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK1_COMPONENT` writer - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
pub fn kick1_component (& self) -> Kick1ComponentR { Kick1ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
# [must_use]
pub fn kick1_component (& mut self) -> Kick1ComponentW < Lock0Kick1Spec > { Kick1ComponentW :: new (self , 0) } } # [doc = "- KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick1Spec ; impl crate :: RegisterSpec for Lock0Kick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick1::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick1Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick1::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK1 to value 0"]
impl crate :: Resettable for Lock0Kick1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_raw_status (rw) register accessor: Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw_status`]
module"]
# [doc (alias = "intr_raw_status")]
pub type IntrRawStatus = crate :: Reg < intr_raw_status :: IntrRawStatusSpec > ; # [doc = "Interrupt Raw Status/Set Register"]
pub mod intr_raw_status { # [doc = "Register `intr_raw_status` reader"]
pub type R = crate :: R < IntrRawStatusSpec > ; # [doc = "Register `intr_raw_status` writer"]
pub type W = crate :: W < IntrRawStatusSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrRawStatusSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrRawStatusSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrRawStatusSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrRawStatusSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrRawStatusSpec ; impl crate :: RegisterSpec for IntrRawStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_raw_status::R`](R) reader structure"]
impl crate :: Readable for IntrRawStatusSpec { } # [doc = "`write(|w| ..)` method takes [`intr_raw_status::W`](W) writer structure"]
impl crate :: Writable for IntrRawStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_raw_status to value 0"]
impl crate :: Resettable for IntrRawStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enabled_status_clear (rw) register accessor: Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enabled_status_clear`]
module"]
# [doc (alias = "intr_enabled_status_clear")]
pub type IntrEnabledStatusClear = crate :: Reg < intr_enabled_status_clear :: IntrEnabledStatusClearSpec > ; # [doc = "Interrupt Enabled Status/Clear register"]
pub mod intr_enabled_status_clear { # [doc = "Register `intr_enabled_status_clear` reader"]
pub type R = crate :: R < IntrEnabledStatusClearSpec > ; # [doc = "Register `intr_enabled_status_clear` writer"]
pub type W = crate :: W < IntrEnabledStatusClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrEnabledStatusClearSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrEnabledStatusClearSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnabledStatusClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnabledStatusClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnabledStatusClearSpec ; impl crate :: RegisterSpec for IntrEnabledStatusClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enabled_status_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnabledStatusClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enabled_status_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnabledStatusClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enabled_status_clear to value 0"]
impl crate :: Resettable for IntrEnabledStatusClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable`]
module"]
# [doc (alias = "intr_enable")]
pub type IntrEnable = crate :: Reg < intr_enable :: IntrEnableSpec > ; # [doc = "Interrupt Enable register"]
pub mod intr_enable { # [doc = "Register `intr_enable` reader"]
pub type R = crate :: R < IntrEnableSpec > ; # [doc = "Register `intr_enable` writer"]
pub type W = crate :: W < IntrEnableSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSpec ; impl crate :: RegisterSpec for IntrEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable to value 0"]
impl crate :: Resettable for IntrEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable_clear (rw) register accessor: Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "intr_enable_clear")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "Interrupt Enable Clear register"]
pub mod intr_enable_clear { # [doc = "Register `intr_enable_clear` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `intr_enable_clear` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableClearSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableClearSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable_clear to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "eoi (rw) register accessor: EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi`]
module"]
# [doc (alias = "eoi")]
pub type Eoi = crate :: Reg < eoi :: EoiSpec > ; # [doc = "EOI register"]
pub mod eoi { # [doc = "Register `eoi` reader"]
pub type R = crate :: R < EoiSpec > ; # [doc = "Register `eoi` writer"]
pub type W = crate :: W < EoiSpec > ; # [doc = "Field `EOI_VECTOR_VALUE_` reader - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_R = crate :: FieldReader ; # [doc = "Field `EOI_VECTOR_VALUE_` writer - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
pub fn eoi_vector_value_ (& self) -> EoiVectorValue_R { EoiVectorValue_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
# [must_use]
pub fn eoi_vector_value_ (& mut self) -> EoiVectorValue_W < EoiSpec > { EoiVectorValue_W :: new (self , 0) } } # [doc = "EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EoiSpec ; impl crate :: RegisterSpec for EoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eoi::R`](R) reader structure"]
impl crate :: Readable for EoiSpec { } # [doc = "`write(|w| ..)` method takes [`eoi::W`](W) writer structure"]
impl crate :: Writable for EoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets eoi to value 0"]
impl crate :: Resettable for EoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_address (rw) register accessor: Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_address`]
module"]
# [doc (alias = "fault_address")]
pub type FaultAddress = crate :: Reg < fault_address :: FaultAddressSpec > ; # [doc = "Fault Address register"]
pub mod fault_address { # [doc = "Register `fault_address` reader"]
pub type R = crate :: R < FaultAddressSpec > ; # [doc = "Register `fault_address` writer"]
pub type W = crate :: W < FaultAddressSpec > ; # [doc = "Field `FAULT_ADDRESS_` reader - 31:0\\]
Fault Address."]
pub type FaultAddress_R = crate :: FieldReader < u32 > ; # [doc = "Field `FAULT_ADDRESS_` writer - 31:0\\]
Fault Address."]
pub type FaultAddress_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
pub fn fault_address_ (& self) -> FaultAddress_R { FaultAddress_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
# [must_use]
pub fn fault_address_ (& mut self) -> FaultAddress_W < FaultAddressSpec > { FaultAddress_W :: new (self , 0) } } # [doc = "Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAddressSpec ; impl crate :: RegisterSpec for FaultAddressSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_address::R`](R) reader structure"]
impl crate :: Readable for FaultAddressSpec { } # [doc = "`write(|w| ..)` method takes [`fault_address::W`](W) writer structure"]
impl crate :: Writable for FaultAddressSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_address to value 0"]
impl crate :: Resettable for FaultAddressSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_type_status (rw) register accessor: Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_type_status`]
module"]
# [doc (alias = "fault_type_status")]
pub type FaultTypeStatus = crate :: Reg < fault_type_status :: FaultTypeStatusSpec > ; # [doc = "Fault Type Status register"]
pub mod fault_type_status { # [doc = "Register `fault_type_status` reader"]
pub type R = crate :: R < FaultTypeStatusSpec > ; # [doc = "Register `fault_type_status` writer"]
pub type W = crate :: W < FaultTypeStatusSpec > ; # [doc = "Field `FAULT_TYPE_10_0000` reader - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000R = crate :: FieldReader ; # [doc = "Field `FAULT_TYPE_10_0000` writer - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NONSECURE_ACCESS_` reader - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_R = crate :: BitReader ; # [doc = "Field `NONSECURE_ACCESS_` writer - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
pub fn fault_type_10_0000 (& self) -> FaultType10_0000R { FaultType10_0000R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
pub fn nonsecure_access_ (& self) -> NonsecureAccess_R { NonsecureAccess_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
# [must_use]
pub fn fault_type_10_0000 (& mut self) -> FaultType10_0000W < FaultTypeStatusSpec > { FaultType10_0000W :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
# [must_use]
pub fn nonsecure_access_ (& mut self) -> NonsecureAccess_W < FaultTypeStatusSpec > { NonsecureAccess_W :: new (self , 6) } } # [doc = "Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultTypeStatusSpec ; impl crate :: RegisterSpec for FaultTypeStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_type_status::R`](R) reader structure"]
impl crate :: Readable for FaultTypeStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_type_status::W`](W) writer structure"]
impl crate :: Writable for FaultTypeStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_type_status to value 0"]
impl crate :: Resettable for FaultTypeStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_attr_status (rw) register accessor: Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_attr_status`]
module"]
# [doc (alias = "fault_attr_status")]
pub type FaultAttrStatus = crate :: Reg < fault_attr_status :: FaultAttrStatusSpec > ; # [doc = "Fault Attribute Status register"]
pub mod fault_attr_status { # [doc = "Register `fault_attr_status` reader"]
pub type R = crate :: R < FaultAttrStatusSpec > ; # [doc = "Register `fault_attr_status` writer"]
pub type W = crate :: W < FaultAttrStatusSpec > ; # [doc = "Field `PRIVILEGE_ID_` reader - 7:0\\]
Privilege ID."]
pub type PrivilegeId_R = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID_` writer - 7:0\\]
Privilege ID."]
pub type PrivilegeId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ROUTE_ID_` reader - 19:8\\]
Route ID."]
pub type RouteId_R = crate :: FieldReader < u16 > ; # [doc = "Field `ROUTE_ID_` writer - 19:8\\]
Route ID."]
pub type RouteId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `XID_` reader - 31:20\\]
XID."]
pub type Xid_R = crate :: FieldReader < u16 > ; # [doc = "Field `XID_` writer - 31:20\\]
XID."]
pub type Xid_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
pub fn privilege_id_ (& self) -> PrivilegeId_R { PrivilegeId_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
pub fn route_id_ (& self) -> RouteId_R { RouteId_R :: new (((self . bits >> 8) & 0x0fff) as u16) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
pub fn xid_ (& self) -> Xid_R { Xid_R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
# [must_use]
pub fn privilege_id_ (& mut self) -> PrivilegeId_W < FaultAttrStatusSpec > { PrivilegeId_W :: new (self , 0) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
# [must_use]
pub fn route_id_ (& mut self) -> RouteId_W < FaultAttrStatusSpec > { RouteId_W :: new (self , 8) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
# [must_use]
pub fn xid_ (& mut self) -> Xid_W < FaultAttrStatusSpec > { Xid_W :: new (self , 20) } } # [doc = "Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAttrStatusSpec ; impl crate :: RegisterSpec for FaultAttrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_attr_status::R`](R) reader structure"]
impl crate :: Readable for FaultAttrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_attr_status::W`](W) writer structure"]
impl crate :: Writable for FaultAttrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_attr_status to value 0"]
impl crate :: Resettable for FaultAttrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_clear (rw) register accessor: Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_clear`]
module"]
# [doc (alias = "fault_clear")]
pub type FaultClear = crate :: Reg < fault_clear :: FaultClearSpec > ; # [doc = "Fault Clear register"]
pub mod fault_clear { # [doc = "Register `fault_clear` reader"]
pub type R = crate :: R < FaultClearSpec > ; # [doc = "Register `fault_clear` writer"]
pub type W = crate :: W < FaultClearSpec > ; # [doc = "Field `FAULT_CLEAR__WRITING` reader - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingR = crate :: BitReader ; # [doc = "Field `FAULT_CLEAR__WRITING` writer - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
pub fn fault_clear__writing (& self) -> FaultClear_WritingR { FaultClear_WritingR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn fault_clear__writing (& mut self) -> FaultClear_WritingW < FaultClearSpec > { FaultClear_WritingW :: new (self , 0) } } # [doc = "Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultClearSpec ; impl crate :: RegisterSpec for FaultClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_clear::R`](R) reader structure"]
impl crate :: Readable for FaultClearSpec { } # [doc = "`write(|w| ..)` method takes [`fault_clear::W`](W) writer structure"]
impl crate :: Writable for FaultClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_clear to value 0"]
impl crate :: Resettable for FaultClearSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "PLLDIG_CTRL"]
pub struct PlldigCtrl { _marker : PhantomData < * const () > } unsafe impl Send for PlldigCtrl { } impl PlldigCtrl { # [doc = r"Pointer to the register block"]
pub const PTR : * const plldig_ctrl :: RegisterBlock = 0x5b04_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const plldig_ctrl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for PlldigCtrl { type Target = plldig_ctrl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for PlldigCtrl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("PlldigCtrl") . finish () } } # [doc = "PLLDIG_CTRL"]
pub mod plldig_ctrl { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , plldig_en : PlldigEn , plldig_mdiv_ndiv : PlldigMdivNdiv , plldig_ctrl : PlldigCtrl , plldig_mode_en : PlldigModeEn , plldig_apll_sw_dis_delay1 : PlldigApllSwDisDelay1 , plldig_apll_sw_dis_delay2 : PlldigApllSwDisDelay2 , plldig_override : PlldigOverride , plldig_status : PlldigStatus , fast_clk_mux_postdiv : FastClkMuxPostdiv , fast_clk_status : FastClkStatus , _reserved11 : [u8 ; 0x0fdc]
, lock0_kick0 : Lock0Kick0 , lock0_kick1 : Lock0Kick1 , intr_raw_status : IntrRawStatus , intr_enabled_status_clear : IntrEnabledStatusClear , intr_enable : IntrEnable , intr_enable_clear : IntrEnableClear , eoi : Eoi , fault_address : FaultAddress , fault_type_status : FaultTypeStatus , fault_attr_status : FaultAttrStatus , fault_clear : FaultClear , } impl RegisterBlock { # [doc = "0x00 - PID register"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - PLLDIG_EN"]
# [inline (always)]
pub const fn plldig_en (& self) -> & PlldigEn { & self . plldig_en } # [doc = "0x08 - PLLDIG_MDIV_NDIV"]
# [inline (always)]
pub const fn plldig_mdiv_ndiv (& self) -> & PlldigMdivNdiv { & self . plldig_mdiv_ndiv } # [doc = "0x0c - PLLDIG_CTRL"]
# [inline (always)]
pub const fn plldig_ctrl (& self) -> & PlldigCtrl { & self . plldig_ctrl } # [doc = "0x10 - PLLDIG_MODE_EN"]
# [inline (always)]
pub const fn plldig_mode_en (& self) -> & PlldigModeEn { & self . plldig_mode_en } # [doc = "0x14 - PLLDIG_APLL_SW_DIS_DELAY1"]
# [inline (always)]
pub const fn plldig_apll_sw_dis_delay1 (& self) -> & PlldigApllSwDisDelay1 { & self . plldig_apll_sw_dis_delay1 } # [doc = "0x18 - PLLDIG_APLL_SW_DIS_DELAY2"]
# [inline (always)]
pub const fn plldig_apll_sw_dis_delay2 (& self) -> & PlldigApllSwDisDelay2 { & self . plldig_apll_sw_dis_delay2 } # [doc = "0x1c - PLLDIG_OVERRIDE"]
# [inline (always)]
pub const fn plldig_override (& self) -> & PlldigOverride { & self . plldig_override } # [doc = "0x20 - PLLDIG_STATUS"]
# [inline (always)]
pub const fn plldig_status (& self) -> & PlldigStatus { & self . plldig_status } # [doc = "0x24 - FAST_CLK_MUX_POSTDIV"]
# [inline (always)]
pub const fn fast_clk_mux_postdiv (& self) -> & FastClkMuxPostdiv { & self . fast_clk_mux_postdiv } # [doc = "0x28 - FAST_CLK_STATUS"]
# [inline (always)]
pub const fn fast_clk_status (& self) -> & FastClkStatus { & self . fast_clk_status } # [doc = "0x1008 - - KICK0 component"]
# [inline (always)]
pub const fn lock0_kick0 (& self) -> & Lock0Kick0 { & self . lock0_kick0 } # [doc = "0x100c - - KICK1 component"]
# [inline (always)]
pub const fn lock0_kick1 (& self) -> & Lock0Kick1 { & self . lock0_kick1 } # [doc = "0x1010 - Interrupt Raw Status/Set Register"]
# [inline (always)]
pub const fn intr_raw_status (& self) -> & IntrRawStatus { & self . intr_raw_status } # [doc = "0x1014 - Interrupt Enabled Status/Clear register"]
# [inline (always)]
pub const fn intr_enabled_status_clear (& self) -> & IntrEnabledStatusClear { & self . intr_enabled_status_clear } # [doc = "0x1018 - Interrupt Enable register"]
# [inline (always)]
pub const fn intr_enable (& self) -> & IntrEnable { & self . intr_enable } # [doc = "0x101c - Interrupt Enable Clear register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x1020 - EOI register"]
# [inline (always)]
pub const fn eoi (& self) -> & Eoi { & self . eoi } # [doc = "0x1024 - Fault Address register"]
# [inline (always)]
pub const fn fault_address (& self) -> & FaultAddress { & self . fault_address } # [doc = "0x1028 - Fault Type Status register"]
# [inline (always)]
pub const fn fault_type_status (& self) -> & FaultTypeStatus { & self . fault_type_status } # [doc = "0x102c - Fault Attribute Status register"]
# [inline (always)]
pub const fn fault_attr_status (& self) -> & FaultAttrStatus { & self . fault_attr_status } # [doc = "0x1030 - Fault Clear register"]
# [inline (always)]
pub const fn fault_clear (& self) -> & FaultClear { & self . fault_clear } } # [doc = "PID (rw) register accessor: PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID register"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `PID_W6_O0` reader - "]
pub type PidW6O0R = crate :: FieldReader ; # [doc = "Field `PID_W6_O0` writer - "]
pub type PidW6O0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `PID_W2_O6` reader - "]
pub type PidW2O6R = crate :: FieldReader ; # [doc = "Field `PID_W2_O6` writer - "]
pub type PidW2O6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PID_W3_O8` reader - "]
pub type PidW3O8R = crate :: FieldReader ; # [doc = "Field `PID_W3_O8` writer - "]
pub type PidW3O8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PID_W5_O11` reader - "]
pub type PidW5O11R = crate :: FieldReader ; # [doc = "Field `PID_W5_O11` writer - "]
pub type PidW5O11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `PID_W16_O16` reader - "]
pub type PidW16O16R = crate :: FieldReader < u16 > ; # [doc = "Field `PID_W16_O16` writer - "]
pub type PidW16O16W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:5"]
# [inline (always)]
pub fn pid_w6_o0 (& self) -> PidW6O0R { PidW6O0R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7"]
# [inline (always)]
pub fn pid_w2_o6 (& self) -> PidW2O6R { PidW2O6R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10"]
# [inline (always)]
pub fn pid_w3_o8 (& self) -> PidW3O8R { PidW3O8R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15"]
# [inline (always)]
pub fn pid_w5_o11 (& self) -> PidW5O11R { PidW5O11R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:31"]
# [inline (always)]
pub fn pid_w16_o16 (& self) -> PidW16O16R { PidW16O16R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:5"]
# [inline (always)]
# [must_use]
pub fn pid_w6_o0 (& mut self) -> PidW6O0W < PidSpec > { PidW6O0W :: new (self , 0) } # [doc = "Bits 6:7"]
# [inline (always)]
# [must_use]
pub fn pid_w2_o6 (& mut self) -> PidW2O6W < PidSpec > { PidW2O6W :: new (self , 6) } # [doc = "Bits 8:10"]
# [inline (always)]
# [must_use]
pub fn pid_w3_o8 (& mut self) -> PidW3O8W < PidSpec > { PidW3O8W :: new (self , 8) } # [doc = "Bits 11:15"]
# [inline (always)]
# [must_use]
pub fn pid_w5_o11 (& mut self) -> PidW5O11W < PidSpec > { PidW5O11W :: new (self , 11) } # [doc = "Bits 16:31"]
# [inline (always)]
# [must_use]
pub fn pid_w16_o16 (& mut self) -> PidW16O16W < PidSpec > { PidW16O16W :: new (self , 16) } } # [doc = "PID register\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_EN (rw) register accessor: PLLDIG_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_en`]
module"]
# [doc (alias = "PLLDIG_EN")]
pub type PlldigEn = crate :: Reg < plldig_en :: PlldigEnSpec > ; # [doc = "PLLDIG_EN"]
pub mod plldig_en { # [doc = "Register `PLLDIG_EN` reader"]
pub type R = crate :: R < PlldigEnSpec > ; # [doc = "Register `PLLDIG_EN` writer"]
pub type W = crate :: W < PlldigEnSpec > ; # [doc = "Field `cfg_plldig_en` reader - 2:0\\]
PLL DIG enable 0x0 = PLL DIG disable 0x7 = PLL DIG enable"]
pub type CfgPlldigEnR = crate :: FieldReader ; # [doc = "Field `cfg_plldig_en` writer - 2:0\\]
PLL DIG enable 0x0 = PLL DIG disable 0x7 = PLL DIG enable"]
pub type CfgPlldigEnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cfg_pll_auto_switch_enable` reader - 10:8\\]
PLL DIG and APLL auto switch enable 0x0 = PLL DIG wont be auto turn off when APLL is enable 0x7 = PLL DIG will be auto turn off when APLL is enable"]
pub type CfgPllAutoSwitchEnableR = crate :: FieldReader ; # [doc = "Field `cfg_pll_auto_switch_enable` writer - 10:8\\]
PLL DIG and APLL auto switch enable 0x0 = PLL DIG wont be auto turn off when APLL is enable 0x7 = PLL DIG will be auto turn off when APLL is enable"]
pub type CfgPllAutoSwitchEnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cfg_plldig_lockmon_enable` reader - 18:16\\]
PLL DIG lockmon enable 0x0 = PLL DIG lockmon disbale 0x7 = PLL DIG lockmon enable"]
pub type CfgPlldigLockmonEnableR = crate :: FieldReader ; # [doc = "Field `cfg_plldig_lockmon_enable` writer - 18:16\\]
PLL DIG lockmon enable 0x0 = PLL DIG lockmon disbale 0x7 = PLL DIG lockmon enable"]
pub type CfgPlldigLockmonEnableW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
PLL DIG enable 0x0 = PLL DIG disable 0x7 = PLL DIG enable"]
# [inline (always)]
pub fn cfg_plldig_en (& self) -> CfgPlldigEnR { CfgPlldigEnR :: new ((self . bits & 7) as u8) } # [doc = "Bits 8:10 - 10:8\\]
PLL DIG and APLL auto switch enable 0x0 = PLL DIG wont be auto turn off when APLL is enable 0x7 = PLL DIG will be auto turn off when APLL is enable"]
# [inline (always)]
pub fn cfg_pll_auto_switch_enable (& self) -> CfgPllAutoSwitchEnableR { CfgPllAutoSwitchEnableR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 16:18 - 18:16\\]
PLL DIG lockmon enable 0x0 = PLL DIG lockmon disbale 0x7 = PLL DIG lockmon enable"]
# [inline (always)]
pub fn cfg_plldig_lockmon_enable (& self) -> CfgPlldigLockmonEnableR { CfgPlldigLockmonEnableR :: new (((self . bits >> 16) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
PLL DIG enable 0x0 = PLL DIG disable 0x7 = PLL DIG enable"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_en (& mut self) -> CfgPlldigEnW < PlldigEnSpec > { CfgPlldigEnW :: new (self , 0) } # [doc = "Bits 8:10 - 10:8\\]
PLL DIG and APLL auto switch enable 0x0 = PLL DIG wont be auto turn off when APLL is enable 0x7 = PLL DIG will be auto turn off when APLL is enable"]
# [inline (always)]
# [must_use]
pub fn cfg_pll_auto_switch_enable (& mut self) -> CfgPllAutoSwitchEnableW < PlldigEnSpec > { CfgPllAutoSwitchEnableW :: new (self , 8) } # [doc = "Bits 16:18 - 18:16\\]
PLL DIG lockmon enable 0x0 = PLL DIG lockmon disbale 0x7 = PLL DIG lockmon enable"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_lockmon_enable (& mut self) -> CfgPlldigLockmonEnableW < PlldigEnSpec > { CfgPlldigLockmonEnableW :: new (self , 16) } } # [doc = "PLLDIG_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigEnSpec ; impl crate :: RegisterSpec for PlldigEnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_en::R`](R) reader structure"]
impl crate :: Readable for PlldigEnSpec { } # [doc = "`write(|w| ..)` method takes [`plldig_en::W`](W) writer structure"]
impl crate :: Writable for PlldigEnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_EN to value 0"]
impl crate :: Resettable for PlldigEnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_MDIV_NDIV (rw) register accessor: PLLDIG_MDIV_NDIV\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_mdiv_ndiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_mdiv_ndiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_mdiv_ndiv`]
module"]
# [doc (alias = "PLLDIG_MDIV_NDIV")]
pub type PlldigMdivNdiv = crate :: Reg < plldig_mdiv_ndiv :: PlldigMdivNdivSpec > ; # [doc = "PLLDIG_MDIV_NDIV"]
pub mod plldig_mdiv_ndiv { # [doc = "Register `PLLDIG_MDIV_NDIV` reader"]
pub type R = crate :: R < PlldigMdivNdivSpec > ; # [doc = "Register `PLLDIG_MDIV_NDIV` writer"]
pub type W = crate :: W < PlldigMdivNdivSpec > ; # [doc = "Field `cfg_plldig_mdiv` reader - 8:0\\]
MDIV value for the PLL DIG Feedback divider settings. MDIV value directly programs the 9-bit feedback divider. Divide value ranges from 2 to 511. MDIV value has to be chosen to generate the required clock out frequency from the 2Mhz internal PLL reference"]
pub type CfgPlldigMdivR = crate :: FieldReader < u16 > ; # [doc = "Field `cfg_plldig_mdiv` writer - 8:0\\]
MDIV value for the PLL DIG Feedback divider settings. MDIV value directly programs the 9-bit feedback divider. Divide value ranges from 2 to 511. MDIV value has to be chosen to generate the required clock out frequency from the 2Mhz internal PLL reference"]
pub type CfgPlldigMdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; # [doc = "Field `cfg_plldig_ndiv` reader - 22:16\\]
NDIV value for the PLL DIG Input clock divider settings .NDIV value directly programs the 7-bit pre- divider. Divide value ranges from 2 to 127. NDIV value has to be chosen based on the REF_CLKIN frequency so as to get the internal reference frequency of the PLL closest to 2Mhz"]
pub type CfgPlldigNdivR = crate :: FieldReader ; # [doc = "Field `cfg_plldig_ndiv` writer - 22:16\\]
NDIV value for the PLL DIG Input clock divider settings .NDIV value directly programs the 7-bit pre- divider. Divide value ranges from 2 to 127. NDIV value has to be chosen based on the REF_CLKIN frequency so as to get the internal reference frequency of the PLL closest to 2Mhz"]
pub type CfgPlldigNdivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bits 0:8 - 8:0\\]
MDIV value for the PLL DIG Feedback divider settings. MDIV value directly programs the 9-bit feedback divider. Divide value ranges from 2 to 511. MDIV value has to be chosen to generate the required clock out frequency from the 2Mhz internal PLL reference"]
# [inline (always)]
pub fn cfg_plldig_mdiv (& self) -> CfgPlldigMdivR { CfgPlldigMdivR :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bits 16:22 - 22:16\\]
NDIV value for the PLL DIG Input clock divider settings .NDIV value directly programs the 7-bit pre- divider. Divide value ranges from 2 to 127. NDIV value has to be chosen based on the REF_CLKIN frequency so as to get the internal reference frequency of the PLL closest to 2Mhz"]
# [inline (always)]
pub fn cfg_plldig_ndiv (& self) -> CfgPlldigNdivR { CfgPlldigNdivR :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:8 - 8:0\\]
MDIV value for the PLL DIG Feedback divider settings. MDIV value directly programs the 9-bit feedback divider. Divide value ranges from 2 to 511. MDIV value has to be chosen to generate the required clock out frequency from the 2Mhz internal PLL reference"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_mdiv (& mut self) -> CfgPlldigMdivW < PlldigMdivNdivSpec > { CfgPlldigMdivW :: new (self , 0) } # [doc = "Bits 16:22 - 22:16\\]
NDIV value for the PLL DIG Input clock divider settings .NDIV value directly programs the 7-bit pre- divider. Divide value ranges from 2 to 127. NDIV value has to be chosen based on the REF_CLKIN frequency so as to get the internal reference frequency of the PLL closest to 2Mhz"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_ndiv (& mut self) -> CfgPlldigNdivW < PlldigMdivNdivSpec > { CfgPlldigNdivW :: new (self , 16) } } # [doc = "PLLDIG_MDIV_NDIV\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_mdiv_ndiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_mdiv_ndiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigMdivNdivSpec ; impl crate :: RegisterSpec for PlldigMdivNdivSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_mdiv_ndiv::R`](R) reader structure"]
impl crate :: Readable for PlldigMdivNdivSpec { } # [doc = "`write(|w| ..)` method takes [`plldig_mdiv_ndiv::W`](W) writer structure"]
impl crate :: Writable for PlldigMdivNdivSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_MDIV_NDIV to value 0"]
impl crate :: Resettable for PlldigMdivNdivSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_CTRL (rw) register accessor: PLLDIG_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_ctrl`]
module"]
# [doc (alias = "PLLDIG_CTRL")]
pub type PlldigCtrl = crate :: Reg < plldig_ctrl :: PlldigCtrlSpec > ; # [doc = "PLLDIG_CTRL"]
pub mod plldig_ctrl { # [doc = "Register `PLLDIG_CTRL` reader"]
pub type R = crate :: R < PlldigCtrlSpec > ; # [doc = "Register `PLLDIG_CTRL` writer"]
pub type W = crate :: W < PlldigCtrlSpec > ; # [doc = "Field `cfg_plldig_ctrl` reader - 31:0\\]
PLL DIG test controls"]
pub type CfgPlldigCtrlR = crate :: FieldReader < u32 > ; # [doc = "Field `cfg_plldig_ctrl` writer - 31:0\\]
PLL DIG test controls"]
pub type CfgPlldigCtrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
PLL DIG test controls"]
# [inline (always)]
pub fn cfg_plldig_ctrl (& self) -> CfgPlldigCtrlR { CfgPlldigCtrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
PLL DIG test controls"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_ctrl (& mut self) -> CfgPlldigCtrlW < PlldigCtrlSpec > { CfgPlldigCtrlW :: new (self , 0) } } # [doc = "PLLDIG_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigCtrlSpec ; impl crate :: RegisterSpec for PlldigCtrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_ctrl::R`](R) reader structure"]
impl crate :: Readable for PlldigCtrlSpec { } # [doc = "`write(|w| ..)` method takes [`plldig_ctrl::W`](W) writer structure"]
impl crate :: Writable for PlldigCtrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_CTRL to value 0"]
impl crate :: Resettable for PlldigCtrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_MODE_EN (rw) register accessor: PLLDIG_MODE_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_mode_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_mode_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_mode_en`]
module"]
# [doc (alias = "PLLDIG_MODE_EN")]
pub type PlldigModeEn = crate :: Reg < plldig_mode_en :: PlldigModeEnSpec > ; # [doc = "PLLDIG_MODE_EN"]
pub mod plldig_mode_en { # [doc = "Register `PLLDIG_MODE_EN` reader"]
pub type R = crate :: R < PlldigModeEnSpec > ; # [doc = "Register `PLLDIG_MODE_EN` writer"]
pub type W = crate :: W < PlldigModeEnSpec > ; # [doc = "Field `cfg_plldig_highfreq_mode_en` reader - 0:0\\]
PLL DIG high frequency mode operation"]
pub type CfgPlldigHighfreqModeEnR = crate :: BitReader ; # [doc = "Field `cfg_plldig_highfreq_mode_en` writer - 0:0\\]
PLL DIG high frequency mode operation"]
pub type CfgPlldigHighfreqModeEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `cfg_plldig_lowfreq_mode_en` reader - 16:16\\]
PLL DIG high frequency mode operation, Divide by 2 the PLL clock out"]
pub type CfgPlldigLowfreqModeEnR = crate :: BitReader ; # [doc = "Field `cfg_plldig_lowfreq_mode_en` writer - 16:16\\]
PLL DIG high frequency mode operation, Divide by 2 the PLL clock out"]
pub type CfgPlldigLowfreqModeEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
PLL DIG high frequency mode operation"]
# [inline (always)]
pub fn cfg_plldig_highfreq_mode_en (& self) -> CfgPlldigHighfreqModeEnR { CfgPlldigHighfreqModeEnR :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - 16:16\\]
PLL DIG high frequency mode operation, Divide by 2 the PLL clock out"]
# [inline (always)]
pub fn cfg_plldig_lowfreq_mode_en (& self) -> CfgPlldigLowfreqModeEnR { CfgPlldigLowfreqModeEnR :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
PLL DIG high frequency mode operation"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_highfreq_mode_en (& mut self) -> CfgPlldigHighfreqModeEnW < PlldigModeEnSpec > { CfgPlldigHighfreqModeEnW :: new (self , 0) } # [doc = "Bit 16 - 16:16\\]
PLL DIG high frequency mode operation, Divide by 2 the PLL clock out"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_lowfreq_mode_en (& mut self) -> CfgPlldigLowfreqModeEnW < PlldigModeEnSpec > { CfgPlldigLowfreqModeEnW :: new (self , 16) } } # [doc = "PLLDIG_MODE_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_mode_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_mode_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigModeEnSpec ; impl crate :: RegisterSpec for PlldigModeEnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_mode_en::R`](R) reader structure"]
impl crate :: Readable for PlldigModeEnSpec { } # [doc = "`write(|w| ..)` method takes [`plldig_mode_en::W`](W) writer structure"]
impl crate :: Writable for PlldigModeEnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_MODE_EN to value 0"]
impl crate :: Resettable for PlldigModeEnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_APLL_SW_DIS_DELAY1 (rw) register accessor: PLLDIG_APLL_SW_DIS_DELAY1\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_apll_sw_dis_delay1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_apll_sw_dis_delay1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_apll_sw_dis_delay1`]
module"]
# [doc (alias = "PLLDIG_APLL_SW_DIS_DELAY1")]
pub type PlldigApllSwDisDelay1 = crate :: Reg < plldig_apll_sw_dis_delay1 :: PlldigApllSwDisDelay1Spec > ; # [doc = "PLLDIG_APLL_SW_DIS_DELAY1"]
pub mod plldig_apll_sw_dis_delay1 { # [doc = "Register `PLLDIG_APLL_SW_DIS_DELAY1` reader"]
pub type R = crate :: R < PlldigApllSwDisDelay1Spec > ; # [doc = "Register `PLLDIG_APLL_SW_DIS_DELAY1` writer"]
pub type W = crate :: W < PlldigApllSwDisDelay1Spec > ; # [doc = "Field `cfg_apll_auto_switch_delay` reader - 15:0\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
pub type CfgApllAutoSwitchDelayR = crate :: FieldReader < u16 > ; # [doc = "Field `cfg_apll_auto_switch_delay` writer - 15:0\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
pub type CfgApllAutoSwitchDelayW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `cfg_plldig_auto_switch_delay` reader - 31:16\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
pub type CfgPlldigAutoSwitchDelayR = crate :: FieldReader < u16 > ; # [doc = "Field `cfg_plldig_auto_switch_delay` writer - 31:16\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
pub type CfgPlldigAutoSwitchDelayW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
# [inline (always)]
pub fn cfg_apll_auto_switch_delay (& self) -> CfgApllAutoSwitchDelayR { CfgApllAutoSwitchDelayR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
# [inline (always)]
pub fn cfg_plldig_auto_switch_delay (& self) -> CfgPlldigAutoSwitchDelayR { CfgPlldigAutoSwitchDelayR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
# [inline (always)]
# [must_use]
pub fn cfg_apll_auto_switch_delay (& mut self) -> CfgApllAutoSwitchDelayW < PlldigApllSwDisDelay1Spec > { CfgApllAutoSwitchDelayW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Delay to switch the PLL clock source when the auto PLL switch mode is enable"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_auto_switch_delay (& mut self) -> CfgPlldigAutoSwitchDelayW < PlldigApllSwDisDelay1Spec > { CfgPlldigAutoSwitchDelayW :: new (self , 16) } } # [doc = "PLLDIG_APLL_SW_DIS_DELAY1\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_apll_sw_dis_delay1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_apll_sw_dis_delay1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigApllSwDisDelay1Spec ; impl crate :: RegisterSpec for PlldigApllSwDisDelay1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_apll_sw_dis_delay1::R`](R) reader structure"]
impl crate :: Readable for PlldigApllSwDisDelay1Spec { } # [doc = "`write(|w| ..)` method takes [`plldig_apll_sw_dis_delay1::W`](W) writer structure"]
impl crate :: Writable for PlldigApllSwDisDelay1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_APLL_SW_DIS_DELAY1 to value 0"]
impl crate :: Resettable for PlldigApllSwDisDelay1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_APLL_SW_DIS_DELAY2 (rw) register accessor: PLLDIG_APLL_SW_DIS_DELAY2\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_apll_sw_dis_delay2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_apll_sw_dis_delay2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_apll_sw_dis_delay2`]
module"]
# [doc (alias = "PLLDIG_APLL_SW_DIS_DELAY2")]
pub type PlldigApllSwDisDelay2 = crate :: Reg < plldig_apll_sw_dis_delay2 :: PlldigApllSwDisDelay2Spec > ; # [doc = "PLLDIG_APLL_SW_DIS_DELAY2"]
pub mod plldig_apll_sw_dis_delay2 { # [doc = "Register `PLLDIG_APLL_SW_DIS_DELAY2` reader"]
pub type R = crate :: R < PlldigApllSwDisDelay2Spec > ; # [doc = "Register `PLLDIG_APLL_SW_DIS_DELAY2` writer"]
pub type W = crate :: W < PlldigApllSwDisDelay2Spec > ; # [doc = "Field `cfg_plldig_disable_delay` reader - 15:0\\]
Delay between the PLL clock source switching and disabling of the PLL DIG"]
pub type CfgPlldigDisableDelayR = crate :: FieldReader < u16 > ; # [doc = "Field `cfg_plldig_disable_delay` writer - 15:0\\]
Delay between the PLL clock source switching and disabling of the PLL DIG"]
pub type CfgPlldigDisableDelayW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `cfg_apll_disable_delay` reader - 31:16\\]
Delay between the PLL clock source switching and disabling of the APLL"]
pub type CfgApllDisableDelayR = crate :: FieldReader < u16 > ; # [doc = "Field `cfg_apll_disable_delay` writer - 31:16\\]
Delay between the PLL clock source switching and disabling of the APLL"]
pub type CfgApllDisableDelayW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Delay between the PLL clock source switching and disabling of the PLL DIG"]
# [inline (always)]
pub fn cfg_plldig_disable_delay (& self) -> CfgPlldigDisableDelayR { CfgPlldigDisableDelayR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - 31:16\\]
Delay between the PLL clock source switching and disabling of the APLL"]
# [inline (always)]
pub fn cfg_apll_disable_delay (& self) -> CfgApllDisableDelayR { CfgApllDisableDelayR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Delay between the PLL clock source switching and disabling of the PLL DIG"]
# [inline (always)]
# [must_use]
pub fn cfg_plldig_disable_delay (& mut self) -> CfgPlldigDisableDelayW < PlldigApllSwDisDelay2Spec > { CfgPlldigDisableDelayW :: new (self , 0) } # [doc = "Bits 16:31 - 31:16\\]
Delay between the PLL clock source switching and disabling of the APLL"]
# [inline (always)]
# [must_use]
pub fn cfg_apll_disable_delay (& mut self) -> CfgApllDisableDelayW < PlldigApllSwDisDelay2Spec > { CfgApllDisableDelayW :: new (self , 16) } } # [doc = "PLLDIG_APLL_SW_DIS_DELAY2\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_apll_sw_dis_delay2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_apll_sw_dis_delay2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigApllSwDisDelay2Spec ; impl crate :: RegisterSpec for PlldigApllSwDisDelay2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_apll_sw_dis_delay2::R`](R) reader structure"]
impl crate :: Readable for PlldigApllSwDisDelay2Spec { } # [doc = "`write(|w| ..)` method takes [`plldig_apll_sw_dis_delay2::W`](W) writer structure"]
impl crate :: Writable for PlldigApllSwDisDelay2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_APLL_SW_DIS_DELAY2 to value 0"]
impl crate :: Resettable for PlldigApllSwDisDelay2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_OVERRIDE (rw) register accessor: PLLDIG_OVERRIDE\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_override::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_override::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_override`]
module"]
# [doc (alias = "PLLDIG_OVERRIDE")]
pub type PlldigOverride = crate :: Reg < plldig_override :: PlldigOverrideSpec > ; # [doc = "PLLDIG_OVERRIDE"]
pub mod plldig_override { # [doc = "Register `PLLDIG_OVERRIDE` reader"]
pub type R = crate :: R < PlldigOverrideSpec > ; # [doc = "Register `PLLDIG_OVERRIDE` writer"]
pub type W = crate :: W < PlldigOverrideSpec > ; # [doc = "Field `cfg_sel_ov_final_plldig_apll_mux_sel` reader - 2:0\\]
Mux select control to select the override value of the fast clock src mux select 0x0 = functional value selected for the fast clock src mux select 0x7 = Override value selected for the fast clock src mux select"]
pub type CfgSelOvFinalPlldigApllMuxSelR = crate :: FieldReader ; # [doc = "Field `cfg_sel_ov_final_plldig_apll_mux_sel` writer - 2:0\\]
Mux select control to select the override value of the fast clock src mux select 0x0 = functional value selected for the fast clock src mux select 0x7 = Override value selected for the fast clock src mux select"]
pub type CfgSelOvFinalPlldigApllMuxSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `cfg_ov_final_plldig_apll_mux_sel` reader - 5:3\\]
Override control for the fast clock src mux select 0x0 = PLL DIG selected as fast clock 0x7 = APLL selected as fast clock"]
pub type CfgOvFinalPlldigApllMuxSelR = crate :: FieldReader ; # [doc = "Field `cfg_ov_final_plldig_apll_mux_sel` writer - 5:3\\]
Override control for the fast clock src mux select 0x0 = PLL DIG selected as fast clock 0x7 = APLL selected as fast clock"]
pub type CfgOvFinalPlldigApllMuxSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - 2:0\\]
Mux select control to select the override value of the fast clock src mux select 0x0 = functional value selected for the fast clock src mux select 0x7 = Override value selected for the fast clock src mux select"]
# [inline (always)]
pub fn cfg_sel_ov_final_plldig_apll_mux_sel (& self) -> CfgSelOvFinalPlldigApllMuxSelR { CfgSelOvFinalPlldigApllMuxSelR :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - 5:3\\]
Override control for the fast clock src mux select 0x0 = PLL DIG selected as fast clock 0x7 = APLL selected as fast clock"]
# [inline (always)]
pub fn cfg_ov_final_plldig_apll_mux_sel (& self) -> CfgOvFinalPlldigApllMuxSelR { CfgOvFinalPlldigApllMuxSelR :: new (((self . bits >> 3) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - 2:0\\]
Mux select control to select the override value of the fast clock src mux select 0x0 = functional value selected for the fast clock src mux select 0x7 = Override value selected for the fast clock src mux select"]
# [inline (always)]
# [must_use]
pub fn cfg_sel_ov_final_plldig_apll_mux_sel (& mut self) -> CfgSelOvFinalPlldigApllMuxSelW < PlldigOverrideSpec > { CfgSelOvFinalPlldigApllMuxSelW :: new (self , 0) } # [doc = "Bits 3:5 - 5:3\\]
Override control for the fast clock src mux select 0x0 = PLL DIG selected as fast clock 0x7 = APLL selected as fast clock"]
# [inline (always)]
# [must_use]
pub fn cfg_ov_final_plldig_apll_mux_sel (& mut self) -> CfgOvFinalPlldigApllMuxSelW < PlldigOverrideSpec > { CfgOvFinalPlldigApllMuxSelW :: new (self , 3) } } # [doc = "PLLDIG_OVERRIDE\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_override::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_override::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigOverrideSpec ; impl crate :: RegisterSpec for PlldigOverrideSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_override::R`](R) reader structure"]
impl crate :: Readable for PlldigOverrideSpec { } # [doc = "`write(|w| ..)` method takes [`plldig_override::W`](W) writer structure"]
impl crate :: Writable for PlldigOverrideSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_OVERRIDE to value 0"]
impl crate :: Resettable for PlldigOverrideSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PLLDIG_STATUS (rw) register accessor: PLLDIG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plldig_status`]
module"]
# [doc (alias = "PLLDIG_STATUS")]
pub type PlldigStatus = crate :: Reg < plldig_status :: PlldigStatusSpec > ; # [doc = "PLLDIG_STATUS"]
pub mod plldig_status { # [doc = "Register `PLLDIG_STATUS` reader"]
pub type R = crate :: R < PlldigStatusSpec > ; # [doc = "Register `PLLDIG_STATUS` writer"]
pub type W = crate :: W < PlldigStatusSpec > ; # [doc = "Field `clkm_xtal_freq` reader - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
pub type ClkmXtalFreqR = crate :: FieldReader ; # [doc = "Field `clkm_xtal_freq` writer - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
pub type ClkmXtalFreqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `plldig_lockmon` reader - 8:8\\]
PLL DIG lockmon status"]
pub type PlldigLockmonR = crate :: BitReader ; # [doc = "Field `plldig_lockmon` writer - 8:8\\]
PLL DIG lockmon status"]
pub type PlldigLockmonW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
# [inline (always)]
pub fn clkm_xtal_freq (& self) -> ClkmXtalFreqR { ClkmXtalFreqR :: new ((self . bits & 3) as u8) } # [doc = "Bit 8 - 8:8\\]
PLL DIG lockmon status"]
# [inline (always)]
pub fn plldig_lockmon (& self) -> PlldigLockmonR { PlldigLockmonR :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz"]
# [inline (always)]
# [must_use]
pub fn clkm_xtal_freq (& mut self) -> ClkmXtalFreqW < PlldigStatusSpec > { ClkmXtalFreqW :: new (self , 0) } # [doc = "Bit 8 - 8:8\\]
PLL DIG lockmon status"]
# [inline (always)]
# [must_use]
pub fn plldig_lockmon (& mut self) -> PlldigLockmonW < PlldigStatusSpec > { PlldigLockmonW :: new (self , 8) } } # [doc = "PLLDIG_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`plldig_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plldig_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PlldigStatusSpec ; impl crate :: RegisterSpec for PlldigStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`plldig_status::R`](R) reader structure"]
impl crate :: Readable for PlldigStatusSpec { } # [doc = "`write(|w| ..)` method takes [`plldig_status::W`](W) writer structure"]
impl crate :: Writable for PlldigStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PLLDIG_STATUS to value 0"]
impl crate :: Resettable for PlldigStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FAST_CLK_MUX_POSTDIV (rw) register accessor: FAST_CLK_MUX_POSTDIV\n\nYou can [`read`](crate::Reg::read) this register and get [`fast_clk_mux_postdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fast_clk_mux_postdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fast_clk_mux_postdiv`]
module"]
# [doc (alias = "FAST_CLK_MUX_POSTDIV")]
pub type FastClkMuxPostdiv = crate :: Reg < fast_clk_mux_postdiv :: FastClkMuxPostdivSpec > ; # [doc = "FAST_CLK_MUX_POSTDIV"]
pub mod fast_clk_mux_postdiv { # [doc = "Register `FAST_CLK_MUX_POSTDIV` reader"]
pub type R = crate :: R < FastClkMuxPostdivSpec > ; # [doc = "Register `FAST_CLK_MUX_POSTDIV` writer"]
pub type W = crate :: W < FastClkMuxPostdivSpec > ; # [doc = "Field `currdivr` reader - 3:0\\]
Status shows the current divider value choosen for FAST_CLK."]
pub type CurrdivrR = crate :: FieldReader ; # [doc = "Field `currdivr` writer - 3:0\\]
Status shows the current divider value choosen for FAST_CLK."]
pub type CurrdivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `divr` reader - 15:4\\]
Divider value for FAST selected clock. Data should be loaded as multibit. For example: if divider value of 8 (1000) needs to be selected then '100010001000' should be configured to the register."]
pub type DivrR = crate :: FieldReader < u16 > ; # [doc = "Field `divr` writer - 15:4\\]
Divider value for FAST selected clock. Data should be loaded as multibit. For example: if divider value of 8 (1000) needs to be selected then '100010001000' should be configured to the register."]
pub type DivrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
Status shows the current divider value choosen for FAST_CLK."]
# [inline (always)]
pub fn currdivr (& self) -> CurrdivrR { CurrdivrR :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - 15:4\\]
Divider value for FAST selected clock. Data should be loaded as multibit. For example: if divider value of 8 (1000) needs to be selected then '100010001000' should be configured to the register."]
# [inline (always)]
pub fn divr (& self) -> DivrR { DivrR :: new (((self . bits >> 4) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
Status shows the current divider value choosen for FAST_CLK."]
# [inline (always)]
# [must_use]
pub fn currdivr (& mut self) -> CurrdivrW < FastClkMuxPostdivSpec > { CurrdivrW :: new (self , 0) } # [doc = "Bits 4:15 - 15:4\\]
Divider value for FAST selected clock. Data should be loaded as multibit. For example: if divider value of 8 (1000) needs to be selected then '100010001000' should be configured to the register."]
# [inline (always)]
# [must_use]
pub fn divr (& mut self) -> DivrW < FastClkMuxPostdivSpec > { DivrW :: new (self , 4) } } # [doc = "FAST_CLK_MUX_POSTDIV\n\nYou can [`read`](crate::Reg::read) this register and get [`fast_clk_mux_postdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fast_clk_mux_postdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FastClkMuxPostdivSpec ; impl crate :: RegisterSpec for FastClkMuxPostdivSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fast_clk_mux_postdiv::R`](R) reader structure"]
impl crate :: Readable for FastClkMuxPostdivSpec { } # [doc = "`write(|w| ..)` method takes [`fast_clk_mux_postdiv::W`](W) writer structure"]
impl crate :: Writable for FastClkMuxPostdivSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FAST_CLK_MUX_POSTDIV to value 0"]
impl crate :: Resettable for FastClkMuxPostdivSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FAST_CLK_STATUS (rw) register accessor: FAST_CLK_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fast_clk_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fast_clk_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fast_clk_status`]
module"]
# [doc (alias = "FAST_CLK_STATUS")]
pub type FastClkStatus = crate :: Reg < fast_clk_status :: FastClkStatusSpec > ; # [doc = "FAST_CLK_STATUS"]
pub mod fast_clk_status { # [doc = "Register `FAST_CLK_STATUS` reader"]
pub type R = crate :: R < FastClkStatusSpec > ; # [doc = "Register `FAST_CLK_STATUS` writer"]
pub type W = crate :: W < FastClkStatusSpec > ; # [doc = "Field `currclk` reader - 1:0\\]
Current Clock selected by GCM Clock Mux 0x1 : PLLDIG 0x2 : APLL"]
pub type CurrclkR = crate :: FieldReader ; # [doc = "Field `currclk` writer - 1:0\\]
Current Clock selected by GCM Clock Mux 0x1 : PLLDIG 0x2 : APLL"]
pub type CurrclkW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Current Clock selected by GCM Clock Mux 0x1 : PLLDIG 0x2 : APLL"]
# [inline (always)]
pub fn currclk (& self) -> CurrclkR { CurrclkR :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Current Clock selected by GCM Clock Mux 0x1 : PLLDIG 0x2 : APLL"]
# [inline (always)]
# [must_use]
pub fn currclk (& mut self) -> CurrclkW < FastClkStatusSpec > { CurrclkW :: new (self , 0) } } # [doc = "FAST_CLK_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fast_clk_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fast_clk_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FastClkStatusSpec ; impl crate :: RegisterSpec for FastClkStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fast_clk_status::R`](R) reader structure"]
impl crate :: Readable for FastClkStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fast_clk_status::W`](W) writer structure"]
impl crate :: Writable for FastClkStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FAST_CLK_STATUS to value 0"]
impl crate :: Resettable for FastClkStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK0 (rw) register accessor: - KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick0`]
module"]
# [doc (alias = "LOCK0_KICK0")]
pub type Lock0Kick0 = crate :: Reg < lock0_kick0 :: Lock0Kick0Spec > ; # [doc = "- KICK0 component"]
pub mod lock0_kick0 { # [doc = "Register `LOCK0_KICK0` reader"]
pub type R = crate :: R < Lock0Kick0Spec > ; # [doc = "Register `LOCK0_KICK0` writer"]
pub type W = crate :: W < Lock0Kick0Spec > ; # [doc = "Field `KICK0_COMPONENT` reader - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK0_COMPONENT` writer - 31:0\\]
- KICK0 component"]
pub type Kick0ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
pub fn kick0_component (& self) -> Kick0ComponentR { Kick0ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK0 component"]
# [inline (always)]
# [must_use]
pub fn kick0_component (& mut self) -> Kick0ComponentW < Lock0Kick0Spec > { Kick0ComponentW :: new (self , 0) } } # [doc = "- KICK0 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick0Spec ; impl crate :: RegisterSpec for Lock0Kick0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick0::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick0Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick0::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK0 to value 0"]
impl crate :: Resettable for Lock0Kick0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "LOCK0_KICK1 (rw) register accessor: - KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock0_kick1`]
module"]
# [doc (alias = "LOCK0_KICK1")]
pub type Lock0Kick1 = crate :: Reg < lock0_kick1 :: Lock0Kick1Spec > ; # [doc = "- KICK1 component"]
pub mod lock0_kick1 { # [doc = "Register `LOCK0_KICK1` reader"]
pub type R = crate :: R < Lock0Kick1Spec > ; # [doc = "Register `LOCK0_KICK1` writer"]
pub type W = crate :: W < Lock0Kick1Spec > ; # [doc = "Field `KICK1_COMPONENT` reader - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentR = crate :: FieldReader < u32 > ; # [doc = "Field `KICK1_COMPONENT` writer - 31:0\\]
- KICK1 component"]
pub type Kick1ComponentW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
pub fn kick1_component (& self) -> Kick1ComponentR { Kick1ComponentR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
- KICK1 component"]
# [inline (always)]
# [must_use]
pub fn kick1_component (& mut self) -> Kick1ComponentW < Lock0Kick1Spec > { Kick1ComponentW :: new (self , 0) } } # [doc = "- KICK1 component\n\nYou can [`read`](crate::Reg::read) this register and get [`lock0_kick1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock0_kick1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lock0Kick1Spec ; impl crate :: RegisterSpec for Lock0Kick1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`lock0_kick1::R`](R) reader structure"]
impl crate :: Readable for Lock0Kick1Spec { } # [doc = "`write(|w| ..)` method takes [`lock0_kick1::W`](W) writer structure"]
impl crate :: Writable for Lock0Kick1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LOCK0_KICK1 to value 0"]
impl crate :: Resettable for Lock0Kick1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_raw_status (rw) register accessor: Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw_status`]
module"]
# [doc (alias = "intr_raw_status")]
pub type IntrRawStatus = crate :: Reg < intr_raw_status :: IntrRawStatusSpec > ; # [doc = "Interrupt Raw Status/Set Register"]
pub mod intr_raw_status { # [doc = "Register `intr_raw_status` reader"]
pub type R = crate :: R < IntrRawStatusSpec > ; # [doc = "Register `intr_raw_status` writer"]
pub type W = crate :: W < IntrRawStatusSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrRawStatusSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrRawStatusSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrRawStatusSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrRawStatusSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Raw Status/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrRawStatusSpec ; impl crate :: RegisterSpec for IntrRawStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_raw_status::R`](R) reader structure"]
impl crate :: Readable for IntrRawStatusSpec { } # [doc = "`write(|w| ..)` method takes [`intr_raw_status::W`](W) writer structure"]
impl crate :: Writable for IntrRawStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_raw_status to value 0"]
impl crate :: Resettable for IntrRawStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enabled_status_clear (rw) register accessor: Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enabled_status_clear`]
module"]
# [doc (alias = "intr_enabled_status_clear")]
pub type IntrEnabledStatusClear = crate :: Reg < intr_enabled_status_clear :: IntrEnabledStatusClearSpec > ; # [doc = "Interrupt Enabled Status/Clear register"]
pub mod intr_enabled_status_clear { # [doc = "Register `intr_enabled_status_clear` reader"]
pub type R = crate :: R < IntrEnabledStatusClearSpec > ; # [doc = "Register `intr_enabled_status_clear` writer"]
pub type W = crate :: W < IntrEnabledStatusClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` reader - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_R = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR_` writer - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type ProtectionViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` reader - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_R = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR_` writer - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type AddressingViolationError_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error_ (& self) -> ProtectionViolationError_R { ProtectionViolationError_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error_ (& self) -> AddressingViolationError_R { AddressingViolationError_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error_ (& mut self) -> ProtectionViolationError_W < IntrEnabledStatusClearSpec > { ProtectionViolationError_W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error_ (& mut self) -> AddressingViolationError_W < IntrEnabledStatusClearSpec > { AddressingViolationError_W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnabledStatusClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnabledStatusClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enabled Status/Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enabled_status_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enabled_status_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnabledStatusClearSpec ; impl crate :: RegisterSpec for IntrEnabledStatusClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enabled_status_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnabledStatusClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enabled_status_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnabledStatusClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enabled_status_clear to value 0"]
impl crate :: Resettable for IntrEnabledStatusClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable`]
module"]
# [doc (alias = "intr_enable")]
pub type IntrEnable = crate :: Reg < intr_enable :: IntrEnableSpec > ; # [doc = "Interrupt Enable register"]
pub mod intr_enable { # [doc = "Register `intr_enable` reader"]
pub type R = crate :: R < IntrEnableSpec > ; # [doc = "Register `intr_enable` writer"]
pub type W = crate :: W < IntrEnableSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSpec ; impl crate :: RegisterSpec for IntrEnableSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable to value 0"]
impl crate :: Resettable for IntrEnableSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "intr_enable_clear (rw) register accessor: Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "intr_enable_clear")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "Interrupt Enable Clear register"]
pub mod intr_enable_clear { # [doc = "Register `intr_enable_clear` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `intr_enable_clear` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` reader - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorR = crate :: BitReader ; # [doc = "Field `PROTECTION_VIOLATION_ERROR` writer - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type ProtectionViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` reader - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorR = crate :: BitReader ; # [doc = "Field `ADDRESSING_VIOLATION_ERROR` writer - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type AddressingViolationErrorW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KICK_ACCESS_VIOLATION` reader - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationR = crate :: BitReader ; # [doc = "Field `KICK_ACCESS_VIOLATION` writer - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type KickAccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` reader - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationR = crate :: BitReader ; # [doc = "Field `PROXY0_ACCESS_VIOLATION` writer - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
pub type Proxy0AccessViolationW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn protection_violation_error (& self) -> ProtectionViolationErrorR { ProtectionViolationErrorR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn addressing_violation_error (& self) -> AddressingViolationErrorR { AddressingViolationErrorR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn kick_access_violation (& self) -> KickAccessViolationR { KickAccessViolationR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
pub fn proxy0_access_violation (& self) -> Proxy0AccessViolationR { Proxy0AccessViolationR :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn protection_violation_error (& mut self) -> ProtectionViolationErrorW < IntrEnableClearSpec > { ProtectionViolationErrorW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn addressing_violation_error (& mut self) -> AddressingViolationErrorW < IntrEnableClearSpec > { AddressingViolationErrorW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn kick_access_violation (& mut self) -> KickAccessViolationW < IntrEnableClearSpec > { KickAccessViolationW :: new (self , 2) } # [doc = "Bit 3 - 3:3\\]
Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn proxy0_access_violation (& mut self) -> Proxy0AccessViolationW < IntrEnableClearSpec > { Proxy0AccessViolationW :: new (self , 3) } } # [doc = "Interrupt Enable Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets intr_enable_clear to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "eoi (rw) register accessor: EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi`]
module"]
# [doc (alias = "eoi")]
pub type Eoi = crate :: Reg < eoi :: EoiSpec > ; # [doc = "EOI register"]
pub mod eoi { # [doc = "Register `eoi` reader"]
pub type R = crate :: R < EoiSpec > ; # [doc = "Register `eoi` writer"]
pub type W = crate :: W < EoiSpec > ; # [doc = "Field `EOI_VECTOR_VALUE_` reader - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_R = crate :: FieldReader ; # [doc = "Field `EOI_VECTOR_VALUE_` writer - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
pub type EoiVectorValue_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
pub fn eoi_vector_value_ (& self) -> EoiVectorValue_R { EoiVectorValue_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
EOI vector value. Write this with interrupt distribution value in the chip."]
# [inline (always)]
# [must_use]
pub fn eoi_vector_value_ (& mut self) -> EoiVectorValue_W < EoiSpec > { EoiVectorValue_W :: new (self , 0) } } # [doc = "EOI register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EoiSpec ; impl crate :: RegisterSpec for EoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`eoi::R`](R) reader structure"]
impl crate :: Readable for EoiSpec { } # [doc = "`write(|w| ..)` method takes [`eoi::W`](W) writer structure"]
impl crate :: Writable for EoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets eoi to value 0"]
impl crate :: Resettable for EoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_address (rw) register accessor: Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_address`]
module"]
# [doc (alias = "fault_address")]
pub type FaultAddress = crate :: Reg < fault_address :: FaultAddressSpec > ; # [doc = "Fault Address register"]
pub mod fault_address { # [doc = "Register `fault_address` reader"]
pub type R = crate :: R < FaultAddressSpec > ; # [doc = "Register `fault_address` writer"]
pub type W = crate :: W < FaultAddressSpec > ; # [doc = "Field `FAULT_ADDRESS_` reader - 31:0\\]
Fault Address."]
pub type FaultAddress_R = crate :: FieldReader < u32 > ; # [doc = "Field `FAULT_ADDRESS_` writer - 31:0\\]
Fault Address."]
pub type FaultAddress_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
pub fn fault_address_ (& self) -> FaultAddress_R { FaultAddress_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Fault Address."]
# [inline (always)]
# [must_use]
pub fn fault_address_ (& mut self) -> FaultAddress_W < FaultAddressSpec > { FaultAddress_W :: new (self , 0) } } # [doc = "Fault Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAddressSpec ; impl crate :: RegisterSpec for FaultAddressSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_address::R`](R) reader structure"]
impl crate :: Readable for FaultAddressSpec { } # [doc = "`write(|w| ..)` method takes [`fault_address::W`](W) writer structure"]
impl crate :: Writable for FaultAddressSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_address to value 0"]
impl crate :: Resettable for FaultAddressSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_type_status (rw) register accessor: Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_type_status`]
module"]
# [doc (alias = "fault_type_status")]
pub type FaultTypeStatus = crate :: Reg < fault_type_status :: FaultTypeStatusSpec > ; # [doc = "Fault Type Status register"]
pub mod fault_type_status { # [doc = "Register `fault_type_status` reader"]
pub type R = crate :: R < FaultTypeStatusSpec > ; # [doc = "Register `fault_type_status` writer"]
pub type W = crate :: W < FaultTypeStatusSpec > ; # [doc = "Field `FAULT_TYPE_10_0000` reader - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000R = crate :: FieldReader ; # [doc = "Field `FAULT_TYPE_10_0000` writer - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
pub type FaultType10_0000W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `NONSECURE_ACCESS_` reader - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_R = crate :: BitReader ; # [doc = "Field `NONSECURE_ACCESS_` writer - 6:6\\]
Non-secure access."]
pub type NonsecureAccess_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
pub fn fault_type_10_0000 (& self) -> FaultType10_0000R { FaultType10_0000R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
pub fn nonsecure_access_ (& self) -> NonsecureAccess_R { NonsecureAccess_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault"]
# [inline (always)]
# [must_use]
pub fn fault_type_10_0000 (& mut self) -> FaultType10_0000W < FaultTypeStatusSpec > { FaultType10_0000W :: new (self , 0) } # [doc = "Bit 6 - 6:6\\]
Non-secure access."]
# [inline (always)]
# [must_use]
pub fn nonsecure_access_ (& mut self) -> NonsecureAccess_W < FaultTypeStatusSpec > { NonsecureAccess_W :: new (self , 6) } } # [doc = "Fault Type Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_type_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_type_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultTypeStatusSpec ; impl crate :: RegisterSpec for FaultTypeStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_type_status::R`](R) reader structure"]
impl crate :: Readable for FaultTypeStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_type_status::W`](W) writer structure"]
impl crate :: Writable for FaultTypeStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_type_status to value 0"]
impl crate :: Resettable for FaultTypeStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_attr_status (rw) register accessor: Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_attr_status`]
module"]
# [doc (alias = "fault_attr_status")]
pub type FaultAttrStatus = crate :: Reg < fault_attr_status :: FaultAttrStatusSpec > ; # [doc = "Fault Attribute Status register"]
pub mod fault_attr_status { # [doc = "Register `fault_attr_status` reader"]
pub type R = crate :: R < FaultAttrStatusSpec > ; # [doc = "Register `fault_attr_status` writer"]
pub type W = crate :: W < FaultAttrStatusSpec > ; # [doc = "Field `PRIVILEGE_ID_` reader - 7:0\\]
Privilege ID."]
pub type PrivilegeId_R = crate :: FieldReader ; # [doc = "Field `PRIVILEGE_ID_` writer - 7:0\\]
Privilege ID."]
pub type PrivilegeId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ROUTE_ID_` reader - 19:8\\]
Route ID."]
pub type RouteId_R = crate :: FieldReader < u16 > ; # [doc = "Field `ROUTE_ID_` writer - 19:8\\]
Route ID."]
pub type RouteId_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `XID_` reader - 31:20\\]
XID."]
pub type Xid_R = crate :: FieldReader < u16 > ; # [doc = "Field `XID_` writer - 31:20\\]
XID."]
pub type Xid_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
pub fn privilege_id_ (& self) -> PrivilegeId_R { PrivilegeId_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
pub fn route_id_ (& self) -> RouteId_R { RouteId_R :: new (((self . bits >> 8) & 0x0fff) as u16) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
pub fn xid_ (& self) -> Xid_R { Xid_R :: new (((self . bits >> 20) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Privilege ID."]
# [inline (always)]
# [must_use]
pub fn privilege_id_ (& mut self) -> PrivilegeId_W < FaultAttrStatusSpec > { PrivilegeId_W :: new (self , 0) } # [doc = "Bits 8:19 - 19:8\\]
Route ID."]
# [inline (always)]
# [must_use]
pub fn route_id_ (& mut self) -> RouteId_W < FaultAttrStatusSpec > { RouteId_W :: new (self , 8) } # [doc = "Bits 20:31 - 31:20\\]
XID."]
# [inline (always)]
# [must_use]
pub fn xid_ (& mut self) -> Xid_W < FaultAttrStatusSpec > { Xid_W :: new (self , 20) } } # [doc = "Fault Attribute Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_attr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_attr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultAttrStatusSpec ; impl crate :: RegisterSpec for FaultAttrStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_attr_status::R`](R) reader structure"]
impl crate :: Readable for FaultAttrStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fault_attr_status::W`](W) writer structure"]
impl crate :: Writable for FaultAttrStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_attr_status to value 0"]
impl crate :: Resettable for FaultAttrStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "fault_clear (rw) register accessor: Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_clear`]
module"]
# [doc (alias = "fault_clear")]
pub type FaultClear = crate :: Reg < fault_clear :: FaultClearSpec > ; # [doc = "Fault Clear register"]
pub mod fault_clear { # [doc = "Register `fault_clear` reader"]
pub type R = crate :: R < FaultClearSpec > ; # [doc = "Register `fault_clear` writer"]
pub type W = crate :: W < FaultClearSpec > ; # [doc = "Field `FAULT_CLEAR__WRITING` reader - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingR = crate :: BitReader ; # [doc = "Field `FAULT_CLEAR__WRITING` writer - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
pub type FaultClear_WritingW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
pub fn fault_clear__writing (& self) -> FaultClear_WritingR { FaultClear_WritingR :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn fault_clear__writing (& mut self) -> FaultClear_WritingW < FaultClearSpec > { FaultClear_WritingW :: new (self , 0) } } # [doc = "Fault Clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FaultClearSpec ; impl crate :: RegisterSpec for FaultClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fault_clear::R`](R) reader structure"]
impl crate :: Readable for FaultClearSpec { } # [doc = "`write(|w| ..)` method takes [`fault_clear::W`](W) writer structure"]
impl crate :: Writable for FaultClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets fault_clear to value 0"]
impl crate :: Resettable for FaultClearSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "PBIST"]
pub struct Pbist { _marker : PhantomData < * const () > } unsafe impl Send for Pbist { } impl Pbist { # [doc = r"Pointer to the register block"]
pub const PTR : * const pbist :: RegisterBlock = 0x5c02_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const pbist :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for Pbist { type Target = pbist :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for Pbist { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Pbist") . finish () } } # [doc = "PBIST"]
pub mod pbist { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { reserved : Reserved , _reserved1 : [u8 ; 0x0160]
, pbist_dlr : PbistDlr , _reserved2 : [u8 ; 0x06]
, pbist_pc : PbistPc , _reserved3 : [u8 ; 0x13]
, pbist_pact : PbistPact , _reserved4 : [u8 ; 0x07]
, pbist_ovr : PbistOvr , _reserved5 : [u8 ; 0x07]
, pbist_fsfr0 : PbistFsfr0 , pbist_fsfr1 : PbistFsfr1 , _reserved7 : [u8 ; 0x28]
, pbist_rom : PbistRom , _reserved8 : [u8 ; 0x03]
, pbist_algo : PbistAlgo , pbist_rinfol : PbistRinfol , pbist_rinfou : PbistRinfou , } impl RegisterBlock { # [doc = "0x00 - Reserved"]
# [inline (always)]
pub const fn reserved (& self) -> & Reserved { & self . reserved } # [doc = "0x164 - Datalogger 0"]
# [inline (always)]
pub const fn pbist_dlr (& self) -> & PbistDlr { & self . pbist_dlr } # [doc = "0x16c - Program Control"]
# [inline (always)]
pub const fn pbist_pc (& self) -> & PbistPc { & self . pbist_pc } # [doc = "0x180 - Pbist Active"]
# [inline (always)]
pub const fn pbist_pact (& self) -> & PbistPact { & self . pbist_pact } # [doc = "0x188 - PBIST Overrides"]
# [inline (always)]
pub const fn pbist_ovr (& self) -> & PbistOvr { & self . pbist_ovr } # [doc = "0x190 - Fail status fail - port 0"]
# [inline (always)]
pub const fn pbist_fsfr0 (& self) -> & PbistFsfr0 { & self . pbist_fsfr0 } # [doc = "0x194 - Fail status fail - port 1"]
# [inline (always)]
pub const fn pbist_fsfr1 (& self) -> & PbistFsfr1 { & self . pbist_fsfr1 } # [doc = "0x1c0 - Rom Mask"]
# [inline (always)]
pub const fn pbist_rom (& self) -> & PbistRom { & self . pbist_rom } # [doc = "0x1c4 - ROM Algorithm Mask 0"]
# [inline (always)]
pub const fn pbist_algo (& self) -> & PbistAlgo { & self . pbist_algo } # [doc = "0x1c8 - RAM Info Mask Lower 0"]
# [inline (always)]
pub const fn pbist_rinfol (& self) -> & PbistRinfol { & self . pbist_rinfol } # [doc = "0x1cc - RAM Info Mask Upper 0"]
# [inline (always)]
pub const fn pbist_rinfou (& self) -> & PbistRinfou { & self . pbist_rinfou } } # [doc = "RESERVED (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserved`]
module"]
# [doc (alias = "RESERVED")]
pub type Reserved = crate :: Reg < reserved :: ReservedSpec > ; # [doc = "Reserved"]
pub mod reserved { # [doc = "Register `RESERVED` reader"]
pub type R = crate :: R < ReservedSpec > ; # [doc = "Register `RESERVED` writer"]
pub type W = crate :: W < ReservedSpec > ; impl W { } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`reserved::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reserved::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ReservedSpec ; impl crate :: RegisterSpec for ReservedSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`reserved::R`](R) reader structure"]
impl crate :: Readable for ReservedSpec { } # [doc = "`write(|w| ..)` method takes [`reserved::W`](W) writer structure"]
impl crate :: Writable for ReservedSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RESERVED to value 0"]
impl crate :: Resettable for ReservedSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIST_DLR (rw) register accessor: Datalogger 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_dlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_dlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_dlr`]
module"]
# [doc (alias = "PBIST_DLR")]
pub type PbistDlr = crate :: Reg < pbist_dlr :: PbistDlrSpec > ; # [doc = "Datalogger 0"]
pub mod pbist_dlr { # [doc = "Register `PBIST_DLR` reader"]
pub type R = crate :: R < PbistDlrSpec > ; # [doc = "Register `PBIST_DLR` writer"]
pub type W = crate :: W < PbistDlrSpec > ; # [doc = "Field `DLR0` reader - 7:0\\]
Datalogger Register \\[1:0\\]
: Reserved \\[2\\]
: ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM \\[3\\]
: Do not change this bit from its default value of 1 \\[4\\]
: Config access mode. Setting this bit allows the host processor to configure the PBIST controller registers \\[7:5\\]
: Reserved"]
pub type Dlr0R = crate :: FieldReader ; # [doc = "Field `DLR0` writer - 7:0\\]
Datalogger Register \\[1:0\\]
: Reserved \\[2\\]
: ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM \\[3\\]
: Do not change this bit from its default value of 1 \\[4\\]
: Config access mode. Setting this bit allows the host processor to configure the PBIST controller registers \\[7:5\\]
: Reserved"]
pub type Dlr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `DLR1` reader - 15:8\\]
Datalogger Register \\[8\\]
: Reserevd \\[9\\]
: Default Testing Mode. When in this mode, ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config, write to both this bit and bit \\[2\\]
of the Datalogger Register simultaneously \\[15:10\\]
: Reserevd"]
pub type Dlr1R = crate :: FieldReader ; # [doc = "Field `DLR1` writer - 15:8\\]
Datalogger Register \\[8\\]
: Reserevd \\[9\\]
: Default Testing Mode. When in this mode, ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config, write to both this bit and bit \\[2\\]
of the Datalogger Register simultaneously \\[15:10\\]
: Reserevd"]
pub type Dlr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Datalogger Register \\[1:0\\]
: Reserved \\[2\\]
: ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM \\[3\\]
: Do not change this bit from its default value of 1 \\[4\\]
: Config access mode. Setting this bit allows the host processor to configure the PBIST controller registers \\[7:5\\]
: Reserved"]
# [inline (always)]
pub fn dlr0 (& self) -> Dlr0R { Dlr0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
Datalogger Register \\[8\\]
: Reserevd \\[9\\]
: Default Testing Mode. When in this mode, ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config, write to both this bit and bit \\[2\\]
of the Datalogger Register simultaneously \\[15:10\\]
: Reserevd"]
# [inline (always)]
pub fn dlr1 (& self) -> Dlr1R { Dlr1R :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Datalogger Register \\[1:0\\]
: Reserved \\[2\\]
: ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM \\[3\\]
: Do not change this bit from its default value of 1 \\[4\\]
: Config access mode. Setting this bit allows the host processor to configure the PBIST controller registers \\[7:5\\]
: Reserved"]
# [inline (always)]
# [must_use]
pub fn dlr0 (& mut self) -> Dlr0W < PbistDlrSpec > { Dlr0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
Datalogger Register \\[8\\]
: Reserevd \\[9\\]
: Default Testing Mode. When in this mode, ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config, write to both this bit and bit \\[2\\]
of the Datalogger Register simultaneously \\[15:10\\]
: Reserevd"]
# [inline (always)]
# [must_use]
pub fn dlr1 (& mut self) -> Dlr1W < PbistDlrSpec > { Dlr1W :: new (self , 8) } } # [doc = "Datalogger 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_dlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_dlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistDlrSpec ; impl crate :: RegisterSpec for PbistDlrSpec { type Ux = u16 ; } # [doc = "`read()` method returns [`pbist_dlr::R`](R) reader structure"]
impl crate :: Readable for PbistDlrSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_dlr::W`](W) writer structure"]
impl crate :: Writable for PbistDlrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets PBIST_DLR to value 0"]
impl crate :: Resettable for PbistDlrSpec { const RESET_VALUE : u16 = 0 ; } } # [doc = "PBIST_PC (rw) register accessor: Program Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_pc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_pc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_pc`]
module"]
# [doc (alias = "PBIST_PC")]
pub type PbistPc = crate :: Reg < pbist_pc :: PbistPcSpec > ; # [doc = "Program Control"]
pub mod pbist_pc { # [doc = "Register `PBIST_PC` reader"]
pub type R = crate :: R < PbistPcSpec > ; # [doc = "Register `PBIST_PC` writer"]
pub type W = crate :: W < PbistPcSpec > ; # [doc = "Field `PBIST_PC` reader - 4:0\\]
TI Internal Register.Reserved for HW RnD"]
pub type PbistPcR = crate :: FieldReader ; # [doc = "Field `PBIST_PC` writer - 4:0\\]
TI Internal Register.Reserved for HW RnD"]
pub type PbistPcW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:4 - 4:0\\]
TI Internal Register.Reserved for HW RnD"]
# [inline (always)]
pub fn pbist_pc (& self) -> PbistPcR { PbistPcR :: new (self . bits & 0x1f) } } impl W { # [doc = "Bits 0:4 - 4:0\\]
TI Internal Register.Reserved for HW RnD"]
# [inline (always)]
# [must_use]
pub fn pbist_pc (& mut self) -> PbistPcW < PbistPcSpec > { PbistPcW :: new (self , 0) } } # [doc = "Program Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_pc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_pc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistPcSpec ; impl crate :: RegisterSpec for PbistPcSpec { type Ux = u8 ; } # [doc = "`read()` method returns [`pbist_pc::R`](R) reader structure"]
impl crate :: Readable for PbistPcSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_pc::W`](W) writer structure"]
impl crate :: Writable for PbistPcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets PBIST_PC to value 0"]
impl crate :: Resettable for PbistPcSpec { const RESET_VALUE : u8 = 0 ; } } # [doc = "PBIST_PACT (rw) register accessor: Pbist Active\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_pact::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_pact::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_pact`]
module"]
# [doc (alias = "PBIST_PACT")]
pub type PbistPact = crate :: Reg < pbist_pact :: PbistPactSpec > ; # [doc = "Pbist Active"]
pub mod pbist_pact { # [doc = "Register `PBIST_PACT` reader"]
pub type R = crate :: R < PbistPactSpec > ; # [doc = "Register `PBIST_PACT` writer"]
pub type W = crate :: W < PbistPactSpec > ; # [doc = "Field `PBIST_PACT` reader - 0:0\\]
Pbist Active/ROM Clock Enable Register \\[0\\]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST will remain in an almost zero-power mode. Value 0 = Disable internal PBIST clocks Value 1 = Enable internal PBIST clocks"]
pub type PbistPactR = crate :: BitReader ; # [doc = "Field `PBIST_PACT` writer - 0:0\\]
Pbist Active/ROM Clock Enable Register \\[0\\]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST will remain in an almost zero-power mode. Value 0 = Disable internal PBIST clocks Value 1 = Enable internal PBIST clocks"]
pub type PbistPactW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Pbist Active/ROM Clock Enable Register \\[0\\]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST will remain in an almost zero-power mode. Value 0 = Disable internal PBIST clocks Value 1 = Enable internal PBIST clocks"]
# [inline (always)]
pub fn pbist_pact (& self) -> PbistPactR { PbistPactR :: new (self . bits) } } impl W { # [doc = "Bit 0 - 0:0\\]
Pbist Active/ROM Clock Enable Register \\[0\\]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST will remain in an almost zero-power mode. Value 0 = Disable internal PBIST clocks Value 1 = Enable internal PBIST clocks"]
# [inline (always)]
# [must_use]
pub fn pbist_pact (& mut self) -> PbistPactW < PbistPactSpec > { PbistPactW :: new (self , 0) } } # [doc = "Pbist Active\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_pact::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_pact::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistPactSpec ; impl crate :: RegisterSpec for PbistPactSpec { type Ux = u8 ; } # [doc = "`read()` method returns [`pbist_pact::R`](R) reader structure"]
impl crate :: Readable for PbistPactSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_pact::W`](W) writer structure"]
impl crate :: Writable for PbistPactSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets PBIST_PACT to value 0"]
impl crate :: Resettable for PbistPactSpec { const RESET_VALUE : u8 = 0 ; } } # [doc = "PBIST_OVR (rw) register accessor: PBIST Overrides\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_ovr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_ovr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_ovr`]
module"]
# [doc (alias = "PBIST_OVR")]
pub type PbistOvr = crate :: Reg < pbist_ovr :: PbistOvrSpec > ; # [doc = "PBIST Overrides"]
pub mod pbist_ovr { # [doc = "Register `PBIST_OVR` reader"]
pub type R = crate :: R < PbistOvrSpec > ; # [doc = "Register `PBIST_OVR` writer"]
pub type W = crate :: W < PbistOvrSpec > ; # [doc = "Field `PBIST_OVR` reader - 3:0\\]
TI Internal Register.Reserved for HW RnD"]
pub type PbistOvrR = crate :: FieldReader ; # [doc = "Field `PBIST_OVR` writer - 3:0\\]
TI Internal Register.Reserved for HW RnD"]
pub type PbistOvrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - 3:0\\]
TI Internal Register.Reserved for HW RnD"]
# [inline (always)]
pub fn pbist_ovr (& self) -> PbistOvrR { PbistOvrR :: new (self . bits & 0x0f) } } impl W { # [doc = "Bits 0:3 - 3:0\\]
TI Internal Register.Reserved for HW RnD"]
# [inline (always)]
# [must_use]
pub fn pbist_ovr (& mut self) -> PbistOvrW < PbistOvrSpec > { PbistOvrW :: new (self , 0) } } # [doc = "PBIST Overrides\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_ovr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_ovr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistOvrSpec ; impl crate :: RegisterSpec for PbistOvrSpec { type Ux = u8 ; } # [doc = "`read()` method returns [`pbist_ovr::R`](R) reader structure"]
impl crate :: Readable for PbistOvrSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_ovr::W`](W) writer structure"]
impl crate :: Writable for PbistOvrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets PBIST_OVR to value 0"]
impl crate :: Resettable for PbistOvrSpec { const RESET_VALUE : u8 = 0 ; } } # [doc = "PBIST_FSFR0 (rw) register accessor: Fail status fail - port 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_fsfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_fsfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_fsfr0`]
module"]
# [doc (alias = "PBIST_FSFR0")]
pub type PbistFsfr0 = crate :: Reg < pbist_fsfr0 :: PbistFsfr0Spec > ; # [doc = "Fail status fail - port 0"]
pub mod pbist_fsfr0 { # [doc = "Register `PBIST_FSFR0` reader"]
pub type R = crate :: R < PbistFsfr0Spec > ; # [doc = "Register `PBIST_FSFR0` writer"]
pub type W = crate :: W < PbistFsfr0Spec > ; # [doc = "Field `PBIST_FSFR0` reader - 0:0\\]
Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
pub type PbistFsfr0R = crate :: BitReader ; # [doc = "Field `PBIST_FSFR0` writer - 0:0\\]
Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
pub type PbistFsfr0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
# [inline (always)]
pub fn pbist_fsfr0 (& self) -> PbistFsfr0R { PbistFsfr0R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
# [inline (always)]
# [must_use]
pub fn pbist_fsfr0 (& mut self) -> PbistFsfr0W < PbistFsfr0Spec > { PbistFsfr0W :: new (self , 0) } } # [doc = "Fail status fail - port 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_fsfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_fsfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistFsfr0Spec ; impl crate :: RegisterSpec for PbistFsfr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbist_fsfr0::R`](R) reader structure"]
impl crate :: Readable for PbistFsfr0Spec { } # [doc = "`write(|w| ..)` method takes [`pbist_fsfr0::W`](W) writer structure"]
impl crate :: Writable for PbistFsfr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIST_FSFR0 to value 0"]
impl crate :: Resettable for PbistFsfr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIST_FSFR1 (rw) register accessor: Fail status fail - port 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_fsfr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_fsfr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_fsfr1`]
module"]
# [doc (alias = "PBIST_FSFR1")]
pub type PbistFsfr1 = crate :: Reg < pbist_fsfr1 :: PbistFsfr1Spec > ; # [doc = "Fail status fail - port 1"]
pub mod pbist_fsfr1 { # [doc = "Register `PBIST_FSFR1` reader"]
pub type R = crate :: R < PbistFsfr1Spec > ; # [doc = "Register `PBIST_FSFR1` writer"]
pub type W = crate :: W < PbistFsfr1Spec > ; # [doc = "Field `PBIST_FSFR1` reader - 0:0\\]
Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
pub type PbistFsfr1R = crate :: BitReader ; # [doc = "Field `PBIST_FSFR1` writer - 0:0\\]
Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
pub type PbistFsfr1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
# [inline (always)]
pub fn pbist_fsfr1 (& self) -> PbistFsfr1R { PbistFsfr1R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure"]
# [inline (always)]
# [must_use]
pub fn pbist_fsfr1 (& mut self) -> PbistFsfr1W < PbistFsfr1Spec > { PbistFsfr1W :: new (self , 0) } } # [doc = "Fail status fail - port 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_fsfr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_fsfr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistFsfr1Spec ; impl crate :: RegisterSpec for PbistFsfr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbist_fsfr1::R`](R) reader structure"]
impl crate :: Readable for PbistFsfr1Spec { } # [doc = "`write(|w| ..)` method takes [`pbist_fsfr1::W`](W) writer structure"]
impl crate :: Writable for PbistFsfr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIST_FSFR1 to value 0"]
impl crate :: Resettable for PbistFsfr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIST_ROM (rw) register accessor: Rom Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_rom::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_rom::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_rom`]
module"]
# [doc (alias = "PBIST_ROM")]
pub type PbistRom = crate :: Reg < pbist_rom :: PbistRomSpec > ; # [doc = "Rom Mask"]
pub mod pbist_rom { # [doc = "Register `PBIST_ROM` reader"]
pub type R = crate :: R < PbistRomSpec > ; # [doc = "Register `PBIST_ROM` writer"]
pub type W = crate :: W < PbistRomSpec > ; # [doc = "Field `PBIST_ROM` reader - 1:0\\]
Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h = Both Algorithm and RAM information from ROM. This option should be selected for application self-test."]
pub type PbistRomR = crate :: FieldReader ; # [doc = "Field `PBIST_ROM` writer - 1:0\\]
Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h = Both Algorithm and RAM information from ROM. This option should be selected for application self-test."]
pub type PbistRomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h = Both Algorithm and RAM information from ROM. This option should be selected for application self-test."]
# [inline (always)]
pub fn pbist_rom (& self) -> PbistRomR { PbistRomR :: new (self . bits & 3) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h = Both Algorithm and RAM information from ROM. This option should be selected for application self-test."]
# [inline (always)]
# [must_use]
pub fn pbist_rom (& mut self) -> PbistRomW < PbistRomSpec > { PbistRomW :: new (self , 0) } } # [doc = "Rom Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_rom::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_rom::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistRomSpec ; impl crate :: RegisterSpec for PbistRomSpec { type Ux = u8 ; } # [doc = "`read()` method returns [`pbist_rom::R`](R) reader structure"]
impl crate :: Readable for PbistRomSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_rom::W`](W) writer structure"]
impl crate :: Writable for PbistRomSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets PBIST_ROM to value 0"]
impl crate :: Resettable for PbistRomSpec { const RESET_VALUE : u8 = 0 ; } } # [doc = "PBIST_ALGO (rw) register accessor: ROM Algorithm Mask 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_algo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_algo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_algo`]
module"]
# [doc (alias = "PBIST_ALGO")]
pub type PbistAlgo = crate :: Reg < pbist_algo :: PbistAlgoSpec > ; # [doc = "ROM Algorithm Mask 0"]
pub mod pbist_algo { # [doc = "Register `PBIST_ALGO` reader"]
pub type R = crate :: R < PbistAlgoSpec > ; # [doc = "Register `PBIST_ALGO` writer"]
pub type W = crate :: W < PbistAlgoSpec > ; # [doc = "Field `ALGO0` reader - 7:0\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo0R = crate :: FieldReader ; # [doc = "Field `ALGO0` writer - 7:0\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ALGO1` reader - 15:8\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo1R = crate :: FieldReader ; # [doc = "Field `ALGO1` writer - 15:8\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ALGO2` reader - 23:16\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo2R = crate :: FieldReader ; # [doc = "Field `ALGO2` writer - 23:16\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ALGO3` reader - 31:24\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo3R = crate :: FieldReader ; # [doc = "Field `ALGO3` writer - 31:24\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
pub type Algo3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
pub fn algo0 (& self) -> Algo0R { Algo0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
pub fn algo1 (& self) -> Algo1R { Algo1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
pub fn algo2 (& self) -> Algo2R { Algo2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
pub fn algo3 (& self) -> Algo3R { Algo3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
# [must_use]
pub fn algo0 (& mut self) -> Algo0W < PbistAlgoSpec > { Algo0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
# [must_use]
pub fn algo1 (& mut self) -> Algo1W < PbistAlgoSpec > { Algo1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
# [must_use]
pub fn algo2 (& mut self) -> Algo2W < PbistAlgoSpec > { Algo2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm."]
# [inline (always)]
# [must_use]
pub fn algo3 (& mut self) -> Algo3W < PbistAlgoSpec > { Algo3W :: new (self , 24) } } # [doc = "ROM Algorithm Mask 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_algo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_algo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistAlgoSpec ; impl crate :: RegisterSpec for PbistAlgoSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbist_algo::R`](R) reader structure"]
impl crate :: Readable for PbistAlgoSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_algo::W`](W) writer structure"]
impl crate :: Writable for PbistAlgoSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIST_ALGO to value 0"]
impl crate :: Resettable for PbistAlgoSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIST_RINFOL (rw) register accessor: RAM Info Mask Lower 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_rinfol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_rinfol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_rinfol`]
module"]
# [doc (alias = "PBIST_RINFOL")]
pub type PbistRinfol = crate :: Reg < pbist_rinfol :: PbistRinfolSpec > ; # [doc = "RAM Info Mask Lower 0"]
pub mod pbist_rinfol { # [doc = "Register `PBIST_RINFOL` reader"]
pub type R = crate :: R < PbistRinfolSpec > ; # [doc = "Register `PBIST_RINFOL` writer"]
pub type W = crate :: W < PbistRinfolSpec > ; # [doc = "Field `RINFOL0` reader - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol0R = crate :: FieldReader ; # [doc = "Field `RINFOL0` writer - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RINFOL1` reader - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol1R = crate :: FieldReader ; # [doc = "Field `RINFOL1` writer - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RINFOL2` reader - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol2R = crate :: FieldReader ; # [doc = "Field `RINFOL2` writer - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RINFOL3` reader - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol3R = crate :: FieldReader ; # [doc = "Field `RINFOL3` writer - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfol3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfol0 (& self) -> Rinfol0R { Rinfol0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfol1 (& self) -> Rinfol1R { Rinfol1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfol2 (& self) -> Rinfol2R { Rinfol2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfol3 (& self) -> Rinfol3R { Rinfol3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfol0 (& mut self) -> Rinfol0W < PbistRinfolSpec > { Rinfol0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfol1 (& mut self) -> Rinfol1W < PbistRinfolSpec > { Rinfol1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfol2 (& mut self) -> Rinfol2W < PbistRinfolSpec > { Rinfol2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfol3 (& mut self) -> Rinfol3W < PbistRinfolSpec > { Rinfol3W :: new (self , 24) } } # [doc = "RAM Info Mask Lower 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_rinfol::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_rinfol::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistRinfolSpec ; impl crate :: RegisterSpec for PbistRinfolSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbist_rinfol::R`](R) reader structure"]
impl crate :: Readable for PbistRinfolSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_rinfol::W`](W) writer structure"]
impl crate :: Writable for PbistRinfolSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIST_RINFOL to value 0"]
impl crate :: Resettable for PbistRinfolSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "PBIST_RINFOU (rw) register accessor: RAM Info Mask Upper 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_rinfou::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_rinfou::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbist_rinfou`]
module"]
# [doc (alias = "PBIST_RINFOU")]
pub type PbistRinfou = crate :: Reg < pbist_rinfou :: PbistRinfouSpec > ; # [doc = "RAM Info Mask Upper 0"]
pub mod pbist_rinfou { # [doc = "Register `PBIST_RINFOU` reader"]
pub type R = crate :: R < PbistRinfouSpec > ; # [doc = "Register `PBIST_RINFOU` writer"]
pub type W = crate :: W < PbistRinfouSpec > ; # [doc = "Field `RINFOU0` reader - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou0R = crate :: FieldReader ; # [doc = "Field `RINFOU0` writer - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RINFOU1` reader - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou1R = crate :: FieldReader ; # [doc = "Field `RINFOU1` writer - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RINFOU2` reader - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou2R = crate :: FieldReader ; # [doc = "Field `RINFOU2` writer - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `RINFOU3` reader - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou3R = crate :: FieldReader ; # [doc = "Field `RINFOU3` writer - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
pub type Rinfou3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfou0 (& self) -> Rinfou0R { Rinfou0R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfou1 (& self) -> Rinfou1R { Rinfou1R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfou2 (& self) -> Rinfou2R { Rinfou2R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:31 - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
pub fn rinfou3 (& self) -> Rinfou3R { Rinfou3R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfou0 (& mut self) -> Rinfou0W < PbistRinfouSpec > { Rinfou0W :: new (self , 0) } # [doc = "Bits 8:15 - 15:8\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfou1 (& mut self) -> Rinfou1W < PbistRinfouSpec > { Rinfou1W :: new (self , 8) } # [doc = "Bits 16:23 - 23:16\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfou2 (& mut self) -> Rinfou2W < PbistRinfouSpec > { Rinfou2W :: new (self , 16) } # [doc = "Bits 24:31 - 31:24\\]
This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group."]
# [inline (always)]
# [must_use]
pub fn rinfou3 (& mut self) -> Rinfou3W < PbistRinfouSpec > { Rinfou3W :: new (self , 24) } } # [doc = "RAM Info Mask Upper 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pbist_rinfou::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbist_rinfou::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbistRinfouSpec ; impl crate :: RegisterSpec for PbistRinfouSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pbist_rinfou::R`](R) reader structure"]
impl crate :: Readable for PbistRinfouSpec { } # [doc = "`write(|w| ..)` method takes [`pbist_rinfou::W`](W) writer structure"]
impl crate :: Writable for PbistRinfouSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PBIST_RINFOU to value 0"]
impl crate :: Resettable for PbistRinfouSpec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "TOP_DEBUGSS"]
pub struct TopDebugss { _marker : PhantomData < * const () > } unsafe impl Send for TopDebugss { } impl TopDebugss { # [doc = r"Pointer to the register block"]
pub const PTR : * const top_debugss :: RegisterBlock = 0x5ca0_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const top_debugss :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TopDebugss { type Target = top_debugss :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TopDebugss { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TopDebugss") . finish () } } # [doc = "TOP_DEBUGSS"]
pub mod top_debugss { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { onemcu_apb_base : OnemcuApbBase , _reserved1 : [u8 ; 0x0ff8]
, onemcu_apb_base_end : OnemcuApbBaseEnd , onemcu_cti_control : OnemcuCtiControl , _reserved3 : [u8 ; 0x0c]
, onemcu_cti_intack : OnemcuCtiIntack , onemcu_cti_appset : OnemcuCtiAppset , onemcu_cti_appclear : OnemcuCtiAppclear , onemcu_cti_apppulse : OnemcuCtiApppulse , onemcu_cti_inen0 : OnemcuCtiInen0 , onemcu_cti_inen1 : OnemcuCtiInen1 , onemcu_cti_inen2 : OnemcuCtiInen2 , onemcu_cti_inen3 : OnemcuCtiInen3 , onemcu_cti_inen4 : OnemcuCtiInen4 , onemcu_cti_inen5 : OnemcuCtiInen5 , onemcu_cti_inen6 : OnemcuCtiInen6 , onemcu_cti_inen7 : OnemcuCtiInen7 , _reserved15 : [u8 ; 0x60]
, onemcu_cti_outen0 : OnemcuCtiOuten0 , onemcu_cti_outen1 : OnemcuCtiOuten1 , onemcu_cti_outen2 : OnemcuCtiOuten2 , onemcu_cti_outen3 : OnemcuCtiOuten3 , onemcu_cti_outen4 : OnemcuCtiOuten4 , onemcu_cti_outen5 : OnemcuCtiOuten5 , onemcu_cti_outen6 : OnemcuCtiOuten6 , onemcu_cti_outen7 : OnemcuCtiOuten7 , _reserved23 : [u8 ; 0x70]
, onemcu_cti_triginstatus : OnemcuCtiTriginstatus , onemcu_cti_trigoutstatus : OnemcuCtiTrigoutstatus , onemcu_cti_chinstatus : OnemcuCtiChinstatus , onemcu_cti_choutstatus : OnemcuCtiChoutstatus , onemcu_cti_gate : OnemcuCtiGate , onemcu_cti_asicctl : OnemcuCtiAsicctl , _reserved29 : [u8 ; 0x0d94]
, onemcu_cti_itchinack : OnemcuCtiItchinack , onemcu_cti_ittriginack : OnemcuCtiIttriginack , onemcu_cti_itchout : OnemcuCtiItchout , onemcu_cti_ittrigout : OnemcuCtiIttrigout , onemcu_cti_itchoutack : OnemcuCtiItchoutack , onemcu_cti_ittrigoutack : OnemcuCtiIttrigoutack , onemcu_cti_itchin : OnemcuCtiItchin , onemcu_cti_ittrigin : OnemcuCtiIttrigin , _reserved37 : [u8 ; 0x04]
, onemcu_cti_itctrl : OnemcuCtiItctrl , _reserved38 : [u8 ; 0x9c]
, onemcu_cti_claim_tag_set : OnemcuCtiClaimTagSet , onemcu_cti_claim_tag_clear : OnemcuCtiClaimTagClear , _reserved40 : [u8 ; 0x08]
, onemcu_cti_lock_access_register : OnemcuCtiLockAccessRegister , onemcu_cti_lock_status_register : OnemcuCtiLockStatusRegister , onemcu_cti_authentication_status : OnemcuCtiAuthenticationStatus , _reserved43 : [u8 ; 0x0c]
, onemcu_cti_device_id : OnemcuCtiDeviceId , onemcu_cti_device_type_identifier : OnemcuCtiDeviceTypeIdentifier , onemcu_cti_peripheral_id4 : OnemcuCtiPeripheralId4 , onemcu_cti_peripheral_id5 : OnemcuCtiPeripheralId5 , onemcu_cti_peripheral_id6 : OnemcuCtiPeripheralId6 , onemcu_cti_peripheral_id7 : OnemcuCtiPeripheralId7 , onemcu_cti_peripheral_id0 : OnemcuCtiPeripheralId0 , onemcu_cti_peripheral_id1 : OnemcuCtiPeripheralId1 , onemcu_cti_peripheral_id2 : OnemcuCtiPeripheralId2 , onemcu_cti_peripheral_id3 : OnemcuCtiPeripheralId3 , onemcu_cti_component_id0 : OnemcuCtiComponentId0 , onemcu_cti_component_id1 : OnemcuCtiComponentId1 , onemcu_cti_component_id2 : OnemcuCtiComponentId2 , onemcu_cti_component_id3 : OnemcuCtiComponentId3 , onemcu_tpiu_sportsz : OnemcuTpiuSportsz , onemcu_tpiu_cportsz : OnemcuTpiuCportsz , _reserved59 : [u8 ; 0xf8]
, onemcu_tpiu_strigm : OnemcuTpiuStrigm , onemcu_tpiu_trigcnt : OnemcuTpiuTrigcnt , onemcu_tpiu_trigmul : OnemcuTpiuTrigmul , _reserved62 : [u8 ; 0xf4]
, onemcu_tpiu_ststptrn : OnemcuTpiuStstptrn , onemcu_tpiu_ctstptrn : OnemcuTpiuCtstptrn , onemcu_tpiu_tprcntr : OnemcuTpiuTprcntr , _reserved65 : [u8 ; 0xf4]
, onemcu_tpiu_ffsts : OnemcuTpiuFfsts , onemcu_tpiu_ffctrl : OnemcuTpiuFfctrl , onemcu_tpiu_fscntr : OnemcuTpiuFscntr , _reserved68 : [u8 ; 0xf4]
, onemcu_tpiu_exctlin : OnemcuTpiuExctlin , onemcu_tpiu_exctlout : OnemcuTpiuExctlout , _reserved70 : [u8 ; 0x0adc]
, onemcu_tpiu_ittrflinack : OnemcuTpiuIttrflinack , onemcu_tpiu_ittrflin : OnemcuTpiuIttrflin , onemcu_tpiu_itatbdata0 : OnemcuTpiuItatbdata0 , onemcu_tpiu_itatbctr2 : OnemcuTpiuItatbctr2 , onemcu_tpiu_itatbctr1 : OnemcuTpiuItatbctr1 , onemcu_tpiu_itatbctr0 : OnemcuTpiuItatbctr0 , _reserved76 : [u8 ; 0x04]
, onemcu_tpiu_itctrl : OnemcuTpiuItctrl , _reserved77 : [u8 ; 0x9c]
, onemcu_tpiu_claimset : OnemcuTpiuClaimset , onemcu_tpiu_claimclr : OnemcuTpiuClaimclr , _reserved79 : [u8 ; 0x08]
, onemcu_tpiu_lar : OnemcuTpiuLar , onemcu_tpiu_lsr : OnemcuTpiuLsr , onemcu_tpiu_authstatus : OnemcuTpiuAuthstatus , _reserved82 : [u8 ; 0x0c]
, onemcu_tpiu_devid : OnemcuTpiuDevid , onemcu_tpiu_devtype : OnemcuTpiuDevtype , onemcu_tpiu_pidr4 : OnemcuTpiuPidr4 , onemcu_tpiu_pidr5 : OnemcuTpiuPidr5 , onemcu_tpiu_pidr6 : OnemcuTpiuPidr6 , onemcu_tpiu_pidr7 : OnemcuTpiuPidr7 , onemcu_tpiu_pidr0 : OnemcuTpiuPidr0 , onemcu_tpiu_pidr1 : OnemcuTpiuPidr1 , onemcu_tpiu_pidr2 : OnemcuTpiuPidr2 , onemcu_tpiu_pidr3 : OnemcuTpiuPidr3 , onemcu_tpiu_cidr0 : OnemcuTpiuCidr0 , onemcu_tpiu_cidr1 : OnemcuTpiuCidr1 , onemcu_tpiu_cidr2 : OnemcuTpiuCidr2 , onemcu_tpiu_cidr3 : OnemcuTpiuCidr3 , _reserved96 : [u8 ; 0xd000]
, app_cm4_cti_control : AppCm4CtiControl , _reserved97 : [u8 ; 0x0c]
, app_cm4_cti_intack : AppCm4CtiIntack , app_cm4_cti_appset : AppCm4CtiAppset , app_cm4_cti_appclear : AppCm4CtiAppclear , app_cm4_cti_apppulse : AppCm4CtiApppulse , app_cm4_cti_inen0 : AppCm4CtiInen0 , app_cm4_cti_inen1 : AppCm4CtiInen1 , app_cm4_cti_inen2 : AppCm4CtiInen2 , app_cm4_cti_inen3 : AppCm4CtiInen3 , app_cm4_cti_inen4 : AppCm4CtiInen4 , app_cm4_cti_inen5 : AppCm4CtiInen5 , app_cm4_cti_inen6 : AppCm4CtiInen6 , app_cm4_cti_inen7 : AppCm4CtiInen7 , _reserved109 : [u8 ; 0x60]
, app_cm4_cti_outen0 : AppCm4CtiOuten0 , app_cm4_cti_outen1 : AppCm4CtiOuten1 , app_cm4_cti_outen2 : AppCm4CtiOuten2 , app_cm4_cti_outen3 : AppCm4CtiOuten3 , app_cm4_cti_outen4 : AppCm4CtiOuten4 , app_cm4_cti_outen5 : AppCm4CtiOuten5 , app_cm4_cti_outen6 : AppCm4CtiOuten6 , app_cm4_cti_outen7 : AppCm4CtiOuten7 , _reserved117 : [u8 ; 0x70]
, app_cm4_cti_triginstatus : AppCm4CtiTriginstatus , app_cm4_cti_trigoutstatus : AppCm4CtiTrigoutstatus , app_cm4_cti_chinstatus : AppCm4CtiChinstatus , app_cm4_cti_choutstatus : AppCm4CtiChoutstatus , app_cm4_cti_gate : AppCm4CtiGate , app_cm4_cti_asicctl : AppCm4CtiAsicctl , _reserved123 : [u8 ; 0x0d94]
, app_cm4_cti_itchinack : AppCm4CtiItchinack , app_cm4_cti_ittriginack : AppCm4CtiIttriginack , app_cm4_cti_itchout : AppCm4CtiItchout , app_cm4_cti_ittrigout : AppCm4CtiIttrigout , app_cm4_cti_itchoutack : AppCm4CtiItchoutack , app_cm4_cti_ittrigoutack : AppCm4CtiIttrigoutack , app_cm4_cti_itchin : AppCm4CtiItchin , app_cm4_cti_ittrigin : AppCm4CtiIttrigin , _reserved131 : [u8 ; 0x04]
, app_cm4_cti_itctrl : AppCm4CtiItctrl , _reserved132 : [u8 ; 0x9c]
, app_cm4_cti_claim_tag_set : AppCm4CtiClaimTagSet , app_cm4_cti_claim_tag_clear : AppCm4CtiClaimTagClear , _reserved134 : [u8 ; 0x08]
, app_cm4_cti_lock_access_register : AppCm4CtiLockAccessRegister , app_cm4_cti_lock_status_register : AppCm4CtiLockStatusRegister , app_cm4_cti_authentication_status : AppCm4CtiAuthenticationStatus , _reserved137 : [u8 ; 0x0c]
, app_cm4_cti_device_id : AppCm4CtiDeviceId , app_cm4_cti_device_type_identifier : AppCm4CtiDeviceTypeIdentifier , app_cm4_cti_peripheral_id4 : AppCm4CtiPeripheralId4 , app_cm4_cti_peripheral_id5 : AppCm4CtiPeripheralId5 , app_cm4_cti_peripheral_id6 : AppCm4CtiPeripheralId6 , app_cm4_cti_peripheral_id7 : AppCm4CtiPeripheralId7 , app_cm4_cti_peripheral_id0 : AppCm4CtiPeripheralId0 , app_cm4_cti_peripheral_id1 : AppCm4CtiPeripheralId1 , app_cm4_cti_peripheral_id2 : AppCm4CtiPeripheralId2 , app_cm4_cti_peripheral_id3 : AppCm4CtiPeripheralId3 , app_cm4_cti_component_id0 : AppCm4CtiComponentId0 , app_cm4_cti_component_id1 : AppCm4CtiComponentId1 , app_cm4_cti_component_id2 : AppCm4CtiComponentId2 , app_cm4_cti_component_id3 : AppCm4CtiComponentId3 , fec_cm3_cti_control : FecCm3CtiControl , _reserved152 : [u8 ; 0x0c]
, fec_cm3_cti_intack : FecCm3CtiIntack , fec_cm3_cti_appset : FecCm3CtiAppset , fec_cm3_cti_appclear : FecCm3CtiAppclear , fec_cm3_cti_apppulse : FecCm3CtiApppulse , fec_cm3_cti_inen0 : FecCm3CtiInen0 , fec_cm3_cti_inen1 : FecCm3CtiInen1 , fec_cm3_cti_inen2 : FecCm3CtiInen2 , fec_cm3_cti_inen3 : FecCm3CtiInen3 , fec_cm3_cti_inen4 : FecCm3CtiInen4 , fec_cm3_cti_inen5 : FecCm3CtiInen5 , fec_cm3_cti_inen6 : FecCm3CtiInen6 , fec_cm3_cti_inen7 : FecCm3CtiInen7 , _reserved164 : [u8 ; 0x60]
, fec_cm3_cti_outen0 : FecCm3CtiOuten0 , fec_cm3_cti_outen1 : FecCm3CtiOuten1 , fec_cm3_cti_outen2 : FecCm3CtiOuten2 , fec_cm3_cti_outen3 : FecCm3CtiOuten3 , fec_cm3_cti_outen4 : FecCm3CtiOuten4 , fec_cm3_cti_outen5 : FecCm3CtiOuten5 , fec_cm3_cti_outen6 : FecCm3CtiOuten6 , fec_cm3_cti_outen7 : FecCm3CtiOuten7 , _reserved172 : [u8 ; 0x70]
, fec_cm3_cti_triginstatus : FecCm3CtiTriginstatus , fec_cm3_cti_trigoutstatus : FecCm3CtiTrigoutstatus , fec_cm3_cti_chinstatus : FecCm3CtiChinstatus , fec_cm3_cti_choutstatus : FecCm3CtiChoutstatus , fec_cm3_cti_gate : FecCm3CtiGate , fec_cm3_cti_asicctl : FecCm3CtiAsicctl , _reserved178 : [u8 ; 0x0d94]
, fec_cm3_cti_itchinack : FecCm3CtiItchinack , fec_cm3_cti_ittriginack : FecCm3CtiIttriginack , fec_cm3_cti_itchout : FecCm3CtiItchout , fec_cm3_cti_ittrigout : FecCm3CtiIttrigout , fec_cm3_cti_itchoutack : FecCm3CtiItchoutack , fec_cm3_cti_ittrigoutack : FecCm3CtiIttrigoutack , fec_cm3_cti_itchin : FecCm3CtiItchin , fec_cm3_cti_ittrigin : FecCm3CtiIttrigin , _reserved186 : [u8 ; 0x04]
, fec_cm3_cti_itctrl : FecCm3CtiItctrl , _reserved187 : [u8 ; 0x9c]
, fec_cm3_cti_claim_tag_set : FecCm3CtiClaimTagSet , fec_cm3_cti_claim_tag_clear : FecCm3CtiClaimTagClear , _reserved189 : [u8 ; 0x08]
, fec_cm3_cti_lock_access_register : FecCm3CtiLockAccessRegister , fec_cm3_cti_lock_status_register : FecCm3CtiLockStatusRegister , fec_cm3_cti_authentication_status : FecCm3CtiAuthenticationStatus , _reserved192 : [u8 ; 0x0c]
, fec_cm3_cti_device_id : FecCm3CtiDeviceId , fec_cm3_cti_device_type_identifier : FecCm3CtiDeviceTypeIdentifier , fec_cm3_cti_peripheral_id4 : FecCm3CtiPeripheralId4 , fec_cm3_cti_peripheral_id5 : FecCm3CtiPeripheralId5 , fec_cm3_cti_peripheral_id6 : FecCm3CtiPeripheralId6 , fec_cm3_cti_peripheral_id7 : FecCm3CtiPeripheralId7 , fec_cm3_cti_peripheral_id0 : FecCm3CtiPeripheralId0 , fec_cm3_cti_peripheral_id1 : FecCm3CtiPeripheralId1 , fec_cm3_cti_peripheral_id2 : FecCm3CtiPeripheralId2 , fec_cm3_cti_peripheral_id3 : FecCm3CtiPeripheralId3 , fec_cm3_cti_component_id0 : FecCm3CtiComponentId0 , fec_cm3_cti_component_id1 : FecCm3CtiComponentId1 , fec_cm3_cti_component_id2 : FecCm3CtiComponentId2 , fec_cm3_cti_component_id3 : FecCm3CtiComponentId3 , } impl RegisterBlock { # [doc = "0x00 - Start Address of ROM Table"]
# [inline (always)]
pub const fn onemcu_apb_base (& self) -> & OnemcuApbBase { & self . onemcu_apb_base } # [doc = "0xffc - End Address of ROM Table"]
# [inline (always)]
pub const fn onemcu_apb_base_end (& self) -> & OnemcuApbBaseEnd { & self . onemcu_apb_base_end } # [doc = "0x1000 - http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html"]
# [inline (always)]
pub const fn onemcu_cti_control (& self) -> & OnemcuCtiControl { & self . onemcu_cti_control } # [doc = "0x1010 - ONEMCU_CTI_INTACK"]
# [inline (always)]
pub const fn onemcu_cti_intack (& self) -> & OnemcuCtiIntack { & self . onemcu_cti_intack } # [doc = "0x1014 - ONEMCU_CTI_APPSET"]
# [inline (always)]
pub const fn onemcu_cti_appset (& self) -> & OnemcuCtiAppset { & self . onemcu_cti_appset } # [doc = "0x1018 - ONEMCU_CTI_APPCLEAR"]
# [inline (always)]
pub const fn onemcu_cti_appclear (& self) -> & OnemcuCtiAppclear { & self . onemcu_cti_appclear } # [doc = "0x101c - ONEMCU_CTI_APPPULSE"]
# [inline (always)]
pub const fn onemcu_cti_apppulse (& self) -> & OnemcuCtiApppulse { & self . onemcu_cti_apppulse } # [doc = "0x1020 - ONEMCU_CTI_INEN0"]
# [inline (always)]
pub const fn onemcu_cti_inen0 (& self) -> & OnemcuCtiInen0 { & self . onemcu_cti_inen0 } # [doc = "0x1024 - ONEMCU_CTI_INEN1"]
# [inline (always)]
pub const fn onemcu_cti_inen1 (& self) -> & OnemcuCtiInen1 { & self . onemcu_cti_inen1 } # [doc = "0x1028 - ONEMCU_CTI_INEN2"]
# [inline (always)]
pub const fn onemcu_cti_inen2 (& self) -> & OnemcuCtiInen2 { & self . onemcu_cti_inen2 } # [doc = "0x102c - ONEMCU_CTI_INEN3"]
# [inline (always)]
pub const fn onemcu_cti_inen3 (& self) -> & OnemcuCtiInen3 { & self . onemcu_cti_inen3 } # [doc = "0x1030 - ONEMCU_CTI_INEN4"]
# [inline (always)]
pub const fn onemcu_cti_inen4 (& self) -> & OnemcuCtiInen4 { & self . onemcu_cti_inen4 } # [doc = "0x1034 - ONEMCU_CTI_INEN5"]
# [inline (always)]
pub const fn onemcu_cti_inen5 (& self) -> & OnemcuCtiInen5 { & self . onemcu_cti_inen5 } # [doc = "0x1038 - ONEMCU_CTI_INEN6"]
# [inline (always)]
pub const fn onemcu_cti_inen6 (& self) -> & OnemcuCtiInen6 { & self . onemcu_cti_inen6 } # [doc = "0x103c - ONEMCU_CTI_INEN7"]
# [inline (always)]
pub const fn onemcu_cti_inen7 (& self) -> & OnemcuCtiInen7 { & self . onemcu_cti_inen7 } # [doc = "0x10a0 - ONEMCU_CTI_OUTEN0"]
# [inline (always)]
pub const fn onemcu_cti_outen0 (& self) -> & OnemcuCtiOuten0 { & self . onemcu_cti_outen0 } # [doc = "0x10a4 - ONEMCU_CTI_OUTEN1"]
# [inline (always)]
pub const fn onemcu_cti_outen1 (& self) -> & OnemcuCtiOuten1 { & self . onemcu_cti_outen1 } # [doc = "0x10a8 - ONEMCU_CTI_OUTEN2"]
# [inline (always)]
pub const fn onemcu_cti_outen2 (& self) -> & OnemcuCtiOuten2 { & self . onemcu_cti_outen2 } # [doc = "0x10ac - ONEMCU_CTI_OUTEN3"]
# [inline (always)]
pub const fn onemcu_cti_outen3 (& self) -> & OnemcuCtiOuten3 { & self . onemcu_cti_outen3 } # [doc = "0x10b0 - ONEMCU_CTI_OUTEN4"]
# [inline (always)]
pub const fn onemcu_cti_outen4 (& self) -> & OnemcuCtiOuten4 { & self . onemcu_cti_outen4 } # [doc = "0x10b4 - ONEMCU_CTI_OUTEN5"]
# [inline (always)]
pub const fn onemcu_cti_outen5 (& self) -> & OnemcuCtiOuten5 { & self . onemcu_cti_outen5 } # [doc = "0x10b8 - ONEMCU_CTI_OUTEN6"]
# [inline (always)]
pub const fn onemcu_cti_outen6 (& self) -> & OnemcuCtiOuten6 { & self . onemcu_cti_outen6 } # [doc = "0x10bc - ONEMCU_CTI_OUTEN7"]
# [inline (always)]
pub const fn onemcu_cti_outen7 (& self) -> & OnemcuCtiOuten7 { & self . onemcu_cti_outen7 } # [doc = "0x1130 - ONEMCU_CTI_TRIGINSTATUS"]
# [inline (always)]
pub const fn onemcu_cti_triginstatus (& self) -> & OnemcuCtiTriginstatus { & self . onemcu_cti_triginstatus } # [doc = "0x1134 - ONEMCU_CTI_TRIGOUTSTATUS"]
# [inline (always)]
pub const fn onemcu_cti_trigoutstatus (& self) -> & OnemcuCtiTrigoutstatus { & self . onemcu_cti_trigoutstatus } # [doc = "0x1138 - ONEMCU_CTI_CHINSTATUS"]
# [inline (always)]
pub const fn onemcu_cti_chinstatus (& self) -> & OnemcuCtiChinstatus { & self . onemcu_cti_chinstatus } # [doc = "0x113c - ONEMCU_CTI_CHOUTSTATUS"]
# [inline (always)]
pub const fn onemcu_cti_choutstatus (& self) -> & OnemcuCtiChoutstatus { & self . onemcu_cti_choutstatus } # [doc = "0x1140 - ONEMCU_CTI_GATE"]
# [inline (always)]
pub const fn onemcu_cti_gate (& self) -> & OnemcuCtiGate { & self . onemcu_cti_gate } # [doc = "0x1144 - ONEMCU_CTI_ASICCTL"]
# [inline (always)]
pub const fn onemcu_cti_asicctl (& self) -> & OnemcuCtiAsicctl { & self . onemcu_cti_asicctl } # [doc = "0x1edc - ONEMCU_CTI_ITCHINACK"]
# [inline (always)]
pub const fn onemcu_cti_itchinack (& self) -> & OnemcuCtiItchinack { & self . onemcu_cti_itchinack } # [doc = "0x1ee0 - ONEMCU_CTI_ITTRIGINACK"]
# [inline (always)]
pub const fn onemcu_cti_ittriginack (& self) -> & OnemcuCtiIttriginack { & self . onemcu_cti_ittriginack } # [doc = "0x1ee4 - ONEMCU_CTI_ITCHOUT"]
# [inline (always)]
pub const fn onemcu_cti_itchout (& self) -> & OnemcuCtiItchout { & self . onemcu_cti_itchout } # [doc = "0x1ee8 - ONEMCU_CTI_ITTRIGOUT"]
# [inline (always)]
pub const fn onemcu_cti_ittrigout (& self) -> & OnemcuCtiIttrigout { & self . onemcu_cti_ittrigout } # [doc = "0x1eec - ONEMCU_CTI_ITCHOUTACK"]
# [inline (always)]
pub const fn onemcu_cti_itchoutack (& self) -> & OnemcuCtiItchoutack { & self . onemcu_cti_itchoutack } # [doc = "0x1ef0 - ONEMCU_CTI_ITTRIGOUTACK"]
# [inline (always)]
pub const fn onemcu_cti_ittrigoutack (& self) -> & OnemcuCtiIttrigoutack { & self . onemcu_cti_ittrigoutack } # [doc = "0x1ef4 - ONEMCU_CTI_ITCHIN"]
# [inline (always)]
pub const fn onemcu_cti_itchin (& self) -> & OnemcuCtiItchin { & self . onemcu_cti_itchin } # [doc = "0x1ef8 - ONEMCU_CTI_ITTRIGIN"]
# [inline (always)]
pub const fn onemcu_cti_ittrigin (& self) -> & OnemcuCtiIttrigin { & self . onemcu_cti_ittrigin } # [doc = "0x1f00 - ONEMCU_CTI_ITCTRL"]
# [inline (always)]
pub const fn onemcu_cti_itctrl (& self) -> & OnemcuCtiItctrl { & self . onemcu_cti_itctrl } # [doc = "0x1fa0 - ONEMCU_CTI_Claim_Tag_Set"]
# [inline (always)]
pub const fn onemcu_cti_claim_tag_set (& self) -> & OnemcuCtiClaimTagSet { & self . onemcu_cti_claim_tag_set } # [doc = "0x1fa4 - ONEMCU_CTI_Claim_Tag_Clear"]
# [inline (always)]
pub const fn onemcu_cti_claim_tag_clear (& self) -> & OnemcuCtiClaimTagClear { & self . onemcu_cti_claim_tag_clear } # [doc = "0x1fb0 - ONEMCU_CTI_Lock_Access_Register"]
# [inline (always)]
pub const fn onemcu_cti_lock_access_register (& self) -> & OnemcuCtiLockAccessRegister { & self . onemcu_cti_lock_access_register } # [doc = "0x1fb4 - ONEMCU_CTI_Lock_Status_Register"]
# [inline (always)]
pub const fn onemcu_cti_lock_status_register (& self) -> & OnemcuCtiLockStatusRegister { & self . onemcu_cti_lock_status_register } # [doc = "0x1fb8 - ONEMCU_CTI_Authentication_Status"]
# [inline (always)]
pub const fn onemcu_cti_authentication_status (& self) -> & OnemcuCtiAuthenticationStatus { & self . onemcu_cti_authentication_status } # [doc = "0x1fc8 - ONEMCU_CTI_Device_ID"]
# [inline (always)]
pub const fn onemcu_cti_device_id (& self) -> & OnemcuCtiDeviceId { & self . onemcu_cti_device_id } # [doc = "0x1fcc - ONEMCU_CTI_Device_Type_Identifier"]
# [inline (always)]
pub const fn onemcu_cti_device_type_identifier (& self) -> & OnemcuCtiDeviceTypeIdentifier { & self . onemcu_cti_device_type_identifier } # [doc = "0x1fd0 - ONEMCU_CTI_PeripheralID4"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id4 (& self) -> & OnemcuCtiPeripheralId4 { & self . onemcu_cti_peripheral_id4 } # [doc = "0x1fd4 - ONEMCU_CTI_PeripheralID5"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id5 (& self) -> & OnemcuCtiPeripheralId5 { & self . onemcu_cti_peripheral_id5 } # [doc = "0x1fd8 - ONEMCU_CTI_PeripheralID6"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id6 (& self) -> & OnemcuCtiPeripheralId6 { & self . onemcu_cti_peripheral_id6 } # [doc = "0x1fdc - ONEMCU_CTI_PeripheralID7"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id7 (& self) -> & OnemcuCtiPeripheralId7 { & self . onemcu_cti_peripheral_id7 } # [doc = "0x1fe0 - ONEMCU_CTI_PeripheralID0"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id0 (& self) -> & OnemcuCtiPeripheralId0 { & self . onemcu_cti_peripheral_id0 } # [doc = "0x1fe4 - ONEMCU_CTI_PeripheralID1"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id1 (& self) -> & OnemcuCtiPeripheralId1 { & self . onemcu_cti_peripheral_id1 } # [doc = "0x1fe8 - ONEMCU_CTI_PeripheralID2"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id2 (& self) -> & OnemcuCtiPeripheralId2 { & self . onemcu_cti_peripheral_id2 } # [doc = "0x1fec - ONEMCU_CTI_PeripheralID3"]
# [inline (always)]
pub const fn onemcu_cti_peripheral_id3 (& self) -> & OnemcuCtiPeripheralId3 { & self . onemcu_cti_peripheral_id3 } # [doc = "0x1ff0 - ONEMCU_CTI_Component_ID0"]
# [inline (always)]
pub const fn onemcu_cti_component_id0 (& self) -> & OnemcuCtiComponentId0 { & self . onemcu_cti_component_id0 } # [doc = "0x1ff4 - ONEMCU_CTI_Component_ID1"]
# [inline (always)]
pub const fn onemcu_cti_component_id1 (& self) -> & OnemcuCtiComponentId1 { & self . onemcu_cti_component_id1 } # [doc = "0x1ff8 - ONEMCU_CTI_Component_ID2"]
# [inline (always)]
pub const fn onemcu_cti_component_id2 (& self) -> & OnemcuCtiComponentId2 { & self . onemcu_cti_component_id2 } # [doc = "0x1ffc - ONEMCU_CTI_Component_ID3"]
# [inline (always)]
pub const fn onemcu_cti_component_id3 (& self) -> & OnemcuCtiComponentId3 { & self . onemcu_cti_component_id3 } # [doc = "0x2000 - Supported port sizes"]
# [inline (always)]
pub const fn onemcu_tpiu_sportsz (& self) -> & OnemcuTpiuSportsz { & self . onemcu_tpiu_sportsz } # [doc = "0x2004 - Current port size"]
# [inline (always)]
pub const fn onemcu_tpiu_cportsz (& self) -> & OnemcuTpiuCportsz { & self . onemcu_tpiu_cportsz } # [doc = "0x2100 - Supported trigger modes"]
# [inline (always)]
pub const fn onemcu_tpiu_strigm (& self) -> & OnemcuTpiuStrigm { & self . onemcu_tpiu_strigm } # [doc = "0x2104 - Trigger counter value"]
# [inline (always)]
pub const fn onemcu_tpiu_trigcnt (& self) -> & OnemcuTpiuTrigcnt { & self . onemcu_tpiu_trigcnt } # [doc = "0x2108 - Trigger multiplier"]
# [inline (always)]
pub const fn onemcu_tpiu_trigmul (& self) -> & OnemcuTpiuTrigmul { & self . onemcu_tpiu_trigmul } # [doc = "0x2200 - Supported test pattern/modes"]
# [inline (always)]
pub const fn onemcu_tpiu_ststptrn (& self) -> & OnemcuTpiuStstptrn { & self . onemcu_tpiu_ststptrn } # [doc = "0x2204 - Current test pattern/mode"]
# [inline (always)]
pub const fn onemcu_tpiu_ctstptrn (& self) -> & OnemcuTpiuCtstptrn { & self . onemcu_tpiu_ctstptrn } # [doc = "0x2208 - Test pattern repeat counter"]
# [inline (always)]
pub const fn onemcu_tpiu_tprcntr (& self) -> & OnemcuTpiuTprcntr { & self . onemcu_tpiu_tprcntr } # [doc = "0x2300 - Formatter and flush status"]
# [inline (always)]
pub const fn onemcu_tpiu_ffsts (& self) -> & OnemcuTpiuFfsts { & self . onemcu_tpiu_ffsts } # [doc = "0x2304 - Formatter and flush control"]
# [inline (always)]
pub const fn onemcu_tpiu_ffctrl (& self) -> & OnemcuTpiuFfctrl { & self . onemcu_tpiu_ffctrl } # [doc = "0x2308 - Formatter synchronization counter"]
# [inline (always)]
pub const fn onemcu_tpiu_fscntr (& self) -> & OnemcuTpiuFscntr { & self . onemcu_tpiu_fscntr } # [doc = "0x2400 - EXTCTL In Port"]
# [inline (always)]
pub const fn onemcu_tpiu_exctlin (& self) -> & OnemcuTpiuExctlin { & self . onemcu_tpiu_exctlin } # [doc = "0x2404 - EXTCTL Out Port"]
# [inline (always)]
pub const fn onemcu_tpiu_exctlout (& self) -> & OnemcuTpiuExctlout { & self . onemcu_tpiu_exctlout } # [doc = "0x2ee4 - Integration Register, ITTRFLINACK"]
# [inline (always)]
pub const fn onemcu_tpiu_ittrflinack (& self) -> & OnemcuTpiuIttrflinack { & self . onemcu_tpiu_ittrflinack } # [doc = "0x2ee8 - Integration Register, ITTRFLIN"]
# [inline (always)]
pub const fn onemcu_tpiu_ittrflin (& self) -> & OnemcuTpiuIttrflin { & self . onemcu_tpiu_ittrflin } # [doc = "0x2eec - Integration Register, ITATBDATA0"]
# [inline (always)]
pub const fn onemcu_tpiu_itatbdata0 (& self) -> & OnemcuTpiuItatbdata0 { & self . onemcu_tpiu_itatbdata0 } # [doc = "0x2ef0 - Integration Register, ITATBCTR2"]
# [inline (always)]
pub const fn onemcu_tpiu_itatbctr2 (& self) -> & OnemcuTpiuItatbctr2 { & self . onemcu_tpiu_itatbctr2 } # [doc = "0x2ef4 - Integration Register, ITATBCTR1"]
# [inline (always)]
pub const fn onemcu_tpiu_itatbctr1 (& self) -> & OnemcuTpiuItatbctr1 { & self . onemcu_tpiu_itatbctr1 } # [doc = "0x2ef8 - Integration Register, ITATBCTR0"]
# [inline (always)]
pub const fn onemcu_tpiu_itatbctr0 (& self) -> & OnemcuTpiuItatbctr0 { & self . onemcu_tpiu_itatbctr0 } # [doc = "0x2f00 - Integration Mode Control Register"]
# [inline (always)]
pub const fn onemcu_tpiu_itctrl (& self) -> & OnemcuTpiuItctrl { & self . onemcu_tpiu_itctrl } # [doc = "0x2fa0 - Claim Tag Set"]
# [inline (always)]
pub const fn onemcu_tpiu_claimset (& self) -> & OnemcuTpiuClaimset { & self . onemcu_tpiu_claimset } # [doc = "0x2fa4 - Claim Tag Clear"]
# [inline (always)]
pub const fn onemcu_tpiu_claimclr (& self) -> & OnemcuTpiuClaimclr { & self . onemcu_tpiu_claimclr } # [doc = "0x2fb0 - Lock status"]
# [inline (always)]
pub const fn onemcu_tpiu_lar (& self) -> & OnemcuTpiuLar { & self . onemcu_tpiu_lar } # [doc = "0x2fb4 - Lock Access"]
# [inline (always)]
pub const fn onemcu_tpiu_lsr (& self) -> & OnemcuTpiuLsr { & self . onemcu_tpiu_lsr } # [doc = "0x2fb8 - Authentication status"]
# [inline (always)]
pub const fn onemcu_tpiu_authstatus (& self) -> & OnemcuTpiuAuthstatus { & self . onemcu_tpiu_authstatus } # [doc = "0x2fc8 - Device ID"]
# [inline (always)]
pub const fn onemcu_tpiu_devid (& self) -> & OnemcuTpiuDevid { & self . onemcu_tpiu_devid } # [doc = "0x2fcc - Device type identifier"]
# [inline (always)]
pub const fn onemcu_tpiu_devtype (& self) -> & OnemcuTpiuDevtype { & self . onemcu_tpiu_devtype } # [doc = "0x2fd0 - Peripheral ID4"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr4 (& self) -> & OnemcuTpiuPidr4 { & self . onemcu_tpiu_pidr4 } # [doc = "0x2fd4 - Peripheral ID5"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr5 (& self) -> & OnemcuTpiuPidr5 { & self . onemcu_tpiu_pidr5 } # [doc = "0x2fd8 - Peripheral ID6"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr6 (& self) -> & OnemcuTpiuPidr6 { & self . onemcu_tpiu_pidr6 } # [doc = "0x2fdc - Peripheral ID7"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr7 (& self) -> & OnemcuTpiuPidr7 { & self . onemcu_tpiu_pidr7 } # [doc = "0x2fe0 - Peripheral ID0"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr0 (& self) -> & OnemcuTpiuPidr0 { & self . onemcu_tpiu_pidr0 } # [doc = "0x2fe4 - Peripheral ID1"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr1 (& self) -> & OnemcuTpiuPidr1 { & self . onemcu_tpiu_pidr1 } # [doc = "0x2fe8 - Peripheral ID2"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr2 (& self) -> & OnemcuTpiuPidr2 { & self . onemcu_tpiu_pidr2 } # [doc = "0x2fec - Peripheral ID3"]
# [inline (always)]
pub const fn onemcu_tpiu_pidr3 (& self) -> & OnemcuTpiuPidr3 { & self . onemcu_tpiu_pidr3 } # [doc = "0x2ff0 - Component ID0"]
# [inline (always)]
pub const fn onemcu_tpiu_cidr0 (& self) -> & OnemcuTpiuCidr0 { & self . onemcu_tpiu_cidr0 } # [doc = "0x2ff4 - Component ID1"]
# [inline (always)]
pub const fn onemcu_tpiu_cidr1 (& self) -> & OnemcuTpiuCidr1 { & self . onemcu_tpiu_cidr1 } # [doc = "0x2ff8 - Component ID2"]
# [inline (always)]
pub const fn onemcu_tpiu_cidr2 (& self) -> & OnemcuTpiuCidr2 { & self . onemcu_tpiu_cidr2 } # [doc = "0x2ffc - Component ID3"]
# [inline (always)]
pub const fn onemcu_tpiu_cidr3 (& self) -> & OnemcuTpiuCidr3 { & self . onemcu_tpiu_cidr3 } # [doc = "0x10000 - http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html"]
# [inline (always)]
pub const fn app_cm4_cti_control (& self) -> & AppCm4CtiControl { & self . app_cm4_cti_control } # [doc = "0x10010 - APP_CM4_CTI_INTACK"]
# [inline (always)]
pub const fn app_cm4_cti_intack (& self) -> & AppCm4CtiIntack { & self . app_cm4_cti_intack } # [doc = "0x10014 - APP_CM4_CTI_APPSET"]
# [inline (always)]
pub const fn app_cm4_cti_appset (& self) -> & AppCm4CtiAppset { & self . app_cm4_cti_appset } # [doc = "0x10018 - APP_CM4_CTI_APPCLEAR"]
# [inline (always)]
pub const fn app_cm4_cti_appclear (& self) -> & AppCm4CtiAppclear { & self . app_cm4_cti_appclear } # [doc = "0x1001c - APP_CM4_CTI_APPPULSE"]
# [inline (always)]
pub const fn app_cm4_cti_apppulse (& self) -> & AppCm4CtiApppulse { & self . app_cm4_cti_apppulse } # [doc = "0x10020 - APP_CM4_CTI_INEN0"]
# [inline (always)]
pub const fn app_cm4_cti_inen0 (& self) -> & AppCm4CtiInen0 { & self . app_cm4_cti_inen0 } # [doc = "0x10024 - APP_CM4_CTI_INEN1"]
# [inline (always)]
pub const fn app_cm4_cti_inen1 (& self) -> & AppCm4CtiInen1 { & self . app_cm4_cti_inen1 } # [doc = "0x10028 - APP_CM4_CTI_INEN2"]
# [inline (always)]
pub const fn app_cm4_cti_inen2 (& self) -> & AppCm4CtiInen2 { & self . app_cm4_cti_inen2 } # [doc = "0x1002c - APP_CM4_CTI_INEN3"]
# [inline (always)]
pub const fn app_cm4_cti_inen3 (& self) -> & AppCm4CtiInen3 { & self . app_cm4_cti_inen3 } # [doc = "0x10030 - APP_CM4_CTI_INEN4"]
# [inline (always)]
pub const fn app_cm4_cti_inen4 (& self) -> & AppCm4CtiInen4 { & self . app_cm4_cti_inen4 } # [doc = "0x10034 - APP_CM4_CTI_INEN5"]
# [inline (always)]
pub const fn app_cm4_cti_inen5 (& self) -> & AppCm4CtiInen5 { & self . app_cm4_cti_inen5 } # [doc = "0x10038 - APP_CM4_CTI_INEN6"]
# [inline (always)]
pub const fn app_cm4_cti_inen6 (& self) -> & AppCm4CtiInen6 { & self . app_cm4_cti_inen6 } # [doc = "0x1003c - APP_CM4_CTI_INEN7"]
# [inline (always)]
pub const fn app_cm4_cti_inen7 (& self) -> & AppCm4CtiInen7 { & self . app_cm4_cti_inen7 } # [doc = "0x100a0 - APP_CM4_CTI_OUTEN0"]
# [inline (always)]
pub const fn app_cm4_cti_outen0 (& self) -> & AppCm4CtiOuten0 { & self . app_cm4_cti_outen0 } # [doc = "0x100a4 - APP_CM4_CTI_OUTEN1"]
# [inline (always)]
pub const fn app_cm4_cti_outen1 (& self) -> & AppCm4CtiOuten1 { & self . app_cm4_cti_outen1 } # [doc = "0x100a8 - APP_CM4_CTI_OUTEN2"]
# [inline (always)]
pub const fn app_cm4_cti_outen2 (& self) -> & AppCm4CtiOuten2 { & self . app_cm4_cti_outen2 } # [doc = "0x100ac - APP_CM4_CTI_OUTEN3"]
# [inline (always)]
pub const fn app_cm4_cti_outen3 (& self) -> & AppCm4CtiOuten3 { & self . app_cm4_cti_outen3 } # [doc = "0x100b0 - APP_CM4_CTI_OUTEN4"]
# [inline (always)]
pub const fn app_cm4_cti_outen4 (& self) -> & AppCm4CtiOuten4 { & self . app_cm4_cti_outen4 } # [doc = "0x100b4 - APP_CM4_CTI_OUTEN5"]
# [inline (always)]
pub const fn app_cm4_cti_outen5 (& self) -> & AppCm4CtiOuten5 { & self . app_cm4_cti_outen5 } # [doc = "0x100b8 - APP_CM4_CTI_OUTEN6"]
# [inline (always)]
pub const fn app_cm4_cti_outen6 (& self) -> & AppCm4CtiOuten6 { & self . app_cm4_cti_outen6 } # [doc = "0x100bc - APP_CM4_CTI_OUTEN7"]
# [inline (always)]
pub const fn app_cm4_cti_outen7 (& self) -> & AppCm4CtiOuten7 { & self . app_cm4_cti_outen7 } # [doc = "0x10130 - APP_CM4_CTI_TRIGINSTATUS"]
# [inline (always)]
pub const fn app_cm4_cti_triginstatus (& self) -> & AppCm4CtiTriginstatus { & self . app_cm4_cti_triginstatus } # [doc = "0x10134 - APP_CM4_CTI_TRIGOUTSTATUS"]
# [inline (always)]
pub const fn app_cm4_cti_trigoutstatus (& self) -> & AppCm4CtiTrigoutstatus { & self . app_cm4_cti_trigoutstatus } # [doc = "0x10138 - APP_CM4_CTI_CHINSTATUS"]
# [inline (always)]
pub const fn app_cm4_cti_chinstatus (& self) -> & AppCm4CtiChinstatus { & self . app_cm4_cti_chinstatus } # [doc = "0x1013c - APP_CM4_CTI_CHOUTSTATUS"]
# [inline (always)]
pub const fn app_cm4_cti_choutstatus (& self) -> & AppCm4CtiChoutstatus { & self . app_cm4_cti_choutstatus } # [doc = "0x10140 - APP_CM4_CTI_GATE"]
# [inline (always)]
pub const fn app_cm4_cti_gate (& self) -> & AppCm4CtiGate { & self . app_cm4_cti_gate } # [doc = "0x10144 - APP_CM4_CTI_ASICCTL"]
# [inline (always)]
pub const fn app_cm4_cti_asicctl (& self) -> & AppCm4CtiAsicctl { & self . app_cm4_cti_asicctl } # [doc = "0x10edc - APP_CM4_CTI_ITCHINACK"]
# [inline (always)]
pub const fn app_cm4_cti_itchinack (& self) -> & AppCm4CtiItchinack { & self . app_cm4_cti_itchinack } # [doc = "0x10ee0 - APP_CM4_CTI_ITTRIGINACK"]
# [inline (always)]
pub const fn app_cm4_cti_ittriginack (& self) -> & AppCm4CtiIttriginack { & self . app_cm4_cti_ittriginack } # [doc = "0x10ee4 - APP_CM4_CTI_ITCHOUT"]
# [inline (always)]
pub const fn app_cm4_cti_itchout (& self) -> & AppCm4CtiItchout { & self . app_cm4_cti_itchout } # [doc = "0x10ee8 - APP_CM4_CTI_ITTRIGOUT"]
# [inline (always)]
pub const fn app_cm4_cti_ittrigout (& self) -> & AppCm4CtiIttrigout { & self . app_cm4_cti_ittrigout } # [doc = "0x10eec - APP_CM4_CTI_ITCHOUTACK"]
# [inline (always)]
pub const fn app_cm4_cti_itchoutack (& self) -> & AppCm4CtiItchoutack { & self . app_cm4_cti_itchoutack } # [doc = "0x10ef0 - APP_CM4_CTI_ITTRIGOUTACK"]
# [inline (always)]
pub const fn app_cm4_cti_ittrigoutack (& self) -> & AppCm4CtiIttrigoutack { & self . app_cm4_cti_ittrigoutack } # [doc = "0x10ef4 - APP_CM4_CTI_ITCHIN"]
# [inline (always)]
pub const fn app_cm4_cti_itchin (& self) -> & AppCm4CtiItchin { & self . app_cm4_cti_itchin } # [doc = "0x10ef8 - APP_CM4_CTI_ITTRIGIN"]
# [inline (always)]
pub const fn app_cm4_cti_ittrigin (& self) -> & AppCm4CtiIttrigin { & self . app_cm4_cti_ittrigin } # [doc = "0x10f00 - APP_CM4_CTI_ITCTRL"]
# [inline (always)]
pub const fn app_cm4_cti_itctrl (& self) -> & AppCm4CtiItctrl { & self . app_cm4_cti_itctrl } # [doc = "0x10fa0 - APP_CM4_CTI_Claim_Tag_Set"]
# [inline (always)]
pub const fn app_cm4_cti_claim_tag_set (& self) -> & AppCm4CtiClaimTagSet { & self . app_cm4_cti_claim_tag_set } # [doc = "0x10fa4 - APP_CM4_CTI_Claim_Tag_Clear"]
# [inline (always)]
pub const fn app_cm4_cti_claim_tag_clear (& self) -> & AppCm4CtiClaimTagClear { & self . app_cm4_cti_claim_tag_clear } # [doc = "0x10fb0 - APP_CM4_CTI_Lock_Access_Register"]
# [inline (always)]
pub const fn app_cm4_cti_lock_access_register (& self) -> & AppCm4CtiLockAccessRegister { & self . app_cm4_cti_lock_access_register } # [doc = "0x10fb4 - APP_CM4_CTI_Lock_Status_Register"]
# [inline (always)]
pub const fn app_cm4_cti_lock_status_register (& self) -> & AppCm4CtiLockStatusRegister { & self . app_cm4_cti_lock_status_register } # [doc = "0x10fb8 - APP_CM4_CTI_Authentication_Status"]
# [inline (always)]
pub const fn app_cm4_cti_authentication_status (& self) -> & AppCm4CtiAuthenticationStatus { & self . app_cm4_cti_authentication_status } # [doc = "0x10fc8 - APP_CM4_CTI_Device_ID"]
# [inline (always)]
pub const fn app_cm4_cti_device_id (& self) -> & AppCm4CtiDeviceId { & self . app_cm4_cti_device_id } # [doc = "0x10fcc - APP_CM4_CTI_Device_Type_Identifier"]
# [inline (always)]
pub const fn app_cm4_cti_device_type_identifier (& self) -> & AppCm4CtiDeviceTypeIdentifier { & self . app_cm4_cti_device_type_identifier } # [doc = "0x10fd0 - APP_CM4_CTI_PeripheralID4"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id4 (& self) -> & AppCm4CtiPeripheralId4 { & self . app_cm4_cti_peripheral_id4 } # [doc = "0x10fd4 - APP_CM4_CTI_PeripheralID5"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id5 (& self) -> & AppCm4CtiPeripheralId5 { & self . app_cm4_cti_peripheral_id5 } # [doc = "0x10fd8 - APP_CM4_CTI_PeripheralID6"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id6 (& self) -> & AppCm4CtiPeripheralId6 { & self . app_cm4_cti_peripheral_id6 } # [doc = "0x10fdc - APP_CM4_CTI_PeripheralID7"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id7 (& self) -> & AppCm4CtiPeripheralId7 { & self . app_cm4_cti_peripheral_id7 } # [doc = "0x10fe0 - APP_CM4_CTI_PeripheralID0"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id0 (& self) -> & AppCm4CtiPeripheralId0 { & self . app_cm4_cti_peripheral_id0 } # [doc = "0x10fe4 - APP_CM4_CTI_PeripheralID1"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id1 (& self) -> & AppCm4CtiPeripheralId1 { & self . app_cm4_cti_peripheral_id1 } # [doc = "0x10fe8 - APP_CM4_CTI_PeripheralID2"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id2 (& self) -> & AppCm4CtiPeripheralId2 { & self . app_cm4_cti_peripheral_id2 } # [doc = "0x10fec - APP_CM4_CTI_PeripheralID3"]
# [inline (always)]
pub const fn app_cm4_cti_peripheral_id3 (& self) -> & AppCm4CtiPeripheralId3 { & self . app_cm4_cti_peripheral_id3 } # [doc = "0x10ff0 - APP_CM4_CTI_Component_ID0"]
# [inline (always)]
pub const fn app_cm4_cti_component_id0 (& self) -> & AppCm4CtiComponentId0 { & self . app_cm4_cti_component_id0 } # [doc = "0x10ff4 - APP_CM4_CTI_Component_ID1"]
# [inline (always)]
pub const fn app_cm4_cti_component_id1 (& self) -> & AppCm4CtiComponentId1 { & self . app_cm4_cti_component_id1 } # [doc = "0x10ff8 - APP_CM4_CTI_Component_ID2"]
# [inline (always)]
pub const fn app_cm4_cti_component_id2 (& self) -> & AppCm4CtiComponentId2 { & self . app_cm4_cti_component_id2 } # [doc = "0x10ffc - APP_CM4_CTI_Component_ID3"]
# [inline (always)]
pub const fn app_cm4_cti_component_id3 (& self) -> & AppCm4CtiComponentId3 { & self . app_cm4_cti_component_id3 } # [doc = "0x11000 - http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html"]
# [inline (always)]
pub const fn fec_cm3_cti_control (& self) -> & FecCm3CtiControl { & self . fec_cm3_cti_control } # [doc = "0x11010 - FEC_CM3_CTI_INTACK"]
# [inline (always)]
pub const fn fec_cm3_cti_intack (& self) -> & FecCm3CtiIntack { & self . fec_cm3_cti_intack } # [doc = "0x11014 - FEC_CM3_CTI_APPSET"]
# [inline (always)]
pub const fn fec_cm3_cti_appset (& self) -> & FecCm3CtiAppset { & self . fec_cm3_cti_appset } # [doc = "0x11018 - FEC_CM3_CTI_APPCLEAR"]
# [inline (always)]
pub const fn fec_cm3_cti_appclear (& self) -> & FecCm3CtiAppclear { & self . fec_cm3_cti_appclear } # [doc = "0x1101c - FEC_CM3_CTI_APPPULSE"]
# [inline (always)]
pub const fn fec_cm3_cti_apppulse (& self) -> & FecCm3CtiApppulse { & self . fec_cm3_cti_apppulse } # [doc = "0x11020 - FEC_CM3_CTI_INEN0"]
# [inline (always)]
pub const fn fec_cm3_cti_inen0 (& self) -> & FecCm3CtiInen0 { & self . fec_cm3_cti_inen0 } # [doc = "0x11024 - FEC_CM3_CTI_INEN1"]
# [inline (always)]
pub const fn fec_cm3_cti_inen1 (& self) -> & FecCm3CtiInen1 { & self . fec_cm3_cti_inen1 } # [doc = "0x11028 - FEC_CM3_CTI_INEN2"]
# [inline (always)]
pub const fn fec_cm3_cti_inen2 (& self) -> & FecCm3CtiInen2 { & self . fec_cm3_cti_inen2 } # [doc = "0x1102c - FEC_CM3_CTI_INEN3"]
# [inline (always)]
pub const fn fec_cm3_cti_inen3 (& self) -> & FecCm3CtiInen3 { & self . fec_cm3_cti_inen3 } # [doc = "0x11030 - FEC_CM3_CTI_INEN4"]
# [inline (always)]
pub const fn fec_cm3_cti_inen4 (& self) -> & FecCm3CtiInen4 { & self . fec_cm3_cti_inen4 } # [doc = "0x11034 - FEC_CM3_CTI_INEN5"]
# [inline (always)]
pub const fn fec_cm3_cti_inen5 (& self) -> & FecCm3CtiInen5 { & self . fec_cm3_cti_inen5 } # [doc = "0x11038 - FEC_CM3_CTI_INEN6"]
# [inline (always)]
pub const fn fec_cm3_cti_inen6 (& self) -> & FecCm3CtiInen6 { & self . fec_cm3_cti_inen6 } # [doc = "0x1103c - FEC_CM3_CTI_INEN7"]
# [inline (always)]
pub const fn fec_cm3_cti_inen7 (& self) -> & FecCm3CtiInen7 { & self . fec_cm3_cti_inen7 } # [doc = "0x110a0 - FEC_CM3_CTI_OUTEN0"]
# [inline (always)]
pub const fn fec_cm3_cti_outen0 (& self) -> & FecCm3CtiOuten0 { & self . fec_cm3_cti_outen0 } # [doc = "0x110a4 - FEC_CM3_CTI_OUTEN1"]
# [inline (always)]
pub const fn fec_cm3_cti_outen1 (& self) -> & FecCm3CtiOuten1 { & self . fec_cm3_cti_outen1 } # [doc = "0x110a8 - FEC_CM3_CTI_OUTEN2"]
# [inline (always)]
pub const fn fec_cm3_cti_outen2 (& self) -> & FecCm3CtiOuten2 { & self . fec_cm3_cti_outen2 } # [doc = "0x110ac - FEC_CM3_CTI_OUTEN3"]
# [inline (always)]
pub const fn fec_cm3_cti_outen3 (& self) -> & FecCm3CtiOuten3 { & self . fec_cm3_cti_outen3 } # [doc = "0x110b0 - FEC_CM3_CTI_OUTEN4"]
# [inline (always)]
pub const fn fec_cm3_cti_outen4 (& self) -> & FecCm3CtiOuten4 { & self . fec_cm3_cti_outen4 } # [doc = "0x110b4 - FEC_CM3_CTI_OUTEN5"]
# [inline (always)]
pub const fn fec_cm3_cti_outen5 (& self) -> & FecCm3CtiOuten5 { & self . fec_cm3_cti_outen5 } # [doc = "0x110b8 - FEC_CM3_CTI_OUTEN6"]
# [inline (always)]
pub const fn fec_cm3_cti_outen6 (& self) -> & FecCm3CtiOuten6 { & self . fec_cm3_cti_outen6 } # [doc = "0x110bc - FEC_CM3_CTI_OUTEN7"]
# [inline (always)]
pub const fn fec_cm3_cti_outen7 (& self) -> & FecCm3CtiOuten7 { & self . fec_cm3_cti_outen7 } # [doc = "0x11130 - FEC_CM3_CTI_TRIGINSTATUS"]
# [inline (always)]
pub const fn fec_cm3_cti_triginstatus (& self) -> & FecCm3CtiTriginstatus { & self . fec_cm3_cti_triginstatus } # [doc = "0x11134 - FEC_CM3_CTI_TRIGOUTSTATUS"]
# [inline (always)]
pub const fn fec_cm3_cti_trigoutstatus (& self) -> & FecCm3CtiTrigoutstatus { & self . fec_cm3_cti_trigoutstatus } # [doc = "0x11138 - FEC_CM3_CTI_CHINSTATUS"]
# [inline (always)]
pub const fn fec_cm3_cti_chinstatus (& self) -> & FecCm3CtiChinstatus { & self . fec_cm3_cti_chinstatus } # [doc = "0x1113c - FEC_CM3_CTI_CHOUTSTATUS"]
# [inline (always)]
pub const fn fec_cm3_cti_choutstatus (& self) -> & FecCm3CtiChoutstatus { & self . fec_cm3_cti_choutstatus } # [doc = "0x11140 - FEC_CM3_CTI_GATE"]
# [inline (always)]
pub const fn fec_cm3_cti_gate (& self) -> & FecCm3CtiGate { & self . fec_cm3_cti_gate } # [doc = "0x11144 - FEC_CM3_CTI_ASICCTL"]
# [inline (always)]
pub const fn fec_cm3_cti_asicctl (& self) -> & FecCm3CtiAsicctl { & self . fec_cm3_cti_asicctl } # [doc = "0x11edc - FEC_CM3_CTI_ITCHINACK"]
# [inline (always)]
pub const fn fec_cm3_cti_itchinack (& self) -> & FecCm3CtiItchinack { & self . fec_cm3_cti_itchinack } # [doc = "0x11ee0 - FEC_CM3_CTI_ITTRIGINACK"]
# [inline (always)]
pub const fn fec_cm3_cti_ittriginack (& self) -> & FecCm3CtiIttriginack { & self . fec_cm3_cti_ittriginack } # [doc = "0x11ee4 - FEC_CM3_CTI_ITCHOUT"]
# [inline (always)]
pub const fn fec_cm3_cti_itchout (& self) -> & FecCm3CtiItchout { & self . fec_cm3_cti_itchout } # [doc = "0x11ee8 - FEC_CM3_CTI_ITTRIGOUT"]
# [inline (always)]
pub const fn fec_cm3_cti_ittrigout (& self) -> & FecCm3CtiIttrigout { & self . fec_cm3_cti_ittrigout } # [doc = "0x11eec - FEC_CM3_CTI_ITCHOUTACK"]
# [inline (always)]
pub const fn fec_cm3_cti_itchoutack (& self) -> & FecCm3CtiItchoutack { & self . fec_cm3_cti_itchoutack } # [doc = "0x11ef0 - FEC_CM3_CTI_ITTRIGOUTACK"]
# [inline (always)]
pub const fn fec_cm3_cti_ittrigoutack (& self) -> & FecCm3CtiIttrigoutack { & self . fec_cm3_cti_ittrigoutack } # [doc = "0x11ef4 - FEC_CM3_CTI_ITCHIN"]
# [inline (always)]
pub const fn fec_cm3_cti_itchin (& self) -> & FecCm3CtiItchin { & self . fec_cm3_cti_itchin } # [doc = "0x11ef8 - FEC_CM3_CTI_ITTRIGIN"]
# [inline (always)]
pub const fn fec_cm3_cti_ittrigin (& self) -> & FecCm3CtiIttrigin { & self . fec_cm3_cti_ittrigin } # [doc = "0x11f00 - FEC_CM3_CTI_ITCTRL"]
# [inline (always)]
pub const fn fec_cm3_cti_itctrl (& self) -> & FecCm3CtiItctrl { & self . fec_cm3_cti_itctrl } # [doc = "0x11fa0 - FEC_CM3_CTI_Claim_Tag_Set"]
# [inline (always)]
pub const fn fec_cm3_cti_claim_tag_set (& self) -> & FecCm3CtiClaimTagSet { & self . fec_cm3_cti_claim_tag_set } # [doc = "0x11fa4 - FEC_CM3_CTI_Claim_Tag_Clear"]
# [inline (always)]
pub const fn fec_cm3_cti_claim_tag_clear (& self) -> & FecCm3CtiClaimTagClear { & self . fec_cm3_cti_claim_tag_clear } # [doc = "0x11fb0 - FEC_CM3_CTI_Lock_Access_Register"]
# [inline (always)]
pub const fn fec_cm3_cti_lock_access_register (& self) -> & FecCm3CtiLockAccessRegister { & self . fec_cm3_cti_lock_access_register } # [doc = "0x11fb4 - FEC_CM3_CTI_Lock_Status_Register"]
# [inline (always)]
pub const fn fec_cm3_cti_lock_status_register (& self) -> & FecCm3CtiLockStatusRegister { & self . fec_cm3_cti_lock_status_register } # [doc = "0x11fb8 - FEC_CM3_CTI_Authentication_Status"]
# [inline (always)]
pub const fn fec_cm3_cti_authentication_status (& self) -> & FecCm3CtiAuthenticationStatus { & self . fec_cm3_cti_authentication_status } # [doc = "0x11fc8 - FEC_CM3_CTI_Device_ID"]
# [inline (always)]
pub const fn fec_cm3_cti_device_id (& self) -> & FecCm3CtiDeviceId { & self . fec_cm3_cti_device_id } # [doc = "0x11fcc - FEC_CM3_CTI_Device_Type_Identifier"]
# [inline (always)]
pub const fn fec_cm3_cti_device_type_identifier (& self) -> & FecCm3CtiDeviceTypeIdentifier { & self . fec_cm3_cti_device_type_identifier } # [doc = "0x11fd0 - FEC_CM3_CTI_PeripheralID4"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id4 (& self) -> & FecCm3CtiPeripheralId4 { & self . fec_cm3_cti_peripheral_id4 } # [doc = "0x11fd4 - FEC_CM3_CTI_PeripheralID5"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id5 (& self) -> & FecCm3CtiPeripheralId5 { & self . fec_cm3_cti_peripheral_id5 } # [doc = "0x11fd8 - FEC_CM3_CTI_PeripheralID6"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id6 (& self) -> & FecCm3CtiPeripheralId6 { & self . fec_cm3_cti_peripheral_id6 } # [doc = "0x11fdc - FEC_CM3_CTI_PeripheralID7"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id7 (& self) -> & FecCm3CtiPeripheralId7 { & self . fec_cm3_cti_peripheral_id7 } # [doc = "0x11fe0 - FEC_CM3_CTI_PeripheralID0"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id0 (& self) -> & FecCm3CtiPeripheralId0 { & self . fec_cm3_cti_peripheral_id0 } # [doc = "0x11fe4 - FEC_CM3_CTI_PeripheralID1"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id1 (& self) -> & FecCm3CtiPeripheralId1 { & self . fec_cm3_cti_peripheral_id1 } # [doc = "0x11fe8 - FEC_CM3_CTI_PeripheralID2"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id2 (& self) -> & FecCm3CtiPeripheralId2 { & self . fec_cm3_cti_peripheral_id2 } # [doc = "0x11fec - FEC_CM3_CTI_PeripheralID3"]
# [inline (always)]
pub const fn fec_cm3_cti_peripheral_id3 (& self) -> & FecCm3CtiPeripheralId3 { & self . fec_cm3_cti_peripheral_id3 } # [doc = "0x11ff0 - FEC_CM3_CTI_Component_ID0"]
# [inline (always)]
pub const fn fec_cm3_cti_component_id0 (& self) -> & FecCm3CtiComponentId0 { & self . fec_cm3_cti_component_id0 } # [doc = "0x11ff4 - FEC_CM3_CTI_Component_ID1"]
# [inline (always)]
pub const fn fec_cm3_cti_component_id1 (& self) -> & FecCm3CtiComponentId1 { & self . fec_cm3_cti_component_id1 } # [doc = "0x11ff8 - FEC_CM3_CTI_Component_ID2"]
# [inline (always)]
pub const fn fec_cm3_cti_component_id2 (& self) -> & FecCm3CtiComponentId2 { & self . fec_cm3_cti_component_id2 } # [doc = "0x11ffc - FEC_CM3_CTI_Component_ID3"]
# [inline (always)]
pub const fn fec_cm3_cti_component_id3 (& self) -> & FecCm3CtiComponentId3 { & self . fec_cm3_cti_component_id3 } } # [doc = "ONEMCU_APB_BASE (rw) register accessor: Start Address of ROM Table\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_apb_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_apb_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_apb_base`]
module"]
# [doc (alias = "ONEMCU_APB_BASE")]
pub type OnemcuApbBase = crate :: Reg < onemcu_apb_base :: OnemcuApbBaseSpec > ; # [doc = "Start Address of ROM Table"]
pub mod onemcu_apb_base { # [doc = "Register `ONEMCU_APB_BASE` reader"]
pub type R = crate :: R < OnemcuApbBaseSpec > ; # [doc = "Register `ONEMCU_APB_BASE` writer"]
pub type W = crate :: W < OnemcuApbBaseSpec > ; # [doc = "Field `ONEMCU_APB_BASE` reader - 31:0\\]
OneMCU APB Space : Start Address of ROM Table"]
pub type OnemcuApbBaseR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_APB_BASE` writer - 31:0\\]
OneMCU APB Space : Start Address of ROM Table"]
pub type OnemcuApbBaseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
OneMCU APB Space : Start Address of ROM Table"]
# [inline (always)]
pub fn onemcu_apb_base (& self) -> OnemcuApbBaseR { OnemcuApbBaseR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
OneMCU APB Space : Start Address of ROM Table"]
# [inline (always)]
# [must_use]
pub fn onemcu_apb_base (& mut self) -> OnemcuApbBaseW < OnemcuApbBaseSpec > { OnemcuApbBaseW :: new (self , 0) } } # [doc = "Start Address of ROM Table\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_apb_base::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_apb_base::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuApbBaseSpec ; impl crate :: RegisterSpec for OnemcuApbBaseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_apb_base::R`](R) reader structure"]
impl crate :: Readable for OnemcuApbBaseSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_apb_base::W`](W) writer structure"]
impl crate :: Writable for OnemcuApbBaseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_APB_BASE to value 0"]
impl crate :: Resettable for OnemcuApbBaseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_APB_BASE_END (rw) register accessor: End Address of ROM Table\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_apb_base_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_apb_base_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_apb_base_end`]
module"]
# [doc (alias = "ONEMCU_APB_BASE_END")]
pub type OnemcuApbBaseEnd = crate :: Reg < onemcu_apb_base_end :: OnemcuApbBaseEndSpec > ; # [doc = "End Address of ROM Table"]
pub mod onemcu_apb_base_end { # [doc = "Register `ONEMCU_APB_BASE_END` reader"]
pub type R = crate :: R < OnemcuApbBaseEndSpec > ; # [doc = "Register `ONEMCU_APB_BASE_END` writer"]
pub type W = crate :: W < OnemcuApbBaseEndSpec > ; # [doc = "Field `ONEMCU_APB_BASE_END` reader - 31:0\\]
OneMCU APB Space : Endt Address of ROM Table"]
pub type OnemcuApbBaseEndR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_APB_BASE_END` writer - 31:0\\]
OneMCU APB Space : Endt Address of ROM Table"]
pub type OnemcuApbBaseEndW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
OneMCU APB Space : Endt Address of ROM Table"]
# [inline (always)]
pub fn onemcu_apb_base_end (& self) -> OnemcuApbBaseEndR { OnemcuApbBaseEndR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
OneMCU APB Space : Endt Address of ROM Table"]
# [inline (always)]
# [must_use]
pub fn onemcu_apb_base_end (& mut self) -> OnemcuApbBaseEndW < OnemcuApbBaseEndSpec > { OnemcuApbBaseEndW :: new (self , 0) } } # [doc = "End Address of ROM Table\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_apb_base_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_apb_base_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuApbBaseEndSpec ; impl crate :: RegisterSpec for OnemcuApbBaseEndSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_apb_base_end::R`](R) reader structure"]
impl crate :: Readable for OnemcuApbBaseEndSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_apb_base_end::W`](W) writer structure"]
impl crate :: Writable for OnemcuApbBaseEndSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_APB_BASE_END to value 0"]
impl crate :: Resettable for OnemcuApbBaseEndSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_CONTROL (rw) register accessor: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_control`]
module"]
# [doc (alias = "ONEMCU_CTI_CONTROL")]
pub type OnemcuCtiControl = crate :: Reg < onemcu_cti_control :: OnemcuCtiControlSpec > ; # [doc = "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html"]
pub mod onemcu_cti_control { # [doc = "Register `ONEMCU_CTI_CONTROL` reader"]
pub type R = crate :: R < OnemcuCtiControlSpec > ; # [doc = "Register `ONEMCU_CTI_CONTROL` writer"]
pub type W = crate :: W < OnemcuCtiControlSpec > ; # [doc = "Field `ONEMCU_CTI_CONTROL` reader - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
pub type OnemcuCtiControlR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_CONTROL` writer - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
pub type OnemcuCtiControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
# [inline (always)]
pub fn onemcu_cti_control (& self) -> OnemcuCtiControlR { OnemcuCtiControlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_control (& mut self) -> OnemcuCtiControlW < OnemcuCtiControlSpec > { OnemcuCtiControlW :: new (self , 0) } } # [doc = "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiControlSpec ; impl crate :: RegisterSpec for OnemcuCtiControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_control::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiControlSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_control::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_CONTROL to value 0"]
impl crate :: Resettable for OnemcuCtiControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INTACK (rw) register accessor: ONEMCU_CTI_INTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_intack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_intack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_intack`]
module"]
# [doc (alias = "ONEMCU_CTI_INTACK")]
pub type OnemcuCtiIntack = crate :: Reg < onemcu_cti_intack :: OnemcuCtiIntackSpec > ; # [doc = "ONEMCU_CTI_INTACK"]
pub mod onemcu_cti_intack { # [doc = "Register `ONEMCU_CTI_INTACK` reader"]
pub type R = crate :: R < OnemcuCtiIntackSpec > ; # [doc = "Register `ONEMCU_CTI_INTACK` writer"]
pub type W = crate :: W < OnemcuCtiIntackSpec > ; # [doc = "Field `ONEMCU_CTI_INTACK` reader - "]
pub type OnemcuCtiIntackR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INTACK` writer - "]
pub type OnemcuCtiIntackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_intack (& self) -> OnemcuCtiIntackR { OnemcuCtiIntackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_intack (& mut self) -> OnemcuCtiIntackW < OnemcuCtiIntackSpec > { OnemcuCtiIntackW :: new (self , 0) } } # [doc = "ONEMCU_CTI_INTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_intack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_intack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiIntackSpec ; impl crate :: RegisterSpec for OnemcuCtiIntackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_intack::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiIntackSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_intack::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiIntackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INTACK to value 0"]
impl crate :: Resettable for OnemcuCtiIntackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_APPSET (rw) register accessor: ONEMCU_CTI_APPSET\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_appset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_appset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_appset`]
module"]
# [doc (alias = "ONEMCU_CTI_APPSET")]
pub type OnemcuCtiAppset = crate :: Reg < onemcu_cti_appset :: OnemcuCtiAppsetSpec > ; # [doc = "ONEMCU_CTI_APPSET"]
pub mod onemcu_cti_appset { # [doc = "Register `ONEMCU_CTI_APPSET` reader"]
pub type R = crate :: R < OnemcuCtiAppsetSpec > ; # [doc = "Register `ONEMCU_CTI_APPSET` writer"]
pub type W = crate :: W < OnemcuCtiAppsetSpec > ; # [doc = "Field `ONEMCU_CTI_APPSET` reader - "]
pub type OnemcuCtiAppsetR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_APPSET` writer - "]
pub type OnemcuCtiAppsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_appset (& self) -> OnemcuCtiAppsetR { OnemcuCtiAppsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_appset (& mut self) -> OnemcuCtiAppsetW < OnemcuCtiAppsetSpec > { OnemcuCtiAppsetW :: new (self , 0) } } # [doc = "ONEMCU_CTI_APPSET\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_appset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_appset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiAppsetSpec ; impl crate :: RegisterSpec for OnemcuCtiAppsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_appset::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiAppsetSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_appset::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiAppsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_APPSET to value 0"]
impl crate :: Resettable for OnemcuCtiAppsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_APPCLEAR (rw) register accessor: ONEMCU_CTI_APPCLEAR\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_appclear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_appclear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_appclear`]
module"]
# [doc (alias = "ONEMCU_CTI_APPCLEAR")]
pub type OnemcuCtiAppclear = crate :: Reg < onemcu_cti_appclear :: OnemcuCtiAppclearSpec > ; # [doc = "ONEMCU_CTI_APPCLEAR"]
pub mod onemcu_cti_appclear { # [doc = "Register `ONEMCU_CTI_APPCLEAR` reader"]
pub type R = crate :: R < OnemcuCtiAppclearSpec > ; # [doc = "Register `ONEMCU_CTI_APPCLEAR` writer"]
pub type W = crate :: W < OnemcuCtiAppclearSpec > ; # [doc = "Field `ONEMCU_CTI_APPCLEAR` reader - "]
pub type OnemcuCtiAppclearR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_APPCLEAR` writer - "]
pub type OnemcuCtiAppclearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_appclear (& self) -> OnemcuCtiAppclearR { OnemcuCtiAppclearR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_appclear (& mut self) -> OnemcuCtiAppclearW < OnemcuCtiAppclearSpec > { OnemcuCtiAppclearW :: new (self , 0) } } # [doc = "ONEMCU_CTI_APPCLEAR\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_appclear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_appclear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiAppclearSpec ; impl crate :: RegisterSpec for OnemcuCtiAppclearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_appclear::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiAppclearSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_appclear::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiAppclearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_APPCLEAR to value 0"]
impl crate :: Resettable for OnemcuCtiAppclearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_APPPULSE (rw) register accessor: ONEMCU_CTI_APPPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_apppulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_apppulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_apppulse`]
module"]
# [doc (alias = "ONEMCU_CTI_APPPULSE")]
pub type OnemcuCtiApppulse = crate :: Reg < onemcu_cti_apppulse :: OnemcuCtiApppulseSpec > ; # [doc = "ONEMCU_CTI_APPPULSE"]
pub mod onemcu_cti_apppulse { # [doc = "Register `ONEMCU_CTI_APPPULSE` reader"]
pub type R = crate :: R < OnemcuCtiApppulseSpec > ; # [doc = "Register `ONEMCU_CTI_APPPULSE` writer"]
pub type W = crate :: W < OnemcuCtiApppulseSpec > ; # [doc = "Field `ONEMCU_CTI_APPPULSE` reader - "]
pub type OnemcuCtiApppulseR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_APPPULSE` writer - "]
pub type OnemcuCtiApppulseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_apppulse (& self) -> OnemcuCtiApppulseR { OnemcuCtiApppulseR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_apppulse (& mut self) -> OnemcuCtiApppulseW < OnemcuCtiApppulseSpec > { OnemcuCtiApppulseW :: new (self , 0) } } # [doc = "ONEMCU_CTI_APPPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_apppulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_apppulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiApppulseSpec ; impl crate :: RegisterSpec for OnemcuCtiApppulseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_apppulse::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiApppulseSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_apppulse::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiApppulseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_APPPULSE to value 0"]
impl crate :: Resettable for OnemcuCtiApppulseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN0 (rw) register accessor: ONEMCU_CTI_INEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen0`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN0")]
pub type OnemcuCtiInen0 = crate :: Reg < onemcu_cti_inen0 :: OnemcuCtiInen0Spec > ; # [doc = "ONEMCU_CTI_INEN0"]
pub mod onemcu_cti_inen0 { # [doc = "Register `ONEMCU_CTI_INEN0` reader"]
pub type R = crate :: R < OnemcuCtiInen0Spec > ; # [doc = "Register `ONEMCU_CTI_INEN0` writer"]
pub type W = crate :: W < OnemcuCtiInen0Spec > ; # [doc = "Field `ONEMCU_CTI_INEN0` reader - "]
pub type OnemcuCtiInen0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN0` writer - "]
pub type OnemcuCtiInen0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen0 (& self) -> OnemcuCtiInen0R { OnemcuCtiInen0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen0 (& mut self) -> OnemcuCtiInen0W < OnemcuCtiInen0Spec > { OnemcuCtiInen0W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen0Spec ; impl crate :: RegisterSpec for OnemcuCtiInen0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen0::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen0::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN0 to value 0"]
impl crate :: Resettable for OnemcuCtiInen0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN1 (rw) register accessor: ONEMCU_CTI_INEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen1`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN1")]
pub type OnemcuCtiInen1 = crate :: Reg < onemcu_cti_inen1 :: OnemcuCtiInen1Spec > ; # [doc = "ONEMCU_CTI_INEN1"]
pub mod onemcu_cti_inen1 { # [doc = "Register `ONEMCU_CTI_INEN1` reader"]
pub type R = crate :: R < OnemcuCtiInen1Spec > ; # [doc = "Register `ONEMCU_CTI_INEN1` writer"]
pub type W = crate :: W < OnemcuCtiInen1Spec > ; # [doc = "Field `ONEMCU_CTI_INEN1` reader - "]
pub type OnemcuCtiInen1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN1` writer - "]
pub type OnemcuCtiInen1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen1 (& self) -> OnemcuCtiInen1R { OnemcuCtiInen1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen1 (& mut self) -> OnemcuCtiInen1W < OnemcuCtiInen1Spec > { OnemcuCtiInen1W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen1Spec ; impl crate :: RegisterSpec for OnemcuCtiInen1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen1::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen1::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN1 to value 0"]
impl crate :: Resettable for OnemcuCtiInen1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN2 (rw) register accessor: ONEMCU_CTI_INEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen2`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN2")]
pub type OnemcuCtiInen2 = crate :: Reg < onemcu_cti_inen2 :: OnemcuCtiInen2Spec > ; # [doc = "ONEMCU_CTI_INEN2"]
pub mod onemcu_cti_inen2 { # [doc = "Register `ONEMCU_CTI_INEN2` reader"]
pub type R = crate :: R < OnemcuCtiInen2Spec > ; # [doc = "Register `ONEMCU_CTI_INEN2` writer"]
pub type W = crate :: W < OnemcuCtiInen2Spec > ; # [doc = "Field `ONEMCU_CTI_INEN2` reader - "]
pub type OnemcuCtiInen2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN2` writer - "]
pub type OnemcuCtiInen2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen2 (& self) -> OnemcuCtiInen2R { OnemcuCtiInen2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen2 (& mut self) -> OnemcuCtiInen2W < OnemcuCtiInen2Spec > { OnemcuCtiInen2W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen2Spec ; impl crate :: RegisterSpec for OnemcuCtiInen2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen2::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen2::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN2 to value 0"]
impl crate :: Resettable for OnemcuCtiInen2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN3 (rw) register accessor: ONEMCU_CTI_INEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen3`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN3")]
pub type OnemcuCtiInen3 = crate :: Reg < onemcu_cti_inen3 :: OnemcuCtiInen3Spec > ; # [doc = "ONEMCU_CTI_INEN3"]
pub mod onemcu_cti_inen3 { # [doc = "Register `ONEMCU_CTI_INEN3` reader"]
pub type R = crate :: R < OnemcuCtiInen3Spec > ; # [doc = "Register `ONEMCU_CTI_INEN3` writer"]
pub type W = crate :: W < OnemcuCtiInen3Spec > ; # [doc = "Field `ONEMCU_CTI_INEN3` reader - "]
pub type OnemcuCtiInen3R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN3` writer - "]
pub type OnemcuCtiInen3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen3 (& self) -> OnemcuCtiInen3R { OnemcuCtiInen3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen3 (& mut self) -> OnemcuCtiInen3W < OnemcuCtiInen3Spec > { OnemcuCtiInen3W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen3Spec ; impl crate :: RegisterSpec for OnemcuCtiInen3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen3::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen3Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen3::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN3 to value 0"]
impl crate :: Resettable for OnemcuCtiInen3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN4 (rw) register accessor: ONEMCU_CTI_INEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen4`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN4")]
pub type OnemcuCtiInen4 = crate :: Reg < onemcu_cti_inen4 :: OnemcuCtiInen4Spec > ; # [doc = "ONEMCU_CTI_INEN4"]
pub mod onemcu_cti_inen4 { # [doc = "Register `ONEMCU_CTI_INEN4` reader"]
pub type R = crate :: R < OnemcuCtiInen4Spec > ; # [doc = "Register `ONEMCU_CTI_INEN4` writer"]
pub type W = crate :: W < OnemcuCtiInen4Spec > ; # [doc = "Field `ONEMCU_CTI_INEN4` reader - "]
pub type OnemcuCtiInen4R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN4` writer - "]
pub type OnemcuCtiInen4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen4 (& self) -> OnemcuCtiInen4R { OnemcuCtiInen4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen4 (& mut self) -> OnemcuCtiInen4W < OnemcuCtiInen4Spec > { OnemcuCtiInen4W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen4Spec ; impl crate :: RegisterSpec for OnemcuCtiInen4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen4::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen4Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen4::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN4 to value 0"]
impl crate :: Resettable for OnemcuCtiInen4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN5 (rw) register accessor: ONEMCU_CTI_INEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen5`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN5")]
pub type OnemcuCtiInen5 = crate :: Reg < onemcu_cti_inen5 :: OnemcuCtiInen5Spec > ; # [doc = "ONEMCU_CTI_INEN5"]
pub mod onemcu_cti_inen5 { # [doc = "Register `ONEMCU_CTI_INEN5` reader"]
pub type R = crate :: R < OnemcuCtiInen5Spec > ; # [doc = "Register `ONEMCU_CTI_INEN5` writer"]
pub type W = crate :: W < OnemcuCtiInen5Spec > ; # [doc = "Field `ONEMCU_CTI_INEN5` reader - "]
pub type OnemcuCtiInen5R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN5` writer - "]
pub type OnemcuCtiInen5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen5 (& self) -> OnemcuCtiInen5R { OnemcuCtiInen5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen5 (& mut self) -> OnemcuCtiInen5W < OnemcuCtiInen5Spec > { OnemcuCtiInen5W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen5Spec ; impl crate :: RegisterSpec for OnemcuCtiInen5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen5::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen5Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen5::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN5 to value 0"]
impl crate :: Resettable for OnemcuCtiInen5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN6 (rw) register accessor: ONEMCU_CTI_INEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen6`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN6")]
pub type OnemcuCtiInen6 = crate :: Reg < onemcu_cti_inen6 :: OnemcuCtiInen6Spec > ; # [doc = "ONEMCU_CTI_INEN6"]
pub mod onemcu_cti_inen6 { # [doc = "Register `ONEMCU_CTI_INEN6` reader"]
pub type R = crate :: R < OnemcuCtiInen6Spec > ; # [doc = "Register `ONEMCU_CTI_INEN6` writer"]
pub type W = crate :: W < OnemcuCtiInen6Spec > ; # [doc = "Field `ONEMCU_CTI_INEN6` reader - "]
pub type OnemcuCtiInen6R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN6` writer - "]
pub type OnemcuCtiInen6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen6 (& self) -> OnemcuCtiInen6R { OnemcuCtiInen6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen6 (& mut self) -> OnemcuCtiInen6W < OnemcuCtiInen6Spec > { OnemcuCtiInen6W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen6Spec ; impl crate :: RegisterSpec for OnemcuCtiInen6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen6::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen6Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen6::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN6 to value 0"]
impl crate :: Resettable for OnemcuCtiInen6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_INEN7 (rw) register accessor: ONEMCU_CTI_INEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_inen7`]
module"]
# [doc (alias = "ONEMCU_CTI_INEN7")]
pub type OnemcuCtiInen7 = crate :: Reg < onemcu_cti_inen7 :: OnemcuCtiInen7Spec > ; # [doc = "ONEMCU_CTI_INEN7"]
pub mod onemcu_cti_inen7 { # [doc = "Register `ONEMCU_CTI_INEN7` reader"]
pub type R = crate :: R < OnemcuCtiInen7Spec > ; # [doc = "Register `ONEMCU_CTI_INEN7` writer"]
pub type W = crate :: W < OnemcuCtiInen7Spec > ; # [doc = "Field `ONEMCU_CTI_INEN7` reader - "]
pub type OnemcuCtiInen7R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_INEN7` writer - "]
pub type OnemcuCtiInen7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_inen7 (& self) -> OnemcuCtiInen7R { OnemcuCtiInen7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_inen7 (& mut self) -> OnemcuCtiInen7W < OnemcuCtiInen7Spec > { OnemcuCtiInen7W :: new (self , 0) } } # [doc = "ONEMCU_CTI_INEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_inen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_inen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiInen7Spec ; impl crate :: RegisterSpec for OnemcuCtiInen7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_inen7::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiInen7Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_inen7::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiInen7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_INEN7 to value 0"]
impl crate :: Resettable for OnemcuCtiInen7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN0 (rw) register accessor: ONEMCU_CTI_OUTEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen0`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN0")]
pub type OnemcuCtiOuten0 = crate :: Reg < onemcu_cti_outen0 :: OnemcuCtiOuten0Spec > ; # [doc = "ONEMCU_CTI_OUTEN0"]
pub mod onemcu_cti_outen0 { # [doc = "Register `ONEMCU_CTI_OUTEN0` reader"]
pub type R = crate :: R < OnemcuCtiOuten0Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN0` writer"]
pub type W = crate :: W < OnemcuCtiOuten0Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN0` reader - "]
pub type OnemcuCtiOuten0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN0` writer - "]
pub type OnemcuCtiOuten0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen0 (& self) -> OnemcuCtiOuten0R { OnemcuCtiOuten0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen0 (& mut self) -> OnemcuCtiOuten0W < OnemcuCtiOuten0Spec > { OnemcuCtiOuten0W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten0Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen0::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen0::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN0 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN1 (rw) register accessor: ONEMCU_CTI_OUTEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen1`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN1")]
pub type OnemcuCtiOuten1 = crate :: Reg < onemcu_cti_outen1 :: OnemcuCtiOuten1Spec > ; # [doc = "ONEMCU_CTI_OUTEN1"]
pub mod onemcu_cti_outen1 { # [doc = "Register `ONEMCU_CTI_OUTEN1` reader"]
pub type R = crate :: R < OnemcuCtiOuten1Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN1` writer"]
pub type W = crate :: W < OnemcuCtiOuten1Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN1` reader - "]
pub type OnemcuCtiOuten1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN1` writer - "]
pub type OnemcuCtiOuten1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen1 (& self) -> OnemcuCtiOuten1R { OnemcuCtiOuten1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen1 (& mut self) -> OnemcuCtiOuten1W < OnemcuCtiOuten1Spec > { OnemcuCtiOuten1W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten1Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen1::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen1::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN1 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN2 (rw) register accessor: ONEMCU_CTI_OUTEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen2`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN2")]
pub type OnemcuCtiOuten2 = crate :: Reg < onemcu_cti_outen2 :: OnemcuCtiOuten2Spec > ; # [doc = "ONEMCU_CTI_OUTEN2"]
pub mod onemcu_cti_outen2 { # [doc = "Register `ONEMCU_CTI_OUTEN2` reader"]
pub type R = crate :: R < OnemcuCtiOuten2Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN2` writer"]
pub type W = crate :: W < OnemcuCtiOuten2Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN2` reader - "]
pub type OnemcuCtiOuten2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN2` writer - "]
pub type OnemcuCtiOuten2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen2 (& self) -> OnemcuCtiOuten2R { OnemcuCtiOuten2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen2 (& mut self) -> OnemcuCtiOuten2W < OnemcuCtiOuten2Spec > { OnemcuCtiOuten2W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten2Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen2::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen2::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN2 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN3 (rw) register accessor: ONEMCU_CTI_OUTEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen3`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN3")]
pub type OnemcuCtiOuten3 = crate :: Reg < onemcu_cti_outen3 :: OnemcuCtiOuten3Spec > ; # [doc = "ONEMCU_CTI_OUTEN3"]
pub mod onemcu_cti_outen3 { # [doc = "Register `ONEMCU_CTI_OUTEN3` reader"]
pub type R = crate :: R < OnemcuCtiOuten3Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN3` writer"]
pub type W = crate :: W < OnemcuCtiOuten3Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN3` reader - "]
pub type OnemcuCtiOuten3R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN3` writer - "]
pub type OnemcuCtiOuten3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen3 (& self) -> OnemcuCtiOuten3R { OnemcuCtiOuten3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen3 (& mut self) -> OnemcuCtiOuten3W < OnemcuCtiOuten3Spec > { OnemcuCtiOuten3W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten3Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen3::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten3Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen3::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN3 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN4 (rw) register accessor: ONEMCU_CTI_OUTEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen4`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN4")]
pub type OnemcuCtiOuten4 = crate :: Reg < onemcu_cti_outen4 :: OnemcuCtiOuten4Spec > ; # [doc = "ONEMCU_CTI_OUTEN4"]
pub mod onemcu_cti_outen4 { # [doc = "Register `ONEMCU_CTI_OUTEN4` reader"]
pub type R = crate :: R < OnemcuCtiOuten4Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN4` writer"]
pub type W = crate :: W < OnemcuCtiOuten4Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN4` reader - "]
pub type OnemcuCtiOuten4R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN4` writer - "]
pub type OnemcuCtiOuten4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen4 (& self) -> OnemcuCtiOuten4R { OnemcuCtiOuten4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen4 (& mut self) -> OnemcuCtiOuten4W < OnemcuCtiOuten4Spec > { OnemcuCtiOuten4W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten4Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen4::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten4Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen4::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN4 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN5 (rw) register accessor: ONEMCU_CTI_OUTEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen5`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN5")]
pub type OnemcuCtiOuten5 = crate :: Reg < onemcu_cti_outen5 :: OnemcuCtiOuten5Spec > ; # [doc = "ONEMCU_CTI_OUTEN5"]
pub mod onemcu_cti_outen5 { # [doc = "Register `ONEMCU_CTI_OUTEN5` reader"]
pub type R = crate :: R < OnemcuCtiOuten5Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN5` writer"]
pub type W = crate :: W < OnemcuCtiOuten5Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN5` reader - "]
pub type OnemcuCtiOuten5R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN5` writer - "]
pub type OnemcuCtiOuten5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen5 (& self) -> OnemcuCtiOuten5R { OnemcuCtiOuten5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen5 (& mut self) -> OnemcuCtiOuten5W < OnemcuCtiOuten5Spec > { OnemcuCtiOuten5W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten5Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen5::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten5Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen5::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN5 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN6 (rw) register accessor: ONEMCU_CTI_OUTEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen6`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN6")]
pub type OnemcuCtiOuten6 = crate :: Reg < onemcu_cti_outen6 :: OnemcuCtiOuten6Spec > ; # [doc = "ONEMCU_CTI_OUTEN6"]
pub mod onemcu_cti_outen6 { # [doc = "Register `ONEMCU_CTI_OUTEN6` reader"]
pub type R = crate :: R < OnemcuCtiOuten6Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN6` writer"]
pub type W = crate :: W < OnemcuCtiOuten6Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN6` reader - "]
pub type OnemcuCtiOuten6R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN6` writer - "]
pub type OnemcuCtiOuten6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen6 (& self) -> OnemcuCtiOuten6R { OnemcuCtiOuten6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen6 (& mut self) -> OnemcuCtiOuten6W < OnemcuCtiOuten6Spec > { OnemcuCtiOuten6W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten6Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen6::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten6Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen6::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN6 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_OUTEN7 (rw) register accessor: ONEMCU_CTI_OUTEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_outen7`]
module"]
# [doc (alias = "ONEMCU_CTI_OUTEN7")]
pub type OnemcuCtiOuten7 = crate :: Reg < onemcu_cti_outen7 :: OnemcuCtiOuten7Spec > ; # [doc = "ONEMCU_CTI_OUTEN7"]
pub mod onemcu_cti_outen7 { # [doc = "Register `ONEMCU_CTI_OUTEN7` reader"]
pub type R = crate :: R < OnemcuCtiOuten7Spec > ; # [doc = "Register `ONEMCU_CTI_OUTEN7` writer"]
pub type W = crate :: W < OnemcuCtiOuten7Spec > ; # [doc = "Field `ONEMCU_CTI_OUTEN7` reader - "]
pub type OnemcuCtiOuten7R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_OUTEN7` writer - "]
pub type OnemcuCtiOuten7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_outen7 (& self) -> OnemcuCtiOuten7R { OnemcuCtiOuten7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_outen7 (& mut self) -> OnemcuCtiOuten7W < OnemcuCtiOuten7Spec > { OnemcuCtiOuten7W :: new (self , 0) } } # [doc = "ONEMCU_CTI_OUTEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_outen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_outen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiOuten7Spec ; impl crate :: RegisterSpec for OnemcuCtiOuten7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_outen7::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiOuten7Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_outen7::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiOuten7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_OUTEN7 to value 0"]
impl crate :: Resettable for OnemcuCtiOuten7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_TRIGINSTATUS (rw) register accessor: ONEMCU_CTI_TRIGINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_triginstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_triginstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_triginstatus`]
module"]
# [doc (alias = "ONEMCU_CTI_TRIGINSTATUS")]
pub type OnemcuCtiTriginstatus = crate :: Reg < onemcu_cti_triginstatus :: OnemcuCtiTriginstatusSpec > ; # [doc = "ONEMCU_CTI_TRIGINSTATUS"]
pub mod onemcu_cti_triginstatus { # [doc = "Register `ONEMCU_CTI_TRIGINSTATUS` reader"]
pub type R = crate :: R < OnemcuCtiTriginstatusSpec > ; # [doc = "Register `ONEMCU_CTI_TRIGINSTATUS` writer"]
pub type W = crate :: W < OnemcuCtiTriginstatusSpec > ; # [doc = "Field `ONEMCU_CTI_TRIGINSTATUS` reader - "]
pub type OnemcuCtiTriginstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_TRIGINSTATUS` writer - "]
pub type OnemcuCtiTriginstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_triginstatus (& self) -> OnemcuCtiTriginstatusR { OnemcuCtiTriginstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_triginstatus (& mut self) -> OnemcuCtiTriginstatusW < OnemcuCtiTriginstatusSpec > { OnemcuCtiTriginstatusW :: new (self , 0) } } # [doc = "ONEMCU_CTI_TRIGINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_triginstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_triginstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiTriginstatusSpec ; impl crate :: RegisterSpec for OnemcuCtiTriginstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_triginstatus::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiTriginstatusSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_triginstatus::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiTriginstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_TRIGINSTATUS to value 0"]
impl crate :: Resettable for OnemcuCtiTriginstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_TRIGOUTSTATUS (rw) register accessor: ONEMCU_CTI_TRIGOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_trigoutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_trigoutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_trigoutstatus`]
module"]
# [doc (alias = "ONEMCU_CTI_TRIGOUTSTATUS")]
pub type OnemcuCtiTrigoutstatus = crate :: Reg < onemcu_cti_trigoutstatus :: OnemcuCtiTrigoutstatusSpec > ; # [doc = "ONEMCU_CTI_TRIGOUTSTATUS"]
pub mod onemcu_cti_trigoutstatus { # [doc = "Register `ONEMCU_CTI_TRIGOUTSTATUS` reader"]
pub type R = crate :: R < OnemcuCtiTrigoutstatusSpec > ; # [doc = "Register `ONEMCU_CTI_TRIGOUTSTATUS` writer"]
pub type W = crate :: W < OnemcuCtiTrigoutstatusSpec > ; # [doc = "Field `ONEMCU_CTI_TRIGOUTSTATUS` reader - "]
pub type OnemcuCtiTrigoutstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_TRIGOUTSTATUS` writer - "]
pub type OnemcuCtiTrigoutstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_trigoutstatus (& self) -> OnemcuCtiTrigoutstatusR { OnemcuCtiTrigoutstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_trigoutstatus (& mut self) -> OnemcuCtiTrigoutstatusW < OnemcuCtiTrigoutstatusSpec > { OnemcuCtiTrigoutstatusW :: new (self , 0) } } # [doc = "ONEMCU_CTI_TRIGOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_trigoutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_trigoutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiTrigoutstatusSpec ; impl crate :: RegisterSpec for OnemcuCtiTrigoutstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_trigoutstatus::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiTrigoutstatusSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_trigoutstatus::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiTrigoutstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_TRIGOUTSTATUS to value 0"]
impl crate :: Resettable for OnemcuCtiTrigoutstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_CHINSTATUS (rw) register accessor: ONEMCU_CTI_CHINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_chinstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_chinstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_chinstatus`]
module"]
# [doc (alias = "ONEMCU_CTI_CHINSTATUS")]
pub type OnemcuCtiChinstatus = crate :: Reg < onemcu_cti_chinstatus :: OnemcuCtiChinstatusSpec > ; # [doc = "ONEMCU_CTI_CHINSTATUS"]
pub mod onemcu_cti_chinstatus { # [doc = "Register `ONEMCU_CTI_CHINSTATUS` reader"]
pub type R = crate :: R < OnemcuCtiChinstatusSpec > ; # [doc = "Register `ONEMCU_CTI_CHINSTATUS` writer"]
pub type W = crate :: W < OnemcuCtiChinstatusSpec > ; # [doc = "Field `ONEMCU_CTI_CHINSTATUS` reader - "]
pub type OnemcuCtiChinstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_CHINSTATUS` writer - "]
pub type OnemcuCtiChinstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_chinstatus (& self) -> OnemcuCtiChinstatusR { OnemcuCtiChinstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_chinstatus (& mut self) -> OnemcuCtiChinstatusW < OnemcuCtiChinstatusSpec > { OnemcuCtiChinstatusW :: new (self , 0) } } # [doc = "ONEMCU_CTI_CHINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_chinstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_chinstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiChinstatusSpec ; impl crate :: RegisterSpec for OnemcuCtiChinstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_chinstatus::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiChinstatusSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_chinstatus::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiChinstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_CHINSTATUS to value 0"]
impl crate :: Resettable for OnemcuCtiChinstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_CHOUTSTATUS (rw) register accessor: ONEMCU_CTI_CHOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_choutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_choutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_choutstatus`]
module"]
# [doc (alias = "ONEMCU_CTI_CHOUTSTATUS")]
pub type OnemcuCtiChoutstatus = crate :: Reg < onemcu_cti_choutstatus :: OnemcuCtiChoutstatusSpec > ; # [doc = "ONEMCU_CTI_CHOUTSTATUS"]
pub mod onemcu_cti_choutstatus { # [doc = "Register `ONEMCU_CTI_CHOUTSTATUS` reader"]
pub type R = crate :: R < OnemcuCtiChoutstatusSpec > ; # [doc = "Register `ONEMCU_CTI_CHOUTSTATUS` writer"]
pub type W = crate :: W < OnemcuCtiChoutstatusSpec > ; # [doc = "Field `ONEMCU_CTI_CHOUTSTATUS` reader - "]
pub type OnemcuCtiChoutstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_CHOUTSTATUS` writer - "]
pub type OnemcuCtiChoutstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_choutstatus (& self) -> OnemcuCtiChoutstatusR { OnemcuCtiChoutstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_choutstatus (& mut self) -> OnemcuCtiChoutstatusW < OnemcuCtiChoutstatusSpec > { OnemcuCtiChoutstatusW :: new (self , 0) } } # [doc = "ONEMCU_CTI_CHOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_choutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_choutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiChoutstatusSpec ; impl crate :: RegisterSpec for OnemcuCtiChoutstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_choutstatus::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiChoutstatusSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_choutstatus::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiChoutstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_CHOUTSTATUS to value 0"]
impl crate :: Resettable for OnemcuCtiChoutstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_GATE (rw) register accessor: ONEMCU_CTI_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_gate`]
module"]
# [doc (alias = "ONEMCU_CTI_GATE")]
pub type OnemcuCtiGate = crate :: Reg < onemcu_cti_gate :: OnemcuCtiGateSpec > ; # [doc = "ONEMCU_CTI_GATE"]
pub mod onemcu_cti_gate { # [doc = "Register `ONEMCU_CTI_GATE` reader"]
pub type R = crate :: R < OnemcuCtiGateSpec > ; # [doc = "Register `ONEMCU_CTI_GATE` writer"]
pub type W = crate :: W < OnemcuCtiGateSpec > ; # [doc = "Field `ONEMCU_CTI_GATE` reader - "]
pub type OnemcuCtiGateR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_GATE` writer - "]
pub type OnemcuCtiGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_gate (& self) -> OnemcuCtiGateR { OnemcuCtiGateR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_gate (& mut self) -> OnemcuCtiGateW < OnemcuCtiGateSpec > { OnemcuCtiGateW :: new (self , 0) } } # [doc = "ONEMCU_CTI_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiGateSpec ; impl crate :: RegisterSpec for OnemcuCtiGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_gate::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiGateSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_gate::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_GATE to value 0"]
impl crate :: Resettable for OnemcuCtiGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ASICCTL (rw) register accessor: ONEMCU_CTI_ASICCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_asicctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_asicctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_asicctl`]
module"]
# [doc (alias = "ONEMCU_CTI_ASICCTL")]
pub type OnemcuCtiAsicctl = crate :: Reg < onemcu_cti_asicctl :: OnemcuCtiAsicctlSpec > ; # [doc = "ONEMCU_CTI_ASICCTL"]
pub mod onemcu_cti_asicctl { # [doc = "Register `ONEMCU_CTI_ASICCTL` reader"]
pub type R = crate :: R < OnemcuCtiAsicctlSpec > ; # [doc = "Register `ONEMCU_CTI_ASICCTL` writer"]
pub type W = crate :: W < OnemcuCtiAsicctlSpec > ; # [doc = "Field `ONEMCU_CTI_ASICCTL` reader - "]
pub type OnemcuCtiAsicctlR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ASICCTL` writer - "]
pub type OnemcuCtiAsicctlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_asicctl (& self) -> OnemcuCtiAsicctlR { OnemcuCtiAsicctlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_asicctl (& mut self) -> OnemcuCtiAsicctlW < OnemcuCtiAsicctlSpec > { OnemcuCtiAsicctlW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ASICCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_asicctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_asicctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiAsicctlSpec ; impl crate :: RegisterSpec for OnemcuCtiAsicctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_asicctl::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiAsicctlSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_asicctl::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiAsicctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ASICCTL to value 0"]
impl crate :: Resettable for OnemcuCtiAsicctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITCHINACK (rw) register accessor: ONEMCU_CTI_ITCHINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchinack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchinack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_itchinack`]
module"]
# [doc (alias = "ONEMCU_CTI_ITCHINACK")]
pub type OnemcuCtiItchinack = crate :: Reg < onemcu_cti_itchinack :: OnemcuCtiItchinackSpec > ; # [doc = "ONEMCU_CTI_ITCHINACK"]
pub mod onemcu_cti_itchinack { # [doc = "Register `ONEMCU_CTI_ITCHINACK` reader"]
pub type R = crate :: R < OnemcuCtiItchinackSpec > ; # [doc = "Register `ONEMCU_CTI_ITCHINACK` writer"]
pub type W = crate :: W < OnemcuCtiItchinackSpec > ; # [doc = "Field `ONEMCU_CTI_ITCHINACK` reader - "]
pub type OnemcuCtiItchinackR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITCHINACK` writer - "]
pub type OnemcuCtiItchinackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_itchinack (& self) -> OnemcuCtiItchinackR { OnemcuCtiItchinackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_itchinack (& mut self) -> OnemcuCtiItchinackW < OnemcuCtiItchinackSpec > { OnemcuCtiItchinackW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITCHINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchinack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchinack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiItchinackSpec ; impl crate :: RegisterSpec for OnemcuCtiItchinackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_itchinack::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiItchinackSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_itchinack::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiItchinackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITCHINACK to value 0"]
impl crate :: Resettable for OnemcuCtiItchinackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITTRIGINACK (rw) register accessor: ONEMCU_CTI_ITTRIGINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittriginack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittriginack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_ittriginack`]
module"]
# [doc (alias = "ONEMCU_CTI_ITTRIGINACK")]
pub type OnemcuCtiIttriginack = crate :: Reg < onemcu_cti_ittriginack :: OnemcuCtiIttriginackSpec > ; # [doc = "ONEMCU_CTI_ITTRIGINACK"]
pub mod onemcu_cti_ittriginack { # [doc = "Register `ONEMCU_CTI_ITTRIGINACK` reader"]
pub type R = crate :: R < OnemcuCtiIttriginackSpec > ; # [doc = "Register `ONEMCU_CTI_ITTRIGINACK` writer"]
pub type W = crate :: W < OnemcuCtiIttriginackSpec > ; # [doc = "Field `ONEMCU_CTI_ITTRIGINACK` reader - "]
pub type OnemcuCtiIttriginackR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITTRIGINACK` writer - "]
pub type OnemcuCtiIttriginackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_ittriginack (& self) -> OnemcuCtiIttriginackR { OnemcuCtiIttriginackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_ittriginack (& mut self) -> OnemcuCtiIttriginackW < OnemcuCtiIttriginackSpec > { OnemcuCtiIttriginackW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITTRIGINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittriginack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittriginack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiIttriginackSpec ; impl crate :: RegisterSpec for OnemcuCtiIttriginackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_ittriginack::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiIttriginackSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_ittriginack::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiIttriginackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITTRIGINACK to value 0"]
impl crate :: Resettable for OnemcuCtiIttriginackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITCHOUT (rw) register accessor: ONEMCU_CTI_ITCHOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_itchout`]
module"]
# [doc (alias = "ONEMCU_CTI_ITCHOUT")]
pub type OnemcuCtiItchout = crate :: Reg < onemcu_cti_itchout :: OnemcuCtiItchoutSpec > ; # [doc = "ONEMCU_CTI_ITCHOUT"]
pub mod onemcu_cti_itchout { # [doc = "Register `ONEMCU_CTI_ITCHOUT` reader"]
pub type R = crate :: R < OnemcuCtiItchoutSpec > ; # [doc = "Register `ONEMCU_CTI_ITCHOUT` writer"]
pub type W = crate :: W < OnemcuCtiItchoutSpec > ; # [doc = "Field `ONEMCU_CTI_ITCHOUT` reader - "]
pub type OnemcuCtiItchoutR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITCHOUT` writer - "]
pub type OnemcuCtiItchoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_itchout (& self) -> OnemcuCtiItchoutR { OnemcuCtiItchoutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_itchout (& mut self) -> OnemcuCtiItchoutW < OnemcuCtiItchoutSpec > { OnemcuCtiItchoutW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITCHOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiItchoutSpec ; impl crate :: RegisterSpec for OnemcuCtiItchoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_itchout::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiItchoutSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_itchout::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiItchoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITCHOUT to value 0"]
impl crate :: Resettable for OnemcuCtiItchoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITTRIGOUT (rw) register accessor: ONEMCU_CTI_ITTRIGOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittrigout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittrigout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_ittrigout`]
module"]
# [doc (alias = "ONEMCU_CTI_ITTRIGOUT")]
pub type OnemcuCtiIttrigout = crate :: Reg < onemcu_cti_ittrigout :: OnemcuCtiIttrigoutSpec > ; # [doc = "ONEMCU_CTI_ITTRIGOUT"]
pub mod onemcu_cti_ittrigout { # [doc = "Register `ONEMCU_CTI_ITTRIGOUT` reader"]
pub type R = crate :: R < OnemcuCtiIttrigoutSpec > ; # [doc = "Register `ONEMCU_CTI_ITTRIGOUT` writer"]
pub type W = crate :: W < OnemcuCtiIttrigoutSpec > ; # [doc = "Field `ONEMCU_CTI_ITTRIGOUT` reader - "]
pub type OnemcuCtiIttrigoutR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITTRIGOUT` writer - "]
pub type OnemcuCtiIttrigoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_ittrigout (& self) -> OnemcuCtiIttrigoutR { OnemcuCtiIttrigoutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_ittrigout (& mut self) -> OnemcuCtiIttrigoutW < OnemcuCtiIttrigoutSpec > { OnemcuCtiIttrigoutW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITTRIGOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittrigout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittrigout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiIttrigoutSpec ; impl crate :: RegisterSpec for OnemcuCtiIttrigoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_ittrigout::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiIttrigoutSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_ittrigout::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiIttrigoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITTRIGOUT to value 0"]
impl crate :: Resettable for OnemcuCtiIttrigoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITCHOUTACK (rw) register accessor: ONEMCU_CTI_ITCHOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchoutack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchoutack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_itchoutack`]
module"]
# [doc (alias = "ONEMCU_CTI_ITCHOUTACK")]
pub type OnemcuCtiItchoutack = crate :: Reg < onemcu_cti_itchoutack :: OnemcuCtiItchoutackSpec > ; # [doc = "ONEMCU_CTI_ITCHOUTACK"]
pub mod onemcu_cti_itchoutack { # [doc = "Register `ONEMCU_CTI_ITCHOUTACK` reader"]
pub type R = crate :: R < OnemcuCtiItchoutackSpec > ; # [doc = "Register `ONEMCU_CTI_ITCHOUTACK` writer"]
pub type W = crate :: W < OnemcuCtiItchoutackSpec > ; # [doc = "Field `ONEMCU_CTI_ITCHOUTACK` reader - "]
pub type OnemcuCtiItchoutackR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITCHOUTACK` writer - "]
pub type OnemcuCtiItchoutackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_itchoutack (& self) -> OnemcuCtiItchoutackR { OnemcuCtiItchoutackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_itchoutack (& mut self) -> OnemcuCtiItchoutackW < OnemcuCtiItchoutackSpec > { OnemcuCtiItchoutackW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITCHOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchoutack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchoutack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiItchoutackSpec ; impl crate :: RegisterSpec for OnemcuCtiItchoutackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_itchoutack::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiItchoutackSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_itchoutack::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiItchoutackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITCHOUTACK to value 0"]
impl crate :: Resettable for OnemcuCtiItchoutackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITTRIGOUTACK (rw) register accessor: ONEMCU_CTI_ITTRIGOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittrigoutack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittrigoutack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_ittrigoutack`]
module"]
# [doc (alias = "ONEMCU_CTI_ITTRIGOUTACK")]
pub type OnemcuCtiIttrigoutack = crate :: Reg < onemcu_cti_ittrigoutack :: OnemcuCtiIttrigoutackSpec > ; # [doc = "ONEMCU_CTI_ITTRIGOUTACK"]
pub mod onemcu_cti_ittrigoutack { # [doc = "Register `ONEMCU_CTI_ITTRIGOUTACK` reader"]
pub type R = crate :: R < OnemcuCtiIttrigoutackSpec > ; # [doc = "Register `ONEMCU_CTI_ITTRIGOUTACK` writer"]
pub type W = crate :: W < OnemcuCtiIttrigoutackSpec > ; # [doc = "Field `ONEMCU_CTI_ITTRIGOUTACK` reader - "]
pub type OnemcuCtiIttrigoutackR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITTRIGOUTACK` writer - "]
pub type OnemcuCtiIttrigoutackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_ittrigoutack (& self) -> OnemcuCtiIttrigoutackR { OnemcuCtiIttrigoutackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_ittrigoutack (& mut self) -> OnemcuCtiIttrigoutackW < OnemcuCtiIttrigoutackSpec > { OnemcuCtiIttrigoutackW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITTRIGOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittrigoutack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittrigoutack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiIttrigoutackSpec ; impl crate :: RegisterSpec for OnemcuCtiIttrigoutackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_ittrigoutack::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiIttrigoutackSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_ittrigoutack::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiIttrigoutackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITTRIGOUTACK to value 0"]
impl crate :: Resettable for OnemcuCtiIttrigoutackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITCHIN (rw) register accessor: ONEMCU_CTI_ITCHIN\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_itchin`]
module"]
# [doc (alias = "ONEMCU_CTI_ITCHIN")]
pub type OnemcuCtiItchin = crate :: Reg < onemcu_cti_itchin :: OnemcuCtiItchinSpec > ; # [doc = "ONEMCU_CTI_ITCHIN"]
pub mod onemcu_cti_itchin { # [doc = "Register `ONEMCU_CTI_ITCHIN` reader"]
pub type R = crate :: R < OnemcuCtiItchinSpec > ; # [doc = "Register `ONEMCU_CTI_ITCHIN` writer"]
pub type W = crate :: W < OnemcuCtiItchinSpec > ; # [doc = "Field `ONEMCU_CTI_ITCHIN` reader - "]
pub type OnemcuCtiItchinR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITCHIN` writer - "]
pub type OnemcuCtiItchinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_itchin (& self) -> OnemcuCtiItchinR { OnemcuCtiItchinR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_itchin (& mut self) -> OnemcuCtiItchinW < OnemcuCtiItchinSpec > { OnemcuCtiItchinW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITCHIN\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itchin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itchin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiItchinSpec ; impl crate :: RegisterSpec for OnemcuCtiItchinSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_itchin::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiItchinSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_itchin::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiItchinSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITCHIN to value 0"]
impl crate :: Resettable for OnemcuCtiItchinSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITTRIGIN (rw) register accessor: ONEMCU_CTI_ITTRIGIN\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittrigin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittrigin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_ittrigin`]
module"]
# [doc (alias = "ONEMCU_CTI_ITTRIGIN")]
pub type OnemcuCtiIttrigin = crate :: Reg < onemcu_cti_ittrigin :: OnemcuCtiIttriginSpec > ; # [doc = "ONEMCU_CTI_ITTRIGIN"]
pub mod onemcu_cti_ittrigin { # [doc = "Register `ONEMCU_CTI_ITTRIGIN` reader"]
pub type R = crate :: R < OnemcuCtiIttriginSpec > ; # [doc = "Register `ONEMCU_CTI_ITTRIGIN` writer"]
pub type W = crate :: W < OnemcuCtiIttriginSpec > ; # [doc = "Field `ONEMCU_CTI_ITTRIGIN` reader - "]
pub type OnemcuCtiIttriginR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITTRIGIN` writer - "]
pub type OnemcuCtiIttriginW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_ittrigin (& self) -> OnemcuCtiIttriginR { OnemcuCtiIttriginR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_ittrigin (& mut self) -> OnemcuCtiIttriginW < OnemcuCtiIttriginSpec > { OnemcuCtiIttriginW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITTRIGIN\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_ittrigin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_ittrigin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiIttriginSpec ; impl crate :: RegisterSpec for OnemcuCtiIttriginSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_ittrigin::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiIttriginSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_ittrigin::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiIttriginSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITTRIGIN to value 0"]
impl crate :: Resettable for OnemcuCtiIttriginSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_ITCTRL (rw) register accessor: ONEMCU_CTI_ITCTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_itctrl`]
module"]
# [doc (alias = "ONEMCU_CTI_ITCTRL")]
pub type OnemcuCtiItctrl = crate :: Reg < onemcu_cti_itctrl :: OnemcuCtiItctrlSpec > ; # [doc = "ONEMCU_CTI_ITCTRL"]
pub mod onemcu_cti_itctrl { # [doc = "Register `ONEMCU_CTI_ITCTRL` reader"]
pub type R = crate :: R < OnemcuCtiItctrlSpec > ; # [doc = "Register `ONEMCU_CTI_ITCTRL` writer"]
pub type W = crate :: W < OnemcuCtiItctrlSpec > ; # [doc = "Field `ONEMCU_CTI_ITCTRL` reader - "]
pub type OnemcuCtiItctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_ITCTRL` writer - "]
pub type OnemcuCtiItctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_itctrl (& self) -> OnemcuCtiItctrlR { OnemcuCtiItctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_itctrl (& mut self) -> OnemcuCtiItctrlW < OnemcuCtiItctrlSpec > { OnemcuCtiItctrlW :: new (self , 0) } } # [doc = "ONEMCU_CTI_ITCTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_itctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_itctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiItctrlSpec ; impl crate :: RegisterSpec for OnemcuCtiItctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_itctrl::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiItctrlSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_itctrl::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiItctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_ITCTRL to value 0"]
impl crate :: Resettable for OnemcuCtiItctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Claim_Tag_Set (rw) register accessor: ONEMCU_CTI_Claim_Tag_Set\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_claim_tag_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_claim_tag_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_claim_tag_set`]
module"]
# [doc (alias = "ONEMCU_CTI_Claim_Tag_Set")]
pub type OnemcuCtiClaimTagSet = crate :: Reg < onemcu_cti_claim_tag_set :: OnemcuCtiClaimTagSetSpec > ; # [doc = "ONEMCU_CTI_Claim_Tag_Set"]
pub mod onemcu_cti_claim_tag_set { # [doc = "Register `ONEMCU_CTI_Claim_Tag_Set` reader"]
pub type R = crate :: R < OnemcuCtiClaimTagSetSpec > ; # [doc = "Register `ONEMCU_CTI_Claim_Tag_Set` writer"]
pub type W = crate :: W < OnemcuCtiClaimTagSetSpec > ; # [doc = "Field `ONEMCU_CTI_Claim_Tag_Set` reader - "]
pub type OnemcuCtiClaimTagSetR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Claim_Tag_Set` writer - "]
pub type OnemcuCtiClaimTagSetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_claim_tag_set (& self) -> OnemcuCtiClaimTagSetR { OnemcuCtiClaimTagSetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_claim_tag_set (& mut self) -> OnemcuCtiClaimTagSetW < OnemcuCtiClaimTagSetSpec > { OnemcuCtiClaimTagSetW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Claim_Tag_Set\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_claim_tag_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_claim_tag_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiClaimTagSetSpec ; impl crate :: RegisterSpec for OnemcuCtiClaimTagSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_claim_tag_set::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiClaimTagSetSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_claim_tag_set::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiClaimTagSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Claim_Tag_Set to value 0"]
impl crate :: Resettable for OnemcuCtiClaimTagSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Claim_Tag_Clear (rw) register accessor: ONEMCU_CTI_Claim_Tag_Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_claim_tag_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_claim_tag_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_claim_tag_clear`]
module"]
# [doc (alias = "ONEMCU_CTI_Claim_Tag_Clear")]
pub type OnemcuCtiClaimTagClear = crate :: Reg < onemcu_cti_claim_tag_clear :: OnemcuCtiClaimTagClearSpec > ; # [doc = "ONEMCU_CTI_Claim_Tag_Clear"]
pub mod onemcu_cti_claim_tag_clear { # [doc = "Register `ONEMCU_CTI_Claim_Tag_Clear` reader"]
pub type R = crate :: R < OnemcuCtiClaimTagClearSpec > ; # [doc = "Register `ONEMCU_CTI_Claim_Tag_Clear` writer"]
pub type W = crate :: W < OnemcuCtiClaimTagClearSpec > ; # [doc = "Field `ONEMCU_CTI_Claim_Tag_Clear` reader - "]
pub type OnemcuCtiClaimTagClearR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Claim_Tag_Clear` writer - "]
pub type OnemcuCtiClaimTagClearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_claim_tag_clear (& self) -> OnemcuCtiClaimTagClearR { OnemcuCtiClaimTagClearR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_claim_tag_clear (& mut self) -> OnemcuCtiClaimTagClearW < OnemcuCtiClaimTagClearSpec > { OnemcuCtiClaimTagClearW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Claim_Tag_Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_claim_tag_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_claim_tag_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiClaimTagClearSpec ; impl crate :: RegisterSpec for OnemcuCtiClaimTagClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_claim_tag_clear::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiClaimTagClearSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_claim_tag_clear::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiClaimTagClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Claim_Tag_Clear to value 0"]
impl crate :: Resettable for OnemcuCtiClaimTagClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Lock_Access_Register (rw) register accessor: ONEMCU_CTI_Lock_Access_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_lock_access_register::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_lock_access_register::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_lock_access_register`]
module"]
# [doc (alias = "ONEMCU_CTI_Lock_Access_Register")]
pub type OnemcuCtiLockAccessRegister = crate :: Reg < onemcu_cti_lock_access_register :: OnemcuCtiLockAccessRegisterSpec > ; # [doc = "ONEMCU_CTI_Lock_Access_Register"]
pub mod onemcu_cti_lock_access_register { # [doc = "Register `ONEMCU_CTI_Lock_Access_Register` reader"]
pub type R = crate :: R < OnemcuCtiLockAccessRegisterSpec > ; # [doc = "Register `ONEMCU_CTI_Lock_Access_Register` writer"]
pub type W = crate :: W < OnemcuCtiLockAccessRegisterSpec > ; # [doc = "Field `ONEMCU_CTI_Lock_Access_Register` reader - "]
pub type OnemcuCtiLockAccessRegisterR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Lock_Access_Register` writer - "]
pub type OnemcuCtiLockAccessRegisterW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_lock_access_register (& self) -> OnemcuCtiLockAccessRegisterR { OnemcuCtiLockAccessRegisterR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_lock_access_register (& mut self) -> OnemcuCtiLockAccessRegisterW < OnemcuCtiLockAccessRegisterSpec > { OnemcuCtiLockAccessRegisterW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Lock_Access_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_lock_access_register::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_lock_access_register::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiLockAccessRegisterSpec ; impl crate :: RegisterSpec for OnemcuCtiLockAccessRegisterSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_lock_access_register::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiLockAccessRegisterSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_lock_access_register::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiLockAccessRegisterSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Lock_Access_Register to value 0"]
impl crate :: Resettable for OnemcuCtiLockAccessRegisterSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Lock_Status_Register (rw) register accessor: ONEMCU_CTI_Lock_Status_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_lock_status_register::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_lock_status_register::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_lock_status_register`]
module"]
# [doc (alias = "ONEMCU_CTI_Lock_Status_Register")]
pub type OnemcuCtiLockStatusRegister = crate :: Reg < onemcu_cti_lock_status_register :: OnemcuCtiLockStatusRegisterSpec > ; # [doc = "ONEMCU_CTI_Lock_Status_Register"]
pub mod onemcu_cti_lock_status_register { # [doc = "Register `ONEMCU_CTI_Lock_Status_Register` reader"]
pub type R = crate :: R < OnemcuCtiLockStatusRegisterSpec > ; # [doc = "Register `ONEMCU_CTI_Lock_Status_Register` writer"]
pub type W = crate :: W < OnemcuCtiLockStatusRegisterSpec > ; # [doc = "Field `ONEMCU_CTI_Lock_Status_Register` reader - "]
pub type OnemcuCtiLockStatusRegisterR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Lock_Status_Register` writer - "]
pub type OnemcuCtiLockStatusRegisterW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_lock_status_register (& self) -> OnemcuCtiLockStatusRegisterR { OnemcuCtiLockStatusRegisterR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_lock_status_register (& mut self) -> OnemcuCtiLockStatusRegisterW < OnemcuCtiLockStatusRegisterSpec > { OnemcuCtiLockStatusRegisterW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Lock_Status_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_lock_status_register::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_lock_status_register::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiLockStatusRegisterSpec ; impl crate :: RegisterSpec for OnemcuCtiLockStatusRegisterSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_lock_status_register::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiLockStatusRegisterSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_lock_status_register::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiLockStatusRegisterSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Lock_Status_Register to value 0"]
impl crate :: Resettable for OnemcuCtiLockStatusRegisterSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Authentication_Status (rw) register accessor: ONEMCU_CTI_Authentication_Status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_authentication_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_authentication_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_authentication_status`]
module"]
# [doc (alias = "ONEMCU_CTI_Authentication_Status")]
pub type OnemcuCtiAuthenticationStatus = crate :: Reg < onemcu_cti_authentication_status :: OnemcuCtiAuthenticationStatusSpec > ; # [doc = "ONEMCU_CTI_Authentication_Status"]
pub mod onemcu_cti_authentication_status { # [doc = "Register `ONEMCU_CTI_Authentication_Status` reader"]
pub type R = crate :: R < OnemcuCtiAuthenticationStatusSpec > ; # [doc = "Register `ONEMCU_CTI_Authentication_Status` writer"]
pub type W = crate :: W < OnemcuCtiAuthenticationStatusSpec > ; # [doc = "Field `ONEMCU_CTI_Authentication_Status` reader - "]
pub type OnemcuCtiAuthenticationStatusR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Authentication_Status` writer - "]
pub type OnemcuCtiAuthenticationStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_authentication_status (& self) -> OnemcuCtiAuthenticationStatusR { OnemcuCtiAuthenticationStatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_authentication_status (& mut self) -> OnemcuCtiAuthenticationStatusW < OnemcuCtiAuthenticationStatusSpec > { OnemcuCtiAuthenticationStatusW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Authentication_Status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_authentication_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_authentication_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiAuthenticationStatusSpec ; impl crate :: RegisterSpec for OnemcuCtiAuthenticationStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_authentication_status::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiAuthenticationStatusSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_authentication_status::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiAuthenticationStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Authentication_Status to value 0"]
impl crate :: Resettable for OnemcuCtiAuthenticationStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Device_ID (rw) register accessor: ONEMCU_CTI_Device_ID\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_device_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_device_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_device_id`]
module"]
# [doc (alias = "ONEMCU_CTI_Device_ID")]
pub type OnemcuCtiDeviceId = crate :: Reg < onemcu_cti_device_id :: OnemcuCtiDeviceIdSpec > ; # [doc = "ONEMCU_CTI_Device_ID"]
pub mod onemcu_cti_device_id { # [doc = "Register `ONEMCU_CTI_Device_ID` reader"]
pub type R = crate :: R < OnemcuCtiDeviceIdSpec > ; # [doc = "Register `ONEMCU_CTI_Device_ID` writer"]
pub type W = crate :: W < OnemcuCtiDeviceIdSpec > ; # [doc = "Field `ONEMCU_CTI_Device_ID` reader - "]
pub type OnemcuCtiDeviceIdR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Device_ID` writer - "]
pub type OnemcuCtiDeviceIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_device_id (& self) -> OnemcuCtiDeviceIdR { OnemcuCtiDeviceIdR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_device_id (& mut self) -> OnemcuCtiDeviceIdW < OnemcuCtiDeviceIdSpec > { OnemcuCtiDeviceIdW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Device_ID\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_device_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_device_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiDeviceIdSpec ; impl crate :: RegisterSpec for OnemcuCtiDeviceIdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_device_id::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiDeviceIdSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_device_id::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiDeviceIdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Device_ID to value 0"]
impl crate :: Resettable for OnemcuCtiDeviceIdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Device_Type_Identifier (rw) register accessor: ONEMCU_CTI_Device_Type_Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_device_type_identifier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_device_type_identifier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_device_type_identifier`]
module"]
# [doc (alias = "ONEMCU_CTI_Device_Type_Identifier")]
pub type OnemcuCtiDeviceTypeIdentifier = crate :: Reg < onemcu_cti_device_type_identifier :: OnemcuCtiDeviceTypeIdentifierSpec > ; # [doc = "ONEMCU_CTI_Device_Type_Identifier"]
pub mod onemcu_cti_device_type_identifier { # [doc = "Register `ONEMCU_CTI_Device_Type_Identifier` reader"]
pub type R = crate :: R < OnemcuCtiDeviceTypeIdentifierSpec > ; # [doc = "Register `ONEMCU_CTI_Device_Type_Identifier` writer"]
pub type W = crate :: W < OnemcuCtiDeviceTypeIdentifierSpec > ; # [doc = "Field `ONEMCU_CTI_Device_Type_Identifier` reader - "]
pub type OnemcuCtiDeviceTypeIdentifierR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Device_Type_Identifier` writer - "]
pub type OnemcuCtiDeviceTypeIdentifierW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_device_type_identifier (& self) -> OnemcuCtiDeviceTypeIdentifierR { OnemcuCtiDeviceTypeIdentifierR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_device_type_identifier (& mut self) -> OnemcuCtiDeviceTypeIdentifierW < OnemcuCtiDeviceTypeIdentifierSpec > { OnemcuCtiDeviceTypeIdentifierW :: new (self , 0) } } # [doc = "ONEMCU_CTI_Device_Type_Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_device_type_identifier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_device_type_identifier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiDeviceTypeIdentifierSpec ; impl crate :: RegisterSpec for OnemcuCtiDeviceTypeIdentifierSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_device_type_identifier::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiDeviceTypeIdentifierSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_device_type_identifier::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiDeviceTypeIdentifierSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Device_Type_Identifier to value 0"]
impl crate :: Resettable for OnemcuCtiDeviceTypeIdentifierSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID4 (rw) register accessor: ONEMCU_CTI_PeripheralID4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id4`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID4")]
pub type OnemcuCtiPeripheralId4 = crate :: Reg < onemcu_cti_peripheral_id4 :: OnemcuCtiPeripheralId4Spec > ; # [doc = "ONEMCU_CTI_PeripheralID4"]
pub mod onemcu_cti_peripheral_id4 { # [doc = "Register `ONEMCU_CTI_PeripheralID4` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId4Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID4` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId4Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID4` reader - "]
pub type OnemcuCtiPeripheralId4R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID4` writer - "]
pub type OnemcuCtiPeripheralId4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id4 (& self) -> OnemcuCtiPeripheralId4R { OnemcuCtiPeripheralId4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id4 (& mut self) -> OnemcuCtiPeripheralId4W < OnemcuCtiPeripheralId4Spec > { OnemcuCtiPeripheralId4W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId4Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id4::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId4Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id4::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID4 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID5 (rw) register accessor: ONEMCU_CTI_PeripheralID5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id5`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID5")]
pub type OnemcuCtiPeripheralId5 = crate :: Reg < onemcu_cti_peripheral_id5 :: OnemcuCtiPeripheralId5Spec > ; # [doc = "ONEMCU_CTI_PeripheralID5"]
pub mod onemcu_cti_peripheral_id5 { # [doc = "Register `ONEMCU_CTI_PeripheralID5` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId5Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID5` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId5Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID5` reader - "]
pub type OnemcuCtiPeripheralId5R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID5` writer - "]
pub type OnemcuCtiPeripheralId5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id5 (& self) -> OnemcuCtiPeripheralId5R { OnemcuCtiPeripheralId5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id5 (& mut self) -> OnemcuCtiPeripheralId5W < OnemcuCtiPeripheralId5Spec > { OnemcuCtiPeripheralId5W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId5Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id5::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId5Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id5::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID5 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID6 (rw) register accessor: ONEMCU_CTI_PeripheralID6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id6`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID6")]
pub type OnemcuCtiPeripheralId6 = crate :: Reg < onemcu_cti_peripheral_id6 :: OnemcuCtiPeripheralId6Spec > ; # [doc = "ONEMCU_CTI_PeripheralID6"]
pub mod onemcu_cti_peripheral_id6 { # [doc = "Register `ONEMCU_CTI_PeripheralID6` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId6Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID6` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId6Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID6` reader - "]
pub type OnemcuCtiPeripheralId6R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID6` writer - "]
pub type OnemcuCtiPeripheralId6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id6 (& self) -> OnemcuCtiPeripheralId6R { OnemcuCtiPeripheralId6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id6 (& mut self) -> OnemcuCtiPeripheralId6W < OnemcuCtiPeripheralId6Spec > { OnemcuCtiPeripheralId6W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId6Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id6::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId6Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id6::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID6 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID7 (rw) register accessor: ONEMCU_CTI_PeripheralID7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id7`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID7")]
pub type OnemcuCtiPeripheralId7 = crate :: Reg < onemcu_cti_peripheral_id7 :: OnemcuCtiPeripheralId7Spec > ; # [doc = "ONEMCU_CTI_PeripheralID7"]
pub mod onemcu_cti_peripheral_id7 { # [doc = "Register `ONEMCU_CTI_PeripheralID7` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId7Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID7` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId7Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID7` reader - "]
pub type OnemcuCtiPeripheralId7R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID7` writer - "]
pub type OnemcuCtiPeripheralId7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id7 (& self) -> OnemcuCtiPeripheralId7R { OnemcuCtiPeripheralId7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id7 (& mut self) -> OnemcuCtiPeripheralId7W < OnemcuCtiPeripheralId7Spec > { OnemcuCtiPeripheralId7W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId7Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id7::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId7Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id7::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID7 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID0 (rw) register accessor: ONEMCU_CTI_PeripheralID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id0`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID0")]
pub type OnemcuCtiPeripheralId0 = crate :: Reg < onemcu_cti_peripheral_id0 :: OnemcuCtiPeripheralId0Spec > ; # [doc = "ONEMCU_CTI_PeripheralID0"]
pub mod onemcu_cti_peripheral_id0 { # [doc = "Register `ONEMCU_CTI_PeripheralID0` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId0Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID0` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId0Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID0` reader - "]
pub type OnemcuCtiPeripheralId0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID0` writer - "]
pub type OnemcuCtiPeripheralId0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id0 (& self) -> OnemcuCtiPeripheralId0R { OnemcuCtiPeripheralId0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id0 (& mut self) -> OnemcuCtiPeripheralId0W < OnemcuCtiPeripheralId0Spec > { OnemcuCtiPeripheralId0W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId0Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id0::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id0::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID0 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID1 (rw) register accessor: ONEMCU_CTI_PeripheralID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id1`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID1")]
pub type OnemcuCtiPeripheralId1 = crate :: Reg < onemcu_cti_peripheral_id1 :: OnemcuCtiPeripheralId1Spec > ; # [doc = "ONEMCU_CTI_PeripheralID1"]
pub mod onemcu_cti_peripheral_id1 { # [doc = "Register `ONEMCU_CTI_PeripheralID1` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId1Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID1` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId1Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID1` reader - "]
pub type OnemcuCtiPeripheralId1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID1` writer - "]
pub type OnemcuCtiPeripheralId1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id1 (& self) -> OnemcuCtiPeripheralId1R { OnemcuCtiPeripheralId1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id1 (& mut self) -> OnemcuCtiPeripheralId1W < OnemcuCtiPeripheralId1Spec > { OnemcuCtiPeripheralId1W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId1Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id1::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id1::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID1 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID2 (rw) register accessor: ONEMCU_CTI_PeripheralID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id2`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID2")]
pub type OnemcuCtiPeripheralId2 = crate :: Reg < onemcu_cti_peripheral_id2 :: OnemcuCtiPeripheralId2Spec > ; # [doc = "ONEMCU_CTI_PeripheralID2"]
pub mod onemcu_cti_peripheral_id2 { # [doc = "Register `ONEMCU_CTI_PeripheralID2` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId2Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID2` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId2Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID2` reader - "]
pub type OnemcuCtiPeripheralId2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID2` writer - "]
pub type OnemcuCtiPeripheralId2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id2 (& self) -> OnemcuCtiPeripheralId2R { OnemcuCtiPeripheralId2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id2 (& mut self) -> OnemcuCtiPeripheralId2W < OnemcuCtiPeripheralId2Spec > { OnemcuCtiPeripheralId2W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId2Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id2::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id2::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID2 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_PeripheralID3 (rw) register accessor: ONEMCU_CTI_PeripheralID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_peripheral_id3`]
module"]
# [doc (alias = "ONEMCU_CTI_PeripheralID3")]
pub type OnemcuCtiPeripheralId3 = crate :: Reg < onemcu_cti_peripheral_id3 :: OnemcuCtiPeripheralId3Spec > ; # [doc = "ONEMCU_CTI_PeripheralID3"]
pub mod onemcu_cti_peripheral_id3 { # [doc = "Register `ONEMCU_CTI_PeripheralID3` reader"]
pub type R = crate :: R < OnemcuCtiPeripheralId3Spec > ; # [doc = "Register `ONEMCU_CTI_PeripheralID3` writer"]
pub type W = crate :: W < OnemcuCtiPeripheralId3Spec > ; # [doc = "Field `ONEMCU_CTI_PeripheralID3` reader - "]
pub type OnemcuCtiPeripheralId3R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_PeripheralID3` writer - "]
pub type OnemcuCtiPeripheralId3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_peripheral_id3 (& self) -> OnemcuCtiPeripheralId3R { OnemcuCtiPeripheralId3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_peripheral_id3 (& mut self) -> OnemcuCtiPeripheralId3W < OnemcuCtiPeripheralId3Spec > { OnemcuCtiPeripheralId3W :: new (self , 0) } } # [doc = "ONEMCU_CTI_PeripheralID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_peripheral_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_peripheral_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiPeripheralId3Spec ; impl crate :: RegisterSpec for OnemcuCtiPeripheralId3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_peripheral_id3::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiPeripheralId3Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_peripheral_id3::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiPeripheralId3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_PeripheralID3 to value 0"]
impl crate :: Resettable for OnemcuCtiPeripheralId3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Component_ID0 (rw) register accessor: ONEMCU_CTI_Component_ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_component_id0`]
module"]
# [doc (alias = "ONEMCU_CTI_Component_ID0")]
pub type OnemcuCtiComponentId0 = crate :: Reg < onemcu_cti_component_id0 :: OnemcuCtiComponentId0Spec > ; # [doc = "ONEMCU_CTI_Component_ID0"]
pub mod onemcu_cti_component_id0 { # [doc = "Register `ONEMCU_CTI_Component_ID0` reader"]
pub type R = crate :: R < OnemcuCtiComponentId0Spec > ; # [doc = "Register `ONEMCU_CTI_Component_ID0` writer"]
pub type W = crate :: W < OnemcuCtiComponentId0Spec > ; # [doc = "Field `ONEMCU_CTI_Component_ID0` reader - "]
pub type OnemcuCtiComponentId0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Component_ID0` writer - "]
pub type OnemcuCtiComponentId0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_component_id0 (& self) -> OnemcuCtiComponentId0R { OnemcuCtiComponentId0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_component_id0 (& mut self) -> OnemcuCtiComponentId0W < OnemcuCtiComponentId0Spec > { OnemcuCtiComponentId0W :: new (self , 0) } } # [doc = "ONEMCU_CTI_Component_ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiComponentId0Spec ; impl crate :: RegisterSpec for OnemcuCtiComponentId0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_component_id0::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiComponentId0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_component_id0::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiComponentId0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Component_ID0 to value 0"]
impl crate :: Resettable for OnemcuCtiComponentId0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Component_ID1 (rw) register accessor: ONEMCU_CTI_Component_ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_component_id1`]
module"]
# [doc (alias = "ONEMCU_CTI_Component_ID1")]
pub type OnemcuCtiComponentId1 = crate :: Reg < onemcu_cti_component_id1 :: OnemcuCtiComponentId1Spec > ; # [doc = "ONEMCU_CTI_Component_ID1"]
pub mod onemcu_cti_component_id1 { # [doc = "Register `ONEMCU_CTI_Component_ID1` reader"]
pub type R = crate :: R < OnemcuCtiComponentId1Spec > ; # [doc = "Register `ONEMCU_CTI_Component_ID1` writer"]
pub type W = crate :: W < OnemcuCtiComponentId1Spec > ; # [doc = "Field `ONEMCU_CTI_Component_ID1` reader - "]
pub type OnemcuCtiComponentId1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Component_ID1` writer - "]
pub type OnemcuCtiComponentId1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_component_id1 (& self) -> OnemcuCtiComponentId1R { OnemcuCtiComponentId1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_component_id1 (& mut self) -> OnemcuCtiComponentId1W < OnemcuCtiComponentId1Spec > { OnemcuCtiComponentId1W :: new (self , 0) } } # [doc = "ONEMCU_CTI_Component_ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiComponentId1Spec ; impl crate :: RegisterSpec for OnemcuCtiComponentId1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_component_id1::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiComponentId1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_component_id1::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiComponentId1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Component_ID1 to value 0"]
impl crate :: Resettable for OnemcuCtiComponentId1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Component_ID2 (rw) register accessor: ONEMCU_CTI_Component_ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_component_id2`]
module"]
# [doc (alias = "ONEMCU_CTI_Component_ID2")]
pub type OnemcuCtiComponentId2 = crate :: Reg < onemcu_cti_component_id2 :: OnemcuCtiComponentId2Spec > ; # [doc = "ONEMCU_CTI_Component_ID2"]
pub mod onemcu_cti_component_id2 { # [doc = "Register `ONEMCU_CTI_Component_ID2` reader"]
pub type R = crate :: R < OnemcuCtiComponentId2Spec > ; # [doc = "Register `ONEMCU_CTI_Component_ID2` writer"]
pub type W = crate :: W < OnemcuCtiComponentId2Spec > ; # [doc = "Field `ONEMCU_CTI_Component_ID2` reader - "]
pub type OnemcuCtiComponentId2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Component_ID2` writer - "]
pub type OnemcuCtiComponentId2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_component_id2 (& self) -> OnemcuCtiComponentId2R { OnemcuCtiComponentId2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_component_id2 (& mut self) -> OnemcuCtiComponentId2W < OnemcuCtiComponentId2Spec > { OnemcuCtiComponentId2W :: new (self , 0) } } # [doc = "ONEMCU_CTI_Component_ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiComponentId2Spec ; impl crate :: RegisterSpec for OnemcuCtiComponentId2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_component_id2::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiComponentId2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_component_id2::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiComponentId2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Component_ID2 to value 0"]
impl crate :: Resettable for OnemcuCtiComponentId2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_CTI_Component_ID3 (rw) register accessor: ONEMCU_CTI_Component_ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_cti_component_id3`]
module"]
# [doc (alias = "ONEMCU_CTI_Component_ID3")]
pub type OnemcuCtiComponentId3 = crate :: Reg < onemcu_cti_component_id3 :: OnemcuCtiComponentId3Spec > ; # [doc = "ONEMCU_CTI_Component_ID3"]
pub mod onemcu_cti_component_id3 { # [doc = "Register `ONEMCU_CTI_Component_ID3` reader"]
pub type R = crate :: R < OnemcuCtiComponentId3Spec > ; # [doc = "Register `ONEMCU_CTI_Component_ID3` writer"]
pub type W = crate :: W < OnemcuCtiComponentId3Spec > ; # [doc = "Field `ONEMCU_CTI_Component_ID3` reader - "]
pub type OnemcuCtiComponentId3R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_CTI_Component_ID3` writer - "]
pub type OnemcuCtiComponentId3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn onemcu_cti_component_id3 (& self) -> OnemcuCtiComponentId3R { OnemcuCtiComponentId3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn onemcu_cti_component_id3 (& mut self) -> OnemcuCtiComponentId3W < OnemcuCtiComponentId3Spec > { OnemcuCtiComponentId3W :: new (self , 0) } } # [doc = "ONEMCU_CTI_Component_ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_cti_component_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_cti_component_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuCtiComponentId3Spec ; impl crate :: RegisterSpec for OnemcuCtiComponentId3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_cti_component_id3::R`](R) reader structure"]
impl crate :: Readable for OnemcuCtiComponentId3Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_cti_component_id3::W`](W) writer structure"]
impl crate :: Writable for OnemcuCtiComponentId3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_CTI_Component_ID3 to value 0"]
impl crate :: Resettable for OnemcuCtiComponentId3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_SPORTSZ (rw) register accessor: Supported port sizes\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_sportsz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_sportsz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_sportsz`]
module"]
# [doc (alias = "ONEMCU_TPIU_SPORTSZ")]
pub type OnemcuTpiuSportsz = crate :: Reg < onemcu_tpiu_sportsz :: OnemcuTpiuSportszSpec > ; # [doc = "Supported port sizes"]
pub mod onemcu_tpiu_sportsz { # [doc = "Register `ONEMCU_TPIU_SPORTSZ` reader"]
pub type R = crate :: R < OnemcuTpiuSportszSpec > ; # [doc = "Register `ONEMCU_TPIU_SPORTSZ` writer"]
pub type W = crate :: W < OnemcuTpiuSportszSpec > ; # [doc = "Field `ONEMCU_TPIU_SPORTSZ` reader - 31:0\\]
Supported port sizes"]
pub type OnemcuTpiuSportszR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_SPORTSZ` writer - 31:0\\]
Supported port sizes"]
pub type OnemcuTpiuSportszW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Supported port sizes"]
# [inline (always)]
pub fn onemcu_tpiu_sportsz (& self) -> OnemcuTpiuSportszR { OnemcuTpiuSportszR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Supported port sizes"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_sportsz (& mut self) -> OnemcuTpiuSportszW < OnemcuTpiuSportszSpec > { OnemcuTpiuSportszW :: new (self , 0) } } # [doc = "Supported port sizes\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_sportsz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_sportsz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuSportszSpec ; impl crate :: RegisterSpec for OnemcuTpiuSportszSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_sportsz::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuSportszSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_sportsz::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuSportszSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_SPORTSZ to value 0"]
impl crate :: Resettable for OnemcuTpiuSportszSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CPORTSZ (rw) register accessor: Current port size\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cportsz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cportsz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_cportsz`]
module"]
# [doc (alias = "ONEMCU_TPIU_CPORTSZ")]
pub type OnemcuTpiuCportsz = crate :: Reg < onemcu_tpiu_cportsz :: OnemcuTpiuCportszSpec > ; # [doc = "Current port size"]
pub mod onemcu_tpiu_cportsz { # [doc = "Register `ONEMCU_TPIU_CPORTSZ` reader"]
pub type R = crate :: R < OnemcuTpiuCportszSpec > ; # [doc = "Register `ONEMCU_TPIU_CPORTSZ` writer"]
pub type W = crate :: W < OnemcuTpiuCportszSpec > ; # [doc = "Field `ONEMCU_TPIU_CPORTSZ` reader - 31:0\\]
Current port size"]
pub type OnemcuTpiuCportszR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CPORTSZ` writer - 31:0\\]
Current port size"]
pub type OnemcuTpiuCportszW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Current port size"]
# [inline (always)]
pub fn onemcu_tpiu_cportsz (& self) -> OnemcuTpiuCportszR { OnemcuTpiuCportszR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Current port size"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_cportsz (& mut self) -> OnemcuTpiuCportszW < OnemcuTpiuCportszSpec > { OnemcuTpiuCportszW :: new (self , 0) } } # [doc = "Current port size\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cportsz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cportsz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuCportszSpec ; impl crate :: RegisterSpec for OnemcuTpiuCportszSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_cportsz::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuCportszSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_cportsz::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuCportszSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CPORTSZ to value 0"]
impl crate :: Resettable for OnemcuTpiuCportszSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_STRIGM (rw) register accessor: Supported trigger modes\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_strigm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_strigm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_strigm`]
module"]
# [doc (alias = "ONEMCU_TPIU_STRIGM")]
pub type OnemcuTpiuStrigm = crate :: Reg < onemcu_tpiu_strigm :: OnemcuTpiuStrigmSpec > ; # [doc = "Supported trigger modes"]
pub mod onemcu_tpiu_strigm { # [doc = "Register `ONEMCU_TPIU_STRIGM` reader"]
pub type R = crate :: R < OnemcuTpiuStrigmSpec > ; # [doc = "Register `ONEMCU_TPIU_STRIGM` writer"]
pub type W = crate :: W < OnemcuTpiuStrigmSpec > ; # [doc = "Field `ONEMCU_TPIU_STRIGM` reader - 31:0\\]
Supported trigger modes"]
pub type OnemcuTpiuStrigmR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_STRIGM` writer - 31:0\\]
Supported trigger modes"]
pub type OnemcuTpiuStrigmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Supported trigger modes"]
# [inline (always)]
pub fn onemcu_tpiu_strigm (& self) -> OnemcuTpiuStrigmR { OnemcuTpiuStrigmR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Supported trigger modes"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_strigm (& mut self) -> OnemcuTpiuStrigmW < OnemcuTpiuStrigmSpec > { OnemcuTpiuStrigmW :: new (self , 0) } } # [doc = "Supported trigger modes\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_strigm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_strigm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuStrigmSpec ; impl crate :: RegisterSpec for OnemcuTpiuStrigmSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_strigm::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuStrigmSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_strigm::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuStrigmSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_STRIGM to value 0"]
impl crate :: Resettable for OnemcuTpiuStrigmSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_TRIGCNT (rw) register accessor: Trigger counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_trigcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_trigcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_trigcnt`]
module"]
# [doc (alias = "ONEMCU_TPIU_TRIGCNT")]
pub type OnemcuTpiuTrigcnt = crate :: Reg < onemcu_tpiu_trigcnt :: OnemcuTpiuTrigcntSpec > ; # [doc = "Trigger counter value"]
pub mod onemcu_tpiu_trigcnt { # [doc = "Register `ONEMCU_TPIU_TRIGCNT` reader"]
pub type R = crate :: R < OnemcuTpiuTrigcntSpec > ; # [doc = "Register `ONEMCU_TPIU_TRIGCNT` writer"]
pub type W = crate :: W < OnemcuTpiuTrigcntSpec > ; # [doc = "Field `ONEMCU_TPIU_TRIGCNT` reader - 31:0\\]
Trigger counter value"]
pub type OnemcuTpiuTrigcntR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_TRIGCNT` writer - 31:0\\]
Trigger counter value"]
pub type OnemcuTpiuTrigcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Trigger counter value"]
# [inline (always)]
pub fn onemcu_tpiu_trigcnt (& self) -> OnemcuTpiuTrigcntR { OnemcuTpiuTrigcntR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Trigger counter value"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_trigcnt (& mut self) -> OnemcuTpiuTrigcntW < OnemcuTpiuTrigcntSpec > { OnemcuTpiuTrigcntW :: new (self , 0) } } # [doc = "Trigger counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_trigcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_trigcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuTrigcntSpec ; impl crate :: RegisterSpec for OnemcuTpiuTrigcntSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_trigcnt::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuTrigcntSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_trigcnt::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuTrigcntSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_TRIGCNT to value 0"]
impl crate :: Resettable for OnemcuTpiuTrigcntSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_TRIGMUL (rw) register accessor: Trigger multiplier\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_trigmul::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_trigmul::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_trigmul`]
module"]
# [doc (alias = "ONEMCU_TPIU_TRIGMUL")]
pub type OnemcuTpiuTrigmul = crate :: Reg < onemcu_tpiu_trigmul :: OnemcuTpiuTrigmulSpec > ; # [doc = "Trigger multiplier"]
pub mod onemcu_tpiu_trigmul { # [doc = "Register `ONEMCU_TPIU_TRIGMUL` reader"]
pub type R = crate :: R < OnemcuTpiuTrigmulSpec > ; # [doc = "Register `ONEMCU_TPIU_TRIGMUL` writer"]
pub type W = crate :: W < OnemcuTpiuTrigmulSpec > ; # [doc = "Field `ONEMCU_TPIU_TRIGMUL` reader - 31:0\\]
Trigger multiplier"]
pub type OnemcuTpiuTrigmulR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_TRIGMUL` writer - 31:0\\]
Trigger multiplier"]
pub type OnemcuTpiuTrigmulW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Trigger multiplier"]
# [inline (always)]
pub fn onemcu_tpiu_trigmul (& self) -> OnemcuTpiuTrigmulR { OnemcuTpiuTrigmulR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Trigger multiplier"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_trigmul (& mut self) -> OnemcuTpiuTrigmulW < OnemcuTpiuTrigmulSpec > { OnemcuTpiuTrigmulW :: new (self , 0) } } # [doc = "Trigger multiplier\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_trigmul::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_trigmul::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuTrigmulSpec ; impl crate :: RegisterSpec for OnemcuTpiuTrigmulSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_trigmul::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuTrigmulSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_trigmul::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuTrigmulSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_TRIGMUL to value 0"]
impl crate :: Resettable for OnemcuTpiuTrigmulSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_STSTPTRN (rw) register accessor: Supported test pattern/modes\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ststptrn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ststptrn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_ststptrn`]
module"]
# [doc (alias = "ONEMCU_TPIU_STSTPTRN")]
pub type OnemcuTpiuStstptrn = crate :: Reg < onemcu_tpiu_ststptrn :: OnemcuTpiuStstptrnSpec > ; # [doc = "Supported test pattern/modes"]
pub mod onemcu_tpiu_ststptrn { # [doc = "Register `ONEMCU_TPIU_STSTPTRN` reader"]
pub type R = crate :: R < OnemcuTpiuStstptrnSpec > ; # [doc = "Register `ONEMCU_TPIU_STSTPTRN` writer"]
pub type W = crate :: W < OnemcuTpiuStstptrnSpec > ; # [doc = "Field `ONEMCU_TPIU_STSTPTRN` reader - 31:0\\]
Supported test pattern/modes"]
pub type OnemcuTpiuStstptrnR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_STSTPTRN` writer - 31:0\\]
Supported test pattern/modes"]
pub type OnemcuTpiuStstptrnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Supported test pattern/modes"]
# [inline (always)]
pub fn onemcu_tpiu_ststptrn (& self) -> OnemcuTpiuStstptrnR { OnemcuTpiuStstptrnR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Supported test pattern/modes"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_ststptrn (& mut self) -> OnemcuTpiuStstptrnW < OnemcuTpiuStstptrnSpec > { OnemcuTpiuStstptrnW :: new (self , 0) } } # [doc = "Supported test pattern/modes\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ststptrn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ststptrn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuStstptrnSpec ; impl crate :: RegisterSpec for OnemcuTpiuStstptrnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_ststptrn::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuStstptrnSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_ststptrn::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuStstptrnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_STSTPTRN to value 0"]
impl crate :: Resettable for OnemcuTpiuStstptrnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CTSTPTRN (rw) register accessor: Current test pattern/mode\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ctstptrn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ctstptrn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_ctstptrn`]
module"]
# [doc (alias = "ONEMCU_TPIU_CTSTPTRN")]
pub type OnemcuTpiuCtstptrn = crate :: Reg < onemcu_tpiu_ctstptrn :: OnemcuTpiuCtstptrnSpec > ; # [doc = "Current test pattern/mode"]
pub mod onemcu_tpiu_ctstptrn { # [doc = "Register `ONEMCU_TPIU_CTSTPTRN` reader"]
pub type R = crate :: R < OnemcuTpiuCtstptrnSpec > ; # [doc = "Register `ONEMCU_TPIU_CTSTPTRN` writer"]
pub type W = crate :: W < OnemcuTpiuCtstptrnSpec > ; # [doc = "Field `ONEMCU_TPIU_CTSTPTRN` reader - 31:0\\]
Current test pattern/mode"]
pub type OnemcuTpiuCtstptrnR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CTSTPTRN` writer - 31:0\\]
Current test pattern/mode"]
pub type OnemcuTpiuCtstptrnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Current test pattern/mode"]
# [inline (always)]
pub fn onemcu_tpiu_ctstptrn (& self) -> OnemcuTpiuCtstptrnR { OnemcuTpiuCtstptrnR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Current test pattern/mode"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_ctstptrn (& mut self) -> OnemcuTpiuCtstptrnW < OnemcuTpiuCtstptrnSpec > { OnemcuTpiuCtstptrnW :: new (self , 0) } } # [doc = "Current test pattern/mode\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ctstptrn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ctstptrn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuCtstptrnSpec ; impl crate :: RegisterSpec for OnemcuTpiuCtstptrnSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_ctstptrn::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuCtstptrnSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_ctstptrn::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuCtstptrnSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CTSTPTRN to value 0"]
impl crate :: Resettable for OnemcuTpiuCtstptrnSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_TPRCNTR (rw) register accessor: Test pattern repeat counter\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_tprcntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_tprcntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_tprcntr`]
module"]
# [doc (alias = "ONEMCU_TPIU_TPRCNTR")]
pub type OnemcuTpiuTprcntr = crate :: Reg < onemcu_tpiu_tprcntr :: OnemcuTpiuTprcntrSpec > ; # [doc = "Test pattern repeat counter"]
pub mod onemcu_tpiu_tprcntr { # [doc = "Register `ONEMCU_TPIU_TPRCNTR` reader"]
pub type R = crate :: R < OnemcuTpiuTprcntrSpec > ; # [doc = "Register `ONEMCU_TPIU_TPRCNTR` writer"]
pub type W = crate :: W < OnemcuTpiuTprcntrSpec > ; # [doc = "Field `ONEMCU_TPIU_TPRCNTR` reader - 31:0\\]
Test pattern repeat counter"]
pub type OnemcuTpiuTprcntrR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_TPRCNTR` writer - 31:0\\]
Test pattern repeat counter"]
pub type OnemcuTpiuTprcntrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Test pattern repeat counter"]
# [inline (always)]
pub fn onemcu_tpiu_tprcntr (& self) -> OnemcuTpiuTprcntrR { OnemcuTpiuTprcntrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Test pattern repeat counter"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_tprcntr (& mut self) -> OnemcuTpiuTprcntrW < OnemcuTpiuTprcntrSpec > { OnemcuTpiuTprcntrW :: new (self , 0) } } # [doc = "Test pattern repeat counter\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_tprcntr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_tprcntr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuTprcntrSpec ; impl crate :: RegisterSpec for OnemcuTpiuTprcntrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_tprcntr::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuTprcntrSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_tprcntr::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuTprcntrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_TPRCNTR to value 0"]
impl crate :: Resettable for OnemcuTpiuTprcntrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_FFSTS (rw) register accessor: Formatter and flush status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ffsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ffsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_ffsts`]
module"]
# [doc (alias = "ONEMCU_TPIU_FFSTS")]
pub type OnemcuTpiuFfsts = crate :: Reg < onemcu_tpiu_ffsts :: OnemcuTpiuFfstsSpec > ; # [doc = "Formatter and flush status"]
pub mod onemcu_tpiu_ffsts { # [doc = "Register `ONEMCU_TPIU_FFSTS` reader"]
pub type R = crate :: R < OnemcuTpiuFfstsSpec > ; # [doc = "Register `ONEMCU_TPIU_FFSTS` writer"]
pub type W = crate :: W < OnemcuTpiuFfstsSpec > ; # [doc = "Field `ONEMCU_TPIU_FFSTS` reader - 31:0\\]
Formatter and flush status"]
pub type OnemcuTpiuFfstsR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_FFSTS` writer - 31:0\\]
Formatter and flush status"]
pub type OnemcuTpiuFfstsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Formatter and flush status"]
# [inline (always)]
pub fn onemcu_tpiu_ffsts (& self) -> OnemcuTpiuFfstsR { OnemcuTpiuFfstsR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Formatter and flush status"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_ffsts (& mut self) -> OnemcuTpiuFfstsW < OnemcuTpiuFfstsSpec > { OnemcuTpiuFfstsW :: new (self , 0) } } # [doc = "Formatter and flush status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ffsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ffsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuFfstsSpec ; impl crate :: RegisterSpec for OnemcuTpiuFfstsSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_ffsts::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuFfstsSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_ffsts::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuFfstsSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_FFSTS to value 0"]
impl crate :: Resettable for OnemcuTpiuFfstsSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_FFCTRL (rw) register accessor: Formatter and flush control\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ffctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ffctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_ffctrl`]
module"]
# [doc (alias = "ONEMCU_TPIU_FFCTRL")]
pub type OnemcuTpiuFfctrl = crate :: Reg < onemcu_tpiu_ffctrl :: OnemcuTpiuFfctrlSpec > ; # [doc = "Formatter and flush control"]
pub mod onemcu_tpiu_ffctrl { # [doc = "Register `ONEMCU_TPIU_FFCTRL` reader"]
pub type R = crate :: R < OnemcuTpiuFfctrlSpec > ; # [doc = "Register `ONEMCU_TPIU_FFCTRL` writer"]
pub type W = crate :: W < OnemcuTpiuFfctrlSpec > ; # [doc = "Field `ONEMCU_TPIU_FFCTRL` reader - 31:0\\]
Formatter and flush control"]
pub type OnemcuTpiuFfctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_FFCTRL` writer - 31:0\\]
Formatter and flush control"]
pub type OnemcuTpiuFfctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Formatter and flush control"]
# [inline (always)]
pub fn onemcu_tpiu_ffctrl (& self) -> OnemcuTpiuFfctrlR { OnemcuTpiuFfctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Formatter and flush control"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_ffctrl (& mut self) -> OnemcuTpiuFfctrlW < OnemcuTpiuFfctrlSpec > { OnemcuTpiuFfctrlW :: new (self , 0) } } # [doc = "Formatter and flush control\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ffctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ffctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuFfctrlSpec ; impl crate :: RegisterSpec for OnemcuTpiuFfctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_ffctrl::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuFfctrlSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_ffctrl::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuFfctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_FFCTRL to value 0"]
impl crate :: Resettable for OnemcuTpiuFfctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_FSCNTR (rw) register accessor: Formatter synchronization counter\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_fscntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_fscntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_fscntr`]
module"]
# [doc (alias = "ONEMCU_TPIU_FSCNTR")]
pub type OnemcuTpiuFscntr = crate :: Reg < onemcu_tpiu_fscntr :: OnemcuTpiuFscntrSpec > ; # [doc = "Formatter synchronization counter"]
pub mod onemcu_tpiu_fscntr { # [doc = "Register `ONEMCU_TPIU_FSCNTR` reader"]
pub type R = crate :: R < OnemcuTpiuFscntrSpec > ; # [doc = "Register `ONEMCU_TPIU_FSCNTR` writer"]
pub type W = crate :: W < OnemcuTpiuFscntrSpec > ; # [doc = "Field `ONEMCU_TPIU_FSCNTR` reader - 31:0\\]
Formatter synchronization counter"]
pub type OnemcuTpiuFscntrR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_FSCNTR` writer - 31:0\\]
Formatter synchronization counter"]
pub type OnemcuTpiuFscntrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Formatter synchronization counter"]
# [inline (always)]
pub fn onemcu_tpiu_fscntr (& self) -> OnemcuTpiuFscntrR { OnemcuTpiuFscntrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Formatter synchronization counter"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_fscntr (& mut self) -> OnemcuTpiuFscntrW < OnemcuTpiuFscntrSpec > { OnemcuTpiuFscntrW :: new (self , 0) } } # [doc = "Formatter synchronization counter\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_fscntr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_fscntr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuFscntrSpec ; impl crate :: RegisterSpec for OnemcuTpiuFscntrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_fscntr::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuFscntrSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_fscntr::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuFscntrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_FSCNTR to value 0"]
impl crate :: Resettable for OnemcuTpiuFscntrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_EXCTLIN (rw) register accessor: EXTCTL In Port\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_exctlin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_exctlin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_exctlin`]
module"]
# [doc (alias = "ONEMCU_TPIU_EXCTLIN")]
pub type OnemcuTpiuExctlin = crate :: Reg < onemcu_tpiu_exctlin :: OnemcuTpiuExctlinSpec > ; # [doc = "EXTCTL In Port"]
pub mod onemcu_tpiu_exctlin { # [doc = "Register `ONEMCU_TPIU_EXCTLIN` reader"]
pub type R = crate :: R < OnemcuTpiuExctlinSpec > ; # [doc = "Register `ONEMCU_TPIU_EXCTLIN` writer"]
pub type W = crate :: W < OnemcuTpiuExctlinSpec > ; # [doc = "Field `ONEMCU_TPIU_EXCTLIN` reader - 31:0\\]
EXTCTL In Port"]
pub type OnemcuTpiuExctlinR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_EXCTLIN` writer - 31:0\\]
EXTCTL In Port"]
pub type OnemcuTpiuExctlinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
EXTCTL In Port"]
# [inline (always)]
pub fn onemcu_tpiu_exctlin (& self) -> OnemcuTpiuExctlinR { OnemcuTpiuExctlinR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
EXTCTL In Port"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_exctlin (& mut self) -> OnemcuTpiuExctlinW < OnemcuTpiuExctlinSpec > { OnemcuTpiuExctlinW :: new (self , 0) } } # [doc = "EXTCTL In Port\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_exctlin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_exctlin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuExctlinSpec ; impl crate :: RegisterSpec for OnemcuTpiuExctlinSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_exctlin::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuExctlinSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_exctlin::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuExctlinSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_EXCTLIN to value 0"]
impl crate :: Resettable for OnemcuTpiuExctlinSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_EXCTLOUT (rw) register accessor: EXTCTL Out Port\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_exctlout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_exctlout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_exctlout`]
module"]
# [doc (alias = "ONEMCU_TPIU_EXCTLOUT")]
pub type OnemcuTpiuExctlout = crate :: Reg < onemcu_tpiu_exctlout :: OnemcuTpiuExctloutSpec > ; # [doc = "EXTCTL Out Port"]
pub mod onemcu_tpiu_exctlout { # [doc = "Register `ONEMCU_TPIU_EXCTLOUT` reader"]
pub type R = crate :: R < OnemcuTpiuExctloutSpec > ; # [doc = "Register `ONEMCU_TPIU_EXCTLOUT` writer"]
pub type W = crate :: W < OnemcuTpiuExctloutSpec > ; # [doc = "Field `ONEMCU_TPIU_EXCTLOUT` reader - 31:0\\]
EXTCTL Out Port"]
pub type OnemcuTpiuExctloutR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_EXCTLOUT` writer - 31:0\\]
EXTCTL Out Port"]
pub type OnemcuTpiuExctloutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
EXTCTL Out Port"]
# [inline (always)]
pub fn onemcu_tpiu_exctlout (& self) -> OnemcuTpiuExctloutR { OnemcuTpiuExctloutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
EXTCTL Out Port"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_exctlout (& mut self) -> OnemcuTpiuExctloutW < OnemcuTpiuExctloutSpec > { OnemcuTpiuExctloutW :: new (self , 0) } } # [doc = "EXTCTL Out Port\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_exctlout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_exctlout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuExctloutSpec ; impl crate :: RegisterSpec for OnemcuTpiuExctloutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_exctlout::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuExctloutSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_exctlout::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuExctloutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_EXCTLOUT to value 0"]
impl crate :: Resettable for OnemcuTpiuExctloutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITTRFLINACK (rw) register accessor: Integration Register, ITTRFLINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ittrflinack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ittrflinack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_ittrflinack`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITTRFLINACK")]
pub type OnemcuTpiuIttrflinack = crate :: Reg < onemcu_tpiu_ittrflinack :: OnemcuTpiuIttrflinackSpec > ; # [doc = "Integration Register, ITTRFLINACK"]
pub mod onemcu_tpiu_ittrflinack { # [doc = "Register `ONEMCU_TPIU_ITTRFLINACK` reader"]
pub type R = crate :: R < OnemcuTpiuIttrflinackSpec > ; # [doc = "Register `ONEMCU_TPIU_ITTRFLINACK` writer"]
pub type W = crate :: W < OnemcuTpiuIttrflinackSpec > ; # [doc = "Field `ONEMCU_TPIU_ITTRFLINACK` reader - 31:0\\]
Integration Register, ITTRFLINACK"]
pub type OnemcuTpiuIttrflinackR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITTRFLINACK` writer - 31:0\\]
Integration Register, ITTRFLINACK"]
pub type OnemcuTpiuIttrflinackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITTRFLINACK"]
# [inline (always)]
pub fn onemcu_tpiu_ittrflinack (& self) -> OnemcuTpiuIttrflinackR { OnemcuTpiuIttrflinackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITTRFLINACK"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_ittrflinack (& mut self) -> OnemcuTpiuIttrflinackW < OnemcuTpiuIttrflinackSpec > { OnemcuTpiuIttrflinackW :: new (self , 0) } } # [doc = "Integration Register, ITTRFLINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ittrflinack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ittrflinack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuIttrflinackSpec ; impl crate :: RegisterSpec for OnemcuTpiuIttrflinackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_ittrflinack::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuIttrflinackSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_ittrflinack::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuIttrflinackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITTRFLINACK to value 0"]
impl crate :: Resettable for OnemcuTpiuIttrflinackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITTRFLIN (rw) register accessor: Integration Register, ITTRFLIN\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ittrflin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ittrflin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_ittrflin`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITTRFLIN")]
pub type OnemcuTpiuIttrflin = crate :: Reg < onemcu_tpiu_ittrflin :: OnemcuTpiuIttrflinSpec > ; # [doc = "Integration Register, ITTRFLIN"]
pub mod onemcu_tpiu_ittrflin { # [doc = "Register `ONEMCU_TPIU_ITTRFLIN` reader"]
pub type R = crate :: R < OnemcuTpiuIttrflinSpec > ; # [doc = "Register `ONEMCU_TPIU_ITTRFLIN` writer"]
pub type W = crate :: W < OnemcuTpiuIttrflinSpec > ; # [doc = "Field `ONEMCU_TPIU_ITTRFLIN` reader - 31:0\\]
Integration Register, ITTRFLIN"]
pub type OnemcuTpiuIttrflinR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITTRFLIN` writer - 31:0\\]
Integration Register, ITTRFLIN"]
pub type OnemcuTpiuIttrflinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITTRFLIN"]
# [inline (always)]
pub fn onemcu_tpiu_ittrflin (& self) -> OnemcuTpiuIttrflinR { OnemcuTpiuIttrflinR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITTRFLIN"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_ittrflin (& mut self) -> OnemcuTpiuIttrflinW < OnemcuTpiuIttrflinSpec > { OnemcuTpiuIttrflinW :: new (self , 0) } } # [doc = "Integration Register, ITTRFLIN\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_ittrflin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_ittrflin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuIttrflinSpec ; impl crate :: RegisterSpec for OnemcuTpiuIttrflinSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_ittrflin::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuIttrflinSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_ittrflin::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuIttrflinSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITTRFLIN to value 0"]
impl crate :: Resettable for OnemcuTpiuIttrflinSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITATBDATA0 (rw) register accessor: Integration Register, ITATBDATA0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbdata0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbdata0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_itatbdata0`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITATBDATA0")]
pub type OnemcuTpiuItatbdata0 = crate :: Reg < onemcu_tpiu_itatbdata0 :: OnemcuTpiuItatbdata0Spec > ; # [doc = "Integration Register, ITATBDATA0"]
pub mod onemcu_tpiu_itatbdata0 { # [doc = "Register `ONEMCU_TPIU_ITATBDATA0` reader"]
pub type R = crate :: R < OnemcuTpiuItatbdata0Spec > ; # [doc = "Register `ONEMCU_TPIU_ITATBDATA0` writer"]
pub type W = crate :: W < OnemcuTpiuItatbdata0Spec > ; # [doc = "Field `ONEMCU_TPIU_ITATBDATA0` reader - 31:0\\]
Integration Register, ITATBDATA0"]
pub type OnemcuTpiuItatbdata0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITATBDATA0` writer - 31:0\\]
Integration Register, ITATBDATA0"]
pub type OnemcuTpiuItatbdata0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBDATA0"]
# [inline (always)]
pub fn onemcu_tpiu_itatbdata0 (& self) -> OnemcuTpiuItatbdata0R { OnemcuTpiuItatbdata0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBDATA0"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_itatbdata0 (& mut self) -> OnemcuTpiuItatbdata0W < OnemcuTpiuItatbdata0Spec > { OnemcuTpiuItatbdata0W :: new (self , 0) } } # [doc = "Integration Register, ITATBDATA0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbdata0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbdata0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuItatbdata0Spec ; impl crate :: RegisterSpec for OnemcuTpiuItatbdata0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_itatbdata0::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuItatbdata0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_itatbdata0::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuItatbdata0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITATBDATA0 to value 0"]
impl crate :: Resettable for OnemcuTpiuItatbdata0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITATBCTR2 (rw) register accessor: Integration Register, ITATBCTR2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbctr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbctr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_itatbctr2`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITATBCTR2")]
pub type OnemcuTpiuItatbctr2 = crate :: Reg < onemcu_tpiu_itatbctr2 :: OnemcuTpiuItatbctr2Spec > ; # [doc = "Integration Register, ITATBCTR2"]
pub mod onemcu_tpiu_itatbctr2 { # [doc = "Register `ONEMCU_TPIU_ITATBCTR2` reader"]
pub type R = crate :: R < OnemcuTpiuItatbctr2Spec > ; # [doc = "Register `ONEMCU_TPIU_ITATBCTR2` writer"]
pub type W = crate :: W < OnemcuTpiuItatbctr2Spec > ; # [doc = "Field `ONEMCU_TPIU_ITATBCTR2` reader - 31:0\\]
Integration Register, ITATBCTR2"]
pub type OnemcuTpiuItatbctr2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITATBCTR2` writer - 31:0\\]
Integration Register, ITATBCTR2"]
pub type OnemcuTpiuItatbctr2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBCTR2"]
# [inline (always)]
pub fn onemcu_tpiu_itatbctr2 (& self) -> OnemcuTpiuItatbctr2R { OnemcuTpiuItatbctr2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBCTR2"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_itatbctr2 (& mut self) -> OnemcuTpiuItatbctr2W < OnemcuTpiuItatbctr2Spec > { OnemcuTpiuItatbctr2W :: new (self , 0) } } # [doc = "Integration Register, ITATBCTR2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbctr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbctr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuItatbctr2Spec ; impl crate :: RegisterSpec for OnemcuTpiuItatbctr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_itatbctr2::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuItatbctr2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_itatbctr2::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuItatbctr2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITATBCTR2 to value 0"]
impl crate :: Resettable for OnemcuTpiuItatbctr2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITATBCTR1 (rw) register accessor: Integration Register, ITATBCTR1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbctr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbctr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_itatbctr1`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITATBCTR1")]
pub type OnemcuTpiuItatbctr1 = crate :: Reg < onemcu_tpiu_itatbctr1 :: OnemcuTpiuItatbctr1Spec > ; # [doc = "Integration Register, ITATBCTR1"]
pub mod onemcu_tpiu_itatbctr1 { # [doc = "Register `ONEMCU_TPIU_ITATBCTR1` reader"]
pub type R = crate :: R < OnemcuTpiuItatbctr1Spec > ; # [doc = "Register `ONEMCU_TPIU_ITATBCTR1` writer"]
pub type W = crate :: W < OnemcuTpiuItatbctr1Spec > ; # [doc = "Field `ONEMCU_TPIU_ITATBCTR1` reader - 31:0\\]
Integration Register, ITATBCTR1"]
pub type OnemcuTpiuItatbctr1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITATBCTR1` writer - 31:0\\]
Integration Register, ITATBCTR1"]
pub type OnemcuTpiuItatbctr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBCTR1"]
# [inline (always)]
pub fn onemcu_tpiu_itatbctr1 (& self) -> OnemcuTpiuItatbctr1R { OnemcuTpiuItatbctr1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBCTR1"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_itatbctr1 (& mut self) -> OnemcuTpiuItatbctr1W < OnemcuTpiuItatbctr1Spec > { OnemcuTpiuItatbctr1W :: new (self , 0) } } # [doc = "Integration Register, ITATBCTR1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbctr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbctr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuItatbctr1Spec ; impl crate :: RegisterSpec for OnemcuTpiuItatbctr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_itatbctr1::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuItatbctr1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_itatbctr1::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuItatbctr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITATBCTR1 to value 0"]
impl crate :: Resettable for OnemcuTpiuItatbctr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITATBCTR0 (rw) register accessor: Integration Register, ITATBCTR0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbctr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbctr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_itatbctr0`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITATBCTR0")]
pub type OnemcuTpiuItatbctr0 = crate :: Reg < onemcu_tpiu_itatbctr0 :: OnemcuTpiuItatbctr0Spec > ; # [doc = "Integration Register, ITATBCTR0"]
pub mod onemcu_tpiu_itatbctr0 { # [doc = "Register `ONEMCU_TPIU_ITATBCTR0` reader"]
pub type R = crate :: R < OnemcuTpiuItatbctr0Spec > ; # [doc = "Register `ONEMCU_TPIU_ITATBCTR0` writer"]
pub type W = crate :: W < OnemcuTpiuItatbctr0Spec > ; # [doc = "Field `ONEMCU_TPIU_ITATBCTR0` reader - 31:0\\]
Integration Register, ITATBCTR0"]
pub type OnemcuTpiuItatbctr0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITATBCTR0` writer - 31:0\\]
Integration Register, ITATBCTR0"]
pub type OnemcuTpiuItatbctr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBCTR0"]
# [inline (always)]
pub fn onemcu_tpiu_itatbctr0 (& self) -> OnemcuTpiuItatbctr0R { OnemcuTpiuItatbctr0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Register, ITATBCTR0"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_itatbctr0 (& mut self) -> OnemcuTpiuItatbctr0W < OnemcuTpiuItatbctr0Spec > { OnemcuTpiuItatbctr0W :: new (self , 0) } } # [doc = "Integration Register, ITATBCTR0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itatbctr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itatbctr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuItatbctr0Spec ; impl crate :: RegisterSpec for OnemcuTpiuItatbctr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_itatbctr0::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuItatbctr0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_itatbctr0::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuItatbctr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITATBCTR0 to value 0"]
impl crate :: Resettable for OnemcuTpiuItatbctr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_ITCTRL (rw) register accessor: Integration Mode Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_itctrl`]
module"]
# [doc (alias = "ONEMCU_TPIU_ITCTRL")]
pub type OnemcuTpiuItctrl = crate :: Reg < onemcu_tpiu_itctrl :: OnemcuTpiuItctrlSpec > ; # [doc = "Integration Mode Control Register"]
pub mod onemcu_tpiu_itctrl { # [doc = "Register `ONEMCU_TPIU_ITCTRL` reader"]
pub type R = crate :: R < OnemcuTpiuItctrlSpec > ; # [doc = "Register `ONEMCU_TPIU_ITCTRL` writer"]
pub type W = crate :: W < OnemcuTpiuItctrlSpec > ; # [doc = "Field `ONEMCU_TPIU_ITCTRL` reader - 31:0\\]
Integration Mode Control Register"]
pub type OnemcuTpiuItctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_ITCTRL` writer - 31:0\\]
Integration Mode Control Register"]
pub type OnemcuTpiuItctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Integration Mode Control Register"]
# [inline (always)]
pub fn onemcu_tpiu_itctrl (& self) -> OnemcuTpiuItctrlR { OnemcuTpiuItctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Integration Mode Control Register"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_itctrl (& mut self) -> OnemcuTpiuItctrlW < OnemcuTpiuItctrlSpec > { OnemcuTpiuItctrlW :: new (self , 0) } } # [doc = "Integration Mode Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_itctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_itctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuItctrlSpec ; impl crate :: RegisterSpec for OnemcuTpiuItctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_itctrl::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuItctrlSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_itctrl::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuItctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_ITCTRL to value 0"]
impl crate :: Resettable for OnemcuTpiuItctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CLAIMSET (rw) register accessor: Claim Tag Set\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_claimset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_claimset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_claimset`]
module"]
# [doc (alias = "ONEMCU_TPIU_CLAIMSET")]
pub type OnemcuTpiuClaimset = crate :: Reg < onemcu_tpiu_claimset :: OnemcuTpiuClaimsetSpec > ; # [doc = "Claim Tag Set"]
pub mod onemcu_tpiu_claimset { # [doc = "Register `ONEMCU_TPIU_CLAIMSET` reader"]
pub type R = crate :: R < OnemcuTpiuClaimsetSpec > ; # [doc = "Register `ONEMCU_TPIU_CLAIMSET` writer"]
pub type W = crate :: W < OnemcuTpiuClaimsetSpec > ; # [doc = "Field `ONEMCU_TPIU_CLAIMSET` reader - 31:0\\]
Claim Tag Set"]
pub type OnemcuTpiuClaimsetR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CLAIMSET` writer - 31:0\\]
Claim Tag Set"]
pub type OnemcuTpiuClaimsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Claim Tag Set"]
# [inline (always)]
pub fn onemcu_tpiu_claimset (& self) -> OnemcuTpiuClaimsetR { OnemcuTpiuClaimsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Claim Tag Set"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_claimset (& mut self) -> OnemcuTpiuClaimsetW < OnemcuTpiuClaimsetSpec > { OnemcuTpiuClaimsetW :: new (self , 0) } } # [doc = "Claim Tag Set\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_claimset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_claimset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuClaimsetSpec ; impl crate :: RegisterSpec for OnemcuTpiuClaimsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_claimset::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuClaimsetSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_claimset::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuClaimsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CLAIMSET to value 0"]
impl crate :: Resettable for OnemcuTpiuClaimsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CLAIMCLR (rw) register accessor: Claim Tag Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_claimclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_claimclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_claimclr`]
module"]
# [doc (alias = "ONEMCU_TPIU_CLAIMCLR")]
pub type OnemcuTpiuClaimclr = crate :: Reg < onemcu_tpiu_claimclr :: OnemcuTpiuClaimclrSpec > ; # [doc = "Claim Tag Clear"]
pub mod onemcu_tpiu_claimclr { # [doc = "Register `ONEMCU_TPIU_CLAIMCLR` reader"]
pub type R = crate :: R < OnemcuTpiuClaimclrSpec > ; # [doc = "Register `ONEMCU_TPIU_CLAIMCLR` writer"]
pub type W = crate :: W < OnemcuTpiuClaimclrSpec > ; # [doc = "Field `ONEMCU_TPIU_CLAIMCLR` reader - 31:0\\]
Claim Tag Clear"]
pub type OnemcuTpiuClaimclrR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CLAIMCLR` writer - 31:0\\]
Claim Tag Clear"]
pub type OnemcuTpiuClaimclrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Claim Tag Clear"]
# [inline (always)]
pub fn onemcu_tpiu_claimclr (& self) -> OnemcuTpiuClaimclrR { OnemcuTpiuClaimclrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Claim Tag Clear"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_claimclr (& mut self) -> OnemcuTpiuClaimclrW < OnemcuTpiuClaimclrSpec > { OnemcuTpiuClaimclrW :: new (self , 0) } } # [doc = "Claim Tag Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_claimclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_claimclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuClaimclrSpec ; impl crate :: RegisterSpec for OnemcuTpiuClaimclrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_claimclr::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuClaimclrSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_claimclr::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuClaimclrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CLAIMCLR to value 0"]
impl crate :: Resettable for OnemcuTpiuClaimclrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_LAR (rw) register accessor: Lock status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_lar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_lar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_lar`]
module"]
# [doc (alias = "ONEMCU_TPIU_LAR")]
pub type OnemcuTpiuLar = crate :: Reg < onemcu_tpiu_lar :: OnemcuTpiuLarSpec > ; # [doc = "Lock status"]
pub mod onemcu_tpiu_lar { # [doc = "Register `ONEMCU_TPIU_LAR` reader"]
pub type R = crate :: R < OnemcuTpiuLarSpec > ; # [doc = "Register `ONEMCU_TPIU_LAR` writer"]
pub type W = crate :: W < OnemcuTpiuLarSpec > ; # [doc = "Field `ONEMCU_TPIU_LAR` reader - 31:0\\]
Lock status"]
pub type OnemcuTpiuLarR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_LAR` writer - 31:0\\]
Lock status"]
pub type OnemcuTpiuLarW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Lock status"]
# [inline (always)]
pub fn onemcu_tpiu_lar (& self) -> OnemcuTpiuLarR { OnemcuTpiuLarR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Lock status"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_lar (& mut self) -> OnemcuTpiuLarW < OnemcuTpiuLarSpec > { OnemcuTpiuLarW :: new (self , 0) } } # [doc = "Lock status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_lar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_lar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuLarSpec ; impl crate :: RegisterSpec for OnemcuTpiuLarSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_lar::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuLarSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_lar::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuLarSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_LAR to value 0"]
impl crate :: Resettable for OnemcuTpiuLarSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_LSR (rw) register accessor: Lock Access\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_lsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_lsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_lsr`]
module"]
# [doc (alias = "ONEMCU_TPIU_LSR")]
pub type OnemcuTpiuLsr = crate :: Reg < onemcu_tpiu_lsr :: OnemcuTpiuLsrSpec > ; # [doc = "Lock Access"]
pub mod onemcu_tpiu_lsr { # [doc = "Register `ONEMCU_TPIU_LSR` reader"]
pub type R = crate :: R < OnemcuTpiuLsrSpec > ; # [doc = "Register `ONEMCU_TPIU_LSR` writer"]
pub type W = crate :: W < OnemcuTpiuLsrSpec > ; # [doc = "Field `ONEMCU_TPIU_LSR` reader - 31:0\\]
Lock Access"]
pub type OnemcuTpiuLsrR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_LSR` writer - 31:0\\]
Lock Access"]
pub type OnemcuTpiuLsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Lock Access"]
# [inline (always)]
pub fn onemcu_tpiu_lsr (& self) -> OnemcuTpiuLsrR { OnemcuTpiuLsrR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Lock Access"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_lsr (& mut self) -> OnemcuTpiuLsrW < OnemcuTpiuLsrSpec > { OnemcuTpiuLsrW :: new (self , 0) } } # [doc = "Lock Access\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_lsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_lsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuLsrSpec ; impl crate :: RegisterSpec for OnemcuTpiuLsrSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_lsr::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuLsrSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_lsr::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuLsrSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_LSR to value 0"]
impl crate :: Resettable for OnemcuTpiuLsrSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_AUTHSTATUS (rw) register accessor: Authentication status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_authstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_authstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_authstatus`]
module"]
# [doc (alias = "ONEMCU_TPIU_AUTHSTATUS")]
pub type OnemcuTpiuAuthstatus = crate :: Reg < onemcu_tpiu_authstatus :: OnemcuTpiuAuthstatusSpec > ; # [doc = "Authentication status"]
pub mod onemcu_tpiu_authstatus { # [doc = "Register `ONEMCU_TPIU_AUTHSTATUS` reader"]
pub type R = crate :: R < OnemcuTpiuAuthstatusSpec > ; # [doc = "Register `ONEMCU_TPIU_AUTHSTATUS` writer"]
pub type W = crate :: W < OnemcuTpiuAuthstatusSpec > ; # [doc = "Field `ONEMCU_TPIU_AUTHSTATUS` reader - 31:0\\]
Authentication status"]
pub type OnemcuTpiuAuthstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_AUTHSTATUS` writer - 31:0\\]
Authentication status"]
pub type OnemcuTpiuAuthstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Authentication status"]
# [inline (always)]
pub fn onemcu_tpiu_authstatus (& self) -> OnemcuTpiuAuthstatusR { OnemcuTpiuAuthstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Authentication status"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_authstatus (& mut self) -> OnemcuTpiuAuthstatusW < OnemcuTpiuAuthstatusSpec > { OnemcuTpiuAuthstatusW :: new (self , 0) } } # [doc = "Authentication status\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_authstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_authstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuAuthstatusSpec ; impl crate :: RegisterSpec for OnemcuTpiuAuthstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_authstatus::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuAuthstatusSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_authstatus::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuAuthstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_AUTHSTATUS to value 0"]
impl crate :: Resettable for OnemcuTpiuAuthstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_DEVID (rw) register accessor: Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_devid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_devid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_devid`]
module"]
# [doc (alias = "ONEMCU_TPIU_DEVID")]
pub type OnemcuTpiuDevid = crate :: Reg < onemcu_tpiu_devid :: OnemcuTpiuDevidSpec > ; # [doc = "Device ID"]
pub mod onemcu_tpiu_devid { # [doc = "Register `ONEMCU_TPIU_DEVID` reader"]
pub type R = crate :: R < OnemcuTpiuDevidSpec > ; # [doc = "Register `ONEMCU_TPIU_DEVID` writer"]
pub type W = crate :: W < OnemcuTpiuDevidSpec > ; # [doc = "Field `ONEMCU_TPIU_DEVID` reader - 31:0\\]
Device ID"]
pub type OnemcuTpiuDevidR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_DEVID` writer - 31:0\\]
Device ID"]
pub type OnemcuTpiuDevidW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Device ID"]
# [inline (always)]
pub fn onemcu_tpiu_devid (& self) -> OnemcuTpiuDevidR { OnemcuTpiuDevidR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Device ID"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_devid (& mut self) -> OnemcuTpiuDevidW < OnemcuTpiuDevidSpec > { OnemcuTpiuDevidW :: new (self , 0) } } # [doc = "Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_devid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_devid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuDevidSpec ; impl crate :: RegisterSpec for OnemcuTpiuDevidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_devid::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuDevidSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_devid::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuDevidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_DEVID to value 0"]
impl crate :: Resettable for OnemcuTpiuDevidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_DEVTYPE (rw) register accessor: Device type identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_devtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_devtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_devtype`]
module"]
# [doc (alias = "ONEMCU_TPIU_DEVTYPE")]
pub type OnemcuTpiuDevtype = crate :: Reg < onemcu_tpiu_devtype :: OnemcuTpiuDevtypeSpec > ; # [doc = "Device type identifier"]
pub mod onemcu_tpiu_devtype { # [doc = "Register `ONEMCU_TPIU_DEVTYPE` reader"]
pub type R = crate :: R < OnemcuTpiuDevtypeSpec > ; # [doc = "Register `ONEMCU_TPIU_DEVTYPE` writer"]
pub type W = crate :: W < OnemcuTpiuDevtypeSpec > ; # [doc = "Field `ONEMCU_TPIU_DEVTYPE` reader - 31:0\\]
Device type identifier"]
pub type OnemcuTpiuDevtypeR = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_DEVTYPE` writer - 31:0\\]
Device type identifier"]
pub type OnemcuTpiuDevtypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Device type identifier"]
# [inline (always)]
pub fn onemcu_tpiu_devtype (& self) -> OnemcuTpiuDevtypeR { OnemcuTpiuDevtypeR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Device type identifier"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_devtype (& mut self) -> OnemcuTpiuDevtypeW < OnemcuTpiuDevtypeSpec > { OnemcuTpiuDevtypeW :: new (self , 0) } } # [doc = "Device type identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_devtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_devtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuDevtypeSpec ; impl crate :: RegisterSpec for OnemcuTpiuDevtypeSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_devtype::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuDevtypeSpec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_devtype::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuDevtypeSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_DEVTYPE to value 0"]
impl crate :: Resettable for OnemcuTpiuDevtypeSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR4 (rw) register accessor: Peripheral ID4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr4`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR4")]
pub type OnemcuTpiuPidr4 = crate :: Reg < onemcu_tpiu_pidr4 :: OnemcuTpiuPidr4Spec > ; # [doc = "Peripheral ID4"]
pub mod onemcu_tpiu_pidr4 { # [doc = "Register `ONEMCU_TPIU_PIDR4` reader"]
pub type R = crate :: R < OnemcuTpiuPidr4Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR4` writer"]
pub type W = crate :: W < OnemcuTpiuPidr4Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR4` reader - 31:0\\]
Peripheral ID4"]
pub type OnemcuTpiuPidr4R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR4` writer - 31:0\\]
Peripheral ID4"]
pub type OnemcuTpiuPidr4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID4"]
# [inline (always)]
pub fn onemcu_tpiu_pidr4 (& self) -> OnemcuTpiuPidr4R { OnemcuTpiuPidr4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID4"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr4 (& mut self) -> OnemcuTpiuPidr4W < OnemcuTpiuPidr4Spec > { OnemcuTpiuPidr4W :: new (self , 0) } } # [doc = "Peripheral ID4\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr4Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr4::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr4Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr4::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR4 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR5 (rw) register accessor: Peripheral ID5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr5`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR5")]
pub type OnemcuTpiuPidr5 = crate :: Reg < onemcu_tpiu_pidr5 :: OnemcuTpiuPidr5Spec > ; # [doc = "Peripheral ID5"]
pub mod onemcu_tpiu_pidr5 { # [doc = "Register `ONEMCU_TPIU_PIDR5` reader"]
pub type R = crate :: R < OnemcuTpiuPidr5Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR5` writer"]
pub type W = crate :: W < OnemcuTpiuPidr5Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR5` reader - 31:0\\]
Peripheral ID5"]
pub type OnemcuTpiuPidr5R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR5` writer - 31:0\\]
Peripheral ID5"]
pub type OnemcuTpiuPidr5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID5"]
# [inline (always)]
pub fn onemcu_tpiu_pidr5 (& self) -> OnemcuTpiuPidr5R { OnemcuTpiuPidr5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID5"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr5 (& mut self) -> OnemcuTpiuPidr5W < OnemcuTpiuPidr5Spec > { OnemcuTpiuPidr5W :: new (self , 0) } } # [doc = "Peripheral ID5\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr5Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr5::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr5Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr5::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR5 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR6 (rw) register accessor: Peripheral ID6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr6`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR6")]
pub type OnemcuTpiuPidr6 = crate :: Reg < onemcu_tpiu_pidr6 :: OnemcuTpiuPidr6Spec > ; # [doc = "Peripheral ID6"]
pub mod onemcu_tpiu_pidr6 { # [doc = "Register `ONEMCU_TPIU_PIDR6` reader"]
pub type R = crate :: R < OnemcuTpiuPidr6Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR6` writer"]
pub type W = crate :: W < OnemcuTpiuPidr6Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR6` reader - 31:0\\]
Peripheral ID6"]
pub type OnemcuTpiuPidr6R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR6` writer - 31:0\\]
Peripheral ID6"]
pub type OnemcuTpiuPidr6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID6"]
# [inline (always)]
pub fn onemcu_tpiu_pidr6 (& self) -> OnemcuTpiuPidr6R { OnemcuTpiuPidr6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID6"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr6 (& mut self) -> OnemcuTpiuPidr6W < OnemcuTpiuPidr6Spec > { OnemcuTpiuPidr6W :: new (self , 0) } } # [doc = "Peripheral ID6\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr6Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr6::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr6Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr6::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR6 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR7 (rw) register accessor: Peripheral ID7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr7`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR7")]
pub type OnemcuTpiuPidr7 = crate :: Reg < onemcu_tpiu_pidr7 :: OnemcuTpiuPidr7Spec > ; # [doc = "Peripheral ID7"]
pub mod onemcu_tpiu_pidr7 { # [doc = "Register `ONEMCU_TPIU_PIDR7` reader"]
pub type R = crate :: R < OnemcuTpiuPidr7Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR7` writer"]
pub type W = crate :: W < OnemcuTpiuPidr7Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR7` reader - 31:0\\]
Peripheral ID7"]
pub type OnemcuTpiuPidr7R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR7` writer - 31:0\\]
Peripheral ID7"]
pub type OnemcuTpiuPidr7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID7"]
# [inline (always)]
pub fn onemcu_tpiu_pidr7 (& self) -> OnemcuTpiuPidr7R { OnemcuTpiuPidr7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID7"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr7 (& mut self) -> OnemcuTpiuPidr7W < OnemcuTpiuPidr7Spec > { OnemcuTpiuPidr7W :: new (self , 0) } } # [doc = "Peripheral ID7\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr7Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr7::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr7Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr7::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR7 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR0 (rw) register accessor: Peripheral ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr0`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR0")]
pub type OnemcuTpiuPidr0 = crate :: Reg < onemcu_tpiu_pidr0 :: OnemcuTpiuPidr0Spec > ; # [doc = "Peripheral ID0"]
pub mod onemcu_tpiu_pidr0 { # [doc = "Register `ONEMCU_TPIU_PIDR0` reader"]
pub type R = crate :: R < OnemcuTpiuPidr0Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR0` writer"]
pub type W = crate :: W < OnemcuTpiuPidr0Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR0` reader - 31:0\\]
Peripheral ID0"]
pub type OnemcuTpiuPidr0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR0` writer - 31:0\\]
Peripheral ID0"]
pub type OnemcuTpiuPidr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID0"]
# [inline (always)]
pub fn onemcu_tpiu_pidr0 (& self) -> OnemcuTpiuPidr0R { OnemcuTpiuPidr0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID0"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr0 (& mut self) -> OnemcuTpiuPidr0W < OnemcuTpiuPidr0Spec > { OnemcuTpiuPidr0W :: new (self , 0) } } # [doc = "Peripheral ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr0Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr0::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr0::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR0 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR1 (rw) register accessor: Peripheral ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr1`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR1")]
pub type OnemcuTpiuPidr1 = crate :: Reg < onemcu_tpiu_pidr1 :: OnemcuTpiuPidr1Spec > ; # [doc = "Peripheral ID1"]
pub mod onemcu_tpiu_pidr1 { # [doc = "Register `ONEMCU_TPIU_PIDR1` reader"]
pub type R = crate :: R < OnemcuTpiuPidr1Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR1` writer"]
pub type W = crate :: W < OnemcuTpiuPidr1Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR1` reader - 31:0\\]
Peripheral ID1"]
pub type OnemcuTpiuPidr1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR1` writer - 31:0\\]
Peripheral ID1"]
pub type OnemcuTpiuPidr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID1"]
# [inline (always)]
pub fn onemcu_tpiu_pidr1 (& self) -> OnemcuTpiuPidr1R { OnemcuTpiuPidr1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID1"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr1 (& mut self) -> OnemcuTpiuPidr1W < OnemcuTpiuPidr1Spec > { OnemcuTpiuPidr1W :: new (self , 0) } } # [doc = "Peripheral ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr1Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr1::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr1::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR1 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR2 (rw) register accessor: Peripheral ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr2`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR2")]
pub type OnemcuTpiuPidr2 = crate :: Reg < onemcu_tpiu_pidr2 :: OnemcuTpiuPidr2Spec > ; # [doc = "Peripheral ID2"]
pub mod onemcu_tpiu_pidr2 { # [doc = "Register `ONEMCU_TPIU_PIDR2` reader"]
pub type R = crate :: R < OnemcuTpiuPidr2Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR2` writer"]
pub type W = crate :: W < OnemcuTpiuPidr2Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR2` reader - 31:0\\]
Peripheral ID2"]
pub type OnemcuTpiuPidr2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR2` writer - 31:0\\]
Peripheral ID2"]
pub type OnemcuTpiuPidr2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID2"]
# [inline (always)]
pub fn onemcu_tpiu_pidr2 (& self) -> OnemcuTpiuPidr2R { OnemcuTpiuPidr2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID2"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr2 (& mut self) -> OnemcuTpiuPidr2W < OnemcuTpiuPidr2Spec > { OnemcuTpiuPidr2W :: new (self , 0) } } # [doc = "Peripheral ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr2Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr2::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr2::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR2 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_PIDR3 (rw) register accessor: Peripheral ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_pidr3`]
module"]
# [doc (alias = "ONEMCU_TPIU_PIDR3")]
pub type OnemcuTpiuPidr3 = crate :: Reg < onemcu_tpiu_pidr3 :: OnemcuTpiuPidr3Spec > ; # [doc = "Peripheral ID3"]
pub mod onemcu_tpiu_pidr3 { # [doc = "Register `ONEMCU_TPIU_PIDR3` reader"]
pub type R = crate :: R < OnemcuTpiuPidr3Spec > ; # [doc = "Register `ONEMCU_TPIU_PIDR3` writer"]
pub type W = crate :: W < OnemcuTpiuPidr3Spec > ; # [doc = "Field `ONEMCU_TPIU_PIDR3` reader - 31:0\\]
Peripheral ID3"]
pub type OnemcuTpiuPidr3R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_PIDR3` writer - 31:0\\]
Peripheral ID3"]
pub type OnemcuTpiuPidr3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID3"]
# [inline (always)]
pub fn onemcu_tpiu_pidr3 (& self) -> OnemcuTpiuPidr3R { OnemcuTpiuPidr3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Peripheral ID3"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_pidr3 (& mut self) -> OnemcuTpiuPidr3W < OnemcuTpiuPidr3Spec > { OnemcuTpiuPidr3W :: new (self , 0) } } # [doc = "Peripheral ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_pidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_pidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuPidr3Spec ; impl crate :: RegisterSpec for OnemcuTpiuPidr3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_pidr3::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuPidr3Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_pidr3::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuPidr3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_PIDR3 to value 0"]
impl crate :: Resettable for OnemcuTpiuPidr3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CIDR0 (rw) register accessor: Component ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_cidr0`]
module"]
# [doc (alias = "ONEMCU_TPIU_CIDR0")]
pub type OnemcuTpiuCidr0 = crate :: Reg < onemcu_tpiu_cidr0 :: OnemcuTpiuCidr0Spec > ; # [doc = "Component ID0"]
pub mod onemcu_tpiu_cidr0 { # [doc = "Register `ONEMCU_TPIU_CIDR0` reader"]
pub type R = crate :: R < OnemcuTpiuCidr0Spec > ; # [doc = "Register `ONEMCU_TPIU_CIDR0` writer"]
pub type W = crate :: W < OnemcuTpiuCidr0Spec > ; # [doc = "Field `ONEMCU_TPIU_CIDR0` reader - 31:0\\]
Component ID0"]
pub type OnemcuTpiuCidr0R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CIDR0` writer - 31:0\\]
Component ID0"]
pub type OnemcuTpiuCidr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Component ID0"]
# [inline (always)]
pub fn onemcu_tpiu_cidr0 (& self) -> OnemcuTpiuCidr0R { OnemcuTpiuCidr0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Component ID0"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_cidr0 (& mut self) -> OnemcuTpiuCidr0W < OnemcuTpiuCidr0Spec > { OnemcuTpiuCidr0W :: new (self , 0) } } # [doc = "Component ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuCidr0Spec ; impl crate :: RegisterSpec for OnemcuTpiuCidr0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_cidr0::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuCidr0Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_cidr0::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuCidr0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CIDR0 to value 0"]
impl crate :: Resettable for OnemcuTpiuCidr0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CIDR1 (rw) register accessor: Component ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_cidr1`]
module"]
# [doc (alias = "ONEMCU_TPIU_CIDR1")]
pub type OnemcuTpiuCidr1 = crate :: Reg < onemcu_tpiu_cidr1 :: OnemcuTpiuCidr1Spec > ; # [doc = "Component ID1"]
pub mod onemcu_tpiu_cidr1 { # [doc = "Register `ONEMCU_TPIU_CIDR1` reader"]
pub type R = crate :: R < OnemcuTpiuCidr1Spec > ; # [doc = "Register `ONEMCU_TPIU_CIDR1` writer"]
pub type W = crate :: W < OnemcuTpiuCidr1Spec > ; # [doc = "Field `ONEMCU_TPIU_CIDR1` reader - 31:0\\]
Component ID1"]
pub type OnemcuTpiuCidr1R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CIDR1` writer - 31:0\\]
Component ID1"]
pub type OnemcuTpiuCidr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Component ID1"]
# [inline (always)]
pub fn onemcu_tpiu_cidr1 (& self) -> OnemcuTpiuCidr1R { OnemcuTpiuCidr1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Component ID1"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_cidr1 (& mut self) -> OnemcuTpiuCidr1W < OnemcuTpiuCidr1Spec > { OnemcuTpiuCidr1W :: new (self , 0) } } # [doc = "Component ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuCidr1Spec ; impl crate :: RegisterSpec for OnemcuTpiuCidr1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_cidr1::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuCidr1Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_cidr1::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuCidr1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CIDR1 to value 0"]
impl crate :: Resettable for OnemcuTpiuCidr1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CIDR2 (rw) register accessor: Component ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_cidr2`]
module"]
# [doc (alias = "ONEMCU_TPIU_CIDR2")]
pub type OnemcuTpiuCidr2 = crate :: Reg < onemcu_tpiu_cidr2 :: OnemcuTpiuCidr2Spec > ; # [doc = "Component ID2"]
pub mod onemcu_tpiu_cidr2 { # [doc = "Register `ONEMCU_TPIU_CIDR2` reader"]
pub type R = crate :: R < OnemcuTpiuCidr2Spec > ; # [doc = "Register `ONEMCU_TPIU_CIDR2` writer"]
pub type W = crate :: W < OnemcuTpiuCidr2Spec > ; # [doc = "Field `ONEMCU_TPIU_CIDR2` reader - 31:0\\]
Component ID2"]
pub type OnemcuTpiuCidr2R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CIDR2` writer - 31:0\\]
Component ID2"]
pub type OnemcuTpiuCidr2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Component ID2"]
# [inline (always)]
pub fn onemcu_tpiu_cidr2 (& self) -> OnemcuTpiuCidr2R { OnemcuTpiuCidr2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Component ID2"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_cidr2 (& mut self) -> OnemcuTpiuCidr2W < OnemcuTpiuCidr2Spec > { OnemcuTpiuCidr2W :: new (self , 0) } } # [doc = "Component ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuCidr2Spec ; impl crate :: RegisterSpec for OnemcuTpiuCidr2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_cidr2::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuCidr2Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_cidr2::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuCidr2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CIDR2 to value 0"]
impl crate :: Resettable for OnemcuTpiuCidr2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "ONEMCU_TPIU_CIDR3 (rw) register accessor: Component ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@onemcu_tpiu_cidr3`]
module"]
# [doc (alias = "ONEMCU_TPIU_CIDR3")]
pub type OnemcuTpiuCidr3 = crate :: Reg < onemcu_tpiu_cidr3 :: OnemcuTpiuCidr3Spec > ; # [doc = "Component ID3"]
pub mod onemcu_tpiu_cidr3 { # [doc = "Register `ONEMCU_TPIU_CIDR3` reader"]
pub type R = crate :: R < OnemcuTpiuCidr3Spec > ; # [doc = "Register `ONEMCU_TPIU_CIDR3` writer"]
pub type W = crate :: W < OnemcuTpiuCidr3Spec > ; # [doc = "Field `ONEMCU_TPIU_CIDR3` reader - 31:0\\]
Component ID3"]
pub type OnemcuTpiuCidr3R = crate :: FieldReader < u32 > ; # [doc = "Field `ONEMCU_TPIU_CIDR3` writer - 31:0\\]
Component ID3"]
pub type OnemcuTpiuCidr3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Component ID3"]
# [inline (always)]
pub fn onemcu_tpiu_cidr3 (& self) -> OnemcuTpiuCidr3R { OnemcuTpiuCidr3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Component ID3"]
# [inline (always)]
# [must_use]
pub fn onemcu_tpiu_cidr3 (& mut self) -> OnemcuTpiuCidr3W < OnemcuTpiuCidr3Spec > { OnemcuTpiuCidr3W :: new (self , 0) } } # [doc = "Component ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`onemcu_tpiu_cidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`onemcu_tpiu_cidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OnemcuTpiuCidr3Spec ; impl crate :: RegisterSpec for OnemcuTpiuCidr3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`onemcu_tpiu_cidr3::R`](R) reader structure"]
impl crate :: Readable for OnemcuTpiuCidr3Spec { } # [doc = "`write(|w| ..)` method takes [`onemcu_tpiu_cidr3::W`](W) writer structure"]
impl crate :: Writable for OnemcuTpiuCidr3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ONEMCU_TPIU_CIDR3 to value 0"]
impl crate :: Resettable for OnemcuTpiuCidr3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_CONTROL (rw) register accessor: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_control`]
module"]
# [doc (alias = "APP_CM4_CTI_CONTROL")]
pub type AppCm4CtiControl = crate :: Reg < app_cm4_cti_control :: AppCm4CtiControlSpec > ; # [doc = "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html"]
pub mod app_cm4_cti_control { # [doc = "Register `APP_CM4_CTI_CONTROL` reader"]
pub type R = crate :: R < AppCm4CtiControlSpec > ; # [doc = "Register `APP_CM4_CTI_CONTROL` writer"]
pub type W = crate :: W < AppCm4CtiControlSpec > ; # [doc = "Field `APP_CM4_CTI_CONTROL` reader - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
pub type AppCm4CtiControlR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_CONTROL` writer - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
pub type AppCm4CtiControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
# [inline (always)]
pub fn app_cm4_cti_control (& self) -> AppCm4CtiControlR { AppCm4CtiControlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_control (& mut self) -> AppCm4CtiControlW < AppCm4CtiControlSpec > { AppCm4CtiControlW :: new (self , 0) } } # [doc = "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiControlSpec ; impl crate :: RegisterSpec for AppCm4CtiControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_control::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiControlSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_control::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_CONTROL to value 0"]
impl crate :: Resettable for AppCm4CtiControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INTACK (rw) register accessor: APP_CM4_CTI_INTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_intack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_intack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_intack`]
module"]
# [doc (alias = "APP_CM4_CTI_INTACK")]
pub type AppCm4CtiIntack = crate :: Reg < app_cm4_cti_intack :: AppCm4CtiIntackSpec > ; # [doc = "APP_CM4_CTI_INTACK"]
pub mod app_cm4_cti_intack { # [doc = "Register `APP_CM4_CTI_INTACK` reader"]
pub type R = crate :: R < AppCm4CtiIntackSpec > ; # [doc = "Register `APP_CM4_CTI_INTACK` writer"]
pub type W = crate :: W < AppCm4CtiIntackSpec > ; # [doc = "Field `APP_CM4_CTI_INTACK` reader - "]
pub type AppCm4CtiIntackR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INTACK` writer - "]
pub type AppCm4CtiIntackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_intack (& self) -> AppCm4CtiIntackR { AppCm4CtiIntackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_intack (& mut self) -> AppCm4CtiIntackW < AppCm4CtiIntackSpec > { AppCm4CtiIntackW :: new (self , 0) } } # [doc = "APP_CM4_CTI_INTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_intack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_intack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiIntackSpec ; impl crate :: RegisterSpec for AppCm4CtiIntackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_intack::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiIntackSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_intack::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiIntackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INTACK to value 0"]
impl crate :: Resettable for AppCm4CtiIntackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_APPSET (rw) register accessor: APP_CM4_CTI_APPSET\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_appset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_appset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_appset`]
module"]
# [doc (alias = "APP_CM4_CTI_APPSET")]
pub type AppCm4CtiAppset = crate :: Reg < app_cm4_cti_appset :: AppCm4CtiAppsetSpec > ; # [doc = "APP_CM4_CTI_APPSET"]
pub mod app_cm4_cti_appset { # [doc = "Register `APP_CM4_CTI_APPSET` reader"]
pub type R = crate :: R < AppCm4CtiAppsetSpec > ; # [doc = "Register `APP_CM4_CTI_APPSET` writer"]
pub type W = crate :: W < AppCm4CtiAppsetSpec > ; # [doc = "Field `APP_CM4_CTI_APPSET` reader - "]
pub type AppCm4CtiAppsetR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_APPSET` writer - "]
pub type AppCm4CtiAppsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_appset (& self) -> AppCm4CtiAppsetR { AppCm4CtiAppsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_appset (& mut self) -> AppCm4CtiAppsetW < AppCm4CtiAppsetSpec > { AppCm4CtiAppsetW :: new (self , 0) } } # [doc = "APP_CM4_CTI_APPSET\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_appset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_appset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiAppsetSpec ; impl crate :: RegisterSpec for AppCm4CtiAppsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_appset::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiAppsetSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_appset::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiAppsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_APPSET to value 0"]
impl crate :: Resettable for AppCm4CtiAppsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_APPCLEAR (rw) register accessor: APP_CM4_CTI_APPCLEAR\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_appclear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_appclear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_appclear`]
module"]
# [doc (alias = "APP_CM4_CTI_APPCLEAR")]
pub type AppCm4CtiAppclear = crate :: Reg < app_cm4_cti_appclear :: AppCm4CtiAppclearSpec > ; # [doc = "APP_CM4_CTI_APPCLEAR"]
pub mod app_cm4_cti_appclear { # [doc = "Register `APP_CM4_CTI_APPCLEAR` reader"]
pub type R = crate :: R < AppCm4CtiAppclearSpec > ; # [doc = "Register `APP_CM4_CTI_APPCLEAR` writer"]
pub type W = crate :: W < AppCm4CtiAppclearSpec > ; # [doc = "Field `APP_CM4_CTI_APPCLEAR` reader - "]
pub type AppCm4CtiAppclearR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_APPCLEAR` writer - "]
pub type AppCm4CtiAppclearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_appclear (& self) -> AppCm4CtiAppclearR { AppCm4CtiAppclearR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_appclear (& mut self) -> AppCm4CtiAppclearW < AppCm4CtiAppclearSpec > { AppCm4CtiAppclearW :: new (self , 0) } } # [doc = "APP_CM4_CTI_APPCLEAR\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_appclear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_appclear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiAppclearSpec ; impl crate :: RegisterSpec for AppCm4CtiAppclearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_appclear::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiAppclearSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_appclear::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiAppclearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_APPCLEAR to value 0"]
impl crate :: Resettable for AppCm4CtiAppclearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_APPPULSE (rw) register accessor: APP_CM4_CTI_APPPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_apppulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_apppulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_apppulse`]
module"]
# [doc (alias = "APP_CM4_CTI_APPPULSE")]
pub type AppCm4CtiApppulse = crate :: Reg < app_cm4_cti_apppulse :: AppCm4CtiApppulseSpec > ; # [doc = "APP_CM4_CTI_APPPULSE"]
pub mod app_cm4_cti_apppulse { # [doc = "Register `APP_CM4_CTI_APPPULSE` reader"]
pub type R = crate :: R < AppCm4CtiApppulseSpec > ; # [doc = "Register `APP_CM4_CTI_APPPULSE` writer"]
pub type W = crate :: W < AppCm4CtiApppulseSpec > ; # [doc = "Field `APP_CM4_CTI_APPPULSE` reader - "]
pub type AppCm4CtiApppulseR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_APPPULSE` writer - "]
pub type AppCm4CtiApppulseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_apppulse (& self) -> AppCm4CtiApppulseR { AppCm4CtiApppulseR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_apppulse (& mut self) -> AppCm4CtiApppulseW < AppCm4CtiApppulseSpec > { AppCm4CtiApppulseW :: new (self , 0) } } # [doc = "APP_CM4_CTI_APPPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_apppulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_apppulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiApppulseSpec ; impl crate :: RegisterSpec for AppCm4CtiApppulseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_apppulse::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiApppulseSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_apppulse::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiApppulseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_APPPULSE to value 0"]
impl crate :: Resettable for AppCm4CtiApppulseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN0 (rw) register accessor: APP_CM4_CTI_INEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen0`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN0")]
pub type AppCm4CtiInen0 = crate :: Reg < app_cm4_cti_inen0 :: AppCm4CtiInen0Spec > ; # [doc = "APP_CM4_CTI_INEN0"]
pub mod app_cm4_cti_inen0 { # [doc = "Register `APP_CM4_CTI_INEN0` reader"]
pub type R = crate :: R < AppCm4CtiInen0Spec > ; # [doc = "Register `APP_CM4_CTI_INEN0` writer"]
pub type W = crate :: W < AppCm4CtiInen0Spec > ; # [doc = "Field `APP_CM4_CTI_INEN0` reader - "]
pub type AppCm4CtiInen0R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN0` writer - "]
pub type AppCm4CtiInen0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen0 (& self) -> AppCm4CtiInen0R { AppCm4CtiInen0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen0 (& mut self) -> AppCm4CtiInen0W < AppCm4CtiInen0Spec > { AppCm4CtiInen0W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen0Spec ; impl crate :: RegisterSpec for AppCm4CtiInen0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen0::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen0Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen0::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN0 to value 0"]
impl crate :: Resettable for AppCm4CtiInen0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN1 (rw) register accessor: APP_CM4_CTI_INEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen1`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN1")]
pub type AppCm4CtiInen1 = crate :: Reg < app_cm4_cti_inen1 :: AppCm4CtiInen1Spec > ; # [doc = "APP_CM4_CTI_INEN1"]
pub mod app_cm4_cti_inen1 { # [doc = "Register `APP_CM4_CTI_INEN1` reader"]
pub type R = crate :: R < AppCm4CtiInen1Spec > ; # [doc = "Register `APP_CM4_CTI_INEN1` writer"]
pub type W = crate :: W < AppCm4CtiInen1Spec > ; # [doc = "Field `APP_CM4_CTI_INEN1` reader - "]
pub type AppCm4CtiInen1R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN1` writer - "]
pub type AppCm4CtiInen1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen1 (& self) -> AppCm4CtiInen1R { AppCm4CtiInen1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen1 (& mut self) -> AppCm4CtiInen1W < AppCm4CtiInen1Spec > { AppCm4CtiInen1W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen1Spec ; impl crate :: RegisterSpec for AppCm4CtiInen1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen1::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen1Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen1::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN1 to value 0"]
impl crate :: Resettable for AppCm4CtiInen1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN2 (rw) register accessor: APP_CM4_CTI_INEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen2`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN2")]
pub type AppCm4CtiInen2 = crate :: Reg < app_cm4_cti_inen2 :: AppCm4CtiInen2Spec > ; # [doc = "APP_CM4_CTI_INEN2"]
pub mod app_cm4_cti_inen2 { # [doc = "Register `APP_CM4_CTI_INEN2` reader"]
pub type R = crate :: R < AppCm4CtiInen2Spec > ; # [doc = "Register `APP_CM4_CTI_INEN2` writer"]
pub type W = crate :: W < AppCm4CtiInen2Spec > ; # [doc = "Field `APP_CM4_CTI_INEN2` reader - "]
pub type AppCm4CtiInen2R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN2` writer - "]
pub type AppCm4CtiInen2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen2 (& self) -> AppCm4CtiInen2R { AppCm4CtiInen2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen2 (& mut self) -> AppCm4CtiInen2W < AppCm4CtiInen2Spec > { AppCm4CtiInen2W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen2Spec ; impl crate :: RegisterSpec for AppCm4CtiInen2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen2::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen2Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen2::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN2 to value 0"]
impl crate :: Resettable for AppCm4CtiInen2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN3 (rw) register accessor: APP_CM4_CTI_INEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen3`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN3")]
pub type AppCm4CtiInen3 = crate :: Reg < app_cm4_cti_inen3 :: AppCm4CtiInen3Spec > ; # [doc = "APP_CM4_CTI_INEN3"]
pub mod app_cm4_cti_inen3 { # [doc = "Register `APP_CM4_CTI_INEN3` reader"]
pub type R = crate :: R < AppCm4CtiInen3Spec > ; # [doc = "Register `APP_CM4_CTI_INEN3` writer"]
pub type W = crate :: W < AppCm4CtiInen3Spec > ; # [doc = "Field `APP_CM4_CTI_INEN3` reader - "]
pub type AppCm4CtiInen3R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN3` writer - "]
pub type AppCm4CtiInen3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen3 (& self) -> AppCm4CtiInen3R { AppCm4CtiInen3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen3 (& mut self) -> AppCm4CtiInen3W < AppCm4CtiInen3Spec > { AppCm4CtiInen3W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen3Spec ; impl crate :: RegisterSpec for AppCm4CtiInen3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen3::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen3Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen3::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN3 to value 0"]
impl crate :: Resettable for AppCm4CtiInen3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN4 (rw) register accessor: APP_CM4_CTI_INEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen4`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN4")]
pub type AppCm4CtiInen4 = crate :: Reg < app_cm4_cti_inen4 :: AppCm4CtiInen4Spec > ; # [doc = "APP_CM4_CTI_INEN4"]
pub mod app_cm4_cti_inen4 { # [doc = "Register `APP_CM4_CTI_INEN4` reader"]
pub type R = crate :: R < AppCm4CtiInen4Spec > ; # [doc = "Register `APP_CM4_CTI_INEN4` writer"]
pub type W = crate :: W < AppCm4CtiInen4Spec > ; # [doc = "Field `APP_CM4_CTI_INEN4` reader - "]
pub type AppCm4CtiInen4R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN4` writer - "]
pub type AppCm4CtiInen4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen4 (& self) -> AppCm4CtiInen4R { AppCm4CtiInen4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen4 (& mut self) -> AppCm4CtiInen4W < AppCm4CtiInen4Spec > { AppCm4CtiInen4W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen4Spec ; impl crate :: RegisterSpec for AppCm4CtiInen4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen4::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen4Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen4::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN4 to value 0"]
impl crate :: Resettable for AppCm4CtiInen4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN5 (rw) register accessor: APP_CM4_CTI_INEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen5`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN5")]
pub type AppCm4CtiInen5 = crate :: Reg < app_cm4_cti_inen5 :: AppCm4CtiInen5Spec > ; # [doc = "APP_CM4_CTI_INEN5"]
pub mod app_cm4_cti_inen5 { # [doc = "Register `APP_CM4_CTI_INEN5` reader"]
pub type R = crate :: R < AppCm4CtiInen5Spec > ; # [doc = "Register `APP_CM4_CTI_INEN5` writer"]
pub type W = crate :: W < AppCm4CtiInen5Spec > ; # [doc = "Field `APP_CM4_CTI_INEN5` reader - "]
pub type AppCm4CtiInen5R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN5` writer - "]
pub type AppCm4CtiInen5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen5 (& self) -> AppCm4CtiInen5R { AppCm4CtiInen5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen5 (& mut self) -> AppCm4CtiInen5W < AppCm4CtiInen5Spec > { AppCm4CtiInen5W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen5Spec ; impl crate :: RegisterSpec for AppCm4CtiInen5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen5::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen5Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen5::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN5 to value 0"]
impl crate :: Resettable for AppCm4CtiInen5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN6 (rw) register accessor: APP_CM4_CTI_INEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen6`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN6")]
pub type AppCm4CtiInen6 = crate :: Reg < app_cm4_cti_inen6 :: AppCm4CtiInen6Spec > ; # [doc = "APP_CM4_CTI_INEN6"]
pub mod app_cm4_cti_inen6 { # [doc = "Register `APP_CM4_CTI_INEN6` reader"]
pub type R = crate :: R < AppCm4CtiInen6Spec > ; # [doc = "Register `APP_CM4_CTI_INEN6` writer"]
pub type W = crate :: W < AppCm4CtiInen6Spec > ; # [doc = "Field `APP_CM4_CTI_INEN6` reader - "]
pub type AppCm4CtiInen6R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN6` writer - "]
pub type AppCm4CtiInen6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen6 (& self) -> AppCm4CtiInen6R { AppCm4CtiInen6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen6 (& mut self) -> AppCm4CtiInen6W < AppCm4CtiInen6Spec > { AppCm4CtiInen6W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen6Spec ; impl crate :: RegisterSpec for AppCm4CtiInen6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen6::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen6Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen6::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN6 to value 0"]
impl crate :: Resettable for AppCm4CtiInen6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_INEN7 (rw) register accessor: APP_CM4_CTI_INEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_inen7`]
module"]
# [doc (alias = "APP_CM4_CTI_INEN7")]
pub type AppCm4CtiInen7 = crate :: Reg < app_cm4_cti_inen7 :: AppCm4CtiInen7Spec > ; # [doc = "APP_CM4_CTI_INEN7"]
pub mod app_cm4_cti_inen7 { # [doc = "Register `APP_CM4_CTI_INEN7` reader"]
pub type R = crate :: R < AppCm4CtiInen7Spec > ; # [doc = "Register `APP_CM4_CTI_INEN7` writer"]
pub type W = crate :: W < AppCm4CtiInen7Spec > ; # [doc = "Field `APP_CM4_CTI_INEN7` reader - "]
pub type AppCm4CtiInen7R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_INEN7` writer - "]
pub type AppCm4CtiInen7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_inen7 (& self) -> AppCm4CtiInen7R { AppCm4CtiInen7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_inen7 (& mut self) -> AppCm4CtiInen7W < AppCm4CtiInen7Spec > { AppCm4CtiInen7W :: new (self , 0) } } # [doc = "APP_CM4_CTI_INEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_inen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_inen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiInen7Spec ; impl crate :: RegisterSpec for AppCm4CtiInen7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_inen7::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiInen7Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_inen7::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiInen7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_INEN7 to value 0"]
impl crate :: Resettable for AppCm4CtiInen7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN0 (rw) register accessor: APP_CM4_CTI_OUTEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen0`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN0")]
pub type AppCm4CtiOuten0 = crate :: Reg < app_cm4_cti_outen0 :: AppCm4CtiOuten0Spec > ; # [doc = "APP_CM4_CTI_OUTEN0"]
pub mod app_cm4_cti_outen0 { # [doc = "Register `APP_CM4_CTI_OUTEN0` reader"]
pub type R = crate :: R < AppCm4CtiOuten0Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN0` writer"]
pub type W = crate :: W < AppCm4CtiOuten0Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN0` reader - "]
pub type AppCm4CtiOuten0R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN0` writer - "]
pub type AppCm4CtiOuten0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen0 (& self) -> AppCm4CtiOuten0R { AppCm4CtiOuten0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen0 (& mut self) -> AppCm4CtiOuten0W < AppCm4CtiOuten0Spec > { AppCm4CtiOuten0W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten0Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen0::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten0Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen0::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN0 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN1 (rw) register accessor: APP_CM4_CTI_OUTEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen1`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN1")]
pub type AppCm4CtiOuten1 = crate :: Reg < app_cm4_cti_outen1 :: AppCm4CtiOuten1Spec > ; # [doc = "APP_CM4_CTI_OUTEN1"]
pub mod app_cm4_cti_outen1 { # [doc = "Register `APP_CM4_CTI_OUTEN1` reader"]
pub type R = crate :: R < AppCm4CtiOuten1Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN1` writer"]
pub type W = crate :: W < AppCm4CtiOuten1Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN1` reader - "]
pub type AppCm4CtiOuten1R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN1` writer - "]
pub type AppCm4CtiOuten1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen1 (& self) -> AppCm4CtiOuten1R { AppCm4CtiOuten1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen1 (& mut self) -> AppCm4CtiOuten1W < AppCm4CtiOuten1Spec > { AppCm4CtiOuten1W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten1Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen1::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten1Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen1::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN1 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN2 (rw) register accessor: APP_CM4_CTI_OUTEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen2`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN2")]
pub type AppCm4CtiOuten2 = crate :: Reg < app_cm4_cti_outen2 :: AppCm4CtiOuten2Spec > ; # [doc = "APP_CM4_CTI_OUTEN2"]
pub mod app_cm4_cti_outen2 { # [doc = "Register `APP_CM4_CTI_OUTEN2` reader"]
pub type R = crate :: R < AppCm4CtiOuten2Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN2` writer"]
pub type W = crate :: W < AppCm4CtiOuten2Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN2` reader - "]
pub type AppCm4CtiOuten2R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN2` writer - "]
pub type AppCm4CtiOuten2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen2 (& self) -> AppCm4CtiOuten2R { AppCm4CtiOuten2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen2 (& mut self) -> AppCm4CtiOuten2W < AppCm4CtiOuten2Spec > { AppCm4CtiOuten2W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten2Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen2::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten2Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen2::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN2 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN3 (rw) register accessor: APP_CM4_CTI_OUTEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen3`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN3")]
pub type AppCm4CtiOuten3 = crate :: Reg < app_cm4_cti_outen3 :: AppCm4CtiOuten3Spec > ; # [doc = "APP_CM4_CTI_OUTEN3"]
pub mod app_cm4_cti_outen3 { # [doc = "Register `APP_CM4_CTI_OUTEN3` reader"]
pub type R = crate :: R < AppCm4CtiOuten3Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN3` writer"]
pub type W = crate :: W < AppCm4CtiOuten3Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN3` reader - "]
pub type AppCm4CtiOuten3R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN3` writer - "]
pub type AppCm4CtiOuten3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen3 (& self) -> AppCm4CtiOuten3R { AppCm4CtiOuten3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen3 (& mut self) -> AppCm4CtiOuten3W < AppCm4CtiOuten3Spec > { AppCm4CtiOuten3W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten3Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen3::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten3Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen3::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN3 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN4 (rw) register accessor: APP_CM4_CTI_OUTEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen4`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN4")]
pub type AppCm4CtiOuten4 = crate :: Reg < app_cm4_cti_outen4 :: AppCm4CtiOuten4Spec > ; # [doc = "APP_CM4_CTI_OUTEN4"]
pub mod app_cm4_cti_outen4 { # [doc = "Register `APP_CM4_CTI_OUTEN4` reader"]
pub type R = crate :: R < AppCm4CtiOuten4Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN4` writer"]
pub type W = crate :: W < AppCm4CtiOuten4Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN4` reader - "]
pub type AppCm4CtiOuten4R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN4` writer - "]
pub type AppCm4CtiOuten4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen4 (& self) -> AppCm4CtiOuten4R { AppCm4CtiOuten4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen4 (& mut self) -> AppCm4CtiOuten4W < AppCm4CtiOuten4Spec > { AppCm4CtiOuten4W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten4Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen4::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten4Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen4::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN4 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN5 (rw) register accessor: APP_CM4_CTI_OUTEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen5`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN5")]
pub type AppCm4CtiOuten5 = crate :: Reg < app_cm4_cti_outen5 :: AppCm4CtiOuten5Spec > ; # [doc = "APP_CM4_CTI_OUTEN5"]
pub mod app_cm4_cti_outen5 { # [doc = "Register `APP_CM4_CTI_OUTEN5` reader"]
pub type R = crate :: R < AppCm4CtiOuten5Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN5` writer"]
pub type W = crate :: W < AppCm4CtiOuten5Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN5` reader - "]
pub type AppCm4CtiOuten5R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN5` writer - "]
pub type AppCm4CtiOuten5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen5 (& self) -> AppCm4CtiOuten5R { AppCm4CtiOuten5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen5 (& mut self) -> AppCm4CtiOuten5W < AppCm4CtiOuten5Spec > { AppCm4CtiOuten5W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten5Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen5::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten5Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen5::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN5 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN6 (rw) register accessor: APP_CM4_CTI_OUTEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen6`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN6")]
pub type AppCm4CtiOuten6 = crate :: Reg < app_cm4_cti_outen6 :: AppCm4CtiOuten6Spec > ; # [doc = "APP_CM4_CTI_OUTEN6"]
pub mod app_cm4_cti_outen6 { # [doc = "Register `APP_CM4_CTI_OUTEN6` reader"]
pub type R = crate :: R < AppCm4CtiOuten6Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN6` writer"]
pub type W = crate :: W < AppCm4CtiOuten6Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN6` reader - "]
pub type AppCm4CtiOuten6R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN6` writer - "]
pub type AppCm4CtiOuten6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen6 (& self) -> AppCm4CtiOuten6R { AppCm4CtiOuten6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen6 (& mut self) -> AppCm4CtiOuten6W < AppCm4CtiOuten6Spec > { AppCm4CtiOuten6W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten6Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen6::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten6Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen6::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN6 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_OUTEN7 (rw) register accessor: APP_CM4_CTI_OUTEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_outen7`]
module"]
# [doc (alias = "APP_CM4_CTI_OUTEN7")]
pub type AppCm4CtiOuten7 = crate :: Reg < app_cm4_cti_outen7 :: AppCm4CtiOuten7Spec > ; # [doc = "APP_CM4_CTI_OUTEN7"]
pub mod app_cm4_cti_outen7 { # [doc = "Register `APP_CM4_CTI_OUTEN7` reader"]
pub type R = crate :: R < AppCm4CtiOuten7Spec > ; # [doc = "Register `APP_CM4_CTI_OUTEN7` writer"]
pub type W = crate :: W < AppCm4CtiOuten7Spec > ; # [doc = "Field `APP_CM4_CTI_OUTEN7` reader - "]
pub type AppCm4CtiOuten7R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_OUTEN7` writer - "]
pub type AppCm4CtiOuten7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_outen7 (& self) -> AppCm4CtiOuten7R { AppCm4CtiOuten7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_outen7 (& mut self) -> AppCm4CtiOuten7W < AppCm4CtiOuten7Spec > { AppCm4CtiOuten7W :: new (self , 0) } } # [doc = "APP_CM4_CTI_OUTEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_outen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_outen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiOuten7Spec ; impl crate :: RegisterSpec for AppCm4CtiOuten7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_outen7::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiOuten7Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_outen7::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiOuten7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_OUTEN7 to value 0"]
impl crate :: Resettable for AppCm4CtiOuten7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_TRIGINSTATUS (rw) register accessor: APP_CM4_CTI_TRIGINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_triginstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_triginstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_triginstatus`]
module"]
# [doc (alias = "APP_CM4_CTI_TRIGINSTATUS")]
pub type AppCm4CtiTriginstatus = crate :: Reg < app_cm4_cti_triginstatus :: AppCm4CtiTriginstatusSpec > ; # [doc = "APP_CM4_CTI_TRIGINSTATUS"]
pub mod app_cm4_cti_triginstatus { # [doc = "Register `APP_CM4_CTI_TRIGINSTATUS` reader"]
pub type R = crate :: R < AppCm4CtiTriginstatusSpec > ; # [doc = "Register `APP_CM4_CTI_TRIGINSTATUS` writer"]
pub type W = crate :: W < AppCm4CtiTriginstatusSpec > ; # [doc = "Field `APP_CM4_CTI_TRIGINSTATUS` reader - "]
pub type AppCm4CtiTriginstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_TRIGINSTATUS` writer - "]
pub type AppCm4CtiTriginstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_triginstatus (& self) -> AppCm4CtiTriginstatusR { AppCm4CtiTriginstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_triginstatus (& mut self) -> AppCm4CtiTriginstatusW < AppCm4CtiTriginstatusSpec > { AppCm4CtiTriginstatusW :: new (self , 0) } } # [doc = "APP_CM4_CTI_TRIGINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_triginstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_triginstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiTriginstatusSpec ; impl crate :: RegisterSpec for AppCm4CtiTriginstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_triginstatus::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiTriginstatusSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_triginstatus::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiTriginstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_TRIGINSTATUS to value 0"]
impl crate :: Resettable for AppCm4CtiTriginstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_TRIGOUTSTATUS (rw) register accessor: APP_CM4_CTI_TRIGOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_trigoutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_trigoutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_trigoutstatus`]
module"]
# [doc (alias = "APP_CM4_CTI_TRIGOUTSTATUS")]
pub type AppCm4CtiTrigoutstatus = crate :: Reg < app_cm4_cti_trigoutstatus :: AppCm4CtiTrigoutstatusSpec > ; # [doc = "APP_CM4_CTI_TRIGOUTSTATUS"]
pub mod app_cm4_cti_trigoutstatus { # [doc = "Register `APP_CM4_CTI_TRIGOUTSTATUS` reader"]
pub type R = crate :: R < AppCm4CtiTrigoutstatusSpec > ; # [doc = "Register `APP_CM4_CTI_TRIGOUTSTATUS` writer"]
pub type W = crate :: W < AppCm4CtiTrigoutstatusSpec > ; # [doc = "Field `APP_CM4_CTI_TRIGOUTSTATUS` reader - "]
pub type AppCm4CtiTrigoutstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_TRIGOUTSTATUS` writer - "]
pub type AppCm4CtiTrigoutstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_trigoutstatus (& self) -> AppCm4CtiTrigoutstatusR { AppCm4CtiTrigoutstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_trigoutstatus (& mut self) -> AppCm4CtiTrigoutstatusW < AppCm4CtiTrigoutstatusSpec > { AppCm4CtiTrigoutstatusW :: new (self , 0) } } # [doc = "APP_CM4_CTI_TRIGOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_trigoutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_trigoutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiTrigoutstatusSpec ; impl crate :: RegisterSpec for AppCm4CtiTrigoutstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_trigoutstatus::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiTrigoutstatusSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_trigoutstatus::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiTrigoutstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_TRIGOUTSTATUS to value 0"]
impl crate :: Resettable for AppCm4CtiTrigoutstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_CHINSTATUS (rw) register accessor: APP_CM4_CTI_CHINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_chinstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_chinstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_chinstatus`]
module"]
# [doc (alias = "APP_CM4_CTI_CHINSTATUS")]
pub type AppCm4CtiChinstatus = crate :: Reg < app_cm4_cti_chinstatus :: AppCm4CtiChinstatusSpec > ; # [doc = "APP_CM4_CTI_CHINSTATUS"]
pub mod app_cm4_cti_chinstatus { # [doc = "Register `APP_CM4_CTI_CHINSTATUS` reader"]
pub type R = crate :: R < AppCm4CtiChinstatusSpec > ; # [doc = "Register `APP_CM4_CTI_CHINSTATUS` writer"]
pub type W = crate :: W < AppCm4CtiChinstatusSpec > ; # [doc = "Field `APP_CM4_CTI_CHINSTATUS` reader - "]
pub type AppCm4CtiChinstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_CHINSTATUS` writer - "]
pub type AppCm4CtiChinstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_chinstatus (& self) -> AppCm4CtiChinstatusR { AppCm4CtiChinstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_chinstatus (& mut self) -> AppCm4CtiChinstatusW < AppCm4CtiChinstatusSpec > { AppCm4CtiChinstatusW :: new (self , 0) } } # [doc = "APP_CM4_CTI_CHINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_chinstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_chinstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiChinstatusSpec ; impl crate :: RegisterSpec for AppCm4CtiChinstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_chinstatus::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiChinstatusSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_chinstatus::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiChinstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_CHINSTATUS to value 0"]
impl crate :: Resettable for AppCm4CtiChinstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_CHOUTSTATUS (rw) register accessor: APP_CM4_CTI_CHOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_choutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_choutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_choutstatus`]
module"]
# [doc (alias = "APP_CM4_CTI_CHOUTSTATUS")]
pub type AppCm4CtiChoutstatus = crate :: Reg < app_cm4_cti_choutstatus :: AppCm4CtiChoutstatusSpec > ; # [doc = "APP_CM4_CTI_CHOUTSTATUS"]
pub mod app_cm4_cti_choutstatus { # [doc = "Register `APP_CM4_CTI_CHOUTSTATUS` reader"]
pub type R = crate :: R < AppCm4CtiChoutstatusSpec > ; # [doc = "Register `APP_CM4_CTI_CHOUTSTATUS` writer"]
pub type W = crate :: W < AppCm4CtiChoutstatusSpec > ; # [doc = "Field `APP_CM4_CTI_CHOUTSTATUS` reader - "]
pub type AppCm4CtiChoutstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_CHOUTSTATUS` writer - "]
pub type AppCm4CtiChoutstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_choutstatus (& self) -> AppCm4CtiChoutstatusR { AppCm4CtiChoutstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_choutstatus (& mut self) -> AppCm4CtiChoutstatusW < AppCm4CtiChoutstatusSpec > { AppCm4CtiChoutstatusW :: new (self , 0) } } # [doc = "APP_CM4_CTI_CHOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_choutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_choutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiChoutstatusSpec ; impl crate :: RegisterSpec for AppCm4CtiChoutstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_choutstatus::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiChoutstatusSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_choutstatus::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiChoutstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_CHOUTSTATUS to value 0"]
impl crate :: Resettable for AppCm4CtiChoutstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_GATE (rw) register accessor: APP_CM4_CTI_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_gate`]
module"]
# [doc (alias = "APP_CM4_CTI_GATE")]
pub type AppCm4CtiGate = crate :: Reg < app_cm4_cti_gate :: AppCm4CtiGateSpec > ; # [doc = "APP_CM4_CTI_GATE"]
pub mod app_cm4_cti_gate { # [doc = "Register `APP_CM4_CTI_GATE` reader"]
pub type R = crate :: R < AppCm4CtiGateSpec > ; # [doc = "Register `APP_CM4_CTI_GATE` writer"]
pub type W = crate :: W < AppCm4CtiGateSpec > ; # [doc = "Field `APP_CM4_CTI_GATE` reader - "]
pub type AppCm4CtiGateR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_GATE` writer - "]
pub type AppCm4CtiGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_gate (& self) -> AppCm4CtiGateR { AppCm4CtiGateR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_gate (& mut self) -> AppCm4CtiGateW < AppCm4CtiGateSpec > { AppCm4CtiGateW :: new (self , 0) } } # [doc = "APP_CM4_CTI_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiGateSpec ; impl crate :: RegisterSpec for AppCm4CtiGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_gate::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiGateSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_gate::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_GATE to value 0"]
impl crate :: Resettable for AppCm4CtiGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ASICCTL (rw) register accessor: APP_CM4_CTI_ASICCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_asicctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_asicctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_asicctl`]
module"]
# [doc (alias = "APP_CM4_CTI_ASICCTL")]
pub type AppCm4CtiAsicctl = crate :: Reg < app_cm4_cti_asicctl :: AppCm4CtiAsicctlSpec > ; # [doc = "APP_CM4_CTI_ASICCTL"]
pub mod app_cm4_cti_asicctl { # [doc = "Register `APP_CM4_CTI_ASICCTL` reader"]
pub type R = crate :: R < AppCm4CtiAsicctlSpec > ; # [doc = "Register `APP_CM4_CTI_ASICCTL` writer"]
pub type W = crate :: W < AppCm4CtiAsicctlSpec > ; # [doc = "Field `APP_CM4_CTI_ASICCTL` reader - "]
pub type AppCm4CtiAsicctlR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ASICCTL` writer - "]
pub type AppCm4CtiAsicctlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_asicctl (& self) -> AppCm4CtiAsicctlR { AppCm4CtiAsicctlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_asicctl (& mut self) -> AppCm4CtiAsicctlW < AppCm4CtiAsicctlSpec > { AppCm4CtiAsicctlW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ASICCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_asicctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_asicctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiAsicctlSpec ; impl crate :: RegisterSpec for AppCm4CtiAsicctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_asicctl::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiAsicctlSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_asicctl::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiAsicctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ASICCTL to value 0"]
impl crate :: Resettable for AppCm4CtiAsicctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITCHINACK (rw) register accessor: APP_CM4_CTI_ITCHINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchinack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchinack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_itchinack`]
module"]
# [doc (alias = "APP_CM4_CTI_ITCHINACK")]
pub type AppCm4CtiItchinack = crate :: Reg < app_cm4_cti_itchinack :: AppCm4CtiItchinackSpec > ; # [doc = "APP_CM4_CTI_ITCHINACK"]
pub mod app_cm4_cti_itchinack { # [doc = "Register `APP_CM4_CTI_ITCHINACK` reader"]
pub type R = crate :: R < AppCm4CtiItchinackSpec > ; # [doc = "Register `APP_CM4_CTI_ITCHINACK` writer"]
pub type W = crate :: W < AppCm4CtiItchinackSpec > ; # [doc = "Field `APP_CM4_CTI_ITCHINACK` reader - "]
pub type AppCm4CtiItchinackR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITCHINACK` writer - "]
pub type AppCm4CtiItchinackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_itchinack (& self) -> AppCm4CtiItchinackR { AppCm4CtiItchinackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_itchinack (& mut self) -> AppCm4CtiItchinackW < AppCm4CtiItchinackSpec > { AppCm4CtiItchinackW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITCHINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchinack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchinack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiItchinackSpec ; impl crate :: RegisterSpec for AppCm4CtiItchinackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_itchinack::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiItchinackSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_itchinack::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiItchinackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITCHINACK to value 0"]
impl crate :: Resettable for AppCm4CtiItchinackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITTRIGINACK (rw) register accessor: APP_CM4_CTI_ITTRIGINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittriginack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittriginack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_ittriginack`]
module"]
# [doc (alias = "APP_CM4_CTI_ITTRIGINACK")]
pub type AppCm4CtiIttriginack = crate :: Reg < app_cm4_cti_ittriginack :: AppCm4CtiIttriginackSpec > ; # [doc = "APP_CM4_CTI_ITTRIGINACK"]
pub mod app_cm4_cti_ittriginack { # [doc = "Register `APP_CM4_CTI_ITTRIGINACK` reader"]
pub type R = crate :: R < AppCm4CtiIttriginackSpec > ; # [doc = "Register `APP_CM4_CTI_ITTRIGINACK` writer"]
pub type W = crate :: W < AppCm4CtiIttriginackSpec > ; # [doc = "Field `APP_CM4_CTI_ITTRIGINACK` reader - "]
pub type AppCm4CtiIttriginackR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITTRIGINACK` writer - "]
pub type AppCm4CtiIttriginackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_ittriginack (& self) -> AppCm4CtiIttriginackR { AppCm4CtiIttriginackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_ittriginack (& mut self) -> AppCm4CtiIttriginackW < AppCm4CtiIttriginackSpec > { AppCm4CtiIttriginackW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITTRIGINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittriginack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittriginack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiIttriginackSpec ; impl crate :: RegisterSpec for AppCm4CtiIttriginackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_ittriginack::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiIttriginackSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_ittriginack::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiIttriginackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITTRIGINACK to value 0"]
impl crate :: Resettable for AppCm4CtiIttriginackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITCHOUT (rw) register accessor: APP_CM4_CTI_ITCHOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_itchout`]
module"]
# [doc (alias = "APP_CM4_CTI_ITCHOUT")]
pub type AppCm4CtiItchout = crate :: Reg < app_cm4_cti_itchout :: AppCm4CtiItchoutSpec > ; # [doc = "APP_CM4_CTI_ITCHOUT"]
pub mod app_cm4_cti_itchout { # [doc = "Register `APP_CM4_CTI_ITCHOUT` reader"]
pub type R = crate :: R < AppCm4CtiItchoutSpec > ; # [doc = "Register `APP_CM4_CTI_ITCHOUT` writer"]
pub type W = crate :: W < AppCm4CtiItchoutSpec > ; # [doc = "Field `APP_CM4_CTI_ITCHOUT` reader - "]
pub type AppCm4CtiItchoutR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITCHOUT` writer - "]
pub type AppCm4CtiItchoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_itchout (& self) -> AppCm4CtiItchoutR { AppCm4CtiItchoutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_itchout (& mut self) -> AppCm4CtiItchoutW < AppCm4CtiItchoutSpec > { AppCm4CtiItchoutW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITCHOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiItchoutSpec ; impl crate :: RegisterSpec for AppCm4CtiItchoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_itchout::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiItchoutSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_itchout::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiItchoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITCHOUT to value 0"]
impl crate :: Resettable for AppCm4CtiItchoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITTRIGOUT (rw) register accessor: APP_CM4_CTI_ITTRIGOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittrigout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittrigout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_ittrigout`]
module"]
# [doc (alias = "APP_CM4_CTI_ITTRIGOUT")]
pub type AppCm4CtiIttrigout = crate :: Reg < app_cm4_cti_ittrigout :: AppCm4CtiIttrigoutSpec > ; # [doc = "APP_CM4_CTI_ITTRIGOUT"]
pub mod app_cm4_cti_ittrigout { # [doc = "Register `APP_CM4_CTI_ITTRIGOUT` reader"]
pub type R = crate :: R < AppCm4CtiIttrigoutSpec > ; # [doc = "Register `APP_CM4_CTI_ITTRIGOUT` writer"]
pub type W = crate :: W < AppCm4CtiIttrigoutSpec > ; # [doc = "Field `APP_CM4_CTI_ITTRIGOUT` reader - "]
pub type AppCm4CtiIttrigoutR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITTRIGOUT` writer - "]
pub type AppCm4CtiIttrigoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_ittrigout (& self) -> AppCm4CtiIttrigoutR { AppCm4CtiIttrigoutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_ittrigout (& mut self) -> AppCm4CtiIttrigoutW < AppCm4CtiIttrigoutSpec > { AppCm4CtiIttrigoutW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITTRIGOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittrigout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittrigout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiIttrigoutSpec ; impl crate :: RegisterSpec for AppCm4CtiIttrigoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_ittrigout::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiIttrigoutSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_ittrigout::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiIttrigoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITTRIGOUT to value 0"]
impl crate :: Resettable for AppCm4CtiIttrigoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITCHOUTACK (rw) register accessor: APP_CM4_CTI_ITCHOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchoutack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchoutack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_itchoutack`]
module"]
# [doc (alias = "APP_CM4_CTI_ITCHOUTACK")]
pub type AppCm4CtiItchoutack = crate :: Reg < app_cm4_cti_itchoutack :: AppCm4CtiItchoutackSpec > ; # [doc = "APP_CM4_CTI_ITCHOUTACK"]
pub mod app_cm4_cti_itchoutack { # [doc = "Register `APP_CM4_CTI_ITCHOUTACK` reader"]
pub type R = crate :: R < AppCm4CtiItchoutackSpec > ; # [doc = "Register `APP_CM4_CTI_ITCHOUTACK` writer"]
pub type W = crate :: W < AppCm4CtiItchoutackSpec > ; # [doc = "Field `APP_CM4_CTI_ITCHOUTACK` reader - "]
pub type AppCm4CtiItchoutackR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITCHOUTACK` writer - "]
pub type AppCm4CtiItchoutackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_itchoutack (& self) -> AppCm4CtiItchoutackR { AppCm4CtiItchoutackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_itchoutack (& mut self) -> AppCm4CtiItchoutackW < AppCm4CtiItchoutackSpec > { AppCm4CtiItchoutackW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITCHOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchoutack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchoutack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiItchoutackSpec ; impl crate :: RegisterSpec for AppCm4CtiItchoutackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_itchoutack::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiItchoutackSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_itchoutack::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiItchoutackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITCHOUTACK to value 0"]
impl crate :: Resettable for AppCm4CtiItchoutackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITTRIGOUTACK (rw) register accessor: APP_CM4_CTI_ITTRIGOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittrigoutack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittrigoutack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_ittrigoutack`]
module"]
# [doc (alias = "APP_CM4_CTI_ITTRIGOUTACK")]
pub type AppCm4CtiIttrigoutack = crate :: Reg < app_cm4_cti_ittrigoutack :: AppCm4CtiIttrigoutackSpec > ; # [doc = "APP_CM4_CTI_ITTRIGOUTACK"]
pub mod app_cm4_cti_ittrigoutack { # [doc = "Register `APP_CM4_CTI_ITTRIGOUTACK` reader"]
pub type R = crate :: R < AppCm4CtiIttrigoutackSpec > ; # [doc = "Register `APP_CM4_CTI_ITTRIGOUTACK` writer"]
pub type W = crate :: W < AppCm4CtiIttrigoutackSpec > ; # [doc = "Field `APP_CM4_CTI_ITTRIGOUTACK` reader - "]
pub type AppCm4CtiIttrigoutackR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITTRIGOUTACK` writer - "]
pub type AppCm4CtiIttrigoutackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_ittrigoutack (& self) -> AppCm4CtiIttrigoutackR { AppCm4CtiIttrigoutackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_ittrigoutack (& mut self) -> AppCm4CtiIttrigoutackW < AppCm4CtiIttrigoutackSpec > { AppCm4CtiIttrigoutackW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITTRIGOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittrigoutack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittrigoutack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiIttrigoutackSpec ; impl crate :: RegisterSpec for AppCm4CtiIttrigoutackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_ittrigoutack::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiIttrigoutackSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_ittrigoutack::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiIttrigoutackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITTRIGOUTACK to value 0"]
impl crate :: Resettable for AppCm4CtiIttrigoutackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITCHIN (rw) register accessor: APP_CM4_CTI_ITCHIN\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_itchin`]
module"]
# [doc (alias = "APP_CM4_CTI_ITCHIN")]
pub type AppCm4CtiItchin = crate :: Reg < app_cm4_cti_itchin :: AppCm4CtiItchinSpec > ; # [doc = "APP_CM4_CTI_ITCHIN"]
pub mod app_cm4_cti_itchin { # [doc = "Register `APP_CM4_CTI_ITCHIN` reader"]
pub type R = crate :: R < AppCm4CtiItchinSpec > ; # [doc = "Register `APP_CM4_CTI_ITCHIN` writer"]
pub type W = crate :: W < AppCm4CtiItchinSpec > ; # [doc = "Field `APP_CM4_CTI_ITCHIN` reader - "]
pub type AppCm4CtiItchinR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITCHIN` writer - "]
pub type AppCm4CtiItchinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_itchin (& self) -> AppCm4CtiItchinR { AppCm4CtiItchinR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_itchin (& mut self) -> AppCm4CtiItchinW < AppCm4CtiItchinSpec > { AppCm4CtiItchinW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITCHIN\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itchin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itchin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiItchinSpec ; impl crate :: RegisterSpec for AppCm4CtiItchinSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_itchin::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiItchinSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_itchin::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiItchinSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITCHIN to value 0"]
impl crate :: Resettable for AppCm4CtiItchinSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITTRIGIN (rw) register accessor: APP_CM4_CTI_ITTRIGIN\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittrigin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittrigin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_ittrigin`]
module"]
# [doc (alias = "APP_CM4_CTI_ITTRIGIN")]
pub type AppCm4CtiIttrigin = crate :: Reg < app_cm4_cti_ittrigin :: AppCm4CtiIttriginSpec > ; # [doc = "APP_CM4_CTI_ITTRIGIN"]
pub mod app_cm4_cti_ittrigin { # [doc = "Register `APP_CM4_CTI_ITTRIGIN` reader"]
pub type R = crate :: R < AppCm4CtiIttriginSpec > ; # [doc = "Register `APP_CM4_CTI_ITTRIGIN` writer"]
pub type W = crate :: W < AppCm4CtiIttriginSpec > ; # [doc = "Field `APP_CM4_CTI_ITTRIGIN` reader - "]
pub type AppCm4CtiIttriginR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITTRIGIN` writer - "]
pub type AppCm4CtiIttriginW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_ittrigin (& self) -> AppCm4CtiIttriginR { AppCm4CtiIttriginR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_ittrigin (& mut self) -> AppCm4CtiIttriginW < AppCm4CtiIttriginSpec > { AppCm4CtiIttriginW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITTRIGIN\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_ittrigin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_ittrigin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiIttriginSpec ; impl crate :: RegisterSpec for AppCm4CtiIttriginSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_ittrigin::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiIttriginSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_ittrigin::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiIttriginSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITTRIGIN to value 0"]
impl crate :: Resettable for AppCm4CtiIttriginSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_ITCTRL (rw) register accessor: APP_CM4_CTI_ITCTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_itctrl`]
module"]
# [doc (alias = "APP_CM4_CTI_ITCTRL")]
pub type AppCm4CtiItctrl = crate :: Reg < app_cm4_cti_itctrl :: AppCm4CtiItctrlSpec > ; # [doc = "APP_CM4_CTI_ITCTRL"]
pub mod app_cm4_cti_itctrl { # [doc = "Register `APP_CM4_CTI_ITCTRL` reader"]
pub type R = crate :: R < AppCm4CtiItctrlSpec > ; # [doc = "Register `APP_CM4_CTI_ITCTRL` writer"]
pub type W = crate :: W < AppCm4CtiItctrlSpec > ; # [doc = "Field `APP_CM4_CTI_ITCTRL` reader - "]
pub type AppCm4CtiItctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_ITCTRL` writer - "]
pub type AppCm4CtiItctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_itctrl (& self) -> AppCm4CtiItctrlR { AppCm4CtiItctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_itctrl (& mut self) -> AppCm4CtiItctrlW < AppCm4CtiItctrlSpec > { AppCm4CtiItctrlW :: new (self , 0) } } # [doc = "APP_CM4_CTI_ITCTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_itctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_itctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiItctrlSpec ; impl crate :: RegisterSpec for AppCm4CtiItctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_itctrl::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiItctrlSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_itctrl::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiItctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_ITCTRL to value 0"]
impl crate :: Resettable for AppCm4CtiItctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Claim_Tag_Set (rw) register accessor: APP_CM4_CTI_Claim_Tag_Set\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_claim_tag_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_claim_tag_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_claim_tag_set`]
module"]
# [doc (alias = "APP_CM4_CTI_Claim_Tag_Set")]
pub type AppCm4CtiClaimTagSet = crate :: Reg < app_cm4_cti_claim_tag_set :: AppCm4CtiClaimTagSetSpec > ; # [doc = "APP_CM4_CTI_Claim_Tag_Set"]
pub mod app_cm4_cti_claim_tag_set { # [doc = "Register `APP_CM4_CTI_Claim_Tag_Set` reader"]
pub type R = crate :: R < AppCm4CtiClaimTagSetSpec > ; # [doc = "Register `APP_CM4_CTI_Claim_Tag_Set` writer"]
pub type W = crate :: W < AppCm4CtiClaimTagSetSpec > ; # [doc = "Field `APP_CM4_CTI_Claim_Tag_Set` reader - "]
pub type AppCm4CtiClaimTagSetR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Claim_Tag_Set` writer - "]
pub type AppCm4CtiClaimTagSetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_claim_tag_set (& self) -> AppCm4CtiClaimTagSetR { AppCm4CtiClaimTagSetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_claim_tag_set (& mut self) -> AppCm4CtiClaimTagSetW < AppCm4CtiClaimTagSetSpec > { AppCm4CtiClaimTagSetW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Claim_Tag_Set\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_claim_tag_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_claim_tag_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiClaimTagSetSpec ; impl crate :: RegisterSpec for AppCm4CtiClaimTagSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_claim_tag_set::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiClaimTagSetSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_claim_tag_set::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiClaimTagSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Claim_Tag_Set to value 0"]
impl crate :: Resettable for AppCm4CtiClaimTagSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Claim_Tag_Clear (rw) register accessor: APP_CM4_CTI_Claim_Tag_Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_claim_tag_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_claim_tag_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_claim_tag_clear`]
module"]
# [doc (alias = "APP_CM4_CTI_Claim_Tag_Clear")]
pub type AppCm4CtiClaimTagClear = crate :: Reg < app_cm4_cti_claim_tag_clear :: AppCm4CtiClaimTagClearSpec > ; # [doc = "APP_CM4_CTI_Claim_Tag_Clear"]
pub mod app_cm4_cti_claim_tag_clear { # [doc = "Register `APP_CM4_CTI_Claim_Tag_Clear` reader"]
pub type R = crate :: R < AppCm4CtiClaimTagClearSpec > ; # [doc = "Register `APP_CM4_CTI_Claim_Tag_Clear` writer"]
pub type W = crate :: W < AppCm4CtiClaimTagClearSpec > ; # [doc = "Field `APP_CM4_CTI_Claim_Tag_Clear` reader - "]
pub type AppCm4CtiClaimTagClearR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Claim_Tag_Clear` writer - "]
pub type AppCm4CtiClaimTagClearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_claim_tag_clear (& self) -> AppCm4CtiClaimTagClearR { AppCm4CtiClaimTagClearR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_claim_tag_clear (& mut self) -> AppCm4CtiClaimTagClearW < AppCm4CtiClaimTagClearSpec > { AppCm4CtiClaimTagClearW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Claim_Tag_Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_claim_tag_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_claim_tag_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiClaimTagClearSpec ; impl crate :: RegisterSpec for AppCm4CtiClaimTagClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_claim_tag_clear::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiClaimTagClearSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_claim_tag_clear::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiClaimTagClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Claim_Tag_Clear to value 0"]
impl crate :: Resettable for AppCm4CtiClaimTagClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Lock_Access_Register (rw) register accessor: APP_CM4_CTI_Lock_Access_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_lock_access_register::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_lock_access_register::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_lock_access_register`]
module"]
# [doc (alias = "APP_CM4_CTI_Lock_Access_Register")]
pub type AppCm4CtiLockAccessRegister = crate :: Reg < app_cm4_cti_lock_access_register :: AppCm4CtiLockAccessRegisterSpec > ; # [doc = "APP_CM4_CTI_Lock_Access_Register"]
pub mod app_cm4_cti_lock_access_register { # [doc = "Register `APP_CM4_CTI_Lock_Access_Register` reader"]
pub type R = crate :: R < AppCm4CtiLockAccessRegisterSpec > ; # [doc = "Register `APP_CM4_CTI_Lock_Access_Register` writer"]
pub type W = crate :: W < AppCm4CtiLockAccessRegisterSpec > ; # [doc = "Field `APP_CM4_CTI_Lock_Access_Register` reader - "]
pub type AppCm4CtiLockAccessRegisterR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Lock_Access_Register` writer - "]
pub type AppCm4CtiLockAccessRegisterW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_lock_access_register (& self) -> AppCm4CtiLockAccessRegisterR { AppCm4CtiLockAccessRegisterR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_lock_access_register (& mut self) -> AppCm4CtiLockAccessRegisterW < AppCm4CtiLockAccessRegisterSpec > { AppCm4CtiLockAccessRegisterW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Lock_Access_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_lock_access_register::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_lock_access_register::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiLockAccessRegisterSpec ; impl crate :: RegisterSpec for AppCm4CtiLockAccessRegisterSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_lock_access_register::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiLockAccessRegisterSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_lock_access_register::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiLockAccessRegisterSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Lock_Access_Register to value 0"]
impl crate :: Resettable for AppCm4CtiLockAccessRegisterSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Lock_Status_Register (rw) register accessor: APP_CM4_CTI_Lock_Status_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_lock_status_register::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_lock_status_register::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_lock_status_register`]
module"]
# [doc (alias = "APP_CM4_CTI_Lock_Status_Register")]
pub type AppCm4CtiLockStatusRegister = crate :: Reg < app_cm4_cti_lock_status_register :: AppCm4CtiLockStatusRegisterSpec > ; # [doc = "APP_CM4_CTI_Lock_Status_Register"]
pub mod app_cm4_cti_lock_status_register { # [doc = "Register `APP_CM4_CTI_Lock_Status_Register` reader"]
pub type R = crate :: R < AppCm4CtiLockStatusRegisterSpec > ; # [doc = "Register `APP_CM4_CTI_Lock_Status_Register` writer"]
pub type W = crate :: W < AppCm4CtiLockStatusRegisterSpec > ; # [doc = "Field `APP_CM4_CTI_Lock_Status_Register` reader - "]
pub type AppCm4CtiLockStatusRegisterR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Lock_Status_Register` writer - "]
pub type AppCm4CtiLockStatusRegisterW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_lock_status_register (& self) -> AppCm4CtiLockStatusRegisterR { AppCm4CtiLockStatusRegisterR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_lock_status_register (& mut self) -> AppCm4CtiLockStatusRegisterW < AppCm4CtiLockStatusRegisterSpec > { AppCm4CtiLockStatusRegisterW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Lock_Status_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_lock_status_register::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_lock_status_register::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiLockStatusRegisterSpec ; impl crate :: RegisterSpec for AppCm4CtiLockStatusRegisterSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_lock_status_register::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiLockStatusRegisterSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_lock_status_register::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiLockStatusRegisterSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Lock_Status_Register to value 0"]
impl crate :: Resettable for AppCm4CtiLockStatusRegisterSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Authentication_Status (rw) register accessor: APP_CM4_CTI_Authentication_Status\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_authentication_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_authentication_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_authentication_status`]
module"]
# [doc (alias = "APP_CM4_CTI_Authentication_Status")]
pub type AppCm4CtiAuthenticationStatus = crate :: Reg < app_cm4_cti_authentication_status :: AppCm4CtiAuthenticationStatusSpec > ; # [doc = "APP_CM4_CTI_Authentication_Status"]
pub mod app_cm4_cti_authentication_status { # [doc = "Register `APP_CM4_CTI_Authentication_Status` reader"]
pub type R = crate :: R < AppCm4CtiAuthenticationStatusSpec > ; # [doc = "Register `APP_CM4_CTI_Authentication_Status` writer"]
pub type W = crate :: W < AppCm4CtiAuthenticationStatusSpec > ; # [doc = "Field `APP_CM4_CTI_Authentication_Status` reader - "]
pub type AppCm4CtiAuthenticationStatusR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Authentication_Status` writer - "]
pub type AppCm4CtiAuthenticationStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_authentication_status (& self) -> AppCm4CtiAuthenticationStatusR { AppCm4CtiAuthenticationStatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_authentication_status (& mut self) -> AppCm4CtiAuthenticationStatusW < AppCm4CtiAuthenticationStatusSpec > { AppCm4CtiAuthenticationStatusW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Authentication_Status\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_authentication_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_authentication_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiAuthenticationStatusSpec ; impl crate :: RegisterSpec for AppCm4CtiAuthenticationStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_authentication_status::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiAuthenticationStatusSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_authentication_status::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiAuthenticationStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Authentication_Status to value 0"]
impl crate :: Resettable for AppCm4CtiAuthenticationStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Device_ID (rw) register accessor: APP_CM4_CTI_Device_ID\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_device_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_device_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_device_id`]
module"]
# [doc (alias = "APP_CM4_CTI_Device_ID")]
pub type AppCm4CtiDeviceId = crate :: Reg < app_cm4_cti_device_id :: AppCm4CtiDeviceIdSpec > ; # [doc = "APP_CM4_CTI_Device_ID"]
pub mod app_cm4_cti_device_id { # [doc = "Register `APP_CM4_CTI_Device_ID` reader"]
pub type R = crate :: R < AppCm4CtiDeviceIdSpec > ; # [doc = "Register `APP_CM4_CTI_Device_ID` writer"]
pub type W = crate :: W < AppCm4CtiDeviceIdSpec > ; # [doc = "Field `APP_CM4_CTI_Device_ID` reader - "]
pub type AppCm4CtiDeviceIdR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Device_ID` writer - "]
pub type AppCm4CtiDeviceIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_device_id (& self) -> AppCm4CtiDeviceIdR { AppCm4CtiDeviceIdR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_device_id (& mut self) -> AppCm4CtiDeviceIdW < AppCm4CtiDeviceIdSpec > { AppCm4CtiDeviceIdW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Device_ID\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_device_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_device_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiDeviceIdSpec ; impl crate :: RegisterSpec for AppCm4CtiDeviceIdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_device_id::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiDeviceIdSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_device_id::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiDeviceIdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Device_ID to value 0"]
impl crate :: Resettable for AppCm4CtiDeviceIdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Device_Type_Identifier (rw) register accessor: APP_CM4_CTI_Device_Type_Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_device_type_identifier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_device_type_identifier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_device_type_identifier`]
module"]
# [doc (alias = "APP_CM4_CTI_Device_Type_Identifier")]
pub type AppCm4CtiDeviceTypeIdentifier = crate :: Reg < app_cm4_cti_device_type_identifier :: AppCm4CtiDeviceTypeIdentifierSpec > ; # [doc = "APP_CM4_CTI_Device_Type_Identifier"]
pub mod app_cm4_cti_device_type_identifier { # [doc = "Register `APP_CM4_CTI_Device_Type_Identifier` reader"]
pub type R = crate :: R < AppCm4CtiDeviceTypeIdentifierSpec > ; # [doc = "Register `APP_CM4_CTI_Device_Type_Identifier` writer"]
pub type W = crate :: W < AppCm4CtiDeviceTypeIdentifierSpec > ; # [doc = "Field `APP_CM4_CTI_Device_Type_Identifier` reader - "]
pub type AppCm4CtiDeviceTypeIdentifierR = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Device_Type_Identifier` writer - "]
pub type AppCm4CtiDeviceTypeIdentifierW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_device_type_identifier (& self) -> AppCm4CtiDeviceTypeIdentifierR { AppCm4CtiDeviceTypeIdentifierR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_device_type_identifier (& mut self) -> AppCm4CtiDeviceTypeIdentifierW < AppCm4CtiDeviceTypeIdentifierSpec > { AppCm4CtiDeviceTypeIdentifierW :: new (self , 0) } } # [doc = "APP_CM4_CTI_Device_Type_Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_device_type_identifier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_device_type_identifier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiDeviceTypeIdentifierSpec ; impl crate :: RegisterSpec for AppCm4CtiDeviceTypeIdentifierSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_device_type_identifier::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiDeviceTypeIdentifierSpec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_device_type_identifier::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiDeviceTypeIdentifierSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Device_Type_Identifier to value 0"]
impl crate :: Resettable for AppCm4CtiDeviceTypeIdentifierSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID4 (rw) register accessor: APP_CM4_CTI_PeripheralID4\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id4`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID4")]
pub type AppCm4CtiPeripheralId4 = crate :: Reg < app_cm4_cti_peripheral_id4 :: AppCm4CtiPeripheralId4Spec > ; # [doc = "APP_CM4_CTI_PeripheralID4"]
pub mod app_cm4_cti_peripheral_id4 { # [doc = "Register `APP_CM4_CTI_PeripheralID4` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId4Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID4` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId4Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID4` reader - "]
pub type AppCm4CtiPeripheralId4R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID4` writer - "]
pub type AppCm4CtiPeripheralId4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id4 (& self) -> AppCm4CtiPeripheralId4R { AppCm4CtiPeripheralId4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id4 (& mut self) -> AppCm4CtiPeripheralId4W < AppCm4CtiPeripheralId4Spec > { AppCm4CtiPeripheralId4W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID4\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId4Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id4::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId4Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id4::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID4 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID5 (rw) register accessor: APP_CM4_CTI_PeripheralID5\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id5`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID5")]
pub type AppCm4CtiPeripheralId5 = crate :: Reg < app_cm4_cti_peripheral_id5 :: AppCm4CtiPeripheralId5Spec > ; # [doc = "APP_CM4_CTI_PeripheralID5"]
pub mod app_cm4_cti_peripheral_id5 { # [doc = "Register `APP_CM4_CTI_PeripheralID5` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId5Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID5` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId5Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID5` reader - "]
pub type AppCm4CtiPeripheralId5R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID5` writer - "]
pub type AppCm4CtiPeripheralId5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id5 (& self) -> AppCm4CtiPeripheralId5R { AppCm4CtiPeripheralId5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id5 (& mut self) -> AppCm4CtiPeripheralId5W < AppCm4CtiPeripheralId5Spec > { AppCm4CtiPeripheralId5W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID5\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId5Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id5::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId5Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id5::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID5 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID6 (rw) register accessor: APP_CM4_CTI_PeripheralID6\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id6`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID6")]
pub type AppCm4CtiPeripheralId6 = crate :: Reg < app_cm4_cti_peripheral_id6 :: AppCm4CtiPeripheralId6Spec > ; # [doc = "APP_CM4_CTI_PeripheralID6"]
pub mod app_cm4_cti_peripheral_id6 { # [doc = "Register `APP_CM4_CTI_PeripheralID6` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId6Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID6` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId6Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID6` reader - "]
pub type AppCm4CtiPeripheralId6R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID6` writer - "]
pub type AppCm4CtiPeripheralId6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id6 (& self) -> AppCm4CtiPeripheralId6R { AppCm4CtiPeripheralId6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id6 (& mut self) -> AppCm4CtiPeripheralId6W < AppCm4CtiPeripheralId6Spec > { AppCm4CtiPeripheralId6W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID6\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId6Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id6::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId6Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id6::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID6 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID7 (rw) register accessor: APP_CM4_CTI_PeripheralID7\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id7`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID7")]
pub type AppCm4CtiPeripheralId7 = crate :: Reg < app_cm4_cti_peripheral_id7 :: AppCm4CtiPeripheralId7Spec > ; # [doc = "APP_CM4_CTI_PeripheralID7"]
pub mod app_cm4_cti_peripheral_id7 { # [doc = "Register `APP_CM4_CTI_PeripheralID7` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId7Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID7` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId7Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID7` reader - "]
pub type AppCm4CtiPeripheralId7R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID7` writer - "]
pub type AppCm4CtiPeripheralId7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id7 (& self) -> AppCm4CtiPeripheralId7R { AppCm4CtiPeripheralId7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id7 (& mut self) -> AppCm4CtiPeripheralId7W < AppCm4CtiPeripheralId7Spec > { AppCm4CtiPeripheralId7W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID7\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId7Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id7::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId7Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id7::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID7 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID0 (rw) register accessor: APP_CM4_CTI_PeripheralID0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id0`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID0")]
pub type AppCm4CtiPeripheralId0 = crate :: Reg < app_cm4_cti_peripheral_id0 :: AppCm4CtiPeripheralId0Spec > ; # [doc = "APP_CM4_CTI_PeripheralID0"]
pub mod app_cm4_cti_peripheral_id0 { # [doc = "Register `APP_CM4_CTI_PeripheralID0` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId0Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID0` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId0Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID0` reader - "]
pub type AppCm4CtiPeripheralId0R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID0` writer - "]
pub type AppCm4CtiPeripheralId0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id0 (& self) -> AppCm4CtiPeripheralId0R { AppCm4CtiPeripheralId0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id0 (& mut self) -> AppCm4CtiPeripheralId0W < AppCm4CtiPeripheralId0Spec > { AppCm4CtiPeripheralId0W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId0Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id0::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId0Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id0::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID0 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID1 (rw) register accessor: APP_CM4_CTI_PeripheralID1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id1`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID1")]
pub type AppCm4CtiPeripheralId1 = crate :: Reg < app_cm4_cti_peripheral_id1 :: AppCm4CtiPeripheralId1Spec > ; # [doc = "APP_CM4_CTI_PeripheralID1"]
pub mod app_cm4_cti_peripheral_id1 { # [doc = "Register `APP_CM4_CTI_PeripheralID1` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId1Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID1` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId1Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID1` reader - "]
pub type AppCm4CtiPeripheralId1R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID1` writer - "]
pub type AppCm4CtiPeripheralId1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id1 (& self) -> AppCm4CtiPeripheralId1R { AppCm4CtiPeripheralId1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id1 (& mut self) -> AppCm4CtiPeripheralId1W < AppCm4CtiPeripheralId1Spec > { AppCm4CtiPeripheralId1W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId1Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id1::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId1Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id1::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID1 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID2 (rw) register accessor: APP_CM4_CTI_PeripheralID2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id2`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID2")]
pub type AppCm4CtiPeripheralId2 = crate :: Reg < app_cm4_cti_peripheral_id2 :: AppCm4CtiPeripheralId2Spec > ; # [doc = "APP_CM4_CTI_PeripheralID2"]
pub mod app_cm4_cti_peripheral_id2 { # [doc = "Register `APP_CM4_CTI_PeripheralID2` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId2Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID2` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId2Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID2` reader - "]
pub type AppCm4CtiPeripheralId2R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID2` writer - "]
pub type AppCm4CtiPeripheralId2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id2 (& self) -> AppCm4CtiPeripheralId2R { AppCm4CtiPeripheralId2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id2 (& mut self) -> AppCm4CtiPeripheralId2W < AppCm4CtiPeripheralId2Spec > { AppCm4CtiPeripheralId2W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId2Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id2::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId2Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id2::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID2 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_PeripheralID3 (rw) register accessor: APP_CM4_CTI_PeripheralID3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_peripheral_id3`]
module"]
# [doc (alias = "APP_CM4_CTI_PeripheralID3")]
pub type AppCm4CtiPeripheralId3 = crate :: Reg < app_cm4_cti_peripheral_id3 :: AppCm4CtiPeripheralId3Spec > ; # [doc = "APP_CM4_CTI_PeripheralID3"]
pub mod app_cm4_cti_peripheral_id3 { # [doc = "Register `APP_CM4_CTI_PeripheralID3` reader"]
pub type R = crate :: R < AppCm4CtiPeripheralId3Spec > ; # [doc = "Register `APP_CM4_CTI_PeripheralID3` writer"]
pub type W = crate :: W < AppCm4CtiPeripheralId3Spec > ; # [doc = "Field `APP_CM4_CTI_PeripheralID3` reader - "]
pub type AppCm4CtiPeripheralId3R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_PeripheralID3` writer - "]
pub type AppCm4CtiPeripheralId3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_peripheral_id3 (& self) -> AppCm4CtiPeripheralId3R { AppCm4CtiPeripheralId3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_peripheral_id3 (& mut self) -> AppCm4CtiPeripheralId3W < AppCm4CtiPeripheralId3Spec > { AppCm4CtiPeripheralId3W :: new (self , 0) } } # [doc = "APP_CM4_CTI_PeripheralID3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_peripheral_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_peripheral_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiPeripheralId3Spec ; impl crate :: RegisterSpec for AppCm4CtiPeripheralId3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_peripheral_id3::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiPeripheralId3Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_peripheral_id3::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiPeripheralId3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_PeripheralID3 to value 0"]
impl crate :: Resettable for AppCm4CtiPeripheralId3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Component_ID0 (rw) register accessor: APP_CM4_CTI_Component_ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_component_id0`]
module"]
# [doc (alias = "APP_CM4_CTI_Component_ID0")]
pub type AppCm4CtiComponentId0 = crate :: Reg < app_cm4_cti_component_id0 :: AppCm4CtiComponentId0Spec > ; # [doc = "APP_CM4_CTI_Component_ID0"]
pub mod app_cm4_cti_component_id0 { # [doc = "Register `APP_CM4_CTI_Component_ID0` reader"]
pub type R = crate :: R < AppCm4CtiComponentId0Spec > ; # [doc = "Register `APP_CM4_CTI_Component_ID0` writer"]
pub type W = crate :: W < AppCm4CtiComponentId0Spec > ; # [doc = "Field `APP_CM4_CTI_Component_ID0` reader - "]
pub type AppCm4CtiComponentId0R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Component_ID0` writer - "]
pub type AppCm4CtiComponentId0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_component_id0 (& self) -> AppCm4CtiComponentId0R { AppCm4CtiComponentId0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_component_id0 (& mut self) -> AppCm4CtiComponentId0W < AppCm4CtiComponentId0Spec > { AppCm4CtiComponentId0W :: new (self , 0) } } # [doc = "APP_CM4_CTI_Component_ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiComponentId0Spec ; impl crate :: RegisterSpec for AppCm4CtiComponentId0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_component_id0::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiComponentId0Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_component_id0::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiComponentId0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Component_ID0 to value 0"]
impl crate :: Resettable for AppCm4CtiComponentId0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Component_ID1 (rw) register accessor: APP_CM4_CTI_Component_ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_component_id1`]
module"]
# [doc (alias = "APP_CM4_CTI_Component_ID1")]
pub type AppCm4CtiComponentId1 = crate :: Reg < app_cm4_cti_component_id1 :: AppCm4CtiComponentId1Spec > ; # [doc = "APP_CM4_CTI_Component_ID1"]
pub mod app_cm4_cti_component_id1 { # [doc = "Register `APP_CM4_CTI_Component_ID1` reader"]
pub type R = crate :: R < AppCm4CtiComponentId1Spec > ; # [doc = "Register `APP_CM4_CTI_Component_ID1` writer"]
pub type W = crate :: W < AppCm4CtiComponentId1Spec > ; # [doc = "Field `APP_CM4_CTI_Component_ID1` reader - "]
pub type AppCm4CtiComponentId1R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Component_ID1` writer - "]
pub type AppCm4CtiComponentId1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_component_id1 (& self) -> AppCm4CtiComponentId1R { AppCm4CtiComponentId1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_component_id1 (& mut self) -> AppCm4CtiComponentId1W < AppCm4CtiComponentId1Spec > { AppCm4CtiComponentId1W :: new (self , 0) } } # [doc = "APP_CM4_CTI_Component_ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiComponentId1Spec ; impl crate :: RegisterSpec for AppCm4CtiComponentId1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_component_id1::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiComponentId1Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_component_id1::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiComponentId1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Component_ID1 to value 0"]
impl crate :: Resettable for AppCm4CtiComponentId1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Component_ID2 (rw) register accessor: APP_CM4_CTI_Component_ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_component_id2`]
module"]
# [doc (alias = "APP_CM4_CTI_Component_ID2")]
pub type AppCm4CtiComponentId2 = crate :: Reg < app_cm4_cti_component_id2 :: AppCm4CtiComponentId2Spec > ; # [doc = "APP_CM4_CTI_Component_ID2"]
pub mod app_cm4_cti_component_id2 { # [doc = "Register `APP_CM4_CTI_Component_ID2` reader"]
pub type R = crate :: R < AppCm4CtiComponentId2Spec > ; # [doc = "Register `APP_CM4_CTI_Component_ID2` writer"]
pub type W = crate :: W < AppCm4CtiComponentId2Spec > ; # [doc = "Field `APP_CM4_CTI_Component_ID2` reader - "]
pub type AppCm4CtiComponentId2R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Component_ID2` writer - "]
pub type AppCm4CtiComponentId2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_component_id2 (& self) -> AppCm4CtiComponentId2R { AppCm4CtiComponentId2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_component_id2 (& mut self) -> AppCm4CtiComponentId2W < AppCm4CtiComponentId2Spec > { AppCm4CtiComponentId2W :: new (self , 0) } } # [doc = "APP_CM4_CTI_Component_ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiComponentId2Spec ; impl crate :: RegisterSpec for AppCm4CtiComponentId2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_component_id2::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiComponentId2Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_component_id2::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiComponentId2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Component_ID2 to value 0"]
impl crate :: Resettable for AppCm4CtiComponentId2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "APP_CM4_CTI_Component_ID3 (rw) register accessor: APP_CM4_CTI_Component_ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_cm4_cti_component_id3`]
module"]
# [doc (alias = "APP_CM4_CTI_Component_ID3")]
pub type AppCm4CtiComponentId3 = crate :: Reg < app_cm4_cti_component_id3 :: AppCm4CtiComponentId3Spec > ; # [doc = "APP_CM4_CTI_Component_ID3"]
pub mod app_cm4_cti_component_id3 { # [doc = "Register `APP_CM4_CTI_Component_ID3` reader"]
pub type R = crate :: R < AppCm4CtiComponentId3Spec > ; # [doc = "Register `APP_CM4_CTI_Component_ID3` writer"]
pub type W = crate :: W < AppCm4CtiComponentId3Spec > ; # [doc = "Field `APP_CM4_CTI_Component_ID3` reader - "]
pub type AppCm4CtiComponentId3R = crate :: FieldReader < u32 > ; # [doc = "Field `APP_CM4_CTI_Component_ID3` writer - "]
pub type AppCm4CtiComponentId3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn app_cm4_cti_component_id3 (& self) -> AppCm4CtiComponentId3R { AppCm4CtiComponentId3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn app_cm4_cti_component_id3 (& mut self) -> AppCm4CtiComponentId3W < AppCm4CtiComponentId3Spec > { AppCm4CtiComponentId3W :: new (self , 0) } } # [doc = "APP_CM4_CTI_Component_ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cm4_cti_component_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cm4_cti_component_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AppCm4CtiComponentId3Spec ; impl crate :: RegisterSpec for AppCm4CtiComponentId3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`app_cm4_cti_component_id3::R`](R) reader structure"]
impl crate :: Readable for AppCm4CtiComponentId3Spec { } # [doc = "`write(|w| ..)` method takes [`app_cm4_cti_component_id3::W`](W) writer structure"]
impl crate :: Writable for AppCm4CtiComponentId3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APP_CM4_CTI_Component_ID3 to value 0"]
impl crate :: Resettable for AppCm4CtiComponentId3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_CONTROL (rw) register accessor: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_control`]
module"]
# [doc (alias = "FEC_CM3_CTI_CONTROL")]
pub type FecCm3CtiControl = crate :: Reg < fec_cm3_cti_control :: FecCm3CtiControlSpec > ; # [doc = "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html"]
pub mod fec_cm3_cti_control { # [doc = "Register `FEC_CM3_CTI_CONTROL` reader"]
pub type R = crate :: R < FecCm3CtiControlSpec > ; # [doc = "Register `FEC_CM3_CTI_CONTROL` writer"]
pub type W = crate :: W < FecCm3CtiControlSpec > ; # [doc = "Field `FEC_CM3_CTI_CONTROL` reader - "]
pub type FecCm3CtiControlR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_CONTROL` writer - "]
pub type FecCm3CtiControlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_control (& self) -> FecCm3CtiControlR { FecCm3CtiControlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_control (& mut self) -> FecCm3CtiControlW < FecCm3CtiControlSpec > { FecCm3CtiControlW :: new (self , 0) } } # [doc = "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiControlSpec ; impl crate :: RegisterSpec for FecCm3CtiControlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_control::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiControlSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_control::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiControlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_CONTROL to value 0"]
impl crate :: Resettable for FecCm3CtiControlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INTACK (rw) register accessor: FEC_CM3_CTI_INTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_intack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_intack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_intack`]
module"]
# [doc (alias = "FEC_CM3_CTI_INTACK")]
pub type FecCm3CtiIntack = crate :: Reg < fec_cm3_cti_intack :: FecCm3CtiIntackSpec > ; # [doc = "FEC_CM3_CTI_INTACK"]
pub mod fec_cm3_cti_intack { # [doc = "Register `FEC_CM3_CTI_INTACK` reader"]
pub type R = crate :: R < FecCm3CtiIntackSpec > ; # [doc = "Register `FEC_CM3_CTI_INTACK` writer"]
pub type W = crate :: W < FecCm3CtiIntackSpec > ; # [doc = "Field `FEC_CM3_CTI_INTACK` reader - "]
pub type FecCm3CtiIntackR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INTACK` writer - "]
pub type FecCm3CtiIntackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_intack (& self) -> FecCm3CtiIntackR { FecCm3CtiIntackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_intack (& mut self) -> FecCm3CtiIntackW < FecCm3CtiIntackSpec > { FecCm3CtiIntackW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_intack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_intack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiIntackSpec ; impl crate :: RegisterSpec for FecCm3CtiIntackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_intack::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiIntackSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_intack::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiIntackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INTACK to value 0"]
impl crate :: Resettable for FecCm3CtiIntackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_APPSET (rw) register accessor: FEC_CM3_CTI_APPSET\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_appset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_appset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_appset`]
module"]
# [doc (alias = "FEC_CM3_CTI_APPSET")]
pub type FecCm3CtiAppset = crate :: Reg < fec_cm3_cti_appset :: FecCm3CtiAppsetSpec > ; # [doc = "FEC_CM3_CTI_APPSET"]
pub mod fec_cm3_cti_appset { # [doc = "Register `FEC_CM3_CTI_APPSET` reader"]
pub type R = crate :: R < FecCm3CtiAppsetSpec > ; # [doc = "Register `FEC_CM3_CTI_APPSET` writer"]
pub type W = crate :: W < FecCm3CtiAppsetSpec > ; # [doc = "Field `FEC_CM3_CTI_APPSET` reader - "]
pub type FecCm3CtiAppsetR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_APPSET` writer - "]
pub type FecCm3CtiAppsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_appset (& self) -> FecCm3CtiAppsetR { FecCm3CtiAppsetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_appset (& mut self) -> FecCm3CtiAppsetW < FecCm3CtiAppsetSpec > { FecCm3CtiAppsetW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_APPSET\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_appset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_appset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiAppsetSpec ; impl crate :: RegisterSpec for FecCm3CtiAppsetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_appset::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiAppsetSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_appset::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiAppsetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_APPSET to value 0"]
impl crate :: Resettable for FecCm3CtiAppsetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_APPCLEAR (rw) register accessor: FEC_CM3_CTI_APPCLEAR\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_appclear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_appclear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_appclear`]
module"]
# [doc (alias = "FEC_CM3_CTI_APPCLEAR")]
pub type FecCm3CtiAppclear = crate :: Reg < fec_cm3_cti_appclear :: FecCm3CtiAppclearSpec > ; # [doc = "FEC_CM3_CTI_APPCLEAR"]
pub mod fec_cm3_cti_appclear { # [doc = "Register `FEC_CM3_CTI_APPCLEAR` reader"]
pub type R = crate :: R < FecCm3CtiAppclearSpec > ; # [doc = "Register `FEC_CM3_CTI_APPCLEAR` writer"]
pub type W = crate :: W < FecCm3CtiAppclearSpec > ; # [doc = "Field `FEC_CM3_CTI_APPCLEAR` reader - "]
pub type FecCm3CtiAppclearR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_APPCLEAR` writer - "]
pub type FecCm3CtiAppclearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_appclear (& self) -> FecCm3CtiAppclearR { FecCm3CtiAppclearR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_appclear (& mut self) -> FecCm3CtiAppclearW < FecCm3CtiAppclearSpec > { FecCm3CtiAppclearW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_APPCLEAR\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_appclear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_appclear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiAppclearSpec ; impl crate :: RegisterSpec for FecCm3CtiAppclearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_appclear::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiAppclearSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_appclear::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiAppclearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_APPCLEAR to value 0"]
impl crate :: Resettable for FecCm3CtiAppclearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_APPPULSE (rw) register accessor: FEC_CM3_CTI_APPPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_apppulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_apppulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_apppulse`]
module"]
# [doc (alias = "FEC_CM3_CTI_APPPULSE")]
pub type FecCm3CtiApppulse = crate :: Reg < fec_cm3_cti_apppulse :: FecCm3CtiApppulseSpec > ; # [doc = "FEC_CM3_CTI_APPPULSE"]
pub mod fec_cm3_cti_apppulse { # [doc = "Register `FEC_CM3_CTI_APPPULSE` reader"]
pub type R = crate :: R < FecCm3CtiApppulseSpec > ; # [doc = "Register `FEC_CM3_CTI_APPPULSE` writer"]
pub type W = crate :: W < FecCm3CtiApppulseSpec > ; # [doc = "Field `FEC_CM3_CTI_APPPULSE` reader - "]
pub type FecCm3CtiApppulseR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_APPPULSE` writer - "]
pub type FecCm3CtiApppulseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_apppulse (& self) -> FecCm3CtiApppulseR { FecCm3CtiApppulseR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_apppulse (& mut self) -> FecCm3CtiApppulseW < FecCm3CtiApppulseSpec > { FecCm3CtiApppulseW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_APPPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_apppulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_apppulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiApppulseSpec ; impl crate :: RegisterSpec for FecCm3CtiApppulseSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_apppulse::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiApppulseSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_apppulse::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiApppulseSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_APPPULSE to value 0"]
impl crate :: Resettable for FecCm3CtiApppulseSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN0 (rw) register accessor: FEC_CM3_CTI_INEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen0`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN0")]
pub type FecCm3CtiInen0 = crate :: Reg < fec_cm3_cti_inen0 :: FecCm3CtiInen0Spec > ; # [doc = "FEC_CM3_CTI_INEN0"]
pub mod fec_cm3_cti_inen0 { # [doc = "Register `FEC_CM3_CTI_INEN0` reader"]
pub type R = crate :: R < FecCm3CtiInen0Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN0` writer"]
pub type W = crate :: W < FecCm3CtiInen0Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN0` reader - "]
pub type FecCm3CtiInen0R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN0` writer - "]
pub type FecCm3CtiInen0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen0 (& self) -> FecCm3CtiInen0R { FecCm3CtiInen0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen0 (& mut self) -> FecCm3CtiInen0W < FecCm3CtiInen0Spec > { FecCm3CtiInen0W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen0Spec ; impl crate :: RegisterSpec for FecCm3CtiInen0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen0::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen0Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen0::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN0 to value 0"]
impl crate :: Resettable for FecCm3CtiInen0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN1 (rw) register accessor: FEC_CM3_CTI_INEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen1`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN1")]
pub type FecCm3CtiInen1 = crate :: Reg < fec_cm3_cti_inen1 :: FecCm3CtiInen1Spec > ; # [doc = "FEC_CM3_CTI_INEN1"]
pub mod fec_cm3_cti_inen1 { # [doc = "Register `FEC_CM3_CTI_INEN1` reader"]
pub type R = crate :: R < FecCm3CtiInen1Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN1` writer"]
pub type W = crate :: W < FecCm3CtiInen1Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN1` reader - "]
pub type FecCm3CtiInen1R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN1` writer - "]
pub type FecCm3CtiInen1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen1 (& self) -> FecCm3CtiInen1R { FecCm3CtiInen1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen1 (& mut self) -> FecCm3CtiInen1W < FecCm3CtiInen1Spec > { FecCm3CtiInen1W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen1Spec ; impl crate :: RegisterSpec for FecCm3CtiInen1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen1::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen1Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen1::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN1 to value 0"]
impl crate :: Resettable for FecCm3CtiInen1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN2 (rw) register accessor: FEC_CM3_CTI_INEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen2`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN2")]
pub type FecCm3CtiInen2 = crate :: Reg < fec_cm3_cti_inen2 :: FecCm3CtiInen2Spec > ; # [doc = "FEC_CM3_CTI_INEN2"]
pub mod fec_cm3_cti_inen2 { # [doc = "Register `FEC_CM3_CTI_INEN2` reader"]
pub type R = crate :: R < FecCm3CtiInen2Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN2` writer"]
pub type W = crate :: W < FecCm3CtiInen2Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN2` reader - "]
pub type FecCm3CtiInen2R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN2` writer - "]
pub type FecCm3CtiInen2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen2 (& self) -> FecCm3CtiInen2R { FecCm3CtiInen2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen2 (& mut self) -> FecCm3CtiInen2W < FecCm3CtiInen2Spec > { FecCm3CtiInen2W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen2Spec ; impl crate :: RegisterSpec for FecCm3CtiInen2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen2::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen2Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen2::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN2 to value 0"]
impl crate :: Resettable for FecCm3CtiInen2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN3 (rw) register accessor: FEC_CM3_CTI_INEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen3`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN3")]
pub type FecCm3CtiInen3 = crate :: Reg < fec_cm3_cti_inen3 :: FecCm3CtiInen3Spec > ; # [doc = "FEC_CM3_CTI_INEN3"]
pub mod fec_cm3_cti_inen3 { # [doc = "Register `FEC_CM3_CTI_INEN3` reader"]
pub type R = crate :: R < FecCm3CtiInen3Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN3` writer"]
pub type W = crate :: W < FecCm3CtiInen3Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN3` reader - "]
pub type FecCm3CtiInen3R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN3` writer - "]
pub type FecCm3CtiInen3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen3 (& self) -> FecCm3CtiInen3R { FecCm3CtiInen3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen3 (& mut self) -> FecCm3CtiInen3W < FecCm3CtiInen3Spec > { FecCm3CtiInen3W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen3Spec ; impl crate :: RegisterSpec for FecCm3CtiInen3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen3::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen3Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen3::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN3 to value 0"]
impl crate :: Resettable for FecCm3CtiInen3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN4 (rw) register accessor: FEC_CM3_CTI_INEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen4`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN4")]
pub type FecCm3CtiInen4 = crate :: Reg < fec_cm3_cti_inen4 :: FecCm3CtiInen4Spec > ; # [doc = "FEC_CM3_CTI_INEN4"]
pub mod fec_cm3_cti_inen4 { # [doc = "Register `FEC_CM3_CTI_INEN4` reader"]
pub type R = crate :: R < FecCm3CtiInen4Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN4` writer"]
pub type W = crate :: W < FecCm3CtiInen4Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN4` reader - "]
pub type FecCm3CtiInen4R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN4` writer - "]
pub type FecCm3CtiInen4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen4 (& self) -> FecCm3CtiInen4R { FecCm3CtiInen4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen4 (& mut self) -> FecCm3CtiInen4W < FecCm3CtiInen4Spec > { FecCm3CtiInen4W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen4Spec ; impl crate :: RegisterSpec for FecCm3CtiInen4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen4::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen4Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen4::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN4 to value 0"]
impl crate :: Resettable for FecCm3CtiInen4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN5 (rw) register accessor: FEC_CM3_CTI_INEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen5`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN5")]
pub type FecCm3CtiInen5 = crate :: Reg < fec_cm3_cti_inen5 :: FecCm3CtiInen5Spec > ; # [doc = "FEC_CM3_CTI_INEN5"]
pub mod fec_cm3_cti_inen5 { # [doc = "Register `FEC_CM3_CTI_INEN5` reader"]
pub type R = crate :: R < FecCm3CtiInen5Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN5` writer"]
pub type W = crate :: W < FecCm3CtiInen5Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN5` reader - "]
pub type FecCm3CtiInen5R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN5` writer - "]
pub type FecCm3CtiInen5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen5 (& self) -> FecCm3CtiInen5R { FecCm3CtiInen5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen5 (& mut self) -> FecCm3CtiInen5W < FecCm3CtiInen5Spec > { FecCm3CtiInen5W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen5Spec ; impl crate :: RegisterSpec for FecCm3CtiInen5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen5::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen5Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen5::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN5 to value 0"]
impl crate :: Resettable for FecCm3CtiInen5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN6 (rw) register accessor: FEC_CM3_CTI_INEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen6`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN6")]
pub type FecCm3CtiInen6 = crate :: Reg < fec_cm3_cti_inen6 :: FecCm3CtiInen6Spec > ; # [doc = "FEC_CM3_CTI_INEN6"]
pub mod fec_cm3_cti_inen6 { # [doc = "Register `FEC_CM3_CTI_INEN6` reader"]
pub type R = crate :: R < FecCm3CtiInen6Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN6` writer"]
pub type W = crate :: W < FecCm3CtiInen6Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN6` reader - "]
pub type FecCm3CtiInen6R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN6` writer - "]
pub type FecCm3CtiInen6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen6 (& self) -> FecCm3CtiInen6R { FecCm3CtiInen6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen6 (& mut self) -> FecCm3CtiInen6W < FecCm3CtiInen6Spec > { FecCm3CtiInen6W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen6Spec ; impl crate :: RegisterSpec for FecCm3CtiInen6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen6::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen6Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen6::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN6 to value 0"]
impl crate :: Resettable for FecCm3CtiInen6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_INEN7 (rw) register accessor: FEC_CM3_CTI_INEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_inen7`]
module"]
# [doc (alias = "FEC_CM3_CTI_INEN7")]
pub type FecCm3CtiInen7 = crate :: Reg < fec_cm3_cti_inen7 :: FecCm3CtiInen7Spec > ; # [doc = "FEC_CM3_CTI_INEN7"]
pub mod fec_cm3_cti_inen7 { # [doc = "Register `FEC_CM3_CTI_INEN7` reader"]
pub type R = crate :: R < FecCm3CtiInen7Spec > ; # [doc = "Register `FEC_CM3_CTI_INEN7` writer"]
pub type W = crate :: W < FecCm3CtiInen7Spec > ; # [doc = "Field `FEC_CM3_CTI_INEN7` reader - "]
pub type FecCm3CtiInen7R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_INEN7` writer - "]
pub type FecCm3CtiInen7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_inen7 (& self) -> FecCm3CtiInen7R { FecCm3CtiInen7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_inen7 (& mut self) -> FecCm3CtiInen7W < FecCm3CtiInen7Spec > { FecCm3CtiInen7W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_INEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_inen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_inen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiInen7Spec ; impl crate :: RegisterSpec for FecCm3CtiInen7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_inen7::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiInen7Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_inen7::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiInen7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_INEN7 to value 0"]
impl crate :: Resettable for FecCm3CtiInen7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN0 (rw) register accessor: FEC_CM3_CTI_OUTEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen0`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN0")]
pub type FecCm3CtiOuten0 = crate :: Reg < fec_cm3_cti_outen0 :: FecCm3CtiOuten0Spec > ; # [doc = "FEC_CM3_CTI_OUTEN0"]
pub mod fec_cm3_cti_outen0 { # [doc = "Register `FEC_CM3_CTI_OUTEN0` reader"]
pub type R = crate :: R < FecCm3CtiOuten0Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN0` writer"]
pub type W = crate :: W < FecCm3CtiOuten0Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN0` reader - "]
pub type FecCm3CtiOuten0R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN0` writer - "]
pub type FecCm3CtiOuten0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen0 (& self) -> FecCm3CtiOuten0R { FecCm3CtiOuten0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen0 (& mut self) -> FecCm3CtiOuten0W < FecCm3CtiOuten0Spec > { FecCm3CtiOuten0W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten0Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen0::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten0Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen0::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN0 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN1 (rw) register accessor: FEC_CM3_CTI_OUTEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen1`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN1")]
pub type FecCm3CtiOuten1 = crate :: Reg < fec_cm3_cti_outen1 :: FecCm3CtiOuten1Spec > ; # [doc = "FEC_CM3_CTI_OUTEN1"]
pub mod fec_cm3_cti_outen1 { # [doc = "Register `FEC_CM3_CTI_OUTEN1` reader"]
pub type R = crate :: R < FecCm3CtiOuten1Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN1` writer"]
pub type W = crate :: W < FecCm3CtiOuten1Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN1` reader - "]
pub type FecCm3CtiOuten1R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN1` writer - "]
pub type FecCm3CtiOuten1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen1 (& self) -> FecCm3CtiOuten1R { FecCm3CtiOuten1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen1 (& mut self) -> FecCm3CtiOuten1W < FecCm3CtiOuten1Spec > { FecCm3CtiOuten1W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten1Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen1::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten1Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen1::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN1 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN2 (rw) register accessor: FEC_CM3_CTI_OUTEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen2`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN2")]
pub type FecCm3CtiOuten2 = crate :: Reg < fec_cm3_cti_outen2 :: FecCm3CtiOuten2Spec > ; # [doc = "FEC_CM3_CTI_OUTEN2"]
pub mod fec_cm3_cti_outen2 { # [doc = "Register `FEC_CM3_CTI_OUTEN2` reader"]
pub type R = crate :: R < FecCm3CtiOuten2Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN2` writer"]
pub type W = crate :: W < FecCm3CtiOuten2Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN2` reader - "]
pub type FecCm3CtiOuten2R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN2` writer - "]
pub type FecCm3CtiOuten2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen2 (& self) -> FecCm3CtiOuten2R { FecCm3CtiOuten2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen2 (& mut self) -> FecCm3CtiOuten2W < FecCm3CtiOuten2Spec > { FecCm3CtiOuten2W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten2Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen2::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten2Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen2::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN2 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN3 (rw) register accessor: FEC_CM3_CTI_OUTEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen3`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN3")]
pub type FecCm3CtiOuten3 = crate :: Reg < fec_cm3_cti_outen3 :: FecCm3CtiOuten3Spec > ; # [doc = "FEC_CM3_CTI_OUTEN3"]
pub mod fec_cm3_cti_outen3 { # [doc = "Register `FEC_CM3_CTI_OUTEN3` reader"]
pub type R = crate :: R < FecCm3CtiOuten3Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN3` writer"]
pub type W = crate :: W < FecCm3CtiOuten3Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN3` reader - "]
pub type FecCm3CtiOuten3R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN3` writer - "]
pub type FecCm3CtiOuten3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen3 (& self) -> FecCm3CtiOuten3R { FecCm3CtiOuten3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen3 (& mut self) -> FecCm3CtiOuten3W < FecCm3CtiOuten3Spec > { FecCm3CtiOuten3W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten3Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen3::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten3Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen3::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN3 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN4 (rw) register accessor: FEC_CM3_CTI_OUTEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen4`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN4")]
pub type FecCm3CtiOuten4 = crate :: Reg < fec_cm3_cti_outen4 :: FecCm3CtiOuten4Spec > ; # [doc = "FEC_CM3_CTI_OUTEN4"]
pub mod fec_cm3_cti_outen4 { # [doc = "Register `FEC_CM3_CTI_OUTEN4` reader"]
pub type R = crate :: R < FecCm3CtiOuten4Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN4` writer"]
pub type W = crate :: W < FecCm3CtiOuten4Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN4` reader - "]
pub type FecCm3CtiOuten4R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN4` writer - "]
pub type FecCm3CtiOuten4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen4 (& self) -> FecCm3CtiOuten4R { FecCm3CtiOuten4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen4 (& mut self) -> FecCm3CtiOuten4W < FecCm3CtiOuten4Spec > { FecCm3CtiOuten4W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN4\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten4Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen4::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten4Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen4::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN4 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN5 (rw) register accessor: FEC_CM3_CTI_OUTEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen5`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN5")]
pub type FecCm3CtiOuten5 = crate :: Reg < fec_cm3_cti_outen5 :: FecCm3CtiOuten5Spec > ; # [doc = "FEC_CM3_CTI_OUTEN5"]
pub mod fec_cm3_cti_outen5 { # [doc = "Register `FEC_CM3_CTI_OUTEN5` reader"]
pub type R = crate :: R < FecCm3CtiOuten5Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN5` writer"]
pub type W = crate :: W < FecCm3CtiOuten5Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN5` reader - "]
pub type FecCm3CtiOuten5R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN5` writer - "]
pub type FecCm3CtiOuten5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen5 (& self) -> FecCm3CtiOuten5R { FecCm3CtiOuten5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen5 (& mut self) -> FecCm3CtiOuten5W < FecCm3CtiOuten5Spec > { FecCm3CtiOuten5W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN5\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten5Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen5::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten5Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen5::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN5 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN6 (rw) register accessor: FEC_CM3_CTI_OUTEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen6`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN6")]
pub type FecCm3CtiOuten6 = crate :: Reg < fec_cm3_cti_outen6 :: FecCm3CtiOuten6Spec > ; # [doc = "FEC_CM3_CTI_OUTEN6"]
pub mod fec_cm3_cti_outen6 { # [doc = "Register `FEC_CM3_CTI_OUTEN6` reader"]
pub type R = crate :: R < FecCm3CtiOuten6Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN6` writer"]
pub type W = crate :: W < FecCm3CtiOuten6Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN6` reader - "]
pub type FecCm3CtiOuten6R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN6` writer - "]
pub type FecCm3CtiOuten6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen6 (& self) -> FecCm3CtiOuten6R { FecCm3CtiOuten6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen6 (& mut self) -> FecCm3CtiOuten6W < FecCm3CtiOuten6Spec > { FecCm3CtiOuten6W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN6\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten6Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen6::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten6Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen6::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN6 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_OUTEN7 (rw) register accessor: FEC_CM3_CTI_OUTEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_outen7`]
module"]
# [doc (alias = "FEC_CM3_CTI_OUTEN7")]
pub type FecCm3CtiOuten7 = crate :: Reg < fec_cm3_cti_outen7 :: FecCm3CtiOuten7Spec > ; # [doc = "FEC_CM3_CTI_OUTEN7"]
pub mod fec_cm3_cti_outen7 { # [doc = "Register `FEC_CM3_CTI_OUTEN7` reader"]
pub type R = crate :: R < FecCm3CtiOuten7Spec > ; # [doc = "Register `FEC_CM3_CTI_OUTEN7` writer"]
pub type W = crate :: W < FecCm3CtiOuten7Spec > ; # [doc = "Field `FEC_CM3_CTI_OUTEN7` reader - "]
pub type FecCm3CtiOuten7R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_OUTEN7` writer - "]
pub type FecCm3CtiOuten7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_outen7 (& self) -> FecCm3CtiOuten7R { FecCm3CtiOuten7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_outen7 (& mut self) -> FecCm3CtiOuten7W < FecCm3CtiOuten7Spec > { FecCm3CtiOuten7W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_OUTEN7\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_outen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_outen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiOuten7Spec ; impl crate :: RegisterSpec for FecCm3CtiOuten7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_outen7::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiOuten7Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_outen7::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiOuten7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_OUTEN7 to value 0"]
impl crate :: Resettable for FecCm3CtiOuten7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_TRIGINSTATUS (rw) register accessor: FEC_CM3_CTI_TRIGINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_triginstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_triginstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_triginstatus`]
module"]
# [doc (alias = "FEC_CM3_CTI_TRIGINSTATUS")]
pub type FecCm3CtiTriginstatus = crate :: Reg < fec_cm3_cti_triginstatus :: FecCm3CtiTriginstatusSpec > ; # [doc = "FEC_CM3_CTI_TRIGINSTATUS"]
pub mod fec_cm3_cti_triginstatus { # [doc = "Register `FEC_CM3_CTI_TRIGINSTATUS` reader"]
pub type R = crate :: R < FecCm3CtiTriginstatusSpec > ; # [doc = "Register `FEC_CM3_CTI_TRIGINSTATUS` writer"]
pub type W = crate :: W < FecCm3CtiTriginstatusSpec > ; # [doc = "Field `FEC_CM3_CTI_TRIGINSTATUS` reader - "]
pub type FecCm3CtiTriginstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_TRIGINSTATUS` writer - "]
pub type FecCm3CtiTriginstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_triginstatus (& self) -> FecCm3CtiTriginstatusR { FecCm3CtiTriginstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_triginstatus (& mut self) -> FecCm3CtiTriginstatusW < FecCm3CtiTriginstatusSpec > { FecCm3CtiTriginstatusW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_TRIGINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_triginstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_triginstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiTriginstatusSpec ; impl crate :: RegisterSpec for FecCm3CtiTriginstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_triginstatus::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiTriginstatusSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_triginstatus::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiTriginstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_TRIGINSTATUS to value 0"]
impl crate :: Resettable for FecCm3CtiTriginstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_TRIGOUTSTATUS (rw) register accessor: FEC_CM3_CTI_TRIGOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_trigoutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_trigoutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_trigoutstatus`]
module"]
# [doc (alias = "FEC_CM3_CTI_TRIGOUTSTATUS")]
pub type FecCm3CtiTrigoutstatus = crate :: Reg < fec_cm3_cti_trigoutstatus :: FecCm3CtiTrigoutstatusSpec > ; # [doc = "FEC_CM3_CTI_TRIGOUTSTATUS"]
pub mod fec_cm3_cti_trigoutstatus { # [doc = "Register `FEC_CM3_CTI_TRIGOUTSTATUS` reader"]
pub type R = crate :: R < FecCm3CtiTrigoutstatusSpec > ; # [doc = "Register `FEC_CM3_CTI_TRIGOUTSTATUS` writer"]
pub type W = crate :: W < FecCm3CtiTrigoutstatusSpec > ; # [doc = "Field `FEC_CM3_CTI_TRIGOUTSTATUS` reader - "]
pub type FecCm3CtiTrigoutstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_TRIGOUTSTATUS` writer - "]
pub type FecCm3CtiTrigoutstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_trigoutstatus (& self) -> FecCm3CtiTrigoutstatusR { FecCm3CtiTrigoutstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_trigoutstatus (& mut self) -> FecCm3CtiTrigoutstatusW < FecCm3CtiTrigoutstatusSpec > { FecCm3CtiTrigoutstatusW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_TRIGOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_trigoutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_trigoutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiTrigoutstatusSpec ; impl crate :: RegisterSpec for FecCm3CtiTrigoutstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_trigoutstatus::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiTrigoutstatusSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_trigoutstatus::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiTrigoutstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_TRIGOUTSTATUS to value 0"]
impl crate :: Resettable for FecCm3CtiTrigoutstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_CHINSTATUS (rw) register accessor: FEC_CM3_CTI_CHINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_chinstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_chinstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_chinstatus`]
module"]
# [doc (alias = "FEC_CM3_CTI_CHINSTATUS")]
pub type FecCm3CtiChinstatus = crate :: Reg < fec_cm3_cti_chinstatus :: FecCm3CtiChinstatusSpec > ; # [doc = "FEC_CM3_CTI_CHINSTATUS"]
pub mod fec_cm3_cti_chinstatus { # [doc = "Register `FEC_CM3_CTI_CHINSTATUS` reader"]
pub type R = crate :: R < FecCm3CtiChinstatusSpec > ; # [doc = "Register `FEC_CM3_CTI_CHINSTATUS` writer"]
pub type W = crate :: W < FecCm3CtiChinstatusSpec > ; # [doc = "Field `FEC_CM3_CTI_CHINSTATUS` reader - "]
pub type FecCm3CtiChinstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_CHINSTATUS` writer - "]
pub type FecCm3CtiChinstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_chinstatus (& self) -> FecCm3CtiChinstatusR { FecCm3CtiChinstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_chinstatus (& mut self) -> FecCm3CtiChinstatusW < FecCm3CtiChinstatusSpec > { FecCm3CtiChinstatusW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_CHINSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_chinstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_chinstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiChinstatusSpec ; impl crate :: RegisterSpec for FecCm3CtiChinstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_chinstatus::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiChinstatusSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_chinstatus::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiChinstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_CHINSTATUS to value 0"]
impl crate :: Resettable for FecCm3CtiChinstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_CHOUTSTATUS (rw) register accessor: FEC_CM3_CTI_CHOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_choutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_choutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_choutstatus`]
module"]
# [doc (alias = "FEC_CM3_CTI_CHOUTSTATUS")]
pub type FecCm3CtiChoutstatus = crate :: Reg < fec_cm3_cti_choutstatus :: FecCm3CtiChoutstatusSpec > ; # [doc = "FEC_CM3_CTI_CHOUTSTATUS"]
pub mod fec_cm3_cti_choutstatus { # [doc = "Register `FEC_CM3_CTI_CHOUTSTATUS` reader"]
pub type R = crate :: R < FecCm3CtiChoutstatusSpec > ; # [doc = "Register `FEC_CM3_CTI_CHOUTSTATUS` writer"]
pub type W = crate :: W < FecCm3CtiChoutstatusSpec > ; # [doc = "Field `FEC_CM3_CTI_CHOUTSTATUS` reader - "]
pub type FecCm3CtiChoutstatusR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_CHOUTSTATUS` writer - "]
pub type FecCm3CtiChoutstatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_choutstatus (& self) -> FecCm3CtiChoutstatusR { FecCm3CtiChoutstatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_choutstatus (& mut self) -> FecCm3CtiChoutstatusW < FecCm3CtiChoutstatusSpec > { FecCm3CtiChoutstatusW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_CHOUTSTATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_choutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_choutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiChoutstatusSpec ; impl crate :: RegisterSpec for FecCm3CtiChoutstatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_choutstatus::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiChoutstatusSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_choutstatus::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiChoutstatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_CHOUTSTATUS to value 0"]
impl crate :: Resettable for FecCm3CtiChoutstatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_GATE (rw) register accessor: FEC_CM3_CTI_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_gate`]
module"]
# [doc (alias = "FEC_CM3_CTI_GATE")]
pub type FecCm3CtiGate = crate :: Reg < fec_cm3_cti_gate :: FecCm3CtiGateSpec > ; # [doc = "FEC_CM3_CTI_GATE"]
pub mod fec_cm3_cti_gate { # [doc = "Register `FEC_CM3_CTI_GATE` reader"]
pub type R = crate :: R < FecCm3CtiGateSpec > ; # [doc = "Register `FEC_CM3_CTI_GATE` writer"]
pub type W = crate :: W < FecCm3CtiGateSpec > ; # [doc = "Field `FEC_CM3_CTI_GATE` reader - "]
pub type FecCm3CtiGateR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_GATE` writer - "]
pub type FecCm3CtiGateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_gate (& self) -> FecCm3CtiGateR { FecCm3CtiGateR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_gate (& mut self) -> FecCm3CtiGateW < FecCm3CtiGateSpec > { FecCm3CtiGateW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_GATE\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiGateSpec ; impl crate :: RegisterSpec for FecCm3CtiGateSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_gate::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiGateSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_gate::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiGateSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_GATE to value 0"]
impl crate :: Resettable for FecCm3CtiGateSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ASICCTL (rw) register accessor: FEC_CM3_CTI_ASICCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_asicctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_asicctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_asicctl`]
module"]
# [doc (alias = "FEC_CM3_CTI_ASICCTL")]
pub type FecCm3CtiAsicctl = crate :: Reg < fec_cm3_cti_asicctl :: FecCm3CtiAsicctlSpec > ; # [doc = "FEC_CM3_CTI_ASICCTL"]
pub mod fec_cm3_cti_asicctl { # [doc = "Register `FEC_CM3_CTI_ASICCTL` reader"]
pub type R = crate :: R < FecCm3CtiAsicctlSpec > ; # [doc = "Register `FEC_CM3_CTI_ASICCTL` writer"]
pub type W = crate :: W < FecCm3CtiAsicctlSpec > ; # [doc = "Field `FEC_CM3_CTI_ASICCTL` reader - "]
pub type FecCm3CtiAsicctlR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ASICCTL` writer - "]
pub type FecCm3CtiAsicctlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_asicctl (& self) -> FecCm3CtiAsicctlR { FecCm3CtiAsicctlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_asicctl (& mut self) -> FecCm3CtiAsicctlW < FecCm3CtiAsicctlSpec > { FecCm3CtiAsicctlW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ASICCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_asicctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_asicctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiAsicctlSpec ; impl crate :: RegisterSpec for FecCm3CtiAsicctlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_asicctl::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiAsicctlSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_asicctl::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiAsicctlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ASICCTL to value 0"]
impl crate :: Resettable for FecCm3CtiAsicctlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITCHINACK (rw) register accessor: FEC_CM3_CTI_ITCHINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchinack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchinack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_itchinack`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITCHINACK")]
pub type FecCm3CtiItchinack = crate :: Reg < fec_cm3_cti_itchinack :: FecCm3CtiItchinackSpec > ; # [doc = "FEC_CM3_CTI_ITCHINACK"]
pub mod fec_cm3_cti_itchinack { # [doc = "Register `FEC_CM3_CTI_ITCHINACK` reader"]
pub type R = crate :: R < FecCm3CtiItchinackSpec > ; # [doc = "Register `FEC_CM3_CTI_ITCHINACK` writer"]
pub type W = crate :: W < FecCm3CtiItchinackSpec > ; # [doc = "Field `FEC_CM3_CTI_ITCHINACK` reader - "]
pub type FecCm3CtiItchinackR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITCHINACK` writer - "]
pub type FecCm3CtiItchinackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_itchinack (& self) -> FecCm3CtiItchinackR { FecCm3CtiItchinackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_itchinack (& mut self) -> FecCm3CtiItchinackW < FecCm3CtiItchinackSpec > { FecCm3CtiItchinackW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITCHINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchinack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchinack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiItchinackSpec ; impl crate :: RegisterSpec for FecCm3CtiItchinackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_itchinack::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiItchinackSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_itchinack::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiItchinackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITCHINACK to value 0"]
impl crate :: Resettable for FecCm3CtiItchinackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITTRIGINACK (rw) register accessor: FEC_CM3_CTI_ITTRIGINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittriginack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittriginack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_ittriginack`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITTRIGINACK")]
pub type FecCm3CtiIttriginack = crate :: Reg < fec_cm3_cti_ittriginack :: FecCm3CtiIttriginackSpec > ; # [doc = "FEC_CM3_CTI_ITTRIGINACK"]
pub mod fec_cm3_cti_ittriginack { # [doc = "Register `FEC_CM3_CTI_ITTRIGINACK` reader"]
pub type R = crate :: R < FecCm3CtiIttriginackSpec > ; # [doc = "Register `FEC_CM3_CTI_ITTRIGINACK` writer"]
pub type W = crate :: W < FecCm3CtiIttriginackSpec > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGINACK` reader - "]
pub type FecCm3CtiIttriginackR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGINACK` writer - "]
pub type FecCm3CtiIttriginackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_ittriginack (& self) -> FecCm3CtiIttriginackR { FecCm3CtiIttriginackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_ittriginack (& mut self) -> FecCm3CtiIttriginackW < FecCm3CtiIttriginackSpec > { FecCm3CtiIttriginackW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITTRIGINACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittriginack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittriginack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiIttriginackSpec ; impl crate :: RegisterSpec for FecCm3CtiIttriginackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_ittriginack::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiIttriginackSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_ittriginack::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiIttriginackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITTRIGINACK to value 0"]
impl crate :: Resettable for FecCm3CtiIttriginackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITCHOUT (rw) register accessor: FEC_CM3_CTI_ITCHOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_itchout`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITCHOUT")]
pub type FecCm3CtiItchout = crate :: Reg < fec_cm3_cti_itchout :: FecCm3CtiItchoutSpec > ; # [doc = "FEC_CM3_CTI_ITCHOUT"]
pub mod fec_cm3_cti_itchout { # [doc = "Register `FEC_CM3_CTI_ITCHOUT` reader"]
pub type R = crate :: R < FecCm3CtiItchoutSpec > ; # [doc = "Register `FEC_CM3_CTI_ITCHOUT` writer"]
pub type W = crate :: W < FecCm3CtiItchoutSpec > ; # [doc = "Field `FEC_CM3_CTI_ITCHOUT` reader - "]
pub type FecCm3CtiItchoutR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITCHOUT` writer - "]
pub type FecCm3CtiItchoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_itchout (& self) -> FecCm3CtiItchoutR { FecCm3CtiItchoutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_itchout (& mut self) -> FecCm3CtiItchoutW < FecCm3CtiItchoutSpec > { FecCm3CtiItchoutW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITCHOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiItchoutSpec ; impl crate :: RegisterSpec for FecCm3CtiItchoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_itchout::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiItchoutSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_itchout::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiItchoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITCHOUT to value 0"]
impl crate :: Resettable for FecCm3CtiItchoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITTRIGOUT (rw) register accessor: FEC_CM3_CTI_ITTRIGOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittrigout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittrigout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_ittrigout`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITTRIGOUT")]
pub type FecCm3CtiIttrigout = crate :: Reg < fec_cm3_cti_ittrigout :: FecCm3CtiIttrigoutSpec > ; # [doc = "FEC_CM3_CTI_ITTRIGOUT"]
pub mod fec_cm3_cti_ittrigout { # [doc = "Register `FEC_CM3_CTI_ITTRIGOUT` reader"]
pub type R = crate :: R < FecCm3CtiIttrigoutSpec > ; # [doc = "Register `FEC_CM3_CTI_ITTRIGOUT` writer"]
pub type W = crate :: W < FecCm3CtiIttrigoutSpec > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGOUT` reader - "]
pub type FecCm3CtiIttrigoutR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGOUT` writer - "]
pub type FecCm3CtiIttrigoutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_ittrigout (& self) -> FecCm3CtiIttrigoutR { FecCm3CtiIttrigoutR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_ittrigout (& mut self) -> FecCm3CtiIttrigoutW < FecCm3CtiIttrigoutSpec > { FecCm3CtiIttrigoutW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITTRIGOUT\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittrigout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittrigout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiIttrigoutSpec ; impl crate :: RegisterSpec for FecCm3CtiIttrigoutSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_ittrigout::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiIttrigoutSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_ittrigout::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiIttrigoutSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITTRIGOUT to value 0"]
impl crate :: Resettable for FecCm3CtiIttrigoutSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITCHOUTACK (rw) register accessor: FEC_CM3_CTI_ITCHOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchoutack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchoutack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_itchoutack`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITCHOUTACK")]
pub type FecCm3CtiItchoutack = crate :: Reg < fec_cm3_cti_itchoutack :: FecCm3CtiItchoutackSpec > ; # [doc = "FEC_CM3_CTI_ITCHOUTACK"]
pub mod fec_cm3_cti_itchoutack { # [doc = "Register `FEC_CM3_CTI_ITCHOUTACK` reader"]
pub type R = crate :: R < FecCm3CtiItchoutackSpec > ; # [doc = "Register `FEC_CM3_CTI_ITCHOUTACK` writer"]
pub type W = crate :: W < FecCm3CtiItchoutackSpec > ; # [doc = "Field `FEC_CM3_CTI_ITCHOUTACK` reader - "]
pub type FecCm3CtiItchoutackR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITCHOUTACK` writer - "]
pub type FecCm3CtiItchoutackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_itchoutack (& self) -> FecCm3CtiItchoutackR { FecCm3CtiItchoutackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_itchoutack (& mut self) -> FecCm3CtiItchoutackW < FecCm3CtiItchoutackSpec > { FecCm3CtiItchoutackW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITCHOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchoutack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchoutack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiItchoutackSpec ; impl crate :: RegisterSpec for FecCm3CtiItchoutackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_itchoutack::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiItchoutackSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_itchoutack::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiItchoutackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITCHOUTACK to value 0"]
impl crate :: Resettable for FecCm3CtiItchoutackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITTRIGOUTACK (rw) register accessor: FEC_CM3_CTI_ITTRIGOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittrigoutack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittrigoutack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_ittrigoutack`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITTRIGOUTACK")]
pub type FecCm3CtiIttrigoutack = crate :: Reg < fec_cm3_cti_ittrigoutack :: FecCm3CtiIttrigoutackSpec > ; # [doc = "FEC_CM3_CTI_ITTRIGOUTACK"]
pub mod fec_cm3_cti_ittrigoutack { # [doc = "Register `FEC_CM3_CTI_ITTRIGOUTACK` reader"]
pub type R = crate :: R < FecCm3CtiIttrigoutackSpec > ; # [doc = "Register `FEC_CM3_CTI_ITTRIGOUTACK` writer"]
pub type W = crate :: W < FecCm3CtiIttrigoutackSpec > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGOUTACK` reader - "]
pub type FecCm3CtiIttrigoutackR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGOUTACK` writer - "]
pub type FecCm3CtiIttrigoutackW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_ittrigoutack (& self) -> FecCm3CtiIttrigoutackR { FecCm3CtiIttrigoutackR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_ittrigoutack (& mut self) -> FecCm3CtiIttrigoutackW < FecCm3CtiIttrigoutackSpec > { FecCm3CtiIttrigoutackW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITTRIGOUTACK\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittrigoutack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittrigoutack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiIttrigoutackSpec ; impl crate :: RegisterSpec for FecCm3CtiIttrigoutackSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_ittrigoutack::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiIttrigoutackSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_ittrigoutack::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiIttrigoutackSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITTRIGOUTACK to value 0"]
impl crate :: Resettable for FecCm3CtiIttrigoutackSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITCHIN (rw) register accessor: FEC_CM3_CTI_ITCHIN\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_itchin`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITCHIN")]
pub type FecCm3CtiItchin = crate :: Reg < fec_cm3_cti_itchin :: FecCm3CtiItchinSpec > ; # [doc = "FEC_CM3_CTI_ITCHIN"]
pub mod fec_cm3_cti_itchin { # [doc = "Register `FEC_CM3_CTI_ITCHIN` reader"]
pub type R = crate :: R < FecCm3CtiItchinSpec > ; # [doc = "Register `FEC_CM3_CTI_ITCHIN` writer"]
pub type W = crate :: W < FecCm3CtiItchinSpec > ; # [doc = "Field `FEC_CM3_CTI_ITCHIN` reader - "]
pub type FecCm3CtiItchinR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITCHIN` writer - "]
pub type FecCm3CtiItchinW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_itchin (& self) -> FecCm3CtiItchinR { FecCm3CtiItchinR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_itchin (& mut self) -> FecCm3CtiItchinW < FecCm3CtiItchinSpec > { FecCm3CtiItchinW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITCHIN\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itchin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itchin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiItchinSpec ; impl crate :: RegisterSpec for FecCm3CtiItchinSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_itchin::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiItchinSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_itchin::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiItchinSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITCHIN to value 0"]
impl crate :: Resettable for FecCm3CtiItchinSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITTRIGIN (rw) register accessor: FEC_CM3_CTI_ITTRIGIN\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittrigin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittrigin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_ittrigin`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITTRIGIN")]
pub type FecCm3CtiIttrigin = crate :: Reg < fec_cm3_cti_ittrigin :: FecCm3CtiIttriginSpec > ; # [doc = "FEC_CM3_CTI_ITTRIGIN"]
pub mod fec_cm3_cti_ittrigin { # [doc = "Register `FEC_CM3_CTI_ITTRIGIN` reader"]
pub type R = crate :: R < FecCm3CtiIttriginSpec > ; # [doc = "Register `FEC_CM3_CTI_ITTRIGIN` writer"]
pub type W = crate :: W < FecCm3CtiIttriginSpec > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGIN` reader - "]
pub type FecCm3CtiIttriginR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITTRIGIN` writer - "]
pub type FecCm3CtiIttriginW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_ittrigin (& self) -> FecCm3CtiIttriginR { FecCm3CtiIttriginR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_ittrigin (& mut self) -> FecCm3CtiIttriginW < FecCm3CtiIttriginSpec > { FecCm3CtiIttriginW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITTRIGIN\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_ittrigin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_ittrigin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiIttriginSpec ; impl crate :: RegisterSpec for FecCm3CtiIttriginSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_ittrigin::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiIttriginSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_ittrigin::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiIttriginSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITTRIGIN to value 0"]
impl crate :: Resettable for FecCm3CtiIttriginSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_ITCTRL (rw) register accessor: FEC_CM3_CTI_ITCTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_itctrl`]
module"]
# [doc (alias = "FEC_CM3_CTI_ITCTRL")]
pub type FecCm3CtiItctrl = crate :: Reg < fec_cm3_cti_itctrl :: FecCm3CtiItctrlSpec > ; # [doc = "FEC_CM3_CTI_ITCTRL"]
pub mod fec_cm3_cti_itctrl { # [doc = "Register `FEC_CM3_CTI_ITCTRL` reader"]
pub type R = crate :: R < FecCm3CtiItctrlSpec > ; # [doc = "Register `FEC_CM3_CTI_ITCTRL` writer"]
pub type W = crate :: W < FecCm3CtiItctrlSpec > ; # [doc = "Field `FEC_CM3_CTI_ITCTRL` reader - "]
pub type FecCm3CtiItctrlR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_ITCTRL` writer - "]
pub type FecCm3CtiItctrlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_itctrl (& self) -> FecCm3CtiItctrlR { FecCm3CtiItctrlR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_itctrl (& mut self) -> FecCm3CtiItctrlW < FecCm3CtiItctrlSpec > { FecCm3CtiItctrlW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_ITCTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_itctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_itctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiItctrlSpec ; impl crate :: RegisterSpec for FecCm3CtiItctrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_itctrl::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiItctrlSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_itctrl::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiItctrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_ITCTRL to value 0"]
impl crate :: Resettable for FecCm3CtiItctrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Claim_Tag_Set (rw) register accessor: FEC_CM3_CTI_Claim_Tag_Set\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_claim_tag_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_claim_tag_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_claim_tag_set`]
module"]
# [doc (alias = "FEC_CM3_CTI_Claim_Tag_Set")]
pub type FecCm3CtiClaimTagSet = crate :: Reg < fec_cm3_cti_claim_tag_set :: FecCm3CtiClaimTagSetSpec > ; # [doc = "FEC_CM3_CTI_Claim_Tag_Set"]
pub mod fec_cm3_cti_claim_tag_set { # [doc = "Register `FEC_CM3_CTI_Claim_Tag_Set` reader"]
pub type R = crate :: R < FecCm3CtiClaimTagSetSpec > ; # [doc = "Register `FEC_CM3_CTI_Claim_Tag_Set` writer"]
pub type W = crate :: W < FecCm3CtiClaimTagSetSpec > ; # [doc = "Field `FEC_CM3_CTI_Claim_Tag_Set` reader - "]
pub type FecCm3CtiClaimTagSetR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Claim_Tag_Set` writer - "]
pub type FecCm3CtiClaimTagSetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_claim_tag_set (& self) -> FecCm3CtiClaimTagSetR { FecCm3CtiClaimTagSetR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_claim_tag_set (& mut self) -> FecCm3CtiClaimTagSetW < FecCm3CtiClaimTagSetSpec > { FecCm3CtiClaimTagSetW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Claim_Tag_Set\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_claim_tag_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_claim_tag_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiClaimTagSetSpec ; impl crate :: RegisterSpec for FecCm3CtiClaimTagSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_claim_tag_set::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiClaimTagSetSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_claim_tag_set::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiClaimTagSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Claim_Tag_Set to value 0"]
impl crate :: Resettable for FecCm3CtiClaimTagSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Claim_Tag_Clear (rw) register accessor: FEC_CM3_CTI_Claim_Tag_Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_claim_tag_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_claim_tag_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_claim_tag_clear`]
module"]
# [doc (alias = "FEC_CM3_CTI_Claim_Tag_Clear")]
pub type FecCm3CtiClaimTagClear = crate :: Reg < fec_cm3_cti_claim_tag_clear :: FecCm3CtiClaimTagClearSpec > ; # [doc = "FEC_CM3_CTI_Claim_Tag_Clear"]
pub mod fec_cm3_cti_claim_tag_clear { # [doc = "Register `FEC_CM3_CTI_Claim_Tag_Clear` reader"]
pub type R = crate :: R < FecCm3CtiClaimTagClearSpec > ; # [doc = "Register `FEC_CM3_CTI_Claim_Tag_Clear` writer"]
pub type W = crate :: W < FecCm3CtiClaimTagClearSpec > ; # [doc = "Field `FEC_CM3_CTI_Claim_Tag_Clear` reader - "]
pub type FecCm3CtiClaimTagClearR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Claim_Tag_Clear` writer - "]
pub type FecCm3CtiClaimTagClearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_claim_tag_clear (& self) -> FecCm3CtiClaimTagClearR { FecCm3CtiClaimTagClearR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_claim_tag_clear (& mut self) -> FecCm3CtiClaimTagClearW < FecCm3CtiClaimTagClearSpec > { FecCm3CtiClaimTagClearW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Claim_Tag_Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_claim_tag_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_claim_tag_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiClaimTagClearSpec ; impl crate :: RegisterSpec for FecCm3CtiClaimTagClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_claim_tag_clear::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiClaimTagClearSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_claim_tag_clear::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiClaimTagClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Claim_Tag_Clear to value 0"]
impl crate :: Resettable for FecCm3CtiClaimTagClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Lock_Access_Register (rw) register accessor: FEC_CM3_CTI_Lock_Access_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_lock_access_register::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_lock_access_register::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_lock_access_register`]
module"]
# [doc (alias = "FEC_CM3_CTI_Lock_Access_Register")]
pub type FecCm3CtiLockAccessRegister = crate :: Reg < fec_cm3_cti_lock_access_register :: FecCm3CtiLockAccessRegisterSpec > ; # [doc = "FEC_CM3_CTI_Lock_Access_Register"]
pub mod fec_cm3_cti_lock_access_register { # [doc = "Register `FEC_CM3_CTI_Lock_Access_Register` reader"]
pub type R = crate :: R < FecCm3CtiLockAccessRegisterSpec > ; # [doc = "Register `FEC_CM3_CTI_Lock_Access_Register` writer"]
pub type W = crate :: W < FecCm3CtiLockAccessRegisterSpec > ; # [doc = "Field `FEC_CM3_CTI_Lock_Access_Register` reader - "]
pub type FecCm3CtiLockAccessRegisterR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Lock_Access_Register` writer - "]
pub type FecCm3CtiLockAccessRegisterW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_lock_access_register (& self) -> FecCm3CtiLockAccessRegisterR { FecCm3CtiLockAccessRegisterR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_lock_access_register (& mut self) -> FecCm3CtiLockAccessRegisterW < FecCm3CtiLockAccessRegisterSpec > { FecCm3CtiLockAccessRegisterW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Lock_Access_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_lock_access_register::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_lock_access_register::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiLockAccessRegisterSpec ; impl crate :: RegisterSpec for FecCm3CtiLockAccessRegisterSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_lock_access_register::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiLockAccessRegisterSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_lock_access_register::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiLockAccessRegisterSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Lock_Access_Register to value 0"]
impl crate :: Resettable for FecCm3CtiLockAccessRegisterSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Lock_Status_Register (rw) register accessor: FEC_CM3_CTI_Lock_Status_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_lock_status_register::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_lock_status_register::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_lock_status_register`]
module"]
# [doc (alias = "FEC_CM3_CTI_Lock_Status_Register")]
pub type FecCm3CtiLockStatusRegister = crate :: Reg < fec_cm3_cti_lock_status_register :: FecCm3CtiLockStatusRegisterSpec > ; # [doc = "FEC_CM3_CTI_Lock_Status_Register"]
pub mod fec_cm3_cti_lock_status_register { # [doc = "Register `FEC_CM3_CTI_Lock_Status_Register` reader"]
pub type R = crate :: R < FecCm3CtiLockStatusRegisterSpec > ; # [doc = "Register `FEC_CM3_CTI_Lock_Status_Register` writer"]
pub type W = crate :: W < FecCm3CtiLockStatusRegisterSpec > ; # [doc = "Field `FEC_CM3_CTI_Lock_Status_Register` reader - "]
pub type FecCm3CtiLockStatusRegisterR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Lock_Status_Register` writer - "]
pub type FecCm3CtiLockStatusRegisterW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_lock_status_register (& self) -> FecCm3CtiLockStatusRegisterR { FecCm3CtiLockStatusRegisterR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_lock_status_register (& mut self) -> FecCm3CtiLockStatusRegisterW < FecCm3CtiLockStatusRegisterSpec > { FecCm3CtiLockStatusRegisterW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Lock_Status_Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_lock_status_register::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_lock_status_register::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiLockStatusRegisterSpec ; impl crate :: RegisterSpec for FecCm3CtiLockStatusRegisterSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_lock_status_register::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiLockStatusRegisterSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_lock_status_register::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiLockStatusRegisterSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Lock_Status_Register to value 0"]
impl crate :: Resettable for FecCm3CtiLockStatusRegisterSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Authentication_Status (rw) register accessor: FEC_CM3_CTI_Authentication_Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_authentication_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_authentication_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_authentication_status`]
module"]
# [doc (alias = "FEC_CM3_CTI_Authentication_Status")]
pub type FecCm3CtiAuthenticationStatus = crate :: Reg < fec_cm3_cti_authentication_status :: FecCm3CtiAuthenticationStatusSpec > ; # [doc = "FEC_CM3_CTI_Authentication_Status"]
pub mod fec_cm3_cti_authentication_status { # [doc = "Register `FEC_CM3_CTI_Authentication_Status` reader"]
pub type R = crate :: R < FecCm3CtiAuthenticationStatusSpec > ; # [doc = "Register `FEC_CM3_CTI_Authentication_Status` writer"]
pub type W = crate :: W < FecCm3CtiAuthenticationStatusSpec > ; # [doc = "Field `FEC_CM3_CTI_Authentication_Status` reader - "]
pub type FecCm3CtiAuthenticationStatusR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Authentication_Status` writer - "]
pub type FecCm3CtiAuthenticationStatusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_authentication_status (& self) -> FecCm3CtiAuthenticationStatusR { FecCm3CtiAuthenticationStatusR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_authentication_status (& mut self) -> FecCm3CtiAuthenticationStatusW < FecCm3CtiAuthenticationStatusSpec > { FecCm3CtiAuthenticationStatusW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Authentication_Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_authentication_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_authentication_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiAuthenticationStatusSpec ; impl crate :: RegisterSpec for FecCm3CtiAuthenticationStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_authentication_status::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiAuthenticationStatusSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_authentication_status::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiAuthenticationStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Authentication_Status to value 0"]
impl crate :: Resettable for FecCm3CtiAuthenticationStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Device_ID (rw) register accessor: FEC_CM3_CTI_Device_ID\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_device_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_device_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_device_id`]
module"]
# [doc (alias = "FEC_CM3_CTI_Device_ID")]
pub type FecCm3CtiDeviceId = crate :: Reg < fec_cm3_cti_device_id :: FecCm3CtiDeviceIdSpec > ; # [doc = "FEC_CM3_CTI_Device_ID"]
pub mod fec_cm3_cti_device_id { # [doc = "Register `FEC_CM3_CTI_Device_ID` reader"]
pub type R = crate :: R < FecCm3CtiDeviceIdSpec > ; # [doc = "Register `FEC_CM3_CTI_Device_ID` writer"]
pub type W = crate :: W < FecCm3CtiDeviceIdSpec > ; # [doc = "Field `FEC_CM3_CTI_Device_ID` reader - "]
pub type FecCm3CtiDeviceIdR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Device_ID` writer - "]
pub type FecCm3CtiDeviceIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_device_id (& self) -> FecCm3CtiDeviceIdR { FecCm3CtiDeviceIdR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_device_id (& mut self) -> FecCm3CtiDeviceIdW < FecCm3CtiDeviceIdSpec > { FecCm3CtiDeviceIdW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Device_ID\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_device_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_device_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiDeviceIdSpec ; impl crate :: RegisterSpec for FecCm3CtiDeviceIdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_device_id::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiDeviceIdSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_device_id::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiDeviceIdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Device_ID to value 0"]
impl crate :: Resettable for FecCm3CtiDeviceIdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Device_Type_Identifier (rw) register accessor: FEC_CM3_CTI_Device_Type_Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_device_type_identifier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_device_type_identifier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_device_type_identifier`]
module"]
# [doc (alias = "FEC_CM3_CTI_Device_Type_Identifier")]
pub type FecCm3CtiDeviceTypeIdentifier = crate :: Reg < fec_cm3_cti_device_type_identifier :: FecCm3CtiDeviceTypeIdentifierSpec > ; # [doc = "FEC_CM3_CTI_Device_Type_Identifier"]
pub mod fec_cm3_cti_device_type_identifier { # [doc = "Register `FEC_CM3_CTI_Device_Type_Identifier` reader"]
pub type R = crate :: R < FecCm3CtiDeviceTypeIdentifierSpec > ; # [doc = "Register `FEC_CM3_CTI_Device_Type_Identifier` writer"]
pub type W = crate :: W < FecCm3CtiDeviceTypeIdentifierSpec > ; # [doc = "Field `FEC_CM3_CTI_Device_Type_Identifier` reader - "]
pub type FecCm3CtiDeviceTypeIdentifierR = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Device_Type_Identifier` writer - "]
pub type FecCm3CtiDeviceTypeIdentifierW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_device_type_identifier (& self) -> FecCm3CtiDeviceTypeIdentifierR { FecCm3CtiDeviceTypeIdentifierR :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_device_type_identifier (& mut self) -> FecCm3CtiDeviceTypeIdentifierW < FecCm3CtiDeviceTypeIdentifierSpec > { FecCm3CtiDeviceTypeIdentifierW :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Device_Type_Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_device_type_identifier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_device_type_identifier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiDeviceTypeIdentifierSpec ; impl crate :: RegisterSpec for FecCm3CtiDeviceTypeIdentifierSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_device_type_identifier::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiDeviceTypeIdentifierSpec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_device_type_identifier::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiDeviceTypeIdentifierSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Device_Type_Identifier to value 0"]
impl crate :: Resettable for FecCm3CtiDeviceTypeIdentifierSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID4 (rw) register accessor: FEC_CM3_CTI_PeripheralID4\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id4`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID4")]
pub type FecCm3CtiPeripheralId4 = crate :: Reg < fec_cm3_cti_peripheral_id4 :: FecCm3CtiPeripheralId4Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID4"]
pub mod fec_cm3_cti_peripheral_id4 { # [doc = "Register `FEC_CM3_CTI_PeripheralID4` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId4Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID4` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId4Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID4` reader - "]
pub type FecCm3CtiPeripheralId4R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID4` writer - "]
pub type FecCm3CtiPeripheralId4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id4 (& self) -> FecCm3CtiPeripheralId4R { FecCm3CtiPeripheralId4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id4 (& mut self) -> FecCm3CtiPeripheralId4W < FecCm3CtiPeripheralId4Spec > { FecCm3CtiPeripheralId4W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID4\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId4Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id4::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId4Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id4::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID4 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID5 (rw) register accessor: FEC_CM3_CTI_PeripheralID5\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id5`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID5")]
pub type FecCm3CtiPeripheralId5 = crate :: Reg < fec_cm3_cti_peripheral_id5 :: FecCm3CtiPeripheralId5Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID5"]
pub mod fec_cm3_cti_peripheral_id5 { # [doc = "Register `FEC_CM3_CTI_PeripheralID5` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId5Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID5` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId5Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID5` reader - "]
pub type FecCm3CtiPeripheralId5R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID5` writer - "]
pub type FecCm3CtiPeripheralId5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id5 (& self) -> FecCm3CtiPeripheralId5R { FecCm3CtiPeripheralId5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id5 (& mut self) -> FecCm3CtiPeripheralId5W < FecCm3CtiPeripheralId5Spec > { FecCm3CtiPeripheralId5W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID5\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId5Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id5::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId5Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id5::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID5 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID6 (rw) register accessor: FEC_CM3_CTI_PeripheralID6\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id6`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID6")]
pub type FecCm3CtiPeripheralId6 = crate :: Reg < fec_cm3_cti_peripheral_id6 :: FecCm3CtiPeripheralId6Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID6"]
pub mod fec_cm3_cti_peripheral_id6 { # [doc = "Register `FEC_CM3_CTI_PeripheralID6` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId6Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID6` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId6Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID6` reader - "]
pub type FecCm3CtiPeripheralId6R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID6` writer - "]
pub type FecCm3CtiPeripheralId6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id6 (& self) -> FecCm3CtiPeripheralId6R { FecCm3CtiPeripheralId6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id6 (& mut self) -> FecCm3CtiPeripheralId6W < FecCm3CtiPeripheralId6Spec > { FecCm3CtiPeripheralId6W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID6\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId6Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id6::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId6Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id6::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID6 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID7 (rw) register accessor: FEC_CM3_CTI_PeripheralID7\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id7`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID7")]
pub type FecCm3CtiPeripheralId7 = crate :: Reg < fec_cm3_cti_peripheral_id7 :: FecCm3CtiPeripheralId7Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID7"]
pub mod fec_cm3_cti_peripheral_id7 { # [doc = "Register `FEC_CM3_CTI_PeripheralID7` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId7Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID7` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId7Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID7` reader - "]
pub type FecCm3CtiPeripheralId7R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID7` writer - "]
pub type FecCm3CtiPeripheralId7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id7 (& self) -> FecCm3CtiPeripheralId7R { FecCm3CtiPeripheralId7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id7 (& mut self) -> FecCm3CtiPeripheralId7W < FecCm3CtiPeripheralId7Spec > { FecCm3CtiPeripheralId7W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID7\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId7Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id7::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId7Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id7::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID7 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID0 (rw) register accessor: FEC_CM3_CTI_PeripheralID0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id0`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID0")]
pub type FecCm3CtiPeripheralId0 = crate :: Reg < fec_cm3_cti_peripheral_id0 :: FecCm3CtiPeripheralId0Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID0"]
pub mod fec_cm3_cti_peripheral_id0 { # [doc = "Register `FEC_CM3_CTI_PeripheralID0` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId0Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID0` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId0Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID0` reader - "]
pub type FecCm3CtiPeripheralId0R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID0` writer - "]
pub type FecCm3CtiPeripheralId0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id0 (& self) -> FecCm3CtiPeripheralId0R { FecCm3CtiPeripheralId0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id0 (& mut self) -> FecCm3CtiPeripheralId0W < FecCm3CtiPeripheralId0Spec > { FecCm3CtiPeripheralId0W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId0Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id0::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId0Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id0::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID0 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID1 (rw) register accessor: FEC_CM3_CTI_PeripheralID1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id1`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID1")]
pub type FecCm3CtiPeripheralId1 = crate :: Reg < fec_cm3_cti_peripheral_id1 :: FecCm3CtiPeripheralId1Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID1"]
pub mod fec_cm3_cti_peripheral_id1 { # [doc = "Register `FEC_CM3_CTI_PeripheralID1` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId1Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID1` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId1Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID1` reader - "]
pub type FecCm3CtiPeripheralId1R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID1` writer - "]
pub type FecCm3CtiPeripheralId1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id1 (& self) -> FecCm3CtiPeripheralId1R { FecCm3CtiPeripheralId1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id1 (& mut self) -> FecCm3CtiPeripheralId1W < FecCm3CtiPeripheralId1Spec > { FecCm3CtiPeripheralId1W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId1Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id1::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId1Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id1::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID1 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID2 (rw) register accessor: FEC_CM3_CTI_PeripheralID2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id2`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID2")]
pub type FecCm3CtiPeripheralId2 = crate :: Reg < fec_cm3_cti_peripheral_id2 :: FecCm3CtiPeripheralId2Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID2"]
pub mod fec_cm3_cti_peripheral_id2 { # [doc = "Register `FEC_CM3_CTI_PeripheralID2` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId2Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID2` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId2Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID2` reader - "]
pub type FecCm3CtiPeripheralId2R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID2` writer - "]
pub type FecCm3CtiPeripheralId2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id2 (& self) -> FecCm3CtiPeripheralId2R { FecCm3CtiPeripheralId2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id2 (& mut self) -> FecCm3CtiPeripheralId2W < FecCm3CtiPeripheralId2Spec > { FecCm3CtiPeripheralId2W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId2Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id2::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId2Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id2::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID2 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_PeripheralID3 (rw) register accessor: FEC_CM3_CTI_PeripheralID3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_peripheral_id3`]
module"]
# [doc (alias = "FEC_CM3_CTI_PeripheralID3")]
pub type FecCm3CtiPeripheralId3 = crate :: Reg < fec_cm3_cti_peripheral_id3 :: FecCm3CtiPeripheralId3Spec > ; # [doc = "FEC_CM3_CTI_PeripheralID3"]
pub mod fec_cm3_cti_peripheral_id3 { # [doc = "Register `FEC_CM3_CTI_PeripheralID3` reader"]
pub type R = crate :: R < FecCm3CtiPeripheralId3Spec > ; # [doc = "Register `FEC_CM3_CTI_PeripheralID3` writer"]
pub type W = crate :: W < FecCm3CtiPeripheralId3Spec > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID3` reader - "]
pub type FecCm3CtiPeripheralId3R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_PeripheralID3` writer - "]
pub type FecCm3CtiPeripheralId3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_peripheral_id3 (& self) -> FecCm3CtiPeripheralId3R { FecCm3CtiPeripheralId3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_peripheral_id3 (& mut self) -> FecCm3CtiPeripheralId3W < FecCm3CtiPeripheralId3Spec > { FecCm3CtiPeripheralId3W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_PeripheralID3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_peripheral_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_peripheral_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiPeripheralId3Spec ; impl crate :: RegisterSpec for FecCm3CtiPeripheralId3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_peripheral_id3::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiPeripheralId3Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_peripheral_id3::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiPeripheralId3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_PeripheralID3 to value 0"]
impl crate :: Resettable for FecCm3CtiPeripheralId3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Component_ID0 (rw) register accessor: FEC_CM3_CTI_Component_ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_component_id0`]
module"]
# [doc (alias = "FEC_CM3_CTI_Component_ID0")]
pub type FecCm3CtiComponentId0 = crate :: Reg < fec_cm3_cti_component_id0 :: FecCm3CtiComponentId0Spec > ; # [doc = "FEC_CM3_CTI_Component_ID0"]
pub mod fec_cm3_cti_component_id0 { # [doc = "Register `FEC_CM3_CTI_Component_ID0` reader"]
pub type R = crate :: R < FecCm3CtiComponentId0Spec > ; # [doc = "Register `FEC_CM3_CTI_Component_ID0` writer"]
pub type W = crate :: W < FecCm3CtiComponentId0Spec > ; # [doc = "Field `FEC_CM3_CTI_Component_ID0` reader - "]
pub type FecCm3CtiComponentId0R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Component_ID0` writer - "]
pub type FecCm3CtiComponentId0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_component_id0 (& self) -> FecCm3CtiComponentId0R { FecCm3CtiComponentId0R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_component_id0 (& mut self) -> FecCm3CtiComponentId0W < FecCm3CtiComponentId0Spec > { FecCm3CtiComponentId0W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Component_ID0\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiComponentId0Spec ; impl crate :: RegisterSpec for FecCm3CtiComponentId0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_component_id0::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiComponentId0Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_component_id0::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiComponentId0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Component_ID0 to value 0"]
impl crate :: Resettable for FecCm3CtiComponentId0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Component_ID1 (rw) register accessor: FEC_CM3_CTI_Component_ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_component_id1`]
module"]
# [doc (alias = "FEC_CM3_CTI_Component_ID1")]
pub type FecCm3CtiComponentId1 = crate :: Reg < fec_cm3_cti_component_id1 :: FecCm3CtiComponentId1Spec > ; # [doc = "FEC_CM3_CTI_Component_ID1"]
pub mod fec_cm3_cti_component_id1 { # [doc = "Register `FEC_CM3_CTI_Component_ID1` reader"]
pub type R = crate :: R < FecCm3CtiComponentId1Spec > ; # [doc = "Register `FEC_CM3_CTI_Component_ID1` writer"]
pub type W = crate :: W < FecCm3CtiComponentId1Spec > ; # [doc = "Field `FEC_CM3_CTI_Component_ID1` reader - "]
pub type FecCm3CtiComponentId1R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Component_ID1` writer - "]
pub type FecCm3CtiComponentId1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_component_id1 (& self) -> FecCm3CtiComponentId1R { FecCm3CtiComponentId1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_component_id1 (& mut self) -> FecCm3CtiComponentId1W < FecCm3CtiComponentId1Spec > { FecCm3CtiComponentId1W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Component_ID1\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiComponentId1Spec ; impl crate :: RegisterSpec for FecCm3CtiComponentId1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_component_id1::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiComponentId1Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_component_id1::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiComponentId1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Component_ID1 to value 0"]
impl crate :: Resettable for FecCm3CtiComponentId1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Component_ID2 (rw) register accessor: FEC_CM3_CTI_Component_ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_component_id2`]
module"]
# [doc (alias = "FEC_CM3_CTI_Component_ID2")]
pub type FecCm3CtiComponentId2 = crate :: Reg < fec_cm3_cti_component_id2 :: FecCm3CtiComponentId2Spec > ; # [doc = "FEC_CM3_CTI_Component_ID2"]
pub mod fec_cm3_cti_component_id2 { # [doc = "Register `FEC_CM3_CTI_Component_ID2` reader"]
pub type R = crate :: R < FecCm3CtiComponentId2Spec > ; # [doc = "Register `FEC_CM3_CTI_Component_ID2` writer"]
pub type W = crate :: W < FecCm3CtiComponentId2Spec > ; # [doc = "Field `FEC_CM3_CTI_Component_ID2` reader - "]
pub type FecCm3CtiComponentId2R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Component_ID2` writer - "]
pub type FecCm3CtiComponentId2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_component_id2 (& self) -> FecCm3CtiComponentId2R { FecCm3CtiComponentId2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_component_id2 (& mut self) -> FecCm3CtiComponentId2W < FecCm3CtiComponentId2Spec > { FecCm3CtiComponentId2W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Component_ID2\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiComponentId2Spec ; impl crate :: RegisterSpec for FecCm3CtiComponentId2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_component_id2::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiComponentId2Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_component_id2::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiComponentId2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Component_ID2 to value 0"]
impl crate :: Resettable for FecCm3CtiComponentId2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "FEC_CM3_CTI_Component_ID3 (rw) register accessor: FEC_CM3_CTI_Component_ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fec_cm3_cti_component_id3`]
module"]
# [doc (alias = "FEC_CM3_CTI_Component_ID3")]
pub type FecCm3CtiComponentId3 = crate :: Reg < fec_cm3_cti_component_id3 :: FecCm3CtiComponentId3Spec > ; # [doc = "FEC_CM3_CTI_Component_ID3"]
pub mod fec_cm3_cti_component_id3 { # [doc = "Register `FEC_CM3_CTI_Component_ID3` reader"]
pub type R = crate :: R < FecCm3CtiComponentId3Spec > ; # [doc = "Register `FEC_CM3_CTI_Component_ID3` writer"]
pub type W = crate :: W < FecCm3CtiComponentId3Spec > ; # [doc = "Field `FEC_CM3_CTI_Component_ID3` reader - "]
pub type FecCm3CtiComponentId3R = crate :: FieldReader < u32 > ; # [doc = "Field `FEC_CM3_CTI_Component_ID3` writer - "]
pub type FecCm3CtiComponentId3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31"]
# [inline (always)]
pub fn fec_cm3_cti_component_id3 (& self) -> FecCm3CtiComponentId3R { FecCm3CtiComponentId3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31"]
# [inline (always)]
# [must_use]
pub fn fec_cm3_cti_component_id3 (& mut self) -> FecCm3CtiComponentId3W < FecCm3CtiComponentId3Spec > { FecCm3CtiComponentId3W :: new (self , 0) } } # [doc = "FEC_CM3_CTI_Component_ID3\n\nYou can [`read`](crate::Reg::read) this register and get [`fec_cm3_cti_component_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fec_cm3_cti_component_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FecCm3CtiComponentId3Spec ; impl crate :: RegisterSpec for FecCm3CtiComponentId3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`fec_cm3_cti_component_id3::R`](R) reader structure"]
impl crate :: Readable for FecCm3CtiComponentId3Spec { } # [doc = "`write(|w| ..)` method takes [`fec_cm3_cti_component_id3::W`](W) writer structure"]
impl crate :: Writable for FecCm3CtiComponentId3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FEC_CM3_CTI_Component_ID3 to value 0"]
impl crate :: Resettable for FecCm3CtiComponentId3Spec { const RESET_VALUE : u32 = 0 ; } } } # [doc = "APP_CFG_QSPI"]
pub struct AppCfgQspi { _marker : PhantomData < * const () > } unsafe impl Send for AppCfgQspi { } impl AppCfgQspi { # [doc = r"Pointer to the register block"]
pub const PTR : * const app_cfg_qspi :: RegisterBlock = 0x7800_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const app_cfg_qspi :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AppCfgQspi { type Target = app_cfg_qspi :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AppCfgQspi { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AppCfgQspi") . finish () } } # [doc = "APP_CFG_QSPI"]
pub mod app_cfg_qspi { # [repr (C)]
# [doc = "Register block"]
pub struct RegisterBlock { pid : Pid , mss_qspi_reserved1 : MssQspiReserved1 , mss_qspi_reserved2 : MssQspiReserved2 , mss_qspi_reserved3 : MssQspiReserved3 , sysconfig : Sysconfig , mss_qspi_reserved4 : MssQspiReserved4 , mss_qspi_reserved5 : MssQspiReserved5 , mss_qspi_reserved6 : MssQspiReserved6 , intr_status_raw_set : IntrStatusRawSet , intr_status_enabled_clear : IntrStatusEnabledClear , intr_enable_set : IntrEnableSet , intr_enable_clear : IntrEnableClear , intc_eoi : IntcEoi , mss_qspi_reserved7 : MssQspiReserved7 , mss_qspi_reserved8 : MssQspiReserved8 , mss_qspi_reserved9 : MssQspiReserved9 , spi_clock_cntrl : SpiClockCntrl , spi_dc : SpiDc , spi_cmd : SpiCmd , spi_status : SpiStatus , spi_data : SpiData , spi_setup0 : SpiSetup0 , spi_setup1 : SpiSetup1 , spi_setup2 : SpiSetup2 , spi_setup3 : SpiSetup3 , spi_switch : SpiSwitch , spi_data1 : SpiData1 , spi_data2 : SpiData2 , spi_data3 : SpiData3 , } impl RegisterBlock { # [doc = "0x00 - PID"]
# [inline (always)]
pub const fn pid (& self) -> & Pid { & self . pid } # [doc = "0x04 - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved1 (& self) -> & MssQspiReserved1 { & self . mss_qspi_reserved1 } # [doc = "0x08 - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved2 (& self) -> & MssQspiReserved2 { & self . mss_qspi_reserved2 } # [doc = "0x0c - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved3 (& self) -> & MssQspiReserved3 { & self . mss_qspi_reserved3 } # [doc = "0x10 - SYSCONFIG"]
# [inline (always)]
pub const fn sysconfig (& self) -> & Sysconfig { & self . sysconfig } # [doc = "0x14 - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved4 (& self) -> & MssQspiReserved4 { & self . mss_qspi_reserved4 } # [doc = "0x18 - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved5 (& self) -> & MssQspiReserved5 { & self . mss_qspi_reserved5 } # [doc = "0x1c - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved6 (& self) -> & MssQspiReserved6 { & self . mss_qspi_reserved6 } # [doc = "0x20 - INTR Interrupt Status Raw/Set Register"]
# [inline (always)]
pub const fn intr_status_raw_set (& self) -> & IntrStatusRawSet { & self . intr_status_raw_set } # [doc = "0x24 - INTR Interrupt Status Enabled/Clear Register"]
# [inline (always)]
pub const fn intr_status_enabled_clear (& self) -> & IntrStatusEnabledClear { & self . intr_status_enabled_clear } # [doc = "0x28 - INTR Interrupt Enable/Set Register"]
# [inline (always)]
pub const fn intr_enable_set (& self) -> & IntrEnableSet { & self . intr_enable_set } # [doc = "0x2c - INTR Interrupt Enable/Clear Register"]
# [inline (always)]
pub const fn intr_enable_clear (& self) -> & IntrEnableClear { & self . intr_enable_clear } # [doc = "0x30 - EOI Register"]
# [inline (always)]
pub const fn intc_eoi (& self) -> & IntcEoi { & self . intc_eoi } # [doc = "0x34 - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved7 (& self) -> & MssQspiReserved7 { & self . mss_qspi_reserved7 } # [doc = "0x38 - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved8 (& self) -> & MssQspiReserved8 { & self . mss_qspi_reserved8 } # [doc = "0x3c - Reserved"]
# [inline (always)]
pub const fn mss_qspi_reserved9 (& self) -> & MssQspiReserved9 { & self . mss_qspi_reserved9 } # [doc = "0x40 - SPI Clock Control Register (SPICC)"]
# [inline (always)]
pub const fn spi_clock_cntrl (& self) -> & SpiClockCntrl { & self . spi_clock_cntrl } # [doc = "0x44 - SPI Data Control Register (SPIDC)"]
# [inline (always)]
pub const fn spi_dc (& self) -> & SpiDc { & self . spi_dc } # [doc = "0x48 - SPI Command Register (SPICR)"]
# [inline (always)]
pub const fn spi_cmd (& self) -> & SpiCmd { & self . spi_cmd } # [doc = "0x4c - SPI Status Register (SPISR)"]
# [inline (always)]
pub const fn spi_status (& self) -> & SpiStatus { & self . spi_status } # [doc = "0x50 - SPI Data Register (SPIDR)"]
# [inline (always)]
pub const fn spi_data (& self) -> & SpiData { & self . spi_data } # [doc = "0x54 - Memory Mapped SPI Setup0 Register"]
# [inline (always)]
pub const fn spi_setup0 (& self) -> & SpiSetup0 { & self . spi_setup0 } # [doc = "0x58 - Memory Mapped SPI Setup1 Register"]
# [inline (always)]
pub const fn spi_setup1 (& self) -> & SpiSetup1 { & self . spi_setup1 } # [doc = "0x5c - Memory Mapped SPI Setup2 Register"]
# [inline (always)]
pub const fn spi_setup2 (& self) -> & SpiSetup2 { & self . spi_setup2 } # [doc = "0x60 - Memory Mapped SPI Setup3 Register"]
# [inline (always)]
pub const fn spi_setup3 (& self) -> & SpiSetup3 { & self . spi_setup3 } # [doc = "0x64 - Memory Mapped SPI Switch Register"]
# [inline (always)]
pub const fn spi_switch (& self) -> & SpiSwitch { & self . spi_switch } # [doc = "0x68 - SPI Data Register (SPIDR1)"]
# [inline (always)]
pub const fn spi_data1 (& self) -> & SpiData1 { & self . spi_data1 } # [doc = "0x6c - SPI Data Register (SPIDR2)"]
# [inline (always)]
pub const fn spi_data2 (& self) -> & SpiData2 { & self . spi_data2 } # [doc = "0x70 - SPI Data Register (SPIDR3)"]
# [inline (always)]
pub const fn spi_data3 (& self) -> & SpiData3 { & self . spi_data3 } } # [doc = "PID (rw) register accessor: PID\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pid`]
module"]
# [doc (alias = "PID")]
pub type Pid = crate :: Reg < pid :: PidSpec > ; # [doc = "PID"]
pub mod pid { # [doc = "Register `PID` reader"]
pub type R = crate :: R < PidSpec > ; # [doc = "Register `PID` writer"]
pub type W = crate :: W < PidSpec > ; # [doc = "Field `MINOR` reader - 5:0\\]
Minor Release Number"]
pub type MinorR = crate :: FieldReader ; # [doc = "Field `MINOR` writer - 5:0\\]
Minor Release Number"]
pub type MinorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `CUSTOM` reader - 7:6\\]
Custom IP"]
pub type CustomR = crate :: FieldReader ; # [doc = "Field `CUSTOM` writer - 7:6\\]
Custom IP"]
pub type CustomW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAJOR` reader - 10:8\\]
Major Release Number"]
pub type MajorR = crate :: FieldReader ; # [doc = "Field `MAJOR` writer - 10:8\\]
Major Release Number"]
pub type MajorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `RTL` reader - 15:11\\]
RTL Release Version The PDR release number of this IP"]
pub type RtlR = crate :: FieldReader ; # [doc = "Field `RTL` writer - 15:11\\]
RTL Release Version The PDR release number of this IP"]
pub type RtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `FUNC` reader - 27:16\\]
The function of the module being used"]
pub type FuncR = crate :: FieldReader < u16 > ; # [doc = "Field `FUNC` writer - 27:16\\]
The function of the module being used"]
pub type FuncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `SCHEME` reader - 31:30\\]
The scheme of the register used. This indicates the PDR3.5 Method"]
pub type SchemeR = crate :: FieldReader ; # [doc = "Field `SCHEME` writer - 31:30\\]
The scheme of the register used. This indicates the PDR3.5 Method"]
pub type SchemeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:5 - 5:0\\]
Minor Release Number"]
# [inline (always)]
pub fn minor (& self) -> MinorR { MinorR :: new ((self . bits & 0x3f) as u8) } # [doc = "Bits 6:7 - 7:6\\]
Custom IP"]
# [inline (always)]
pub fn custom (& self) -> CustomR { CustomR :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:10 - 10:8\\]
Major Release Number"]
# [inline (always)]
pub fn major (& self) -> MajorR { MajorR :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Release Version The PDR release number of this IP"]
# [inline (always)]
pub fn rtl (& self) -> RtlR { RtlR :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:27 - 27:16\\]
The function of the module being used"]
# [inline (always)]
pub fn func (& self) -> FuncR { FuncR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 30:31 - 31:30\\]
The scheme of the register used. This indicates the PDR3.5 Method"]
# [inline (always)]
pub fn scheme (& self) -> SchemeR { SchemeR :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:5 - 5:0\\]
Minor Release Number"]
# [inline (always)]
# [must_use]
pub fn minor (& mut self) -> MinorW < PidSpec > { MinorW :: new (self , 0) } # [doc = "Bits 6:7 - 7:6\\]
Custom IP"]
# [inline (always)]
# [must_use]
pub fn custom (& mut self) -> CustomW < PidSpec > { CustomW :: new (self , 6) } # [doc = "Bits 8:10 - 10:8\\]
Major Release Number"]
# [inline (always)]
# [must_use]
pub fn major (& mut self) -> MajorW < PidSpec > { MajorW :: new (self , 8) } # [doc = "Bits 11:15 - 15:11\\]
RTL Release Version The PDR release number of this IP"]
# [inline (always)]
# [must_use]
pub fn rtl (& mut self) -> RtlW < PidSpec > { RtlW :: new (self , 11) } # [doc = "Bits 16:27 - 27:16\\]
The function of the module being used"]
# [inline (always)]
# [must_use]
pub fn func (& mut self) -> FuncW < PidSpec > { FuncW :: new (self , 16) } # [doc = "Bits 30:31 - 31:30\\]
The scheme of the register used. This indicates the PDR3.5 Method"]
# [inline (always)]
# [must_use]
pub fn scheme (& mut self) -> SchemeW < PidSpec > { SchemeW :: new (self , 30) } } # [doc = "PID\n\nYou can [`read`](crate::Reg::read) this register and get [`pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PidSpec ; impl crate :: RegisterSpec for PidSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`pid::R`](R) reader structure"]
impl crate :: Readable for PidSpec { } # [doc = "`write(|w| ..)` method takes [`pid::W`](W) writer structure"]
impl crate :: Writable for PidSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PID to value 0"]
impl crate :: Resettable for PidSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved1`]
module"]
# [doc (alias = "MSS_QSPI_Reserved1")]
pub type MssQspiReserved1 = crate :: Reg < mss_qspi_reserved1 :: MssQspiReserved1Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved1 { # [doc = "Register `MSS_QSPI_Reserved1` reader"]
pub type R = crate :: R < MssQspiReserved1Spec > ; # [doc = "Register `MSS_QSPI_Reserved1` writer"]
pub type W = crate :: W < MssQspiReserved1Spec > ; # [doc = "Field `Reserved_1` reader - 31:0\\]
Reserved"]
pub type Reserved1R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_1` writer - 31:0\\]
Reserved"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_1 (& self) -> Reserved1R { Reserved1R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_1 (& mut self) -> Reserved1W < MssQspiReserved1Spec > { Reserved1W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved1Spec ; impl crate :: RegisterSpec for MssQspiReserved1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved1::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved1Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved1::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved1 to value 0"]
impl crate :: Resettable for MssQspiReserved1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved2`]
module"]
# [doc (alias = "MSS_QSPI_Reserved2")]
pub type MssQspiReserved2 = crate :: Reg < mss_qspi_reserved2 :: MssQspiReserved2Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved2 { # [doc = "Register `MSS_QSPI_Reserved2` reader"]
pub type R = crate :: R < MssQspiReserved2Spec > ; # [doc = "Register `MSS_QSPI_Reserved2` writer"]
pub type W = crate :: W < MssQspiReserved2Spec > ; # [doc = "Field `Reserved_2` reader - 31:0\\]
Reserved"]
pub type Reserved2R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_2` writer - 31:0\\]
Reserved"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_2 (& self) -> Reserved2R { Reserved2R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_2 (& mut self) -> Reserved2W < MssQspiReserved2Spec > { Reserved2W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved2Spec ; impl crate :: RegisterSpec for MssQspiReserved2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved2::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved2Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved2::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved2 to value 0"]
impl crate :: Resettable for MssQspiReserved2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved3`]
module"]
# [doc (alias = "MSS_QSPI_Reserved3")]
pub type MssQspiReserved3 = crate :: Reg < mss_qspi_reserved3 :: MssQspiReserved3Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved3 { # [doc = "Register `MSS_QSPI_Reserved3` reader"]
pub type R = crate :: R < MssQspiReserved3Spec > ; # [doc = "Register `MSS_QSPI_Reserved3` writer"]
pub type W = crate :: W < MssQspiReserved3Spec > ; # [doc = "Field `Reserved_3` reader - 31:0\\]
Reserved"]
pub type Reserved3R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_3` writer - 31:0\\]
Reserved"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_3 (& self) -> Reserved3R { Reserved3R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_3 (& mut self) -> Reserved3W < MssQspiReserved3Spec > { Reserved3W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved3Spec ; impl crate :: RegisterSpec for MssQspiReserved3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved3::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved3Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved3::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved3 to value 0"]
impl crate :: Resettable for MssQspiReserved3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SYSCONFIG (rw) register accessor: SYSCONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`sysconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysconfig`]
module"]
# [doc (alias = "SYSCONFIG")]
pub type Sysconfig = crate :: Reg < sysconfig :: SysconfigSpec > ; # [doc = "SYSCONFIG"]
pub mod sysconfig { # [doc = "Register `SYSCONFIG` reader"]
pub type R = crate :: R < SysconfigSpec > ; # [doc = "Register `SYSCONFIG` writer"]
pub type W = crate :: W < SysconfigSpec > ; # [doc = "Field `Reserved1` reader - 1:0\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 1:0\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IDLEMODE` reader - 3:2\\]
Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module \"swakeup\" output(s) is (are) implemented"]
pub type IdlemodeR = crate :: FieldReader ; # [doc = "Field `IDLEMODE` writer - 3:2\\]
Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module \"swakeup\" output(s) is (are) implemented"]
pub type IdlemodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved2` reader - 5:4\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 5:4\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved3` reader - 31:6\\]
Always read as 0"]
pub type Reserved3R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved3` writer - 31:6\\]
Always read as 0"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 26 , u32 > ; impl R { # [doc = "Bits 0:1 - 1:0\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - 3:2\\]
Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module \"swakeup\" output(s) is (are) implemented"]
# [inline (always)]
pub fn idlemode (& self) -> IdlemodeR { IdlemodeR :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - 5:4\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:31 - 31:6\\]
Always read as 0"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new ((self . bits >> 6) & 0x03ff_ffff) } } impl W { # [doc = "Bits 0:1 - 1:0\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SysconfigSpec > { Reserved1W :: new (self , 0) } # [doc = "Bits 2:3 - 3:2\\]
Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module \"swakeup\" output(s) is (are) implemented"]
# [inline (always)]
# [must_use]
pub fn idlemode (& mut self) -> IdlemodeW < SysconfigSpec > { IdlemodeW :: new (self , 2) } # [doc = "Bits 4:5 - 5:4\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SysconfigSpec > { Reserved2W :: new (self , 4) } # [doc = "Bits 6:31 - 31:6\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SysconfigSpec > { Reserved3W :: new (self , 6) } } # [doc = "SYSCONFIG\n\nYou can [`read`](crate::Reg::read) this register and get [`sysconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysconfigSpec ; impl crate :: RegisterSpec for SysconfigSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`sysconfig::R`](R) reader structure"]
impl crate :: Readable for SysconfigSpec { } # [doc = "`write(|w| ..)` method takes [`sysconfig::W`](W) writer structure"]
impl crate :: Writable for SysconfigSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SYSCONFIG to value 0"]
impl crate :: Resettable for SysconfigSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved4 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved4`]
module"]
# [doc (alias = "MSS_QSPI_Reserved4")]
pub type MssQspiReserved4 = crate :: Reg < mss_qspi_reserved4 :: MssQspiReserved4Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved4 { # [doc = "Register `MSS_QSPI_Reserved4` reader"]
pub type R = crate :: R < MssQspiReserved4Spec > ; # [doc = "Register `MSS_QSPI_Reserved4` writer"]
pub type W = crate :: W < MssQspiReserved4Spec > ; # [doc = "Field `Reserved_4` reader - 31:0\\]
Reserved"]
pub type Reserved4R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_4` writer - 31:0\\]
Reserved"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_4 (& self) -> Reserved4R { Reserved4R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_4 (& mut self) -> Reserved4W < MssQspiReserved4Spec > { Reserved4W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved4Spec ; impl crate :: RegisterSpec for MssQspiReserved4Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved4::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved4Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved4::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved4Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved4 to value 0"]
impl crate :: Resettable for MssQspiReserved4Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved5 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved5`]
module"]
# [doc (alias = "MSS_QSPI_Reserved5")]
pub type MssQspiReserved5 = crate :: Reg < mss_qspi_reserved5 :: MssQspiReserved5Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved5 { # [doc = "Register `MSS_QSPI_Reserved5` reader"]
pub type R = crate :: R < MssQspiReserved5Spec > ; # [doc = "Register `MSS_QSPI_Reserved5` writer"]
pub type W = crate :: W < MssQspiReserved5Spec > ; # [doc = "Field `Reserved_5` reader - 31:0\\]
Reserved"]
pub type Reserved5R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_5` writer - 31:0\\]
Reserved"]
pub type Reserved5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_5 (& self) -> Reserved5R { Reserved5R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_5 (& mut self) -> Reserved5W < MssQspiReserved5Spec > { Reserved5W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved5Spec ; impl crate :: RegisterSpec for MssQspiReserved5Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved5::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved5Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved5::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved5Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved5 to value 0"]
impl crate :: Resettable for MssQspiReserved5Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved6 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved6`]
module"]
# [doc (alias = "MSS_QSPI_Reserved6")]
pub type MssQspiReserved6 = crate :: Reg < mss_qspi_reserved6 :: MssQspiReserved6Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved6 { # [doc = "Register `MSS_QSPI_Reserved6` reader"]
pub type R = crate :: R < MssQspiReserved6Spec > ; # [doc = "Register `MSS_QSPI_Reserved6` writer"]
pub type W = crate :: W < MssQspiReserved6Spec > ; # [doc = "Field `Reserved_6` reader - 31:0\\]
Reserved"]
pub type Reserved6R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_6` writer - 31:0\\]
Reserved"]
pub type Reserved6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_6 (& self) -> Reserved6R { Reserved6R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_6 (& mut self) -> Reserved6W < MssQspiReserved6Spec > { Reserved6W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved6Spec ; impl crate :: RegisterSpec for MssQspiReserved6Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved6::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved6Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved6::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved6Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved6 to value 0"]
impl crate :: Resettable for MssQspiReserved6Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTR_STATUS_RAW_SET (rw) register accessor: INTR Interrupt Status Raw/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status_raw_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status_raw_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_raw_set`]
module"]
# [doc (alias = "INTR_STATUS_RAW_SET")]
pub type IntrStatusRawSet = crate :: Reg < intr_status_raw_set :: IntrStatusRawSetSpec > ; # [doc = "INTR Interrupt Status Raw/Set Register"]
pub mod intr_status_raw_set { # [doc = "Register `INTR_STATUS_RAW_SET` reader"]
pub type R = crate :: R < IntrStatusRawSetSpec > ; # [doc = "Register `INTR_STATUS_RAW_SET` writer"]
pub type W = crate :: W < IntrStatusRawSetSpec > ; # [doc = "Field `FIRQ_RAW` reader - 0:0\\]
Frame Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
pub type FirqRawR = crate :: BitReader ; # [doc = "Field `FIRQ_RAW` writer - 0:0\\]
Frame Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
pub type FirqRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WIRQ_RAW` reader - 1:1\\]
Word Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
pub type WirqRawR = crate :: BitReader ; # [doc = "Field `WIRQ_RAW` writer - 1:1\\]
Word Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
pub type WirqRawW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
# [inline (always)]
pub fn firq_raw (& self) -> FirqRawR { FirqRawR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
# [inline (always)]
pub fn wirq_raw (& self) -> WirqRawR { WirqRawR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn firq_raw (& mut self) -> FirqRawW < IntrStatusRawSetSpec > { FirqRawW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn wirq_raw (& mut self) -> WirqRawW < IntrStatusRawSetSpec > { WirqRawW :: new (self , 1) } } # [doc = "INTR Interrupt Status Raw/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status_raw_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status_raw_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrStatusRawSetSpec ; impl crate :: RegisterSpec for IntrStatusRawSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_status_raw_set::R`](R) reader structure"]
impl crate :: Readable for IntrStatusRawSetSpec { } # [doc = "`write(|w| ..)` method takes [`intr_status_raw_set::W`](W) writer structure"]
impl crate :: Writable for IntrStatusRawSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTR_STATUS_RAW_SET to value 0"]
impl crate :: Resettable for IntrStatusRawSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTR_STATUS_ENABLED_CLEAR (rw) register accessor: INTR Interrupt Status Enabled/Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status_enabled_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status_enabled_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_enabled_clear`]
module"]
# [doc (alias = "INTR_STATUS_ENABLED_CLEAR")]
pub type IntrStatusEnabledClear = crate :: Reg < intr_status_enabled_clear :: IntrStatusEnabledClearSpec > ; # [doc = "INTR Interrupt Status Enabled/Clear Register"]
pub mod intr_status_enabled_clear { # [doc = "Register `INTR_STATUS_ENABLED_CLEAR` reader"]
pub type R = crate :: R < IntrStatusEnabledClearSpec > ; # [doc = "Register `INTR_STATUS_ENABLED_CLEAR` writer"]
pub type W = crate :: W < IntrStatusEnabledClearSpec > ; # [doc = "Field `FIRQ_ENA` reader - 0:0\\]
Frame Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
pub type FirqEnaR = crate :: BitReader ; # [doc = "Field `FIRQ_ENA` writer - 0:0\\]
Frame Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
pub type FirqEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WIRQ_ENA` reader - 1:1\\]
Word Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
pub type WirqEnaR = crate :: BitReader ; # [doc = "Field `WIRQ_ENA` writer - 1:1\\]
Word Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
pub type WirqEnaW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
# [inline (always)]
pub fn firq_ena (& self) -> FirqEnaR { FirqEnaR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
# [inline (always)]
pub fn wirq_ena (& self) -> WirqEnaR { WirqEnaR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn firq_ena (& mut self) -> FirqEnaW < IntrStatusEnabledClearSpec > { FirqEnaW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn wirq_ena (& mut self) -> WirqEnaW < IntrStatusEnabledClearSpec > { WirqEnaW :: new (self , 1) } } # [doc = "INTR Interrupt Status Enabled/Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status_enabled_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status_enabled_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrStatusEnabledClearSpec ; impl crate :: RegisterSpec for IntrStatusEnabledClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_status_enabled_clear::R`](R) reader structure"]
impl crate :: Readable for IntrStatusEnabledClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_status_enabled_clear::W`](W) writer structure"]
impl crate :: Writable for IntrStatusEnabledClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTR_STATUS_ENABLED_CLEAR to value 0"]
impl crate :: Resettable for IntrStatusEnabledClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTR_ENABLE_SET (rw) register accessor: INTR Interrupt Enable/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_set`]
module"]
# [doc (alias = "INTR_ENABLE_SET")]
pub type IntrEnableSet = crate :: Reg < intr_enable_set :: IntrEnableSetSpec > ; # [doc = "INTR Interrupt Enable/Set Register"]
pub mod intr_enable_set { # [doc = "Register `INTR_ENABLE_SET` reader"]
pub type R = crate :: R < IntrEnableSetSpec > ; # [doc = "Register `INTR_ENABLE_SET` writer"]
pub type W = crate :: W < IntrEnableSetSpec > ; # [doc = "Field `FIRQ_ENA_SET` reader - 0:0\\]
Frame Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
pub type FirqEnaSetR = crate :: BitReader ; # [doc = "Field `FIRQ_ENA_SET` writer - 0:0\\]
Frame Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
pub type FirqEnaSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WIRQ_ENA_SET` reader - 1:1\\]
Word Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
pub type WirqEnaSetR = crate :: BitReader ; # [doc = "Field `WIRQ_ENA_SET` writer - 1:1\\]
Word Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
pub type WirqEnaSetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
# [inline (always)]
pub fn firq_ena_set (& self) -> FirqEnaSetR { FirqEnaSetR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
# [inline (always)]
pub fn wirq_ena_set (& self) -> WirqEnaSetR { WirqEnaSetR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn firq_ena_set (& mut self) -> FirqEnaSetW < IntrEnableSetSpec > { FirqEnaSetW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn wirq_ena_set (& mut self) -> WirqEnaSetW < IntrEnableSetSpec > { WirqEnaSetW :: new (self , 1) } } # [doc = "INTR Interrupt Enable/Set Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableSetSpec ; impl crate :: RegisterSpec for IntrEnableSetSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_set::R`](R) reader structure"]
impl crate :: Readable for IntrEnableSetSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_set::W`](W) writer structure"]
impl crate :: Writable for IntrEnableSetSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTR_ENABLE_SET to value 0"]
impl crate :: Resettable for IntrEnableSetSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTR_ENABLE_CLEAR (rw) register accessor: INTR Interrupt Enable/Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_enable_clear`]
module"]
# [doc (alias = "INTR_ENABLE_CLEAR")]
pub type IntrEnableClear = crate :: Reg < intr_enable_clear :: IntrEnableClearSpec > ; # [doc = "INTR Interrupt Enable/Clear Register"]
pub mod intr_enable_clear { # [doc = "Register `INTR_ENABLE_CLEAR` reader"]
pub type R = crate :: R < IntrEnableClearSpec > ; # [doc = "Register `INTR_ENABLE_CLEAR` writer"]
pub type W = crate :: W < IntrEnableClearSpec > ; # [doc = "Field `FIRQ_ENA_CLR` reader - 0:0\\]
Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
pub type FirqEnaClrR = crate :: BitReader ; # [doc = "Field `FIRQ_ENA_CLR` writer - 0:0\\]
Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
pub type FirqEnaClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WIRQ_ENA_CLR` reader - 1:1\\]
Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
pub type WirqEnaClrR = crate :: BitReader ; # [doc = "Field `WIRQ_ENA_CLR` writer - 1:1\\]
Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
pub type WirqEnaClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
# [inline (always)]
pub fn firq_ena_clr (& self) -> FirqEnaClrR { FirqEnaClrR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
# [inline (always)]
pub fn wirq_ena_clr (& self) -> WirqEnaClrR { WirqEnaClrR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn firq_ena_clr (& mut self) -> FirqEnaClrW < IntrEnableClearSpec > { FirqEnaClrW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect"]
# [inline (always)]
# [must_use]
pub fn wirq_ena_clr (& mut self) -> WirqEnaClrW < IntrEnableClearSpec > { WirqEnaClrW :: new (self , 1) } } # [doc = "INTR Interrupt Enable/Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_enable_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_enable_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntrEnableClearSpec ; impl crate :: RegisterSpec for IntrEnableClearSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intr_enable_clear::R`](R) reader structure"]
impl crate :: Readable for IntrEnableClearSpec { } # [doc = "`write(|w| ..)` method takes [`intr_enable_clear::W`](W) writer structure"]
impl crate :: Writable for IntrEnableClearSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTR_ENABLE_CLEAR to value 0"]
impl crate :: Resettable for IntrEnableClearSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTC_EOI (rw) register accessor: EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intc_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intc_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intc_eoi`]
module"]
# [doc (alias = "INTC_EOI")]
pub type IntcEoi = crate :: Reg < intc_eoi :: IntcEoiSpec > ; # [doc = "EOI Register"]
pub mod intc_eoi { # [doc = "Register `INTC_EOI` reader"]
pub type R = crate :: R < IntcEoiSpec > ; # [doc = "Register `INTC_EOI` writer"]
pub type W = crate :: W < IntcEoiSpec > ; # [doc = "Field `EOI_VECTOR` reader - 31:0\\]
Number associated with the ipgenericirq for intr output. There are 1 interrupt outputs Write 0x0 : Write to intr IP Generic Any other write value is ignored."]
pub type EoiVectorR = crate :: FieldReader < u32 > ; # [doc = "Field `EOI_VECTOR` writer - 31:0\\]
Number associated with the ipgenericirq for intr output. There are 1 interrupt outputs Write 0x0 : Write to intr IP Generic Any other write value is ignored."]
pub type EoiVectorW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Number associated with the ipgenericirq for intr output. There are 1 interrupt outputs Write 0x0 : Write to intr IP Generic Any other write value is ignored."]
# [inline (always)]
pub fn eoi_vector (& self) -> EoiVectorR { EoiVectorR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Number associated with the ipgenericirq for intr output. There are 1 interrupt outputs Write 0x0 : Write to intr IP Generic Any other write value is ignored."]
# [inline (always)]
# [must_use]
pub fn eoi_vector (& mut self) -> EoiVectorW < IntcEoiSpec > { EoiVectorW :: new (self , 0) } } # [doc = "EOI Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intc_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intc_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntcEoiSpec ; impl crate :: RegisterSpec for IntcEoiSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`intc_eoi::R`](R) reader structure"]
impl crate :: Readable for IntcEoiSpec { } # [doc = "`write(|w| ..)` method takes [`intc_eoi::W`](W) writer structure"]
impl crate :: Writable for IntcEoiSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTC_EOI to value 0"]
impl crate :: Resettable for IntcEoiSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved7 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved7`]
module"]
# [doc (alias = "MSS_QSPI_Reserved7")]
pub type MssQspiReserved7 = crate :: Reg < mss_qspi_reserved7 :: MssQspiReserved7Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved7 { # [doc = "Register `MSS_QSPI_Reserved7` reader"]
pub type R = crate :: R < MssQspiReserved7Spec > ; # [doc = "Register `MSS_QSPI_Reserved7` writer"]
pub type W = crate :: W < MssQspiReserved7Spec > ; # [doc = "Field `Reserved_7` reader - 31:0\\]
Reserved"]
pub type Reserved7R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_7` writer - 31:0\\]
Reserved"]
pub type Reserved7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_7 (& self) -> Reserved7R { Reserved7R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_7 (& mut self) -> Reserved7W < MssQspiReserved7Spec > { Reserved7W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved7Spec ; impl crate :: RegisterSpec for MssQspiReserved7Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved7::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved7Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved7::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved7Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved7 to value 0"]
impl crate :: Resettable for MssQspiReserved7Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved8 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved8`]
module"]
# [doc (alias = "MSS_QSPI_Reserved8")]
pub type MssQspiReserved8 = crate :: Reg < mss_qspi_reserved8 :: MssQspiReserved8Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved8 { # [doc = "Register `MSS_QSPI_Reserved8` reader"]
pub type R = crate :: R < MssQspiReserved8Spec > ; # [doc = "Register `MSS_QSPI_Reserved8` writer"]
pub type W = crate :: W < MssQspiReserved8Spec > ; # [doc = "Field `Reserved_8` reader - 31:0\\]
Reserved"]
pub type Reserved8R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_8` writer - 31:0\\]
Reserved"]
pub type Reserved8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_8 (& self) -> Reserved8R { Reserved8R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_8 (& mut self) -> Reserved8W < MssQspiReserved8Spec > { Reserved8W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved8Spec ; impl crate :: RegisterSpec for MssQspiReserved8Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved8::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved8Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved8::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved8Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved8 to value 0"]
impl crate :: Resettable for MssQspiReserved8Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "MSS_QSPI_Reserved9 (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mss_qspi_reserved9`]
module"]
# [doc (alias = "MSS_QSPI_Reserved9")]
pub type MssQspiReserved9 = crate :: Reg < mss_qspi_reserved9 :: MssQspiReserved9Spec > ; # [doc = "Reserved"]
pub mod mss_qspi_reserved9 { # [doc = "Register `MSS_QSPI_Reserved9` reader"]
pub type R = crate :: R < MssQspiReserved9Spec > ; # [doc = "Register `MSS_QSPI_Reserved9` writer"]
pub type W = crate :: W < MssQspiReserved9Spec > ; # [doc = "Field `Reserved_9` reader - 31:0\\]
Reserved"]
pub type Reserved9R = crate :: FieldReader < u32 > ; # [doc = "Field `Reserved_9` writer - 31:0\\]
Reserved"]
pub type Reserved9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
pub fn reserved_9 (& self) -> Reserved9R { Reserved9R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Reserved"]
# [inline (always)]
# [must_use]
pub fn reserved_9 (& mut self) -> Reserved9W < MssQspiReserved9Spec > { Reserved9W :: new (self , 0) } } # [doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_qspi_reserved9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_qspi_reserved9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MssQspiReserved9Spec ; impl crate :: RegisterSpec for MssQspiReserved9Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`mss_qspi_reserved9::R`](R) reader structure"]
impl crate :: Readable for MssQspiReserved9Spec { } # [doc = "`write(|w| ..)` method takes [`mss_qspi_reserved9::W`](W) writer structure"]
impl crate :: Writable for MssQspiReserved9Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MSS_QSPI_Reserved9 to value 0"]
impl crate :: Resettable for MssQspiReserved9Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_CLOCK_CNTRL (rw) register accessor: SPI Clock Control Register (SPICC)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_clock_cntrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_clock_cntrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clock_cntrl`]
module"]
# [doc (alias = "SPI_CLOCK_CNTRL")]
pub type SpiClockCntrl = crate :: Reg < spi_clock_cntrl :: SpiClockCntrlSpec > ; # [doc = "SPI Clock Control Register (SPICC)"]
pub mod spi_clock_cntrl { # [doc = "Register `SPI_CLOCK_CNTRL` reader"]
pub type R = crate :: R < SpiClockCntrlSpec > ; # [doc = "Register `SPI_CLOCK_CNTRL` writer"]
pub type W = crate :: W < SpiClockCntrlSpec > ; # [doc = "Field `DCLK_DIV` reader - 15:0\\]
Serial data clock divide by ratio"]
pub type DclkDivR = crate :: FieldReader < u16 > ; # [doc = "Field `DCLK_DIV` writer - 15:0\\]
Serial data clock divide by ratio"]
pub type DclkDivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; # [doc = "Field `CLKEN` reader - 31:31\\]
Clock Enable. 0- Data clock is turned off 1- Data clock is enabled"]
pub type ClkenR = crate :: BitReader ; # [doc = "Field `CLKEN` writer - 31:31\\]
Clock Enable. 0- Data clock is turned off 1- Data clock is enabled"]
pub type ClkenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:15 - 15:0\\]
Serial data clock divide by ratio"]
# [inline (always)]
pub fn dclk_div (& self) -> DclkDivR { DclkDivR :: new ((self . bits & 0xffff) as u16) } # [doc = "Bit 31 - 31:31\\]
Clock Enable. 0- Data clock is turned off 1- Data clock is enabled"]
# [inline (always)]
pub fn clken (& self) -> ClkenR { ClkenR :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:15 - 15:0\\]
Serial data clock divide by ratio"]
# [inline (always)]
# [must_use]
pub fn dclk_div (& mut self) -> DclkDivW < SpiClockCntrlSpec > { DclkDivW :: new (self , 0) } # [doc = "Bit 31 - 31:31\\]
Clock Enable. 0- Data clock is turned off 1- Data clock is enabled"]
# [inline (always)]
# [must_use]
pub fn clken (& mut self) -> ClkenW < SpiClockCntrlSpec > { ClkenW :: new (self , 31) } } # [doc = "SPI Clock Control Register (SPICC)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_clock_cntrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_clock_cntrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiClockCntrlSpec ; impl crate :: RegisterSpec for SpiClockCntrlSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_clock_cntrl::R`](R) reader structure"]
impl crate :: Readable for SpiClockCntrlSpec { } # [doc = "`write(|w| ..)` method takes [`spi_clock_cntrl::W`](W) writer structure"]
impl crate :: Writable for SpiClockCntrlSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_CLOCK_CNTRL to value 0"]
impl crate :: Resettable for SpiClockCntrlSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_DC (rw) register accessor: SPI Data Control Register (SPIDC)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dc`]
module"]
# [doc (alias = "SPI_DC")]
pub type SpiDc = crate :: Reg < spi_dc :: SpiDcSpec > ; # [doc = "SPI Data Control Register (SPIDC)"]
pub mod spi_dc { # [doc = "Register `SPI_DC` reader"]
pub type R = crate :: R < SpiDcSpec > ; # [doc = "Register `SPI_DC` writer"]
pub type W = crate :: W < SpiDcSpec > ; # [doc = "Field `CKP0` reader - 0:0\\]
Clock polarity for chip select 0 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp0R = crate :: BitReader ; # [doc = "Field `CKP0` writer - 0:0\\]
Clock polarity for chip select 0 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSP0` reader - 1:1\\]
Chip select polarity for chip select 0 0- Active low 1- Active high"]
pub type Csp0R = crate :: BitReader ; # [doc = "Field `CSP0` writer - 1:1\\]
Chip select polarity for chip select 0 0- Active low 1- Active high"]
pub type Csp0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CKPH0` reader - 2:2\\]
Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph0R = crate :: BitReader ; # [doc = "Field `CKPH0` writer - 2:2\\]
Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DD0` reader - 4:3\\]
Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd0R = crate :: FieldReader ; # [doc = "Field `DD0` writer - 4:3\\]
Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 7:5\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 7:5\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CKP1` reader - 8:8\\]
Clock polarity for chip select 1 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp1R = crate :: BitReader ; # [doc = "Field `CKP1` writer - 8:8\\]
Clock polarity for chip select 1 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSP1` reader - 9:9\\]
Chip select polarity for chip select 1 0- Active low 1- Active high"]
pub type Csp1R = crate :: BitReader ; # [doc = "Field `CSP1` writer - 9:9\\]
Chip select polarity for chip select 1 0- Active low 1- Active high"]
pub type Csp1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CKPH1` reader - 10:10\\]
Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph1R = crate :: BitReader ; # [doc = "Field `CKPH1` writer - 10:10\\]
Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DD1` reader - 12:11\\]
Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd1R = crate :: FieldReader ; # [doc = "Field `DD1` writer - 12:11\\]
Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved2` reader - 15:13\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 15:13\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CKP2` reader - 16:16\\]
Clock polarity for chip select 2 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp2R = crate :: BitReader ; # [doc = "Field `CKP2` writer - 16:16\\]
Clock polarity for chip select 2 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSP2` reader - 17:17\\]
Chip select polarity for chip select 2 0- Active low 1- Active high"]
pub type Csp2R = crate :: BitReader ; # [doc = "Field `CSP2` writer - 17:17\\]
Chip select polarity for chip select 2 0- Active low 1- Active high"]
pub type Csp2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CKPH2` reader - 18:18\\]
Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph2R = crate :: BitReader ; # [doc = "Field `CKPH2` writer - 18:18\\]
Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DD2` reader - 20:19\\]
Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd2R = crate :: FieldReader ; # [doc = "Field `DD2` writer - 20:19\\]
Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved3` reader - 23:21\\]
Always read as 0"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 23:21\\]
Always read as 0"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `CKP3` reader - 24:24\\]
Clock polarity for chip select 3 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp3R = crate :: BitReader ; # [doc = "Field `CKP3` writer - 24:24\\]
Clock polarity for chip select 3 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
pub type Ckp3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSP3` reader - 25:25\\]
Chip select polarity for chip select 3 0- Active low 1- Active high"]
pub type Csp3R = crate :: BitReader ; # [doc = "Field `CSP3` writer - 25:25\\]
Chip select polarity for chip select 3 0- Active low 1- Active high"]
pub type Csp3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CKPH3` reader - 26:26\\]
Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph3R = crate :: BitReader ; # [doc = "Field `CKPH3` writer - 26:26\\]
Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
pub type Ckph3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DD3` reader - 28:27\\]
Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd3R = crate :: FieldReader ; # [doc = "Field `DD3` writer - 28:27\\]
Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
pub type Dd3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved4` reader - 31:29\\]
Always read as 0"]
pub type Reserved4R = crate :: FieldReader ; # [doc = "Field `Reserved4` writer - 31:29\\]
Always read as 0"]
pub type Reserved4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Clock polarity for chip select 0 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
pub fn ckp0 (& self) -> Ckp0R { Ckp0R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Chip select polarity for chip select 0 0- Active low 1- Active high"]
# [inline (always)]
pub fn csp0 (& self) -> Csp0R { Csp0R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
pub fn ckph0 (& self) -> Ckph0R { Ckph0R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:4 - 4:3\\]
Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
pub fn dd0 (& self) -> Dd0R { Dd0R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 5:7 - 7:5\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bit 8 - 8:8\\]
Clock polarity for chip select 1 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
pub fn ckp1 (& self) -> Ckp1R { Ckp1R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - 9:9\\]
Chip select polarity for chip select 1 0- Active low 1- Active high"]
# [inline (always)]
pub fn csp1 (& self) -> Csp1R { Csp1R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - 10:10\\]
Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
pub fn ckph1 (& self) -> Ckph1R { Ckph1R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:12 - 12:11\\]
Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
pub fn dd1 (& self) -> Dd1R { Dd1R :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bits 13:15 - 15:13\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bit 16 - 16:16\\]
Clock polarity for chip select 2 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
pub fn ckp2 (& self) -> Ckp2R { Ckp2R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - 17:17\\]
Chip select polarity for chip select 2 0- Active low 1- Active high"]
# [inline (always)]
pub fn csp2 (& self) -> Csp2R { Csp2R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - 18:18\\]
Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
pub fn ckph2 (& self) -> Ckph2R { Ckph2R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:20 - 20:19\\]
Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
pub fn dd2 (& self) -> Dd2R { Dd2R :: new (((self . bits >> 19) & 3) as u8) } # [doc = "Bits 21:23 - 23:21\\]
Always read as 0"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bit 24 - 24:24\\]
Clock polarity for chip select 3 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
pub fn ckp3 (& self) -> Ckp3R { Ckp3R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - 25:25\\]
Chip select polarity for chip select 3 0- Active low 1- Active high"]
# [inline (always)]
pub fn csp3 (& self) -> Csp3R { Csp3R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - 26:26\\]
Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
pub fn ckph3 (& self) -> Ckph3R { Ckph3R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bits 27:28 - 28:27\\]
Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
pub fn dd3 (& self) -> Dd3R { Dd3R :: new (((self . bits >> 27) & 3) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
pub fn reserved4 (& self) -> Reserved4R { Reserved4R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Clock polarity for chip select 0 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
# [must_use]
pub fn ckp0 (& mut self) -> Ckp0W < SpiDcSpec > { Ckp0W :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Chip select polarity for chip select 0 0- Active low 1- Active high"]
# [inline (always)]
# [must_use]
pub fn csp0 (& mut self) -> Csp0W < SpiDcSpec > { Csp0W :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
# [must_use]
pub fn ckph0 (& mut self) -> Ckph0W < SpiDcSpec > { Ckph0W :: new (self , 2) } # [doc = "Bits 3:4 - 4:3\\]
Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
# [must_use]
pub fn dd0 (& mut self) -> Dd0W < SpiDcSpec > { Dd0W :: new (self , 3) } # [doc = "Bits 5:7 - 7:5\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiDcSpec > { Reserved1W :: new (self , 5) } # [doc = "Bit 8 - 8:8\\]
Clock polarity for chip select 1 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
# [must_use]
pub fn ckp1 (& mut self) -> Ckp1W < SpiDcSpec > { Ckp1W :: new (self , 8) } # [doc = "Bit 9 - 9:9\\]
Chip select polarity for chip select 1 0- Active low 1- Active high"]
# [inline (always)]
# [must_use]
pub fn csp1 (& mut self) -> Csp1W < SpiDcSpec > { Csp1W :: new (self , 9) } # [doc = "Bit 10 - 10:10\\]
Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
# [must_use]
pub fn ckph1 (& mut self) -> Ckph1W < SpiDcSpec > { Ckph1W :: new (self , 10) } # [doc = "Bits 11:12 - 12:11\\]
Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
# [must_use]
pub fn dd1 (& mut self) -> Dd1W < SpiDcSpec > { Dd1W :: new (self , 11) } # [doc = "Bits 13:15 - 15:13\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiDcSpec > { Reserved2W :: new (self , 13) } # [doc = "Bit 16 - 16:16\\]
Clock polarity for chip select 2 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
# [must_use]
pub fn ckp2 (& mut self) -> Ckp2W < SpiDcSpec > { Ckp2W :: new (self , 16) } # [doc = "Bit 17 - 17:17\\]
Chip select polarity for chip select 2 0- Active low 1- Active high"]
# [inline (always)]
# [must_use]
pub fn csp2 (& mut self) -> Csp2W < SpiDcSpec > { Csp2W :: new (self , 17) } # [doc = "Bit 18 - 18:18\\]
Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
# [must_use]
pub fn ckph2 (& mut self) -> Ckph2W < SpiDcSpec > { Ckph2W :: new (self , 18) } # [doc = "Bits 19:20 - 20:19\\]
Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
# [must_use]
pub fn dd2 (& mut self) -> Dd2W < SpiDcSpec > { Dd2W :: new (self , 19) } # [doc = "Bits 21:23 - 23:21\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SpiDcSpec > { Reserved3W :: new (self , 21) } # [doc = "Bit 24 - 24:24\\]
Clock polarity for chip select 3 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1"]
# [inline (always)]
# [must_use]
pub fn ckp3 (& mut self) -> Ckp3W < SpiDcSpec > { Ckp3W :: new (self , 24) } # [doc = "Bit 25 - 25:25\\]
Chip select polarity for chip select 3 0- Active low 1- Active high"]
# [inline (always)]
# [must_use]
pub fn csp3 (& mut self) -> Csp3W < SpiDcSpec > { Csp3W :: new (self , 25) } # [doc = "Bit 26 - 26:26\\]
Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge"]
# [inline (always)]
# [must_use]
pub fn ckph3 (& mut self) -> Ckph3W < SpiDcSpec > { Ckph3W :: new (self , 26) } # [doc = "Bits 27:28 - 28:27\\]
Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active"]
# [inline (always)]
# [must_use]
pub fn dd3 (& mut self) -> Dd3W < SpiDcSpec > { Dd3W :: new (self , 27) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved4 (& mut self) -> Reserved4W < SpiDcSpec > { Reserved4W :: new (self , 29) } } # [doc = "SPI Data Control Register (SPIDC)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiDcSpec ; impl crate :: RegisterSpec for SpiDcSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_dc::R`](R) reader structure"]
impl crate :: Readable for SpiDcSpec { } # [doc = "`write(|w| ..)` method takes [`spi_dc::W`](W) writer structure"]
impl crate :: Writable for SpiDcSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_DC to value 0"]
impl crate :: Resettable for SpiDcSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_CMD (rw) register accessor: SPI Command Register (SPICR)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cmd`]
module"]
# [doc (alias = "SPI_CMD")]
pub type SpiCmd = crate :: Reg < spi_cmd :: SpiCmdSpec > ; # [doc = "SPI Command Register (SPICR)"]
pub mod spi_cmd { # [doc = "Register `SPI_CMD` reader"]
pub type R = crate :: R < SpiCmdSpec > ; # [doc = "Register `SPI_CMD` writer"]
pub type W = crate :: W < SpiCmdSpec > ; # [doc = "Field `FLEN` reader - 11:0\\]
Frame Length 0- 1 word 1- 2 words … 4095 – 4096 words"]
pub type FlenR = crate :: FieldReader < u16 > ; # [doc = "Field `FLEN` writer - 11:0\\]
Frame Length 0- 1 word 1- 2 words … 4095 – 4096 words"]
pub type FlenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `Reserved1` reader - 13:12\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 13:12\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WIRQ` reader - 14:14\\]
Word count interrupt enable"]
pub type WirqR = crate :: BitReader ; # [doc = "Field `WIRQ` writer - 14:14\\]
Word count interrupt enable"]
pub type WirqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FIRQ` reader - 15:15\\]
Frame count interrupt enable"]
pub type FirqR = crate :: BitReader ; # [doc = "Field `FIRQ` writer - 15:15\\]
Frame count interrupt enable"]
pub type FirqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CMD` reader - 18:16\\]
Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 ΓÇô Reserved 101 ΓÇô 3 pin Read Single 110 ΓÇô 3 pin Write Single 111 ΓÇô 6 pin Read Quad"]
pub type CmdR = crate :: FieldReader ; # [doc = "Field `CMD` writer - 18:16\\]
Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 ΓÇô Reserved 101 ΓÇô 3 pin Read Single 110 ΓÇô 3 pin Write Single 111 ΓÇô 6 pin Read Quad"]
pub type CmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `WLEN` reader - 25:19\\]
Word length. Sets the size of the individual transfers from 1 – 128 bits 0- 1 bit 1- 2 bits … 127 – 128 bits"]
pub type WlenR = crate :: FieldReader ; # [doc = "Field `WLEN` writer - 25:19\\]
Word length. Sets the size of the individual transfers from 1 – 128 bits 0- 1 bit 1- 2 bits … 127 – 128 bits"]
pub type WlenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `Reserved2` reader - 27:26\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 27:26\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CSNUM` reader - 29:28\\]
Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active"]
pub type CsnumR = crate :: FieldReader ; # [doc = "Field `CSNUM` writer - 29:28\\]
Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active"]
pub type CsnumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved3` reader - 31:30\\]
Always read as 0"]
pub type Reserved3R = crate :: FieldReader ; # [doc = "Field `Reserved3` writer - 31:30\\]
Always read as 0"]
pub type Reserved3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:11 - 11:0\\]
Frame Length 0- 1 word 1- 2 words … 4095 – 4096 words"]
# [inline (always)]
pub fn flen (& self) -> FlenR { FlenR :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 12:13 - 13:12\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - 14:14\\]
Word count interrupt enable"]
# [inline (always)]
pub fn wirq (& self) -> WirqR { WirqR :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - 15:15\\]
Frame count interrupt enable"]
# [inline (always)]
pub fn firq (& self) -> FirqR { FirqR :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - 18:16\\]
Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 ΓÇô Reserved 101 ΓÇô 3 pin Read Single 110 ΓÇô 3 pin Write Single 111 ΓÇô 6 pin Read Quad"]
# [inline (always)]
pub fn cmd (& self) -> CmdR { CmdR :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bits 19:25 - 25:19\\]
Word length. Sets the size of the individual transfers from 1 – 128 bits 0- 1 bit 1- 2 bits … 127 – 128 bits"]
# [inline (always)]
pub fn wlen (& self) -> WlenR { WlenR :: new (((self . bits >> 19) & 0x7f) as u8) } # [doc = "Bits 26:27 - 27:26\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - 29:28\\]
Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active"]
# [inline (always)]
pub fn csnum (& self) -> CsnumR { CsnumR :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - 31:30\\]
Always read as 0"]
# [inline (always)]
pub fn reserved3 (& self) -> Reserved3R { Reserved3R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:11 - 11:0\\]
Frame Length 0- 1 word 1- 2 words … 4095 – 4096 words"]
# [inline (always)]
# [must_use]
pub fn flen (& mut self) -> FlenW < SpiCmdSpec > { FlenW :: new (self , 0) } # [doc = "Bits 12:13 - 13:12\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiCmdSpec > { Reserved1W :: new (self , 12) } # [doc = "Bit 14 - 14:14\\]
Word count interrupt enable"]
# [inline (always)]
# [must_use]
pub fn wirq (& mut self) -> WirqW < SpiCmdSpec > { WirqW :: new (self , 14) } # [doc = "Bit 15 - 15:15\\]
Frame count interrupt enable"]
# [inline (always)]
# [must_use]
pub fn firq (& mut self) -> FirqW < SpiCmdSpec > { FirqW :: new (self , 15) } # [doc = "Bits 16:18 - 18:16\\]
Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 ΓÇô Reserved 101 ΓÇô 3 pin Read Single 110 ΓÇô 3 pin Write Single 111 ΓÇô 6 pin Read Quad"]
# [inline (always)]
# [must_use]
pub fn cmd (& mut self) -> CmdW < SpiCmdSpec > { CmdW :: new (self , 16) } # [doc = "Bits 19:25 - 25:19\\]
Word length. Sets the size of the individual transfers from 1 – 128 bits 0- 1 bit 1- 2 bits … 127 – 128 bits"]
# [inline (always)]
# [must_use]
pub fn wlen (& mut self) -> WlenW < SpiCmdSpec > { WlenW :: new (self , 19) } # [doc = "Bits 26:27 - 27:26\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiCmdSpec > { Reserved2W :: new (self , 26) } # [doc = "Bits 28:29 - 29:28\\]
Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active"]
# [inline (always)]
# [must_use]
pub fn csnum (& mut self) -> CsnumW < SpiCmdSpec > { CsnumW :: new (self , 28) } # [doc = "Bits 30:31 - 31:30\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved3 (& mut self) -> Reserved3W < SpiCmdSpec > { Reserved3W :: new (self , 30) } } # [doc = "SPI Command Register (SPICR)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiCmdSpec ; impl crate :: RegisterSpec for SpiCmdSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_cmd::R`](R) reader structure"]
impl crate :: Readable for SpiCmdSpec { } # [doc = "`write(|w| ..)` method takes [`spi_cmd::W`](W) writer structure"]
impl crate :: Writable for SpiCmdSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_CMD to value 0"]
impl crate :: Resettable for SpiCmdSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_STATUS (rw) register accessor: SPI Status Register (SPISR)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_status`]
module"]
# [doc (alias = "SPI_STATUS")]
pub type SpiStatus = crate :: Reg < spi_status :: SpiStatusSpec > ; # [doc = "SPI Status Register (SPISR)"]
pub mod spi_status { # [doc = "Register `SPI_STATUS` reader"]
pub type R = crate :: R < SpiStatusSpec > ; # [doc = "Register `SPI_STATUS` writer"]
pub type W = crate :: W < SpiStatusSpec > ; # [doc = "Field `BUSY` reader - 0:0\\]
Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words, the bit will clear to signal that it is ok to read/write the data registers. 0- Idle 1- Busy"]
pub type BusyR = crate :: BitReader ; # [doc = "Field `BUSY` writer - 0:0\\]
Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words, the bit will clear to signal that it is ok to read/write the data registers. 0- Idle 1- Busy"]
pub type BusyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WC` reader - 1:1\\]
Word complete. This bit is set after each word transfer is completed. 0- Word transfer is not complete 1- Word transfer is complete This bit is reset when the SPI Status Register is read"]
pub type WcR = crate :: BitReader ; # [doc = "Field `WC` writer - 1:1\\]
Word complete. This bit is set after each word transfer is completed. 0- Word transfer is not complete 1- Word transfer is complete This bit is reset when the SPI Status Register is read"]
pub type WcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FC` reader - 2:2\\]
Frame complete. This bit is set after all of the requested words have been transmitted. 0- Transfer is not complete 1- Transfer is complete This bit is reset when the SPI Status Register is read"]
pub type FcR = crate :: BitReader ; # [doc = "Field `FC` writer - 2:2\\]
Frame complete. This bit is set after all of the requested words have been transmitted. 0- Transfer is not complete 1- Transfer is complete This bit is reset when the SPI Status Register is read"]
pub type FcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `Reserved1` reader - 15:3\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader < u16 > ; # [doc = "Field `Reserved1` writer - 15:3\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; # [doc = "Field `WDCNT` reader - 27:16\\]
Word count. This field will reflect the 1-4096 words transferred"]
pub type WdcntR = crate :: FieldReader < u16 > ; # [doc = "Field `WDCNT` writer - 27:16\\]
Word count. This field will reflect the 1-4096 words transferred"]
pub type WdcntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `Reserved2` reader - 31:28\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:28\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bit 0 - 0:0\\]
Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words, the bit will clear to signal that it is ok to read/write the data registers. 0- Idle 1- Busy"]
# [inline (always)]
pub fn busy (& self) -> BusyR { BusyR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Word complete. This bit is set after each word transfer is completed. 0- Word transfer is not complete 1- Word transfer is complete This bit is reset when the SPI Status Register is read"]
# [inline (always)]
pub fn wc (& self) -> WcR { WcR :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - 2:2\\]
Frame complete. This bit is set after all of the requested words have been transmitted. 0- Transfer is not complete 1- Transfer is complete This bit is reset when the SPI Status Register is read"]
# [inline (always)]
pub fn fc (& self) -> FcR { FcR :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:15 - 15:3\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 3) & 0x1fff) as u16) } # [doc = "Bits 16:27 - 27:16\\]
Word count. This field will reflect the 1-4096 words transferred"]
# [inline (always)]
pub fn wdcnt (& self) -> WdcntR { WdcntR :: new (((self . bits >> 16) & 0x0fff) as u16) } # [doc = "Bits 28:31 - 31:28\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - 0:0\\]
Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words, the bit will clear to signal that it is ok to read/write the data registers. 0- Idle 1- Busy"]
# [inline (always)]
# [must_use]
pub fn busy (& mut self) -> BusyW < SpiStatusSpec > { BusyW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Word complete. This bit is set after each word transfer is completed. 0- Word transfer is not complete 1- Word transfer is complete This bit is reset when the SPI Status Register is read"]
# [inline (always)]
# [must_use]
pub fn wc (& mut self) -> WcW < SpiStatusSpec > { WcW :: new (self , 1) } # [doc = "Bit 2 - 2:2\\]
Frame complete. This bit is set after all of the requested words have been transmitted. 0- Transfer is not complete 1- Transfer is complete This bit is reset when the SPI Status Register is read"]
# [inline (always)]
# [must_use]
pub fn fc (& mut self) -> FcW < SpiStatusSpec > { FcW :: new (self , 2) } # [doc = "Bits 3:15 - 15:3\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiStatusSpec > { Reserved1W :: new (self , 3) } # [doc = "Bits 16:27 - 27:16\\]
Word count. This field will reflect the 1-4096 words transferred"]
# [inline (always)]
# [must_use]
pub fn wdcnt (& mut self) -> WdcntW < SpiStatusSpec > { WdcntW :: new (self , 16) } # [doc = "Bits 28:31 - 31:28\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiStatusSpec > { Reserved2W :: new (self , 28) } } # [doc = "SPI Status Register (SPISR)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiStatusSpec ; impl crate :: RegisterSpec for SpiStatusSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_status::R`](R) reader structure"]
impl crate :: Readable for SpiStatusSpec { } # [doc = "`write(|w| ..)` method takes [`spi_status::W`](W) writer structure"]
impl crate :: Writable for SpiStatusSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_STATUS to value 0"]
impl crate :: Resettable for SpiStatusSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_DATA (rw) register accessor: SPI Data Register (SPIDR)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_data`]
module"]
# [doc (alias = "SPI_DATA")]
pub type SpiData = crate :: Reg < spi_data :: SpiDataSpec > ; # [doc = "SPI Data Register (SPIDR)"]
pub mod spi_data { # [doc = "Register `SPI_DATA` reader"]
pub type R = crate :: R < SpiDataSpec > ; # [doc = "Register `SPI_DATA` writer"]
pub type W = crate :: W < SpiDataSpec > ; # [doc = "Field `DATA` reader - 31:0\\]
Data register for read and write operations"]
pub type DataR = crate :: FieldReader < u32 > ; # [doc = "Field `DATA` writer - 31:0\\]
Data register for read and write operations"]
pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
# [must_use]
pub fn data (& mut self) -> DataW < SpiDataSpec > { DataW :: new (self , 0) } } # [doc = "SPI Data Register (SPIDR)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiDataSpec ; impl crate :: RegisterSpec for SpiDataSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_data::R`](R) reader structure"]
impl crate :: Readable for SpiDataSpec { } # [doc = "`write(|w| ..)` method takes [`spi_data::W`](W) writer structure"]
impl crate :: Writable for SpiDataSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_DATA to value 0"]
impl crate :: Resettable for SpiDataSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_SETUP0 (rw) register accessor: Memory Mapped SPI Setup0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_setup0`]
module"]
# [doc (alias = "SPI_SETUP0")]
pub type SpiSetup0 = crate :: Reg < spi_setup0 :: SpiSetup0Spec > ; # [doc = "Memory Mapped SPI Setup0 Register"]
pub mod spi_setup0 { # [doc = "Register `SPI_SETUP0` reader"]
pub type R = crate :: R < SpiSetup0Spec > ; # [doc = "Register `SPI_SETUP0` writer"]
pub type W = crate :: W < SpiSetup0Spec > ; # [doc = "Field `RCMD` reader - 7:0\\]
Read Command"]
pub type RcmdR = crate :: FieldReader ; # [doc = "Field `RCMD` writer - 7:0\\]
Read Command"]
pub type RcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_A_BYTES` reader - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesR = crate :: FieldReader ; # [doc = "Field `NUM_A_BYTES` writer - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NUM_D_BYTES` reader - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesR = crate :: FieldReader ; # [doc = "Field `NUM_D_BYTES` writer - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `READ_TYPE` reader - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeR = crate :: FieldReader ; # [doc = "Field `READ_TYPE` writer - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 15:14\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:14\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WCMD` reader - 23:16\\]
Write Command"]
pub type WcmdR = crate :: FieldReader ; # [doc = "Field `WCMD` writer - 23:16\\]
Write Command"]
pub type WcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_D_BITS` reader - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsR = crate :: FieldReader ; # [doc = "Field `NUM_D_BITS` writer - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `Reserved2` reader - 31:29\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:29\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
pub fn rcmd (& self) -> RcmdR { RcmdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
pub fn num_a_bytes (& self) -> NumABytesR { NumABytesR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
pub fn num_d_bytes (& self) -> NumDBytesR { NumDBytesR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
pub fn read_type (& self) -> ReadTypeR { ReadTypeR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
pub fn wcmd (& self) -> WcmdR { WcmdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
pub fn num_d_bits (& self) -> NumDBitsR { NumDBitsR :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
# [must_use]
pub fn rcmd (& mut self) -> RcmdW < SpiSetup0Spec > { RcmdW :: new (self , 0) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
# [must_use]
pub fn num_a_bytes (& mut self) -> NumABytesW < SpiSetup0Spec > { NumABytesW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
# [must_use]
pub fn num_d_bytes (& mut self) -> NumDBytesW < SpiSetup0Spec > { NumDBytesW :: new (self , 10) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
# [must_use]
pub fn read_type (& mut self) -> ReadTypeW < SpiSetup0Spec > { ReadTypeW :: new (self , 12) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiSetup0Spec > { Reserved1W :: new (self , 14) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
# [must_use]
pub fn wcmd (& mut self) -> WcmdW < SpiSetup0Spec > { WcmdW :: new (self , 16) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
# [must_use]
pub fn num_d_bits (& mut self) -> NumDBitsW < SpiSetup0Spec > { NumDBitsW :: new (self , 24) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiSetup0Spec > { Reserved2W :: new (self , 29) } } # [doc = "Memory Mapped SPI Setup0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiSetup0Spec ; impl crate :: RegisterSpec for SpiSetup0Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_setup0::R`](R) reader structure"]
impl crate :: Readable for SpiSetup0Spec { } # [doc = "`write(|w| ..)` method takes [`spi_setup0::W`](W) writer structure"]
impl crate :: Writable for SpiSetup0Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_SETUP0 to value 0"]
impl crate :: Resettable for SpiSetup0Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_SETUP1 (rw) register accessor: Memory Mapped SPI Setup1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_setup1`]
module"]
# [doc (alias = "SPI_SETUP1")]
pub type SpiSetup1 = crate :: Reg < spi_setup1 :: SpiSetup1Spec > ; # [doc = "Memory Mapped SPI Setup1 Register"]
pub mod spi_setup1 { # [doc = "Register `SPI_SETUP1` reader"]
pub type R = crate :: R < SpiSetup1Spec > ; # [doc = "Register `SPI_SETUP1` writer"]
pub type W = crate :: W < SpiSetup1Spec > ; # [doc = "Field `RCMD` reader - 7:0\\]
Read Command"]
pub type RcmdR = crate :: FieldReader ; # [doc = "Field `RCMD` writer - 7:0\\]
Read Command"]
pub type RcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_A_BYTES` reader - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesR = crate :: FieldReader ; # [doc = "Field `NUM_A_BYTES` writer - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NUM_D_BYTES` reader - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesR = crate :: FieldReader ; # [doc = "Field `NUM_D_BYTES` writer - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `READ_TYPE` reader - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeR = crate :: FieldReader ; # [doc = "Field `READ_TYPE` writer - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 15:14\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:14\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WCMD` reader - 23:16\\]
Write Command"]
pub type WcmdR = crate :: FieldReader ; # [doc = "Field `WCMD` writer - 23:16\\]
Write Command"]
pub type WcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_D_BITS` reader - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsR = crate :: FieldReader ; # [doc = "Field `NUM_D_BITS` writer - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `Reserved2` reader - 31:29\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:29\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
pub fn rcmd (& self) -> RcmdR { RcmdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
pub fn num_a_bytes (& self) -> NumABytesR { NumABytesR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
pub fn num_d_bytes (& self) -> NumDBytesR { NumDBytesR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
pub fn read_type (& self) -> ReadTypeR { ReadTypeR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
pub fn wcmd (& self) -> WcmdR { WcmdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
pub fn num_d_bits (& self) -> NumDBitsR { NumDBitsR :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
# [must_use]
pub fn rcmd (& mut self) -> RcmdW < SpiSetup1Spec > { RcmdW :: new (self , 0) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
# [must_use]
pub fn num_a_bytes (& mut self) -> NumABytesW < SpiSetup1Spec > { NumABytesW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
# [must_use]
pub fn num_d_bytes (& mut self) -> NumDBytesW < SpiSetup1Spec > { NumDBytesW :: new (self , 10) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
# [must_use]
pub fn read_type (& mut self) -> ReadTypeW < SpiSetup1Spec > { ReadTypeW :: new (self , 12) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiSetup1Spec > { Reserved1W :: new (self , 14) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
# [must_use]
pub fn wcmd (& mut self) -> WcmdW < SpiSetup1Spec > { WcmdW :: new (self , 16) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
# [must_use]
pub fn num_d_bits (& mut self) -> NumDBitsW < SpiSetup1Spec > { NumDBitsW :: new (self , 24) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiSetup1Spec > { Reserved2W :: new (self , 29) } } # [doc = "Memory Mapped SPI Setup1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiSetup1Spec ; impl crate :: RegisterSpec for SpiSetup1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_setup1::R`](R) reader structure"]
impl crate :: Readable for SpiSetup1Spec { } # [doc = "`write(|w| ..)` method takes [`spi_setup1::W`](W) writer structure"]
impl crate :: Writable for SpiSetup1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_SETUP1 to value 0"]
impl crate :: Resettable for SpiSetup1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_SETUP2 (rw) register accessor: Memory Mapped SPI Setup2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_setup2`]
module"]
# [doc (alias = "SPI_SETUP2")]
pub type SpiSetup2 = crate :: Reg < spi_setup2 :: SpiSetup2Spec > ; # [doc = "Memory Mapped SPI Setup2 Register"]
pub mod spi_setup2 { # [doc = "Register `SPI_SETUP2` reader"]
pub type R = crate :: R < SpiSetup2Spec > ; # [doc = "Register `SPI_SETUP2` writer"]
pub type W = crate :: W < SpiSetup2Spec > ; # [doc = "Field `RCMD` reader - 7:0\\]
Read Command"]
pub type RcmdR = crate :: FieldReader ; # [doc = "Field `RCMD` writer - 7:0\\]
Read Command"]
pub type RcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_A_BYTES` reader - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesR = crate :: FieldReader ; # [doc = "Field `NUM_A_BYTES` writer - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NUM_D_BYTES` reader - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesR = crate :: FieldReader ; # [doc = "Field `NUM_D_BYTES` writer - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `READ_TYPE` reader - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeR = crate :: FieldReader ; # [doc = "Field `READ_TYPE` writer - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 15:14\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:14\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WCMD` reader - 23:16\\]
Write Command"]
pub type WcmdR = crate :: FieldReader ; # [doc = "Field `WCMD` writer - 23:16\\]
Write Command"]
pub type WcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_D_BITS` reader - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsR = crate :: FieldReader ; # [doc = "Field `NUM_D_BITS` writer - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `Reserved2` reader - 31:29\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:29\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
pub fn rcmd (& self) -> RcmdR { RcmdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
pub fn num_a_bytes (& self) -> NumABytesR { NumABytesR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
pub fn num_d_bytes (& self) -> NumDBytesR { NumDBytesR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
pub fn read_type (& self) -> ReadTypeR { ReadTypeR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
pub fn wcmd (& self) -> WcmdR { WcmdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
pub fn num_d_bits (& self) -> NumDBitsR { NumDBitsR :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
# [must_use]
pub fn rcmd (& mut self) -> RcmdW < SpiSetup2Spec > { RcmdW :: new (self , 0) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
# [must_use]
pub fn num_a_bytes (& mut self) -> NumABytesW < SpiSetup2Spec > { NumABytesW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
# [must_use]
pub fn num_d_bytes (& mut self) -> NumDBytesW < SpiSetup2Spec > { NumDBytesW :: new (self , 10) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
# [must_use]
pub fn read_type (& mut self) -> ReadTypeW < SpiSetup2Spec > { ReadTypeW :: new (self , 12) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiSetup2Spec > { Reserved1W :: new (self , 14) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
# [must_use]
pub fn wcmd (& mut self) -> WcmdW < SpiSetup2Spec > { WcmdW :: new (self , 16) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
# [must_use]
pub fn num_d_bits (& mut self) -> NumDBitsW < SpiSetup2Spec > { NumDBitsW :: new (self , 24) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiSetup2Spec > { Reserved2W :: new (self , 29) } } # [doc = "Memory Mapped SPI Setup2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiSetup2Spec ; impl crate :: RegisterSpec for SpiSetup2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_setup2::R`](R) reader structure"]
impl crate :: Readable for SpiSetup2Spec { } # [doc = "`write(|w| ..)` method takes [`spi_setup2::W`](W) writer structure"]
impl crate :: Writable for SpiSetup2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_SETUP2 to value 0"]
impl crate :: Resettable for SpiSetup2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_SETUP3 (rw) register accessor: Memory Mapped SPI Setup3 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_setup3`]
module"]
# [doc (alias = "SPI_SETUP3")]
pub type SpiSetup3 = crate :: Reg < spi_setup3 :: SpiSetup3Spec > ; # [doc = "Memory Mapped SPI Setup3 Register"]
pub mod spi_setup3 { # [doc = "Register `SPI_SETUP3` reader"]
pub type R = crate :: R < SpiSetup3Spec > ; # [doc = "Register `SPI_SETUP3` writer"]
pub type W = crate :: W < SpiSetup3Spec > ; # [doc = "Field `RCMD` reader - 7:0\\]
Read Command"]
pub type RcmdR = crate :: FieldReader ; # [doc = "Field `RCMD` writer - 7:0\\]
Read Command"]
pub type RcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_A_BYTES` reader - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesR = crate :: FieldReader ; # [doc = "Field `NUM_A_BYTES` writer - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
pub type NumABytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `NUM_D_BYTES` reader - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesR = crate :: FieldReader ; # [doc = "Field `NUM_D_BYTES` writer - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
pub type NumDBytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `READ_TYPE` reader - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeR = crate :: FieldReader ; # [doc = "Field `READ_TYPE` writer - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
pub type ReadTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `Reserved1` reader - 15:14\\]
Always read as 0"]
pub type Reserved1R = crate :: FieldReader ; # [doc = "Field `Reserved1` writer - 15:14\\]
Always read as 0"]
pub type Reserved1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `WCMD` reader - 23:16\\]
Write Command"]
pub type WcmdR = crate :: FieldReader ; # [doc = "Field `WCMD` writer - 23:16\\]
Write Command"]
pub type WcmdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `NUM_D_BITS` reader - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsR = crate :: FieldReader ; # [doc = "Field `NUM_D_BITS` writer - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
pub type NumDBitsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `Reserved2` reader - 31:29\\]
Always read as 0"]
pub type Reserved2R = crate :: FieldReader ; # [doc = "Field `Reserved2` writer - 31:29\\]
Always read as 0"]
pub type Reserved2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
pub fn rcmd (& self) -> RcmdR { RcmdR :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
pub fn num_a_bytes (& self) -> NumABytesR { NumABytesR :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
pub fn num_d_bytes (& self) -> NumDBytesR { NumDBytesR :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
pub fn read_type (& self) -> ReadTypeR { ReadTypeR :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
pub fn reserved1 (& self) -> Reserved1R { Reserved1R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
pub fn wcmd (& self) -> WcmdR { WcmdR :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
pub fn num_d_bits (& self) -> NumDBitsR { NumDBitsR :: new (((self . bits >> 24) & 0x1f) as u8) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
pub fn reserved2 (& self) -> Reserved2R { Reserved2R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:7 - 7:0\\]
Read Command"]
# [inline (always)]
# [must_use]
pub fn rcmd (& mut self) -> RcmdW < SpiSetup3Spec > { RcmdW :: new (self , 0) } # [doc = "Bits 8:9 - 9:8\\]
Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes"]
# [inline (always)]
# [must_use]
pub fn num_a_bytes (& mut self) -> NumABytesW < SpiSetup3Spec > { NumABytesW :: new (self , 8) } # [doc = "Bits 10:11 - 11:10\\]
Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits"]
# [inline (always)]
# [must_use]
pub fn num_d_bytes (& mut self) -> NumDBytesW < SpiSetup3Spec > { NumDBytesW :: new (self , 10) } # [doc = "Bits 12:13 - 13:12\\]
Determines if the read command is a single, dual or quad read mode command 00 ΓÇô Normal read (all data input on spi_din) 01 ΓÇô Dual read (odd bytes input on spi_din; even on spi_dout) 10 ΓÇô Normal read (all data input on spi_din) 11 ΓÇô Quad read (uses spi_qdin0/1)"]
# [inline (always)]
# [must_use]
pub fn read_type (& mut self) -> ReadTypeW < SpiSetup3Spec > { ReadTypeW :: new (self , 12) } # [doc = "Bits 14:15 - 15:14\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved1 (& mut self) -> Reserved1W < SpiSetup3Spec > { Reserved1W :: new (self , 14) } # [doc = "Bits 16:23 - 23:16\\]
Write Command"]
# [inline (always)]
# [must_use]
pub fn wcmd (& mut self) -> WcmdW < SpiSetup3Spec > { WcmdW :: new (self , 16) } # [doc = "Bits 24:28 - 28:24\\]
Number of dummy bits to use if NUM_D_BYTES = 0"]
# [inline (always)]
# [must_use]
pub fn num_d_bits (& mut self) -> NumDBitsW < SpiSetup3Spec > { NumDBitsW :: new (self , 24) } # [doc = "Bits 29:31 - 31:29\\]
Always read as 0"]
# [inline (always)]
# [must_use]
pub fn reserved2 (& mut self) -> Reserved2W < SpiSetup3Spec > { Reserved2W :: new (self , 29) } } # [doc = "Memory Mapped SPI Setup3 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_setup3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_setup3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiSetup3Spec ; impl crate :: RegisterSpec for SpiSetup3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_setup3::R`](R) reader structure"]
impl crate :: Readable for SpiSetup3Spec { } # [doc = "`write(|w| ..)` method takes [`spi_setup3::W`](W) writer structure"]
impl crate :: Writable for SpiSetup3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_SETUP3 to value 0"]
impl crate :: Resettable for SpiSetup3Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_SWITCH (rw) register accessor: Memory Mapped SPI Switch Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_switch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_switch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_switch`]
module"]
# [doc (alias = "SPI_SWITCH")]
pub type SpiSwitch = crate :: Reg < spi_switch :: SpiSwitchSpec > ; # [doc = "Memory Mapped SPI Switch Register"]
pub mod spi_switch { # [doc = "Register `SPI_SWITCH` reader"]
pub type R = crate :: R < SpiSwitchSpec > ; # [doc = "Register `SPI_SWITCH` writer"]
pub type W = crate :: W < SpiSwitchSpec > ; # [doc = "Field `MMPT_S` reader - 0:0\\]
MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1, Memory Mapped Protocol Translator is selected to control config port of core SPI module."]
pub type MmptSR = crate :: BitReader ; # [doc = "Field `MMPT_S` writer - 0:0\\]
MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1, Memory Mapped Protocol Translator is selected to control config port of core SPI module."]
pub type MmptSW < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MM_INT_EN` reader - 1:1\\]
Memory Mapped mode interrupt enable. 0 ΓÇô Interrupts are disabled during memory mapped operations 1 ΓÇô Word Count interrupt is enabled for memory mapped operations"]
pub type MmIntEnR = crate :: BitReader ; # [doc = "Field `MM_INT_EN` writer - 1:1\\]
Memory Mapped mode interrupt enable. 0 ΓÇô Interrupts are disabled during memory mapped operations 1 ΓÇô Word Count interrupt is enabled for memory mapped operations"]
pub type MmIntEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - 0:0\\]
MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1, Memory Mapped Protocol Translator is selected to control config port of core SPI module."]
# [inline (always)]
pub fn mmpt_s (& self) -> MmptSR { MmptSR :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - 1:1\\]
Memory Mapped mode interrupt enable. 0 ΓÇô Interrupts are disabled during memory mapped operations 1 ΓÇô Word Count interrupt is enabled for memory mapped operations"]
# [inline (always)]
pub fn mm_int_en (& self) -> MmIntEnR { MmIntEnR :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - 0:0\\]
MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1, Memory Mapped Protocol Translator is selected to control config port of core SPI module."]
# [inline (always)]
# [must_use]
pub fn mmpt_s (& mut self) -> MmptSW < SpiSwitchSpec > { MmptSW :: new (self , 0) } # [doc = "Bit 1 - 1:1\\]
Memory Mapped mode interrupt enable. 0 ΓÇô Interrupts are disabled during memory mapped operations 1 ΓÇô Word Count interrupt is enabled for memory mapped operations"]
# [inline (always)]
# [must_use]
pub fn mm_int_en (& mut self) -> MmIntEnW < SpiSwitchSpec > { MmIntEnW :: new (self , 1) } } # [doc = "Memory Mapped SPI Switch Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_switch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_switch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiSwitchSpec ; impl crate :: RegisterSpec for SpiSwitchSpec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_switch::R`](R) reader structure"]
impl crate :: Readable for SpiSwitchSpec { } # [doc = "`write(|w| ..)` method takes [`spi_switch::W`](W) writer structure"]
impl crate :: Writable for SpiSwitchSpec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_SWITCH to value 0"]
impl crate :: Resettable for SpiSwitchSpec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_DATA1 (rw) register accessor: SPI Data Register (SPIDR1)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_data1`]
module"]
# [doc (alias = "SPI_DATA1")]
pub type SpiData1 = crate :: Reg < spi_data1 :: SpiData1Spec > ; # [doc = "SPI Data Register (SPIDR1)"]
pub mod spi_data1 { # [doc = "Register `SPI_DATA1` reader"]
pub type R = crate :: R < SpiData1Spec > ; # [doc = "Register `SPI_DATA1` writer"]
pub type W = crate :: W < SpiData1Spec > ; # [doc = "Field `DATA` reader - 31:0\\]
Data register for read and write operations"]
pub type DataR = crate :: FieldReader < u32 > ; # [doc = "Field `DATA` writer - 31:0\\]
Data register for read and write operations"]
pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
# [must_use]
pub fn data (& mut self) -> DataW < SpiData1Spec > { DataW :: new (self , 0) } } # [doc = "SPI Data Register (SPIDR1)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiData1Spec ; impl crate :: RegisterSpec for SpiData1Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_data1::R`](R) reader structure"]
impl crate :: Readable for SpiData1Spec { } # [doc = "`write(|w| ..)` method takes [`spi_data1::W`](W) writer structure"]
impl crate :: Writable for SpiData1Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_DATA1 to value 0"]
impl crate :: Resettable for SpiData1Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_DATA2 (rw) register accessor: SPI Data Register (SPIDR2)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_data2`]
module"]
# [doc (alias = "SPI_DATA2")]
pub type SpiData2 = crate :: Reg < spi_data2 :: SpiData2Spec > ; # [doc = "SPI Data Register (SPIDR2)"]
pub mod spi_data2 { # [doc = "Register `SPI_DATA2` reader"]
pub type R = crate :: R < SpiData2Spec > ; # [doc = "Register `SPI_DATA2` writer"]
pub type W = crate :: W < SpiData2Spec > ; # [doc = "Field `DATA` reader - 31:0\\]
Data register for read and write operations"]
pub type DataR = crate :: FieldReader < u32 > ; # [doc = "Field `DATA` writer - 31:0\\]
Data register for read and write operations"]
pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
# [must_use]
pub fn data (& mut self) -> DataW < SpiData2Spec > { DataW :: new (self , 0) } } # [doc = "SPI Data Register (SPIDR2)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiData2Spec ; impl crate :: RegisterSpec for SpiData2Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_data2::R`](R) reader structure"]
impl crate :: Readable for SpiData2Spec { } # [doc = "`write(|w| ..)` method takes [`spi_data2::W`](W) writer structure"]
impl crate :: Writable for SpiData2Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_DATA2 to value 0"]
impl crate :: Resettable for SpiData2Spec { const RESET_VALUE : u32 = 0 ; } } # [doc = "SPI_DATA3 (rw) register accessor: SPI Data Register (SPIDR3)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_data3`]
module"]
# [doc (alias = "SPI_DATA3")]
pub type SpiData3 = crate :: Reg < spi_data3 :: SpiData3Spec > ; # [doc = "SPI Data Register (SPIDR3)"]
pub mod spi_data3 { # [doc = "Register `SPI_DATA3` reader"]
pub type R = crate :: R < SpiData3Spec > ; # [doc = "Register `SPI_DATA3` writer"]
pub type W = crate :: W < SpiData3Spec > ; # [doc = "Field `DATA` reader - 31:0\\]
Data register for read and write operations"]
pub type DataR = crate :: FieldReader < u32 > ; # [doc = "Field `DATA` writer - 31:0\\]
Data register for read and write operations"]
pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - 31:0\\]
Data register for read and write operations"]
# [inline (always)]
# [must_use]
pub fn data (& mut self) -> DataW < SpiData3Spec > { DataW :: new (self , 0) } } # [doc = "SPI Data Register (SPIDR3)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_data3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_data3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiData3Spec ; impl crate :: RegisterSpec for SpiData3Spec { type Ux = u32 ; } # [doc = "`read()` method returns [`spi_data3::R`](R) reader structure"]
impl crate :: Readable for SpiData3Spec { } # [doc = "`write(|w| ..)` method takes [`spi_data3::W`](W) writer structure"]
impl crate :: Writable for SpiData3Spec { type Safety = crate :: Unsafe ; const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SPI_DATA3 to value 0"]
impl crate :: Resettable for SpiData3Spec { const RESET_VALUE : u32 = 0 ; } } } # [no_mangle]
static mut DEVICE_PERIPHERALS : bool = false ; # [doc = r" All the peripherals."]
# [allow (non_snake_case)]
pub struct Peripherals { # [doc = "GPADC_CTRL"]
pub gpadc_ctrl : GpadcCtrl , # [doc = "APP_LIN"]
pub app_lin : AppLin , # [doc = "APP_UART_0"]
pub app_uart_0 : AppUart0 , # [doc = "APP_SPI_0"]
pub app_spi_0 : AppSpi0 , # [doc = "APP_CANCFG"]
pub app_cancfg : AppCancfg , # [doc = "APP_CANECC"]
pub app_canecc : AppCanecc , # [doc = "TPTC_A0"]
pub tptc_a0 : TptcA0 , # [doc = "TPTC_A1"]
pub tptc_a1 : TptcA1 , # [doc = "APP_CRC"]
pub app_crc : AppCrc , # [doc = "HWA_CFG"]
pub hwa_cfg : HwaCfg , # [doc = "TPTC_B0"]
pub tptc_b0 : TptcB0 , # [doc = "TPTC_B0_1"]
pub tptc_b0_1 : TptcB0_1 , # [doc = "TPCC_B"]
pub tpcc_b : TpccB , # [doc = "TPCC_A"]
pub tpcc_a : TpccA , # [doc = "APP_RCM"]
pub app_rcm : AppRcm , # [doc = "APP_CTRL"]
pub app_ctrl : AppCtrl , # [doc = "APP_HWA_ADCBUF_CTRL"]
pub app_hwa_adcbuf_ctrl : AppHwaAdcbufCtrl , # [doc = "APP_ECC_AGG"]
pub app_ecc_agg : AppEccAgg , # [doc = "APP_RTI"]
pub app_rti : AppRti , # [doc = "APP_WD"]
pub app_wd : AppWd , # [doc = "APP_DCC"]
pub app_dcc : AppDcc , # [doc = "APP_ESM"]
pub app_esm : AppEsm , # [doc = "APP_UART_1"]
pub app_uart_1 : AppUart1 , # [doc = "APP_SPI_1"]
pub app_spi_1 : AppSpi1 , # [doc = "APP_I2C"]
pub app_i2c : AppI2c , # [doc = "APP_PWM"]
pub app_pwm : AppPwm , # [doc = "TOP_IO_MUX"]
pub top_io_mux : TopIoMux , # [doc = "APP_PRCM"]
pub app_prcm : AppPrcm , # [doc = "TOP_GIO"]
pub top_gio : TopGio , # [doc = "TOPSS_CTRL"]
pub topss_ctrl : TopssCtrl , # [doc = "PLLDIG_CTRL"]
pub plldig_ctrl : PlldigCtrl , # [doc = "PBIST"]
pub pbist : Pbist , # [doc = "TOP_DEBUGSS"]
pub top_debugss : TopDebugss , # [doc = "APP_CFG_QSPI"]
pub app_cfg_qspi : AppCfgQspi , } impl Peripherals { # [doc = r" Returns all the peripherals *once*."]
# [cfg (feature = "critical-section")]
# [inline]
pub fn take () -> Option < Self > { critical_section :: with (| _ | { if unsafe { DEVICE_PERIPHERALS } { return None } Some (unsafe { Peripherals :: steal () }) }) } # [doc = r" Unchecked version of `Peripherals::take`."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Each of the returned peripherals must be used at most once."]
# [inline]
pub unsafe fn steal () -> Self { DEVICE_PERIPHERALS = true ; Peripherals { gpadc_ctrl : GpadcCtrl :: steal () , app_lin : AppLin :: steal () , app_uart_0 : AppUart0 :: steal () , app_spi_0 : AppSpi0 :: steal () , app_cancfg : AppCancfg :: steal () , app_canecc : AppCanecc :: steal () , tptc_a0 : TptcA0 :: steal () , tptc_a1 : TptcA1 :: steal () , app_crc : AppCrc :: steal () , hwa_cfg : HwaCfg :: steal () , tptc_b0 : TptcB0 :: steal () , tptc_b0_1 : TptcB0_1 :: steal () , tpcc_b : TpccB :: steal () , tpcc_a : TpccA :: steal () , app_rcm : AppRcm :: steal () , app_ctrl : AppCtrl :: steal () , app_hwa_adcbuf_ctrl : AppHwaAdcbufCtrl :: steal () , app_ecc_agg : AppEccAgg :: steal () , app_rti : AppRti :: steal () , app_wd : AppWd :: steal () , app_dcc : AppDcc :: steal () , app_esm : AppEsm :: steal () , app_uart_1 : AppUart1 :: steal () , app_spi_1 : AppSpi1 :: steal () , app_i2c : AppI2c :: steal () , app_pwm : AppPwm :: steal () , top_io_mux : TopIoMux :: steal () , app_prcm : AppPrcm :: steal () , top_gio : TopGio :: steal () , topss_ctrl : TopssCtrl :: steal () , plldig_ctrl : PlldigCtrl :: steal () , pbist : Pbist :: steal () , top_debugss : TopDebugss :: steal () , app_cfg_qspi : AppCfgQspi :: steal () , } } }